Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

International Nuclear Information System (INIS)

Lee, Youngmin; Lee, Sejoon; Im, Hyunsik; Hiramoto, Toshiro

2015-01-01

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

Energy Technology Data Exchange (ETDEWEB)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik [Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715 (Korea, Republic of); Hiramoto, Toshiro [Institute of Industrial Science, University of Tokyo, Tokyo 153-8505 (Japan)

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

Energy Technology Data Exchange (ETDEWEB)

Liu, J. W., E-mail: liu.jiangwei@nims.go.jp [International Center for Young Scientists (ICYS), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Liao, M. Y.; Imura, M. [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Watanabe, E.; Oosato, H. [Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Koide, Y., E-mail: koide.yasuo@nims.go.jp [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Center of Materials Research for Low Carbon Emission, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-08-25

A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be −40.7 mA·mm{sup −1}, 13.2 ± 0.1 mS·mm{sup −1}, and −3.1 ± 0.1 V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to −10.0 V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

Study and simulation of the time behaviour of MOS transistor devices. Application to a logic assembly

International Nuclear Information System (INIS)

Barocas, Marcel

1974-01-01

The objective of this research thesis is to determine, by simulation, the time response of devices based on MOS transistors. After a theoretical study of the MOS element, the author develops a transistor model based on its physical components. This model is firstly used to obtain the transistor static characteristics. The author then studies the time response of the inverter logic circuit which is the basic operator of these circuits. Theoretical results are verified by simulation and by experiments. The author then reports a detailed study of the inverter input impedance, and the decoupling property between logic operators in cascade. The simulation confirms the obtained results. Based on this decoupling property, the output time response of a logic chain is studied by using a simulation software. A general method of determination of the output time response is developed with application to a logic assembly [fr

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Integrated circuits and logic operations based on single-layer MoS2.

Science.gov (United States)

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

A single nano cantilever as a reprogrammable universal logic gate

International Nuclear Information System (INIS)

Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J

2017-01-01

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)

A single nano cantilever as a reprogrammable universal logic gate

KAUST Repository

Chappanda, K. N.

2017-02-24

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

Transistor data book

International Nuclear Information System (INIS)

1988-03-01

It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

Non-classical logic inverter coupling a ZnO nanowire-based Schottky barrier transistor and adjacent Schottky diode.

Science.gov (United States)

Hosseini Shokouh, Seyed Hossein; Raza, Syed Raza Ali; Lee, Hee Sung; Im, Seongil

2014-08-21

On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

Science.gov (United States)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing

Power transistor module for high current applications

International Nuclear Information System (INIS)

Cilyo, F.F.

1975-01-01

One of the parts needed for the control system of the 400-GeV accelerator at Fermilab was a power transistor with a safe operating area of 1800A at 50V, dc current gain of 100,000 and 20 kHz bandwidth. Since the commercially available discrete devices and power hybrid packages did not meet these requirements, a power transistor module was developed which performed satisfactorily. By connecting 13 power transistors in parallel, with due consideration for network and heat dissipation problems, and by driving these 13 with another power transistor, a super power transistor is made, having an equivalent current, power, and safe operating area capability of 13 transistors. For higher capabilities, additional modules can be conveniently added. (auth)

Design Techniques for Power-Aware Combinational Logic SER Mitigation

Science.gov (United States)

Mahatme, Nihaar N.

SEUs. This was mainly because the operating frequencies were much lower for older technology generations. The Intel Pentium II for example was fabricated using 0.35 microm technology and operated between 200-330 MHz. With technology scaling however, operating frequencies have increased tremendously and the contribution of soft errors due to latched SETs from combinational logic could account for a significant proportion of the chip-level soft error rate [Sief-12][Maha-11][Shiv02] [Bu97]. Therefore there is a need to systematically characterize the problem of combinational logic single-event effects (SEE) and understand the various factors that affect the combinational logic single-event error rate. Just as scaling has led to soft errors emerging as a reliability-limiting failure mode for modern digital ICs, the problem of increasing power consumption has arguably been a bigger bane of scaling. While Moore's Law loftily states the blessing of technology scaling to be smaller and faster transistor it fails to highlight that the power density increases exponentially with every technology generation. The power density problem was partially solved in the 1970's and 1980's by moving from bipolar and GaAs technologies to full-scale silicon CMOS technologies. Following this however, technology miniaturization that enabled high-speed, multicore and parallel computing has steadily increased the power density and the power consumption problem. Today minimizing the power consumption is as much critical for power hungry server farms as it for portable devices, all pervasive sensor networks and future eco-bio-sensors. Low-power consumption is now regularly part of design philosophies for various digital products with diverse applications from computing to communication to healthcare. Thus designers in today's world are left grappling with both a "power wall" as well as a "reliability wall". Unfortunately, when it comes to improving reliability through soft error mitigation, most

Tunable Tribotronic Dual-Gate Logic Devices Based on 2D MoS2 and Black Phosphorus.

Science.gov (United States)

Gao, Guoyun; Wan, Bensong; Liu, Xingqiang; Sun, Qijun; Yang, Xiaonian; Wang, Longfei; Pan, Caofeng; Wang, Zhong Lin

2018-03-01

With the Moore's law hitting the bottleneck of scaling-down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self-powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual-gate logic device based on a MoS 2 field-effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm -1 . Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low-power-consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human-machine interfacing, data processing and transmission. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Single InAs/GaSb nanowire low-power CMOS inverter.

Science.gov (United States)

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

FY1995 study of low power LSI design automation software with parallel processing; 1995 nendo heiretsu shori wo katsuyoshita shodenryoku LSI muke sekkei jidoka software no kenkyu kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The needs for low power LSIs have rapidly increased recently. For the low power LSI development, not only new circuit technologies but also new design automation tools supporting the new technologies are indispensable. The purpose of this project is to develop a new design automation software, which is able to design new digital LSIs with much lower power than that of conventional CMOS LSIs. A new design automation software for very low power LSIs has been developed targeting the pass-transistor logic SPL, a dedicated low power circuit technology. The software includes a logic synthesis function for pass-transistor-based macrocells and a macrocell placement function. Several new algorithms have been developed for the software, e.g. BDD construction. Some of them are designed and implemented for parallel processing in order to reduce the processing time. The logic synthesis function was tested on a set of benchmarks and finally applied to a low power CPU design. The designed 8-bit CPU was fully compatible with Zilog Z-80. The power dissipation of the CPU was compared with that of commercial CMOS Z-80. At most 82% of power of CMOS was reduced by the new CPU. On the other hand, parallel processing speed up was measured on the macrocell placement function. 34 folds speed up was realized. (NEDO)

Low Power Consumption Complementary Inverters with n-MoS2 and p-WSe2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits.

Science.gov (United States)

Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil

2015-10-14

Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Directory of Open Access Journals (Sweden)

Shipra Upadhyay

2013-01-01

Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

Ternary logic implemented on a single dopant atom field effect silicon transistor

NARCIS (Netherlands)

Klein, M.; Mol, J.A.; Verduijn, J.; Lansbergen, G.P.; Rogge, S.; Levine, R.D.; Remacle, F.

2010-01-01

We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through

Adiabatic logic future trend and system level perspective

CERN Document Server

Teichmann, Philip

2012-01-01

Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the p...

Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

Science.gov (United States)

Yu, Woo Jong; Li, Zheng; Zhou, Hailong; Chen, Yu; Wang, Yang; Huang, Yu; Duan, Xiangfeng

2014-01-01

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration. PMID:23241535

A nanoscale piezoelectric transformer for low-voltage transistors.

Science.gov (United States)

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Low swing differential logic for mixed signal applications

International Nuclear Information System (INIS)

Fischer, P.; Kraft, E.

2004-01-01

Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power

Identification of initiating events using a master logic diagram in low-power and shutdown PSA for nuclear power plant

International Nuclear Information System (INIS)

Han, S. J.; Park, J. H.; Kim, T. W.; Ha, J. J.

2003-01-01

It is necessary to apply a formal technique instead of an empirical technique in the identification of initiating events for Low Power and ShutDown (LPSD) Probabilistic Safety Assessment (PSA) of Nuclear Power Plant (NPP). The present study focuses on the examination of Master Logic Diagram (MLD) technique as a formal technique in the identification of initiating events. The MLD technique is a deductive tool using top-down approach for the formal and logical indentification of initiating events. The present study modified the MLD used in the full power PSA considering the characteristics of LPSD operation. The modified MLD introduced a systematic formation in decomposition process of which the MLD for full power PSA lacked. The modified MLD was able to identify initiating events systematic and logical. However, the formal techniques including the MLD have a limitation for precisely identifying all of the initiating events. In order to overcome this limitation, it is necessary to combine it with an empirical technique. We expect that the modified MLD can be used in an upgrade of the current LPSD PSAs

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

Directory of Open Access Journals (Sweden)

Myunghwan Ryu

2016-01-01

Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

Designing and simulation smart multifunctional continuous logic device as a basic cell of advanced high-performance sensor systems with MIMO-structure

Science.gov (United States)

Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

2015-01-01

We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It's have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V.

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

Science.gov (United States)

Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Das, Saptarshi; Roelofs, Andreas [Center for Nanoscale Material, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Dubey, Madan [U.S. Army Research Laboratory, Adelphi, Maryland 20783 (United States)

2014-08-25

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.

Nanomagnetic Logic

Science.gov (United States)

Carlton, David Bryan

The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

OpenAIRE

Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

2011-01-01

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

Vertical organic transistors

International Nuclear Information System (INIS)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-01-01

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

Vertical organic transistors.

Science.gov (United States)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Light-effect transistor (LET with multiple independent gating controls for optical logic gates and optical amplification

Directory of Open Access Journals (Sweden)

Jason eMarmon

2016-03-01

Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Universal power transistor base drive control unit

Science.gov (United States)

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

Science.gov (United States)

Moon, Kyeong-Ju; Lee, Tae-Il; Lee, Sang-Hoon; Han, Young-Uk; Ham, Moon-Ho; Myoung, Jae-Min

2012-07-25

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

Science.gov (United States)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Efficient simulation of power MOS transistors

NARCIS (Netherlands)

Ugryumova, M.; Schilders, W.H.A.

2011-01-01

In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

Science.gov (United States)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Science.gov (United States)

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

International Nuclear Information System (INIS)

Kanungo, Jitendra; Dasgupta, S.

2014-01-01

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator (PCG). The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder (RCA) and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic. (semiconductor integrated circuits)

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

Science.gov (United States)

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

Science.gov (United States)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

High reliability EPI-base radiation hardened power transistor

International Nuclear Information System (INIS)

Clark, L.E.; Saltich, J.L.

1978-01-01

A high-voltage power transistor is described which is able to withstand fluences as high as 3 x 10 14 neutrons per square centimeter and still be able to operate satisfactorily. The collector may be made essentially half as thick and twice as heavily doped as normally and its base is made in two regions which together are essentially four times as thick as the normal power transistor base region. The base region has a heavily doped upper region and a lower region intermediate the upper heavily doped region and the collector. The doping in the intermediate region is as close to intrinsic as possible, in any event less than about 3 x 10 15 impurities per cubic centimeter. The second base region has small width in comparison to the first base region, the ratio of the first to the second being at least about 5 to 1. The base region having the upper heavily doped region and the intermediate or lower low doped region contributes to the higher breakdown voltage which the transistor is able to withstand. The high doping of the collector region essentially lowers that portion of the breakdown voltage achieved by the collector region. Accordingly, it is necessary to transfer certain of this breakdown capability to the base region and this is achieved by using the upper region of heavily doped and an intermediate or lower region of low doping

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

International Nuclear Information System (INIS)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir

2013-11-26

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

Science.gov (United States)

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

A low-power CMOS frequency synthesizer for GPS receivers

International Nuclear Information System (INIS)

Yu Yunfeng; Xiao Shimao; Zhuang Haixiao; Ma Chengyan; Ye Tianchun; Yue Jianlian

2010-01-01

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 . (semiconductor integrated circuits)

Low-background transistors for application in nuclear electronics

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

Investigations of silicon transistors were carried out to determine transistors with low value of base distributed resistance (R). Measurement results for R and current amplification coefficient β are presented for bipolar transistor several types. Correlations between R and β were studied. KT 399A, 2T640A and KT3117B transistors are found to be most adequate ones as a base for low-background amplifier development

Lateral power transistors in integrated circuits

CERN Document Server

Erlbacher, Tobias

2014-01-01

This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

Improving the positive feedback adiabatic logic familiy

Directory of Open Access Journals (Sweden)

J. Fischer

2004-01-01

Full Text Available Positive Feedback Adiabatic Logic (PFAL shows the lowest energy dissipation among adiabatic logic families based on cross-coupled transistors, due to the reduction of both adiabatic and non-adiabatic losses. The dissipation primarily depends on the resistance of the charging path, which consists of a single p-channel MOSFET during the recovery phase. In this paper, a new logic family called Improved PFAL (IPFAL is proposed, where all n- and pchannel devices are swapped so that the charge can be recovered through an n-channel MOSFET. This allows to decrease the resistance of the charging path up to a factor of 2, and it enables a significant reduction of the energy dissipation. Simulations based on a 0.13µm CMOS process confirm the improvements in terms of power consumption over a large frequency range. However, the same simple design rule, which enables in PFAL an additional reduction of the dissipation by optimal transistor sizing, does not apply to IPFAL. Therefore, the influence of several sources of dissipation for a generic IPFAL gate is illustrated and discussed, in order to lower the power consumption and achieve better performance.

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Fuzzy logic control of nuclear power plant

International Nuclear Information System (INIS)

Yao Liangzhong; Guo Renjun; Ma Changwen

1996-01-01

The main advantage of the fuzzy logic control is that the method does not require a detailed mathematical model of the object to be controlled. In this paper, the shortcomings and limitations of the model-based method in nuclear power plant control were presented, the theory of the fuzzy logic control was briefly introduced, and the applications of the fuzzy logic control technology in nuclear power plant controls were surveyed. Finally, the problems to be solved by using the fuzzy logic control in nuclear power plants were discussed

One electron-based smallest flexible logic cell

Science.gov (United States)

Kim, S. J.; Lee, J. J.; Kang, H. J.; Choi, J. B.; Yu, Y.-S.; Takahashi, Y.; Hasko, D. G.

2012-10-01

A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.

GaN transistors for efficient power conversion

CERN Document Server

Lidow, Alex; de Rooij, Michael; Reusch, David

2014-01-01

The first edition of GaN Transistors for Efficient Power Conversion was self-published by EPC in 2012, and is currently the only other book to discuss GaN transistor technology and specific applications for the technology. More than 1,200 copies of the first edition have been sold through Amazon or distributed to selected university professors, students and potential customers, and a simplified Chinese translation is also available. The second edition has expanded emphasis on applications for GaN transistors and design considerations. This textbook provides technical and application-focused i

Microelectromechanical reprogrammable logic device

Science.gov (United States)

Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

2016-01-01

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

Microelectromechanical reprogrammable logic device

KAUST Repository

Hafiz, Md Abdullah Al

2016-03-29

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

International Nuclear Information System (INIS)

Yang Ling; Zhou Xiao-Wei; Ma Xiao-Hua; Lv Ling; Zhang Jin-Cheng; Hao Yue; Cao Yan-Rong

2017-01-01

The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor (HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties. (paper)

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Science.gov (United States)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

Science.gov (United States)

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Logic verification system for power plant sequence diagrams

International Nuclear Information System (INIS)

Fukuda, Mitsuko; Yamada, Naoyuki; Teshima, Toshiaki; Kan, Ken-ichi; Utsunomiya, Mitsugu.

1994-01-01

A logic verification system for sequence diagrams of power plants has been developed. The system's main function is to verify correctness of the logic realized by sequence diagrams for power plant control systems. The verification is based on a symbolic comparison of the logic of the sequence diagrams with the logic of the corresponding IBDs (interlock Block Diagrams) in combination with reference to design knowledge. The developed system points out the sub-circuit which is responsible for any existing mismatches between the IBD logic and the logic realized by the sequence diagrams. Applications to the verification of actual sequence diagrams of power plants confirmed that the developed system is practical and effective. (author)

Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

Science.gov (United States)

Tsai, Jung-Hui

2014-01-01

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (-27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

On-line tuning of a fuzzy-logic power system stabilizer

International Nuclear Information System (INIS)

Hossein-Zadeh, N.; Kalam, A.

2002-01-01

A scheme for on-line tuning of a fuzzy-logic power system stabilizer is presented. firstly, a fuzzy-logic power system stabilizer is developed using speed deviation and accelerating power as the controller input variables. The inference mechanism of fuzzy-logic controller is represented by a decision table, constructed of linguistic IF-THEN rules. The Linguistic rules are available from experts and the design procedure is based on these rules. It assumed that an exact model of the plant is not available and it is difficult to extract the exact parameters of the power plant. Thus, the design procedure can not be based on an exact model. This is an advantage of fuzzy logic that makes the design of a controller possible without knowing the exact model of the plant. Secondly, two scaling parameters are introduced to tune the fuzzy-logic power system stabilizer. These scaling parameters are the outputs of another fuzzy-logic system, which gets the operating conditions of power system as inputs. These mechanism of tuning the fuzzy-logic power system stabilizer makes the fuzzy-logic power system stabilizer adaptive to changes in the operating conditions. Therefore, the degradation of the system response, under a wide range of operating conditions, is less compared to the system response with a fixed-parameter fuzzy-logic power system stabilizer and a conventional (linear) power system stabilizer. The tuned stabilizer has been tested by performing nonlinear simulations using a synchronous machine-infinite bus model. The responses are compared with a fixed parameters fuzzy-logic power system stabilizer and a conventional (linear) power system stabilizer. It is shown that the tuned fuzzy-logic power system stabilizer is superior to both of them

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Transistor-based filter for inhibiting load noise from entering a power supply

Science.gov (United States)

Taubman, Matthew S

2013-07-02

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

Science.gov (United States)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Large signal S-parameters: modeling and radiation effects in microwave power transistors

International Nuclear Information System (INIS)

Graham, E.D. Jr.; Chaffin, R.J.; Gwyn, C.W.

1973-01-01

Microwave power transistors are usually characterized by measuring the source and load impedances, efficiency, and power output at a specified frequency and bias condition in a tuned circuit. These measurements provide limited data for circuit design and yield essentially no information concerning broadbanding possibilities. Recently, a method using large signal S-parameters has been developed which provides a rapid and repeatable means for measuring microwave power transistor parameters. These large signal S-parameters have been successfully used to design rf power amplifiers. Attempts at modeling rf power transistors have in the past been restricted to a modified Ebers-Moll procedure with numerous adjustable model parameters. The modified Ebers-Moll model is further complicated by inclusion of package parasitics. In the present paper an exact one-dimensional device analysis code has been used to model the performance of the transistor chip. This code has been integrated into the SCEPTRE circuit analysis code such that chip, package and circuit performance can be coupled together in the analysis. Using []his computational tool, rf transistor performance has been examined with particular attention given to the theoretical validity of large-signal S-parameters and the effects of nuclear radiation on device parameters. (auth)

Complementary HFET technology for low-power mixed-mode applications

Energy Technology Data Exchange (ETDEWEB)

Baca, A.G.; Sherwin, M.E.; Zolper, J.C.; Dubbert, D.F.; Hietala, V.M.; Shul, R.J.; Sloan, L.R.; Hafich, M.J.

1996-06-01

Development of a complementary heterostructure field effect transistor (CHFET) technology for low-power, mixed-mode digital-microwave applications is presented. An earlier digital CHFET technology with independently optimizable transistors which operated with 319 ps loaded gate delays at 8.9 fJ is reviewed. Then work demonstrating the applicability of the digital nJFET device as a low-power microwave transistor in a hybrid microwave amplifier without any modification to the digital process is presented. A narrow band amplifier with a 0.7 {times} 100 {micro}m nJFET as the active element was designed, constructed, and tested. At 1 mW operating power, the amplifier showed 9.7 dB of gain at 2.15 GHz and a minimum noise figure of 2.5 dB. In addition, next generation CHFET transistors with sub 0.5 {micro}m gate lengths were developed. Cutoff frequencies, f{sub t} of 49 GHz and 11.5 GHz were achieved for n- and p-channel FETs with 0.3 and 0.4 {micro}m gates, respectively. These FETs will enable both digital and microwave circuits with enhanced performance.

Adaptive Supply Voltage Management for Low Power Logic Circuitry Operating at Subthreshold

OpenAIRE

Rehan Ahmed

2015-01-01

With the rise in demand of portable hand held devices and with the rise in application of wireless sensor networks and RFID reduction of total power consumption has become a necessity. To save power we operate the logic circuitry of our devices at sub-threshold. In sub-threshold the drain current is exponentially dependent on the threshold voltage hence the threshold variation causes profound variation of ION and IOFF the ratio of which affect the speed of a circuit drastically. S...

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Radiation resistance of wide-bandgap semiconductor power transistors

Energy Technology Data Exchange (ETDEWEB)

Hazdra, Pavel; Popelka, Stanislav [Department of Microelectronics, Czech Technical University in Prague (Czech Republic)

2017-04-15

Radiation resistance of state-of-the-art commercial wide-bandgap power transistors, 1700 V 4H-SiC power MOSFETs and 200 V GaN HEMTs, to the total ionization dose was investigated. Transistors were irradiated with 4.5 MeV electrons with doses up to 2000 kGy. Electrical characteristics and introduced defects were characterized by current-voltage (I-V), capacitance-voltage (C-V), and deep level transient spectroscopy (DLTS) measurements. Results show that already low doses of 4.5 MeV electrons (>1 kGy) cause a significant decrease in threshold voltage of SiC MOSFETs due to embedding of the positive charge into the gate oxide. On the other hand, other parameters like the ON-state resistance are nearly unchanged up to the dose of 20 kGy. At 200 kGy, the threshold voltage returns back close to its original value, however, the ON-state resistance increases and transconductance is lowered. This effect is caused by radiation defects introduced into the low-doped drift region which decrease electron concentration and mobility. GaN HEMTs exhibit significantly higher radiation resistance. They keep within the datasheet specification up to doses of 2000 kGy. Absence of dielectric layer beneath the gate and high concentration of carriers in the two dimensional electron gas channel are the reasons of higher radiation resistance of GaN HEMTs. Their degradation then occurs at much higher doses due to electron mobility degradation. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

Science.gov (United States)

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

KAUST Repository

Petti, Luisa

2017-03-17

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V−1 s−1 and 0.013 cm2 V−1 s−1, respectively, current on/off ratio in the range 102–104, and maximum operating voltages between −3.5 and −10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Design of digital logic control for accelerator magnet power supply

International Nuclear Information System (INIS)

Long Fengli; Hu Wei; Cheng Jian

2008-01-01

For the accelerator magnet power supply, usually the Programmable Logic Controller (PLC) is used to server as the controller for logic protection and control. Along with the development of modern accelerator technology, it is a trend to use fully-digital control to the magnet power supply. It is possible to integrate the logic control part into the digital control component of the power supply, for example, the Field Programmable Gate Array (FPGA). The paper introduces to different methods which are designed for the logic protection and control for accelerator magnet power supplies with the FPGA as the control component. (authors)

Evolution of the MOS transistor - From conception to VLSI

International Nuclear Information System (INIS)

Sah, C.T.

1988-01-01

Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

KAUST Repository

Hanna, Amir

2014-06-01

We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4x increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, similar to 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers a pragmatic opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications without any limitation any TFT materials.

75 GHz InP DHBT power amplifier based on two-stacked transistors

DEFF Research Database (Denmark)

Squartecchia, Michele; Midili, Virginio; Johansen, Tom Keinicke

2017-01-01

In this paper we present the design and measurements of a two-stage 75-GHz InP Double Heterojunction Bipolar Transistor (DHBT) power amplifier (PA). An optimized two-stacked transistor power cell has been designed, which represents the building block in the power stage as well as in the driver st......, the power amplifier exhibits a small signal gain of G = 12.6 dB, output power at 1-dB compression of Pout, 1dB = 18.6 dBm and a saturated output power of Psat > 21.4 dBm....

Transistor design considerations for low-noise preamplifiers

International Nuclear Information System (INIS)

Fair, R.B.

1976-01-01

A review is presented of design considerations for GaAs Schottky-barrier FETs and other types of transistors in low-noise amplifiers for capacitive sources which are used in nuclear radiation detectors and high speed fiber-optic communication systems. Ultimate limits on performance are evaluated in terms of the g/sub m//C/sub i/ ratio and the gate leakage current to minimize the noise sources. Si bipolar transistors and the future prospects of GaAs, Si and InAs MISFETs are discussed, and performance is compared to FETs currently being used in low-noise preamplifiers

Highly efficient conductance control in a topological insulator based magnetoelectric transistor

Energy Technology Data Exchange (ETDEWEB)

Duan, Xiaopeng; Li, Xi-Lai; Li, Xiaodong; Semenov, Yuriy G. [Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Kim, Ki Wook, E-mail: kwk@ncsu.edu [Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Department of Physics, North Carolina State University, Raleigh, North Carolina 27695 (United States)

2015-12-14

The spin-momentum interlocked properties of the topological insulator (TI) surface states are exploited in a transistor-like structure for efficient conductance control in the TI-magnet system. Combined with the electrically induced magnetization rotation as part of the gate function, the proposed structure takes advantage of the magnetically modulated TI electronic band dispersion in addition to the conventional electrostatic barrier. The transport analysis coupled with the magnetic simulation predicts super-steep current-voltage characteristics near the threshold along with the GHz operating frequencies. Potential implementation to a complementary logic is also examined. The predicted characteristics are most suitable for applications requiring low power or those with small signals.

Programmable automated transistor test system

International Nuclear Information System (INIS)

Truong, L.V.; Sundberg, G.R.

1986-01-01

The paper describes a programmable automated transistor test system (PATTS) and its utilization to evaluate bipolar transistors and Darlingtons, and such MOSFET and special types as can be accommodated with the PATTS base-drive. An application of a pulsed power technique at low duty cycles in a non-destructive test is used to examine the dynamic switching characteristic curves of power transistors. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software. In addition a library of test data is established on disks, tapes, and hard copies for future reference

Programmable, automated transistor test system

Science.gov (United States)

Truong, L. V.; Sundburg, G. R.

1986-01-01

A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.

Nanowire NMOS Logic Inverter Characterization.

Science.gov (United States)

Hashim, Yasir

2016-06-01

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Trap Healing for High-Performance Low-Voltage Polymer Transistors and Solution-Based Analog Amplifiers on Foil.

Science.gov (United States)

Pecunia, Vincenzo; Nikolka, Mark; Sou, Antony; Nasrallah, Iyad; Amin, Atefeh Y; McCulloch, Iain; Sirringhaus, Henning

2017-06-01

Solution-processed semiconductors such as conjugated polymers have great potential in large-area electronics. While extremely appealing due to their low-temperature and high-throughput deposition methods, their integration in high-performance circuits has been difficult. An important remaining challenge is the achievement of low-voltage circuit operation. The present study focuses on state-of-the-art polymer thin-film transistors based on poly(indacenodithiophene-benzothiadiazole) and shows that the general paradigm for low-voltage operation via an enhanced gate-to-channel capacitive coupling is unable to deliver high-performance device behavior. The order-of-magnitude longitudinal-field reduction demanded by low-voltage operation plays a fundamental role, enabling bulk trapping and leading to compromised contact properties. A trap-reduction technique based on small molecule additives, however, is capable of overcoming this effect, allowing low-voltage high-mobility operation. This approach is readily applicable to low-voltage circuit integration, as this work exemplifies by demonstrating high-performance analog differential amplifiers operating at a battery-compatible power supply voltage of 5 V with power dissipation of 11 µW, and attaining a voltage gain above 60 dB at a power supply voltage below 8 V. These findings constitute an important milestone in realizing low-voltage polymer transistors for solution-based analog electronics that meets performance and power-dissipation requirements for a range of battery-powered smart-sensing applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

Science.gov (United States)

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Tunneling field effect transistor technology

CERN Document Server

Chan, Mansun

2016-01-01

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Science.gov (United States)

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Brain Computation Is Organized via Power-of-Two-Based Permutation Logic

Science.gov (United States)

Xie, Kun; Fox, Grace E.; Liu, Jun; Lyu, Cheng; Lee, Jason C.; Kuang, Hui; Jacobs, Stephanie; Li, Meng; Liu, Tianming; Song, Sen; Tsien, Joe Z.

2016-01-01

There is considerable scientific interest in understanding how cell assemblies—the long-presumed computational motif—are organized so that the brain can generate intelligent cognition and flexible behavior. The Theory of Connectivity proposes that the origin of intelligence is rooted in a power-of-two-based permutation logic (N = 2i–1), producing specific-to-general cell-assembly architecture capable of generating specific perceptions and memories, as well as generalized knowledge and flexible actions. We show that this power-of-two-based permutation logic is widely used in cortical and subcortical circuits across animal species and is conserved for the processing of a variety of cognitive modalities including appetitive, emotional and social information. However, modulatory neurons, such as dopaminergic (DA) neurons, use a simpler logic despite their distinct subtypes. Interestingly, this specific-to-general permutation logic remained largely intact although NMDA receptors—the synaptic switch for learning and memory—were deleted throughout adulthood, suggesting that the logic is developmentally pre-configured. Moreover, this computational logic is implemented in the cortex via combining a random-connectivity strategy in superficial layers 2/3 with nonrandom organizations in deep layers 5/6. This randomness of layers 2/3 cliques—which preferentially encode specific and low-combinatorial features and project inter-cortically—is ideal for maximizing cross-modality novel pattern-extraction, pattern-discrimination and pattern-categorization using sparse code, consequently explaining why it requires hippocampal offline-consolidation. In contrast, the nonrandomness in layers 5/6—which consists of few specific cliques but a higher portion of more general cliques projecting mostly to subcortical systems—is ideal for feedback-control of motivation, emotion, consciousness and behaviors. These observations suggest that the brain’s basic computational

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

A comparative TCAD assessment of III-V channel materials for future high speed and low power logic applications

Science.gov (United States)

Gomes, U. P.; Takhar, K.; Ranjan, K.; Rathi, S.; Biswas, D.

2015-02-01

In this work, by means physics based drift-diffusion simulations, three different narrow band gap semiconductors; InAs, InSb and In0.53Ga0.47As, and their associated heterostructures have been studied for future high speed and low power logic applications. It is observed that In0.53Ga0.47As has higher immunity towards short channel effects with low DIBL and sub-threshold slope than InSb and InAs. Also it is observed that for the same device geometry InSb has the highest drive current and lower intrinsic delay but its ION/IOFF figure of merit is deteriorated due to excess leakage current.

Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature

KAUST Repository

Pattanasattayavong, Pichaya; Yaacobi-Gross, Nir; Zhao, Kui; Ndjawa, Guy Olivier Ngongang; Li, Jinhua; Yan, Feng; O'Regan, Brian C.; Amassian, Aram; Anthopoulos, Thomas D.

2012-01-01

ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm2 V-1 s-1. By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. Copyright © 2013 WILEY

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

KAUST Repository

Hanna, Amir

2013-12-23

We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

International Nuclear Information System (INIS)

Kobayashi, H.; Kim, W. B.; Matsumoto, T.

2011-01-01

We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

Science.gov (United States)

Mclyman, W. T. (Inventor)

1981-01-01

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

International Nuclear Information System (INIS)

Chen Liang; Zhang Wan-Rong; Jin Dong-Yue; Shen Pei; Xie Hong-Yun; Ding Chun-Bao; Xiao Ying; Sun Bo-Tao; Wang Ren-Qing

2011-01-01

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions. (interdisciplinary physics and related areas of science and technology)

Static Characteristics of the Ferroelectric Transistor Inverter

Science.gov (United States)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Brain computation is organized via power-of-two-based permutation logic

Directory of Open Access Journals (Sweden)

Kun Xie

2016-11-01

Full Text Available There is considerable scientific interest in understanding how cell assemblies - the long-presumed computational motif - are organized so that the brain can generate cognitive behavior. The Theory of Connectivity proposes that the origin of intelligence is rooted in a power-of-two-based permutation logic (N=2i–1, giving rise to the specific-to-general cell-assembly organization capable of generating specific perceptions and memories, as well as generalized knowledge and flexible actions. We show that this power-of-two-based computational logic is widely used in cortical and subcortical circuits across animal species and is conserved for the processing of a variety of cognitive modalities including appetitive, emotional and social cognitions. However, modulatory neurons, such as dopaminergic neurons, use a simpler logic despite their distinct subtypes. Interestingly, this specific-to-general permutation logic remained largely intact despite the NMDA receptors – the synaptic switch for learning and memory – were deleted throughout adulthood, suggesting that it is likely developmentally pre-configured. Moreover, this logic is implemented in the cortex vertically via combining a random-connectivity strategy in superficial layers 2/3 with nonrandom organizations in deep layers 5/6. This randomness of layers 2/3 cliques – which preferentially encode specific and low-combinatorial features and project inter-cortically – is ideal for maximizing cross-modality novel pattern-extraction, pattern-discrimination, and pattern-categorization using sparse code, consequently explaining why it requires hippocampal offline-consolidation. In contrast, the non-randomness in layers 5/6 - which consists of few specific cliques but a higher portion of more general cliques projecting mostly to subcortical systems – is ideal for robust feedback-control of motivation, emotion, consciousness, and behaviors. These observations suggest that the brain’s basic

Flexible logic circuits composed of chalcogenide-nanocrystal-based thin film transistors

International Nuclear Information System (INIS)

Yun, Junggwon; Cho, Kyoungah; Kim, Sangsig

2010-01-01

Complementary NAND and NOR gates composed of p-channel HgTe-nanocrystal (NC) films and n-channel HgSe-NC films were constructed on back-gate patterned plastic substrates. The NAND gate was made of two HgTe-p-channel thin film transistors (TFTs) in parallel and two HgSe-n-channel TFTs in series. The NOR gate was built up with both two HgSe-n-channel TFTs in parallel and two HgTe-p-channel TFTs in series. The mobility and on/off ratio for the p-channel TFTs were estimated to be 0.9 cm 2 V -1 s -1 and 10, respectively, and those for the n-channel TFTs were measured to be 1.8 cm 2 V -1 s -1 and 10 2 , respectively. The NAND and NOR gates were operated with gains of 1.45 and 1.63 and transition widths of 7.8 and 6.2 V, respectively, at room temperature in air. In addition, the operations of the NAND and NOR logics are reproducible for up to 1000 strain cycles.

Radiation damage to integrated injection logic cells

International Nuclear Information System (INIS)

Pease, R.L.; Galloway, K.F.; Stehlin, R.A.

1975-01-01

The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (l 2 L) cell and an l 2 L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed

Electron irradiation of power transistors

International Nuclear Information System (INIS)

Hower, P.L.; Fiedor, R.J.

1982-01-01

A method for reducing storage time and gain parameters in a semiconductor transistor includes the step of subjecting the transistor to electron irradiation of a dosage determined from measurements of the parameters of a test batch of transistors. Reduction of carrier lifetime by proton bombardment and gold doping is mentioned as an alternative to electron irradiation. (author)

Developing Student Worksheet Based On Higher Order Thinking Skills on the Topic of Transistor Power Amplifier

Science.gov (United States)

Sardia Ratna Kusuma, Luckey; Rakhmawati, Lusia; Wiryanto

2018-04-01

The purpose of this study is to develop a student worksheet about the transistor power amplifier based on higher order thinking skills include critical, logical, reflective, metacognitive, and creative thinking, which could be useful for teachers in improving student learning outcomes. Research and Development (R & D) methodology was used in this study. The pilot study of the worksheet was carried out with class X AV 2 at SMK Negeri 5 Surabaya. The result showed satisfies aspect of validity with 81.76 %, and effectiveness (students learning outcomes is classically passed out with percentage of 82.4 % and the students gave positive responses to the student worksheet of each statement. It can be concluded that this worksheet categorized good and worthy to be used as a source of learning in the learning activities.

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel

Directory of Open Access Journals (Sweden)

Orly Yadid-Pecht

2012-07-01

Full Text Available Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR and Dynamic Range (DR as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

SiC for microwave power transistors

Energy Technology Data Exchange (ETDEWEB)

Sriram, S.; Siergiej, R.R.; Clarke, R.C.; Agarwal, A.K.; Brandt, C.D. [Northrop Grumman Sci. and Technol. Center, Pittsburgh, PA (United States)

1997-07-16

The advantages of SiC for high power, microwave devices are discussed. The design considerations, fabrication, and experimental results are described for SiC MESFETs and SITs. The highest reported f{sub max} for a 0.5 {mu}m MESFET using semi-insulating 4H-SiC is 42 GHz. These devices also showed a small signal gain of 5.1 dB at 20 GHz. Other 4H-SiC MESFETs have shown a power density of 3.3 W/mm at 850 MHz. The largest SiC power transistor reported is a 450 W SIT measured at 600 MHz. The power output density of this SIT is 2.5 times higher than that of comparable silicon devices. SITs have been designed to operate as high as 3.0 GHz, with a 3 cm periphery part delivering 38 W of output power. (orig.) 28 refs.

A Survey on Modeling and Simulation of MEMS Switches and Its Application in Power Gating Techniques

OpenAIRE

Pramod Kumar M.P; A.S. Augustine Fletcher

2014-01-01

Large numbers of techniques have been developed to reduce the leakage power, including supply voltage scaling, varying threshold voltages, smaller logic banks, etc. Power gating is a technique which is used to reduce the static power when the sleep transistor is in off condition. Micro Electro mechanical System (MEMS) switches have properties that are very close to an ideal switch, with infinite off-resistance due to an air gap and low on-resistance due to the ohmic metal to m...

Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

KAUST Repository

Hanna, Amir; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor

Fuzzy logic based power-efficient real-time multi-core system

CERN Document Server

Ahmed, Jameel; Najam, Shaheryar; Najam, Zohaib

2017-01-01

This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors. .

Power-Split Hybrid Electric Vehicle Energy Management Based on Improved Logic Threshold Approach

Directory of Open Access Journals (Sweden)

Zhumu Fu

2013-01-01

Full Text Available We design an improved logic threshold approach of energy management for a power-split HEV assisted by an integrated starter generator (ISG. By combining the efficiency map and the optimum torque curve of internal combustion engine (ICE with the state of charge (SOC of batteries, the improved logic threshold controller manages the ICE within its peak efficiency region at first. Then the electrical power demand is established based on the ICE energy output. On that premise, a variable logic threshold value K is defined to achieve the power distribution between the ISG and the electric motor/generator (EMG. Finally, simulation models for the power-split HEV with improved logic threshold controller are established in ADVISOR. Compared to the equally power-split HEV with the logic threshold controller, when using the improved logic threshold controller, the battery power consumption, the ICE efficiency, the fuel consumption, and the motor driving system efficiency are improved.

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

A fuzzy logic pitch angle controller for power system stabilization

Energy Technology Data Exchange (ETDEWEB)

Jauch, Clemens; Cronin, Tom; Sorensen, Poul [Wind Energy Department, Riso National Laboratory, PO Box 49, DK-4000 Roskilde, (Denmark); Jensen, Birgitte Bak [Institute of Energy Technology, Aalborg University, Pontoppidanstraede 101, DK-9220 Aalborg East, (Denmark)

2006-07-12

In this article the design of a fuzzy logic pitch angle controller for a fixed speed, active-stall wind turbine, which is used for power system stabilization, is presented. The system to be controlled, which is the wind turbine and the power system to which the turbine is connected, is described. The advantages of fuzzy logic control when applied to large-signal control of active-stall wind turbines are outlined. The general steps of the design process for a fuzzy logic controller, including definition of the controller inputs, set-up of the fuzzy rules and the method of defuzzification, are described. The performance of the controller is assessed by simulation, where the wind turbine's task is to dampen power system oscillations. In the scenario simulated for this work, the wind turbine has to ride through a transient short-circuit fault and subsequently contribute to the damping of the grid frequency oscillations that are caused by the transient fault. It is concluded that the fuzzy logic controller enables the wind turbine to dampen power system oscillations. It is also concluded that, owing to the inherent non-linearities in a wind turbine and the unpredictability of the whole system, the fuzzy logic controller is very suitable for this application. (Author).

Failure rates for accelerated acceptance testing of silicon transistors

Science.gov (United States)

Toye, C. R.

1968-01-01

Extrapolation tables for the control of silicon transistor product reliability have been compiled. The tables are based on a version of the Arrhenius statistical relation and are intended to be used for low- and medium-power silicon transistors.

Transistor and integrated circuit manufacture

Energy Technology Data Exchange (ETDEWEB)

Colman, D

1978-09-27

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Directory of Open Access Journals (Sweden)

Qutaiba Alasad

2017-09-01

Full Text Available The outsourcing of integrated circuit (IC fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs to replace the conventional Exclusive-OR (XOR-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

Material Targets for Scaling All-Spin Logic

Science.gov (United States)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Low Power and High Sensitivity MOSFET-Based Pressure Sensor

International Nuclear Information System (INIS)

Zhang Zhao-Hua; Ren Tian-Ling; Zhang Yan-Hong; Han Rui-Rui; Liu Li-Tian

2012-01-01

Based on the metal-oxide-semiconductor field effect transistor (MOSFET) stress sensitive phenomenon, a low power MOSFET pressure sensor is proposed. Compared with the traditional piezoresistive pressure sensor, the present pressure sensor displays high performances on sensitivity and power consumption. The sensitivity of the MOSFET sensor is raised by 87%, meanwhile the power consumption is decreased by 20%. (cross-disciplinary physics and related areas of science and technology)

The conflicting logics of the Europe of electric power

International Nuclear Information System (INIS)

Audigier, Pierre

2013-01-01

As the European Union has no explicit competency in the field of energy policy, the author outlines that two logics exist which constrain the freedom of action of member states: the logics of competition which is the exclusive competency of the European Commission, and the logics of exemption granted to renewable energies. The author aims at highlighting the always exacerbating contradiction between these both logics, and the perverse effect of this contradiction on the evolution of the European electric power system. He comments the European and German policies regarding renewable energies, and outlines the chaos they create. He comments the position of the European commission with respect to renewable energies, the status of development of renewable energies in Germany and in border countries, and finally outlines that the European market will be always more disturbed by the priority given to intermittent electric power sources

Transistor and integrated circuit manufacture

International Nuclear Information System (INIS)

Colman, D.

1978-01-01

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Directory of Open Access Journals (Sweden)

Ravi S. P. Nair

2015-09-01

Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

Science.gov (United States)

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

Energy Technology Data Exchange (ETDEWEB)

Hunter, By Simon; Anthopoulos, Thomas D., E-mail: t.anthopoulos@ic.ac.uk [Department of Physics and Centre for Plastic Electronics, Imperial College London, South Kensington SW7 2AZ (United Kingdom); Ward, Jeremy W.; Jurchescu, Oana D. [Department of Physics, Wake Forest University, Winston-Salem, North Carolina 27109 (United States); Payne, Marcia M.; Anthony, John E. [Department of Chemistry, University of Kentucky, Lexington, Kentucky 40506 (United States)

2015-06-01

Organic thin-film electronics have long been considered an enticing candidate in achieving high-throughput manufacturing of low-power ubiquitous electronics. However, to achieve this goal, more work is required to reduce operating voltages and develop suitable mass-manufacture techniques. Here, we demonstrate low-voltage spray-cast organic thin-film transistors based on a semiconductor blend of 2,8-difluoro- 5,11-bis (triethylsilylethynyl) anthradithiophene and poly(triarylamine). Both semiconductor and dielectric films are deposited via successive spray deposition in ambient conditions (air with 40%–60% relative humidity) without any special precautions. Despite the simplicity of the deposition method, p-channel transistors with hole mobilities of >1 cm{sup 2}/Vs are realized at −4 V operation, and unipolar inverters operating at −6 V are demonstrated.

Controlled ion-beam transformation of silicon bipolar microwave power transistor's characteristics

International Nuclear Information System (INIS)

Solodukha, V.A.; Snitovskij, Yu.P.

2015-01-01

In this article, a method for changing the silicon bipolar microwave power transistor's characteristics in a direct and deliberate manner by modifying the chemical composition at the molybdenum - silicon boundary, the electro-physical properties of molybdenum - silicon contacts, and the electrophysical characteristics of transistor structure areas by the phosphorus ions irradiation of generated ohmic molybdenum - silicon contacts to the transistor emitters is proposed for the first time. The possibilities of this method are investigated and confirmed experimentally. (authors)

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

Science.gov (United States)

Wang, Tian; Cui, Xiaoxin; Ni, Yewen; Liao, Kai; Liao, Nan; Yu, Dunshan; Cui, Xiaole

2017-04-01

With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability. Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

Quantum ballistic transistor and low noise HEMT for cryo-electronics lower than 4.2 K

International Nuclear Information System (INIS)

Gremion, E.

2008-01-01

Next generations of cryo-detectors, widely used in physics of particles and physics of universe, will need in the future high-performance cryo-electronics less noisy and closer to the detector. Within this context, this work investigates properties of two dimensional electron gas GaAlAs/GaAs by studying two components, quantum point contact (QPC) and high electron mobility transistor (HEMT). Thanks to quantized conductance steps in QPC, we have realized a quantum ballistic transistor (voltage gain higher than 1), a new component useful for cryo-electronics thanks to its operating temperature and weak power consumption (about 1 nW). Moreover, the very low capacity of this component leads to promising performances for multiplexing low temperature bolometer dedicated to millimetric astronomy. The second study focused on HEMT with very high quality 2DEG. At 4.2 K, a voltage gain higher than 20 can be obtained with a very low power dissipation of less than 100 μW. Under the above experimental conditions, an equivalent input voltage noise of 1.2 nV/√(Hz) at 1 kHz and 0.12 nV/√(Hz) at 100 kHz has been reached. According to the Hooge formula, these noise performances are get by increasing gate capacity estimated to 60 pF. (author)

Single-event burnout of power bipolar junction transistors

International Nuclear Information System (INIS)

Titus, J.L.; Johnson, G.H.; Schrimpf, R.D.; Galloway, K.F.

1991-01-01

Experimental evidence of single-event burnout of power bipolar junctions transistors (BJTs) is reported for the first time. Several commercial power BJTs were characterized in a simulated cosmic ray environment using mono-energetic ions at the tandem Van de Graaff accelerator facility at Brookhaven National Laboratory. Most of the device types exposed to this simulated environment exhibited burnout behavior. In this paper the experimental technique, data, and results are presented, while a qualitative model is used to help explain those results and trends observed in this experiment

A new universal gate for low power SoC applications

Indian Academy of Sciences (India)

This paper formulates a new design technique for an area and energy ... Low power; CMOS; pass-transistor; NAND gate; Koomey's law. 1. ... amount of battery you need will fall by a factor of two every year and a half' (Koomey Jonathan.

Low-voltage protonic/electronic hybrid indium zinc oxide synaptic transistors on paper substrates

International Nuclear Information System (INIS)

Wu, Guodong; Wan, Changjin; Wan, Qing; Zhou, Jumei; Zhu, Liqiang

2014-01-01

Low-voltage (1.5 V) indium zinc oxide (IZO)-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by nanogranular proton conducting SiO 2 electrolyte films are fabricated on paper substrates. Both enhancement-mode and depletion-mode operation are obtained by tuning the thickness of the IZO channel layer. Furthermore, such flexible IZO protonic/electronic hybrid EDL TFTs can be used as artificial synapses, and synaptic stimulation response and short-term synaptic plasticity function are demonstrated. The protonic/electronic hybrid EDL TFTs on paper substrates proposed here are promising for low-power flexible paper electronics, artificial synapses and bioelectronics. (paper)

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Science.gov (United States)

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

Science.gov (United States)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Error Immune Logic for Low-Power Probabilistic Computing

Directory of Open Access Journals (Sweden)

Bo Marr

2010-01-01

design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

Fermilab main accelerator quadrupole transistorized regulators for improved tune stability

International Nuclear Information System (INIS)

Yarema, R.J.; Pfeffer, H.

1977-01-01

During early operation of the Fermilab Main Accelerator, tune fluctuations, caused by the SCR-controlled power supplies in the quad bus, limited the beam aperature at low energies. To correct this problem, two transistorized power supplies were built in 1975 to regulate and filter the main ring quad magnet current during injection and beam acceleration through the rf transistion region. There is one power supply in series with each quad bus. Each supply uses 320 parallel power transistors and is rated at 300A, 120V. Since the voltage and current capabilities of the transistorized supplies are limited, the supplies are turned-off at about 25GeV. A real-time computer system initiates turn-on of the SCR-controlled power supplies and regulation takeover by the SCR-controlled supplies, at the appropriate times

Planar transistors and impatt diodes with ion implantation

International Nuclear Information System (INIS)

Dorendorf, H.; Glawischnig, H.; Grasser, L.; Hammerschmitt, J.

1975-03-01

Low frequency planar npn and pnp transistors have been developed in which the base and emitter have been fabricated using ion implantation of boron and phosphorus by a drive-in diffusion. Electrical parameters of the transistors are comparable with conventionally produced transistors; the noise figure was improved and production tolerances were significantly reduced. Silicon-impatt diodes for the microwave range were also fabricated with implanted pn junctions and tested for their high frequency characteristics. These diodes, made in an improved upside down technology, delivered output power up to 40 mW (burn out power) at 30 GHz. Reverse leakage current and current carrying capability of these diodes were comparable to diffused structures. (orig.) 891 ORU 892 MB [de

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

Science.gov (United States)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems.

Science.gov (United States)

Wang, Zhongqiang; Ambrogio, Stefano; Balatti, Simone; Ielmini, Daniele

2014-01-01

Resistive (or memristive) switching devices based on metal oxides find applications in memory, logic and neuromorphic computing systems. Their small area, low power operation, and high functionality meet the challenges of brain-inspired computing aiming at achieving a huge density of active connections (synapses) with low operation power. This work presents a new artificial synapse scheme, consisting of a memristive switch connected to 2 transistors responsible for gating the communication and learning operations. Spike timing dependent plasticity (STDP) is achieved through appropriate shaping of the pre-synaptic and the post synaptic spikes. Experiments with integrated artificial synapses demonstrate STDP with stochastic behavior due to (i) the natural variability of set/reset processes in the nanoscale switch, and (ii) the different response of the switch to a given stimulus depending on the initial state. Experimental results are confirmed by model-based simulations of the memristive switching. Finally, system-level simulations of a 2-layer neural network and a simplified STDP model show random learning and recognition of patterns.

Modelling, development and optimization of integrated power LDMOS transistor. Performance limits in terms of energy; Modelisation, conception et optimisation de composant de puissance lateral DMOS integre. Etude des limites de performance en energie

Energy Technology Data Exchange (ETDEWEB)

Farenc, D.

1997-12-16

Technologies for Smart Power Integrated Circuits combine into a single chip Bipolar and CMOS transistors, plus power with lateral or vertical DMOS transistors. Complexity which has been increasing dramatically since the mid-80`s has allowed to integrate, into a single monolithic solution, entire systems. This thesis deals with the modelling, conception and test of the power integrated LDMOS transistor. The power LDMOS transistor is used as a switching device. It is characterized by two parameters which are the Specific On-resistance R{sub sp} and the breakdown voltage BV{sub DSS}. The LDMOS transistor developed for the new Smart Power technology exhibits a Specific On-resistance of 200 m{Omega}{sup *}mm{sup 2} and a breakdown voltage of 60 V. This device is dedicated to automotive applications. A reduction of the power device which is achieved with a low Specific On-resistance puts forward new issues such as the maximum Energy capability. When the power device is switched-off on an inductive load, a certain amount of energy is dissipated; if it is beyond a certain limit, the device is destroyed. Our goal is to determine the energy limits which are associated with our new Power integrated LDMOS transistor. (author) 28 refs.

Feasible reactor power cutback logic development for an integral reactor

International Nuclear Information System (INIS)

Han, Soon-Kyoo; Lee, Chung-Chan; Choi, Suhn; Kang, Han-Ok

2013-01-01

Major features of integral reactors that have been developed around the world recently are simplified operating systems and passive safety systems. Even though highly simplified control system and very reliable components are utilized in the integral reactor, the possibility of major component malfunction cannot be ruled out. So, feasible reactor power cutback logic is required to cope with the malfunction of components without inducing reactor trip. Simplified reactor power cutback logic has been developed on the basis of the real component data and operational parameters of plant in this study. Due to the relatively high rod worth of the integral reactor the control rod assembly drop method which had been adapted for large nuclear power plants was not desirable for reactor power cutback of the integral reactor. Instead another method, the control rod assembly control logic of reactor regulating system controls the control rod assembly movements, was chosen as an alternative. Sensitivity analyses and feasibility evaluations were performed for the selected method by varying the control rod assembly driving speed. In the results, sensitivity study showed that the performance goal of reactor power cutback system could be achieved with the limited range of control rod assembly driving speed. (orig.)

Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature

KAUST Repository

Pattanasattayavong, Pichaya

2012-12-27

The wide bandgap and highly transparent inorganic compound copper(I) thiocyanate (CuSCN) is used for the first time to fabricate p-type thin-film transistors processed from solution at room temperature. By combining CuSCN with the high-k relaxor ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm2 V-1 s-1. By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A low-power multi port register file design using a low-swing strategy

International Nuclear Information System (INIS)

Yan Hao; Liu Yan; Hua Siliang; Wang Donghui; Hou Chaohuan

2012-01-01

A low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power. This method contains two parts: WRITE and READ strategy. In the WRITE low-swing scheme, the modified memory cell is used to support low-swing WRITE. The modified NAND decoder not only dissipates less power, but also enables a great deal of area reduction. Compared with the conventional single-ended register file, the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately. The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy. (semiconductor integrated circuits)

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

Energy Technology Data Exchange (ETDEWEB)

Erofeev, E. V., E-mail: erofeev@micran.ru [Tomsk State University of Control Systems and Radioelectronics, Research Institute of Electrical-Communication Systems (Russian Federation); Fedin, I. V.; Kutkov, I. V. [Research and Production Company “Micran” (Russian Federation); Yuryev, Yu. N. [National Research Tomsk Polytechnic University, Institute of Physics and Technology (Russian Federation)

2017-02-15

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

International Nuclear Information System (INIS)

Erofeev, E. V.; Fedin, I. V.; Kutkov, I. V.; Yuryev, Yu. N.

2017-01-01

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V_t_h = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V_t_h = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

A pixel segmented silicon strip detector for ultra fast shaping at low noise and low power consumption

International Nuclear Information System (INIS)

Misiakos, K.; Kavadias, S.

1996-01-01

A new radiation imaging device is proposed based on strips segmented into small pixels. Every pixel contains a submicron transistor that is normally biased in weak inversion. The ionization charge, upon collection by the pixel, changes the bias of the transistor to strong inversion and supplies a current up to several tens of a microA. This is a consequence of the small pixel capacitance (12 fF). The drains and sources of the transistors on the same row and column are shorted to bus lines that effectively become the Y and X coordinates. These bus lines are connected to the off chip ICON amplifiers to provide a 10 ns peaking time at a noise of about 150 electrons and 1 nW power consumption, for a 10x10 cm 2 detector and a MIP excitation. The noise performance is dominated by the ICON transistors. The cross talk between adjacent strips can be kept at a few percentage points provided a low transistor bias current is used

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

A Novel Realization of Low-Power and Low-Distortion Multiplier Circuit with Improved Dynamic Range

Directory of Open Access Journals (Sweden)

Ali Naderi Saatlo

2017-01-01

Full Text Available A novel topology of four-quadrant analog multiplier circuit is presented in this paper. The voltage mode technique is employed to design the circuit in CMOS technology. The dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. Also the proposed multiplier is suitable for low voltage operation and its power consumption is relatively low. In order to verify the performance of the proposed circuit, performance of the circuit affected by second order effects including transistor mismatch and mobility reduction is analyzed in detail. It will be shown that any conceivable mismatch in the transistor parameters leads to second harmonic distortion. Additionally, the effect of mobility reduction in the third harmonic distortion will be computed. In order to simulate the circuit, Cadence and HSPICE software are used with TSMC level 49 (BSIM3v3 parameters for 0.18 μm CMOS technology, where under supply voltage of 1.5 V, total power consumption is 44 µW, the corresponding average nonlinearity remains as low as 1 %, and the input range of the circuit is ± 400 mV.

Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

Energy Technology Data Exchange (ETDEWEB)

Liu, Yang Hui; Wan, Qing, E-mail: wanqing@nju.edu.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China); Qiang Zhu, Li, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Shi, Yi [School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China)

2014-03-31

Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ∼5.5 × 10{sup −3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ∼2.0 μF/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup −1} s{sup −1}, 2.8 × 10{sup 6}, and 130 mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

r-Universal reversible logic gates

International Nuclear Information System (INIS)

Vos, A de; Storme, L

2004-01-01

Reversible logic plays a fundamental role both in ultra-low power electronics and in quantum computing. It is therefore important to know which reversible logic gates can be used as building block for the reversible implementation of an arbitrary boolean function and which cannot

High current transistor pulse generator

International Nuclear Information System (INIS)

Nesterov, V.; Cassel, R.

1991-05-01

A solid state pulse generator capable of delivering high current trapezoidally shaped pulses into an inductive load has been developed at SLAC. Energy stored in the capacitor bank of the pulse generator is switched to the load through a pair of Darlington transistors. A combination of diodes and Darlington transistors is used to obtain trapezoidal or triangular shaped current pulses into an inductive load and to recover the remaining energy in the same capacitor bank without reversing capacitor voltage. The transistors work in the switch mode, and the power losses are low. The rack mounted pulse generators presently used at SLAC contain a 660 microfarad storage capacitor bank and can deliver 400 amps at 800 volts into inductive loads up to 3 mH. The pulse generators are used in several different power systems, including pulse to pulse bipolar power supplies and in application with current pulses distributed into different inductive loads. The current amplitude and discharge time are controlled by the central computer system through a specially developed multichannel controller. Several years of operation with the pulse generators have proven their consistent performance and reliability. 8 figs

Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

International Nuclear Information System (INIS)

Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

2010-01-01

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

The point of practical use for the transistor circuit

International Nuclear Information System (INIS)

1996-01-01

This is comprised of eight chapters and goes as follows; what is transistor? the first step for use of transistor such as connection between power and signal source, static characteristic of transistor and equivalent circuit of transistor, design of easy small-signal amplifier circuit, design for amplification of electric power and countermeasure for prevention of trouble, transistor concerned interface, transistor circuit around micro computer, transistor in active use of FET and power circuit and transistor. It has an appendix on transistor and design of bias of FET circuits like small signal transistor circuit and FET circuit.

Buried injector logic, a vertical IIL using deep ion implantation

NARCIS (Netherlands)

Mouthaan, A.J.

1987-01-01

A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is

GaN transistors on Si for switching and high-frequency applications

Science.gov (United States)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

Science.gov (United States)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

KAUST Repository

Chappanda, K N

2018-02-16

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

KAUST Repository

Chappanda , K. N.; Ilyas, Saad; Younis, Mohammad I.

2018-01-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

DEFF Research Database (Denmark)

Igor, Mucha

1997-01-01

A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

International Nuclear Information System (INIS)

Zheng Yuzhan; Lu Wu; Ren Diyuan; Wang Yiyuan; Wang Zhikuan; Yang Yonghui

2010-01-01

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally, through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail. (semiconductor integrated circuits)

Quantum ballistic transistor and low noise HEMT for cryo-electronics lower than 4.2 K; Transistor balistique quantique et HEMT bas-bruit pour la cryoelectronique inferieure a 4.2 K

Energy Technology Data Exchange (ETDEWEB)

Gremion, E

2008-01-15

Next generations of cryo-detectors, widely used in physics of particles and physics of universe, will need in the future high-performance cryo-electronics less noisy and closer to the detector. Within this context, this work investigates properties of two dimensional electron gas GaAlAs/GaAs by studying two components, quantum point contact (QPC) and high electron mobility transistor (HEMT). Thanks to quantized conductance steps in QPC, we have realized a quantum ballistic transistor (voltage gain higher than 1), a new component useful for cryo-electronics thanks to its operating temperature and weak power consumption (about 1 nW). Moreover, the very low capacity of this component leads to promising performances for multiplexing low temperature bolometer dedicated to millimetric astronomy. The second study focused on HEMT with very high quality 2DEG. At 4.2 K, a voltage gain higher than 20 can be obtained with a very low power dissipation of less than 100 {mu}W. Under the above experimental conditions, an equivalent input voltage noise of 1.2 nV/{radical}(Hz) at 1 kHz and 0.12 nV/{radical}(Hz) at 100 kHz has been reached. According to the Hooge formula, these noise performances are get by increasing gate capacity estimated to 60 pF. (author)

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

Science.gov (United States)

Geier, Michael

symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Silicon photonic crystal all-optical logic gates

Energy Technology Data Exchange (ETDEWEB)

Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

2013-01-03

All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

Ultra-Low Power Optical Transistor Using a Single Quantum Dot Embedded in a Photonic Wire

DEFF Research Database (Denmark)

Nguyen, H.A.; Grange, T.; Malik, N.S.

2017-01-01

Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons.......Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons....

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

Science.gov (United States)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Power Consumption of a MOSFET

Directory of Open Access Journals (Sweden)

Frederick Selkey

2010-01-01

Full Text Available A MOSFET is defined as metal oxide semiconductor field effect transistor. These electrical components are combined or integrated to form control and logic functions for laptop and desktop computers, power controls in printing devices, motor controls and are used in many other electrical circuits. All electrical devices consume electrical power based on current and voltage. For this paper we calculated the power consumption of a Toshiba 2SK3563 MOSFET during its triode mode by finding the area under the current-voltage characteristic curve.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

Science.gov (United States)

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Ultra-low power circuits based on tunnel FETs for energy harvesting applications

OpenAIRE

Cavalheiro, David

2017-01-01

There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadraticall...

Graphene field effect transistor without an energy gap.

Science.gov (United States)

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

Science.gov (United States)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Availability analysis of nuclear power plant system with the consideration of logical loop structures

International Nuclear Information System (INIS)

Matsuoka, Takeshi

2013-01-01

Nuclear power plants have logical loop structures in their system configuration. The typical example is a power source system, that is, a nuclear plant generates electricity and it is used for the operation of pumps in the plant. For the reliability or availability analysis of nuclear power plants, it is necessary to treat accurately logical loop structures. Authors have proposed an exact method for solving logical loop structure in reliability analysis, and generalized method has recently been presented. A nuclear power plant system is taken up and essential parts of logical loop structures are modeled into relatively simple form. The procedure to solve a loop structure is shown in which the proposed generalized method is applied, and availability of the system with loop structure is accurately solved. The analysis results indicate that reconsideration of present plant operating procedure should be made for the increase of safety of nuclear power plant in case of 'Loss of offsite power' incident. The analysis results also show an important role of loop structures for maintaining the overall system availability. The analysis procedure is also useful in effectively designing high reliable systems. (author)

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil

2017-11-13

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Transistor challenges - A DRAM perspective

International Nuclear Information System (INIS)

Faul, Juergen W.; Henke, Dietmar

2005-01-01

Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

Leveraging the Radiation-Resistance and Power Efficiency of Nano-Magnetic Logic to Develop More Affordable, Efficient, and Reliable Space Technologies

Data.gov (United States)

National Aeronautics and Space Administration — I am researching nano-magnetic logic (NML) because it has low power consumption, high density of computing and memory elements, CMOS integration capabilities, and...

Fundamentals of RF and microwave transistor amplifiers

CERN Document Server

Bahl, Inder J

2009-01-01

A Comprehensive and Up-to-Date Treatment of RF and Microwave Transistor Amplifiers This book provides state-of-the-art coverage of RF and microwave transistor amplifiers, including low-noise, narrowband, broadband, linear, high-power, high-efficiency, and high-voltage. Topics covered include modeling, analysis, design, packaging, and thermal and fabrication considerations. Through a unique integration of theory and practice, readers will learn to solve amplifier-related design problems ranging from matching networks to biasing and stability. More than 240 problems are included to help read

A real time fuzzy logic power management strategy for a fuel cell vehicle

International Nuclear Information System (INIS)

Hemi, Hanane; Ghouili, Jamel; Cheriti, Ahmed

2014-01-01

Highlights: • We present a real time fuzzy logic power management strategy. • This strategy is applied to hybrid electric vehicle dynamic model. • Three configurations evaluated during a drive cycle. • The hydrogen consumption is analysed for the three configurations. - Abstract: This paper presents real time fuzzy logic controller (FLC) approach used to design a power management strategy for a hybrid electric vehicle and to protect the battery from overcharging during the repetitive braking energy accumulation. The fuel cell (FC) and battery (B)/supercapacitor (SC) are the primary and secondary power sources, respectively. This paper analyzes and evaluates the performance of the three configurations, FC/B, FC/SC and FC/B/SC during real time driving conditions and unknown driving cycle. The MATLAB/Simulink and SimPowerSystems software packages are used to model the electrical and mechanical elements of hybrid vehicles and implement a fuzzy logic strategy

Power control of SAFE reactor using fuzzy logic

International Nuclear Information System (INIS)

Irvine, Claude

2002-01-01

Controlling the 100 kW SAFE (Safe Affordable Fission Engine) reactor consists of design and implementation of a fuzzy logic process control system to regulate dynamic variables related to nuclear system power. The first phase of development concentrates primarily on system power startup and regulation, maintaining core temperature equilibrium, and power profile matching. This paper discusses the experimental work performed in those areas. Nuclear core power from the fuel elements is simulated using resistive heating elements while heat rejection is processed by a series of heat pipes. Both axial and radial nuclear power distributions are determined from neuronic modeling codes. The axial temperature profile of the simulated core is matched to the nuclear power profile by varying the resistance of the heating elements. The SAFE model establishes radial temperature profile equivalence by establishing 32 control zones as the nodal coordinates. Control features also allow for slow warm up, since complete shutoff can occur in the heat pipes if heat-source temperatures drop/rise below a certain minimum value, depending on the specific fluid and gas combination in the heat pipe. The entire system is expected to be self-adaptive, i.e., capable of responding to long-range changes in the space environment. Particular attention in the development of the fuzzy logic algorithm shall ensure that the system process remains at set point, virtually eliminating overshoot on start-up and during in-process disturbances. The controller design will withstand harsh environments and applications where it might come in contact with water, corrosive chemicals, radiation fields, etc

Radiation tolerant combinational logic cell

Science.gov (United States)

Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

2009-01-01

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

DESIGN OF LOW EPI AND HIGH THROUGHPUT CORDIC CELL TO IMPROVE THE PERFORMANCE OF MOBILE ROBOT

Directory of Open Access Journals (Sweden)

P. VELRAJKUMAR

2014-04-01

Full Text Available This paper mainly focuses on pass logic based design, which gives an low Energy Per Instruction (EPI and high throughput COrdinate Rotation Digital Computer (CORDIC cell for application of robotic exploration. The basic components of CORDIC cell namely register, multiplexer and proposed adder is designed using pass transistor logic (PTL design. The proposed adder is implemented in bit-parallel iterative CORDIC circuit whereas designed using DSCH2 VLSI CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The propagation delay, area and power dissipation are calculated from the simulated results for proposed adder based CORDIC cell. The EPI, throughput and effect of temperature are calculated from generated layout. The output parameter of generated layout is analysed using BSIM4 advanced analyzer. The simulated result of the proposed adder based CORDIC circuit is compared with other adder based CORDIC circuits. From the analysis of these simulated results, it was found that the proposed adder based CORDIC circuit dissipates low power, gives faster response, low EPI and high throughput.

An optimized Fuzzy Logic Controller by Water Cycle Algorithm for power management of Stand-alone Hybrid Green Power generation

International Nuclear Information System (INIS)

Sarvi, Mohammad; Avanaki, Isa Nasiri

2015-01-01

Highlights: • A new method to improve the performance of renewable power management is proposed. • The proposed method is based on Fuzzy Logic optimized by the Water Cycle Algorithm. • The proposed method characteristics are compared with two other methods. • The comparisons confirm that the proposed method is robust and effectiveness one. - Abstract: This paper aims to improve the power management system of a Stand-alone Hybrid Green Power generation based on the Fuzzy Logic Controller optimized by the Water Cycle Algorithm. The proposed Stand-alone Hybrid Green Power consists of wind energy conversion and photovoltaic systems as primary power sources and a battery, fuel cell, and Electrolyzer as energy storage systems. Hydrogen is produced from surplus power generated by the wind energy conversion and photovoltaic systems of Stand-alone Hybrid Green Power and stored in the hydrogen storage tank for fuel cell later using when the power generated by primary sources is lower than load demand. The proposed optimized Fuzzy Logic Controller based power management system determines the power that is generated by fuel cell or use by Electrolyzer. In a hybrid system, operation and maintenance cost and reliability of the system are the important issues that should be considered in studies. In this regard, Water Cycle Algorithm is used to optimize membership functions in order to simultaneously minimize the Loss of Power Supply Probability and operation and maintenance. The results are compared with the particle swarm optimization and the un-optimized Fuzzy Logic Controller power management system to prove that the proposed method is robust and effective. Reduction in Loss of Power Supply Probability and operation and maintenance, are the most advantages of the proposed method. Moreover the level of the State of Charge of the battery in the proposed method is higher than other mentioned methods which leads to increase battery lifetime.

Multi-region fuzzy logic controller with local PID controllers for U-tube steam generator in nuclear power plant

Directory of Open Access Journals (Sweden)

Puchalski Bartosz

2015-12-01

Full Text Available In the paper, analysis of multi-region fuzzy logic controller with local PID controllers for steam generator of pressurized water reactor (PWR working in wide range of thermal power changes is presented. The U-tube steam generator has a nonlinear dynamics depending on thermal power transferred from coolant of the primary loop of the PWR plant. Control of water level in the steam generator conducted by a traditional PID controller which is designed for nominal power level of the nuclear reactor operates insufficiently well in wide range of operational conditions, especially at the low thermal power level. Thus the steam generator is often controlled manually by operators. Incorrect water level in the steam generator may lead to accidental shutdown of the nuclear reactor and consequently financial losses. In the paper a comparison of proposed multi region fuzzy logic controller and traditional PID controllers designed only for nominal condition is presented. The gains of the local PID controllers have been derived by solving appropriate optimization tasks with the cost function in a form of integrated squared error (ISE criterion. In both cases, a model of steam generator which is readily available in literature was used for control algorithms synthesis purposes. The proposed multi-region fuzzy logic controller and traditional PID controller were subjected to broad-based simulation tests in rapid prototyping software - Matlab/Simulink. These tests proved the advantage of multi-region fuzzy logic controller with local PID controllers over its traditional counterpart.

Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

Science.gov (United States)

Ukah, Ndubuisi Benjamin

This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

Construction and evaluation of photovoltaic power generation and power storage system using SiC field-effect transistor inverter

International Nuclear Information System (INIS)

Oku, Takeo; Matsumoto, Taisuke; Ohishi, Yuya; Hiramatsu, Koichi; Yasuda, Masashi; Shimono, Akio; Takeda, Yoshikazu; Murozono, Mikio

2016-01-01

A power storage system using spherical silicon (Si) solar cells, maximum power point tracking charge controller, lithium-ion battery and a direct current-alternating current (DC-AC) inverter was constructed. Performance evaluation of the DC-AC inverter was carried out, and the DC-AC conversion efficiencies of the SiC field-effect transistor (FET) inverter was improved compared with those of the ordinary Si-FET based inverter

Construction and evaluation of photovoltaic power generation and power storage system using SiC field-effect transistor inverter

Energy Technology Data Exchange (ETDEWEB)

Oku, Takeo, E-mail: oku@mat.usp.ac.jp; Matsumoto, Taisuke; Ohishi, Yuya [Department of Materials Science, The University of Shiga Prefecture, 2500 Hassaka, Hikone, Shiga 522-8533 (Japan); Hiramatsu, Koichi; Yasuda, Masashi [Collaborative Research Center, The University of Shiga Prefecture, 2500 Hassaka, Hikone, Shiga 522-8533 (Japan); Shimono, Akio; Takeda, Yoshikazu [Kyoshin Electric Co. Ltd., 18, Goshonouchi-Nishimachi, Shichijo, Shimogyou-ku, Kyoto 600-8865 (Japan); Murozono, Mikio [Clean Venture 21 Co., 38 Ishihara Douno-Ushirocho, Kissyouin, Minami-ku, Kyoto 601-8355 (Japan)

2016-02-01

A power storage system using spherical silicon (Si) solar cells, maximum power point tracking charge controller, lithium-ion battery and a direct current-alternating current (DC-AC) inverter was constructed. Performance evaluation of the DC-AC inverter was carried out, and the DC-AC conversion efficiencies of the SiC field-effect transistor (FET) inverter was improved compared with those of the ordinary Si-FET based inverter.

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

Science.gov (United States)

Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

2002-01-01

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Realworld maximum power point tracking simulation of PV system based on Fuzzy Logic control

Science.gov (United States)

Othman, Ahmed M.; El-arini, Mahdi M. M.; Ghitas, Ahmed; Fathy, Ahmed

2012-12-01

In the recent years, the solar energy becomes one of the most important alternative sources of electric energy, so it is important to improve the efficiency and reliability of the photovoltaic (PV) systems. Maximum power point tracking (MPPT) plays an important role in photovoltaic power systems because it maximize the power output from a PV system for a given set of conditions, and therefore maximize their array efficiency. This paper presents a maximum power point tracker (MPPT) using Fuzzy Logic theory for a PV system. The work is focused on the well known Perturb and Observe (P&O) algorithm and is compared to a designed fuzzy logic controller (FLC). The simulation work dealing with MPPT controller; a DC/DC Ćuk converter feeding a load is achieved. The results showed that the proposed Fuzzy Logic MPPT in the PV system is valid.

Fuzzy Logic Based Control of Power of PEM Fuel Cell System for Residential Application

Directory of Open Access Journals (Sweden)

Khaled MAMMAR

2009-07-01

Full Text Available This paper presents a dynamic model of Fuel cell system for residential power generation. The models proposed include a fuel cell stack model, reformer model and DC/AC inverter model. Furthermore a fuzzy logic (FLC controller is used to control active power of PEM fuel cell system. The controller modifies the hydrogen flow feedback from the terminal load. Simulation results confirmed the high performance capability of the fuzzy logic controller to control power generation.

Resonant Full-Bridge Synchronous Rectifier Utilizing 15 V GaN Transistors for Wireless Power Transfer Applications Following AirFuel Standard Operating at 6.78 MHz

DEFF Research Database (Denmark)

Jensen, Christopher Have Kiaerskou; Spliid, Frederik Monrad; Hertel, Jens Christian

2018-01-01

Connectivity in smart devices is increasingly realized by wireless connections. The remaining reason for using connectors at all is for charging the internal battery, for which wireless power transfer is an alternative. Two industry standards, AirFuel and Qi, exist to support compatibility between......, this work uses low voltage GaN transistors on the receiver (Rx) side to allow synchronous rectification and soft switching, thereby achieving high efficiency. After analyzing adequate Class-DE rectifier topologies, a ClassDE full-bridge 5 W rectifier using 15 V GaN transistors are designed and implemented...

A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Bruun, Erik

2004-01-01

This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well...... as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 d...

Flexible low-voltage organic transistors with high thermal stability at 250 °C.

Science.gov (United States)

Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

2013-07-19

Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Organic electrochemical transistors

Science.gov (United States)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan

2018-01-16

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Fuzzy-logic-based power control system for multifield electrostatic precipitators

Energy Technology Data Exchange (ETDEWEB)

Grass, N. [Siemens AG, Erlangen (Germany)

2002-10-01

The power consumption of large precipitators can be in the range of 1 MW and above. Depending on the dust load properties, the electrical power may be reduced by up to 50% by applying fuzzy logic, without significantly increasing the dust emissions. The new approach uses fuzzy logic for optimization of existing electrostatic precipitators. The software runs on a standard personal computer platform under the, Windows NT operating system. The controllers of the electrostatic precipitator power supplies are linked to the personal computer via an industrial network (e.g., PROFIBUS). The system determines online the differentials of emission versus electrical power of each field. This measurement is difficult because of overlaid events in the other zones, and process changes. The long response time of the resultant dust emission due to electrical power changes in the precipitator is an additional complication. Rules were defined for a coarse, but fast-response power adaptation of all zones. Fine tuning the running system after the coarse optimization increased the accuracy and reliability. When installed on a 4 x 5 zone precipitator in a power station, significant results were obtained. The power savings over three months of operation were in the range of 40%-60% depending on the load and fuel characteristics. Data were recorded over the test period of three months. The results are presented.

Review of mixer design for low voltage - low power applications

Science.gov (United States)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Testing Superconductor Logic Integrated Circuits

NARCIS (Netherlands)

Arun, A.J.; Kerkhoff, Hans G.

2005-01-01

Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these

A low-power wide range transimpedance amplifier for biochemical sensing.

Science.gov (United States)

Rodriguez-Villegas, Esther

2007-01-01

This paper presents a novel low voltage and low power transimpedance amplifier for amperometric potentiostats. The power is optimized by having three different gain settings for different current ranges, which can be programmed with a biasing current. The voltage ranges have been optimized by using FGMOS transistors in a second voltage amplification stage that simultaneously allow for offset calibration as well as independent biasing of the gates. The circuit operates with input currents from 1 pA to 1 microA, with a maximum power supply voltage of 1.5 V and consumes 82.5 nW, 9.825 microW, 47.325 microW for currents varying from (1 pA, 0.25 nA), (0.25 nA, 62.5 nA) and (62.5 nA, 1 microA) respectively.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

MOS Current Mode Logic Near Threshold Circuits

Directory of Open Access Journals (Sweden)

Alexander Shapiro

2014-06-01

Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

A study of s new power semiconductor insulated gate bipolar transistor (IGBT) characteristics and its application to automotive ignition

International Nuclear Information System (INIS)

Rabah, K.V.O.

1995-05-01

Assessment has been made of the problem of the on-resistance and temperature effects in the three power transistor combinations, such as Darlington-types or IGBT. The IGBT is a device in which the drain of the MOSFET feeds the bipolar base in monolithic (IC and Power on the same chip) to give it both the MOS and bipolar advantages. The high temperature operating characteristics of the device are discussed and compared to that of power bipolar transistor. Unlike the power bipolar transistor whose operating current density shows current crowding at above forward collector current of 4Amps and forward voltage drop above 0.4V, the IGBT is found to maintain its high current density above forward collector of current 1Amp (or a forward voltage drop above 1.2V). The results also indicate that these devices (IGBTs) can be interdigited (paralleled) without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.2V, and this makes it the best candidate for automotive ignition power switches. (author). 20 refs, 10 figs, 1 tab

FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

DEFF Research Database (Denmark)

Thind, Vandana; Hussain, Dil muhammed Akbar

2015-01-01

and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

Realworld maximum power point tracking simulation of PV system based on Fuzzy Logic control

Directory of Open Access Journals (Sweden)

Ahmed M. Othman

2012-12-01

Full Text Available In the recent years, the solar energy becomes one of the most important alternative sources of electric energy, so it is important to improve the efficiency and reliability of the photovoltaic (PV systems. Maximum power point tracking (MPPT plays an important role in photovoltaic power systems because it maximize the power output from a PV system for a given set of conditions, and therefore maximize their array efficiency. This paper presents a maximum power point tracker (MPPT using Fuzzy Logic theory for a PV system. The work is focused on the well known Perturb and Observe (P&O algorithm and is compared to a designed fuzzy logic controller (FLC. The simulation work dealing with MPPT controller; a DC/DC Ćuk converter feeding a load is achieved. The results showed that the proposed Fuzzy Logic MPPT in the PV system is valid.

Use of UPFC device controlled by fuzzy logic controllers for decoupled power flow control

Directory of Open Access Journals (Sweden)

Ivković Sanja

2014-01-01

Full Text Available This paper investigates the possibility of decoupled active and reactive power flow control in a power system using a UPFC device controlled by fuzzy logic controllers. A Brief theoretical review of the operation principles and applications of UPFC devices and design principles of the fuzzy logic controller used are given. A Matlab/Simulink model of the system with UPFC, the fuzzy controller setup, and graphs of the results are presented. Conclusions are drawn regarding the possibility of using this system for decoupled control of the power flow in power systems based on analysis of these graphs.

Radiation effects on JFETS, MOSFETS, and bipolar transistors, as related to SSC circuit design

Energy Technology Data Exchange (ETDEWEB)

Kennedy, E J; Gray, B; Wu, A [Dept. of Electrical and Computer Engineering, Univ. of Tennessee, Knoxville, TN (United States); Alley, G T; Britton, Jr, C L [Oak Ridge National Lab., TN (United States); Skubic, P L [Univ. of Oklahoma, Dept. of Physics and Astronomy, Norman, OK (United States)

1991-10-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular at currents {<=} 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier. (orig.).

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

Science.gov (United States)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A

Low-frequency noise in single electron tunneling transistor

DEFF Research Database (Denmark)

Tavkhelidze, A.N.; Mygind, Jesper

1998-01-01

The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz ..., we find the same input charge noise, typically QN = 5 × 10–4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends...... when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage. ©1998 American Institute of Physics....

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

Science.gov (United States)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Metal-Halide Perovskite Transistors for Printed Electronics: Challenges and Opportunities

KAUST Repository

Lin, Yen-Hung

2017-10-12

Following the unprecedented rise in photovoltaic power conversion efficiencies during the past five years, metal-halide perovskites (MHPs) have emerged as a new and highly promising class of solar-energy materials. Their extraordinary electrical and optical properties combined with the abundance of the raw materials, the simplicity of synthetic routes, and processing versatility make MHPs ideal for cost-efficient, large-volume manufacturing of a plethora of optoelectronic devices that span far beyond photovoltaics. Herein looks beyond current applications in the field of energy, to the area of large-area electronics using MHPs as the semiconductor material. A comprehensive overview of the relevant fundamental material properties of MHPs, including crystal structure, electronic states, and charge transport, is provided first. Thereafter, recent demonstrations of MHP-based thin-film transistors and their application in logic circuits, as well as bi-functional devices such as light-sensing and light-emitting transistors, are discussed. Finally, the challenges and opportunities in the area of MHPs-based electronics, with particular emphasis on manufacturing, stability, and health and environmental concerns, are highlighted.

Programmable Array Logic Design

International Nuclear Information System (INIS)

Demon Handoyo; Djen Djen Djainal

2007-01-01

Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

Directory of Open Access Journals (Sweden)

Tony T. Kim

2011-07-01

Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

International Nuclear Information System (INIS)

Gelinck, Gerwin H; Cobb, Brian; Van Breemen, Albert J J M; Myny, Kris

2015-01-01

Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these. (paper)

HDL to verification logic translator

Science.gov (United States)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

Freestanding Artificial Synapses Based on Laterally Proton-Coupled Transistors on Chitosan Membranes.

Science.gov (United States)

Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2015-10-07

Freestanding synaptic transistors are fabricated on solution-processed chitosan membranes. A short-term memory to long-term memory transition is observed due to proton-related electrochemical doping under repeated pulse stimulus. Moreover, freestanding artificial synaptic devices with multiple presynaptic inputs are investigated, and spiking logic operation and logic modulation are realized. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Artificial Synapses Based on in-Plane Gate Organic Electrochemical Transistors.

Science.gov (United States)

Qian, Chuan; Sun, Jia; Kong, Ling-An; Gou, Guangyang; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

2016-10-05

Realization of biological synapses using electronic devices is regarded as the basic building blocks for neuromorphic engineering and artificial neural network. With the advantages of biocompatibility, low cost, flexibility, and compatible with printing and roll-to-roll processes, the artificial synapse based on organic transistor is of great interest. In this paper, the artificial synapse simulation by ion-gel gated organic field-effect transistors (FETs) with poly(3-hexylthiophene) (P3HT) active channel is demonstrated. Key features of the synaptic behaviors, such as paired-pulse facilitation (PPF), short-term plasticity (STP), self-tuning, the spike logic operation, spatiotemporal dentritic integration, and modulation are successfully mimicked. Furthermore, the interface doping processes of electrolyte ions between the active P3HT layer and ion gels is comprehensively studied for confirming the operating processes underlying the conductivity and excitatory postsynaptic current (EPSC) variations in the organic synaptic devices. This study represents an important step toward building future artificial neuromorphic systems with newly emerged ion gel gated organic synaptic devices.

Current fluctuation of electron and hole carriers in multilayer WSe{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho-Kyun; Jin, Jun Eon; Kim, Gyu-Tae, E-mail: gtkim@korea.ac.kr [School of Electrical Engineering, Korea University, Seoul 02481 (Korea, Republic of); Kim, Yong Jin; Kim, Young Keun [Department of Materials Science and Engineering, Korea University, Seoul 02481 (Korea, Republic of); Shin, Minju [School of Electrical Engineering, Korea University, Seoul 02481 (Korea, Republic of); IMEP-LAHC, Grenoble INP-MINATEC, 3 Parvis Louis Neel, 38016 Grenoble (France)

2015-12-14

Two-dimensional materials have outstanding scalability due to their structural and electrical properties for the logic devices. Here, we report the current fluctuation in multilayer WSe{sub 2} field effect transistors (FETs). In order to demonstrate the impact on carrier types, n-type and p-type WSe{sub 2} FETs are fabricated with different work function metals. Each device has similar electrical characteristics except for the threshold voltage. In the low frequency noise analysis, drain current power spectral density (S{sub I}) is inversely proportional to frequency, indicating typical 1/f noise behaviors. The curves of the normalized drain current power spectral density (NS{sub I}) as a function of drain current at the 10 Hz of frequency indicate that our devices follow the carrier number fluctuation with correlated mobility fluctuation model. This means that current fluctuation depends on the trapping-detrapping motion of the charge carriers near the channel interface. No significant difference is observed in the current fluctuation according to the charge carrier type, electrons and holes that occurred in the junction and channel region.

ESTIMATION OF THERMAL PARAMETERS OF POWER BIPOLAR TRANSISTORS BY THE METHOD OF THERMAL RELAXATION DIFFERENTIAL SPECTROMETRY

Directory of Open Access Journals (Sweden)

V. S. Niss

2015-01-01

Full Text Available Thermal performance of electronic devices determines the stability and reliability of the equipment. This leads to the need for a detailed thermal analysis of semiconductor devices. The goal of the work is evaluation of thermal parameters of high-power bipolar transistors in plastic packages TO-252 and TO-126 by a method of thermal relaxation differential spectrometry. Thermal constants of device elements and distribution structure of thermal resistance defined as discrete and continuous spectra using previously developed relaxation impedance spectrometer. Continuous spectrum, based on higher-order derivatives of the dynamic thermal impedance, follows the model of Foster, and discrete to model of Cauer. The structure of sample thermal resistance is presented in the form of siх-chain electro-thermal RC model. Analysis of the heat flow spreading in the studied structures is carried out on the basis of the concept of thermal diffusivity. For transistor structures the area and distribution of the heat flow cross-section are determined. On the basis of the measurements the thermal parameters of high-power bipolar transistors is evaluated, in particular, the structure of their thermal resistance. For all of the measured samples is obtained that the thermal resistance of the layer planting crystal makes a defining contribution to the internal thermal resistance of transistors. In the transition layer at the border of semiconductor-solder the thermal resistance increases due to changes in the mechanism of heat transfer. Defects in this area in the form of delamination of solder, voids and cracks lead to additional growth of thermal resistance caused by the reduction of the active square of the transition layer. Method of thermal relaxation differential spectrometry allows effectively control the distribution of heat flow in high-power semiconductor devices, which is important for improving the design, improve the quality of landing crystals of power

Nanophotonic quantum computer based on atomic quantum transistor

International Nuclear Information System (INIS)

Andrianov, S N; Moiseev, S A

2015-01-01

We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

Nanophotonic quantum computer based on atomic quantum transistor

Energy Technology Data Exchange (ETDEWEB)

Andrianov, S N [Institute of Advanced Research, Academy of Sciences of the Republic of Tatarstan, Kazan (Russian Federation); Moiseev, S A [Kazan E. K. Zavoisky Physical-Technical Institute, Kazan Scientific Center, Russian Academy of Sciences, Kazan (Russian Federation)

2015-10-31

We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

Science.gov (United States)

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

Science.gov (United States)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Doped Organic Transistors.

Science.gov (United States)

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Vertical architecture for enhancement mode power transistors based on GaN nanowires

Science.gov (United States)

Yu, F.; Rümmler, D.; Hartmann, J.; Caccamo, L.; Schimpke, T.; Strassburg, M.; Gad, A. E.; Bakin, A.; Wehmann, H.-H.; Witzigmann, B.; Wasisto, H. S.; Waag, A.

2016-05-01

The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

Flexible Low-power SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout

Science.gov (United States)

England, Troy; Lilly, Michael; Curry, Matthew; Carr, Stephen; Carroll, Malcolm

Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout of electrons bound to Si:P donors. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will introduce two new amplifier topologies that provide excellent gain versus power tradeoffs using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The AC HBT allows in-situ adjustment of power dissipation during an experiment and can provide gain in the millikelvin temperature regime while dissipating less than 500 nW. The AC Current Amplifier maximizes gain at nearly 800 A/A. We will also show results of using these amplifiers with SETs at 4 K. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. Flexible Low-power SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout.

Transparent ambipolar organic thin film transistors based on multilayer transparent source-drain electrodes

Energy Technology Data Exchange (ETDEWEB)

Zhang, Nan; Hu, Yongsheng, E-mail: huyongsheng@ciomp.ac.cn, E-mail: liuxy@ciomp.ac.cn; Lin, Jie; Li, Yantao; Liu, Xingyuan, E-mail: huyongsheng@ciomp.ac.cn, E-mail: liuxy@ciomp.ac.cn [State Key Laboratory of Luminescence and Applications, Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033 (China)

2016-08-08

A fabrication method for transparent ambipolar organic thin film transistors with transparent Sb{sub 2}O{sub 3}/Ag/Sb{sub 2}O{sub 3} (SAS) source and drain electrodes has been developed. A pentacene/N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic di-imide (PTCDI-C13) bilayer heterojunction is used as the active semiconductor. The electrodes are deposited by room temperature electron beam evaporation. The devices are fabricated without damaging the active layers. The SAS electrodes have high transmittance (82.5%) and low sheet resistance (8 Ω/sq). High performance devices with hole and electron mobilities of 0.3 cm{sup 2}/V s and 0.027 cm{sup 2}/V s, respectively, and average visible range transmittance of 72% were obtained. These transistors have potential for transparent logic integrated circuit applications.

An optically controlled SiC lateral power transistor based on SiC/SiCGe super junction structure

International Nuclear Information System (INIS)

Pu Hongbin; Cao Lin; Ren Jie; Chen Zhiming; Nan Yagong

2010-01-01

An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively. (semiconductor devices)

An optically controlled SiC lateral power transistor based on SiC/SiCGe super junction structure

Energy Technology Data Exchange (ETDEWEB)

Pu Hongbin; Cao Lin; Ren Jie; Chen Zhiming; Nan Yagong, E-mail: puhongbin@xaut.edu.c [Xi' an University of Technology, Xi' an 710048 (China)

2010-04-15

An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 {mu}m and 0.7 {mu}m are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively. (semiconductor devices)

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon S.; Hussain, Muhammad Mustafa

2017-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Graphene Field Effect Transistor for Radiation Detection

Science.gov (United States)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Science.gov (United States)

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Microwave Enhanced Cotunneling in SET Transistors

DEFF Research Database (Denmark)

Manscher, Martin; Savolainen, M.; Mygind, Jesper

2003-01-01

Cotunneling in single electron tunneling (SET) devices is an error process which may severely limit their electronic and metrologic applications. Here is presented an experimental investigation of the theory for adiabatic enhancement of cotunneling by coherent microwaves. Cotunneling in SET...... transistors has been measured as function of temperature, gate voltage, frequency, and applied microwave power. At low temperatures and applied power levels, including also sequential tunneling, the results can be made consistent with theory using the unknown damping in the microwave line as the only free...

Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

Science.gov (United States)

2015-02-01

executed with SolidWorks Flow Simulation , a computational fluid-dynamics code. The graph in Fig. 2 shows the timing and amplitudes of power pulses...defined a convective flow of air perpendicular to the bottom surface of the mounting plate, with a velocity of 10 ft/s. The thermal simulations were...Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Science.gov (United States)

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Parametrization of the radiation induced leakage current increase of NMOS transistors

CERN Document Server

Backhaus, Malte

2017-01-13

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

Radiation and Thermal Cycling Effects on EPC1001 Gallium Nitride Power Transistors

Science.gov (United States)

Patterson, Richard L.; Scheick, Leif Z.; Lauenstein, Jean M.; Casey, Megan C.; Hammoud, Ahmad

2012-01-01

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Information pertaining to performance of electronic parts and systems under hostile environments is very scarce, especially for new devices. Such data is very critical so that proper design is implemented in order to ensure mission success and to mitigate risks associated with exposure of on-board systems to the operational environment. In this work, newly-developed enhancement-mode field effect transistors (FET) based on gallium nitride (GaN) technology were exposed to various particles of ionizing radiation and to long-term thermal cycling over a wide temperature range. Data obtained on control (un-irradiated) and irradiated samples of these power transistors are presented and the results are discussed.

Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

Energy Technology Data Exchange (ETDEWEB)

Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

2015-12-21

Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

High total dose proton irradiation effects on silicon NPN rf power transistors

International Nuclear Information System (INIS)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana; Pushpa, N.

2014-01-01

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods

High total dose proton irradiation effects on silicon NPN rf power transistors

Energy Technology Data Exchange (ETDEWEB)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in [Department of Studies in Physics, University of Mysore, Manasagangotri, Mysore-570006, Karnataka (India); Pushpa, N. [Department of PG Studies in Physics, JSS College, Ooty Road, Mysore-570025, Karnataka (India)

2014-04-24

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods.

Sidewall gated double well quasi-one-dimensional resonant tunneling transistors

Science.gov (United States)

Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Youtsey, C.

1997-12-01

We present gating characteristics of submicron vertical resonant tunneling transistors in double quantum well heterostructures. Current-voltage characteristics at room temperature and 77 K for devices with minimum feature widths of 0.9 and 0.7 μm are presented and discussed. The evolution of the I-V characteristics with increasing negative gate biases is related to the change in the lateral confinement, with a transition from a large area 2D to a quasi-1D. Even gating of multiple wells and lateral confinement effects observable at 77 K make these devices ideally suited for applications in multi-valued logic systems and low-dimensional structures.

Fuzzy logic based ELF magnetic field estimation in substations

International Nuclear Information System (INIS)

Kosalay, I.

2008-01-01

This paper examines estimation of the extremely low frequency magnetic fields (MF) in the power substation. First, the results of the previous relevant research studies and the MF measurements in a sample power substation are presented. Then, a fuzzy logic model based on the geometric definitions in order to estimate the MF distribution is explained. Visual software, which has a three-dimensional screening unit, based on the fuzzy logic technique, has been developed. (authors)

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Science.gov (United States)

Sengupta, Sarmista; Pandit, Soumya

2015-06-01

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

Thermal resistance matrix representation of thermal effects and thermal design in multi-finger power heterojunction bipolar transistors

Institute of Scientific and Technical Information of China (English)

Jin Dong-Yue; Zhang Wan-Rong; Chen Liang; Fu Qiang; Xiao Ying; Wang Ren-Qing; Zhao Xin

2011-01-01

The thermal resistance matrix including self-heating thermal resistance and thermal coupling resistance is presented to describe the thermal effects of multi-finger power heterojunction bipolar transistors. The dependence of thermal resistance matrix on finger spacing is also investigated. It is shown that both self-heating thermal resistance and thermal coupling resistance are lowered by increasing the finger spacing, in which the downward dissipated heat path is widened and the heat flow from adjacent fingers is effectively suppressed. The decrease of self-heating thermal resistance and thermal coupling resistance is helpful for improving the thermal stability of power devices. Furthermore, with the aid of the thermal resistance matrix, a 10-finger power heterojunction bipolar transistor (HBT) with non-uniform finger spacing is designed for high thermal stability. The optimized structure can effectively lower the peak temperature while maintaining a uniformity of the temperature profile at various biases and thus the device effectively may operate at a higher power level.

Accelerating the life of transistors

International Nuclear Information System (INIS)

Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

2013-01-01

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

Metal-Halide Perovskite Transistors for Printed Electronics: Challenges and Opportunities.

Science.gov (United States)

Lin, Yen-Hung; Pattanasattayavong, Pichaya; Anthopoulos, Thomas D

2017-12-01

Following the unprecedented rise in photovoltaic power conversion efficiencies during the past five years, metal-halide perovskites (MHPs) have emerged as a new and highly promising class of solar-energy materials. Their extraordinary electrical and optical properties combined with the abundance of the raw materials, the simplicity of synthetic routes, and processing versatility make MHPs ideal for cost-efficient, large-volume manufacturing of a plethora of optoelectronic devices that span far beyond photovoltaics. Herein looks beyond current applications in the field of energy, to the area of large-area electronics using MHPs as the semiconductor material. A comprehensive overview of the relevant fundamental material properties of MHPs, including crystal structure, electronic states, and charge transport, is provided first. Thereafter, recent demonstrations of MHP-based thin-film transistors and their application in logic circuits, as well as bi-functional devices such as light-sensing and light-emitting transistors, are discussed. Finally, the challenges and opportunities in the area of MHPs-based electronics, with particular emphasis on manufacturing, stability, and health and environmental concerns, are highlighted. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

Science.gov (United States)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

Transistorized ignition system for internal combustion engines, in particular for vehicles

Energy Technology Data Exchange (ETDEWEB)

Mieras, L F; Skay, F

1977-05-12

The invention concerns an ignition system for motor vehicles with solid state control of the power transistor switching the primary current of the ignition coil. A pulse generator driven by the engine is used for this, whose voltage pulses control the switching on of the power transistor and increase in a certain ratio to the engine speed. This ensures that the closing angle, i.e. the mechanical angle of rotation which the machine passes through while loading the ignition coil with mechanical energy, is automatically changed so that for low speeds it is just sufficient for certain ignition, but increases with increasing speed, so that the required ignition energy is always available. At low speeds one avoids charging current flowing through the primary winding of the ignition coil for longer than necessary and thus wasting electrical energy.

Light programmable organic transistor memory device based on hybrid dielectric

Science.gov (United States)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

Science.gov (United States)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Large-area formation of self-aligned crystalline domains of organic semiconductors on transistor channels using CONNECT

Science.gov (United States)

Park, Steve; Giri, Gaurav; Shaw, Leo; Pitner, Gregory; Ha, Jewook; Koo, Ja Hoon; Gu, Xiaodan; Park, Joonsuk; Lee, Tae Hoon; Nam, Ji Hyun; Hong, Yongtaek; Bao, Zhenan

2015-01-01

The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed “controlled OSC nucleation and extension for circuits” (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication. PMID:25902502

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

Comparison of fuzzy logic and neural network in maximum power point tracker for PV systems

Energy Technology Data Exchange (ETDEWEB)

Ben Salah, Chokri; Ouali, Mohamed [Research Unit on Intelligent Control, Optimization, Design and Optimization of Complex Systems (ICOS), Department of Electrical Engineering, National School of Engineers of Sfax, BP. W, 3038, Sfax (Tunisia)

2011-01-15

This paper proposes two methods of maximum power point tracking using a fuzzy logic and a neural network controllers for photovoltaic systems. The two maximum power point tracking controllers receive solar radiation and photovoltaic cell temperature as inputs, and estimated the optimum duty cycle corresponding to maximum power as output. The approach is validated on a 100 Wp PVP (two parallels SM50-H panel) connected to a 24 V dc load. The new method gives a good maximum power operation of any photovoltaic array under different conditions such as changing solar radiation and PV cell temperature. From the simulation and experimental results, the fuzzy logic controller can deliver more power than the neural network controller and can give more power than other different methods in literature. (author)

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Rapid single flux quantum logic in high temperature superconductor technology

NARCIS (Netherlands)

Shunmugavel, K.

2006-01-01

A Josephson junction is the basic element of rapid single flux quantum logic (RSFQ) circuits. A high operating speed and low power consumption are the main advantages of RSFQ logic over semiconductor electronic circuits. To realize complex RSFQ circuits in HTS technology one needs a reproducible

Study of Reversible Logic Synthesis with Application in SOC: A Review

Science.gov (United States)

Sharma, Chinmay; Pahuja, Hitesh; Dadhwal, Mandeep; Singh, Balwinder

2017-08-01

The prime concern in today’s SOC designs is the power dissipation which increases with technology scaling. The reversible logic possesses very high potential in reducing power dissipation in these designs. It finds its application in latest research fields such as DNA computing, quantum computing, ultra-low power CMOS design and nanotechnology. The reversible circuits can be easily designed using the conventional CMOS technology at a cost of a garbage output which maintains the reversibility. The purpose of this paper is to provide an overview of the developments that have occurred till date in this concept and how the new reversible logic gates are used to design the logic functions.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

Science.gov (United States)

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Impact of field-induced quantum confinement on the onset of tunneling field-effect transistors: Experimental verification

Energy Technology Data Exchange (ETDEWEB)

Smets, Quentin, E-mail: quentin.smets@imec.be; Verreck, Devin; Heyns, Marc M. [Imec, Kapeldreef 75, 3001 Heverlee (Belgium); KULeuven, 3000 Leuven (Belgium); Verhulst, Anne S.; Martens, Koen; Lin, Han Chung; Kazzi, Salim El; Simoen, Eddy; Collaert, Nadine; Thean, Aaron [Imec, Kapeldreef 75, 3001 Heverlee (Belgium); Raskin, Jean-Pierre [ICTEAM, Université catholique de Louvain, 1348 Louvain-la-Neuve (Belgium)

2014-11-17

The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band.

Impact of field-induced quantum confinement on the onset of tunneling field-effect transistors: Experimental verification

International Nuclear Information System (INIS)

Smets, Quentin; Verreck, Devin; Heyns, Marc M.; Verhulst, Anne S.; Martens, Koen; Lin, Han Chung; Kazzi, Salim El; Simoen, Eddy; Collaert, Nadine; Thean, Aaron; Raskin, Jean-Pierre

2014-01-01

The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band

Reconfigurable Boolean logic using magnetic single-electron transistors

Czech Academy of Sciences Publication Activity Database

Gonzalez-Zalba, M.F.; Ciccarelli, C.; Zarbo, Liviu; Irvine, A.C.; Campion, R.C.; Gallagher, B. L.; Jungwirth, Tomáš; Ferguson, A.J.; Wunderlich, Joerg

2015-01-01

Roč. 10, č. 4 (2015), e0125142 E-ISSN 1932-6203 R&D Projects: GA MŠk(CZ) LM2011026; GA ČR GB14-37427G EU Projects: European Commission(XE) 268066 - 0MSPIN Institutional support: RVO:68378271 Keywords : single-electron transitor * reconfigurable logic * ferromagnetic semiconductor Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.057, year: 2015

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity

International Nuclear Information System (INIS)

Li Jinjin; Zhu Kadi

2011-01-01

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

Science.gov (United States)

Li, Jin-Jin; Zhu, Ka-Di

2011-02-04

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

Parametrization of the radiation induced leakage current increase of NMOS transistors

International Nuclear Information System (INIS)

Backhaus, M.

2017-01-01

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon

Advances in NO2 sensing with individual single-walled carbon nanotube transistors.

Science.gov (United States)

Chikkadi, Kiran; Muoth, Matthias; Roman, Cosmin; Haluska, Miroslav; Hierold, Christofer

2014-01-01

The charge carrier transport in carbon nanotubes is highly sensitive to certain molecules attached to their surface. This property has generated interest for their application in sensing gases, chemicals and biomolecules. With over a decade of research, a clearer picture of the interactions between the carbon nanotube and its surroundings has been achieved. In this review, we intend to summarize the current knowledge on this topic, focusing not only on the effect of adsorbates but also the effect of dielectric charge traps on the electrical transport in single-walled carbon nanotube transistors that are to be used in sensing applications. Recently, contact-passivated, open-channel individual single-walled carbon nanotube field-effect transistors have been shown to be operational at room temperature with ultra-low power consumption. Sensor recovery within minutes through UV illumination or self-heating has been shown. Improvements in fabrication processes aimed at reducing the impact of charge traps have reduced the hysteresis, drift and low-frequency noise in carbon nanotube transistors. While open challenges such as large-scale fabrication, selectivity tuning and noise reduction still remain, these results demonstrate considerable progress in transforming the promise of carbon nanotube properties into functional ultra-low power, highly sensitive gas sensors.

Hybrid light emitting transistors (Presentation Recording)

Science.gov (United States)

Muhieddine, Khalid; Ullah, Mujeeb; Namdas, Ebinazar B.; Burn, Paul L.

2015-10-01

Organic light-emitting diodes (OLEDs) are well studied and established in current display applications. Light-emitting transistors (LETs) have been developed to further simplify the necessary circuitry for these applications, combining the switching capabilities of a transistor with the light emitting capabilities of an OLED. Such devices have been studied using mono- and bilayer geometries and a variety of polymers [1], small organic molecules [2] and single crystals [3] within the active layers. Current devices can often suffer from low carrier mobilities and most operate in p-type mode due to a lack of suitable n-type organic charge carrier materials. Hybrid light-emitting transistors (HLETs) are a logical step to improve device performance by harnessing the charge carrier capabilities of inorganic semiconductors [4]. We present state of the art, all solution processed hybrid light-emitting transistors using a non-planar contact geometry [1, 5]. We will discuss HLETs comprised of an inorganic electron transport layer prepared from a sol-gel of zinc tin oxide and several organic emissive materials. The mobility of the devices is found between 1-5 cm2/Vs and they had on/off ratios of ~105. Combined with optical brightness and efficiencies of the order of 103 cd/m2 and 10-3-10-1 %, respectively, these devices are moving towards the performance required for application in displays. [1] M. Ullah, K. Tandy, S. D. Yambem, M. Aljada, P. L. Burn, P. Meredith, E. B. Namdas., Adv. Mater. 2013, 25, 53, 6213 [2] R. Capelli, S. Toffanin, G. Generali, H. Usta, A. Facchetti, M. Muccini, Nature Materials 2010, 9, 496 [3] T. Takenobu, S. Z. Bisri, T. Takahashi, M. Yahiro, C. Adachi, Y. Iwasa, Phys. Rev. Lett. 2008, 100, 066601 [4] H. Nakanotani, M. Yahiro, C. Adachi, K. Yano, Appl. Phys. Lett. 2007, 90, 262104 [5] K. Muhieddine, M. Ullah, B. N. Pal, P. Burn E. B. Namdas, Adv. Mater. 2014, 26,37, 6410

AlGaN Channel Transistors for Power Management and Distribution

Science.gov (United States)

VanHove, James M.

1996-01-01

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

Development of Real Time Implementation of 5/5 Rule based Fuzzy Logic Controller Shunt Active Power Filter for Power Quality Improvement

Science.gov (United States)

Puhan, Pratap Sekhar; Ray, Pravat Kumar; Panda, Gayadhar

2016-12-01

This paper presents the effectiveness of 5/5 Fuzzy rule implementation in Fuzzy Logic Controller conjunction with indirect control technique to enhance the power quality in single phase system, An indirect current controller in conjunction with Fuzzy Logic Controller is applied to the proposed shunt active power filter to estimate the peak reference current and capacitor voltage. Current Controller based pulse width modulation (CCPWM) is used to generate the switching signals of voltage source inverter. Various simulation results are presented to verify the good behaviour of the Shunt active Power Filter (SAPF) with proposed two levels Hysteresis Current Controller (HCC). For verification of Shunt Active Power Filter in real time, the proposed control algorithm has been implemented in laboratory developed setup in dSPACE platform.

The multi-interlock and check of logical system for 5 MW low power reactor automatic rod

International Nuclear Information System (INIS)

Li Guangjian; Zhao Zengqiao

1992-01-01

The safety and reliability of the logical system for 5 MW LPR automatic rod are improved, because of using multi-interlock and manual check on line. The design character and function of the logical system are introduced

A new high-voltage level-shifting circuit for half-bridge power ICs

International Nuclear Information System (INIS)

Kong Moufu; Chen Xingbi

2013-01-01

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well. (semiconductor integrated circuits)

An evaluation of low-energy x-ray and cobalt-60 irradiations of MOS transistors

International Nuclear Information System (INIS)

Dozier, C.M.; Fleetwood, D.M.

1987-01-01

An evaluation of methodologies for irradiating MOS transistors with low-energy x-ray and Co-60 sources has been performed. The authors find that comparisons of voltage shifts produced by bulk trapped charge and interface states in MOS transistors irradiated using two different low energy x-ray sources (an ARACOR 10 keV W source and an 8 keV Cu source) agree to within better than 30 percent. This quality of agreement is similar in magnitude to that between MOS devices irradiated by different Co-60 sources. In contrast, the measurements indicate that interlaboratory comparisons of ratios of shifts produced by x-ray and Co-60 sources can lead to differences in ratios as large as a factor of --1.7. Improved electron-hole recombination data for oxides is presented. This recombination correction, in conjunction with a correction for interface dose enhancement, is used to predict the ratios of shifts produced by x-ray and Co-60 sources. However, the results show that corrections for electron-hole recombination and interface does enhancement do not, by themselves, adequately predict the field dependent behavior of these transistors

Fuzzy logics acquisition and simulation modules for expert systems to assist operator's decision for nuclear power stations

International Nuclear Information System (INIS)

Averkin, A.A.

1994-01-01

A new type of fuzzy expert system for assisting the operator's decisions in nuclear power plant system in non-standard situations is proposed. This expert system is based on new approaches to fuzzy logics acquisition and to fuzzy logics testing. Fuzzy logics can be generated by a T-norms axiomatic system to choose the most suitable to operator's way of thinking. Then the chosen fuzzy logic is tested by simulation of inference process in expert system. The designed logic is the input of inference module of expert system

A low noise single-transistor transimpedance preamplifier for Fourier-transform mass spectrometry using a T feedback network.

Science.gov (United States)

Lin, Tzu-Yung; Green, Roger J; O'Connor, Peter B

2012-09-01

A novel single-transistor transimpedance preamplifier has been introduced for improving performance in Fourier-transform ion cyclotron resonance (FT-ICR) mass spectrometry. A low noise junction field-effect transistor (JFET), BF862, is used as the main amplification stage of this trans-impedance preamplifier, and a T-shaped feedback network is introduced as both the feedback and the gate biasing solutions. The T feedback network has been studied using an operational amplifier (Op Amp), AD8099. Such a feedback system allows ~100-fold less feedback resistance at a given transimpedance, hence preserving bandwidth, which is beneficial to applications demanding high gain. The single-transistor preamplifier yields a tested transimpedance of ~10(4) Ω (80 dBΩ) in the frequency range between 1 kHz and 1 MHz (mass-to-charge ratio, m/z, of around 180-180k for a 12-T FT-ICR system), with a low power consumption of ~6 mW, which implies that this preamplifier is well suited to a 12-T FT-ICR mass spectrometer. In trading noise performance for higher trans-impedance, an alternative preamplifier design, an AD8099 preamplifier with the T feedback network, has also been studied with a capability of ~10(6) Ω (120 dBΩ) transimpedance in the same frequency range. The resistive components in the T feedback network reported here can be replaced by complex impedances, which allows adaptation of this feedback system to other frequency, transimpedance, and noise characteristics for applications not only in other mass spectrometers, such as Orbitrap, time-of-flight (TOF), and ion trap systems, but also in other charge/current detecting systems such as spectroscopy systems, microscopy systems, optical communication systems, or charge-coupled devices (CCDs).

A parity checker circuit based on microelectromechanical resonator logic elements

KAUST Repository

Hafiz, Md Abdullah Al

2017-01-11

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

A parity checker circuit based on microelectromechanical resonator logic elements

KAUST Repository

Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein

2017-01-01

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

A real time status monitor for transistor bank driver power limit resistor in boost injection kicker power supply

Energy Technology Data Exchange (ETDEWEB)

Mi, J.; Tan, Y.; Zhang, W.

2011-03-28

For years suffering of Booster Injection Kicker transistor bank driver regulator troubleshooting, a new real time monitor system has been developed. A simple and floating circuit has been designed and tested. This circuit monitor system can monitor the driver regulator power limit resistor status in real time and warn machine operator if the power limit resistor changes values. This paper will mainly introduce the power supply and the new designed monitoring system. This real time resistor monitor circuit shows a useful method to monitor some critical parts in the booster pulse power supply. After two years accelerator operation, it shows that this monitor works well. Previously, we spent a lot of time in booster machine trouble shooting. We will reinstall all 4 PCB into Euro Card Standard Chassis when the power supply system will be updated.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

Science.gov (United States)

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Structural Logical Relations

DEFF Research Database (Denmark)

Schürmann, Carsten; Sarnat, Jeffrey

2008-01-01

Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics......, such as Twelf, and yet they are often straightforward in proof assistants with stronger meta-logics. In this paper, we propose structural logical relations as a technique for conducting these proofs in systems with limited meta-logical strength by explicitly representing and reasoning about an auxiliary logic...

Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology

Directory of Open Access Journals (Sweden)

Abbas Asadi Aghbolaghi

2015-07-01

Full Text Available The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP compared to the existing counterparts.

Ultra low power CMOS-based sensor for on-body radiation dose measurements

KAUST Repository

Arsalan, Muhammad

2012-03-01

For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA\\'s 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

Ultra low power CMOS-based sensor for on-body radiation dose measurements

KAUST Repository

Arsalan, Muhammad; Shamim, Atif; Shams, Maitham; Tarr, Nathan Garry; Roy, Langis

2012-01-01

For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA's 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

Controlling the power output of a nuclear reactor with fuzzy logic

NARCIS (Netherlands)

Ruan, D.; Wal, A.J. van der

1998-01-01

The application of fuzzy logic control (FLC) in the domain of nuclear industry presents a tremendous challenge. The main reason for this is the public awareness of the risks of nuclear reactors and the very strict safety regulations in force for nuclear power plants. The very same regulations

Controlling the Power Output of a Nuclear Reactor with Fuzzy Logic

NARCIS (Netherlands)

Ruan, D.; Wal, A.J. van der

1997-01-01

The application of fuzzy logic control (FLC) in the domain of nuclear industry presents a tremendous challenge. The main reason for this is the public awareness of the risks of nuclear reactors and the very strict safety regulations in force for nuclear power plants. The very same regulations

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Frank, H.; Petr, I.

1977-01-01

The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2016-03-01

Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Energy Technology Data Exchange (ETDEWEB)

Curry, M. J. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carroll, M. S. [Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); Carr, S. M. [Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States)

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

Science.gov (United States)

Chen, Dakai; Ladbury Raymond; LaBel, Kenneth; Topper, Alyson; Ladbury, Raymond; Triggs, Brian; Kazmakites, Tony

2012-01-01

We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

International Nuclear Information System (INIS)

Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

Energy Technology Data Exchange (ETDEWEB)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-01-25

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

High-performance silicon nanotube tunneling FET for ultralow-power logic applications

KAUST Repository

Fahad, Hossain M.; Hussain, Muhammad Mustafa

2013-01-01

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

Evaluation of flux-based logic schemes for high-Tc applications

International Nuclear Information System (INIS)

Fleishman, J.; Feld, D.; Xiao, P.; Van Dazer, T.

1991-01-01

This paper presents analyses of three digital logic families that can be made using nonhysteretic Josephson junctions, potentially the only kind of Josephson device realizable with superconductors having high transition temperatures. These logic families utilize magnetic flux-transfer and are characterized by very low power dissipation. Rapid Single Flux Quantum (RSFQ) and Phase Mode logic are both based on pulse propagation. The Quantum Flux Parametron (QFP) logic family is based on current latching. Simulations of RSFQ, Phase-Mode, and QFP logic families using high-T c junction parameters are presented to demonstrate the compatibility of these logic families with the new perovskite superconductors. The operation of these logic families is analyzed and the advantages and disadvantages of each are discussed

High performance printed oxide field-effect transistors processed using photonic curing

Science.gov (United States)

Garlapati, Suresh Kumar; Cadilha Marques, Gabriel; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Baradaran Tahoori, Mehdi; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

2018-06-01

Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

A Fuzzy-Logic Power Management Strategy Based on Markov Random Prediction for Hybrid Energy Storage Systems

Directory of Open Access Journals (Sweden)

Yanzi Wang

2016-01-01

Full Text Available Over the last few years; issues regarding the use of hybrid energy storage systems (HESSs in hybrid electric vehicles have been highlighted by the industry and in academic fields. This paper proposes a fuzzy-logic power management strategy based on Markov random prediction for an active parallel battery-UC HESS. The proposed power management strategy; the inputs for which are the vehicle speed; the current electric power demand and the predicted electric power demand; is used to distribute the electrical power between the battery bank and the UC bank. In this way; the battery bank power is limited to a certain range; and the peak and average charge/discharge power of the battery bank and overall loss incurred by the whole HESS are also reduced. Simulations and scaled-down experimental platforms are constructed to verify the proposed power management strategy. The simulations and experimental results demonstrate the advantages; feasibility and effectiveness of the fuzzy-logic power management strategy based on Markov random prediction.

Characterization of a power bipolar transistor as high-dose dosimeter for 1.9-2.2 MeV electron beams

Energy Technology Data Exchange (ETDEWEB)

Fuochi, P.G., E-mail: fuochi@isof.cnr.i [ISOF-CNR Institute, Via P. Gobetti 101, I-40129, Bologna (Italy); Lavalle, M.; Corda, U. [ISOF-CNR Institute, Via P. Gobetti 101, I-40129, Bologna (Italy); Kuntz, F.; Plumeri, S. [Aerial, Parc d' Innovation Rue Laurent Fries F-67400 Illkirch (France); Gombia, E. [IMEM-CNR Institute, Viale delle Scienze 37 A, Loc. Fontanini, 43010 Parma (Italy)

2010-04-15

Results of the characterization studies on a power bipolar transistor investigated as a possible radiation dosimeter under laboratory condition using electron beams of energies from 2.2 to 8.6 MeV and gamma rays from a {sup 60}Co source and tested in industrial irradiation plants having high-activity {sup 60}Co gamma-source and high-energy, high-power electron beam have previously been reported. The present paper describes recent studies performed on this type of bipolar transistor irradiated with 1.9 and 2.2 MeV electron beams in the dose range 5-50 kGy. Dose response, post-irradiation heat treatment and stability, effects of temperature during irradiation in the range from -104 to +22 deg. C, dependence on temperature during reading in the range 20-50 deg. C, and the difference in response of the transistors irradiated from the plastic side and the copper side are reported. DLTS measurements performed on the irradiated devices to identify the recombination centres introduced by radiation and their dependence on dose and energy of the electron beam are also reported.

Electrical properties of solution-deposited ZnO thin-film transistors by low-temperature annealing.

Science.gov (United States)

Lim, Chul; Oh, Ji Young; Koo, Jae Bon; Park, Chan Woo; Jung, Soon-Won; Na, Bock Soon; Chu, Hye Yong

2014-11-01

Flexible oxide thin-film transistors (Oxide-TFTs) have emerged as next generation transistors because of their applicability in electronic device. In particular, the major driving force behind solution-processed zinc oxide film research is its prospective use in printing for electronics. A low-temperature process to improve the performance of solution-processed n-channel ZnO thin-film transistors (TFTs) fabricated via spin-coating and inkjet-printing is introduced here. ZnO nanoparticles were synthesized using a facile sonochemical method that was slightly modified based on a previously reported method. The influence of the annealing atmosphere on both nanoparticle-based TFT devices fabricated via spin-coating and those created via inkjet printing was investigated. For the inkjet-printed TFTs, the characteristics were improved significantly at an annealing temperature of 150 degrees C. The field effect mobility, V(th), and the on/off current ratios were 3.03 cm2/Vs, -3.3 V, and 10(4), respectively. These results indicate that annealing at 150 degrees C 1 h is sufficient to obtain a mobility (μ(sat)) as high as 3.03 cm2/Vs. Also, the active layer of the solution-based ZnO nanoparticles allowed the production of high-performance TFTs for low-cost, large-area electronics and flexible devices.

Low-frequency 1/f noise in MoS2 transistors: Relative contributions of the channel and contacts

Science.gov (United States)

Renteria, J.; Samnakay, R.; Rumyantsev, S. L.; Jiang, C.; Goli, P.; Shur, M. S.; Balandin, A. A.

2014-04-01

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS2 field-effect transistors revealing the relative contributions of the MoS2 channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS2 transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS2 transistors, are 2 × 1019 eV-1cm-3 and 2.5 × 1020 eV-1cm-3 for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS2 transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS2 and other van der Waals materials.

Ultrafast all-optical arithmetic logic based on hydrogenated amorphous silicon microring resonators

Science.gov (United States)

Gostimirovic, Dusan; Ye, Winnie N.

2016-03-01

For decades, the semiconductor industry has been steadily shrinking transistor sizes to fit more performance into a single silicon-based integrated chip. This technology has become the driving force for advances in education, transportation, and health, among others. However, transistor sizes are quickly approaching their physical limits (channel lengths are now only a few silicon atoms in length), and Moore's law will likely soon be brought to a stand-still despite many unique attempts to keep it going (FinFETs, high-k dielectrics, etc.). This technology must then be pushed further by exploring (almost) entirely new methodologies. Given the explosive growth of optical-based long-haul telecommunications, we look to apply the use of high-speed optics as a substitute to the digital model; where slow, lossy, and noisy metal interconnections act as a major bottleneck to performance. We combine the (nonlinear) optical Kerr effect with a single add-drop microring resonator to perform the fundamental AND-XOR logical operations of a half adder, by all-optical means. This process is also applied to subtraction, higher-order addition, and the realization of an all-optical arithmetic logic unit (ALU). The rings use hydrogenated amorphous silicon as a material with superior nonlinear properties to crystalline silicon, while still maintaining CMOS-compatibility and the many benefits that come with it (low cost, ease of fabrication, etc.). Our method allows for multi-gigabit-per-second data rates while maintaining simplicity and spatial minimalism in design for high-capacity manufacturing potential.

Design, Specification, and Synthesis of Aircraft Electric Power Systems Control Logic

Science.gov (United States)

Xu, Huan

Cyber-physical systems integrate computation, networking, and physical processes. Substantial research challenges exist in the design and verification of such large-scale, distributed sensing, actuation, and control systems. Rapidly improving technology and recent advances in control theory, networked systems, and computer science give us the opportunity to drastically improve our approach to integrated flow of information and cooperative behavior. Current systems rely on text-based specifications and manual design. Using new technology advances, we can create easier, more efficient, and cheaper ways of developing these control systems. This thesis will focus on design considerations for system topologies, ways to formally and automatically specify requirements, and methods to synthesize reactive control protocols, all within the context of an aircraft electric power system as a representative application area. This thesis consists of three complementary parts: synthesis, specification, and design. The first section focuses on the synthesis of central and distributed reactive controllers for an aircraft elec- tric power system. This approach incorporates methodologies from computer science and control. The resulting controllers are correct by construction with respect to system requirements, which are formulated using the specification language of linear temporal logic (LTL). The second section addresses how to formally specify requirements and introduces a domain-specific language for electric power systems. A software tool automatically converts high-level requirements into LTL and synthesizes a controller. The final sections focus on design space exploration. A design methodology is proposed that uses mixed-integer linear programming to obtain candidate topologies, which are then used to synthesize controllers. The discrete-time control logic is then verified in real-time by two methods: hardware and simulation. Finally, the problem of partial observability and

High-performance silicon nanotube tunneling FET for ultralow-power logic applications

KAUST Repository

Fahad, Hossain M.

2013-03-01

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET\\'s effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

Energy Technology Data Exchange (ETDEWEB)

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

Science.gov (United States)

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

A parity checker circuit based on microelectromechanical resonator logic elements

Energy Technology Data Exchange (ETDEWEB)

Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)

2017-03-03

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.

What are Institutional Logics

OpenAIRE

Berg Johansen, Christina; Bock Waldorff, Susanne

2015-01-01

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guided by institutional logics, as well as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to...

Pseudo-diode based on protonic/electronic hybrid oxide transistor

Science.gov (United States)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

International Nuclear Information System (INIS)

But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

2014-01-01

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm 2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm 2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm 2 . The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm 2 to ∼5 kW/cm 2 )

What are Institutional Logics

DEFF Research Database (Denmark)

Berg Johansen, Christina; Waldorff, Susanne Boch

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...

A New Control Strategy Based Multi Converter UPQC Using Fuzzy Logic Controller to Improve the Power Quality Issues

Directory of Open Access Journals (Sweden)

Chandra Babu Paduchuri

2014-01-01

Full Text Available A design of multiconverter unified power quality conditioner to improve the power quality issues is presents in this paper. Modified SRF theory and fuzzy logic controller technique are incorporated in this modelling. This newly designed controller is connected to a source in order to compensate voltage and current in the two feeders. The expanded concept of UPQC is multi converter-UPQC; this system has two series voltage source converter (VSC and one shunt VSC connected back to back. In the proposed system, the power can be conveyed from one feeder to another in order to mitigate the voltage sag, swell, interruption and transient response of the system. The control strategies of multi converter-UPQC are designed based on the modified synchronous reference frame theory with fuzzy logic controller. The transient response of the fuzzy logic controller in dc-link voltage controller will be very fast. The relevant simulation and compensation performance analysis of multi converter-UPQC with fuzzy logic controller is performed using MATLAB/Simulink software.

The concept of biologically motivated time-pulse information processing for design and construction of multifunctional devices of neural logic

Science.gov (United States)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Sholohov, V. I.

2004-04-01

On the basis of the analysis of advanced approaches and optoelectronic systems for realization of various logics: two-valued, multi-valued, neural, continuous and others the biologically motivated time-pulse conception for building of multifunctional reconfigurable universal elements with programmable tuning for neurobiologic is grounded. The concept consists in usage of preliminary conversion of multi-level or continuous optic 2D signals into durations of time intervals (the conversion to a temporal area) and further use of time-pulse two-level digital signals that allows to ensure fast tuning to a required function of two-valued, multi-valued and other logics. It is shown that optoelectronic pulse-phase and pulse-width modulators (PPM and PWM) are the base elements for that. Time-pulse coding universal elements for matrix two-valued and multi-valued logics and structural-functional design of universal time-pulse coding elements for neural (continuous) logic are considered in the article. PPMs realized on 1.5μm technology CMOS transistors are considered. The PPMs have parameters: the input photocurrent range is 10nA...10μA the conversion period is 10μs...1ms the conversion relative error is 0.1...1%; the conversion law is ramp; the supply voltage is 3V and the power consumption is 83μW. The small power consumption of such PPMs enables successfully their integration in 2Darray with size of 128x128 elements and more and productivity equals 1...10 Giga continuous logic operations per sec.

Computation On dP Type power System Stabilizer Using Fuzzy Logic

International Nuclear Information System (INIS)

Iskandar, M.A.; Irwan, R.; Husdi; Riza; Mardhana, E.; Triputranto, A.

1997-01-01

Power system stabilizers (PSS) are widely applied in power generators to damp power oscillation caused by certain disturbances in order to increase the power supply capacity. PSS design is often suffered from the difficulty on setting periodically its parameters, which are gain and compensators, in order to have an optimal damping characteristic. This paper proposes a methode to determine parameters of dP type PSS by implementing fuzzy logic rules in a computer program,to obtain the appropriate characteristics of synchronous torque and damping torque. PSS with the calculated parameters is investigated on a simulation using a non-linear electric power system of a thermal generator connected to infinite bus system model. Simulation results show that great improvement in damping characteristic and enhancement of stability margin of electric power system are obtained by using the proposed PSS

Self-powered 'AND' logic circuit of dynamic type with positive safety and application of said 'AND' circuit

International Nuclear Information System (INIS)

Lefebvre, Claude; Therond, J.P.

1974-01-01

The present invention relates to a self-powered 'AND' logic circuit of dynamic type with positive safety, which delivers on duty operation an output signal equal to the logic product of the input logic signals. The invention relates also to the use of said 'AND' logic circuits in developing n/m logics also of dynamic types with positive safety, delivering on duty operation a zero valued signal when, at least n of the m input signals have the value zero. This type of logics can be inserted in nuclear reactor protection systems; when the value of the reactor operating physical characteristics go out of the safety margins, or true trouble affects 'AND' circuits the value of the output signal is zero, that triggers off the safety absorber drap, for instance [fr

Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

International Nuclear Information System (INIS)

Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

1999-01-01

We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

DEFF Research Database (Denmark)

Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

2002-01-01

is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more......This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

Low-frequency 1/f noise in MoS2 transistors: Relative contributions of the channel and contacts

International Nuclear Information System (INIS)

Renteria, J.; Jiang, C.; Samnakay, R.; Rumyantsev, S. L.; Goli, P.; Balandin, A. A.; Shur, M. S.

2014-01-01

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS 2 field-effect transistors revealing the relative contributions of the MoS 2 channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS 2 transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS 2 transistors, are 2 × 10 19  eV −1 cm −3 and 2.5 × 10 20  eV −1 cm −3 for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS 2 transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS 2 and other van der Waals materials

Effect of 50 MeV Li3+ ion irradiation on electrical characteristics of high speed NPN power transistor

International Nuclear Information System (INIS)

Dinesh, C.M.; Ramani; Radhakrishna, M.C.; Dutt, R.N.; Khan, S.A.; Kanjilal, D.

2008-01-01

Silicon NPN overlay RF power high speed commercial bipolar junction transistors (BJTs) find applications in military, space and communication equipments. Here we report the effect of 50 MeV Li 3+ ion irradiation in the fluence range 1 x 10 11 -1.8 x 10 12 ions cm -2 on NPN power transistor. The range (R), electronic energy loss (S e ), nuclear energy loss (S n ), total ionizing dose (TID) and total displacement damage (D d ) in the silicon target are calculated from TRIM Monte Carlo Code. Output resistance is 3.568 x 10 4 Ω for unirradiated device and it increases to 6 x 10 7 Ω as the fluence is increased from 1 x 10 11 to 1.8 x 10 12 ions cm -2 . The capacitance of the emitter-base junction of the transistor decreases and dielectric loss of the emitter-base junction increases with increase in ion fluence. The built in voltage of the unirradiated sample is 0.5 V and it shifts to 0.4 V after irradiation at fluence of 1.8 x 10 12 ions cm -2 and the corresponding doping density reduced to 5.758 x 10 16 cm -3 . The charge carrier removal rate varies linearly with the increase in ion fluence

Cooperation in multicultural negotiations: How the cultures of people with low and high power interact.

Science.gov (United States)

Kopelman, Shirli; Hardin, Ashley E; Myers, Christopher G; Tost, Leigh Plunkett

2016-05-01

This study examined whether the cultures of low- and high-power negotiators interact to influence cooperative behavior of low-power negotiators. Managers from 4 different cultural groups (Germany, Hong Kong, Israel, and the United States) negotiated face-to-face in a simulated power-asymmetric commons dilemma. Results supported an interaction effect in which cooperation of people with lower power was influenced by both their culture and the culture of the person with higher power. In particular, in a multicultural setting, low-power managers from Hong Kong, a vertical-collectivist culture emphasizing power differences and group alignment, adjusted their cooperation depending on the culture of the high-power manager with whom they interacted. This study contributes to understanding how culture shapes behavior of people with relatively low power, illustrates how a logic of appropriateness informs cooperation, and highlights the importance of studying multicultural social interactions in the context of negotiations, work teams, and global leadership. (PsycINFO Database Record (c) 2016 APA, all rights reserved).

Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer.

Science.gov (United States)

Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

2017-04-20

Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO₂ have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm² at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 10⁵. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices.

Low-Voltage Solution-Processed Hybrid Light-Emitting Transistors.

Science.gov (United States)

Chaudhry, Mujeeb Ullah; Tetzner, Kornelius; Lin, Yen-Hung; Nam, Sungho; Pearson, Christopher; Groves, Chris; Petty, Michael C; Anthopoulos, Thomas D; Bradley, Donal D C

2018-05-21

We report the development of low operating voltages in inorganic-organic hybrid light-emitting transistors (HLETs) based on a solution-processed ZrO x gate dielectric and a hybrid multilayer channel consisting of the heterojunction In 2 O 3 /ZnO and the organic polymer "Super Yellow" acting as n- and p-channel/emissive layers, respectively. Resulting HLETs operate at the lowest voltages reported to-date (<10 V) and combine high electron mobility (22 cm 2 /(V s)) with appreciable current on/off ratios (≈10 3 ) and an external quantum efficiency of 2 × 10 -2 % at 700 cd/m 2 . The charge injection, transport, and recombination mechanisms within this HLET architecture are discussed, and prospects for further performance enhancement are considered.

Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)

Science.gov (United States)

Karmakar, Supriya

2014-10-01

This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.

Neuromorphic transistor achieved by redox reaction of WO3 thin film

Science.gov (United States)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

Research on fault diagnosis of nuclear power plants based on genetic algorithms and fuzzy logic

International Nuclear Information System (INIS)

Zhou Yangping; Zhao Bingquan

2001-01-01

Based on genetic algorithms and fuzzy logic and using expert knowledge, mini-knowledge tree model and standard signals from simulator, a new fuzzy-genetic method is developed to fault diagnosis in nuclear power plants. A new replacement method of genetic algorithms is adopted. Fuzzy logic is used to calculate the fitness of the strings in genetic algorithms. Experiments on the simulator show it can deal with the uncertainty and the fuzzy factor

Low-resistance gateless high electron mobility transistors using three-dimensional inverted pyramidal AlGaN/GaN surfaces

International Nuclear Information System (INIS)

So, Hongyun; Senesky, Debbie G.

2016-01-01

In this letter, three-dimensional gateless AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated with 54% reduction in electrical resistance and 73% increase in surface area compared with conventional gateless HEMTs on planar substrates. Inverted pyramidal AlGaN/GaN surfaces were microfabricated using potassium hydroxide etched silicon with exposed (111) surfaces and metal-organic chemical vapor deposition of coherent AlGaN/GaN thin films. In addition, electrical characterization of the devices showed that a combination of series and parallel connections of the highly conductive two-dimensional electron gas along the pyramidal geometry resulted in a significant reduction in electrical resistance at both room and high temperatures (up to 300 °C). This three-dimensional HEMT architecture can be leveraged to realize low-power and reliable power electronics, as well as harsh environment sensors with increased surface area

Low-resistance gateless high electron mobility transistors using three-dimensional inverted pyramidal AlGaN/GaN surfaces

Energy Technology Data Exchange (ETDEWEB)

So, Hongyun, E-mail: hyso@stanford.edu [Department of Aeronautics and Astronautics, Stanford University, Stanford, California 94305 (United States); Senesky, Debbie G. [Department of Aeronautics and Astronautics, Stanford University, Stanford, California 94305 (United States); Department of Electrical Engineering, Stanford University, Stanford, California 94305 (United States)

2016-01-04

In this letter, three-dimensional gateless AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated with 54% reduction in electrical resistance and 73% increase in surface area compared with conventional gateless HEMTs on planar substrates. Inverted pyramidal AlGaN/GaN surfaces were microfabricated using potassium hydroxide etched silicon with exposed (111) surfaces and metal-organic chemical vapor deposition of coherent AlGaN/GaN thin films. In addition, electrical characterization of the devices showed that a combination of series and parallel connections of the highly conductive two-dimensional electron gas along the pyramidal geometry resulted in a significant reduction in electrical resistance at both room and high temperatures (up to 300 °C). This three-dimensional HEMT architecture can be leveraged to realize low-power and reliable power electronics, as well as harsh environment sensors with increased surface area.

Design, implementation and performance comparison of multiplier topologies in power-delay space

Directory of Open Access Journals (Sweden)

Mansi Jhamb

2016-03-01

Full Text Available With the advancements in the semiconductor industry, designing a high performance processor is a prime concern. Multiplier is one of the most crucial parts in almost every digital signal processing applications. This paper addresses the implementation of an 8-bit multiplier design employing CMOS full adder, full adder using Double Pass Transistor (DPL and multioutput carry Lookahead logic (CLA. DPL adder avoids the noise margin problem and speed degradation at low value of supply voltages associated with complementary pass transistor (CPL logic circuits. Multioutput carry lookahead adder leads to significant improvement in the speed of the overall circuitry. The investigation is carried out with simulation runs on HSPICE environment using 90 nm process technology at 25 °C. Finally, the design guidelines are derived to select the most suitable topology for the desired applications. Investigation reveals that multiplier design using multioutput carry lookahead adder proves to be more speed efficient in comparison with the other two considered design strategies.

Peak Power Control with an Energy Management System

Science.gov (United States)

2013-03-01

EMS. .....................18  Figure 17.  Circuit schematic implemented in the Simulink model. ..................................18  Figure 18.  The...21  Figure 20.  The non-critical load block implementation ...Modulation SCR Silicon Controller Rectifier SDC Student Design Center TTL Transistor Transistor Logic USB Universal Serial Bus VHDL VHSIC Hardware

Design of a fuzzy logic based controller for neutron power regulation

International Nuclear Information System (INIS)

Velez D, D.

2000-01-01

This work presents a fuzzy logic controller design for neutron power control, from its source to its full power level, applied to a nuclear reactor model. First, we present the basic definitions on fuzzy sets as generalized definitions of the crisp (non fuzzy) set theory. Likewise, we define the basic operations on fuzzy sets (complement, union, and intersection), and the operations on fuzzy relations such as projection and cylindrical extension operations. Furthermore, some concepts of the fuzzy control theory, such as the main modules of the typical fuzzy controller structure and its internal variables, are defined. After the knowledge base is obtained by simulation of the reactor behavior, where the controlled system is modeled by a simple nonlinear reactor model, this model is used to infer a set of fuzzy rules for the reactor response to different insertions of reactivity. The reduction of the response time, using fuzzy rule based controllers on this reactor, is possible by adjusting the output membership functions, by selecting fuzzy rule sets, or by increasing the number of crisp inputs to the fuzzy controller. System characteristics, such as number of rules, response times, and safety parameter values, were considered in the evaluation of each controller merits. Different fuzzy controllers are designed to attain the desired power level, to maintain a constant level for long periods of time, and to keep the reactor away from a shutdown condition. The basic differences among the controllers are the number of crisp inputs and the novel implementation of a crisp power level-based selection of different sets of output membership functions. Simulation results highlight, mainly: (1) A decrease of the response variations at low power level, and (2) a decrease in the time required to attain the desired neutron power. Finally, we present a comparative study of different fuzzy control algorithms applied to a nuclear model. (Author)

On the choice of a head element for low-noise bipolar transistor amplifier

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

The measurement results of equivalent noise charge (ENC) for KT382 transistor depending on detector capacity, formation duration and collector current are given. It is shown that the measurement results for this transistor in good agreement with calculations according to the noise model, time-consuming ENC measurements can be replaced by preliminary transistor rejection according to the distributed base resistance, current gain and simple calculations. In applications in the field of nuclear electronics the KT382 transistor enables to attain the same noise parameters as NE578, NE021 transistors (Japan) and it can be recommended for using as a head element of amplifiers

Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

Directory of Open Access Journals (Sweden)

Ching-Hwa Cheng

2011-09-01

Full Text Available The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism.

Protonic transistors from thin reflecting films

Energy Technology Data Exchange (ETDEWEB)

Ordinario, David D.; Phan, Long; Jocson, Jonah-Micah [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Nguyen, Tam [Department of Chemistry, University of California, Irvine, California 92697 (United States); Gorodetsky, Alon A., E-mail: alon.gorodetsky@uci.edu [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Department of Chemistry, University of California, Irvine, California 92697 (United States)

2015-01-01

Ionic transistors from organic and biological materials hold great promise for bioelectronics applications. Thus, much research effort has focused on optimizing the performance of these devices. Herein, we experimentally validate a straightforward strategy for enhancing the high to low current ratios of protein-based protonic transistors. Upon reducing the thickness of the transistors’ active layers, we increase their high to low current ratios 2-fold while leaving the other figures of merit unchanged. The measured ratio of 3.3 is comparable to the best values found for analogous devices. These findings underscore the importance of the active layer geometry for optimum protonic transistor functionality.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Science.gov (United States)

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Spintronic logic design methodology based on spin Hall effect–driven magnetic tunnel junctions

International Nuclear Information System (INIS)

Kang, Wang; Zhang, Youguang; Zhao, Weisheng; Wang, Zhaohao; Klein, Jacques-Olivier; Lv, Weifeng

2016-01-01

Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau–Lifshitz–Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing. (paper)

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Transistor Effect in Improperly Connected Transistors.

Science.gov (United States)

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

A novel GUI modeled fuzzy logic controller for a solar powered energy utilization scheme

International Nuclear Information System (INIS)

Altas, I. H.; Sharaf, A. M.

2007-01-01

Photovoltaic PVA-solar powered electrical systems comprise different components and subsystems to be controlled separately. Since the generated solar power is dependant on uncontrollable environmental conditions, it requires extra caution to design controllers that handle unpredictable events and maintain efficient load matching power. In this study, a photovoltaic (PV) solar array model is developed for Matlab/Simulink GUI environment and controlled using a fuzzy logic controller (FLC), which is also developed for GUI environment. The FLC is also used to control the DC load bus voltage at constant value as well as controlling the speed of a PMDC motor as one of the loads being fed. The FLC controller designed using the Matlab/Simuling GUI environment has flexible design criteria's so that it can easily be modified and extended for controlling different systems. The proposed FLC is used in three different parts of the PVA stand alone utilization scheme here. One of these parts is the speed control of the PMDC load, one of the other parts is controlling the DC load bus voltage, and the third part is the maximum power point (MPPT) tracking control, which is used to operate the PVA at its available maximum power as the solar insolation and ambient temperature change. This paper presents a study of a standalone Photovoltaic energy utilization system feeding a DC and AC hybrid electric load and is fully controlled by a novel and simple on-line fuzzy logic based dynamic search, detection and tracking controller that ensures maximum power point operation under excursions in Solar Insolation, Ambient temperature and electric load variations. The maximum power point MPP-Search and Detection algorithm is fully dynamic in nature and operates without any required direct measurement or forecasted PV array information about the irradiation and temperature. An added Search sensitivity measure is defined and also used in the MPP search algorithm to sense and dynamic response for

Fuzzy Logic Based Controller for a Grid-Connected Solid Oxide Fuel Cell Power Plant.

Science.gov (United States)

Chatterjee, Kalyan; Shankar, Ravi; Kumar, Amit

2014-10-01

This paper describes a mathematical model of a solid oxide fuel cell (SOFC) power plant integrated in a multimachine power system. The utilization factor of a fuel stack maintains steady state by tuning the fuel valve in the fuel processor at a rate proportional to a current drawn from the fuel stack. A suitable fuzzy logic control is used for the overall system, its objective being controlling the current drawn by the power conditioning unit and meet a desirable output power demand. The proposed control scheme is verified through computer simulations.

High-power microwave LDMOS transistors for wireless data transmission technologies (Review)

International Nuclear Information System (INIS)

Kuznetsov, E. V.; Shemyakin, A. V.

2010-01-01

The fields of the application, structure, fabrication, and packaging technology of high-power microwave LDMOS transistors and the main advantages of these devices were analyzed. Basic physical parameters and some technology factors were matched for optimum device operation. Solid-state microwave electronics has been actively developed for the last 10-15 years. Simultaneously with improvement of old devices, new devices and structures are actively being adopted and developed and new semiconductor materials are being commercialized. Microwave LDMOS technology is in demand in such fields as avionics, civil and military radars, repeaters, base stations of cellular communication systems, television and broadcasting transmitters, and transceivers for high-speed wireless computer networks (promising Wi-Fi and Wi-Max standards).

Performance enhancement of a heterojunction bipolar transistor (HBT) by two-step passivation

International Nuclear Information System (INIS)

Fu, S.-I.; Lai, P.-H.; Tsai, Y.-Y.; Hung, C.-W.; Yen, C.-H.; Cheng, S.-Y.; Liu, W.-C.

2006-01-01

An interesting two-step passivation (with ledge structure and sulphide based chemical treatment) on base surface, for the first time, is demonstrated to study the temperature-dependent DC characteristics and noise performance of an InGaP/GaAs heterojunction bipolar transistor (HBT). Improved transistor behaviors on maximum current gain β max , offset voltage ΔV CE , and emitter size effect are obtained by using the two-step passivation. Moreover, the device with the two-step passivation exhibits relatively temperature-independent and improved thermal stable performances as the temperature is increased. Therefore, the two-step passivationed device can be used for high-temperature and low-power electronics applications

A low-power digital frequency divider for system-on-a-chip applications

KAUST Repository

Omran, Hesham

2011-08-01

In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.

Integrated-Circuit Controller For Brushless dc Motor

Science.gov (United States)

Le, Dong Tuan

1994-01-01

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Complex programmable logic device based alarm sequencer for nuclear power plants

International Nuclear Information System (INIS)

Khedkar, Ravindra; Solomon, J. Selva; KrishnaKumar, B.

2001-01-01

Complex Programmable Logic Device based Alarm Sequencer is an instrument, which detects alarms, memorizes them and displays the sequences of occurrence of alarms. It caters to sixteen alarm signals and distinguishes the sequence among any two alarms with a time resolution of 1 ms. The system described has been designed for continuous operation in process plants, nuclear power plants etc. The system has been tested and found to be working satisfactorily. (author)

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

Science.gov (United States)

2013-05-01

The largest company in the world is now a technology company (Apple Inc.) whose products are all enabled by transistors [2]. Any changes, for better...increasing standby battery life. The nVidia Tegra 3 mobile processor for applications in smartphones and tablets contains five cores: one low power...white paper, NVIDIA , 2011. 14. W. G. Vandenberghe, B. Sorée, W. Magnus, G. Groeseneken, and M. V. Fischetti, “Impact of field-induced quantum

Low-threshold amplitude discriminator circuit with tunnel diode and two transistors in differential connection

International Nuclear Information System (INIS)

Ryba, J.; Volny, J.

1973-01-01

The connection is designed of a low-threshold amplitude discriminator and a tunnel diode with two transistors in differential connection. The discriminator is by its simple connection, its low consumption and high temperature stability suitable especially for portable radiation detectors. The tunnel diode is connected by one pole to a collector clamp and by the other to the supply voltage. A suitable resistor is connected in parallel with the tunnel diode to meet demands for higher sensitivity. (Z.S.)

A low-power microcontroller in a 40-nm CMOS using charge recycling

NARCIS (Netherlands)

Blutman, K.; Kapoor, A.; Majumdar, A.; Martinez, J.G.; Echeverri, J.; Sevat, L.; Van Der Wel, A.P.; Fatemi, H.; Makinwa, K.A.A; De Gyvez, J.P.

2017-01-01

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its

Solution-processable precursor route for fabricating ultrathin silica film for high performance and low voltage organic transistors

Institute of Scientific and Technical Information of China (English)

Shujing Guo; Liqiang Li; Zhongwu Wang; Zeyang Xu; Shuguang Wang; Kunjie Wu; Shufeng Chen; Zongbo Zhang; Caihong Xu; Wenfeng Qiu

2017-01-01

Silica is one of the most commonly used materials for dielectric layer in organic thin-film transistors due to its excellent stability,excellent electrical properties,mature preparation process,and good compatibility with organic semiconductors.However,most of conventional preparation methods for silica film are generally performed at high temperature and/or high vacuum.In this paper,we introduce a simple solution spin-coating method to fabricate silica thin film from precursor route,which possesses a low leakage current,high capacitance,and low surface roughness.The silica thin film can be produced in the condition of low temperature and atmospheric environment.To meet various demands,the thickness of film can be adjusted by means of preparation conditions such as the speed of spin-coating and the concentration of solution.The p-type and n-type organic field effect transistors fabricated by using this film as gate electrodes exhibit excellent electrical performance including low voltage and high performance.This method shows great potential for industrialization owing to its characteristic of low consumption and energy saving,time-saving and easy to operate.

The EU as a global ecological power: The logics of market integration

International Nuclear Information System (INIS)

Laurent, Eloi; Le Cacheux, Jacques

2010-05-01

In this paper, we try to show how the EU became a global ecological power, i.e. a power that influences environmental policies throughout the world. While the existing literature stresses the significance of normative power, regulatory politics and multi-level governance in this process, we highlight the importance of what we call the logics of market integration. By that we mean the decisive role of Single market integration in fostering convergence of environmental policies at the European level as well as in extending European influence at the global level. We illustrate our approach with the case of climate policy, detailing the EU's influence on economic instruments developed worldwide to mitigate climate change. (authors)

Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts

Energy Technology Data Exchange (ETDEWEB)

Renteria, J.; Jiang, C. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Samnakay, R. [Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Rumyantsev, S. L. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States); Ioffe Physical-Technical Institute, St. Petersburg 194021 (Russian Federation); Goli, P.; Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Shur, M. S. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States)

2014-04-14

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2 × 10{sup 19} eV{sup −1}cm{sup −3} and 2.5 × 10{sup 20} eV{sup −1}cm{sup −3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.

Logic and structure

CERN Document Server

Dalen, Dirk

1983-01-01

A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...

The Organic Power Transistor: Roll-to-Roll Manufacture, Thermal Behavior, and Power Handling When Driving Printed Electronics

DEFF Research Database (Denmark)

Pastorelli, Francesco; Schmidt, Thomas Mikael; Hösel, Markus

2016-01-01

to drive large currents while handling the thermal aspects in operation together with other organic printed electronics technologies such as large area organic photovoltaics (OPV)[2] and large area electrochromic displays (EC).[3] We find especially that an elevated operational temperature is beneficial...... with respect to both transconductance and on/off ratio. We achieve high currents of up to 45mA at a temperature of 80 C with an on/ off ratio of 100 which is sufficient to drive large area organic electronics such as an EC device powered by OPV devices that we also demonstrate. Finally, we observe......We present flexible organic power transistors prepared by fast (20mmin1) roll-to-roll (R2R) flexographic printing[1] of the drain (D) and source (S) electrode structures directly on polyester foil. The devices have top gate architecture and were completed by spin coating or slot-die coating...

Sensitivity of encapsulated diamond-protein transistor renewed by low temperature hydrogen plasma

Czech Academy of Sciences Publication Activity Database

Krátká, Marie; Neykova, Neda; Ukraintsev, Egor; Kromka, Alexander; Rezek, Bohuslav

2013-01-01

Roč. 8, č. 2 (2013), s. 1598-1608 ISSN 1452-3981 R&D Projects: GA ČR(CZ) GBP108/12/G108; GA ČR GAP108/12/0996; GA ČR GD202/09/H041 Institutional support: RVO:68378271 Keywords : nanocrystalline diamond * solution-gated field-effect transistor * low temperature hydrogen termination * proteins * encapsulation Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 1.956, year: 2013 http://www.electrochemsci.org/list13.htm#current

Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors

NARCIS (Netherlands)

Nenadovic, N.

2004-01-01

In this thesis, research is focused on the investigation of electrothermal effects in high-speed silicon transistors. At high current levels the power dissipation in these devices can lead to heating of both the device itself and the adjacent devices. In advanced transistors these effects are

Improved transistorized AC motor controller for battery powered urban electric passenger vehicles

Science.gov (United States)

Peak, S. C.

1982-01-01

An ac motor controller for an induction motor electric vehicle drive system was designed, fabricated, tested, evaluated, and cost analyzed. A vehicle performance analysis was done to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of ac motor and ac controller requirements. The power inverter is a three-phase bridge using power Darlington transistors. The induction motor was optimized for use with an inverter power source. The drive system has a constant torque output to base motor speed and a constant horsepower output to maximum speed. A gear shifting transmission is not required. The ac controller was scaled from the base 20 hp (41 hp peak) at 108 volts dec to an expanded horsepower and battery voltage range. Motor reversal was accomplished by electronic reversal of the inverter phase sequence. The ac controller can also be used as a boost chopper battery charger. The drive system was tested on a dynamometer and results are presented. The current-controlled pulse width modulation control scheme yielded improved motor current waveforms. The ac controller favors a higher system voltage.

Power Conversion Efficiency of AlGaAs/GaAs Schottky Diode for Low-Power On-Chip Rectenna Device Application

International Nuclear Information System (INIS)

Mustafa, Farahiyah; Hashim, Abdul Manaf; Rahman, Shaharin Fadzli Abd; Osman, Mohd Nizam

2011-01-01

A Schottky diode has been designed and fabricated on n-AlGaAs/GaAs high-electron-mobility-transistor (HEMT) structure. Current-voltage (I-V) measurements show good device rectification with a Schottky barrier height of 0.4349 eV for Ni/Au metallization. The differences of Schottky barrier height from theoretical value are due to the fabrication process and smaller contact area. The RF signals up to 1 GHz are well rectified by the fabricated Schottky diodes and stable DC output voltage is obtained. Power conversion efficiency up to 50% is obtained at 1 GHz with series connection between diode and load. The fabricated the n-AlGaAs/GaAs Schottky diode provide conduit for breakthrough designs for ultra-low power on-chip rectenna device technology to be integrated in nanosystems.

Enhanced low dose rate sensitivity (ELDRS) in a voltage comparator which only utilizes complementary vertical NPN and PNP transistors

International Nuclear Information System (INIS)

Krieg, J.F.; Titus, J.L.; Emily, D.; Gehlhausen, M.; Swonger, J.; Platteter, D.

1999-01-01

For the first time, enhanced low dose rate sensitivity (ELDRS) is reported in a vertical bipolar process. A radiation hardness assurance (RHA) test method was successfully demonstrated on a linear circuit, the HS139RH quad comparator, and its discrete transistor elements. This circuit only uses vertical NPN and PNP transistors. Radiation tests on the HS139RH were performed at 25 C using dose rates of 50 rd(Si)/s, 100 mrd(Si)/s and 10 mrd(Si)/s, and at 100 C using a dose rate of 10 rd(Si)/s. Tests at dose rates of 50 rd(Si)/s at 25 C and 10 rd(Si)/s at 100 C were performed on discrete vertical NPN and PNP transistor elements which comprise the HS139RH. Transistor and circuit responses were evaluated. The die's passivation overcoat layers were varied to examine the effect of removing a nitride layer and thinning a deposited SiO 2 (silox) layer

First-Order Hybrid Logic

DEFF Research Database (Denmark)

Braüner, Torben

2011-01-01

Hybrid logic is an extension of modal logic which allows us to refer explicitly to points of the model in the syntax of formulas. It is easy to justify interest in hybrid logic on applied grounds, with the usefulness of the additional expressive power. For example, when reasoning about time one...... often wants to build up a series of assertions about what happens at a particular instant, and standard modal formalisms do not allow this. What is less obvious is that the route hybrid logic takes to overcome this problem often actually improves the behaviour of the underlying modal formalism....... For example, it becomes far simpler to formulate proof-systems for hybrid logic, and completeness results can be proved of a generality that is simply not available in modal logic. That is, hybridization is a systematic way of remedying a number of known deficiencies of modal logic. First-order hybrid logic...

Improvement in the performance of graphene nanoribbon p-i-n tunneling field effect transistors by applying lightly doped profile on drain region

Science.gov (United States)

Naderi, Ali

2017-12-01

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrödinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain-source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

Science.gov (United States)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Electrical pulse burnout of transistors in intense ionizing radiation

International Nuclear Information System (INIS)

Hartman, E.F.; Evans, D.C.

1975-01-01

Tests examining possible synergistic effects of electrical pulses and ionizing radiation on transistors were performed and energy/power thresholds for transistor burnout determined. The effect of ionizing radiation on burnout thresholds was found to be minimal, indicating that electrical pulse testing in the absence of radiation produces burnout-threshold results which are applicable to IEMP studies. The conditions of ionized transistor junctions and radiation induced current surges at semiconductor device terminals are inherent in IEMP studies of electrical circuits

Design and Simulation of a 6-Bit Successive-Approximation ADC Using Modeled Organic Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Huyen Thanh Pham

2016-01-01

Full Text Available We have demonstrated a method for using proper models of pentacene P-channel and fullerene N-channel thin-film transistors (TFTs in order to design and simulate organic integrated circuits. Initially, the transistors were fabricated, and we measured their main physical and electrical parameters. Then, these organic TFTs (OTFTs were modeled with support of an organic process design kit (OPDK added in Cadence. The key specifications of the modeled elements were extracted from measured data, whereas the fitting ones were elected to replicate experimental curves. The simulating process proves that frequency responses of the TFTs cover all biosignal frequency ranges; hence, it is reasonable to deploy the elements to design integrated circuits used in biomedical applications. Complying with complementary rules, the organic circuits work properly, including logic gates, flip-flops, comparators, and analog-to-digital converters (ADCs as well. The proposed successive-approximation-register (SAR ADC consumes a power of 883.7 µW and achieves an ENOB of 5.05 bits, a SNR of 32.17 dB at a supply voltage of 10 V, and a sampling frequency of about 2 KHz.

Organic semiconductors for organic field-effect transistors

International Nuclear Information System (INIS)

Yamashita, Yoshiro

2009-01-01

The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

Organic semiconductors for organic field-effect transistors

Directory of Open Access Journals (Sweden)

Yoshiro Yamashita

2009-01-01

Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic

Energy Technology Data Exchange (ETDEWEB)

Du Rui; Dai Yang; Chen Yanling; Yang Fuhua, E-mail: ddrr@semi.ac.c [Research Center of Semiconductor Integration, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-03-15

A voltage-controlled ring oscillator (VCO) based on a full enhancement-mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) logic is proposed. An enhancement-mode HEMT (E-HEMT) is fabricated, whose threshold is demonstrated to be 10 mV. The model of the E-HEMT is established and used in the SPICE simulation of the VCO. The result proves that the full E-HEMT logic technology can be applied to the VCO. And compared with the HEMT DCFL technology, the complexity of our fabrication process is reduced and the reliability is improved.

The total dose effects on the 1/f noise of deep submicron CMOS transistors

International Nuclear Information System (INIS)

Hu Rongbin; Wang Yuxin; Lu Wu

2014-01-01

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

Self-assembled monolayer exchange reactions as a tool for channel interface engineering in low-voltage organic thin-film transistors.

Science.gov (United States)

Lenz, Thomas; Schmaltz, Thomas; Novak, Michael; Halik, Marcus

2012-10-02

In this work, we compared the kinetics of monolayer self-assembly long-chained carboxylic acids and phosphonic acids on thin aluminum oxide surfaces and investigated their dielectric properties in capacitors and low-voltage organic thin-film transistors. Phosphonic acid anchor groups tend to substitute carboxylic acid molecules on aluminum oxide surfaces and thus allow the formation of mixed or fully exchanged monolayers. With different alkyl chain substituents (n-alkyl or fluorinated alkyl chains), the exchange reaction can be monitored as a function of time by static contact angle measurements. The threshold voltage in α,α'-dihexyl-sexithiophene thin-film transistors composed of such mixed layer dielectrics correlates with the exchange progress and can be tuned from negative to positive values or vice versa depending on the dipole moment of the alkyl chain substituents. The change in the dipole moment with increasing exchange time also shifts the capacitance of these devices. The rate constants for exchange reactions determined by the time-dependent shift of static contact angle, threshold voltage, and capacitance exhibit virtually the same value thus proving the exchange kinetics to be highly controllable. In general, the exchange approach is a powerful tool in interface engineering, displaying a great potential for tailoring of device characteristics.

POWER SYSTEM PLANNING USING ANN WITH FUZZY LOGIC AND WAVELET ANALYSIS

Directory of Open Access Journals (Sweden)

V. Dharma Dharshin

2016-10-01

Full Text Available The electricity load required for the forthcoming years are predetermined by means of power system planning. Accuracy is the crucial factor that must be taken care of in the power system planning. Electricity is generally volatile, that is it changes and hence appropriate estimation must be done without leading to overestimation or underestimation. The aim of the project is to do appropriate power estimation with the help of the economic factors. The 9 input factors used are GDP, industry, imports, CO2 emission, exports, services, manufacturing, population, per capita consumption. The proposed methodology is done by means of Neural Network concept and Wavelet Analysis. Regression Analysis is also performed and the comparisons are done using Fuzzy Logic. The nonlinear model, Artificial Neural Network and the Wavelet Analysis are found to be more accurate and effective.

Computational logic with square rings of nanomagnets

Science.gov (United States)

Arava, Hanu; Derlet, Peter M.; Vijayakumar, Jaianth; Cui, Jizhai; Bingham, Nicholas S.; Kleibert, Armin; Heyderman, Laura J.

2018-06-01

Nanomagnets are a promising low-power alternative to traditional computing. However, the successful implementation of nanomagnets in logic gates has been hindered so far by a lack of reliability. Here, we present a novel design with dipolar-coupled nanomagnets arranged on a square lattice to (i) support transfer of information and (ii) perform logic operations. We introduce a thermal protocol, using thermally active nanomagnets as a means to perform computation. Within this scheme, the nanomagnets are initialized by a global magnetic field and thermally relax on raising the temperature with a resistive heater. We demonstrate error-free transfer of information in chains of up to 19 square rings and we show a high level of reliability with successful gate operations of ∼94% across more than 2000 logic gates. Finally, we present a functionally complete prototype NAND/NOR logic gate that could be implemented for advanced logic operations. Here we support our experiments with simulations of the thermally averaged output and determine the optimal gate parameters. Our approach provides a new pathway to a long standing problem concerning reliability in the use of nanomagnets for computation.

Transistorized PWM inverter-induction motor drive system

Science.gov (United States)

Peak, S. C.; Plunkett, A. B.

1982-01-01

This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Enhancement of ambipolar characteristics in single-walled carbon nanotubes using C{sub 60} and fabrication of logic gates

Energy Technology Data Exchange (ETDEWEB)

Park, Steve [Department of Materials Science and Engineering, Stanford University, Durand Building, 496 Lomita Mall, Stanford, California 94305-4034 (United States); Nam, Ji Hyun [Department of Electrical Engineering, Stanford University, David Packard Building, 350 Serra Mall, Mail Code: 9505, Stanford, California 94305-9505 (United States); Koo, Ja Hoon; Lei, Ting; Bao, Zhenan, E-mail: zbao@stanford.edu [Department of Chemical Engineering, Stanford University, Shriram Center, 443 Via Ortega, Room 307, Stanford, California 94305-4145 (United States)

2015-03-09

We demonstrate a technique to convert p-type single-walled carbon nanotube (SWNT) network transistor into ambipolar transistor by thermally evaporating C{sub 60} on top. The addition of C{sub 60} was observed to have two effects in enhancing ambipolar characteristics. First, C{sub 60} served as an encapsulating layer that enhanced the ambipolar characteristics of SWNTs. Second, C{sub 60} itself served as an electron transporting layer that contributed to the n-type conduction. Such a dual effect enables effective conversion of p-type into ambipolar characteristics. We have fabricated inverters using our SWNT/C{sub 60} ambipolar transistors with gain as high as 24, along with adaptive NAND and NOR logic gates.

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

A low power 20 GHz comparator in 90 nm COMS technology

Science.gov (United States)

Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

2014-05-01

A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

Logic computation in phase change materials by threshold and memory switching.

Science.gov (United States)

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Metal nanoparticle film-based room temperature Coulomb transistor.

Science.gov (United States)

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY

KAUST Repository

Fahad, Hossain M.

2014-03-01

Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep

Electro-Thermo-Mechanical Analysis of High-Power Press-Pack Insulated Gate Bipolar Transistors under Various Mechanical Clamping Conditions

DEFF Research Database (Denmark)

Hasmasan, Adrian Augustin; Busca, Cristian; Teodorescu, Remus

2014-01-01

With the continuously increasing demand for energy and the limited supply of fossil fuels, renewable power sources are becoming ever more important. Knowing that future energy demand will grow, manufacturers are increasing the size of new wind turbines (WTs) in order to reduce the cost of energy...... production. The reliability of the components has a large impact on the overall cost of a WT, and press-pack (PP) insulated gate bipolar transistors (IGBTs) could be a good solution for future multi-megawatt WTs because of advantages like high power density and reliability. When used in power converters, PP...

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Energy Technology Data Exchange (ETDEWEB)

Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

Science.gov (United States)

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

International Nuclear Information System (INIS)

Li Shu; Zhang Tong

2008-01-01

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

Science.gov (United States)

Ayala, Christopher Lawrence

Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using

A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC

Science.gov (United States)

Shubin, Liu; Zhangming, Zhu; Yintang, Yang; Lianxi, Liu

2014-05-01

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier (SHA)-less pipelined analog-to-digital converters (ADC). Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.

A new quantum flux parametron logic gate with large input margin

International Nuclear Information System (INIS)

Hioe, W.; Hosoya, M.; Goto, E.

1991-01-01

This paper reports on the Quantum Flux Parametron (QFP) which is a flux transfer, flux activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device its correct operation may be affected by coupling to other QFPs. The problems include backcoupling from active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which being a linear input logic, has low input margin. A new logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise and reaction hazard are substantially reduced. Moreover, the input have little interaction hence input margin is greatly improved

Novel field-effect schottky barrier transistors based on graphene-MoS 2 heterojunctions

KAUST Repository

Tian, He

2014-08-11

Recently, two-dimensional materials such as molybdenum disulphide (MoS 2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5-20 cm2/V.s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V.s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

Science.gov (United States)

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

Understanding Social Media Logic

Directory of Open Access Journals (Sweden)

José van Dijck

2013-08-01

Full Text Available Over the past decade, social media platforms have penetrated deeply into the mech­anics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpin­ning its dynamics. This logic will be considered in light of what has been identified as mass me­dia logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmabil­ity, popularity, connectivity, and datafication—and argue that these principles become increas­ingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance ex­isting mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relat­ively simple to identify, but it is much harder to map the complex connections between plat­forms that distribute this logic: users that employ them, technologies that

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors.

Science.gov (United States)

Cho, Ah-Jin; Park, Kee Chan; Kwon, Jang-Yeon

2015-01-01

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

Ultra-high gain diffusion-driven organic transistor

Science.gov (United States)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

High-Performance Vertical Organic Electrochemical Transistors.

Science.gov (United States)

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

Science.gov (United States)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

Directory of Open Access Journals (Sweden)

Salah Bouzina

2016-12-01

Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

Fabrication and simulation of organic transistors and functional circuits