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Sample records for low-power logic transistor

  1. Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

    Science.gov (United States)

    2012-05-10

    CMOS) technology. In this work, Tunnel Field Effect Transistor (TFET) based on Band-to-Band Tunneling ( BTBT ) will be proposed and investigated as an...Band Tunneling ( BTBT ) will be proposed and investigated as an alternative logic switch which can achieve steeper switching characteristics than the...11 2.3.2 Calculation of the Imaginary Dispersion Relation ……………………… 12 2.3.3 Calculation of the BTBT Current and Generation Rate

  2. Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

    Science.gov (United States)

    Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

    2018-06-01

    Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

  3. Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

    Science.gov (United States)

    Mookerjea, Saurabh A.

    Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SSswitching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

  4. Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

    Science.gov (United States)

    Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

    2013-07-01

    We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

  5. From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

    International Nuclear Information System (INIS)

    Register, L.F.; Basu, D.; Reddy, D.

    2011-01-01

    Colleagues and we recently proposed a new type of transistor, a Bilayer Pseudo Spin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineer able device parameters on the formation and gating of interlayer coherent state.

  6. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    International Nuclear Information System (INIS)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-01-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries. (semiconductor integrated circuits)

  7. Optimization of ultra-low-power CMOS transistors

    International Nuclear Information System (INIS)

    Stockinger, M.

    2000-01-01

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  8. Error Immune Logic for Low-Power Probabilistic Computing

    Directory of Open Access Journals (Sweden)

    Bo Marr

    2010-01-01

    design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

  9. DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

    Directory of Open Access Journals (Sweden)

    A. KISHORE KUMAR

    2014-12-01

    Full Text Available Static Random Access Memory (SRAM has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST logic is proposed. The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability. The proposed design is simulated using 0.18 µm process technology and compared with conventional 6T cell. Simulation results show that the proposed memory cell achieves significant improvements in power consumption during read and write operations. It can retain data at a lower supply voltage of 300 mV. This new type of SRAM design can operate at a maximum frequency of 1 GHz at 1 V supply voltage. These qualities of the proposed design make it a best choice for high performance memory chips in the semiconductor industry where reliability and power consumption are of great interest.

  10. Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

    Science.gov (United States)

    Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

    2016-10-20

    Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

  11. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Tooraj Nikoubin

    2010-01-01

    Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

  12. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    OpenAIRE

    Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

    2011-01-01

    Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

  13. Implementation of Self-Bias Transistor on Voting Logic

    International Nuclear Information System (INIS)

    Harzawardi Hasim; Syirrazie Che Soh

    2014-01-01

    Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

  14. Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

    KAUST Repository

    Hanna, Amir; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor

  15. Ambipolar organic tri-gate transistor for low-power complementary electronics

    NARCIS (Netherlands)

    Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

    2016-01-01

    Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

  16. Ultra-Low Power Optical Transistor Using a Single Quantum Dot Embedded in a Photonic Wire

    DEFF Research Database (Denmark)

    Nguyen, H.A.; Grange, T.; Malik, N.S.

    2017-01-01

    Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons.......Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons....

  17. FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

    DEFF Research Database (Denmark)

    Thind, Vandana; Hussain, Dil muhammed Akbar

    2015-01-01

    and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

  18. Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

    International Nuclear Information System (INIS)

    Yang Ling; Zhou Xiao-Wei; Ma Xiao-Hua; Lv Ling; Zhang Jin-Cheng; Hao Yue; Cao Yan-Rong

    2017-01-01

    The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor (HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties. (paper)

  19. Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

    International Nuclear Information System (INIS)

    Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

    2013-01-01

    We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions

  20. Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

    KAUST Repository

    Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Hussain, Muhammad Mustafa

    2013-01-01

    We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

  1. Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

    KAUST Repository

    Hanna, Amir

    2013-11-26

    We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

  2. Low Power Consumption Complementary Inverters with n-MoS2 and p-WSe2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits.

    Science.gov (United States)

    Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil

    2015-10-14

    Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

  3. Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

    KAUST Repository

    Hanna, Amir

    2013-12-23

    We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

    KAUST Repository

    Hanna, Amir

    2014-06-01

    We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4x increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, similar to 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers a pragmatic opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications without any limitation any TFT materials.

  5. Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

    Directory of Open Access Journals (Sweden)

    Shipra Upadhyay

    2013-01-01

    Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

  6. Adaptive Supply Voltage Management for Low Power Logic Circuitry Operating at Subthreshold

    OpenAIRE

    Rehan Ahmed

    2015-01-01

    With the rise in demand of portable hand held devices and with the rise in application of wireless sensor networks and RFID reduction of total power consumption has become a necessity. To save power we operate the logic circuitry of our devices at sub-threshold. In sub-threshold the drain current is exponentially dependent on the threshold voltage hence the threshold variation causes profound variation of ION and IOFF the ratio of which affect the speed of a circuit drastically. S...

  7. Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

    International Nuclear Information System (INIS)

    Kobayashi, H.; Kim, W. B.; Matsumoto, T.

    2011-01-01

    We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

  8. Identification of initiating events using a master logic diagram in low-power and shutdown PSA for nuclear power plant

    International Nuclear Information System (INIS)

    Han, S. J.; Park, J. H.; Kim, T. W.; Ha, J. J.

    2003-01-01

    It is necessary to apply a formal technique instead of an empirical technique in the identification of initiating events for Low Power and ShutDown (LPSD) Probabilistic Safety Assessment (PSA) of Nuclear Power Plant (NPP). The present study focuses on the examination of Master Logic Diagram (MLD) technique as a formal technique in the identification of initiating events. The MLD technique is a deductive tool using top-down approach for the formal and logical indentification of initiating events. The present study modified the MLD used in the full power PSA considering the characteristics of LPSD operation. The modified MLD introduced a systematic formation in decomposition process of which the MLD for full power PSA lacked. The modified MLD was able to identify initiating events systematic and logical. However, the formal techniques including the MLD have a limitation for precisely identifying all of the initiating events. In order to overcome this limitation, it is necessary to combine it with an empirical technique. We expect that the modified MLD can be used in an upgrade of the current LPSD PSAs

  9. A comparative TCAD assessment of III-V channel materials for future high speed and low power logic applications

    Science.gov (United States)

    Gomes, U. P.; Takhar, K.; Ranjan, K.; Rathi, S.; Biswas, D.

    2015-02-01

    In this work, by means physics based drift-diffusion simulations, three different narrow band gap semiconductors; InAs, InSb and In0.53Ga0.47As, and their associated heterostructures have been studied for future high speed and low power logic applications. It is observed that In0.53Ga0.47As has higher immunity towards short channel effects with low DIBL and sub-threshold slope than InSb and InAs. Also it is observed that for the same device geometry InSb has the highest drive current and lower intrinsic delay but its ION/IOFF figure of merit is deteriorated due to excess leakage current.

  10. Modeling and the analysis of control logic for a digital PWM controller based on a nano electronic single electron transistor

    Directory of Open Access Journals (Sweden)

    Rathnakannan Kailasam

    2008-01-01

    Full Text Available This paper describes the modelling and the analysis of control logic for a Nano-Device- based PWM controller. A comprehensive simple SPICE schematic model for Single Electron transistor has been proposed. The operation of basic Single Electron Transistor logic gates and SET flip flops were successfully designed and their performances analyzed. The proposed design for realizing the logic gates and flip-flops is used in constructing the PWM controller utilized for switching the buck converter circuit. The output of the converter circuit is compared with reference voltage, and when the error voltage and the reference are matched the latch is reset so as to generate the PWM signal. Due to the simplicity and accuracy of the compact model, the simulation time and speed are much faster, which makes it potentially applicable in large-scale circuit simulation. This study confirms that the SET-based PWM controller is small in size, consumes ultra low power and operates at high speeds without compromising any performance. In addition these devices are capable of measuring charges of extremely high sensitivity.

  11. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  12. Study and simulation of the time behaviour of MOS transistor devices. Application to a logic assembly

    International Nuclear Information System (INIS)

    Barocas, Marcel

    1974-01-01

    The objective of this research thesis is to determine, by simulation, the time response of devices based on MOS transistors. After a theoretical study of the MOS element, the author develops a transistor model based on its physical components. This model is firstly used to obtain the transistor static characteristics. The author then studies the time response of the inverter logic circuit which is the basic operator of these circuits. Theoretical results are verified by simulation and by experiments. The author then reports a detailed study of the inverter input impedance, and the decoupling property between logic operators in cascade. The simulation confirms the obtained results. Based on this decoupling property, the output time response of a logic chain is studied by using a simulation software. A general method of determination of the output time response is developed with application to a logic assembly [fr

  13. A hybrid nanomemristor/transistor logic circuit capable of self-programming.

    Science.gov (United States)

    Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

    2009-02-10

    Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

  14. Non-classical logic inverter coupling a ZnO nanowire-based Schottky barrier transistor and adjacent Schottky diode.

    Science.gov (United States)

    Hosseini Shokouh, Seyed Hossein; Raza, Syed Raza Ali; Lee, Hee Sung; Im, Seongil

    2014-08-21

    On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

  15. Transistor data book

    International Nuclear Information System (INIS)

    1988-03-01

    It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

  16. Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

    Science.gov (United States)

    Es-Sakhi, Azzedin D.

    Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

  17. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  18. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    International Nuclear Information System (INIS)

    Lee, Youngmin; Lee, Sejoon; Im, Hyunsik; Hiramoto, Toshiro

    2015-01-01

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions

  19. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik [Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715 (Korea, Republic of); Hiramoto, Toshiro [Institute of Industrial Science, University of Tokyo, Tokyo 153-8505 (Japan)

    2015-02-14

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

  20. Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

    Science.gov (United States)

    Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

    2007-03-01

    A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

  1. Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

    Science.gov (United States)

    Moon, Kyeong-Ju; Lee, Tae-Il; Lee, Sang-Hoon; Han, Young-Uk; Ham, Moon-Ho; Myoung, Jae-Min

    2012-07-25

    A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

  2. Ternary logic implemented on a single dopant atom field effect silicon transistor

    NARCIS (Netherlands)

    Klein, M.; Mol, J.A.; Verduijn, J.; Lansbergen, G.P.; Rogge, S.; Levine, R.D.; Remacle, F.

    2010-01-01

    We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through

  3. The multi-interlock and check of logical system for 5 MW low power reactor automatic rod

    International Nuclear Information System (INIS)

    Li Guangjian; Zhao Zengqiao

    1992-01-01

    The safety and reliability of the logical system for 5 MW LPR automatic rod are improved, because of using multi-interlock and manual check on line. The design character and function of the logical system are introduced

  4. Reconfigurable Boolean logic using magnetic single-electron transistors

    Czech Academy of Sciences Publication Activity Database

    Gonzalez-Zalba, M.F.; Ciccarelli, C.; Zarbo, Liviu; Irvine, A.C.; Campion, R.C.; Gallagher, B. L.; Jungwirth, Tomáš; Ferguson, A.J.; Wunderlich, Joerg

    2015-01-01

    Roč. 10, č. 4 (2015), e0125142 E-ISSN 1932-6203 R&D Projects: GA MŠk(CZ) LM2011026; GA ČR GB14-37427G EU Projects: European Commission(XE) 268066 - 0MSPIN Institutional support: RVO:68378271 Keywords : single-electron transitor * reconfigurable logic * ferromagnetic semiconductor Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.057, year: 2015

  5. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

    Directory of Open Access Journals (Sweden)

    A. Kishore Kumar

    2013-01-01

    Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

  6. Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Minsoo, E-mail: minsoo@mosfet.t.u-tokyo.ac.jp; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi

    2014-04-30

    We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al{sub 2}O{sub 3}-based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I{sub ON}/I{sub OFF} ratio of 10{sup 3}–10{sup 4} were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation.

  7. Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

    International Nuclear Information System (INIS)

    Kim, Minsoo; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi

    2014-01-01

    We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al 2 O 3 -based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I ON /I OFF ratio of 10 3 –10 4 were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation

  8. Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

    Science.gov (United States)

    Yu, Woo Jong; Li, Zheng; Zhou, Hailong; Chen, Yu; Wang, Yang; Huang, Yu; Duan, Xiangfeng

    2014-01-01

    The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration. PMID:23241535

  9. Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

    Energy Technology Data Exchange (ETDEWEB)

    Liu, J. W., E-mail: liu.jiangwei@nims.go.jp [International Center for Young Scientists (ICYS), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Liao, M. Y.; Imura, M. [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Watanabe, E.; Oosato, H. [Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Koide, Y., E-mail: koide.yasuo@nims.go.jp [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Center of Materials Research for Low Carbon Emission, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

    2014-08-25

    A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be −40.7 mA·mm{sup −1}, 13.2 ± 0.1 mS·mm{sup −1}, and −3.1 ± 0.1 V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to −10.0 V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

  10. Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

    Science.gov (United States)

    Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

    2017-05-10

    We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

  11. Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

    Science.gov (United States)

    Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

    2013-05-01

    ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

  12. Flexible logic circuits composed of chalcogenide-nanocrystal-based thin film transistors

    International Nuclear Information System (INIS)

    Yun, Junggwon; Cho, Kyoungah; Kim, Sangsig

    2010-01-01

    Complementary NAND and NOR gates composed of p-channel HgTe-nanocrystal (NC) films and n-channel HgSe-NC films were constructed on back-gate patterned plastic substrates. The NAND gate was made of two HgTe-p-channel thin film transistors (TFTs) in parallel and two HgSe-n-channel TFTs in series. The NOR gate was built up with both two HgSe-n-channel TFTs in parallel and two HgTe-p-channel TFTs in series. The mobility and on/off ratio for the p-channel TFTs were estimated to be 0.9 cm 2 V -1 s -1 and 10, respectively, and those for the n-channel TFTs were measured to be 1.8 cm 2 V -1 s -1 and 10 2 , respectively. The NAND and NOR gates were operated with gains of 1.45 and 1.63 and transition widths of 7.8 and 6.2 V, respectively, at room temperature in air. In addition, the operations of the NAND and NOR logics are reproducible for up to 1000 strain cycles.

  13. Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

    Science.gov (United States)

    Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

    The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

  14. Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

    Directory of Open Access Journals (Sweden)

    Jiann-Shiun Yuan

    2017-09-01

    Full Text Available In this review article for Internet of Things (IoT applications, important low-power design techniques for digital and mixed-signal analog–digital converter (ADC circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR ADC security using tunnel field effect transistors (FETs, logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

  15. 3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY

    KAUST Repository

    Fahad, Hossain M.

    2014-03-01

    Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep

  16. Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2016-03-01

    Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  17. Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Science.gov (United States)

    Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

    2016-03-01

    A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  18. Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

    KAUST Repository

    Hanna, Amir; Hussain, Aftab M.; Hussain, Muhammad Mustafa

    2015-01-01

    We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling. © 2015 IEEE.

  19. Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

    KAUST Repository

    Hanna, Amir

    2015-08-12

    We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling. © 2015 IEEE.

  20. Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

    Science.gov (United States)

    Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

    2017-01-01

    Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

  1. Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

    Directory of Open Access Journals (Sweden)

    Myunghwan Ryu

    2016-01-01

    Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

  2. Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

    Science.gov (United States)

    Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

    2018-03-01

    The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

  3. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Science.gov (United States)

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  4. Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

    Science.gov (United States)

    Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

    2018-01-03

    Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

  5. Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

    Science.gov (United States)

    Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

    2015-10-01

    In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

  6. Light-effect transistor (LET with multiple independent gating controls for optical logic gates and optical amplification

    Directory of Open Access Journals (Sweden)

    Jason eMarmon

    2016-03-01

    Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

  7. High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Das, Saptarshi; Roelofs, Andreas [Center for Nanoscale Material, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Dubey, Madan [U.S. Army Research Laboratory, Adelphi, Maryland 20783 (United States)

    2014-08-25

    In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.

  8. Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Shin, SeungJun; Yu, YunSeop; Choi, JungBum

    2008-10-01

    New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

  9. Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

    Science.gov (United States)

    Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

    2016-05-01

    Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

  10. Nanoelectromechanical Switches for Low-Power Digital Computing

    Directory of Open Access Journals (Sweden)

    Alexis Peschot

    2015-08-01

    Full Text Available The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS transistors has become a major concern as the power consumption of electronic integrated circuits (ICs steadily increases with technology scaling. Nano-Electro-Mechanical (NEM relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.

  11. Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

    Science.gov (United States)

    Neudeck, Philip G.

    1998-01-01

    The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

  12. Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

    Science.gov (United States)

    Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

    2017-01-01

    In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

  13. Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol for the Gate Insulator of Pentacene-Based Thin-Film Transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2017-07-01

    Full Text Available In this study, a proposed Microwave-Induction Heating (MIH scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO metal below the Poly(4-vinylphenol (PVP film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min and low-power microwave-irradiation (50 W.

  14. A low-power CMOS frequency synthesizer for GPS receivers

    International Nuclear Information System (INIS)

    Yu Yunfeng; Xiao Shimao; Zhuang Haixiao; Ma Chengyan; Ye Tianchun; Yue Jianlian

    2010-01-01

    A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 . (semiconductor integrated circuits)

  15. FY1995 study of low power LSI design automation software with parallel processing; 1995 nendo heiretsu shori wo katsuyoshita shodenryoku LSI muke sekkei jidoka software no kenkyu kaihatsu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The needs for low power LSIs have rapidly increased recently. For the low power LSI development, not only new circuit technologies but also new design automation tools supporting the new technologies are indispensable. The purpose of this project is to develop a new design automation software, which is able to design new digital LSIs with much lower power than that of conventional CMOS LSIs. A new design automation software for very low power LSIs has been developed targeting the pass-transistor logic SPL, a dedicated low power circuit technology. The software includes a logic synthesis function for pass-transistor-based macrocells and a macrocell placement function. Several new algorithms have been developed for the software, e.g. BDD construction. Some of them are designed and implemented for parallel processing in order to reduce the processing time. The logic synthesis function was tested on a set of benchmarks and finally applied to a low power CPU design. The designed 8-bit CPU was fully compatible with Zilog Z-80. The power dissipation of the CPU was compared with that of commercial CMOS Z-80. At most 82% of power of CMOS was reduced by the new CPU. On the other hand, parallel processing speed up was measured on the macrocell placement function. 34 folds speed up was realized. (NEDO)

  16. Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

    Science.gov (United States)

    Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

    2015-02-04

    Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  17. Nanomagnetic Logic

    Science.gov (United States)

    Carlton, David Bryan

    The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly

  18. High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass.

    Science.gov (United States)

    Shokouh, Seyed Hossein Hosseini; Pezeshki, Atiye; Ali Raza, Syed Raza; Lee, Hee Sung; Min, Sung-Wook; Jeon, Pyo Jin; Shin, Jae Min; Im, Seongil

    2015-01-07

    A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

    Science.gov (United States)

    Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

    The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

  20. Single InAs/GaSb nanowire low-power CMOS inverter.

    Science.gov (United States)

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  1. Low power arcjet performance

    Science.gov (United States)

    Curran, Francis M.; Sarmiento, Charles J.

    1990-01-01

    An experimental investigation was performed to evaluate arcjet operation at low power. A standard, 1 kW, constricted arcjet was run using nozzles with three different constrictor diameters. Each nozzle was run over a range of current and mass flow rates to explore stability and performance in the low power regime. A standard pulse-width modulated power processor was modified to accommodate the high operating voltages required under certain conditions. Stable, reliable operation at power levels below 0.5 kW was obtained at efficiencies between 30 and 40 percent. The operating range was found to be somewhat dependent on constrictor geometry at low mass flow rates. Quasi-periodic voltage fluctuations were observed at the low power end of the operating envelope. The nozzle insert geometry was found to have little effect on the performance of the device. The observed performance levels show that specific impulse levels above 350 seconds can be obtained at the 0.5 kW power level.

  2. Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

    Science.gov (United States)

    Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2015-04-01

    Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

  3. Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

    Science.gov (United States)

    Tsai, Jung-Hui

    2014-01-01

    DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (-27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

  4. Adiabatic logic future trend and system level perspective

    CERN Document Server

    Teichmann, Philip

    2012-01-01

    Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the p...

  5. Low power adaptive synchronizer

    Energy Technology Data Exchange (ETDEWEB)

    Sadowski, Greg

    2018-02-20

    A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.

  6. Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

    Science.gov (United States)

    Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

    2017-08-01

    The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

    DEFF Research Database (Denmark)

    Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

    As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...

  8. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    Science.gov (United States)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  9. Low power constant fraction discriminator

    International Nuclear Information System (INIS)

    Krishnan, Shanti; Raut, S.M.; Mukhopadhyay, P.K.

    2001-01-01

    This paper describes the design of a low power ultrafast constant fraction discriminator, which significantly reduces the power consumption. A conventional fast discriminator consumes about 1250 MW of power whereas this low power version consumes about 440 MW. In a multi detector system, where the number of discriminators is very large, reduction of power is of utmost importance. This low power discriminator is being designed for GRACE (Gamma Ray Atmospheric Cerenkov Experiments) telescope where 1000 channels of discriminators are required. A novel method of decreasing power consumption has been described. (author)

  10. Integrated circuits and logic operations based on single-layer MoS2.

    Science.gov (United States)

    Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

    2011-12-27

    Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

  11. Low Power and High Sensitivity MOSFET-Based Pressure Sensor

    International Nuclear Information System (INIS)

    Zhang Zhao-Hua; Ren Tian-Ling; Zhang Yan-Hong; Han Rui-Rui; Liu Li-Tian

    2012-01-01

    Based on the metal-oxide-semiconductor field effect transistor (MOSFET) stress sensitive phenomenon, a low power MOSFET pressure sensor is proposed. Compared with the traditional piezoresistive pressure sensor, the present pressure sensor displays high performances on sensitivity and power consumption. The sensitivity of the MOSFET sensor is raised by 87%, meanwhile the power consumption is decreased by 20%. (cross-disciplinary physics and related areas of science and technology)

  12. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  13. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  14. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  15. Low-power wind plants

    International Nuclear Information System (INIS)

    Kovalenko, V.I.; Shevchenko, Yu.V.; Shikhajlov, N.A.; Kokhanevich, V.P.; Tanan, G.L.

    1993-01-01

    Design peculiarities, as well as the prospects of development and introduction of the low-power (from 0.5 up to 4 kW) wind power plants (WPP) are considered. The variants of WPP with vertical and horizontal rotation axis are described. The data characterizing cost and structure of expenditures on WPP manufacture and operation are given

  16. Low power digital signal processing

    DEFF Research Database (Denmark)

    Paker, Ozgun

    2003-01-01

    hardwired ASICs and more than 6 21 times lower than current state of the art low-power DSP processors. An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved...... to be a viable alternative to conventional expensive test equipment. Finally, the work presented in this thesis has been published at several IEEE workshops and conferences, and in the Journal of VLSI Signal Processing....

  17. Vertical organic transistors.

    Science.gov (United States)

    Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

    2015-11-11

    Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

  18. Tunable Tribotronic Dual-Gate Logic Devices Based on 2D MoS2 and Black Phosphorus.

    Science.gov (United States)

    Gao, Guoyun; Wan, Bensong; Liu, Xingqiang; Sun, Qijun; Yang, Xiaonian; Wang, Longfei; Pan, Caofeng; Wang, Zhong Lin

    2018-03-01

    With the Moore's law hitting the bottleneck of scaling-down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self-powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual-gate logic device based on a MoS 2 field-effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm -1 . Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low-power-consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human-machine interfacing, data processing and transmission. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Low power unattended defense reactor

    International Nuclear Information System (INIS)

    Kirchner, W.L.; Meier, K.L.

    1984-01-01

    A small, low power, passive, nuclear reactor electric power supply has been designed for unattended defense applications. Through innovative utilization of existing proven technologies and components, a highly reliable, ''walk-away safe'' design has been obtained. Operating at a thermal power level of 200 kWt, the reactor uses low enrichment uranium fuel in a graphite block core to generate heat that is transferred through heat pipes to a thermoelectric (TE) converter. Waste heat is removed from the TEs by circulation of ambient air. Because such a power supply offers the promise of minimal operation and maintenance (OandM) costs as well as no fuel logistics, it is particularly attractive for remote, unattended applications such as the North Warning System

  20. Low power unattended defense reactor

    International Nuclear Information System (INIS)

    Kirchner, W.L.; Meier, K.L.

    1984-01-01

    A small, low power, passive, nuclear reactor electric power supply has been designed for unattended defense applications. Through innovative utilization of existing proven technologies and components, a highly reliable, walk-away safe design has been obtained. Operating at a thermal power level of 200 kWt, the reactor uses low enrichment uranium fuel in a graphite block core to generate heat that is transferred through heat pipes to a thermoelectric (TE) converter. Waste heat is removed from the TEs by circulation of ambient air. Because such a power supply offers the promise of minimal operation and maintenance (O and M) costs as well as no fuel logistics, it is particularly attractive for remote, unattended applications such as the North Warning System

  1. A new universal gate for low power SoC applications

    Indian Academy of Sciences (India)

    This paper formulates a new design technique for an area and energy ... Low power; CMOS; pass-transistor; NAND gate; Koomey's law. 1. ... amount of battery you need will fall by a factor of two every year and a half' (Koomey Jonathan.

  2. Designing and simulation smart multifunctional continuous logic device as a basic cell of advanced high-performance sensor systems with MIMO-structure

    Science.gov (United States)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2015-01-01

    We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It's have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V.

  3. Microelectromechanical reprogrammable logic device

    Science.gov (United States)

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  4. Microelectromechanical reprogrammable logic device

    KAUST Repository

    Hafiz, Md Abdullah Al

    2016-03-29

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

  5. Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

    Science.gov (United States)

    Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

    Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

  6. Low-Power Wireless Sensor Network Infrastructures

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg

    Advancements in wireless communication and electronics improving form factor and hardware capabilities has expanded the applicability of wireless sensor networks. Despite these advancements, devices are still limited in terms of energy which creates the need for duty-cycling and low-power protocols...... peripherals need to by duty-cycled and the low-power wireless radios are severely influenced by the environmental effects causing bursty and unreliable wireless channels. This dissertation presents a communication stack providing services for low-power communication, secure communication, data collection......, and network management which enables construction of low-power wireless sensor network applications. More specifically, these services are designed with the extreme low-power scenarios of the SensoByg project in mind and are implemented as follows. First, low-power communication is implemented with Auto...

  7. One electron-based smallest flexible logic cell

    Science.gov (United States)

    Kim, S. J.; Lee, J. J.; Kang, H. J.; Choi, J. B.; Yu, Y.-S.; Takahashi, Y.; Hasko, D. G.

    2012-10-01

    A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.

  8. Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

    Science.gov (United States)

    Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

    2018-05-09

    Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

  9. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  10. Review of mixer design for low voltage - low power applications

    Science.gov (United States)

    Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

    2017-09-01

    A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

  11. Radiation tolerant combinational logic cell

    Science.gov (United States)

    Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

    2009-01-01

    A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

  12. Tunneling field effect transistor technology

    CERN Document Server

    Chan, Mansun

    2016-01-01

    This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

  13. Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

    Science.gov (United States)

    Wang, Tian; Cui, Xiaoxin; Ni, Yewen; Liao, Kai; Liao, Nan; Yu, Dunshan; Cui, Xiaole

    2017-04-01

    With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability. Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

  14. Data Logic

    DEFF Research Database (Denmark)

    Nilsson, Jørgen Fischer

    A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...

  15. Copper atomic-scale transistors.

    Science.gov (United States)

    Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

    2017-01-01

    We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

  16. Programmable Array Logic Design

    International Nuclear Information System (INIS)

    Demon Handoyo; Djen Djen Djainal

    2007-01-01

    Good digital circuit design that part of a complex system, often becoming a separate problem. To produce finishing design according to wanted performance is often given on to considerations which each other confuse, hence thereby analyse optimization become important in this case. To realization is made design logic program, the first are determined global diagram block, then are decided contents of these block diagram, and then determined its interconnection in the form of logic expression, continued with election of component. These steps are done to be obtained the design with low price, easy in its interconnection, minimal volume, low power and certainty god work. (author)

  17. Ultra-low power circuits based on tunnel FETs for energy harvesting applications

    OpenAIRE

    Cavalheiro, David

    2017-01-01

    There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadraticall...

  18. Perspectives on Low Power and Shutdown Risk

    International Nuclear Information System (INIS)

    Camp, Allen L.; Whitehead, Donnie W.; Wheeler, Timothy A.; Lehner, John; Chu, Tsong-Lun; Lois, Erasmai; Drouin, Mary

    2000-01-01

    This paper presents results from a program sponsored by the US Nuclear Regulatory Commission to examine the risks from low power and shutdown operations. Significant progress has been made by the industry in reducing such risks; however, important operational events continue to occur. Current perceptions of low power and shutdown risks are discussed in the paper along with an assessment of the current methods for understanding important events and quantifying their associated risk

  19. Ultra low power full adder topologies

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid

    In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the pr...... the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations....

  20. Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

    Directory of Open Access Journals (Sweden)

    Salah Bouzina

    2016-12-01

    Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

  1. Unijunction transistors

    International Nuclear Information System (INIS)

    1981-01-01

    The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

  2. Complementary HFET technology for low-power mixed-mode applications

    Energy Technology Data Exchange (ETDEWEB)

    Baca, A.G.; Sherwin, M.E.; Zolper, J.C.; Dubbert, D.F.; Hietala, V.M.; Shul, R.J.; Sloan, L.R.; Hafich, M.J.

    1996-06-01

    Development of a complementary heterostructure field effect transistor (CHFET) technology for low-power, mixed-mode digital-microwave applications is presented. An earlier digital CHFET technology with independently optimizable transistors which operated with 319 ps loaded gate delays at 8.9 fJ is reviewed. Then work demonstrating the applicability of the digital nJFET device as a low-power microwave transistor in a hybrid microwave amplifier without any modification to the digital process is presented. A narrow band amplifier with a 0.7 {times} 100 {micro}m nJFET as the active element was designed, constructed, and tested. At 1 mW operating power, the amplifier showed 9.7 dB of gain at 2.15 GHz and a minimum noise figure of 2.5 dB. In addition, next generation CHFET transistors with sub 0.5 {micro}m gate lengths were developed. Cutoff frequencies, f{sub t} of 49 GHz and 11.5 GHz were achieved for n- and p-channel FETs with 0.3 and 0.4 {micro}m gates, respectively. These FETs will enable both digital and microwave circuits with enhanced performance.

  3. Vertical organic transistors

    International Nuclear Information System (INIS)

    Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

    2015-01-01

    Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

  4. Organic electrochemical transistors

    Science.gov (United States)

    Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

    2018-02-01

    Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

  5. Organic electrochemical transistors

    KAUST Repository

    Rivnay, Jonathan

    2018-01-16

    Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

  6. r-Universal reversible logic gates

    International Nuclear Information System (INIS)

    Vos, A de; Storme, L

    2004-01-01

    Reversible logic plays a fundamental role both in ultra-low power electronics and in quantum computing. It is therefore important to know which reversible logic gates can be used as building block for the reversible implementation of an arbitrary boolean function and which cannot

  7. Testing Superconductor Logic Integrated Circuits

    NARCIS (Netherlands)

    Arun, A.J.; Kerkhoff, Hans G.

    2005-01-01

    Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these

  8. Superconducting transistor

    International Nuclear Information System (INIS)

    Gray, K.E.

    1978-01-01

    A three film superconducting tunneling device, analogous to a semiconductor transistor, is presented, including a theoretical description and experimental results showing a current gain of four. Much larger current gains are shown to be feasible. Such a development is particularly interesting because of its novelty and the striking analogies with the semiconductor junction transistor

  9. Highly efficient conductance control in a topological insulator based magnetoelectric transistor

    Energy Technology Data Exchange (ETDEWEB)

    Duan, Xiaopeng; Li, Xi-Lai; Li, Xiaodong; Semenov, Yuriy G. [Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Kim, Ki Wook, E-mail: kwk@ncsu.edu [Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Department of Physics, North Carolina State University, Raleigh, North Carolina 27695 (United States)

    2015-12-14

    The spin-momentum interlocked properties of the topological insulator (TI) surface states are exploited in a transistor-like structure for efficient conductance control in the TI-magnet system. Combined with the electrically induced magnetization rotation as part of the gate function, the proposed structure takes advantage of the magnetically modulated TI electronic band dispersion in addition to the conventional electrostatic barrier. The transport analysis coupled with the magnetic simulation predicts super-steep current-voltage characteristics near the threshold along with the GHz operating frequencies. Potential implementation to a complementary logic is also examined. The predicted characteristics are most suitable for applications requiring low power or those with small signals.

  10. Embedding Logics into Product Logic

    Czech Academy of Sciences Publication Activity Database

    Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David

    1998-01-01

    Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics

  11. Low power laser in Odonto-stomathology

    International Nuclear Information System (INIS)

    Valiente Zaldivar, Carolina

    2009-01-01

    The use of low power laser technology in our country, and mainly in Odonto-stomathology, have gad a constant evolution and development since the 80's, being significant the social repercution between professionals and patients, achieving and alternative of treatment, which is non painful, and the results, either analgesic, anti-inflammatory, and stimulating of the tissue regeneration. This work intends to show the therapeutic procedure, and the different clinical entities, treated with Cuban instruments, that contains red or infrared diode lasers. The experience, during more than 20 years of the use of this kind of low power lasers, with different radiation techniques, includes: laser therapy or their combination with acupuncture points, so-called Laser puncture, which makes this technology an alternative of treatment for several clinical entities in correspondence with alterations of the tissues of the tooth, the mucose, neuronal alterations, and so on, procedures that are generalized in more that 60 services of our country. (Author)

  12. Low-Power Public Key Cryptography

    Energy Technology Data Exchange (ETDEWEB)

    BEAVER,CHERYL L.; DRAELOS,TIMOTHY J.; HAMILTON,VICTORIA A.; SCHROEPPEL,RICHARD C.; GONZALES,RITA A.; MILLER,RUSSELL D.; THOMAS,EDWARD V.

    2000-11-01

    This report presents research on public key, digital signature algorithms for cryptographic authentication in low-powered, low-computation environments. We assessed algorithms for suitability based on their signature size, and computation and storage requirements. We evaluated a variety of general purpose and special purpose computing platforms to address issues such as memory, voltage requirements, and special functionality for low-powered applications. In addition, we examined custom design platforms. We found that a custom design offers the most flexibility and can be optimized for specific algorithms. Furthermore, the entire platform can exist on a single Application Specific Integrated Circuit (ASIC) or can be integrated with commercially available components to produce the desired computing platform.

  13. Low Cost, Low Power, High Sensitivity Magnetometer

    Science.gov (United States)

    2008-12-01

    which are used to measure the small magnetic signals from brain. Other types of vector magnetometers are fluxgate , coil based, and magnetoresistance...concentrator with the magnetometer currently used in Army multimodal sensor systems, the Brown fluxgate . One sees the MEMS fluxgate magnetometer is...Guedes, A.; et al., 2008: Hybrid - LOW COST, LOW POWER, HIGH SENSITIVITY MAGNETOMETER A.S. Edelstein*, James E. Burnette, Greg A. Fischer, M.G

  14. Integrated low power ultrasound sensor interfaces

    OpenAIRE

    Gustafsson, Martin

    2005-01-01

    Imagine that the technical development can take the ultrasound measurement systems from the large piece of machinery today, to a coin size system tomorrow. The factor that has reduced the size of electronic systems over time is integration and integrated circuits. In this thesis circuit simulator models of complete ultrasound systems are used to design custom integrated circuits. These circuits are optimized for low power consumption and small size. The models that are used predict the acoust...

  15. Transistor challenges - A DRAM perspective

    International Nuclear Information System (INIS)

    Faul, Juergen W.; Henke, Dietmar

    2005-01-01

    Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

  16. Transistor Effect in Improperly Connected Transistors.

    Science.gov (United States)

    Luzader, Stephen; Sanchez-Velasco, Eduardo

    1996-01-01

    Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

  17. Logical labyrinths

    CERN Document Server

    Smullyan, Raymond

    2008-01-01

    This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T

  18. Static Characteristics of the Ferroelectric Transistor Inverter

    Science.gov (United States)

    Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

    2010-01-01

    The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

  19. Low power signal processing research at Stanford

    Science.gov (United States)

    Burr, J.; Williamson, P. R.; Peterson, A.

    1991-01-01

    This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

  20. Mathematical logic

    CERN Document Server

    Kleene, Stephen Cole

    1967-01-01

    Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.

  1. BDI Logics

    NARCIS (Netherlands)

    Meyer, J.J.Ch.; Broersen, J.M.; Herzig, A.

    2015-01-01

    This paper presents an overview of so-called BDI logics, logics where the notion of Beliefs, Desires and Intentions play a central role. Starting out from the basic ideas about BDI by Bratman, we consider various formalizations in logic, such as the approach of Cohen and Levesque, slightly

  2. A low power Multi-Channel Analyzer

    International Nuclear Information System (INIS)

    Anderson, G.A.; Brackenbush, L.W.

    1993-06-01

    The instrumentation used in nuclear spectroscopy is generally large, is not portable, and requires a lot of power. Key components of these counting systems are the computer and the Multi-Channel Analyzer (MCA). To assist in performing measurements requiring portable systems, a small, very low power MCA has been developed at Pacific Northwest Laboratory (PNL). This MCA is interfaced with a Hewlett Packard palm top computer for portable applications. The MCA can also be connected to an IBM/PC for data storage and analysis. In addition, a real-time time display mode allows the user to view the spectra as they are collected

  3. Cold neutron radiography using low power accelerator

    International Nuclear Information System (INIS)

    Kiyanagi, Yoshiaki; Iwasa, Hirokatu

    1993-01-01

    A cold neutron source which can be adopted at a low power accelerator was studied. Time-of-flight radiography using the cold neutron source was performed. It is suggested that time-of-flight cold neutron radiography has possibility to distinguish the materials more clearly than the traditional film method since large contrast differences can be obtained by using digital data of the neutron intensity at different energies from thermal to cold region. Material will be identified at the same time by this method. (author)

  4. A heterogeneous multi-core platform for low power signal processing in systems-on-chip

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

    2002-01-01

    is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more......This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

  5. Graphene Field Effect Transistor for Radiation Detection

    Science.gov (United States)

    Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

    2016-01-01

    The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

  6. Low power adder based auditory filter architecture.

    Science.gov (United States)

    Rahiman, P F Khaleelur; Jayanthi, V S

    2014-01-01

    Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  7. Low Power Adder Based Auditory Filter Architecture

    Directory of Open Access Journals (Sweden)

    P. F. Khaleelur Rahiman

    2014-01-01

    Full Text Available Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  8. Low power reactor for remote applications

    International Nuclear Information System (INIS)

    Meier, K.L.; Palmer, R.G.; Kirchner, W.L.

    1985-01-01

    A compact, low power reactor is being designed to provide electric power for remote, unattended applications. Because of the high fuel and maintenance costs for conventional power sources such as diesel generators, a reactor power supply appears especially attractive for remote and inaccessible locations. Operating at a thermal power level of 135 kWt, the power supply achieves a gross electrical output of 25 kWe from an organic Rankine cycle (ORC) engine. By intentional selection of design features stressing inherent safety, operation in an unattended mode is possible with minimal risk to the environment. Reliability is achieved through the use of components representing existing, proven technology. Low enrichment uranium particle fuel, in graphite core blocks, cooled by heat pipes coupled to an ORC converter insures long-term, virtually maintenance free, operation of this reactor for remote applications. 10 refs., 7 figs., 3 tabs

  9. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  10. Radiation Tolerant Low Power Precision Time Source, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — The availability of small, low power atomic clocks is now a reality for ground-based and airborne navigation systems. Kernco's Low Power Precision Time Source...

  11. A pulse amplitude discriminator with very low-power consuming

    International Nuclear Information System (INIS)

    Deng Changming; Liu Zhengshan; Zhang Zhiyong; Cheng Chang

    2000-01-01

    A low-power pulse amplitude discriminator is described. The discriminator circuit is mainly composed of an integrated voltage comparator, MAX921, and owns the characters of very low-power and low operating voltage

  12. Dispositional logic

    Science.gov (United States)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  13. Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

    Science.gov (United States)

    Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

    2017-07-01

    In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

  14. Energy neutral and low power wireless communications

    Science.gov (United States)

    Orhan, Oner

    Wireless sensor nodes are typically designed to have low cost and small size. These design objectives impose restrictions on the capacity and efficiency of the transceiver components and energy storage units that can be used. As a result, energy becomes a bottleneck and continuous operation of the sensor network requires frequent battery replacements, increasing the maintenance cost. Energy harvesting and energy efficient transceiver architectures are able to overcome these challenges by collecting energy from the environment and utilizing the energy in an intelligent manner. However, due to the nature of the ambient energy sources, the amount of useful energy that can be harvested is limited and unreliable. Consequently, optimal management of the harvested energy and design of low power transceivers pose new challenges for wireless network design and operation. The first part of this dissertation is on energy neutral wireless networking, where optimal transmission schemes under different system setups and objectives are investigated. First, throughput maximization for energy harvesting two-hop networks with decode-and-forward half-duplex relays is studied. For a system with two parallel relays, various combinations of the following four transmission modes are considered: Broadcast from the source, multi-access from the relays, and successive relaying phases I and II. Next, the energy cost of the processing circuitry as well as the transmission energy are taken into account for communication over a broadband fading channel powered by an energy harvesting transmitter. Under this setup, throughput maximization, energy maximization, and transmission completion time minimization problems are studied. Finally, source and channel coding for an energy-limited wireless sensor node is investigated under various energy constraints including energy harvesting, processing and sampling costs. For each objective, optimal transmission policies are formulated as the solutions of a

  15. A single nano cantilever as a reprogrammable universal logic gate

    KAUST Repository

    Chappanda, K. N.

    2017-02-24

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

  16. A single nano cantilever as a reprogrammable universal logic gate

    International Nuclear Information System (INIS)

    Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J

    2017-01-01

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)

  17. Logic Meeting

    CERN Document Server

    Tugué, Tosiyuki; Slaman, Theodore

    1989-01-01

    These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.

  18. Buried injector logic, a vertical IIL using deep ion implantation

    NARCIS (Netherlands)

    Mouthaan, A.J.

    1987-01-01

    A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is

  19. Low power acoustic harvesting of aerosols

    Energy Technology Data Exchange (ETDEWEB)

    Kaduchak, G. (Gregory); Sinha, D. N. (Dipen N)

    2001-01-01

    A new acoustic device for levitation and/or concentration of aerosols and sniall liquid/solid samples (up to several millimeters in diameter) in air has been developed. The device is inexpensive, low-power, and, in its simplest embodiment, does not require accurate alignmen1 of a resonant cavity. It is constructed from a cylindrical PZT tube of outside diameter D = 19.0 mm and thickness-to-radius ratio h/a - 0.03. The lowest-order breathing mode of the tube is tuned to match a resonant mode of the interior air-filled cylindrical cavity. A high Q cavity results that can be driven efficiently. An acoustic standing wave is created in the inteirior cavity of the cylindrical shell where particle concrmtration takes place at the nodal planes of the field. It is shown that drops of water in excess of 1 mm in diameter may be levitated against the force of gravity for approxirnately 100 mW of input electrical power. The main objective of the research is to implement this lowpower device to concentrate and harvest aerosols in a flowing system. Several different cavity geonietries iwe presented for efficient collection of 1 he conaartratetl aerosols. Concentraiion factors greater than 40 iue demonstrated for particles of size 0.7 1.1 in a flow volume of 50 L/minute.

  20. New generation low power radiation survey instruments

    International Nuclear Information System (INIS)

    Waechter, D.A.; Bjarke, G.O.; Trujillo, F.; Umbarger, C.J.; Wolf, M.A.

    1984-01-01

    A number of new, ultra-low-powered radiation instruments have recently been developed at Los Alamos. Among these are two instruments which use a novel power source to eliminate costly batteries. The newly developed gamma detecting radiac, nicknamed the Firefly, and the alpha particle detecting instrument, called the Simple Cordless Alpha Monitor, both use recent advances in miniaturization and powersaving electronics to yield devices which are small, rugged, and very power-frugal. The two instruments consume so little power that the need for batteries to run them is eliminated. They are, instead, powered by a charged capacitor which will operate the instruments for an hour or more. Use of a capacitor as a power source eliminates many problems commonly associated with battery-operated instruments, such as having to open the case to change batteries, battery storage life, availability of batteries in the field, and some savings in weight. Both line power and mechanical sources are used to charge the storage capacitors which power the instruments

  1. Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

    International Nuclear Information System (INIS)

    Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

    1990-01-01

    Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

  2. Rapid single flux quantum logic in high temperature superconductor technology

    NARCIS (Netherlands)

    Shunmugavel, K.

    2006-01-01

    A Josephson junction is the basic element of rapid single flux quantum logic (RSFQ) circuits. A high operating speed and low power consumption are the main advantages of RSFQ logic over semiconductor electronic circuits. To realize complex RSFQ circuits in HTS technology one needs a reproducible

  3. A parity checker circuit based on microelectromechanical resonator logic elements

    Energy Technology Data Exchange (ETDEWEB)

    Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)

    2017-03-03

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.

  4. A parity checker circuit based on microelectromechanical resonator logic elements

    KAUST Repository

    Hafiz, Md Abdullah Al

    2017-01-11

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

  5. A parity checker circuit based on microelectromechanical resonator logic elements

    KAUST Repository

    Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein

    2017-01-01

    Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

  6. Hacking and penetration testing with low power devices

    CERN Document Server

    Polstra, Philip

    2014-01-01

    Hacking and Penetration Testing with Low Power Devices shows you how to perform penetration tests using small, low-powered devices that are easily hidden and may be battery-powered. It shows how to use an army of devices, costing less than you might spend on a laptop, from distances of a mile or more. Hacking and Penetration Testing with Low Power Devices shows how to use devices running a version of The Deck, a full-featured penetration testing and forensics Linux distribution, and can run for days or weeks on batteries due to their low power consumption. Author Philip Polstra shows how to

  7. Propositional Logics of Dependence

    NARCIS (Netherlands)

    Yang, F.; Väänänen, J.

    2016-01-01

    In this paper, we study logics of dependence on the propositional level. We prove that several interesting propositional logics of dependence, including propositional dependence logic, propositional intuitionistic dependence logic as well as propositional inquisitive logic, are expressively complete

  8. Intuitionistic hybrid logic

    DEFF Research Database (Denmark)

    Braüner, Torben

    2011-01-01

    Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....

  9. Fuzzy logic

    CERN Document Server

    Smets, P

    1995-01-01

    We start by describing the nature of imperfect data, and giving an overview of the various models that have been proposed. Fuzzy sets theory is shown to be an extension of classical set theory, and as such has a proeminent role or modelling imperfect data. The mathematic of fuzzy sets theory is detailled, in particular the role of the triangular norms. The use of fuzzy sets theory in fuzzy logic and possibility theory,the nature of the generalized modus ponens and of the implication operator for approximate reasoning are analysed. The use of fuzzy logic is detailled for application oriented towards process control and database problems.

  10. Separation Logic

    DEFF Research Database (Denmark)

    Reynolds, John C.

    2002-01-01

    In joint work with Peter O'Hearn and others, based on early ideas of Burstall, we have developed an extension of Hoare logic that permits reasoning about low-level imperative programs that use shared mutable data structure. The simple imperative programming language is extended with commands (not...... with the inductive definition of predicates on abstract data structures, this extension permits the concise and flexible description of structures with controlled sharing. In this paper, we will survey the current development of this program logic, including extensions that permit unrestricted address arithmetic...

  11. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-01-01

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  12. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  13. Dynamic electrical characteristics of low-power ring oscillators constructed with inorganic nanoparticles on flexible plastics.

    Science.gov (United States)

    Yun, Junggwon; Cho, Kyoungah; Kim, Sangsig

    2012-11-01

    In this study, we demonstrate for the first time the low-power and stable performance of a ring oscillator constructed on a flexible plastic with solution-processable inorganic nanoparticles (NPs). Our flexible ring oscillator is composed of three inverters based on n- and p-type inorganic NP thin-film transistors. Each of the component inverters exhibits a gain of ∼80 at a voltage of 5 V. For the ring oscillator, the sine waves are generated with a frequency of up to 12 kHz. The waveforms are undistorted under strained conditions and maintained even after 5000 bending cycles. The frequency and waveform of the output waves obtained from our flexible ring oscillator are analyzed and discussed in detail.

  14. A low-power wide range transimpedance amplifier for biochemical sensing.

    Science.gov (United States)

    Rodriguez-Villegas, Esther

    2007-01-01

    This paper presents a novel low voltage and low power transimpedance amplifier for amperometric potentiostats. The power is optimized by having three different gain settings for different current ranges, which can be programmed with a biasing current. The voltage ranges have been optimized by using FGMOS transistors in a second voltage amplification stage that simultaneously allow for offset calibration as well as independent biasing of the gates. The circuit operates with input currents from 1 pA to 1 microA, with a maximum power supply voltage of 1.5 V and consumes 82.5 nW, 9.825 microW, 47.325 microW for currents varying from (1 pA, 0.25 nA), (0.25 nA, 62.5 nA) and (62.5 nA, 1 microA) respectively.

  15. Mono-Type TFT Logic Architectures for Low Power Systems on Panel Applications

    OpenAIRE

    Yang, Yifan; Lee, Sungsik; Holburn, David Michael; Nathan, Arokia

    2016-01-01

    This paper introduces novel 7-T pseudo-CMOS for enhancement mode and 6-T pseudo-CMOS for depletion mode inverter circuit architectures. The designs are built around mono-type of TFTs and consume less power consumption than existing 4-T pseudo-CMOS circuits. In addition, they provide steep transfer curves, along with embedded control for compensation of device parameter variations. Analysis of the transient behavior for the various circuit architectures is presented, providing quantitative ins...

  16. Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

    Science.gov (United States)

    Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

    2016-08-24

    Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

  17. Nanowire NMOS Logic Inverter Characterization.

    Science.gov (United States)

    Hashim, Yasir

    2016-06-01

    This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

  18. A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

    International Nuclear Information System (INIS)

    Zhang Junyu; Wang Yong; Liu Jing; Zhang Manhong; Xu Zhongguang; Huo Zongliang; Liu Ming

    2012-01-01

    We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the 'erased states' can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications. (semiconductor devices)

  19. Ultra low power CMOS-based sensor for on-body radiation dose measurements

    KAUST Repository

    Arsalan, Muhammad

    2012-03-01

    For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA\\'s 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

  20. Ultra low power CMOS-based sensor for on-body radiation dose measurements

    KAUST Repository

    Arsalan, Muhammad; Shamim, Atif; Shams, Maitham; Tarr, Nathan Garry; Roy, Langis

    2012-01-01

    For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA's 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

  1. Design of ultra-low power impulse radios

    CERN Document Server

    Apsel, Alyssa; Dokania, Rajeev

    2014-01-01

    This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead.  This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs.  Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.   • Enables detailed understanding of the design space for ultra-low power radio; • Provides detailed discussion and examples of the design of a practical low power ...

  2. Low Power Microrobotics Utilizing Biologically Inspired Energy Generation

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase I study, the study team will investigate the usability of a microbial fuel cell to power a small microrover, design low-power electronics for effective...

  3. Dual Mode Low Power Hall Thruster, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Sample and return missions desire and missions like Saturn Observer require a low power Hall thruster that can operate at high thrust to power as well as high...

  4. Low Power/Low Voltage Interface Circuitry for Capacitive Sensors

    DEFF Research Database (Denmark)

    Furst, Claus Efdmann

    This thesis focuses mainly on low power/low voltage interface circuits, implemented in CMOS, for capacitive sensors. A brief discussion of demands and possibilities for analog signal processing in the future is presented. Techniques for low power design is presented. This is done by analyzing power...... power consumption. It is shown that the Sigma-Delta modulator is advantageous when embedded in a feedback loop with a mechanical sensor. Here a micro mechanical capacitive microphone. Feedback and detection circuitry for a capacitive microphone is presented. Practical implementations of low power....../low voltage interface circuitry is presented. It is demonstrated that an amplifier optimized for a capacitive microphone implemented in a standard 0.7 micron CMOS technology competes well with a traditional JFET amplifier. Furthermore a low power/low voltage 3rd order Sigma-Delta modulator is presented...

  5. Wireless powering for low-power distributed sensors

    Directory of Open Access Journals (Sweden)

    Popović Zoya B.

    2006-01-01

    Full Text Available In this paper, an overview of the field of wireless powering is presented with an emphasis on low-power applications. Several rectenna elements and arrays are discussed in more detail: (1 a 10-GHz array for powering sensors in aircraft wings; (2 a single antenna in the 2.4-GHz ISM band for low-power assisted-living sensors; and (3 a broadband array for power harvesting in the 2-18GHz frequency range.

  6. Doped Organic Transistors.

    Science.gov (United States)

    Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

    2016-11-23

    Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

  7. SOI Transistor measurement techniques using body contacted transistors

    International Nuclear Information System (INIS)

    Worley, E.R.; Williams, R.

    1989-01-01

    Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

  8. Choreographies, Logically

    DEFF Research Database (Denmark)

    Carbone, Marco; Montesi, Fabrizio; Schürmann, Carsten

    2014-01-01

    In Choreographic Programming, a distributed system is programmed by giving a choreography, a global description of its interactions, instead of separately specifying the behaviour of each of its processes. Process implementations in terms of a distributed language can then be automatically...... projected from a choreography. We present Linear Compositional Choreographies (LCC), a proof theory for reasoning about programs that modularly combine choreographies with processes. Using LCC, we logically reconstruct a semantics and a projection procedure for programs. For the first time, we also obtain...... a procedure for extracting choreographies from process terms....

  9. Flexible Low-power SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout

    Science.gov (United States)

    England, Troy; Lilly, Michael; Curry, Matthew; Carr, Stephen; Carroll, Malcolm

    Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout of electrons bound to Si:P donors. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will introduce two new amplifier topologies that provide excellent gain versus power tradeoffs using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The AC HBT allows in-situ adjustment of power dissipation during an experiment and can provide gain in the millikelvin temperature regime while dissipating less than 500 nW. The AC Current Amplifier maximizes gain at nearly 800 A/A. We will also show results of using these amplifiers with SETs at 4 K. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. Flexible Low-power SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout.

  10. Quantum logic

    International Nuclear Information System (INIS)

    Mittelstaedt, P.

    1979-01-01

    The subspaces of Hilbert space constitute an orthocomplemented quasimodular lattice Lsub(q) for which neither a two-valued function nor generalized truth function exist. A generalisation of the dialogic method can be used as an interpretation of a lattice Lsub(qi), which may be considered as the intuitionistic part of Lsub(q). Some obvious modifications of the dialogic method are introduced which come from the possible incommensurability of propositions about quantum mechanical systems. With the aid of this generalized dialogic method a propositional calculus Qsub(eff) is derived which is similar to the calculus of effective (intuitionistic) logic, but contains a few restrictions which are based on the incommensurability of quantum mechanical propositions. It can be shown within the framework of the calculus Qsub(eff) that the value-definiteness of the elementary propositions which are proved by quantum mechanical propositions is inherited by all finite compund propositions. In this way one arrives at the calculus Q of full quantum logic which incorporates the principle of excluded middle for all propositions and which is a model for the lattice Lsub(q). (Auth.)

  11. 47 CFR 73.6019 - Digital Class A TV station protection of low power TV, TV translator, digital low power TV and...

    Science.gov (United States)

    2010-10-01

    ... power TV, TV translator, digital low power TV and digital TV translator stations. 73.6019 Section 73... low power TV, TV translator, digital low power TV and digital TV translator stations. An application... A TV station will not be accepted if it fails to protect authorized low power TV, TV translator...

  12. Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

    Science.gov (United States)

    Sengupta, Sarmista; Pandit, Soumya

    2015-06-01

    Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

  13. Study of methodology for low power/shutdown fire PSA

    International Nuclear Information System (INIS)

    Yan Zhen; Li Zhaohua; Li Lin; Song Lei

    2014-01-01

    As a risk assessment technology based on probability, the fire PSA is accepted abroad by nuclear industry in its application in the risk assessment for nuclear power plants. Based on the industry experience, the fire-induced impact on the plant safety during low power and shutdown operation cannot be neglected, therefore fire PSA can be used to assess the corresponding fire risk. However, there is no corresponding domestic guidance/standard as well as accepted analysis methodology up to date. Through investigating the latest evolvement on fire PSA during low power and shutdown operation, and integrating its characteristic with the corresponding engineering experience, an engineering methodology to evaluate the fire risk during low power and shutdown operation for nuclear power plant is established in this paper. In addition, an analysis demonstration as an example is given. (authors)

  14. Design of ternary low-power Domino JKL flip—flop and its application

    International Nuclear Information System (INIS)

    Wang Pengjun; Yang Qiankun; Zheng Xuesong

    2012-01-01

    By researching the ternary flip—flop and the adiabatic Domino circuit, a novel design of low-power ternary Domino JKL flip—flop on the switch level is proposed. First, the switch-level structure of the ternary adiabatic Domino JKL flip—flop is derived according to the switch-signal theory and its truth table. Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL flip—flop. Finally, the circuit is simulated by using the Spice tool and the results show that the logic function is correct. The energy consumption of the ternary adiabatic Domino JKL flip—flop is 69% less than its conventional Domino counterpart. (semiconductor integrated circuits)

  15. A low-power multi port register file design using a low-swing strategy

    International Nuclear Information System (INIS)

    Yan Hao; Liu Yan; Hua Siliang; Wang Donghui; Hou Chaohuan

    2012-01-01

    A low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power. This method contains two parts: WRITE and READ strategy. In the WRITE low-swing scheme, the modified memory cell is used to support low-swing WRITE. The modified NAND decoder not only dissipates less power, but also enables a great deal of area reduction. Compared with the conventional single-ended register file, the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately. The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy. (semiconductor integrated circuits)

  16. Advances in Modal Logic

    DEFF Research Database (Denmark)

    Modal logic is a subject with ancient roots in the western logical tradition. Up until the last few generations, it was pursued mainly as a branch of philosophy. But in recent years, the subject has taken new directions with connections to topics in computer science and mathematics. This volume...... is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...... epistemic logic, and the logic of evidence....

  17. A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems.

    Science.gov (United States)

    Wang, Zhongqiang; Ambrogio, Stefano; Balatti, Simone; Ielmini, Daniele

    2014-01-01

    Resistive (or memristive) switching devices based on metal oxides find applications in memory, logic and neuromorphic computing systems. Their small area, low power operation, and high functionality meet the challenges of brain-inspired computing aiming at achieving a huge density of active connections (synapses) with low operation power. This work presents a new artificial synapse scheme, consisting of a memristive switch connected to 2 transistors responsible for gating the communication and learning operations. Spike timing dependent plasticity (STDP) is achieved through appropriate shaping of the pre-synaptic and the post synaptic spikes. Experiments with integrated artificial synapses demonstrate STDP with stochastic behavior due to (i) the natural variability of set/reset processes in the nanoscale switch, and (ii) the different response of the switch to a given stimulus depending on the initial state. Experimental results are confirmed by model-based simulations of the memristive switching. Finally, system-level simulations of a 2-layer neural network and a simplified STDP model show random learning and recognition of patterns.

  18. Low Power Systolic Array Based Digital Filter for DSP Applications

    Directory of Open Access Journals (Sweden)

    S. Karthick

    2015-01-01

    Full Text Available Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

  19. Authenticated Encryption for Low-Power Reconfigurable Wireless Devices

    DEFF Research Database (Denmark)

    Khajuria, Samant; Andersen, Birger

    2013-01-01

    this enabling technology, these radios have to propose cryptographic services such as con- fidentiality, integrity and authentication. Therefore, integration of security services to these low-power devices is very challenging and crucial as they have limited resources and computational capabilities....... In this paper, we present a crypto solution for reconfigurable devices. The solution is a single pass Authenticated Encryption (AE) scheme that is designed for protecting both message confidentiality and its authenticity. This makes AE very attractive for low-cost low-power hardware implementation. For test...

  20. Plant operational states analysis in low power and shutdown PSA

    International Nuclear Information System (INIS)

    He Jiandong; Qiu Yongping; Zhang Qinfang; An Hongzhen; Li Maolin

    2013-01-01

    The purpose of Plant Operational States (POS) analysis is to disperse the continuous and dynamic process of low power and shutdown operation, which is the basis of developing event tree models for accident sequence analysis. According to the design of a 300 MW Nuclear Power Plant Project, operating experience and procedures of the reference plant, a detailed POS analysis is carried out based on relative criteria. Then, several kinds of POS are obtained, and the duration of each POS is calculated according to the operation records of the reference plant. The POS analysis is an important element in low power and shutdown PSA. The methodology and contents provide reference for POS analysis. (authors)

  1. Aiding operator performance at low power feedwater control

    International Nuclear Information System (INIS)

    Woods, D.D.

    1986-01-01

    Control of the feedwater system during low power operations (approximately 2% to 30% power) is a difficult task where poor performance (excessive trips) has a high cost to utilities. This paper describes several efforts in the human factors aspects of this task that are underway to improve feedwater control. A variety of knowledge acquisition techniques have been used to understand the details of what makes feedwater control at low power difficult and what knowledge and skill distinguishes expert operators at this task from less experienced ones. The results indicate that there are multiple factors that contribute to task difficulty

  2. Comparison of Preamplifiers for Low-power Consumption Design

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seung Hyun; Kim, Han Soo; Lee, Kyu Hong; Choi, Hyo Jeong; Na, Teresa W.; Ha, Jang Ho [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Chai, Jong Seo [Sungkyunkwan University, Suwon (Korea, Republic of)

    2011-10-15

    The commonly used electronic devices in radiation detector system are the preamplifier, the amplifier, ADC, and etc. to extract the signal from the detector and to process the signal. These components are composed of semiconductor devices like BJT, MOSFET, OPAMP, and etc. Performance and power consumption of these components are various according to the composition of semiconductor devices. In this study, preamplifiers, which are composed of high efficiency semiconductor devices, are compared to design low-power consumption and high performance preamplifier. To confirm the purpose, preamplifiers are designed for low-power consumption and high gain by some OPAMP (Operational Amplifier). The comparison was performed by experimental result and design simulation

  3. Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

    Science.gov (United States)

    2013-05-01

    The largest company in the world is now a technology company (Apple Inc.) whose products are all enabled by transistors [2]. Any changes, for better...increasing standby battery life. The nVidia Tegra 3 mobile processor for applications in smartphones and tablets contains five cores: one low power...white paper, NVIDIA , 2011. 14. W. G. Vandenberghe, B. Sorée, W. Magnus, G. Groeseneken, and M. V. Fischetti, “Impact of field-induced quantum

  4. EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

    Science.gov (United States)

    Demming, Anna

    2012-09-01

    behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously

  5. A low power 20 GHz comparator in 90 nm COMS technology

    Science.gov (United States)

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

    2014-05-01

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

  6. Low-power non-volatile spintronic memory: STT-RAM and beyond

    International Nuclear Information System (INIS)

    Wang, K L; Alzate, J G; Khalili Amiri, P

    2013-01-01

    The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets. (paper)

  7. Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

    Directory of Open Access Journals (Sweden)

    Tony T. Kim

    2011-07-01

    Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

  8. Radiation effects on JFETS, MOSFETS, and bipolar transistors, as related to SSC circuit design

    Energy Technology Data Exchange (ETDEWEB)

    Kennedy, E J; Gray, B; Wu, A [Dept. of Electrical and Computer Engineering, Univ. of Tennessee, Knoxville, TN (United States); Alley, G T; Britton, Jr, C L [Oak Ridge National Lab., TN (United States); Skubic, P L [Univ. of Oklahoma, Dept. of Physics and Astronomy, Norman, OK (United States)

    1991-10-01

    Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular at currents {<=} 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier. (orig.).

  9. Low Power system Design techniques for mobile computers

    NARCIS (Netherlands)

    Havinga, Paul J.M.; Smit, Gerardus Johannes Maria

    1997-01-01

    Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding

  10. Encoded low swing for ultra low power interconnect

    NARCIS (Netherlands)

    Krishnan, R.; Pineda de Gyvez, J.

    2003-01-01

    We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we

  11. Conceptual Study for development of a low power research reactor

    International Nuclear Information System (INIS)

    Park, C.; Kim, H. S.; Park, J. H.; Chae, H. T.; Lee, B. C.

    2013-01-01

    Even though the nuclear society is again facing with difficult situations after Fukusima accident, some countries still continues to consider nuclear power as one option of national energy sources and to introduce nuclear energy. As a research reactor has been regarded as a step-stone to establish infrastructures for the nuclear power development program, some countries that have plan to introduce the nuclear power energy are considering to construct a research reactor. Particularly, a low power research reactor whose main purpose is basic researches on the nuclear technology and education/training would be of interest to developing countries when taking the economy and level of science and technology into consideration. And many low power research reactors at operation are obsolescent and their numbers are decreasing. Hence, some concepts on a low power research reactor are being studied for the future needs. This paper presents the conceptual study on the basic requirements and the preliminary design features of a low power research reactor

  12. Benefits of low-power lasers on oral soft tissue

    Science.gov (United States)

    Eduardo, Carlos d. P.; Cecchini, Silvia C. M.; Cecchini, Renata C.

    1996-04-01

    The last five years have represented a great advance in relation to laser development. Countries like Japan, United States, French, England, Israel and others, have been working on the association of researches and clinical applications, in the field of laser. Low power lasers like He-Ne laser, emitting at 632,8 nm and Ga-As-Al laser, at 790 nm, have been detached acting not only as a coadjutant but some times as an specific treatment. Low power lasers provide non thermal effect at wavelengths believed to stimulate circulation and cellular activity. These lasers have been used to promote wound healing and reduce inflammation edema and pain. This work presents a five year clinical study with good results related to oral tissue healing. Oral cavity lesions, like herpes and aphthous ulcers were irradiated with Ga-Al- As laser. In both cases, an excellent result was obtained. The low power laser application decrease the painful sintomatology immediately and increase the reparation process of these lesions. An excellent result was obtained with application of low power laser in herpetic lesions associated with a secondary infection situated at the lip commissure covering the internal tissue of the mouth. The healing occurred after one week. An association of Ga-Al-As laser and Nd:YAG laser have been also proven to be good therapy for these kind of lesions. This association of low and high power laser has been done since 1992 and it seems to be a complement of the conventional therapies.

  13. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...

  14. Analytical models for low-power rectenna design

    NARCIS (Netherlands)

    Akkermans, J.A.G.; Beurden, van M.C.; Doodeman, G.J.N.; Visser, H.J.

    2005-01-01

    The design of a low-cost rectenna for low-power applications is presented. The rectenna is designed with the use of analytical models and closed-form analytical expressions. This allows for a fast design of the rectenna system. To acquire a small-area rectenna, a layered design is proposed.

  15. Application of low power X-ray tubes in geology

    International Nuclear Information System (INIS)

    Massalski, J.M.; Zaraska, W.

    1981-01-01

    Low power X-ray tubes with transmission anodes for X-ray fluorescence analysis with energy dispersion were elaborated. Paper contains experimental results of application of X-ray tubes in the apparatus for nondestructive measurements of the concentration of some elements in borehole cores. (author)

  16. Paraconsistent Computational Logic

    DEFF Research Database (Denmark)

    Jensen, Andreas Schmidt; Villadsen, Jørgen

    2012-01-01

    In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study....

  17. Microelectromechanical reprogrammable logic device

    KAUST Repository

    Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.

    2016-01-01

    on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance

  18. Stochastic coalgebraic logic

    CERN Document Server

    Doberkat, Ernst-Erich

    2009-01-01

    Combining coalgebraic reasoning, stochastic systems and logic, this volume presents the principles of coalgebraic logic from a categorical perspective. Modal logics are also discussed, including probabilistic interpretations and an analysis of Kripke models.

  19. Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

    Directory of Open Access Journals (Sweden)

    Qutaiba Alasad

    2017-09-01

    Full Text Available The outsourcing of integrated circuit (IC fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs to replace the conventional Exclusive-OR (XOR-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

  20. Classical logic and logicism in human thought

    OpenAIRE

    Elqayam, Shira

    2012-01-01

    This chapter explores the role of classical logic as a theory of human reasoning. I distinguish between classical logic as a normative, computational and algorithmic system, and review its role is theories of human reasoning since the 1960s. The thesis I defend is that psychological theories have been moving further and further away from classical logic on all three levels. I examine some prominent example of logicist theories, which incorporate logic in their psychological account, includin...

  1. Logic programming extensions of Horn clause logic

    Directory of Open Access Journals (Sweden)

    Ron Sigal

    1988-11-01

    Full Text Available Logic programming is now firmly established as an alternative programming paradigm, distinct and arguably superior to the still dominant imperative style of, for instance, the Algol family of languages. The concept of a logic programming language is not precisely defined, but it is generally understood to be characterized buy: a declarative nature; foundation in some well understood logical system, e.g., first order logic.

  2. Transistor analogs of emergent iono-neuronal dynamics.

    Science.gov (United States)

    Rachmuth, Guy; Poon, Chi-Sang

    2008-06-01

    Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

  3. Three-valued logics in modal logic

    NARCIS (Netherlands)

    Kooi, Barteld; Tamminga, Allard

    2013-01-01

    Every truth-functional three-valued propositional logic can be conservatively translated into the modal logic S5. We prove this claim constructively in two steps. First, we define a Translation Manual that converts any propositional formula of any three-valued logic into a modal formula. Second, we

  4. Evolution of the MOS transistor - From conception to VLSI

    International Nuclear Information System (INIS)

    Sah, C.T.

    1988-01-01

    Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

  5. A fast electrostatic chopper of low power consumption

    International Nuclear Information System (INIS)

    Bizzeti, P.G.; Fazzini, T.; Taccetti, N.

    1979-01-01

    An electrostatic chopper for the continuous beams of a 7.5 MV Van de Graaff accelerator is described. The electrostatic deflector uses complemetary transistors, driven by optoelectronic couplers, as voltage switches. The power consumption of the high voltage system at 30 kHz repetition frequency is approximately 3 W. Rise and fall times are symmetric and of the order of 0.4 μs. Experimental time spectra of prompt and delayed γ-rays are presented. (Auth.)

  6. Low-power-laser therapy used in tendon damage

    Science.gov (United States)

    Strupinska, Ewa

    1996-03-01

    The following paper covers evaluation of low-power laser therapy results in chronic Achilles tendon damage and external Epicondylalia (tennis elbow). Fifty patients with Achilles damage (18 women and 32 men, age average 30, 24 plus or minus 10, 39 years) and fifty patients having external Epicondyalgiae (31 women and 19 men, age average 44, 36 plus or minus 10, 88 years) have been examined. The patients were irradiated by semiconductor infrared laser wavelength 904 nm separately or together with helium-neon laser wavelength 632.8 nm. The results of therapy have been based on the patient's interviews and examinations of patients as well as on the Laitinen pain questionnaire. The results prove analgesic effects in usage of low- power laser radiation therapy can be obtained.

  7. Low-power attitude determination for magnetometry planetary missions

    DEFF Research Database (Denmark)

    Christensen, Thorbjørn Helvig

    This work covers the subject of orientation or attitude in space and on the surface of a planet. Different attitude sensor technologies have been investigated with emphasis on very low power consumption and mass. In addition robust methods for attitude determination have been covered again...... with emphasis on the limited budget onboard very small satellites. A true low-power attitude sensor using the Anisotropic Magneto Resistor effect have been designed to late prototype state. Two prototypes of the AMR magnetometer have been built. One of the prototypes has an analog output and the second...... calibration has been performed on both of the prototypes of the AMR magnetometer with very good overall result. Different attitude representations such as orthogonal matrices, Euler angles and quaternions are presented. Also methods for attitude determination of a sensor platform with more than one vector...

  8. Cost-effectiveness of low-power nuclear power plants

    International Nuclear Information System (INIS)

    Mitenkov, F.M.; Vostokov, V.S.; Drozhkin, V.N.; Samoilov, O.B.

    1994-01-01

    Many potential consumers of electricity and heat, consuming several thousands of kilowatts (up to 10-15 MW), have now been identified. This is significant primarily for regions far from power grids and other centralized sources of energy, such as, for example, Yakutiya, Northeastern Siberia, and elsewhere. These consumers are now supplied with fossil fuel, which is often difficult and expensive to deliver. For this reason it is very important to develop low-power nuclear power plants for remote regions

  9. Capacity of Fading Channels in the Low Power Regime

    KAUST Repository

    Benkhelifa, Fatma

    2013-01-01

    The low power regime has attracted various researchers in the information theory and communication communities to understand the performance limits of wireless systems. Indeed, the energy consumption is becoming one of the major limiting factors in wireless systems. As such, energy-efficient wireless systems are of major importance to the next generation wireless systems designers. The capacity is a metric that measures the performance limit of a wireless system. The study of the ergodic capacity of some fading channels in the low power regime is the main subject of this thesis. In our study, we consider that the receiver has always a full knowledge of the channel state information. However, we assume that the transmitter has possibly imperfect knowledge of the channel state information, i.e. he knows either perfectly the channel or only an estimated version of the channel. Both radio frequency and free space optical communication channel models are considered. The main contribution of this work is the explicit characterization of how the capacity scales as function of the signal-to-noise ratio in the low power regime. This allows us to characterize the gain due to the perfect knowledge compared to no knowledge of the channel state information at the transmitter. In particular, we show that the gain increases logarithmically for radio frequency communication. However, the gain increases as log2(Pavg) or log4(Pavg) for free-space optical communication, where Pavg is the average power constraint imposed to the input. Furthermore, we characterize the capacity of cascaded fading channels and we applied the result to Rayleigh-product fading channel and to a free-space optical link over gamma-gamma atmospheric turbulence in the presence of pointing errors. Finally, we study the capacity of Nakagami-m fading channel under quality of service constraints, namely the effective capacity. We have shown that the effective capacity converges to Shannon capacity in the very low

  10. Remarks on building of low-powered airplanes

    Science.gov (United States)

    Langsdorff, Werner V

    1924-01-01

    If the low-powered airplane is to be used advantageously by private individuals, the most important consideration is a smaller fuel consumption and, hence, a lower engine power. From experiments with gliders, it appears entirely possible, by utilizing ascending winds (on the weather side of mountains and those generated by the heat of the sun) and by employing engine flight intermittently, as required to fly long distances over land.

  11. Characteristics of the low power cylindrical anode layer ion source

    International Nuclear Information System (INIS)

    Zhao Jie; Tang Deli; Cheng Changming; Geng Shaofei

    2009-01-01

    A low power cylindrical anode layer ion source and its working characteristic, and the beam distribution are introduced. This ion source has two working states, emanative state and collimated state, and the normal parameters of this system are: working voltage 200-1200 V, discharge current 0.1-1.4A, air pressure 1.9 x 10 -2 -1.7 x 10 -1 Pa, gas flow 5-20 sccm. (authors)

  12. An Electronic System for Ultra-low Power Hearing Implants

    Science.gov (United States)

    2013-02-15

    Battery Charger Circuit ," IEEE Transactions on Biomedical Circuits and Systems, Vol. 5, No.2, pp. 131-137,2011. [6] K. H. Wee, L. Turicchia, and R...analyzers [1], [2], useful in several hearing systems. 4) We have designed and built a lithium-ion battery -recharging circuit that exploits a novel analog...lab and the use of intelligent low-power filters and circuits have been successful in reducing noise exposure while improving speech intelligibility

  13. Quantifiers for quantum logic

    OpenAIRE

    Heunen, Chris

    2008-01-01

    We consider categorical logic on the category of Hilbert spaces. More generally, in fact, any pre-Hilbert category suffices. We characterise closed subobjects, and prove that they form orthomodular lattices. This shows that quantum logic is just an incarnation of categorical logic, enabling us to establish an existential quantifier for quantum logic, and conclude that there cannot be a universal quantifier.

  14. Ultra low power signal oriented approach for wireless health monitoring.

    Science.gov (United States)

    Marinkovic, Stevan; Popovici, Emanuel

    2012-01-01

    In recent years there is growing pressure on the medical sector to reduce costs while maintaining or even improving the quality of care. A potential solution to this problem is real time and/or remote patient monitoring by using mobile devices. To achieve this, medical sensors with wireless communication, computational and energy harvesting capabilities are networked on, or in, the human body forming what is commonly called a Wireless Body Area Network (WBAN). We present the implementation of a novel Wake Up Receiver (WUR) in the context of standardised wireless protocols, in a signal-oriented WBAN environment and present a novel protocol intended for wireless health monitoring (WhMAC). WhMAC is a TDMA-based protocol with very low power consumption. It utilises WBAN-specific features and a novel ultra low power wake up receiver technology, to achieve flexible and at the same time very low power wireless data transfer of physiological signals. As the main application is in the medical domain, or personal health monitoring, the protocol caters for different types of medical sensors. We define four sensor modes, in which the sensors can transmit data, depending on the sensor type and emergency level. A full power dissipation model is provided for the protocol, with individual hardware and application parameters. Finally, an example application shows the reduction in the power consumption for different data monitoring scenarios.

  15. Nanophotonic quantum computer based on atomic quantum transistor

    International Nuclear Information System (INIS)

    Andrianov, S N; Moiseev, S A

    2015-01-01

    We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

  16. Nanophotonic quantum computer based on atomic quantum transistor

    Energy Technology Data Exchange (ETDEWEB)

    Andrianov, S N [Institute of Advanced Research, Academy of Sciences of the Republic of Tatarstan, Kazan (Russian Federation); Moiseev, S A [Kazan E. K. Zavoisky Physical-Technical Institute, Kazan Scientific Center, Russian Academy of Sciences, Kazan (Russian Federation)

    2015-10-31

    We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

  17. Improving the positive feedback adiabatic logic familiy

    Directory of Open Access Journals (Sweden)

    J. Fischer

    2004-01-01

    Full Text Available Positive Feedback Adiabatic Logic (PFAL shows the lowest energy dissipation among adiabatic logic families based on cross-coupled transistors, due to the reduction of both adiabatic and non-adiabatic losses. The dissipation primarily depends on the resistance of the charging path, which consists of a single p-channel MOSFET during the recovery phase. In this paper, a new logic family called Improved PFAL (IPFAL is proposed, where all n- and pchannel devices are swapped so that the charge can be recovered through an n-channel MOSFET. This allows to decrease the resistance of the charging path up to a factor of 2, and it enables a significant reduction of the energy dissipation. Simulations based on a 0.13µm CMOS process confirm the improvements in terms of power consumption over a large frequency range. However, the same simple design rule, which enables in PFAL an additional reduction of the dissipation by optimal transistor sizing, does not apply to IPFAL. Therefore, the influence of several sources of dissipation for a generic IPFAL gate is illustrated and discussed, in order to lower the power consumption and achieve better performance.

  18. Radiation damage to integrated injection logic cells

    International Nuclear Information System (INIS)

    Pease, R.L.; Galloway, K.F.; Stehlin, R.A.

    1975-01-01

    The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (l 2 L) cell and an l 2 L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed

  19. 47 CFR 74.710 - Digital low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.710 Digital low power TV and TV translator station protection. (a) An application to construct a new low power TV, TV translator, or TV...

  20. 47 CFR 74.795 - Digital low power TV and TV translator transmission system facilities.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.795 Digital low power TV and TV translator transmission system facilities. (a) A digital low power TV or TV translator station shall operate...

  1. 47 CFR 74.792 - Digital low power TV and TV translator station protected contour.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.792 Digital low power TV and TV translator station protected contour. (a) A digital low power TV or TV translator will be protected from...

  2. 47 CFR 74.707 - Low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.707 Low power TV and TV translator station protection. (a)(1) A low power TV or TV translator will be protected from interference from other...

  3. Metamathematics of fuzzy logic

    CERN Document Server

    Hájek, Petr

    1998-01-01

    This book presents a systematic treatment of deductive aspects and structures of fuzzy logic understood as many valued logic sui generis. Some important systems of real-valued propositional and predicate calculus are defined and investigated. The aim is to show that fuzzy logic as a logic of imprecise (vague) propositions does have well-developed formal foundations and that most things usually named `fuzzy inference' can be naturally understood as logical deduction.

  4. What are Institutional Logics

    OpenAIRE

    Berg Johansen, Christina; Bock Waldorff, Susanne

    2015-01-01

    This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guided by institutional logics, as well as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to...

  5. Low swing differential logic for mixed signal applications

    International Nuclear Information System (INIS)

    Fischer, P.; Kraft, E.

    2004-01-01

    Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power

  6. Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

    Science.gov (United States)

    Ayyoub, Slimani; Achour, Benslama

    2017-08-01

    Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

  7. Silicon photonic crystal all-optical logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

    2013-01-03

    All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

  8. HDL to verification logic translator

    Science.gov (United States)

    Gambles, J. W.; Windley, P. J.

    1992-01-01

    The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

  9. Silicon heterojunction transistor

    International Nuclear Information System (INIS)

    Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

    1979-01-01

    SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

  10. Design Techniques for Power-Aware Combinational Logic SER Mitigation

    Science.gov (United States)

    Mahatme, Nihaar N.

    SEUs. This was mainly because the operating frequencies were much lower for older technology generations. The Intel Pentium II for example was fabricated using 0.35 microm technology and operated between 200-330 MHz. With technology scaling however, operating frequencies have increased tremendously and the contribution of soft errors due to latched SETs from combinational logic could account for a significant proportion of the chip-level soft error rate [Sief-12][Maha-11][Shiv02] [Bu97]. Therefore there is a need to systematically characterize the problem of combinational logic single-event effects (SEE) and understand the various factors that affect the combinational logic single-event error rate. Just as scaling has led to soft errors emerging as a reliability-limiting failure mode for modern digital ICs, the problem of increasing power consumption has arguably been a bigger bane of scaling. While Moore's Law loftily states the blessing of technology scaling to be smaller and faster transistor it fails to highlight that the power density increases exponentially with every technology generation. The power density problem was partially solved in the 1970's and 1980's by moving from bipolar and GaAs technologies to full-scale silicon CMOS technologies. Following this however, technology miniaturization that enabled high-speed, multicore and parallel computing has steadily increased the power density and the power consumption problem. Today minimizing the power consumption is as much critical for power hungry server farms as it for portable devices, all pervasive sensor networks and future eco-bio-sensors. Low-power consumption is now regularly part of design philosophies for various digital products with diverse applications from computing to communication to healthcare. Thus designers in today's world are left grappling with both a "power wall" as well as a "reliability wall". Unfortunately, when it comes to improving reliability through soft error mitigation, most

  11. Computational logic with square rings of nanomagnets

    Science.gov (United States)

    Arava, Hanu; Derlet, Peter M.; Vijayakumar, Jaianth; Cui, Jizhai; Bingham, Nicholas S.; Kleibert, Armin; Heyderman, Laura J.

    2018-06-01

    Nanomagnets are a promising low-power alternative to traditional computing. However, the successful implementation of nanomagnets in logic gates has been hindered so far by a lack of reliability. Here, we present a novel design with dipolar-coupled nanomagnets arranged on a square lattice to (i) support transfer of information and (ii) perform logic operations. We introduce a thermal protocol, using thermally active nanomagnets as a means to perform computation. Within this scheme, the nanomagnets are initialized by a global magnetic field and thermally relax on raising the temperature with a resistive heater. We demonstrate error-free transfer of information in chains of up to 19 square rings and we show a high level of reliability with successful gate operations of ∼94% across more than 2000 logic gates. Finally, we present a functionally complete prototype NAND/NOR logic gate that could be implemented for advanced logic operations. Here we support our experiments with simulations of the thermally averaged output and determine the optimal gate parameters. Our approach provides a new pathway to a long standing problem concerning reliability in the use of nanomagnets for computation.

  12. Connections among quantum logics

    International Nuclear Information System (INIS)

    Lock, P.F.; Hardegree, G.M.

    1985-01-01

    In this paper, a theory of quantum logics is proposed which is general enough to enable us to reexamine a previous work on quantum logics in the context of this theory. It is then easy to assess the differences between the different systems studied. The quantum logical systems which are incorporated are divided into two groups which we call ''quantum propositional logics'' and ''quantum event logics''. The work of Kochen and Specker (partial Boolean algebras) is included and so is that of Greechie and Gudder (orthomodular partially ordered sets), Domotar (quantum mechanical systems), and Foulis and Randall (operational logics) in quantum propositional logics; and Abbott (semi-Boolean algebras) and Foulis and Randall (manuals) in quantum event logics, In this part of the paper, an axiom system for quantum propositional logics is developed and the above structures in the context of this system examined. (author)

  13. Circuits and Systems for Low-Power Miniaturized Wireless Sensors

    Science.gov (United States)

    Nagaraju, Manohar

    The field of electronic sensors has witnessed a tremendous growth over the last decade particularly with the proliferation of mobile devices. New applications in Internet of Things (IoT), wearable technology, are further expected to fuel the demand for sensors from current numbers in the range of billions to trillions in the next decade. The main challenges for a trillion sensors are continued miniaturization, low-cost and large-scale manufacturing process, and low power consumption. Traditional integration and circuit design techniques in sensor systems are not suitable for applications in smart dust, IoT etc. The first part of this thesis demonstrates an example sensor system for biosignal recording and illustrates the tradeoffs in the design of low-power miniaturized sensors. The different components of the sensor system are integrated at the board level. The second part of the thesis demonstrates fully integrated sensors that enable extreme miniaturization of a sensing system with the sensor element, processing circuitry, a frequency reference for communication and the communication circuitry in a single hermetically sealed die. Design techniques to reduce the power consumption of the sensor interface circuitry at the architecture and circuit level are demonstrated. The principles are used to design sensors for two of the most common physical variables, mass and pressure. A low-power wireless mass and pressure sensor suitable for a wide variety of biological/chemical sensing applications and Tire Pressure Monitoring Systems (TPMS) respectively are demonstrated. Further, the idea of using high-Q resonators for a Voltage Controlled Oscillator (VCO) is proposed and a low-noise, wide bandwidth FBAR-based VCO is presented.

  14. Silicon nanowire transistors

    CERN Document Server

    Bindal, Ahmet

    2016-01-01

    This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

  15. Organic electrochemical transistors

    KAUST Repository

    Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Ró isí n M.; Berggren, Magnus; Malliaras, George G.

    2018-01-01

    Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume

  16. Assessment of nuclear reactor concepts for low power space applications

    Science.gov (United States)

    Klein, Andrew C.; Gedeon, Stephen R.; Morey, Dennis C.

    1988-01-01

    The results of a preliminary small reactor concepts feasibility and safety evaluation designed to provide a first order validation of the nuclear feasibility and safety of six small reactor concepts are given. These small reactor concepts have potential space applications for missions in the 1 to 20 kWe power output range. It was concluded that low power concepts are available from the U.S. nuclear industry that have the potential for meeting both the operational and launch safety space mission requirements. However, each design has its uncertainties, and further work is required. The reactor concepts must be mated to a power conversion technology that can offer safe and reliable operation.

  17. EXPERIMENTAL INVESTIGATION OF AN AIR CHARGED LOW POWERED STIRLING ENGINE

    Directory of Open Access Journals (Sweden)

    Can ÇINAR

    2004-01-01

    Full Text Available In this study, an air charged, low powered manufactured ? type Stirling engine was investigated experimentally. Tests were conducted at 800, 900 and 1000 °C hot source temperatures, 1, 1.5, 2, 2.5, 3, 3.5 bars air charge pressure. The variation of engine power depending on the charge pressure and hot source temperature for two different heat transfer area was investigated experimentally. Maximum output power was obtained at 1000 °C and 3 bars charge pressure as 58 W at 441 rpm. Engine speed was reached at 846 rpm without load.

  18. Extreme low-power mixed signal IC design

    CERN Document Server

    Tajalli, Armin

    2010-01-01

    This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical ""subthreshold CMOS"" techniques. This book introduces a new family of ""subthreshold circuits"" called ""source-coupled circuits"". This family of circuits can be used for implementing digita

  19. Ultra-low-power short-range radios

    CERN Document Server

    Chandrakasan, Anantha

    2015-01-01

    This book explores the design of ultra-low-power radio-frequency integrated circuits (RFICs), with communication distances ranging from a few centimeters to a few meters. Such radios have unique challenges compared to longer-range, higher-powered systems. As a result, many different applications are covered, ranging from body-area networks to transcutaneous implant communications and Internet-of-Things devices. A mix of introductory and cutting-edge design techniques and architectures which facilitate each of these applications are discussed in detail. Specifically, this book covers:.

  20. Low-power signal processing devices for portable ECG detection.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Cheng, Chih-Jen; Wang, Cheng-Pin; Kao, Wei-Chun

    2008-01-01

    An analog front end for diagnosing and monitoring the behavior of the heart is presented. This sensing front end has two low-power processing devices, including a 5(th)-order Butterworth operational transconductance-C (OTA-C) filter and an 8-bit successive approximation analog-to-digital converter (SAADC). The components fabricated in a 0.18-microm CMOS technology feature with power consumptions of 453 nW (filter) and 940 nW (ADC) at a supply voltage of 1 V, respectively. The system specifications in terms of output noise and linearity associated with the two integrated circuits are described in this paper.

  1. Standard filter approximations for low power Continuous Wavelet Transforms.

    Science.gov (United States)

    Casson, Alexander J; Rodriguez-Villegas, Esther

    2010-01-01

    Analogue domain implementations of the Continuous Wavelet Transform (CWT) have proved popular in recent years as they can be implemented at very low power consumption levels. This is essential for use in wearable, long term physiological monitoring systems. Present analogue CWT implementations rely on taking mathematical a approximation of the wanted mother wavelet function to give a filter transfer function that is suitable for circuit implementation. This paper investigates the use of standard filter approximations (Butterworth, Chebyshev, Bessel) as an alternative wavelet approximation technique. This extends the number of approximation techniques available for generating analogue CWT filters. An example ECG analysis shows that signal information can be successfully extracted using these CWT approximations.

  2. A low power ADS for transmutation studies in fast systems

    Science.gov (United States)

    Panza, Fabio; Firpo, Gabriele; Lomonaco, Guglielmo; Osipenko, Mikhail; Ricco, Giovanni; Ripani, Marco; Saracco, Paolo; Viberti, Carlo Maria

    2017-12-01

    In this work, we report studies on a fast low power accelerator driven system model as a possible experimental facility, focusing on its capabilities in terms of measurement of relevant integral nuclear quantities. In particular, we performed Monte Carlo simulations of minor actinides and fission products irradiation and estimated the fission rate within fission chambers in the reactor core and the reflector, in order to evaluate the transmutation rates and the measurement sensitivity. We also performed a photo-peak analysis of available experimental data from a research reactor, in order to estimate the expected sensitivity of this analysis method on the irradiation of samples in the ADS considered.

  3. Design of low-power coarse-grained reconfigurable architectures

    CERN Document Server

    Kim, Yoonjin

    2010-01-01

    Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks.The first half of the book explains how to reduce power in the configuration cache. T

  4. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  5. Speed of sound in biodiesel produced by low power ultrasound

    Science.gov (United States)

    Oliveira, P. A.; Silva, R. M. B.; Morais, G. C.; Alvarenga, A. V.; Costa-Felix, R. P. B.

    2018-03-01

    The quality control of the biodiesel produced is an important issue to be addressed for every manufacturer or retailer. The speed of sound is a property that has an influence on the quality of the produced fuel. This work presents the evaluation about the speed of sound in biodiesel produced with the aid of low power ultrasound in the frequencies of 1 MHz and 3 MHz. The speed of sound was measured by pulse-echo technique. The ultrasonic frequency used during reaction affects the speed of sound in biodiesel. The larger expanded uncertainty for adjusted curve was 4.9 m.s-1.

  6. LOW-POWER AC LOADS AND ELECTRICAL POWER QUALITY

    Directory of Open Access Journals (Sweden)

    EPURE S.

    2016-12-01

    Full Text Available This paper deals with experimental study and numerical simulation of single phase AC low power loads: artificial light sources, personal computers, refrigeration units, air conditioning units and TV receivers. These loads are in such large numbers that represents the main source of disturbances (harmonic current, reactive power and unbalanced three-phase network. The obtained simulation models, verified by comparison with experimental results may be used in larger simulation models for testing and sizing the optimum parameters of active power filters. Models can also be used to study the interactions between grid elements and various loads or situations.

  7. Structural Logical Relations

    DEFF Research Database (Denmark)

    Schürmann, Carsten; Sarnat, Jeffrey

    2008-01-01

    Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics......, such as Twelf, and yet they are often straightforward in proof assistants with stronger meta-logics. In this paper, we propose structural logical relations as a technique for conducting these proofs in systems with limited meta-logical strength by explicitly representing and reasoning about an auxiliary logic...

  8. What are Institutional Logics

    DEFF Research Database (Denmark)

    Berg Johansen, Christina; Waldorff, Susanne Boch

    This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...

  9. Indeterministic Temporal Logic

    Directory of Open Access Journals (Sweden)

    Trzęsicki Kazimierz

    2015-09-01

    Full Text Available The questions od determinism, causality, and freedom have been the main philosophical problems debated since the beginning of temporal logic. The issue of the logical value of sentences about the future was stated by Aristotle in the famous tomorrow sea-battle passage. The question has inspired Łukasiewicz’s idea of many-valued logics and was a motive of A. N. Prior’s considerations about the logic of tenses. In the scheme of temporal logic there are different solutions to the problem. In the paper we consider indeterministic temporal logic based on the idea of temporal worlds and the relation of accessibility between them.

  10. Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

    International Nuclear Information System (INIS)

    Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

    2010-01-01

    Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

  11. Impact of field-induced quantum confinement on the onset of tunneling field-effect transistors: Experimental verification

    Energy Technology Data Exchange (ETDEWEB)

    Smets, Quentin, E-mail: quentin.smets@imec.be; Verreck, Devin; Heyns, Marc M. [Imec, Kapeldreef 75, 3001 Heverlee (Belgium); KULeuven, 3000 Leuven (Belgium); Verhulst, Anne S.; Martens, Koen; Lin, Han Chung; Kazzi, Salim El; Simoen, Eddy; Collaert, Nadine; Thean, Aaron [Imec, Kapeldreef 75, 3001 Heverlee (Belgium); Raskin, Jean-Pierre [ICTEAM, Université catholique de Louvain, 1348 Louvain-la-Neuve (Belgium)

    2014-11-17

    The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band.

  12. Impact of field-induced quantum confinement on the onset of tunneling field-effect transistors: Experimental verification

    International Nuclear Information System (INIS)

    Smets, Quentin; Verreck, Devin; Heyns, Marc M.; Verhulst, Anne S.; Martens, Koen; Lin, Han Chung; Kazzi, Salim El; Simoen, Eddy; Collaert, Nadine; Thean, Aaron; Raskin, Jean-Pierre

    2014-01-01

    The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band

  13. Quantum Logic as a Dynamic Logic

    NARCIS (Netherlands)

    Baltag, A.; Smets, S.

    We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear “no”.

  14. Quantum logic as a dynamic logic

    NARCIS (Netherlands)

    Baltag, Alexandru; Smets, Sonja

    We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear "no".

  15. Transforming equality logic to propositional logic

    NARCIS (Netherlands)

    Zantema, H.; Groote, J.F.

    2003-01-01

    Abstract We investigate and compare various ways of transforming equality formulas to propositional formulas, in order to be able to solve satisfiability in equality logic by means of satisfiability in propositional logic. We propose equality substitution as a new approach combining desirable

  16. A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

    Directory of Open Access Journals (Sweden)

    Sumitra Singar

    2018-01-01

    Full Text Available Dual edge triggered (DET techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

  17. Designing an Inverter-based Operational Transconductance Amplifier-capacitor Filter with Low Power Consumption for Biomedical Applications.

    Science.gov (United States)

    Yousefinezhad, Sajad; Kermani, Saeed; Hosseinnia, Saeed

    2018-01-01

    The operational transconductance amplifier-capacitor (OTA-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal OTA-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal OTA-C filter was designed based on the minimum number of transconductance blocks and an inverter circuit by three transconductance blocks (OTA).

  18. Validation of a Portable Low-Power Deep Brain Stimulation Device Through Anxiolytic Effects in a Laboratory Rat Model.

    Science.gov (United States)

    Kouzani, Abbas Z; Kale, Rajas P; Zarate-Garza, Pablo Patricio; Berk, Michael; Walder, Ken; Tye, Susannah J

    2017-09-01

    Deep brain stimulation (DBS) devices deliver electrical pulses to neural tissue through an electrode. To study the mechanisms and therapeutic benefits of deep brain stimulation, murine preclinical research is necessary. However, conducting naturalistic long-term, uninterrupted animal behavioral experiments can be difficult with bench-top systems. The reduction of size, weight, power consumption, and cost of DBS devices can assist the progress of this research in animal studies. A low power, low weight, miniature DBS device is presented in this paper. This device consists of electronic hardware and software components including a low-power microcontroller, an adjustable current source, an n-channel metal-oxide-semiconductor field-effect transistor, a coin-cell battery, electrode wires and a software program to operate the device. Evaluation of the performance of the device in terms of battery lifetime and device functionality through bench and in vivo tests was conducted. The bench test revealed that this device can deliver continuous stimulation current pulses of strength [Formula: see text], width [Formula: see text], and frequency 130 Hz for over 22 days. The in vivo tests demonstrated that chronic stimulation of the nucleus accumbens (NAc) with this device significantly increased psychomotor activity, together with a dramatic reduction in anxiety-like behavior in the elevated zero-maze test.

  19. Parametrization of the radiation induced leakage current increase of NMOS transistors

    CERN Document Server

    Backhaus, Malte

    2017-01-13

    The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

  20. System Control Applications of Low-Power Radio Frequency Devices

    Science.gov (United States)

    van Rensburg, Roger

    2017-09-01

    This paper conceptualizes a low-power wireless sensor network design for application employment to reduce theft of portable computer devices used in educational institutions today. The aim of this study is to design and develop a reliable and robust wireless network that can eradicate accessibility of a device’s human interface. An embedded system supplied by an energy harvesting source, installed on the portable computer device, may represent one of multiple slave nodes which request regular updates from a standalone master station. A portable computer device which is operated in an undesignated area or in a field perimeter where master to slave communication is restricted, indicating a possible theft scenario, will initiate a shutdown of its operating system and render the device unusable. Consequently, an algorithm in the device firmware may ensure the necessary steps are executed to track the device, irrespective whether the device is enabled. Design outcomes thus far indicate that a wireless network using low-power embedded hardware, is feasible for anti-theft applications. By incorporating one of the latest Bluetooth low-energy, ANT+, ZigBee or Thread wireless technologies, an anti-theft system may be implemented that has the potential to reduce major portable computer device theft in institutions of digitized learning.

  1. Random Sequence for Optimal Low-Power Laser Generated Ultrasound

    Science.gov (United States)

    Vangi, D.; Virga, A.; Gulino, M. S.

    2017-08-01

    Low-power laser generated ultrasounds are lately gaining importance in the research world, thanks to the possibility of investigating a mechanical component structural integrity through a non-contact and Non-Destructive Testing (NDT) procedure. The ultrasounds are, however, very low in amplitude, making it necessary to use pre-processing and post-processing operations on the signals to detect them. The cross-correlation technique is used in this work, meaning that a random signal must be used as laser input. For this purpose, a highly random and simple-to-create code called T sequence, capable of enhancing the ultrasound detectability, is introduced (not previously available at the state of the art). Several important parameters which characterize the T sequence can influence the process: the number of pulses Npulses , the pulse duration δ and the distance between pulses dpulses . A Finite Element FE model of a 3 mm steel disk has been initially developed to analytically study the longitudinal ultrasound generation mechanism and the obtainable outputs. Later, experimental tests have shown that the T sequence is highly flexible for ultrasound detection purposes, making it optimal to use high Npulses and δ but low dpulses . In the end, apart from describing all phenomena that arise in the low-power laser generation process, the results of this study are also important for setting up an effective NDT procedure using this technology.

  2. Low-power cryptographic coprocessor for autonomous wireless sensor networks

    Science.gov (United States)

    Olszyna, Jakub; Winiecki, Wiesław

    2013-10-01

    The concept of autonomous wireless sensor networks involves energy harvesting, as well as effective management of system resources. Public-key cryptography (PKC) offers the advantage of elegant key agreement schemes with which a secret key can be securely established over unsecure channels. In addition to solving the key management problem, the other major application of PKC is digital signatures, with which non-repudiation of messages exchanges can be achieved. The motivation for studying low-power and area efficient modular arithmetic algorithms comes from enabling public-key security for low-power devices that can perform under constrained environment like autonomous wireless sensor networks. This paper presents a cryptographic coprocessor tailored to the autonomous wireless sensor networks constraints. Such hardware circuit is aimed to support the implementation of different public-key cryptosystems based on modular arithmetic in GF(p) and GF(2m). Key components of the coprocessor are described as GEZEL models and can be easily transformed to VHDL and implemented in hardware.

  3. Low Power Multi-Hop Networking Analysis in Intelligent Environments.

    Science.gov (United States)

    Etxaniz, Josu; Aranguren, Gerardo

    2017-05-19

    Intelligent systems are driven by the latest technological advances in many different areas such as sensing, embedded systems, wireless communications or context recognition. This paper focuses on some of those areas. Concretely, the paper deals with wireless communications issues in embedded systems. More precisely, the paper combines the multi-hop networking with Bluetooth technology and a quality of service (QoS) metric, the latency. Bluetooth is a radio license-free worldwide communication standard that makes low power multi-hop wireless networking available. It establishes piconets (point-to-point and point-to-multipoint links) and scatternets (multi-hop networks). As a result, many Bluetooth nodes can be interconnected to set up ambient intelligent networks. Then, this paper presents the results of the investigation on multi-hop latency with park and sniff Bluetooth low power modes conducted over the hardware test bench previously implemented. In addition, the empirical models to estimate the latency of multi-hop communications over Bluetooth Asynchronous Connectionless Links (ACL) in park and sniff mode are given. The designers of devices and networks for intelligent systems will benefit from the estimation of the latency in Bluetooth multi-hop communications that the models provide.

  4. Wake-up receiver based ultra-low-power WBAN

    CERN Document Server

    Lont, Maarten; Roermund, Arthur van

    2014-01-01

    This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.   • Provides an overview of wireless body area network design from the network layer to the circuit implementation, and an overview of the cross-layer design trade-offs; • Discusses design at both the network or MAC-layer and circuit-level, with an emphasis on circuit design; • Covers the design of low-power frequency shift keying (FSK) wake-up-receivers; • Validates theory presented with two different recei...

  5. Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

    Science.gov (United States)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2014-05-07

    Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

  6. Many-valued logics

    CERN Document Server

    Bolc, Leonard

    1992-01-01

    Many-valued logics were developed as an attempt to handle philosophical doubts about the "law of excluded middle" in classical logic. The first many-valued formal systems were developed by J. Lukasiewicz in Poland and E.Post in the U.S.A. in the 1920s, and since then the field has expanded dramatically as the applicability of the systems to other philosophical and semantic problems was recognized. Intuitionisticlogic, for example, arose from deep problems in the foundations of mathematics. Fuzzy logics, approximation logics, and probability logics all address questions that classical logic alone cannot answer. All these interpretations of many-valued calculi motivate specific formal systems thatallow detailed mathematical treatment. In this volume, the authors are concerned with finite-valued logics, and especially with three-valued logical calculi. Matrix constructions, axiomatizations of propositional and predicate calculi, syntax, semantic structures, and methodology are discussed. Separate chapters deal w...

  7. Against Logical Form

    Directory of Open Access Journals (Sweden)

    P N Johnson-Laird

    2010-10-01

    Full Text Available An old view in logic going back to Aristotle is that an inference is valid in virtue of its logical form. Many psychologists have adopted the same point of view about human reasoning: the first step is to recover the logical form of an inference, and the second step is to apply rules of inference that match these forms in order to prove that the conclusion follows from the premises. The present paper argues against this idea. The logical form of an inference transcends the grammatical forms of the sentences used to express it, because logical form also depends on context. Context is not readily expressed in additional premises. And the recovery of logical form leads ineluctably to the need for infinitely many axioms to capture the logical properties of relations. An alternative theory is that reasoning depends on mental models, and this theory obviates the need to recover logical form.

  8. Logic an introductory course

    CERN Document Server

    Newton-Smith, WH

    2003-01-01

    A complete introduction to logic for first-year university students with no background in logic, philosophy or mathematics. In easily understood steps it shows the mechanics of the formal analysis of arguments.

  9. Anticoincidence logic using PALs

    International Nuclear Information System (INIS)

    Bolanos, L.; Arista Romeu, E.

    1997-01-01

    This paper describes the functioning principle of an anticoincidence logic and a design of this based on programing logic. The circuit was included in a discriminator of an equipment for single-photon absorptiometry

  10. Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature

    KAUST Repository

    Pattanasattayavong, Pichaya; Yaacobi-Gross, Nir; Zhao, Kui; Ndjawa, Guy Olivier Ngongang; Li, Jinhua; Yan, Feng; O'Regan, Brian C.; Amassian, Aram; Anthopoulos, Thomas D.

    2012-01-01

    ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm2 V-1 s-1. By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. Copyright © 2013 WILEY

  11. Connections among quantum logics

    International Nuclear Information System (INIS)

    Lock, P.F.; Hardegree, G.M.

    1985-01-01

    This paper gives a brief introduction to the major areas of work in quantum event logics: manuals (Foulis and Randall) and semi-Boolean algebras (Abbott). The two theories are compared, and the connection between quantum event logics and quantum propositional logics is made explicit. In addition, the work on manuals provides us with many examples of results stated in Part I. (author)

  12. Equational type logic

    NARCIS (Netherlands)

    Manca, V.; Salibra, A.; Scollo, Giuseppe

    1990-01-01

    Equational type logic is an extension of (conditional) equational logic, that enables one to deal in a single, unified framework with diverse phenomena such as partiality, type polymorphism and dependent types. In this logic, terms may denote types as well as elements, and atomic formulae are either

  13. Concurrent weighted logic

    DEFF Research Database (Denmark)

    Xue, Bingtian; Larsen, Kim Guldstrand; Mardare, Radu Iulian

    2015-01-01

    We introduce Concurrent Weighted Logic (CWL), a multimodal logic for concurrent labeled weighted transition systems (LWSs). The synchronization of LWSs is described using dedicated functions that, in various concurrency paradigms, allow us to encode the compositionality of LWSs. To reflect these......-completeness results for this logic. To complete these proofs we involve advanced topological techniques from Model Theory....

  14. Real Islamic Logic

    NARCIS (Netherlands)

    Bergstra, J.A.

    2011-01-01

    Four options for assigning a meaning to Islamic Logic are surveyed including a new proposal for an option named "Real Islamic Logic" (RIL). That approach to Islamic Logic should serve modern Islamic objectives in a way comparable to the functionality of Islamic Finance. The prospective role of RIL

  15. Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

    Science.gov (United States)

    Geier, Michael

    symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

  16. Biophysical basis of low-power-laser effects

    Science.gov (United States)

    Karu, Tiina I.

    1996-06-01

    Biological responses of cells to visible and near IR (laser) radiation occur due to physical and/or chemical changes in photoacceptor molecules, components of respiratory chains (cyt a/a3 in mitochondria). As a result of the photoexcitation of electronic states, the following physical and/or chemical changes can occur: alteration of redox properties and acceleration of electron transfer, changes in biochemical activity due to local transient heating of chromophores, one-electron auto-oxidation and O2- production, and photodynamic action and 1O2 production. Different reaction channels can be activated to achieve the photobiological macroeffect. The primary physical and/or chemical changes induced by light in photoacceptor molecules are followed by a cascade of biochemical reactions in the cell that do not need further light activation and occur in the dark (photosignal transduction and amplification chains). These actions are connected with changes in cellular homeostasis parameters. The crucial step here is thought to be an alteration of the cellular redox state: a shift towards oxidation is associated with stimulation of cellular vitality, and a shift towards reduction is linked to inhibition. Cells with a lower than normal pH, where the redox state is shifted in the reduced direction, are considered to be more sensitive to the stimulative action of light than those with the respective parameters being optimal or near optimal. This circumstance explains the possible variations in observed magnitudes of low-power laser effects. Light action on the redox state of a cell via the respiratory chain also explains the diversity of low-power laser effects. Beside explaining many controversies in the field of low-power laser effects (i.e., the diversity of effects, the variable magnitude or absence of effects in certain studies), the proposed redox-regulation mechanism may be a fundamental explanation for some clinical effects of irradiation, for example the positive

  17. [Low power laser biostimulation in the treatment of bronchial asthma].

    Science.gov (United States)

    Milojević, Momir; Kuruc, Vesna

    2003-01-01

    Modern concept of acupuncture is based on the fact there are designated locations on the surface of human body, which are related to integrative systems of an organism by means of sensory nerves, correlating and synchronizing organ functioning, depending on external and internal conditions, by means of nervous and neurohumoral regulation of metabolic and regenerative processes, including also mobilisation of immunological, protective and antistress reactions. Apart from standard needle acupuncture, other methods of stimulating acupuncture points are also applied. Due to invention of low power lasers, irradiation laser acupuncture has been introduced into routine medical practice, characterised by painless and aseptic technique and outstanding clinical results. The investigation was aimed at defining therapeutic effects of low power laser irradiation by stimulating acupuncture points or local treatment of asthma. A prospective analysis included 50 patients treated at the Institute of Pulmonary Diseases in Sremska Kamenica during 2000, 2001 and 2002. Together with conservative treatment of present disease, these patients were treated with laser stimulation of acupuncture points in duration of ten days. During treatment changes of functional respiratory parameters were recorded. Results were compared with those in the control group. The control group consisted of the same number of patients and differed from the examination group only by not using laser stimulation. Patients with bronchial asthma presented with significant improvement (p lower frequency and intensity of attacks. The mechanism of laser stimulation activity in treatment of bronchial asthma is explained in detail, correlating our results to those obtained by other authors. A ten-day course of low-power laser stimulation of acupuncture points in patients with bronchial asthma improves both the lung function and gas exchange parameters. Positive effects of laser treatment in patients with bronchial asthma

  18. Hybrid light emitting transistors (Presentation Recording)

    Science.gov (United States)

    Muhieddine, Khalid; Ullah, Mujeeb; Namdas, Ebinazar B.; Burn, Paul L.

    2015-10-01

    Organic light-emitting diodes (OLEDs) are well studied and established in current display applications. Light-emitting transistors (LETs) have been developed to further simplify the necessary circuitry for these applications, combining the switching capabilities of a transistor with the light emitting capabilities of an OLED. Such devices have been studied using mono- and bilayer geometries and a variety of polymers [1], small organic molecules [2] and single crystals [3] within the active layers. Current devices can often suffer from low carrier mobilities and most operate in p-type mode due to a lack of suitable n-type organic charge carrier materials. Hybrid light-emitting transistors (HLETs) are a logical step to improve device performance by harnessing the charge carrier capabilities of inorganic semiconductors [4]. We present state of the art, all solution processed hybrid light-emitting transistors using a non-planar contact geometry [1, 5]. We will discuss HLETs comprised of an inorganic electron transport layer prepared from a sol-gel of zinc tin oxide and several organic emissive materials. The mobility of the devices is found between 1-5 cm2/Vs and they had on/off ratios of ~105. Combined with optical brightness and efficiencies of the order of 103 cd/m2 and 10-3-10-1 %, respectively, these devices are moving towards the performance required for application in displays. [1] M. Ullah, K. Tandy, S. D. Yambem, M. Aljada, P. L. Burn, P. Meredith, E. B. Namdas., Adv. Mater. 2013, 25, 53, 6213 [2] R. Capelli, S. Toffanin, G. Generali, H. Usta, A. Facchetti, M. Muccini, Nature Materials 2010, 9, 496 [3] T. Takenobu, S. Z. Bisri, T. Takahashi, M. Yahiro, C. Adachi, Y. Iwasa, Phys. Rev. Lett. 2008, 100, 066601 [4] H. Nakanotani, M. Yahiro, C. Adachi, K. Yano, Appl. Phys. Lett. 2007, 90, 262104 [5] K. Muhieddine, M. Ullah, B. N. Pal, P. Burn E. B. Namdas, Adv. Mater. 2014, 26,37, 6410

  19. The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

    Science.gov (United States)

    Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

    2002-01-01

    As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

  20. Low-power FLC-based retromodulator communications system

    Science.gov (United States)

    Swenson, Charles M.; Steed, Clark A.; de La Rue, Imelda A.; Fugate, Robert Q.

    1997-05-01

    On September 15, 1996, researchers from Utah State University/Space Dynamics Lab in conjunction with Phillips Lab/Starfire Optical Range and Kjome Research successfully flew and tested a retromodulator laser communication package on a high altitude balloon. This paper addresses the layout and hardware used for the communication link, as well as presenting some preliminary data collected during the 6 hour flight of the balloon. The package was a proof of concept demonstration system for a low-power laser communications systems for small, low Earth orbiting satellites. The ferroelectric liquid crystal based retromodulator design of Utah State provided test patterns for modulation rates up to 20 kilo bits per second. Data was successfully downlinked using a 1200 bps RS232 format and a simplistic receiver. The Starfire Optical Range 1.5-meter telescope located on Kirtland AFB, tracked the balloon, which reached a float altitude of 31 km and collected the modulated light reflected from the payload.

  1. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  2. Sub-10ps monolithic and low-power photodetector readout

    International Nuclear Information System (INIS)

    Varner, Gary S.; Ruckman, Larry L.

    2009-01-01

    Recent advances in photon detectors have resulted in high-density imaging arrays that offer many performance and cost advantages. In particular, the excellent transit time spread of certain devices show promise to provide tangible benefits in applications such as Positron Emission Tomography (PET). Meanwhile, high-density, high-performance readout techniques have not kept on pace for exploiting these developments. Photodetector readout for next generation high event rate particle identification and time-resolved PET requires a highly-integrated, low-power, and cost-effective readout technique. We propose fast waveform sampling as a method that meets these criteria and demonstrate that sub-10ps resolution can be obtained for an existing device

  3. Energy scavenging sensors for ultra-low power sensor networks

    Science.gov (United States)

    O'Brien, Dominic C.; Liu, Jing Jing; Faulkner, Grahame E.; Vachiramon, Pithawat; Collins, Steve; Elston, Steven J.

    2010-08-01

    The 'internet of things' will require very low power wireless communications, preferably using sensors that scavenge power from their environment. Free space optics allows communications over long ranges, with simple transceivers at each end, offering the possibility of low energy consumption. In addition there can be sufficient energy in the communications beam to power simple terminals. In this paper we report experimental results from an architecture that achieves this. A base station that tracks sensors in its coverage area and communicates with them using low divergence optical beams is presented. Sensor nodes use modulated retro-reflectors to communicate with the base station, and the nodes are powered by the illuminating beam. The paper presents design and implementation details, as well as future directions for this work.

  4. New reactor safety circuit for low-power-level operation

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

    1978-01-01

    In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

  5. Low-power adaptive filter based on RNS components

    DEFF Research Database (Denmark)

    Bernocchi, Gian Luca; Cardarilli, Gian Carlo; Del Re, Andrea

    2007-01-01

    In this paper a low-power implementation of an adaptive FIR filter is presented. The filter is designed to meet the constraints of channel equalization for fixed wireless communications that typically requires a large number of taps, but a serial updating of the filter coefficients, based...... on the least mean squares (LMS) algorithm, is allowed. Previous work showed that the use of the residue number system (RNS) for the variable FIR filter grants advantages both in area and power consumption. On the other hand, the use of a binary serial implementation of the adaptation algorithm eliminates...... the need for complex scaling circuits in RNS. The advantages in terms of area and speed of the presented filter, with respect to its two's complement counterpart, are evaluated for implementations in standard cells....

  6. Low power consumption and high temperature durability for radiation sensor

    International Nuclear Information System (INIS)

    Matsumoto, Yoshinori; Ueno, Hiroto

    2015-01-01

    Low power consumption and high temperature operation are important in an environmental monitoring system. The power consumption of 3 mW is achieved for the radiation sensor using low voltage operational amplifier and comparator in the signal processing circuit. The leakage reverse current of photodiode causes the charge amplifier saturation over 50degC. High temperature durability was improved by optimizing the circuit configuration and the values of feedback resistance and capacitance in the charge amplifier. The pulse response of the radiation sensor was measured up to 55degC. The custom detection circuit was designed by 0.6 μm CMOS process at 5-V supply voltage. The operation temperature was improved up to 65degC. (author)

  7. Flight experience with lightweight, low-power miniaturized instrumentation systems

    Science.gov (United States)

    Hamory, Philip J.; Murray, James E.

    1992-01-01

    Engineers at the NASA Dryden Flight Research Facility (NASA-Dryden) have conducted two flight research programs with lightweight, low-power miniaturized instrumentation systems built around commercial data loggers. One program quantified the performance of a radio-controlled model airplane. The other program was a laminar boundary-layer transition experiment on a manned sailplane. The purpose of this paper is to report NASA-Dryden personnel's flight experience with the miniaturized instrumentation systems used on these two programs. The paper will describe the data loggers, the sensors, and the hardware and software developed to complete the systems. The paper also describes how the systems were used and covers the challenges encountered to make them work. Examples of raw data and derived results will be shown as well. Finally, future plans for these systems will be discussed.

  8. Low Power Measurements on a Finger Drift Tube Linac

    CERN Document Server

    Schempp, A

    2004-01-01

    The efficiency of RFQs decreases at higher particle energies. The DTL structures used in this energy regions have a defocusing influence on the beam. To achieve a focusing effect, fingers with quadrupole symmetry were added to the drift tubes. Driven by the same power supply as the drift tubes, the fingers do not need an additional power source or feedthrough. Beam dynamics have been studied with PARMTEQ . Detailed analysis of the field distribution was done and the geometry of the finger array has been optimized with respect to beam dynamics. A spiral loaded cavity with finger drift tubes was built up and low power measurements were done. In this contribution, the results of the rf simulating with Microwave Studio are shown in comparison with bead pertubation measurement on a prototype cavity.

  9. Smartphone-Driven Low-Power Light-Emitting Device

    Directory of Open Access Journals (Sweden)

    Hea-Ja An

    2017-01-01

    Full Text Available Low-level light (laser therapy (LLLT has been widely researched in the recent past. Existing LLLT studies were performed based on laser. Recently, studies using LED have increased. This study presents a smartphone-driven low-power light-emitting device for use in colour therapy as an alternative medicine. The device consists of a control unit and a colour probe. The device is powered by and communicates with a smartphone using USB On-The-Go (OTG technology. The control unit controls emitting time and intensity of illumination with the configuration value of a smartphone application. Intensity is controlled by pulse width modulation (PWM without feedback. A calibration is performed to resolve a drawback of no feedback. To calibrate, intensity is measured in every 10 percent PWM output. PWM value is linearly calibrated to obtain accurate intensity. The device can control the intensity of illumination, and so, it can find application in varied scenarios.

  10. Experimental study of rectenna coupling at low power level

    International Nuclear Information System (INIS)

    Douyère, A; Alicalapa, F; Lan Sun Luk, J-D; Rivière, S

    2013-01-01

    The experimental results presented in this paper focus on the performance of a rectenna array by studying the effect of mutual coupling between two rectennas. The measurements in several planes of the space are investigated and used to help us to define the minimum distance for future rectenna arrays that can be used at a low power density level. The single element chosen for the array is composed of a rectifier circuit and a CSPA (Circular Slot Patch Antenna). This study shows that at a distance greater than 6cm (λ/2) between two rectennas in reception, we observe that the DC received voltage is constant in the Y plane, while in the X plane, the DC received voltage remains constant whatever the distance. We deduce that these rectennas are uncoupled in this case. We can consider each rectenna like an independent system.

  11. Optimization of passive low power wireless electromagnetic energy harvesters.

    Science.gov (United States)

    Nimo, Antwi; Grgić, Dario; Reindl, Leonhard M

    2012-10-11

    This work presents the optimization of antenna captured low power radio frequency (RF) to direct current (DC) power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor) resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at -30 dBm antenna input power. Additionally, a wireless harvester (rectenna) is built and tested for receiving range performance.

  12. A low power 12-bit ADC for nuclear instrumentation

    International Nuclear Information System (INIS)

    Adachi, R.; Landis, D.; Madden, N.; Silver, E.; LeGros, M.

    1992-10-01

    A low power, successive approximation, analog-to-digital converter (ADC) for low rate, low cost, battery powered applications is described. The ADC is based on a commercial 50 mW successive approximation CMOS device (CS5102). An on-chip self-calibration circuit reduces the inherent differential nonlinearity to 7%. A further reduction of the differential nonlinearity to 0.5% is attained with a four bit Gatti function. The Gatti function is distributed to minimize battery power consumption. All analog functions reside with the ADC while the noisy digital functions reside in the personal computer based histogramming memory. Fiber optic cables carry afl digital information between the ADC and the personal computer based histogramming memory

  13. Recent advances in flexible low power cholesteric LCDs

    Science.gov (United States)

    Khan, Asad; Shiyanovskaya, Irina; Montbach, Erica; Schneider, Tod; Nicholson, Forrest; Miller, Nick; Marhefka, Duane; Ernst, Todd; Doane, J. W.

    2006-05-01

    Bistable reflective cholesteric displays are a liquid crystal display technology developed to fill a market need for very low power displays. Their unique look, high reflectivity, bistability, and simple structure make them an ideal flat panel display choice for handheld or other portable devices where small lightweight batteries with long lifetimes are important. Applications ranging from low resolution large signs to ultra high resolution electronic books can utilize cholesteric displays to not only benefit from the numerous features, but also create enabling features that other flat panel display technologies cannot. Flexible displays are the focus of attention of numerous research groups and corporations worldwide. Cholesteric displays have been demonstrated to be highly amenable to flexible substrates. This paper will review recent advances in flexible cholesteric displays including both phase separation and emulsification approaches to encapsulation. Both approaches provide unique benefits to various aspects of manufacturability, processes, flexibility, and conformability.

  14. Low power cw-laser signatures on human skin

    International Nuclear Information System (INIS)

    Lihachev, A; Lesinsh, J; Jakovels, D; Spigulis, J

    2011-01-01

    Impact of cw laser radiation on autofluorescence features of human skin is studied. Two methods of autofluorescence detection are applied: the spectral method with the use of a fibreoptic probe and spectrometer for determining the autofluorescence recovery kinetics at a fixed skin area of ∼12 mm 2 , and the multispectral visualisation method with the use of a multispectral imaging camera for visualising long-term autofluorescence changes in a skin area of ∼4 cm 2 . The autofluorescence recovery kinetics after preliminary laser irradiation is determined. Skin autofluorescence images with visible long-term changes - 'signatures' of low power laser treatment are acquired. (application of lasers and laser-optical methods in life sciences)

  15. Sub-10ps monolithic and low-power photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Varner, Gary S.; Ruckman, Larry L.

    2009-02-20

    Recent advances in photon detectors have resulted in high-density imaging arrays that offer many performance and cost advantages. In particular, the excellent transit time spread of certain devices show promise to provide tangible benefits in applications such as Positron Emission Tomography (PET). Meanwhile, high-density, high-performance readout techniques have not kept on pace for exploiting these developments. Photodetector readout for next generation high event rate particle identification and time-resolved PET requires a highly-integrated, low-power, and cost-effective readout technique. We propose fast waveform sampling as a method that meets these criteria and demonstrate that sub-10ps resolution can be obtained for an existing device.

  16. Neutron energy spectra calculations in the low power research reactor

    International Nuclear Information System (INIS)

    Omar, H.; Khattab, K.; Ghazi, N.

    2011-01-01

    The neutron energy spectra have been calculated in the fuel region, inner and outer irradiation sites of the zero power research reactor using the MCNP-4C code and the combination of the WIMS-D/4 transport code for generation of group constants and the three-dimensional CITATION diffusion code for core analysis calculations. The neutron energy spectrum has been divided into three regions and compared with the proposed empirical correlations. The calculated thermal and fast neutron fluxes in the low power research reactor MNSR inner and outer irradiation sites have been compared with the measured results. Better agreements have been noticed between the calculated and measured results using the MCNP code than those obtained by the CITATION code. (author)

  17. Biomedical effects of low-power laser controlled by electroacupuncture

    Science.gov (United States)

    Kalenchits, Nadezhda I.; Nicolaenko, Andrej A.; Shpilevoj, Boris N.

    1997-12-01

    The methods and technical facilities of testing the biomedical effects caused by the influence of low-power laser radiation in the process of laser therapy are presented. Described studies have been conducted by means of the complex of fireware facilities consisting of the system of electroacupuncture diagnostics (EA) and a system of laser therapy on the basis of multichannel laser and magneto-laser devices. The task of laser therapy was concluded in undertaking acupuncture anaesthetization, achievement of antioedemic and dispersional actions, raising tone of musculus and nervous system, normalization of immunity factors under the control of system EA. The 82 percent to 95 percent agreement of the result of an electroacupuncture diagnostics with clinical diagnoses were achieved.

  18. New-generation low-power radiation survey instruments

    International Nuclear Information System (INIS)

    Waechter, D.A.; Bjarke, G.O.; Wolf, M.A.; Trujillo, F.; Umbarger, C.J.

    1983-01-01

    A number of new, ultra-low-powered radiation instruments have recently been developed at Los Alamos. Among these are two instruments which use a novel power source to eliminate costly batteries. The newly developed gamma detecting radiac, nicknamed the Firefly, and the alpha particle detecting instrument, called the Simple Cordless Alpha Monitor, both use recent advances in miniaturization and power-saving electronics to yield devices which are small, rugged, and very power-frugal. The two instruments consume so little power that the need for batteries to run them is eliminated. They are, instead, powered by a charged capacitor which will operate the instruments for an hour or more. Both line power and mechanical sources are used to charge the storage capacitors which power the instruments

  19. Low-Power Architecture for an Optical Life Gas Analyzer

    Science.gov (United States)

    Pilgrim, Jeffrey; Vakhtin, Andrei

    2012-01-01

    Analog and digital electronic control architecture has been combined with an operating methodology for an optical trace gas sensor platform that allows very low power consumption while providing four independent gas measurements in essentially real time, as well as a user interface and digital data storage and output. The implemented design eliminates the cross-talk between the measurement channels while maximizing the sensitivity, selectivity, and dynamic range for each measured gas. The combination provides for battery operation on a simple camcorder battery for as long as eight hours. The custom, compact, rugged, self-contained design specifically targets applications of optical major constituent and trace gas detection for multiple gases using multiple lasers and photodetectors in an integrated package.

  20. Low-power resistive random access memory by confining the formation of conducting filaments

    International Nuclear Information System (INIS)

    Huang, Yi-Jen; Lee, Si-Chen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen

    2016-01-01

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO_x/silver nanoparticles/TiO_x/AlTiO_x, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO_x layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  1. Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

    Directory of Open Access Journals (Sweden)

    M. F. Siddiqui

    2014-01-01

    Full Text Available A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT algorithm. This research work proposed a novel Common Subexpression Elimination (CSE based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

  2. Investigation of a novel common subexpression elimination method for low power and area efficient DCT architecture.

    Science.gov (United States)

    Siddiqui, M F; Reza, A W; Kanesan, J; Ramiah, H

    2014-01-01

    A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

  3. Development of Risk Assessment Technology for Low Power, Shutdown and Digital I and C System

    International Nuclear Information System (INIS)

    Jang, Seung Cheol; Kang, Hyun Gook; Lim, Ho Gon; Park, Jin Hee; Kang, Dae Il; Eom, Heung Sub; Kim, Man Cheol; Lee, Ho Joong; Kim, Jae Whan; Ha, Jae Joo

    2007-06-01

    There are two technical areas to deal with in the project: the low power and shutdown probabilistic safety assessment (PSA), and the digital I and C PSA. The scope and contents of each area could be summarized as follows: The LPSD PSA Area Ο Quality improvement of the KSNP LPSD PSA model in the following four technical areas; human reliability analysis (HR), system analysis (SY), data analysis (DA) and accident sequence quantification (QU) Ο Development of the LPSD configuration risk management(CRM) model - Study on the methodology for developing a CRM model, so-called ASLOC (Autonomous Shutdown LOgic Creation) - Development of the LPSD CRM model for the units of Ulchin 3 and 4 The Digital I and C PSA Area Ο Development of impact model of ESF-CCS on plant risks - Unavailability analysis of ESF-CCS for APR-1400 - Digital plant risk models for evaluating core damage frequency (CDF) Ο Study on the methodologies for treating digital-specific problems in the digital I and C PSA - Study on the methodology for evaluating safety-critical SW reliability by BBN techniques, including a feasibility study of reliability growth model - Study on the methodology for the safety-critical network system by Markov chain

  4. High-Voltage, Low-Power BNC Feedthrough Terminator

    Science.gov (United States)

    Bearden, Douglas

    2012-01-01

    This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

  5. Ambipolar phosphorene field effect transistor.

    Science.gov (United States)

    Das, Saptarshi; Demarteau, Marcel; Roelofs, Andreas

    2014-11-25

    In this article, we demonstrate enhanced electron and hole transport in few-layer phosphorene field effect transistors (FETs) using titanium as the source/drain contact electrode and 20 nm SiO2 as the back gate dielectric. The field effect mobility values were extracted to be ∼38 cm(2)/Vs for electrons and ∼172 cm(2)/Vs for the holes. On the basis of our experimental data, we also comprehensively discuss how the contact resistances arising due to the Schottky barriers at the source and the drain end effect the different regime of the device characteristics and ultimately limit the ON state performance. We also propose and implement a novel technique for extracting the transport gap as well as the Schottky barrier height at the metal-phosphorene contact interface from the ambipolar transfer characteristics of the phosphorene FETs. This robust technique is applicable to any ultrathin body semiconductor which demonstrates symmetric ambipolar conduction. Finally, we demonstrate a high gain, high noise margin, chemical doping free, and fully complementary logic inverter based on ambipolar phosphorene FETs.

  6. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  7. Abductive Logic Grammars

    DEFF Research Database (Denmark)

    Christiansen, Henning; Dahl, Veronica

    2009-01-01

    By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting....... We formalize these ideas, and exemplify them both within and outside first-order logic, and for both fixed and dynamic knowledge bases. Within the latter variety, we consider the usual left-to-right derivations that are traditional in logic grammars, but also -- in a significant departure from...

  8. Action Type Deontic Logic

    DEFF Research Database (Denmark)

    Bentzen, Martin Mose

    2014-01-01

    A new deontic logic, Action Type Deontic Logic, is presented. To motivate this logic, a number of benchmark cases are shown, representing inferences a deontic logic should validate. Some of the benchmark cases are singled out for further comments and some formal approaches to deontic reasoning...... are evaluated with respect to the benchmark cases. After that follows an informal introduction to the ideas behind the formal semantics, focussing on the distinction between action types and action tokens. Then the syntax and semantics of Action Type Deontic Logic is presented and it is shown to meet...

  9. Product Lukasiewicz Logic

    Czech Academy of Sciences Publication Activity Database

    Horčík, Rostislav; Cintula, Petr

    2004-01-01

    Roč. 43, - (2004), s. 477-503 ISSN 1432-0665 R&D Projects: GA AV ČR IAA1030004; GA ČR GA201/02/1540 Grant - others:GA CTU(CZ) project 0208613; net CEEPUS(SK) SK-042 Institutional research plan: CEZ:AV0Z1030915 Keywords : fuzzy logic * many-valued logic * Lukasiewicz logic * Lpi logic * Takeuti-Titani logic * MV-algebras * product MV-algebras Subject RIV: BA - General Mathematics Impact factor: 0.295, year: 2004

  10. Achievable rate of spectrum sharing cognitive radio systems over fading channels at low-power regime

    KAUST Repository

    Sboui, Lokman; Rezki, Zouheir; Alouini, Mohamed-Slim

    2014-01-01

    the previously achieved rate at the low-power regime. Interestingly, we show that the low-power regime analysis provides a specific insight into the maximum achievable rate behavior of CR that has not been reported by previous studies.

  11. G(sup 4)FET Implementations of Some Logic Circuits

    Science.gov (United States)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  12. Heuristic Synthesis of Reversible Logic – A Comparative Study

    Directory of Open Access Journals (Sweden)

    Chua Shin Cheng

    2014-01-01

    Full Text Available Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based. All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.

  13. Henkin and Hybrid Logic

    DEFF Research Database (Denmark)

    Blackburn, Patrick Rowan; Huertas, Antonia; Manzano, Maria

    2014-01-01

    Leon Henkin was not a modal logician, but there is a branch of modal logic that has been deeply influenced by his work. That branch is hybrid logic, a family of logics that extend orthodox modal logic with special proposition symbols (called nominals) that name worlds. This paper explains why...... Henkin’s techniques are so important in hybrid logic. We do so by proving a completeness result for a hybrid type theory called HTT, probably the strongest hybrid logic that has yet been explored. Our completeness result builds on earlier work with a system called BHTT, or basic hybrid type theory...... is due to the first-order perspective, which lies at the heart of Henin’s best known work and hybrid logic....

  14. Logic and Ontology

    Directory of Open Access Journals (Sweden)

    Newton C. A. da Costa

    2002-12-01

    Full Text Available In view of the present state of development of non classical logic, especially of paraconsistent logic, a new stand regarding the relations between logic and ontology is defended In a parody of a dictum of Quine, my stand May be summarized as follows. To be is to be the value of a variable a specific language with a given underlying logic Yet my stand differs from Quine’s, because, among other reasons, I accept some first order heterodox logics as genuine alternatives to classical logic I also discuss some questions of non classical logic to substantiate my argument, and suggest that may position complements and extends some ideas advanced by L Apostel.

  15. Institutional Logics in Action

    DEFF Research Database (Denmark)

    Lounsbury, Michael; Boxenbaum, Eva

    2013-01-01

    This double volume presents state-of-the-art research and thinking on the dynamics of actors and institutional logics. In the introduction, we briefly sketch the roots and branches of institutional logics scholarship before turning to the new buds of research on the topic of how actors engage...... institutional logics in the course of their organizational practice. We introduce an exciting line of new works on the meta-theoretical foundations of logics, institutional logic processes, and institutional complexity and organizational responses. Collectively, the papers in this volume advance the very...... prolific stream of research on institutional logics by deepening our insight into the active use of institutional logics in organizational action and interaction, including the institutional effects of such (inter)actions....

  16. Electron irradiation of power transistors

    International Nuclear Information System (INIS)

    Hower, P.L.; Fiedor, R.J.

    1982-01-01

    A method for reducing storage time and gain parameters in a semiconductor transistor includes the step of subjecting the transistor to electron irradiation of a dosage determined from measurements of the parameters of a test batch of transistors. Reduction of carrier lifetime by proton bombardment and gold doping is mentioned as an alternative to electron irradiation. (author)

  17. Evaluation of flux-based logic schemes for high-Tc applications

    International Nuclear Information System (INIS)

    Fleishman, J.; Feld, D.; Xiao, P.; Van Dazer, T.

    1991-01-01

    This paper presents analyses of three digital logic families that can be made using nonhysteretic Josephson junctions, potentially the only kind of Josephson device realizable with superconductors having high transition temperatures. These logic families utilize magnetic flux-transfer and are characterized by very low power dissipation. Rapid Single Flux Quantum (RSFQ) and Phase Mode logic are both based on pulse propagation. The Quantum Flux Parametron (QFP) logic family is based on current latching. Simulations of RSFQ, Phase-Mode, and QFP logic families using high-T c junction parameters are presented to demonstrate the compatibility of these logic families with the new perovskite superconductors. The operation of these logic families is analyzed and the advantages and disadvantages of each are discussed

  18. Freestanding Artificial Synapses Based on Laterally Proton-Coupled Transistors on Chitosan Membranes.

    Science.gov (United States)

    Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2015-10-07

    Freestanding synaptic transistors are fabricated on solution-processed chitosan membranes. A short-term memory to long-term memory transition is observed due to proton-related electrochemical doping under repeated pulse stimulus. Moreover, freestanding artificial synaptic devices with multiple presynaptic inputs are investigated, and spiking logic operation and logic modulation are realized. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. 47 CFR 74.785 - Low power TV digital data service pilot project.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV digital data service pilot project... Power TV, TV Translator, and TV Booster Stations § 74.785 Low power TV digital data service pilot project. Low power TV stations authorized pursuant to the LPTV Digital Data Services Act (Public Law 106...

  20. 76 FR 11680 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2011-03-03

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A... Commission's Rules to Establish Rules for Digital Low Power, Television Translator, and Television Booster... Digital Low Power Television Translator, Television Booster Stations, and to Amend Rules for Digital Class...

  1. 76 FR 23795 - Low-Power Television and Translator Upgrade Program: Notice of Final Closing Date

    Science.gov (United States)

    2011-04-28

    .... 110418247-1247-01] Low-Power Television and Translator Upgrade Program: Notice of Final Closing Date AGENCY... receipt of applications for the Low-Power Television and Translator Upgrade Program (Upgrade Program) will... Rules to Establish Rules for Digital Low Power Television, Television Translator, and Television Booster...

  2. Leveraging the Radiation-Resistance and Power Efficiency of Nano-Magnetic Logic to Develop More Affordable, Efficient, and Reliable Space Technologies

    Data.gov (United States)

    National Aeronautics and Space Administration — I am researching nano-magnetic logic (NML) because it has low power consumption, high density of computing and memory elements, CMOS integration capabilities, and...

  3. Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

    Science.gov (United States)

    Lee, Sungsik; Nathan, Arokia

    2016-10-01

    The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

  4. Neuromorphic transistor achieved by redox reaction of WO3 thin film

    Science.gov (United States)

    Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

    2018-04-01

    An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

  5. Accelerating the life of transistors

    International Nuclear Information System (INIS)

    Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

    2013-01-01

    Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

  6. Logic and structure

    CERN Document Server

    Dalen, Dirk

    1983-01-01

    A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...

  7. The Football of Logic

    Directory of Open Access Journals (Sweden)

    Schang Fabien

    2017-03-01

    Full Text Available An analogy is made between two rather different domains, namely: logic, and football (or soccer. Starting from a comparative table between the two activities, an alternative explanation of logic is given in terms of players, ball, goal, and the like. Our main thesis is that, just as the task of logic is preserving truth from premises to the conclusion, footballers strive to keep the ball as far as possible until the opposite goal. Assuming this analogy may help think about logic in the same way as in dialogical logic, but it should also present truth-values in an alternative sense of speech-acts occurring in a dialogue. The relativity of truth-values is focused by this way, thereby leading to an additional way of logical pluralism.

  8. Low Power Shutdown PSA for CANDU Type Plants

    Energy Technology Data Exchange (ETDEWEB)

    Bae, Yeon Kyoung; Kim, Myung Su [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    KHNP also have concentrated on full power PSA. Some recently constructed OPR1000 type plants and APR1400 type plants have performed the low power and shutdown (LPSD) PSA. The purpose of LPSD PSA is to identify the main contributors on the accident sequences of core damage and to find the measure of safety improvement. After the Fukushima accident, Korean regulatory agency required the shutdown severe accident management guidelines (SSAMG) development for safety enhancement. For the reliability of SSAMG, KHNP should develop the LPSD PSA. Especially, the LPSD PSA for CANDU type plant had developed for the first time in Korea. This paper illustrates how the LPSD PSA for CANDU type developed and the core damage frequency (CDF) is different with that of full power PSA. KHNP performed LPSD PSA to develop the SSAMG after the Fukushima accidents. The results show that risk at the specific operation mode during outage is higher than that of full power operation. Also, the results indicated that recovery failure of class 4 power at the POS 5A, 5B contribute dominantly to the total CDF from importances analysis. LPSD PSA results such as CDF with initiating events and POSs, risk results with plant damage state, and containment failure probability and frequency with POSs can be used by inputs for developing the SSAMG.

  9. Quantum broadcasting problem in classical low-power signal processing

    International Nuclear Information System (INIS)

    Janzing, Dominik; Steudel, Bastian

    2007-01-01

    We prove a no-broadcasting theorem for the Holevo information of a noncommuting ensemble stating that no operation can generate a bipartite ensemble such that both copies have the same information as the original. We argue that upper bounds on the average information over both copies imply lower bounds on the quantum capacity required to send the ensemble without information loss. This is because a channel with zero quantum capacity has a unitary extension transferring at least as much information to its environment as it transfers to the output. For an ensemble being the time orbit of a pure state under a Hamiltonian evolution, we derive such a bound on the required quantum capacity in terms of properties of the input and output energy distribution. Moreover, we discuss relations between the broadcasting problem and entropy power inequalities. The broadcasting problem arises when a signal should be transmitted by a time-invariant device such that the outgoing signal has the same timing information as the incoming signal had. Based on previous results we argue that this establishes a link between quantum information theory and the theory of low power computing because the loss of timing information implies loss of free energy

  10. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Science.gov (United States)

    Nimo, Antwi; Grgić, Dario; Reindl, Leonhard M.

    2012-01-01

    This work presents the optimization of antenna captured low power radio frequency (RF) to direct current (DC) power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor) resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna) is built and tested for receiving range performance. PMID:23202014

  11. Low-Power Embedded DSP Core for Communication Systems

    Science.gov (United States)

    Tsao, Ya-Lan; Chen, Wei-Hao; Tan, Ming Hsuan; Lin, Maw-Ching; Jou, Shyh-Jye

    2003-12-01

    This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35[InlineEquation not available: see fulltext.]m SPQM and 0.25[InlineEquation not available: see fulltext.]m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a[InlineEquation not available: see fulltext.] version is 100 MHz (0.35[InlineEquation not available: see fulltext.]m) and 140 MHz (0.25[InlineEquation not available: see fulltext.]m).

  12. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Directory of Open Access Journals (Sweden)

    Dario Grgić

    2012-10-01

    Full Text Available This work presents the optimization of antenna captured low power radio frequency (RF to direct current (DC power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna is built and tested for receiving range performance.

  13. Low power consumption mini rotary actuator with SMA wires

    Science.gov (United States)

    Manfredi, Luigi; Huan, Yu; Cuschieri, Alfred

    2017-11-01

    Shape memory alloys (SMAs) are smart materials widely used as actuators for their high power to weight ratio despite their well-known low energy efficiency and limited mechanical bandwidth. For robotic applications, SMAs exhibit limitations due to high power consumption and limited stroke, varying from 4% to 7% of the total length. Hysteresis, during the contraction and extension cycle, requires a complex control algorithm. On the positive side, the small size and low weight are eminently suited for the design of mini actuators for robotic platforms. This paper describes the design and construction of a light weight and low power consuming mini rotary actuator with on-board contact-less position and force sensors. The design is specifically intended to reduce (i) energy consumption, (ii) dimensions of the sensory system, and (iii) provide a simple control without any need for SMA characterisation. The torque produced is controlled by on-board force sensors. Experiments were performed to investigate the energy consumption and performance (step and sinusoidal angle profiles with a frequency varying from 0.5 to 10 Hz and maximal amplitude of {15}\\circ ). We describe a transient capacitor effect related to the SMA wires during the sinusoidal profile when the active SMA wire is powered and the antagonist one switched-off, resulting in a transient current time varying from 300 to 400 ms.

  14. ``Low Power Wireless Technologies: An Approach to Medical Applications''

    Science.gov (United States)

    Bellido O., Francisco J.; González R., Miguel; Moreno M., Antonio; de La Cruz F, José Luis

    Wireless communication supposed a great both -quantitative and qualitative, jump in the management of the information, allowing the access and interchange of it without the need of a physical cable connection. The wireless transmission of voice and information has remained in constant evolution, arising new standards like BluetoothTM, WibreeTM or ZigbeeTM developed under the IEEE 802.15 norm. These newest wireless technologies are oriented to systems of communication of short-medium distance and optimized for a low cost and minor consume, becoming recognized as a flexible and reliable medium for data communications across a broad range of applications due to the potential that the wireless networks presents to operate in demanding environments providing clear advantages in cost, size, power, flexibility, and distributed intelligence. About the medical applications, the remote health or telecare (also called eHealth) is getting a bigger place into the manufacturers and medical companies, in order to incorporate products for assisted living and remote monitoring of health parameteres. At this point, the IEEE 1073, Personal Health Devices Working Group, stablish the framework for these kind of applications. Particularly, the 1073.3.X describes the physical and transport layers, where the new ultra low power short range wireless technologies can play a big role, providing solutions that allow the design of products which are particularly appropriate for monitor people’s health with interoperability requirements.

  15. Recirculating steam generator operation at very low power

    International Nuclear Information System (INIS)

    Holcblat, A.

    2001-01-01

    The behaviour of recirculating SG's at very low power has been thoroughly investigated by laboratory and on-site tests as well as numerical simulations. A special experimental program dedicated to recirculation threshold determination has been performed on the Freon SG mock-up CLOTAIRE. These laboratory data are completed with transients of feedwater injections at hot stand-by on two instrumented SG's, one boiler type SG and one economizer type SG. The phenomena are different on both types. In boiler SG's, the SG behaves like a U-tube and recirculation stops around 2% load at stand-by temperature and water level. In economizer SG's, the presence of 2 separate down-comers and a divider plate inside the tube bundle allows a recirculation loop by-passing the separators. The mixing of saturated and cold water induced by this loop limits down-comer cooling and thus alleviates the thermal load on the tube sheet. These tests were used to validate the SG transient analysis 1-D code ANETH. (author)

  16. Low power offloading strategy for femto-cloud mobile network

    Directory of Open Access Journals (Sweden)

    Anwesha Mukherjee

    2016-03-01

    Full Text Available Nowadays offloading is a popular method of mobile cloud computing where the required computation takes place remotely inside the cloud. But whether to process an application inside the mobile device or to the cloud is a challenging issue because communication with the cloud involves latency and power consumption. This paper has proposed a method of decision making regarding whether to offload or not-to-offload an application to the cloud. According to the proposed strategy, application is offloaded only if it results in lower power consumption than local execution within the mobile device itself. If this condition is satisfied, computation time and deadline of the job are considered as the basic parameters to decide whether to offload or not. Experimental results demonstrate that the proposed offloading algorithm reduces the power consumption to approximately 3–32%. To achieve power-efficiency and security both, femto-cloud architecture is used in the proposed work. In this case offloading from the mobile device to the cloud takes place through the low power and secure femtocell base station. Simulation results present that using femto-cloud architecture 70–83% and 52–66% power savings are achieved than using macrocell and microcell base stations respectively while offloading an application to the cloud.

  17. An optimized low-power voltage controlled oscillator

    Science.gov (United States)

    Shah, Kriyang; Le, Hai Phuong; Singh, Jugdutt

    2007-01-01

    This paper presents an optimised low-power low-phase-noise Voltage Controlled Oscillator (VCO) for Bluetooth wireless applications. The system level design issues and tradeoffs related to Direct Conversion Receiver (DCR) and Low Intermediate Frequency (IF) architecture for Bluetooth are discussed. Subsequently, for a low IF architecture, the critical VCO performance parameters are derived from system specifications. The VCO presented in the paper is optimised by implementing a novel biasing circuit that employs two current mirrors, one at the top and the other one at the bottom of the cross-coupled complementary VCO, to give the exact replica of the current in both the arms of current mirror circuit. This approach, therefore, significantly reduces the system power consumption as well as improves the system performance. Results show that, the VCO consumes only 281μW of power at 2V supply. Its phase noise performance are -115dBc/Hz, -130dBc/Hz and -141dBc/Hz at the offset frequency of 1MHz, 3MHz and 5MHz respectively. Results indicate that 31% reduction in power consumption is achieved as compared to the traditional VCO design. These characteristics make the designed VCO a better candidate for Bluetooth wireless application where power consumption is the major issue.

  18. Quality of the current low power and shutdown PSA practice

    International Nuclear Information System (INIS)

    Jang, Seung Cheol; Park, Jin Hee; Lim, Ho Gon; Kim, Tae Woon

    2004-01-01

    A probabilistic safety assessment (PSA) for the low-power and shutdown (LPSD) modes in a Korea standard nuclear power plant (KSNP) has been performed for the purpose of estimating the LPSD risk and identifying the vulnerabilities of LPSD operations. Both the operational experience and PSA results indicate that the risks from LPSD operations could be comparable with those from power operations. However, the application of the LPSD risk insights to risk-informed decision making has been slow to be adopted in practice. It is largely due to the question of whether the current LPSD PSA practice is appropriate for application to risk-informed decision making or not. Such a question has to do with the quality of the current LPSD PSA practice. In this paper, we have performed self-assessment of the KSNP LPSD PSA quality based on the ANS Standard (draft as of 13 Sep. 2002). The aims of the work are to find the LPSD PSA technical areas insufficient for application to risk-informed decision making and to efficiently allocate the limited research resources to improve the LPSD PSA model quality. Many useful findings regarding the current LPSD PSA quality are presented in this paper

  19. Low power gas sensor array on flexible acetate substrate

    Science.gov (United States)

    Benedict, Samatha; Basu, Palash Kumar; Bhat, Navakanta

    2017-07-01

    In this paper, we present a novel approach of fabricating a low-cost and low power gas sensor array on flexible acetate sheets for sensing CO, SO2, H2 and NO2 gases. The array has four sensor elements with an integrated microheater which can be individually controlled enabling the monitoring of four gases. The thermal properties of the microheater characterized by IR imaging are presented. The microheater with an active area of 15 µm  ×  5 µm reaches a temperature of 300 °C, consuming 2 mW power, the lowest reported on flexible substrates. A sensing electrode is patterned on top of the microheater, and a nanogap (100 nm) is created by an electromigration process. This nanogap is bridged by four sensing materials doped with platinum, deposited using a solution dispensing technique. The sensing material characterization is completed using energy dispersive x-ray analysis. The sensing characteristics of ZnO for CO, V2O5 for SO2, SnO2 for H2 and WO3 for NO2 gases are studied at different microheater voltages. The sensing characteristics of ZnO at different bending angles is also studied, which shows that the microheater and the sensing material are intact without any breaking upto a bending angle of 20°. The ZnO CO sensor shows sensitivity of 146.2% at 1 ppm with good selectivity.

  20. Low power RF measurements of travelling wave type linear accelerator

    International Nuclear Information System (INIS)

    Reddy, Sivananda; Wanmode, Yashwant; Bhisikar, A.; Shrivastava, Purushottam

    2015-01-01

    RRCAT is engaged in the development of travelling wave (TW) type linear accelerator for irradiation of industrial and agricultural products. TW accelerator designed for 2π/3 mode to operate at frequency of 2856 MHz. It consists of input coupler, buncher cells, regular cells and output coupler. Low power measurement of this structure includes measurement of resonant frequency of the cells for different resonant modes and quality factor, tuning of input-output coupler and measurement of phase advance per cell and electric field in the structure. Steele's non-resonant perturbation technique has been used for measurement of phase advance per cell and electric field in the structure. Kyhl's method has been used for the tuning of input-output coupler. Computer based automated bead pull set-up has been developed for measurement of phase advance per cell and electric field profile in the structure. All the codes are written in Python for interfacing of Vector Network Analyzer (VNA) , stepper motor with computer. These codes also automate the measurement process. This paper describes the test set- up for measurement and results of measurement of travelling wave type linear accelerating structure. (author)

  1. Low power femtosecond tip-based nanofabrication with advanced control

    Science.gov (United States)

    Liu, Jiangbo; Guo, Zhixiong; Zou, Qingze

    2018-02-01

    In this paper, we propose an approach to enable the use of low power femtosecond laser in tip-based nanofabrication (TBN) without thermal damage. One major challenge in laser-assisted TBN is in maintaining precision control of the tip-surface positioning throughout the fabrication process. An advanced iterative learning control technique is exploited to overcome this challenge in achieving high-quality patterning of arbitrary shape on a metal surface. The experimental results are analyzed to understand the ablation mechanism involved. Specifically, the near-field radiation enhancement is examined via the surface-enhanced Raman scattering effect, and it was revealed the near-field enhanced plasma-mediated ablation. Moreover, silicon nitride tip is utilized to alleviate the adverse thermal damage. Experiment results including line patterns fabricated under different writing speeds and an "R" pattern are presented. The fabrication quality with regard to the line width, depth, and uniformity is characterized to demonstrate the efficacy of the proposed approach.

  2. Photosensitive graphene transistors.

    Science.gov (United States)

    Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

    2014-08-20

    High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  3. Logic of likelihood

    International Nuclear Information System (INIS)

    Wall, M.J.W.

    1992-01-01

    The notion of open-quotes probabilityclose quotes is generalized to that of open-quotes likelihood,close quotes and a natural logical structure is shown to exist for any physical theory which predicts likelihoods. Two physically based axioms are given for this logical structure to form an orthomodular poset, with an order-determining set of states. The results strengthen the basis of the quantum logic approach to axiomatic quantum theory. 25 refs

  4. Logical database design principles

    CERN Document Server

    Garmany, John; Clark, Terry

    2005-01-01

    INTRODUCTION TO LOGICAL DATABASE DESIGNUnderstanding a Database Database Architectures Relational Databases Creating the Database System Development Life Cycle (SDLC)Systems Planning: Assessment and Feasibility System Analysis: RequirementsSystem Analysis: Requirements Checklist Models Tracking and Schedules Design Modeling Functional Decomposition DiagramData Flow Diagrams Data Dictionary Logical Structures and Decision Trees System Design: LogicalSYSTEM DESIGN AND IMPLEMENTATION The ER ApproachEntities and Entity Types Attribute Domains AttributesSet-Valued AttributesWeak Entities Constraint

  5. Erotetic epistemic logic

    Czech Academy of Sciences Publication Activity Database

    Peliš, Michal

    2017-01-01

    Roč. 26, č. 3 (2017), s. 357-381 ISSN 1425-3305 R&D Projects: GA ČR(CZ) GC16-07954J Institutional support: RVO:67985955 Keywords : epistemic logic * erotetic implication * erotetic logic * logic of questions Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology http://apcz.umk.pl/czasopisma/index.php/LLP/article/view/LLP.2017.007

  6. Logic for Physicists

    Science.gov (United States)

    Pereyra, Nicolas A.

    2018-06-01

    This book gives a rigorous yet 'physics-focused' introduction to mathematical logic that is geared towards natural science majors. We present the science major with a robust introduction to logic, focusing on the specific knowledge and skills that will unavoidably be needed in calculus topics and natural science topics in general (rather than taking a philosophical-math-fundamental oriented approach that is commonly found in mathematical logic textbooks).

  7. What is mathematical logic?

    CERN Document Server

    Crossley, J N; Brickhill, CJ; Stillwell, JC

    2010-01-01

    Although mathematical logic can be a formidably abstruse topic, even for mathematicians, this concise book presents the subject in a lively and approachable fashion. It deals with the very important ideas in modern mathematical logic without the detailed mathematical work required of those with a professional interest in logic.The book begins with a historical survey of the development of mathematical logic from two parallel streams: formal deduction, which originated with Aristotle, Euclid, and others; and mathematical analysis, which dates back to Archimedes in the same era. The streams beg

  8. Indexical Hybrid Tense Logic

    DEFF Research Database (Denmark)

    Blackburn, Patrick Rowan; Jørgensen, Klaus Frovin

    2012-01-01

    In this paper we explore the logic of now, yesterday, today and tomorrow by combining the semantic approach to indexicality pioneered by Hans Kamp [9] and refined by David Kaplan [10] with hybrid tense logic. We first introduce a special now nominal (our @now corresponds to Kamp’s original now...... operator N) and prove completeness results for both logical and contextual validity. We then add propositional constants to handle yesterday, today and tomorrow; our system correctly treats sentences like “Niels will die yesterday” as contextually unsatisfiable. Building on our completeness results for now......, we prove completeness for the richer language, again for both logical and contextual validity....

  9. A Logic for Choreographies

    DEFF Research Database (Denmark)

    Lopez, Hugo Andres; Carbone, Marco; Hildebrandt, Thomas

    2010-01-01

    We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL...... ), a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof...

  10. Superconductor fluxoid logic

    International Nuclear Information System (INIS)

    Andronov, A.A.; Kurin, V.V.; Levichev, M.Yu.; Ryndyk, D.A.; Vostokov, V.I.

    1993-01-01

    In recent years there has been much interest in superconductor logical devices. Our paper is devoted to the analysis of some new possibilities in this field. The main problems here are: minimization of time of logical operations and reducing of device scale. Josephson systems are quite appropriate for this purpose because of small size, short characteristic time and also small energy losses. Two different types of Josephson logic have been investigated during last years. The first type is based on hysteretic V-A characteristic of a single Josephson junction. Superconducting and resistive (with nonzero voltage) states are considered as logical zero and logical unit. The second one - rapid single flux quantum logic, has been developed recently and is based on SQUID-like bistability. Different logical states are the states with different number of magnetic flux quanta inside closed superconducting contour. Information is represented by voltage pulses with fixed ''area'' (∫ V(t)/dt). This pulses are generated when logical state of SQUID-like elementary cell changes. The fundamental role of magnetic flux quantization in this type of logic leads to the necessity of large enough self-inductance of superconductor contour and thus to limitations on minimal device dimensions. (orig.)

  11. A Logic for Choreographies

    Directory of Open Access Journals (Sweden)

    Marco Carbone

    2011-10-01

    Full Text Available We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL, a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof system for checking validity of formulae.

  12. Introduction to mathematical logic

    CERN Document Server

    Mendelson, Elliott

    2015-01-01

    The new edition of this classic textbook, Introduction to Mathematical Logic, Sixth Edition explores the principal topics of mathematical logic. It covers propositional logic, first-order logic, first-order number theory, axiomatic set theory, and the theory of computability. The text also discusses the major results of Gödel, Church, Kleene, Rosser, and Turing.The sixth edition incorporates recent work on Gödel's second incompleteness theorem as well as restoring an appendix on consistency proofs for first-order arithmetic. This appendix last appeared in the first edition. It is offered in th

  13. Design for low-power and reliable flexible electronics

    Science.gov (United States)

    Huang, Tsung-Ching (Jim)

    Flexible electronics are emerging as an alternative to conventional Si electronics for large-area low-cost applications such as e-paper, smart sensors, and disposable RFID tags. By utilizing inexpensive manufacturing methods such as ink-jet printing and roll-to-roll imprinting, flexible electronics can be made on low-cost plastics just like printing a newspaper. However, the key elements of exible electronics, thin-film transistors (TFTs), have slower operating speeds and less reliability than their Si electronics counterparts. Furthermore, depending on the material property, TFTs are usually mono-type -- either p- or n-type -- devices. Making air-stable complementary TFT circuits is very challenging and not applicable to most TFT technologies. Existing design methodologies for Si electronics, therefore, cannot be directly applied to exible electronics. Other inhibiting factors such as high supply voltage, large process variation, and lack of trustworthy device modeling also make designing larger-scale and robust TFT circuits a significant challenge. The major goal of this dissertation is to provide a viable solution for robust circuit design in exible electronics. I will first introduce a reliability simulation framework that can predict the degraded TFT circuits' performance under bias-stress. This framework has been validated using the amorphous-silicon (a-Si) TFT scan driver for TFT-LCD displays. To reuse the existing CMOS design ow for exible electronics, I propose a Pseudo-CMOS cell library that can make TFT circuits operable under low supply voltage and which has post-fabrication tunability for reliability and performance enhancement. This cell library has been validated using 2V self-assembly-monolayer (SAM) organic TFTs with a low-cost shadow-mask deposition process. I will also demonstrate a 3-bit 1.25KS/s Flash ADC in a-Si TFTs, which is based on the proposed Pseudo-CMOS cell library, and explore more possibilities in display, energy, and sensing

  14. Silicon, germanium, and III-V-based tunneling devices for low-power applications

    Science.gov (United States)

    Smith, Joshua T.

    While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit---the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the

  15. Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

    Science.gov (United States)

    DeGregorio, Kelly; Wilson, Dale G.

    2009-01-01

    Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

  16. Understanding Social Media Logic

    Directory of Open Access Journals (Sweden)

    José van Dijck

    2013-08-01

    Full Text Available Over the past decade, social media platforms have penetrated deeply into the mech­anics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpin­ning its dynamics. This logic will be considered in light of what has been identified as mass me­dia logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmabil­ity, popularity, connectivity, and datafication—and argue that these principles become increas­ingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance ex­isting mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relat­ively simple to identify, but it is much harder to map the complex connections between plat­forms that distribute this logic: users that employ them, technologies that

  17. Delay-Limited Capacity in the Low Power Regime

    KAUST Repository

    Rezki, Zouheir

    2016-02-11

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated in the low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a shortterm power constraint (STPC) and a long-term power constraint (LTPC). Subject to STPC, we show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. Subject to LTPC, we show that the above guidelines still holds and that the outage performance improves due to the flexibility of the LTPC over the STPC. More interestingly, we prove that LTPC allows zero-outage communication even at low SNR and characterize the delaylimited capacity at low SNR in a simple form. More precisely, we establish that the delay-limited capacity scales linearly with the power constraint, for a given M < 1. Our framework highlights the benefit of fading at low SNR as the delay-limited capacity may outperform the AWGN capacity. For instance, for Rayleigh fading and with M = 3, the delay-limited capacity is 16% higher than the capacity of an AWGN channel.

  18. Low Power Design for Future Wearable and Implantable Devices

    Directory of Open Access Journals (Sweden)

    Katrine Lundager

    2016-10-01

    Full Text Available With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs, especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs, as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery

  19. Low power data acquisition unit for autonomous geophysical instrumentation

    Science.gov (United States)

    Prystai, Andrii

    2017-04-01

    The development of an autonomous instrumentation for field research is always a challenge which needs knowledge and application of recent advances in technology and components production. Using this information a super-low power, low-cost, stand-alone GPS time synchronized data acquisition unit was created. It comprises an extended utilization of the microcontroller modules and peripherals and special firmware with flexible PLL parameters. The present report is devoted to a discussion of synchronization mode of data sampling in autonomous field instruments with possibility of GPS random breaks. In the result the achieved sampling timing accuracy is better than ± 60 ns without phase jumps and distortion plus fixed shift depending on the sample rate. The main application of the system is for simultaneous measurement of several channels from magnetic and electric sensors in field conditions for magneto-telluric instruments. First utilization of this system was in the new developed versions of LEMI-026 magnetometer and LEMI-423 field station, where it was applied for digitizing of up to 6 analogue channels with 32-bit resolution in the range ± 2.5V, digital filtration (LPF) and maximum sample rate 4kS/s. It is ready for record in 5 minutes after being turned on. Recently, this system was successfully utilized with the drone-portable magnetometers destined for the search of metallic objects, like UXO, in rural areas, research of engineering underground structure and for mapping ore bodies. The successful tests of drone-portable system were made and tests results are also discussed.

  20. Inexpensive, Low Power, Open-Source Data Logging hardware development

    Science.gov (United States)

    Sandell, C. T.; Schulz, B.; Wickert, A. D.

    2017-12-01

    Over the past six years, we have developed a suite of open-source, low-cost, and lightweight data loggers for scientific research. These loggers employ the popular and easy-to-use Arduino programming environment, but consist of custom hardware optimized for field research. They may be connected to a broad and expanding range of off-the-shelf sensors, with software support built in directly to the "ALog" library. Three main models exist: The ALog (for Autonomous or Arduino Logger) is the extreme low-power model for years-long deployments with only primary AA or D batteries. The ALog shield is a stripped-down ALog that nests with a standard Arduino board for prototyping or education. The TLog (for Telemetering Logger) contains an embedded radio with 500 m range and a GPS for communications and precision timekeeping. This enables meshed networks of loggers that can send their data back to an internet-connected "home base" logger for near-real-time field data retrieval. All boards feature feature a high-precision clock, full size SD card slot for high-volume data storage, large screw terminals to connect sensors, interrupts, SPI and I2C communication capability, and 3.3V/5V power outputs. The ALog and TLog have fourteen 16-bit analog inputs with a precision voltage reference for precise analog measurements. Their components are rated -40 to +85 degrees C, and they have been tested in harsh field conditions. These low-cost and open-source data loggers have enabled our research group to collect field data across North and South America on a limited budget, support student projects, and build toward better future scientific data systems.

  1. Low power interface IC's for electrostatic energy harvesting applications

    Science.gov (United States)

    Kempitiya, Asantha

    interest where the storage capacitor can be optimized to produce almost 70% of the ideal power taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous EHC implemented with a macro-scale electrostatic converter prototype. Based on the preceding analysis, the design of a novel ultra low power electrostatic integrated energy harvesting circuit is proposed for efficient harvesting of mechanical energy. The fundamental challenges of designing reliable low power sensing circuits for charge constrained electrostatic energy harvesters with capacity to self power its controller and driver stages are addressed. Experimental results are presented for a controller design implemented in AMI 0.7muM high voltage CMOS process using a macro-scale electrostatic converter prototype. The EHC produces 1.126muW for a power investment of 417nW with combined conduction and controller losses of 450nW which is a 20-30% improvement compared to prior art on electrostatic EHCs operating under charge constrain. Inherently dual plate variable capacitors harvest energy only during half of the mechanical cycle with the other half unutilized for energy conversion. To harvest mechanical energy over the complete mechanical vibration cycle, a low power energy harvesting circuit (EHC) that performs charge constrained synchronous energy conversion on a tri-plate variable capacitor for maximizing energy conversion is proposed. The tri-plate macro electrostatic generator with capacitor variation of 405pF to 1.15nF and 405pF to 1.07nF on two complementary adjacent capacitors is fabricated and used in the characterization of the designed EHC. The integrated circuit fabricated in AMI 0.7muM high voltage CMOS process, produces a total output power of 497nW to a 10muF reservoir capacitor from a 98Hz vibration signal. In summary, the thesis lays out the

  2. Material Targets for Scaling All-Spin Logic

    Science.gov (United States)

    Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

    2016-01-01

    All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

  3. Weakly Intuitionistic Quantum Logic

    NARCIS (Netherlands)

    Hermens, Ronnie

    2013-01-01

    In this article von Neumann's proposal that in quantum mechanics projections can be seen as propositions is followed. However, the quantum logic derived by Birkhoff and von Neumann is rejected due to the failure of the law of distributivity. The options for constructing a distributive logic while

  4. Modal Logics and Definability

    OpenAIRE

    Kuusisto, Antti

    2013-01-01

    In recent years, research into the mathematical foundations of modal logic has become increasingly popular. One of the main reasons for this is the fact that modal logic seems to adapt well to the requirements of a wide range of different fields of application. This paper is a summary of some of the author’s contributions to the understanding of modal definability theory.

  5. Modal logics are coalgebraic

    NARCIS (Netherlands)

    Cirstea, C.; Kurz, A.; Pattinson, D.; Schröder, L.; Venema, Y.

    2011-01-01

    Applications of modal logics are abundant in computer science, and a large number of structurally different modal logics have been successfully employed in a diverse spectrum of application contexts. Coalgebraic semantics, on the other hand, provides a uniform and encompassing view on the large

  6. Description logics of context

    CSIR Research Space (South Africa)

    Klarman, S

    2013-05-01

    Full Text Available We introduce Description Logics of Context (DLCs) - an extension of Description Logics (DLs) for context-based reasoning. Our approach descends from J. McCarthy's tradition of treating contexts as formal objects over which one can quantify...

  7. Criteria for logical formalization

    Czech Academy of Sciences Publication Activity Database

    Peregrin, Jaroslav; Svoboda, Vladimír

    2013-01-01

    Roč. 190, č. 14 (2013), s. 2897-2924 ISSN 0039-7857 R&D Projects: GA ČR(CZ) GAP401/10/1279 Institutional support: RVO:67985955 Keywords : logic * logical form * formalization * reflective equilibrium Subject RIV: AA - Philosophy ; Religion Impact factor: 0.637, year: 2013

  8. Automata, Logic, and XML

    OpenAIRE

    NEVEN, Frank

    2002-01-01

    We survey some recent developments in the broad area of automata and logic which are motivated by the advent of XML. In particular, we consider unranked tree automata, tree-walking automata, and automata over infinite alphabets. We focus on their connection with logic and on questions imposed by XML.

  9. One reason, several logics

    Directory of Open Access Journals (Sweden)

    Evandro Agazzi

    2011-06-01

    Full Text Available Humans have used arguments for defending or refuting statements long before the creation of logic as a specialized discipline. This can be interpreted as the fact that an intuitive notion of "logical consequence" or a psychic disposition to articulate reasoning according to this pattern is present in common sense, and logic simply aims at describing and codifying the features of this spontaneous capacity of human reason. It is well known, however, that several arguments easily accepted by common sense are actually "logical fallacies", and this indicates that logic is not just a descriptive, but also a prescriptive or normative enterprise, in which the notion of logical consequence is defined in a precise way and then certain rules are established in order to maintain the discourse in keeping with this notion. Yet in the justification of the correctness and adequacy of these rules commonsense reasoning must necessarily be used, and in such a way its foundational role is recognized. Moreover, it remains also true that several branches and forms of logic have been elaborated precisely in order to reflect the structural features of correct argument used in different fields of human reasoning and yet insufficiently mirrored by the most familiar logical formalisms.

  10. The logic of ACP

    NARCIS (Netherlands)

    A. Ponse (Alban); M.B. van der Zwaag

    2002-01-01

    textabstractWe distinguish two interpretations for the truth value `undefined' in Kleene's three-valued logic. Combining these two interpretations leads to a four-valued propositional logic that characterizes two particular ingredients of process algebra: ``choice' and ``inaction'. We study two

  11. Anselm's logic of agency

    NARCIS (Netherlands)

    Uckelman, S.L.

    2009-01-01

    The origins of treating agency as a modal concept go back at least to the 11th century when Anselm, Archbishop of Canterbury, provided a modal explication of the Latin facere ‘to do’, which can be formalized within the context of modern modal logic and neighborhood semantics. The agentive logic

  12. Temporalized Epistemic Default Logic

    NARCIS (Netherlands)

    van der Hoek, W.; Meyer, J.J.; Treur, J.; Gabbay, D.

    2001-01-01

    The nonmonotonic logic Epistemic Default Logic (EDL) [Meyer and van der Hoek, 1993] is based on the metaphore of a meta-level architecture. It has already been established [Meyer and van der Hoek, 1993] how upward reflection can be formalized by a nonmonotonic entailment based on epistemic states,

  13. Logic Programming: PROLOG.

    Science.gov (United States)

    Lopez, Antonio M., Jr.

    1989-01-01

    Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)

  14. Honesty in partial logic

    NARCIS (Netherlands)

    W. van der Hoek (Wiebe); J.O.M. Jaspars; E. Thijsse

    1995-01-01

    textabstractWe propose an epistemic logic in which knowledge is fully introspective and implies truth, although truth need not imply epistemic possibility. The logic is presented in sequential format and is interpreted in a natural class of partial models, called balloon models. We examine the

  15. Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

    Science.gov (United States)

    Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

    2008-11-01

    In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

  16. High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

    Science.gov (United States)

    Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

    2016-02-01

    The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

  17. A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

    Science.gov (United States)

    Li, Jin-Jin; Zhu, Ka-Di

    2011-02-04

    Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

  18. A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity

    International Nuclear Information System (INIS)

    Li Jinjin; Zhu Kadi

    2011-01-01

    Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

  19. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  20. Heterogeneous logics of competition

    DEFF Research Database (Denmark)

    Mossin, Christiane

    2015-01-01

    of competition are only realized as particular forms of social organization by virtue of interplaying with other kinds of logics, like legal logics. (2) Competition logics enjoy a peculiar status in-between constructedness and givenness; although competition depends on laws and mechanisms of socialization, we...... still experience competition as an expression of spontaneous human activities. On the basis of these perspectives, a study of fundamental rights of EU law, springing from the principle of ‘free movement of people’, is conducted. The first part of the empirical analysis seeks to detect the presence...... of a presumed logic of competition within EU law, whereas the second part focuses on particular legal logics. In this respect, the so-called ‘real link criterion’ (determining the access to transnational social rights for certain groups of unemployed people) is given special attention. What is particularly...

  1. A low-power timing discriminator for space instrumentation

    International Nuclear Information System (INIS)

    Devoto, P.; Medale, J.-L.; Aoustin, C.; Sauvaud, J.-A.

    2004-01-01

    A front-end electronics for three-dimensional time-of-flight space plasma analyzers has been developed. These mass spectrometers, allowing the determination of the distribution functions of the main ion species, are based on the selection of the ion energy per charge and arrival direction using an electrostatic analyzer, and on the determination of their velocity from the time separating a start and a stop pulse. The start pulse is provided by the collection on a microchannel plate (MCP) of secondary electrons emitted when each ion crosses a thin carbon foil. The stop pulse is provided by the ion hitting a second MCP. The aim of the electronics presented in this article is to process the signals provided by MCPs to generate logic pulses, allowing the measurement of precise time differences. The design consists of an amplifier and a timing discriminator which performs a timing compensation to eliminate the time walk. A first version of the circuit has been developed and achieves a time walk of ∼400 ps for an input amplitude dynamic range of 25 dB. The total power dissipation per channel is ∼14 mW at an event rate of 100 KHz and ∼19 mW at a rate of 1 MHz. The influence of the temperature on the circuit behavior has been investigated. The performances of the circuit in a complete detector were also evaluated. This circuit is designed to be used in various designs for future missions

  2. Bus Implementation Using New Low Power PFSCL Tristate Buffers

    Directory of Open Access Journals (Sweden)

    Neeta Pandey

    2016-01-01

    Full Text Available This paper proposes new positive feedback source coupled logic (PFSCL tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.

  3. Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

    Science.gov (United States)

    Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

    2017-09-01

    Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

  4. Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

    Science.gov (United States)

    Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

    2012-06-01

    High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

  5. Research on laser detonation pulse circuit with low-power based on super capacitor

    Science.gov (United States)

    Wang, Hao-yu; Hong, Jin; He, Aifeng; Jing, Bo; Cao, Chun-qiang; Ma, Yue; Chu, En-yi; Hu, Ya-dong

    2018-03-01

    According to the demand of laser initiating device miniaturization and low power consumption of weapon system, research on the low power pulse laser detonation circuit with super capacitor. Established a dynamic model of laser output based on super capacitance storage capacity, discharge voltage and programmable output pulse width. The output performance of the super capacitor under different energy storage capacity and discharge voltage is obtained by simulation. The experimental test system was set up, and the laser diode of low power pulsed laser detonation circuit was tested and the laser output waveform of laser diode in different energy storage capacity and discharge voltage was collected. Experiments show that low power pulse laser detonation based on super capacitor energy storage circuit discharge with high efficiency, good transient performance, for a low power consumption requirement, for laser detonation system and low power consumption and provide reference light miniaturization of engineering practice.

  6. Junctionless Cooper pair transistor

    Energy Technology Data Exchange (ETDEWEB)

    Arutyunov, K. Yu., E-mail: konstantin.yu.arutyunov@jyu.fi [National Research University Higher School of Economics , Moscow Institute of Electronics and Mathematics, 101000 Moscow (Russian Federation); P.L. Kapitza Institute for Physical Problems RAS , Moscow 119334 (Russian Federation); Lehtinen, J.S. [VTT Technical Research Centre of Finland Ltd., Centre for Metrology MIKES, P.O. Box 1000, FI-02044 VTT (Finland)

    2017-02-15

    Highlights: • Junctionless Cooper pair box. • Quantum phase slips. • Coulomb blockade and gate modulation of the Coulomb gap. - Abstract: Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current–voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

  7. Mesoscopic photon heat transistor

    DEFF Research Database (Denmark)

    Ojanen, T.; Jauho, Antti-Pekka

    2008-01-01

    We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir-Wingreen-Landauer-typ......We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir......-Wingreen-Landauer-type of conductance formula, which gives the photonic heat current through an arbitrary circuit element coupled to two dissipative reservoirs at finite temperatures. As an illustration we present an exact solution for the case when the intermediate circuit can be described as an electromagnetic resonator. We discuss...

  8. Low power laser irradiation does not affect the generation of signals in a sensory receptor

    Energy Technology Data Exchange (ETDEWEB)

    Lundeberg, T.; Zhou, J.

    1989-01-01

    The effect of low power Helium-Neon (He-Ne) and Gallium-Arsenide (Ga-As) laser on the slowly adapting crustacean stretch receptor was studied. The results showed that low power laser irradiation did not affect the membrane potential of the stretch receptor. These results are discussed in relation to the use of low power laser irradiation on the skin overlaying acupuncture points in treatment of pain syndrome.

  9. A study on water level control of PWR steam generator at low power and the self-tuning of its fuzzy controller

    International Nuclear Information System (INIS)

    Na, N.; Kwon, K.; Ham, C.; Bien, Z.

    1994-01-01

    The water level control system of a steam generator in a pressurized water reactor and its control problems during the operation at low power is analysed. In particular, a strategy for a water level control system, which is based on the use of a fuzzy logic controller, is proposed. The control strategy includes dynamic tuning for the large transient. The fuzzy variable of the flow rate during the power operation is obtained from the bypass valve opening and not from the incorrect measured signal at the low flow rate. The practical self-tuning algorithm is based on the optimal control performance

  10. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  11. A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

    2015-01-01

    A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

  12. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  13. High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

    Science.gov (United States)

    Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

    2017-08-01

    In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

  14. THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE

    Science.gov (United States)

    COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS

  15. Relativistic quantum logic

    International Nuclear Information System (INIS)

    Mittelstaedt, P.

    1983-01-01

    on the basis of the well-known quantum logic and quantum probability a formal language of relativistic quantum physics is developed. This language incorporates quantum logical as well as relativistic restrictions. It is shown that relativity imposes serious restrictions on the validity regions of propositions in space-time. By an additional postulate this relativistic quantum logic can be made consistent. The results of this paper are derived exclusively within the formal quantum language; they are, however, in accordance with well-known facts of relativistic quantum physics in Hilbert space. (author)

  16. Coherent quantum logic

    International Nuclear Information System (INIS)

    Finkelstein, D.

    1987-01-01

    The von Neumann quantum logic lacks two basic symmetries of classical logic, that between sets and classes, and that between lower and higher order predicates. Similarly, the structural parallel between the set algebra and linear algebra of Grassmann and Peano was left incomplete by them in two respects. In this work a linear algebra is constructed that completes this correspondence and is interpreted as a new quantum logic that restores these invariances, and as a quantum set theory. It applies to experiments with coherent quantum phase relations between the quantum and the apparatus. The quantum set theory is applied to model a Lorentz-invariant quantum time-space complex

  17. Logical inference and evaluation

    International Nuclear Information System (INIS)

    Perey, F.G.

    1981-01-01

    Most methodologies of evaluation currently used are based upon the theory of statistical inference. It is generally perceived that this theory is not capable of dealing satisfactorily with what are called systematic errors. Theories of logical inference should be capable of treating all of the information available, including that not involving frequency data. A theory of logical inference is presented as an extension of deductive logic via the concept of plausibility and the application of group theory. Some conclusions, based upon the application of this theory to evaluation of data, are also given

  18. Layered Fixed Point Logic

    DEFF Research Database (Denmark)

    Filipiuk, Piotr; Nielson, Flemming; Nielson, Hanne Riis

    2012-01-01

    We present a logic for the specification of static analysis problems that goes beyond the logics traditionally used. Its most prominent feature is the direct support for both inductive computations of behaviors as well as co-inductive specifications of properties. Two main theoretical contributions...... are a Moore Family result and a parametrized worst case time complexity result. We show that the logic and the associated solver can be used for rapid prototyping of analyses and illustrate a wide variety of applications within Static Analysis, Constraint Satisfaction Problems and Model Checking. In all cases...

  19. A multiplicity logic unit

    International Nuclear Information System (INIS)

    Bialkowski, J.; Moszynski, M.; Zagorski, A.

    1981-01-01

    The logic diagram principle of operation and some details of the design of the multiplicity logic unit are presented. This unit was specially designed to fulfil the requirements of a multidetector arrangement for gamma-ray multiplicity measurements. The unit is equipped with 16 inputs controlled by a common coincidence gate. It delivers a linear output pulse with the height proportional to the multiplicity of coincidences and logic pulses corresponding to 0, 1, ... up to >= 5-fold coincidences. These last outputs are used to steer the routing unit working with the multichannel analyser. (orig.)

  20. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    Science.gov (United States)

    Chappanda, K. N.; Ilyas, S.; Younis, M. I.

    2018-05-01

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

  1. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    KAUST Repository

    Chappanda , K. N.; Ilyas, Saad; Younis, Mohammad I.

    2018-01-01

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

  2. Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

    KAUST Repository

    Chappanda, K N

    2018-02-16

    Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.

  3. Study of Reversible Logic Synthesis with Application in SOC: A Review

    Science.gov (United States)

    Sharma, Chinmay; Pahuja, Hitesh; Dadhwal, Mandeep; Singh, Balwinder

    2017-08-01

    The prime concern in today’s SOC designs is the power dissipation which increases with technology scaling. The reversible logic possesses very high potential in reducing power dissipation in these designs. It finds its application in latest research fields such as DNA computing, quantum computing, ultra-low power CMOS design and nanotechnology. The reversible circuits can be easily designed using the conventional CMOS technology at a cost of a garbage output which maintains the reversibility. The purpose of this paper is to provide an overview of the developments that have occurred till date in this concept and how the new reversible logic gates are used to design the logic functions.

  4. Advances in temporal logic

    CERN Document Server

    Fisher, Michael; Gabbay, Dov; Gough, Graham

    2000-01-01

    Time is a fascinating subject that has captured mankind's imagination from ancient times to the present. It has been, and continues to be studied across a wide range of disciplines, from the natural sciences to philosophy and logic. More than two decades ago, Pnueli in a seminal work showed the value of temporal logic in the specification and verification of computer programs. Today, a strong, vibrant international research community exists in the broad community of computer science and AI. This volume presents a number of articles from leading researchers containing state-of-the-art results in such areas as pure temporal/modal logic, specification and verification, temporal databases, temporal aspects in AI, tense and aspect in natural language, and temporal theorem proving. Earlier versions of some of the articles were given at the most recent International Conference on Temporal Logic, University of Manchester, UK. Readership: Any student of the area - postgraduate, postdoctoral or even research professor ...

  5. Logic and Learning

    DEFF Research Database (Denmark)

    Hendricks, Vincent Fella; Gierasimczuk, Nina; de Jong, Dick

    2014-01-01

    Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study of inform......Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study...... of information processing, but likewise helped bring logic and learning in close proximity. This proximity relation is examined with respect to learning and belief revision, updating and efficiency, and with respect to how learnability fits in the greater scheme of dynamic epistemic logic and scientific method....

  6. Characterization of quantum logics

    International Nuclear Information System (INIS)

    Lahti, P.J.

    1980-01-01

    The quantum logic approach to axiomatic quantum mechanics is used to analyze the conceptual foundations of the traditional quantum theory. The universal quantum of action h>0 is incorporated into the theory by introducing the uncertainty principle, the complementarity principle, and the superposition principle into the framework. A characterization of those quantum logics (L,S) which may provide quantum descriptions is then given. (author)

  7. A Conceptual Space Logic

    DEFF Research Database (Denmark)

    Nilsson, Jørgen Fischer

    1999-01-01

    Conceptual spaces have been proposed as topological or geometric means for establishing conceptual structures and models. This paper, after briey reviewing conceptual spaces, focusses on the relationship between conceptual spaces and logical concept languages with operations for combining concepts...... to form concepts. Speci cally is introduced an algebraic concept logic, for which conceptual spaces are installed as semantic domain as replacement for, or enrichment of, the traditional....

  8. 47 CFR 74.793 - Digital low power TV and TV translator station protection of broadcast stations.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.793 Digital low power TV and TV translator station protection of broadcast stations. (a) An application to construct a new digital low power...

  9. Extending Value Logic Thinking to Value Logic Portfolios

    DEFF Research Database (Denmark)

    Andersen, Poul Houman; Ritter, Thomas

    2014-01-01

    Based on value creation logic theory (Stabell & Fjeldstad, 1998), this paper suggests an extension of the original Stabell & Fjeldstad model by an additional fourth value logic, the value system logic. Furthermore, instead of only allowing one dominant value creation logic for a given firm...... or transaction, an understanding of firms and transactions as a portfolio of value logics (i.e. an interconnected coexistence of different value creation logics) is proposed. These additions to the original value creation logic theory imply interesting avenues for both, strategic decision making in firms...

  10. On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

    Science.gov (United States)

    Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

    2017-11-28

    Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

  11. 76 FR 81998 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2011-12-29

    ... NUCLEAR REGULATORY COMMISSION [NRC-2011-0295] Methodology for Low Power/Shutdown Fire PRA AGENCY..., ``Methodology for Low Power/Shutdown Fire PRA--Draft Report for Comment.'' DATES: Submit comments by March 01... risk assessment (PRA) method for quantitatively analyzing fire risk in commercial nuclear power plants...

  12. Radio frequency energy harvesting and low power data transmission for autonomous wireless sensor nodes

    NARCIS (Netherlands)

    Rodrigues Mansano, A.L.

    2016-01-01

    Since the Internet of Things (IoT) is expected to be the new technology to drive the semiconductor industry, significant research efforts have been made to develop new circuit and system techniques for autonomous/very low-power operation of wireless sensor nodes. Very low-power consumption of

  13. 76 FR 44821 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-07-27

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend Rules... Digital Low Power Television, Television Translator, and Television Booster Stations and to Amend Rules... translator facilities in the 700 MHz band. These provisions provide procedures for a primary wireless...

  14. 76 FR 72849 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-11-28

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend Rules... for Digital Low Power Television, Television Translator, and Television Booster Stations and to Amend... television, TV translator, and Class A television station DTV licensees''). The Commission has also revised...

  15. 75 FR 63766 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2010-10-18

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A... TV, TV Translator or TV Booster Station, FCC Form 346; 47 CFR 74.793(d); LPTV Out-of-Core Digital... collection requirements: 47 CFR 74.793(d) proposes that certain digital low power and TV translator stations...

  16. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  17. Towards a Formal Occurrence Logic based on Predicate Logic

    DEFF Research Database (Denmark)

    Badie, Farshad; Götzsche, Hans

    2015-01-01

    In this discussion we will concentrate on the main characteristics of an alternative kind of logic invented by Hans Götzsche: Occurrence Logic, which is not based on truth functionality. Our approach is based on temporal logic developed and elaborated by A. N. Prior. We will focus on characterising...... argumentation based on formal Occurrence Logic concerning events and occurrences, and illustrate the relations between Predicate Logic and Occurrence Logic. The relationships (and dependencies) is conducive to an approach that can analyse the occurrences of ”logical statements based on different logical...... principles” in different moments. We will also conclude that the elaborated Götzsche’s Occurrence Logic could be able to direct us to a truth-functional independent computer-based logic for analysing argumentation based on events and occurrences....

  18. Dosimetric properties of MOS transistors

    International Nuclear Information System (INIS)

    Peter, I.; Frank, G.

    1977-01-01

    The performance of MOS transistors as gamma detectors has been tested. The dosimeter sensitivity has proved to be independent on the doses ranging from 10 3 to 10 6 R, and gamma energy of 137 Cs, 60 Co - sources and 5 - 18 MeV electrons. Fading of the space charge trapped by the SiO 2 layer of the transistor has appeared to be neglegible at room temperature after 400 hrs. The isochronous annealing in the temperature range of 40-260 deg C had a more substantial effect on the space charge of the transistor irradiated with 18 MeV electrons than on the 137 Cs gamma-irradiated transistors. This proved a repeated use of γ-dosemeters. MOS transistors are concluded to be promising for gamma dosimetry [ru

  19. High voltage generator circuit with low power and high efficiency applied in EEPROM

    International Nuclear Information System (INIS)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

  20. Spintronic logic design methodology based on spin Hall effect–driven magnetic tunnel junctions

    International Nuclear Information System (INIS)

    Kang, Wang; Zhang, Youguang; Zhao, Weisheng; Wang, Zhaohao; Klein, Jacques-Olivier; Lv, Weifeng

    2016-01-01

    Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau–Lifshitz–Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing. (paper)

  1. Power Conversion Efficiency of AlGaAs/GaAs Schottky Diode for Low-Power On-Chip Rectenna Device Application

    International Nuclear Information System (INIS)

    Mustafa, Farahiyah; Hashim, Abdul Manaf; Rahman, Shaharin Fadzli Abd; Osman, Mohd Nizam

    2011-01-01

    A Schottky diode has been designed and fabricated on n-AlGaAs/GaAs high-electron-mobility-transistor (HEMT) structure. Current-voltage (I-V) measurements show good device rectification with a Schottky barrier height of 0.4349 eV for Ni/Au metallization. The differences of Schottky barrier height from theoretical value are due to the fabrication process and smaller contact area. The RF signals up to 1 GHz are well rectified by the fabricated Schottky diodes and stable DC output voltage is obtained. Power conversion efficiency up to 50% is obtained at 1 GHz with series connection between diode and load. The fabricated the n-AlGaAs/GaAs Schottky diode provide conduit for breakthrough designs for ultra-low power on-chip rectenna device technology to be integrated in nanosystems.

  2. Spin Hall effect transistor

    Czech Academy of Sciences Publication Activity Database

    Wunderlich, Joerg; Park, B.G.; Irvine, A.C.; Zarbo, Liviu; Rozkotová, E.; Němec, P.; Novák, Vít; Sinova, Jairo; Jungwirth, Tomáš

    2010-01-01

    Roč. 330, č. 6012 (2010), s. 1801-1804 ISSN 0036-8075 R&D Projects: GA AV ČR KAN400100652; GA MŠk LC510 EU Projects: European Commission(XE) 215368 - SemiSpinNet Grant - others:AV ČR(CZ) AP0801 Program:Akademická prémie - Praemium Academiae Institutional research plan: CEZ:AV0Z10100521 Keywords : spin Hall effect * spintronics * spin transistor Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 31.364, year: 2010

  3. Modern logic and quantum mechanics

    International Nuclear Information System (INIS)

    Garden, R.W.

    1984-01-01

    The book applies the methods of modern logic and probabilities to ''interpreting'' quantum mechanics. The subject is described and discussed under the chapter headings: classical and quantum mechanics, modern logic, the propositional logic of mechanics, states and measurement in mechanics, the traditional analysis of probabilities, the probabilities of mechanics and the model logic of predictions. (U.K.)

  4. Semantic theory for logic programming

    Energy Technology Data Exchange (ETDEWEB)

    Brown, F M

    1981-01-01

    The author axiomatizes a number of meta theoretic concepts which have been used in logic programming, including: meaning, logical truth, nonentailment, assertion and erasure, thus showing that these concepts are logical in nature and need not be defined as they have previously been defined in terms of the operations of any particular interpreter for logic programs. 10 references.

  5. Relational Parametricity and Separation Logic

    DEFF Research Database (Denmark)

    Birkedal, Lars; Yang, Hongseok

    2008-01-01

    Separation logic is a recent extension of Hoare logic for reasoning about programs with references to shared mutable data structures. In this paper, we provide a new interpretation of the logic for a programming language with higher types. Our interpretation is based on Reynolds's relational...... parametricity, and it provides a formal connection between separation logic and data abstraction. Udgivelsesdato: 2008...

  6. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-01-25

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

  7. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    International Nuclear Information System (INIS)

    Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

    2016-01-01

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

  8. Non-logic devices in logic processes

    CERN Document Server

    Ma, Yanjun

    2017-01-01

    This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes.  Readers will benefit from the author’s extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.

  9. Physical limits of silicon transistors and circuits

    International Nuclear Information System (INIS)

    Keyes, Robert W

    2005-01-01

    A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented

  10. Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

    Science.gov (United States)

    Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

    2017-07-10

    Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

  11. Parametrization of the radiation induced leakage current increase of NMOS transistors

    International Nuclear Information System (INIS)

    Backhaus, M.

    2017-01-01

    The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

  12. A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

    International Nuclear Information System (INIS)

    Wu, Ming-Chi; Tseng, Tseung-Yuen; Jang, Wen-Yueh; Lin, Chen-Hsi

    2012-01-01

    Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO 2 /Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO 2 /Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO 2 -based RRAM is a prospective alternative for nonvolatile multilevel memory device applications. (paper)

  13. Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

    Science.gov (United States)

    Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

    2014-06-13

    Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

  14. Modal Logics with Counting

    Science.gov (United States)

    Areces, Carlos; Hoffmann, Guillaume; Denis, Alexandre

    We present a modal language that includes explicit operators to count the number of elements that a model might include in the extension of a formula, and we discuss how this logic has been previously investigated under different guises. We show that the language is related to graded modalities and to hybrid logics. We illustrate a possible application of the language to the treatment of plural objects and queries in natural language. We investigate the expressive power of this logic via bisimulations, discuss the complexity of its satisfiability problem, define a new reasoning task that retrieves the cardinality bound of the extension of a given input formula, and provide an algorithm to solve it.

  15. Diagnosable structured logic array

    Science.gov (United States)

    Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)

    2009-01-01

    A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

  16. VHDL for logic synthesis

    CERN Document Server

    Rushton, Andrew

    2011-01-01

    Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types. This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features. Features to this edition include: * a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies...

  17. Fuzzy logic in management

    CERN Document Server

    Carlsson, Christer; Fullér, Robert

    2004-01-01

    Fuzzy Logic in Management demonstrates that difficult problems and changes in the management environment can be more easily handled by bringing fuzzy logic into the practice of management. This explicit theme is developed through the book as follows: Chapter 1, "Management and Intelligent Support Technologies", is a short survey of management leadership and what can be gained from support technologies. Chapter 2, "Fuzzy Sets and Fuzzy Logic", provides a short introduction to fuzzy sets, fuzzy relations, the extension principle, fuzzy implications and linguistic variables. Chapter 3, "Group Decision Support Systems", deals with group decision making, and discusses methods for supporting the consensus reaching processes. Chapter 4, "Fuzzy Real Options for Strategic Planning", summarizes research where the fuzzy real options theory was implemented as a series of models. These models were thoroughly tested on a number of real life investments, and validated in 2001. Chapter 5, "Soft Computing Methods for Reducing...

  18. Continuous Markovian Logics

    DEFF Research Database (Denmark)

    Mardare, Radu Iulian; Cardelli, Luca; Larsen, Kim Guldstrand

    2012-01-01

    Continuous Markovian Logic (CML) is a multimodal logic that expresses quantitative and qualitative properties of continuous-time labelled Markov processes with arbitrary (analytic) state-spaces, henceforth called continuous Markov processes (CMPs). The modalities of CML evaluate the rates...... of the exponentially distributed random variables that characterize the duration of the labeled transitions of a CMP. In this paper we present weak and strong complete axiomatizations for CML and prove a series of metaproperties, including the finite model property and the construction of canonical models. CML...... characterizes stochastic bisimilarity and it supports the definition of a quantified extension of the satisfiability relation that measures the "compatibility" between a model and a property. In this context, the metaproperties allows us to prove two robustness theorems for the logic stating that one can...

  19. Programmable automated transistor test system

    International Nuclear Information System (INIS)

    Truong, L.V.; Sundberg, G.R.

    1986-01-01

    The paper describes a programmable automated transistor test system (PATTS) and its utilization to evaluate bipolar transistors and Darlingtons, and such MOSFET and special types as can be accommodated with the PATTS base-drive. An application of a pulsed power technique at low duty cycles in a non-destructive test is used to examine the dynamic switching characteristic curves of power transistors. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software. In addition a library of test data is established on disks, tapes, and hard copies for future reference

  20. Accident sequence analysis for a BWR [Boiling Water Reactor] during low power and shutdown operations

    International Nuclear Information System (INIS)

    Whitehead, D.W.; Hake, T.M.

    1990-01-01

    Most previous Probabilistic Risk Assessments have excluded consideration of accidents initiated in low power and shutdown modes of operation. A study of the risk associated with operation in low power and shutdown is being performed at Sandia National Laboratories for a US Boiling Water Reactor (BWR). This paper describes the proposed methodology for the analysis of the risk associated with the operation of a BWR during low power and shutdown modes and presents preliminary information resulting from the application of the methodology. 2 refs., 2 tabs

  1. Low-Power Differential SRAM design for SOC Based on the 25-um Technology

    Science.gov (United States)

    Godugunuri, Sivaprasad; Dara, Naveen; Sambasiva Nayak, R.; Nayeemuddin, Md; Singh, Yadu, Dr.; Veda, R. N. S. Sunil

    2017-08-01

    In recent, the SOC styles area unit the vast complicated styles in VLSI these SOC styles having important low-power operations problems, to comprehend this we tend to enforced low-power SRAM. However these SRAM Architectures critically affects the entire power of SOC and competitive space. To beat the higher than disadvantages, during this paper, a low-power differential SRAM design is planned. The differential SRAM design stores multiple bits within the same cell, operates at minimum in operation low-tension and space per bit. The differential SRAM design designed supported the 25-um technology using Tanner-EDA Tool.

  2. MANUAL LOGIC CONTROLLER (MLC)

    OpenAIRE

    Claude Ziad Bayeh

    2015-01-01

    The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...

  3. Set theory and logic

    CERN Document Server

    Stoll, Robert R

    1979-01-01

    Set Theory and Logic is the result of a course of lectures for advanced undergraduates, developed at Oberlin College for the purpose of introducing students to the conceptual foundations of mathematics. Mathematics, specifically the real number system, is approached as a unity whose operations can be logically ordered through axioms. One of the most complex and essential of modern mathematical innovations, the theory of sets (crucial to quantum mechanics and other sciences), is introduced in a most careful concept manner, aiming for the maximum in clarity and stimulation for further study in

  4. Introduction to mathematical logic

    CERN Document Server

    Mendelson, Elliott

    2009-01-01

    The Propositional CalculusPropositional Connectives. Truth TablesTautologies Adequate Sets of Connectives An Axiom System for the Propositional Calculus Independence. Many-Valued LogicsOther AxiomatizationsFirst-Order Logic and Model TheoryQuantifiersFirst-Order Languages and Their Interpretations. Satisfiability and Truth. ModelsFirst-Order TheoriesProperties of First-Order Theories Additional Metatheorems and Derived Rules Rule C Completeness Theorems First-Order Theories with EqualityDefinitions of New Function Letters and Individual Constants Prenex Normal Forms Isomorphism of Interpretati

  5. The Logic of XACML

    DEFF Research Database (Denmark)

    Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming

    2011-01-01

    We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML....... To guard against modelling artefacts we provide an alternative way of characterizing the policy combining algorithms and we formally prove the equivalence of these approaches. This allows us to pinpoint the shortcoming of previous approaches to formalization based either on Belnap logic or on D -algebra....

  6. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  7. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  8. Logic of the digital

    CERN Document Server

    Evens, Aden

    2015-01-01

    Building a foundational understanding of the digital, Logic of the Digital reveals a unique digital ontology. Beginning from formal and technical characteristics, especially the binary code at the core of all digital technologies, Aden Evens traces the pathways along which the digital domain of abstract logic encounters the material, human world. How does a code using only 0s and 1s give rise to the vast range of applications and information that constitutes a great and growing portion of our world? Evens' analysis shows how any encounter between the actual and the digital must cross an ontolo

  9. Quantum logics with existence property

    International Nuclear Information System (INIS)

    Schindler, C.

    1991-01-01

    A quantum logic (σ-orthocomplete orthomodular poset L with a convex, unital, and separating set Δ of states) is said to have the existence property if the expectation functionals on lin(Δ) associated with the bounded observables of L form a vector space. Classical quantum logics as well as the Hilbert space logics of traditional quantum mechanics have this property. The author shows that, if a quantum logic satisfies certain conditions in addition to having property E, then the number of its blocks (maximal classical subsystems) must either be one (classical logics) or uncountable (as in Hilbert space logics)

  10. GOAL Agents Instantiate Intention Logic

    OpenAIRE

    Hindriks, Koen; van der Hoek, Wiebe

    2008-01-01

    It is commonly believed there is a big gap between agent logics and computational agent frameworks. In this paper, we show that this gap is not as big as believed by showing that GOAL agents instantiate Intention Logic of Cohen and Levesque. That is, we show that GOAL agent programs can be formally related to Intention Logic.We do so by proving that the GOAL Verification Logic can be embedded into Intention Logic. It follows that (a fragment of) Intention Logic can be used t...

  11. Querying Natural Logic Knowledge Bases

    DEFF Research Database (Denmark)

    Andreasen, Troels; Bulskov, Henrik; Jensen, Per Anker

    2017-01-01

    This paper describes the principles of a system applying natural logic as a knowledge base language. Natural logics are regimented fragments of natural language employing high level inference rules. We advocate the use of natural logic for knowledge bases dealing with querying of classes...... in ontologies and class-relationships such as are common in life-science descriptions. The paper adopts a version of natural logic with recursive restrictive clauses such as relative clauses and adnominal prepositional phrases. It includes passive as well as active voice sentences. We outline a prototype...... for partial translation of natural language into natural logic, featuring further querying and conceptual path finding in natural logic knowledge bases....

  12. High transconductance organic electrochemical transistors

    Science.gov (United States)

    Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

    2013-07-01

    The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

  13. Organic tunnel field effect transistors

    KAUST Repository

    Tietze, Max Lutz; Lussem, Bjorn; Liu, Shiyi

    2017-01-01

    Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer

  14. High transconductance organic electrochemical transistors

    Science.gov (United States)

    Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

    2013-01-01

    The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

  15. Some relationships between logic programming and multiple-valued logic

    International Nuclear Information System (INIS)

    Rine, D.C.

    1986-01-01

    There have been suggestions in the artificial intelligence literature that investigations into relationships between logic programming and multiple-valued logic may be helpful. This paper presents some of these relationships through equivalent algebraic evaluations

  16. Delay-limited capacity of fading multiple access and broadcast channels in the low power regime

    KAUST Repository

    Rezki, Zouheir; Alouini, Mohamed-Slim

    2015-01-01

    show that for fading channels where the MAC capacity region is strictly positive, it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power, the boundary

  17. On the capacity of multiaccess fading channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir; Alouini, Mohamed-Slim

    2013-01-01

    multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum rate maximizer

  18. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  19. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  20. Ultra low-power biomedical signal processing : An analog wavelet filter approach for pacemakers

    NARCIS (Netherlands)

    Pavlík Haddad, S.A.

    2006-01-01

    The purpose of this thesis is to describe novel signal processing methodologies and analog integrated circuit techniques for low-power biomedical systems. Physiological signals, such as the electrocardiogram (ECG), the electroencephalogram (EEG) and the electromyogram (EMG) are mostly

  1. Low-Power Large-Area Radiation Detector for Space Science Measurements

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of this task is to develop a low-power, large-area detectors from SiC, taking advantage of very low thermal noise characteristics and high radiation...

  2. Probabilistic safety assessments of nuclear power plants for low power and shutdown modes

    International Nuclear Information System (INIS)

    2000-03-01

    Within the past several years the results of nuclear power plant operating experience and performance of probabilistic safety assessments (PSAs) for low power and shutdown operating modes have revealed that the risk from operating modes other than full power may contribute significantly to the overall risk from plant operations. These early results have led to an increased focus on safety during low power and shutdown operating modes and to an increased interest of many plant operators in performing shutdown and low power PSAs. This publication was developed to provide guidance and insights on the performance of PSA for shutdown and low power operating modes. The preparation of this publication was initiated in 1994. Two technical consultants meetings were conducted in 1994 and one in February 1999 in support of the development of this report

  3. Compact Low-Power Driver for Deformable Mirror Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Boston Micromachines Corporation (BMC), a leading developer of unique, high-resolution micromachined deformable mirrors (DMs), will develop a compact, low-power,...

  4. Shutdown and low-power operation at commercial nuclear power plants in the United States

    International Nuclear Information System (INIS)

    1993-09-01

    The report contains the results of the NRC Staff's evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements

  5. Low power consumption O-band VCSEL sources for upstream channels in PON systems

    DEFF Research Database (Denmark)

    Vegas Olmos, Juan José; Rodes Lopez, Roberto; Tafur Monroy, Idelfonso

    2012-01-01

    This paper presents an experimental validation of a low power optical network unit employing vertical-cavity surface-emitting lasers as upstream sources for passive optical networks with an increased power budget, enabling even larger splitting ratios....

  6. Circuit Simulation of All-Spin Logic

    KAUST Repository

    Alawein, Meshal

    2016-05-01

    With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall

  7. Dosimetric properties of MOS transistors

    International Nuclear Information System (INIS)

    Frank, H.; Petr, I.

    1977-01-01

    The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

  8. The logic of XACML

    DEFF Research Database (Denmark)

    Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming

    2014-01-01

    We study the international standard XACML 3.0 for describing security access control policies in a compositional way. Our main contributions are (i) to derive a logic that precisely captures the intentions of the standard, (ii) to formally define a semantics for the XACML 3.0 component evaluation...

  9. The Logic of XACML

    DEFF Research Database (Denmark)

    Ramli, Carroline Dewi Puspa Kencana; Nielson, Hanne Riis; Nielson, Flemming

    2011-01-01

    We study the international standard XACML 3.0 for describing security access control policy in a compositional way. Our main contribution is to derive a logic that precisely captures the idea behind the standard and to formally define the semantics of the policy combining algorithms of XACML...

  10. Categories and logical syntax

    NARCIS (Netherlands)

    Klev, Ansten Morch

    2014-01-01

    The notions of category and type are here studied through the lens of logical syntax: Aristotle's as well as Kant's categories through the traditional form of proposition `S is P', and modern doctrines of type through the Fregean form of proposition `F(a)', function applied to argument. Topics

  11. Structures for Epistemic Logic

    NARCIS (Netherlands)

    Bezhanishvili, N.; Hoek, W. van der

    2013-01-01

    Epistemic modal logic in a narrow sense studies and formalises reasoning about knowledge. In a wider sense, it gives a formal account of the informational attitude that agents may have, and covers notions like knowledge, belief, uncertainty, and hence incomplete or partial information. As is so

  12. Time and Logic

    DEFF Research Database (Denmark)

    Øhrstrøm, Peter

    2009-01-01

    's notion of branching time is analysed. It is argued that Prior can be criticized for identifying 'plain future'. Finally, Prior's four grades of tense-logical involvement are introduced and discussed. It is argued that the third grade is the most attractive form a philosophical point of view....

  13. Expressivist Perspective on Logicality

    Czech Academy of Sciences Publication Activity Database

    Arazim, Pavel

    2017-01-01

    Roč. 11, č. 4 (2017), s. 409-419 ISSN 1661-8297 R&D Projects: GA ČR(CZ) GA17-15645S Institutional support: RVO:67985955 Keywords : logical constant * expressivism * topic-neutrality * proof- theory * conservativity Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology

  14. Fictional Separation Logic

    DEFF Research Database (Denmark)

    Jensen, Jonas Buhrkal; Birkedal, Lars

    2012-01-01

    , separation means physical separation. In this paper, we introduce \\emph{fictional separation logic}, which includes more general forms of fictional separating conjunctions P * Q, where "*" does not require physical separation, but may also be used in situations where the memory resources described by P and Q...

  15. Dedekind’s logicism

    Czech Academy of Sciences Publication Activity Database

    Klev, Ansten

    2017-01-01

    Roč. 25, č. 3 (2017), s. 341-368 ISSN 0031-8019 Institutional support: RVO:67985955 Keywords : Philosophy of mathematics * logicism * Richard Dedekind Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology Impact factor: 0.419, year: 2016

  16. Modular Logic Metaprogramming

    DEFF Research Database (Denmark)

    Klose, Karl; Ostermann, Klaus

    2010-01-01

    In logic metaprogramming, programs are not stored as plain textfiles but rather derived from a deductive database. While the benefits of this approach for metaprogramming are obvious, its incompatibility with separate checking limits its applicability to large-scale projects. We analyze the probl...

  17. LOGICAL SEMANTICS OF MODULARIZATION

    NARCIS (Netherlands)

    DELAVALETTE, GRR

    1992-01-01

    An algebra of theories, signatures, renamings and the operations import and export is investigated. A normal form theorem for terms of this algebra is proved. Another algebraic approach and the relation with a fragment of second order logic are also considered.

  18. Duration Calculus: Logical Foundations

    DEFF Research Database (Denmark)

    Hansen, Michael Reichhardt; Chaochen, Zhou

    1997-01-01

    The Duration Calculus (abbreviated DC) represents a logical approach to formal design of real-time systems, where real numbers are used to model time and Boolean valued functions over time are used to model states and events of real-time systems. Since it introduction, DC has been applied to many...

  19. Logicism, intuitionism, and formalism

    CERN Document Server

    Symons, John

    2008-01-01

    Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.

  20. Foundations of mathematical logic

    CERN Document Server

    Curry, Haskell B

    2010-01-01

    Written by a pioneer of mathematical logic, this comprehensive graduate-level text explores the constructive theory of first-order predicate calculus. It covers formal methods, including algorithms and epitheory, and offers a brief treatment of Markov's approach to algorithms, explains elementary facts about lattices and similar algebraic systems, and more. 1963 edition.