WorldWideScience

Sample records for lensfree on-chip imaging

  1. Wide-field computational imaging of pathology slides using lens-free on-chip microscopy.

    Science.gov (United States)

    Greenbaum, Alon; Zhang, Yibo; Feizi, Alborz; Chung, Ping-Luen; Luo, Wei; Kandukuri, Shivani R; Ozcan, Aydogan

    2014-12-17

    Optical examination of microscale features in pathology slides is one of the gold standards to diagnose disease. However, the use of conventional light microscopes is partially limited owing to their relatively high cost, bulkiness of lens-based optics, small field of view (FOV), and requirements for lateral scanning and three-dimensional (3D) focus adjustment. We illustrate the performance of a computational lens-free, holographic on-chip microscope that uses the transport-of-intensity equation, multi-height iterative phase retrieval, and rotational field transformations to perform wide-FOV imaging of pathology samples with comparable image quality to a traditional transmission lens-based microscope. The holographically reconstructed image can be digitally focused at any depth within the object FOV (after image capture) without the need for mechanical focus adjustment and is also digitally corrected for artifacts arising from uncontrolled tilting and height variations between the sample and sensor planes. Using this lens-free on-chip microscope, we successfully imaged invasive carcinoma cells within human breast sections, Papanicolaou smears revealing a high-grade squamous intraepithelial lesion, and sickle cell anemia blood smears over a FOV of 20.5 mm(2). The resulting wide-field lens-free images had sufficient image resolution and contrast for clinical evaluation, as demonstrated by a pathologist's blinded diagnosis of breast cancer tissue samples, achieving an overall accuracy of ~99%. By providing high-resolution images of large-area pathology samples with 3D digital focus adjustment, lens-free on-chip microscopy can be useful in resource-limited and point-of-care settings. Copyright © 2014, American Association for the Advancement of Science.

  2. Wide-field synovial fluid imaging using polarized lens-free on-chip microscopy for point-of-care diagnostics of gout (Conference Presentation)

    Science.gov (United States)

    Zhang, Yibo; Lee, Seung Yoon; Zhang, Yun; Furst, Daniel; Fitzgerald, John; Ozcan, Aydogan

    2016-03-01

    Gout and pseudogout are forms of crystal arthropathy caused by monosodium urate (MSU) and calcium pyrophosphate dehydrate (CPPD) crystals in the joint, respectively, that can result in painful joints. Detecting the unique-shaped, birefringent MSU/CPPD crystals in a synovial fluid sample using a compensated polarizing microscope has been the gold-standard for diagnosis since the 1960's. However, this can be time-consuming and inaccurate, especially if there are only few crystals in the fluid. The high-cost and bulkiness of conventional microscopes can also be limiting for point-of-care diagnosis. Lens-free on-chip microscopy based on digital holography routinely achieves high-throughput and high-resolution imaging in a cost-effective and field-portable design. Here we demonstrate, for the first time, polarized lens-free on-chip imaging of MSU and CPPD crystals over a wide field-of-view (FOV ~ 20.5 mm2, i.e., slide, after which a quarter-wave-plate and an angle-mismatched linear polarizer are used to analyze the transmitted light. Two lens-free holograms of the MSU/CPPD sample are taken, with the sample rotated by 90°, to rule out any non-birefringent objects within the specimen. A phase-recovery algorithm is also used to improve the reconstruction quality, and digital pseudo-coloring is utilized to match the color and contrast of the lens-free image to that of a gold-standard microscope image to ease the examination by a rheumatologist or a laboratory technician, and to facilitate computerized analysis.

  3. Rapid, portable and cost-effective yeast cell viability and concentration analysis using lensfree on-chip microscopy and machine learning

    KAUST Repository

    Feizi, Alborz

    2016-09-24

    Monitoring yeast cell viability and concentration is important in brewing, baking and biofuel production. However, existing methods of measuring viability and concentration are relatively bulky, tedious and expensive. Here we demonstrate a compact and cost-effective automatic yeast analysis platform (AYAP), which can rapidly measure cell concentration and viability. AYAP is based on digital in-line holography and on-chip microscopy and rapidly images a large field-of-view of 22.5 mm2. This lens-free microscope weighs 70 g and utilizes a partially-coherent illumination source and an opto-electronic image sensor chip. A touch-screen user interface based on a tablet-PC is developed to reconstruct the holographic shadows captured by the image sensor chip and use a support vector machine (SVM) model to automatically classify live and dead cells in a yeast sample stained with methylene blue. In order to quantify its accuracy, we varied the viability and concentration of the cells and compared AYAP\\'s performance with a fluorescence exclusion staining based gold-standard using regression analysis. The results agree very well with this gold-standard method and no significant difference was observed between the two methods within a concentration range of 1.4 × 105 to 1.4 × 106 cells per mL, providing a dynamic range suitable for various applications. This lensfree computational imaging technology that is coupled with machine learning algorithms would be useful for cost-effective and rapid quantification of cell viability and density even in field and resource-poor settings.

  4. Lensfree optofluidic microscopy and tomography.

    Science.gov (United States)

    Bishara, Waheb; Isikman, Serhan O; Ozcan, Aydogan

    2012-02-01

    Microfluidic devices aim at miniaturizing, automating, and lowering the cost of chemical and biological sample manipulation and detection, hence creating new opportunities for lab-on-a-chip platforms. Recently, optofluidic devices have also emerged where optics is used to enhance the functionality and the performance of microfluidic components in general. Lensfree imaging within microfluidic channels is one such optofluidic platform, and in this article, we focus on the holographic implementation of lensfree optofluidic microscopy and tomography, which might provide a simpler and more powerful solution for three-dimensional (3D) on-chip imaging. This lensfree optofluidic imaging platform utilizes partially coherent digital in-line holography to allow phase and amplitude imaging of specimens flowing through micro-channels, and takes advantage of the fluidic flow to achieve higher spatial resolution imaging compared to a stationary specimen on the same chip. In addition to this, 3D tomographic images of the same samples can also be reconstructed by capturing lensfree projection images of the samples at various illumination angles as a function of the fluidic flow. Based on lensfree digital holographic imaging, this optofluidic microscopy and tomography concept could be valuable especially for providing a compact, yet powerful toolset for lab-on-a-chip devices.

  5. Whole slide imaging of unstained tissue using lensfree microscopy

    Science.gov (United States)

    Morel, Sophie Nhu An; Hervé, Lionel; Bordy, Thomas; Cioni, Olivier; Delon, Antoine; Fromentin, Catherine; Dinten, Jean-Marc; Allier, Cédric

    2016-04-01

    Pathologist examination of tissue slides provides insightful information about a patient's disease. Traditional analysis of tissue slides is performed under a binocular microscope, which requires staining of the sample and delays the examination. We present a simple cost-effective lensfree imaging method to record 2-4μm resolution wide-field (10 mm2 to 6 cm2) images of unstained tissue slides. The sample processing time is reduced as there is no need for staining. A wide field of view (10 mm2) lensfree hologram is recorded in a single shot and the image is reconstructed in 2s providing a very fast acquisition chain. The acquisition is multispectral, i.e. multiple holograms are recorded simultaneously at three different wavelengths, and a dedicated holographic reconstruction algorithm is used to retrieve both amplitude and phase. Whole tissue slides imaging is obtained by recording 130 holograms with X-Y translation stages and by computing the mosaic of a 25 x 25 mm2 reconstructed image. The reconstructed phase provides a phase-contrast-like image of the unstained specimen, revealing structures of healthy and diseased tissue. Slides from various organs can be reconstructed, e.g. lung, colon, ganglion, etc. To our knowledge, our method is the first technique that enables fast wide-field lensfree imaging of such unlabeled dense samples. This technique is much cheaper and compact than a conventional phase contrast microscope and could be made portable. In sum, we present a new methodology that could quickly provide useful information when a rapid diagnosis is needed, such as tumor margin identification on frozen section biopsies during surgery.

  6. Fusion of lens-free microscopy and mobile-phone microscopy images for high-color-accuracy and high-resolution pathology imaging

    Science.gov (United States)

    Zhang, Yibo; Wu, Yichen; Zhang, Yun; Ozcan, Aydogan

    2017-03-01

    Digital pathology and telepathology require imaging tools with high-throughput, high-resolution and accurate color reproduction. Lens-free on-chip microscopy based on digital in-line holography is a promising technique towards these needs, as it offers a wide field of view (FOV >20 mm2) and high resolution with a compact, low-cost and portable setup. Color imaging has been previously demonstrated by combining reconstructed images at three discrete wavelengths in the red, green and blue parts of the visible spectrum, i.e., the RGB combination method. However, this RGB combination method is subject to color distortions. To improve the color performance of lens-free microscopy for pathology imaging, here we present a wavelet-based color fusion imaging framework, termed "digital color fusion microscopy" (DCFM), which digitally fuses together a grayscale lens-free microscope image taken at a single wavelength and a low-resolution and low-magnification color-calibrated image taken by a lens-based microscope, which can simply be a mobile phone based cost-effective microscope. We show that the imaging results of an H&E stained breast cancer tissue slide with the DCFM technique come very close to a color-calibrated microscope using a 40x objective lens with 0.75 NA. Quantitative comparison showed 2-fold reduction in the mean color distance using the DCFM method compared to the RGB combination method, while also preserving the high-resolution features of the lens-free microscope. Due to the cost-effective and field-portable nature of both lens-free and mobile-phone microscopy techniques, their combination through the DCFM framework could be useful for digital pathology and telepathology applications, in low-resource and point-of-care settings.

  7. Automated Micro-Object Detection for Mobile Diagnostics Using Lens-Free Imaging Technology

    Directory of Open Access Journals (Sweden)

    Mohendra Roy

    2016-05-01

    Full Text Available Lens-free imaging technology has been extensively used recently for microparticle and biological cell analysis because of its high throughput, low cost, and simple and compact arrangement. However, this technology still lacks a dedicated and automated detection system. In this paper, we describe a custom-developed automated micro-object detection method for a lens-free imaging system. In our previous work (Roy et al., we developed a lens-free imaging system using low-cost components. This system was used to generate and capture the diffraction patterns of micro-objects and a global threshold was used to locate the diffraction patterns. In this work we used the same setup to develop an improved automated detection and analysis algorithm based on adaptive threshold and clustering of signals. For this purpose images from the lens-free system were then used to understand the features and characteristics of the diffraction patterns of several types of samples. On the basis of this information, we custom-developed an automated algorithm for the lens-free imaging system. Next, all the lens-free images were processed using this custom-developed automated algorithm. The performance of this approach was evaluated by comparing the counting results with standard optical microscope results. We evaluated the counting results for polystyrene microbeads, red blood cells, and HepG2, HeLa, and MCF7 cells. The comparison shows good agreement between the systems, with a correlation coefficient of 0.91 and linearity slope of 0.877. We also evaluated the automated size profiles of the microparticle samples. This Wi-Fi-enabled lens-free imaging system, along with the dedicated software, possesses great potential for telemedicine applications in resource-limited settings.

  8. Optimized computational imaging methods for small-target sensing in lens-free holographic microscopy

    Science.gov (United States)

    Xiong, Zhen; Engle, Isaiah; Garan, Jacob; Melzer, Jeffrey E.; McLeod, Euan

    2018-02-01

    Lens-free holographic microscopy is a promising diagnostic approach because it is cost-effective, compact, and suitable for point-of-care applications, while providing high resolution together with an ultra-large field-of-view. It has been applied to biomedical sensing, where larger targets like eukaryotic cells, bacteria, or viruses can be directly imaged without labels, and smaller targets like proteins or DNA strands can be detected via scattering labels like micro- or nano-spheres. Automated image processing routines can count objects and infer target concentrations. In these sensing applications, sensitivity and specificity are critically affected by image resolution and signal-to-noise ratio (SNR). Pixel super-resolution approaches have been shown to boost resolution and SNR by synthesizing a high-resolution image from multiple, partially redundant, low-resolution images. However, there are several computational methods that can be used to synthesize the high-resolution image, and previously, it has been unclear which methods work best for the particular case of small-particle sensing. Here, we quantify the SNR achieved in small-particle sensing using regularized gradient-descent optimization method, where the regularization is based on cardinal-neighbor differences, Bayer-pattern noise reduction, or sparsity in the image. In particular, we find that gradient-descent with sparsity-based regularization works best for small-particle sensing. These computational approaches were evaluated on images acquired using a lens-free microscope that we assembled from an off-the-shelf LED array and color image sensor. Compared to other lens-free imaging systems, our hardware integration, calibration, and sample preparation are particularly simple. We believe our results will help to enable the best performance in lens-free holographic sensing.

  9. Giga-pixel lensfree holographic microscopy and tomography using color image sensors.

    Directory of Open Access Journals (Sweden)

    Serhan O Isikman

    Full Text Available We report Giga-pixel lensfree holographic microscopy and tomography using color sensor-arrays such as CMOS imagers that exhibit Bayer color filter patterns. Without physically removing these color filters coated on the sensor chip, we synthesize pixel super-resolved lensfree holograms, which are then reconstructed to achieve ~350 nm lateral resolution, corresponding to a numerical aperture of ~0.8, across a field-of-view of ~20.5 mm(2. This constitutes a digital image with ~0.7 Billion effective pixels in both amplitude and phase channels (i.e., ~1.4 Giga-pixels total. Furthermore, by changing the illumination angle (e.g., ± 50° and scanning a partially-coherent light source across two orthogonal axes, super-resolved images of the same specimen from different viewing angles are created, which are then digitally combined to synthesize tomographic images of the object. Using this dual-axis lensfree tomographic imager running on a color sensor-chip, we achieve a 3D spatial resolution of ~0.35 µm × 0.35 µm × ~2 µm, in x, y and z, respectively, creating an effective voxel size of ~0.03 µm(3 across a sample volume of ~5 mm(3, which is equivalent to >150 Billion voxels. We demonstrate the proof-of-concept of this lensfree optical tomographic microscopy platform on a color CMOS image sensor by creating tomograms of micro-particles as well as a wild-type C. elegans nematode.

  10. 3D imaging of optically cleared tissue using a simplified CLARITY method and on-chip microscopy

    KAUST Repository

    Zhang, Yibo

    2017-08-12

    High-throughput sectioning and optical imaging of tissue samples using traditional immunohistochemical techniques can be costly and inaccessible in resource-limited areas. We demonstrate three-dimensional (3D) imaging and phenotyping in optically transparent tissue using lens-free holographic on-chip microscopy as a low-cost, simple, and high-throughput alternative to conventional approaches. The tissue sample is passively cleared using a simplified CLARITY method and stained using 3,3′-diaminobenzidine to target cells of interest, enabling bright-field optical imaging and 3D sectioning of thick samples. The lens-free computational microscope uses pixel super-resolution and multi-height phase recovery algorithms to digitally refocus throughout the cleared tissue and obtain a 3D stack of complex-valued images of the sample, containing both phase and amplitude information. We optimized the tissue-clearing and imaging system by finding the optimal illumination wavelength, tissue thickness, sample preparation parameters, and the number of heights of the lens-free image acquisition and implemented a sparsity-based denoising algorithm to maximize the imaging volume and minimize the amount of the acquired data while also preserving the contrast-to-noise ratio of the reconstructed images. As a proof of concept, we achieved 3D imaging of neurons in a 200-μm-thick cleared mouse brain tissue over a wide field of view of 20.5 mm2. The lens-free microscope also achieved more than an order-of-magnitude reduction in raw data compared to a conventional scanning optical microscope imaging the same sample volume. Being low cost, simple, high-throughput, and data-efficient, we believe that this CLARITY-enabled computational tissue imaging technique could find numerous applications in biomedical diagnosis and research in low-resource settings.

  11. Escherichia coli counting using lens-free imaging for sepsis diagnosis

    Science.gov (United States)

    Moon, Sangjun; Manzur, Fahim; Manzur, Tariq; Klapperich, Catherine; Demirci, Utkan

    2009-09-01

    Sepsis causes 9.3% of overall deaths in United States. To diagnose sepsis, cell/bacteria capture and culturing methods have been widely investigated in the medical field. Escherichia Coli (E. Coli) is used as a model organism for sepsis in blood stream since wide variety of antibodies are established and the genetic modification process is well documented for fluorescent tagging. In point-of-care testing applications, the sepsis diagnostics require fast monitoring, inexpensive testing, and reliable results at resource limited settings, i.e. battle field, home care for dialysis. However, the cell/E.coli are hard to directly capture and see at the POCT because of the small size, 2 μm long and 0.5 μm in diameter, and the bacteria are rare in the blood stream in sepsis. Here, we propose a novel POCT platform to image and enumerate cell/E.coli on a microfluidic surface to diagnose sepsis at resource limited conditions. We demonstrate that target cells are captured from 5 μl of whole blood using specific antibodies and E.coli are imaged using a lens-free imaging platform, 2.2 μm pixel CMOS based imaging sensor. This POCT cell/bacteria capture and enumeration approach can further be used for medical diagnostics of sepsis. We also show approaches to rapidly quantify white blood cell counts from blood which can be used to monitor immune response.

  12. Lensfree Computational Microscopy Tools and their Biomedical Applications

    Science.gov (United States)

    Sencan, Ikbal

    Conventional microscopy has been a revolutionary tool for biomedical applications since its invention several centuries ago. Ability to non-destructively observe very fine details of biological objects in real time enabled to answer many important questions about their structures and functions. Unfortunately, most of these advance microscopes are complex, bulky, expensive, and/or hard to operate, so they could not reach beyond the walls of well-equipped laboratories. Recent improvements in optoelectronic components and computational methods allow creating imaging systems that better fulfill the specific needs of clinics or research related biomedical applications. In this respect, lensfree computational microscopy aims to replace bulky and expensive optical components with compact and cost-effective alternatives through the use of computation, which can be particularly useful for lab-on-a-chip platforms as well as imaging applications in low-resource settings. Several high-throughput on-chip platforms are built with this approach for applications including, but not limited to, cytometry, micro-array imaging, rare cell analysis, telemedicine, and water quality screening. The lack of optical complexity in these lensfree on-chip imaging platforms is compensated by using computational techniques. These computational methods are utilized for various purposes in coherent, incoherent and fluorescent on-chip imaging platforms e.g. improving the spatial resolution, to undo the light diffraction without using lenses, localization of objects in a large volume and retrieval of the phase or the color/spectral content of the objects. For instance, pixel super resolution approaches based on source shifting are used in lensfree imaging platforms to prevent under sampling, Bayer pattern, and aliasing artifacts. Another method, iterative phase retrieval, is utilized to compensate the lack of lenses by undoing the diffraction and removing the twin image noise of in-line holograms

  13. Color calibration and fusion of lens-free and mobile-phone microscopy images for high-resolution and accurate color reproduction

    Science.gov (United States)

    Zhang, Yibo; Wu, Yichen; Zhang, Yun; Ozcan, Aydogan

    2016-06-01

    Lens-free holographic microscopy can achieve wide-field imaging in a cost-effective and field-portable setup, making it a promising technique for point-of-care and telepathology applications. However, due to relatively narrow-band sources used in holographic microscopy, conventional colorization methods that use images reconstructed at discrete wavelengths, corresponding to e.g., red (R), green (G) and blue (B) channels, are subject to color artifacts. Furthermore, these existing RGB colorization methods do not match the chromatic perception of human vision. Here we present a high-color-fidelity and high-resolution imaging method, termed “digital color fusion microscopy” (DCFM), which fuses a holographic image acquired at a single wavelength with a color-calibrated image taken by a low-magnification lens-based microscope using a wavelet transform-based colorization method. We demonstrate accurate color reproduction of DCFM by imaging stained tissue sections. In particular we show that a lens-free holographic microscope in combination with a cost-effective mobile-phone-based microscope can generate color images of specimens, performing very close to a high numerical-aperture (NA) benchtop microscope that is corrected for color distortions and chromatic aberrations, also matching the chromatic response of human vision. This method can be useful for wide-field imaging needs in telepathology applications and in resource-limited settings, where whole-slide scanning microscopy systems are not available.

  14. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  15. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  16. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-09-18

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  17. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Directory of Open Access Journals (Sweden)

    Cally Gill

    2013-09-01

    Full Text Available The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  18. On-chip immobilization of planarians for in vivo imaging.

    Science.gov (United States)

    Dexter, Joseph P; Tamme, Mary B; Lind, Christine H; Collins, Eva-Maria S

    2014-09-17

    Planarians are an important model organism for regeneration and stem cell research. A complete understanding of stem cell and regeneration dynamics in these animals requires time-lapse imaging in vivo, which has been difficult to achieve due to a lack of tissue-specific markers and the strong negative phototaxis of planarians. We have developed the Planarian Immobilization Chip (PIC) for rapid, stable immobilization of planarians for in vivo imaging without injury or biochemical alteration. The chip is easy and inexpensive to fabricate, and worms can be mounted for and removed after imaging within minutes. We show that the PIC enables significantly higher-stability immobilization than can be achieved with standard techniques, allowing for imaging of planarians at sub-cellular resolution in vivo using brightfield and fluorescence microscopy. We validate the performance of the PIC by performing time-lapse imaging of planarian wound closure and sequential imaging over days of head regeneration. We further show that the device can be used to immobilize Hydra, another photophobic regenerative model organism. The simple fabrication, low cost, ease of use, and enhanced specimen stability of the PIC should enable its broad application to in vivo studies of stem cell and regeneration dynamics in planarians and Hydra.

  19. Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light

    Science.gov (United States)

    Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltan; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

    2017-03-01

    Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

  20. Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light

    KAUST Repository

    Daloglu, Mustafa Ugur

    2017-03-09

    Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

  1. High resolution computational on-chip imaging of biological samples using sparsity constraint (Conference Presentation)

    Science.gov (United States)

    Rivenson, Yair; Wu, Chris; Wang, Hongda; Zhang, Yibo; Ozcan, Aydogan

    2017-03-01

    Microscopic imaging of biological samples such as pathology slides is one of the standard diagnostic methods for screening various diseases, including cancer. These biological samples are usually imaged using traditional optical microscopy tools; however, the high cost, bulkiness and limited imaging throughput of traditional microscopes partially restrict their deployment in resource-limited settings. In order to mitigate this, we previously demonstrated a cost-effective and compact lens-less on-chip microscopy platform with a wide field-of-view of >20-30 mm^2. The lens-less microscopy platform has shown its effectiveness for imaging of highly connected biological samples, such as pathology slides of various tissue samples and smears, among others. This computational holographic microscope requires a set of super-resolved holograms acquired at multiple sample-to-sensor distances, which are used as input to an iterative phase recovery algorithm and holographic reconstruction process, yielding high-resolution images of the samples in phase and amplitude channels. Here we demonstrate that in order to reconstruct clinically relevant images with high resolution and image contrast, we require less than 50% of the previously reported nominal number of holograms acquired at different sample-to-sensor distances. This is achieved by incorporating a loose sparsity constraint as part of the iterative holographic object reconstruction. We demonstrate the success of this sparsity-based computational lens-less microscopy platform by imaging pathology slides of breast cancer tissue and Papanicolaou (Pap) smears.

  2. On-chip imaging of Schistosoma haematobium eggs in urine for diagnosis by computer vision.

    Directory of Open Access Journals (Sweden)

    Ewert Linder

    Full Text Available BACKGROUND: Microscopy, being relatively easy to perform at low cost, is the universal diagnostic method for detection of most globally important parasitic infections. As quality control is hard to maintain, misdiagnosis is common, which affects both estimates of parasite burdens and patient care. Novel techniques for high-resolution imaging and image transfer over data networks may offer solutions to these problems through provision of education, quality assurance and diagnostics. Imaging can be done directly on image sensor chips, a technique possible to exploit commercially for the development of inexpensive "mini-microscopes". Images can be transferred for analysis both visually and by computer vision both at point-of-care and at remote locations. METHODS/PRINCIPAL FINDINGS: Here we describe imaging of helminth eggs using mini-microscopes constructed from webcams and mobile phone cameras. The results show that an inexpensive webcam, stripped off its optics to allow direct application of the test sample on the exposed surface of the sensor, yields images of Schistosoma haematobium eggs, which can be identified visually. Using a highly specific image pattern recognition algorithm, 4 out of 5 eggs observed visually could be identified. CONCLUSIONS/SIGNIFICANCE: As proof of concept we show that an inexpensive imaging device, such as a webcam, may be easily modified into a microscope, for the detection of helminth eggs based on on-chip imaging. Furthermore, algorithms for helminth egg detection by machine vision can be generated for automated diagnostics. The results can be exploited for constructing simple imaging devices for low-cost diagnostics of urogenital schistosomiasis and other neglected tropical infectious diseases.

  3. On chip cryo-anesthesia of Drosophila larvae for high resolution in vivo imaging applications.

    Science.gov (United States)

    Chaudhury, Amrita Ray; Insolera, Ryan; Hwang, Ran-Der; Fridell, Yih-Woei; Collins, Catherine; Chronis, Nikos

    2017-06-27

    We present a microfluidic chip for immobilizing Drosophila melanogaster larvae for high resolution in vivo imaging. The chip creates a low-temperature micro-environment that anaesthetizes and immobilizes the larva in under 3 minutes. We characterized the temperature distribution within the chip and analyzed the resulting larval body movement using high resolution fluorescence imaging. Our results indicate that the proposed method minimizes submicron movements of internal organs and tissue without affecting the larva physiology. It can be used to continuously immobilize larvae for short periods of time (minutes) or for longer periods (several hours) if used intermittently. The same chip can be used to accommodate and immobilize arvae across all developmental stages (1st instar to late 3rd instar), and loading larvae onto the chip does not require any specialized skills. To demonstrate the usability of the chip, we observed mitochondrial trafficking in neurons from the cell bodies to the axon terminals along with mitochondrial fusion and neuro-synaptic growth through time in intact larvae. Besides studying sub-cellular processes and cellular development, we envision the use of on chip cryo-anesthesia in a wide variety of biological in vivo imaging applications, including observing organ development of the salivary glands, fat bodies and body-wall muscles.

  4. Non-destructive on-chip cell sorting system with real-time microscopic image processing

    Directory of Open Access Journals (Sweden)

    Ichiki Takanori

    2004-06-01

    Full Text Available Abstract Studying cell functions for cellomics studies often requires the use of purified individual cells from mixtures of various kinds of cells. We have developed a new non-destructive on-chip cell sorting system for single cell based cultivation, by exploiting the advantage of microfluidics and electrostatic force. The system consists of the following two parts: a cell sorting chip made of poly-dimethylsiloxane (PDMS on a 0.2-mm-thick glass slide, and an image analysis system with a phase-contrast/fluorescence microscope. The unique features of our system include (i identification of a target from sample cells is achieved by comparison of the 0.2-μm-resolution phase-contrast and fluorescence images of cells in the microchannel every 1/30 s; (ii non-destructive sorting of target cells in a laminar flow by application of electrostatic repulsion force for removing unrequited cells from the one laminar flow to the other; (iii the use of agar gel for electrodes in order to minimize the effect on cells by electrochemical reactions of electrodes, and (iv pre-filter, which was fabricated within the channel for removal of dust contained in a sample solution from tissue extracts. The sorting chip is capable of continuous operation and we have purified more than ten thousand cells for cultivation without damaging them. Our design has proved to be very efficient and suitable for the routine use in cell purification experiments.

  5. Laser Doppler blood flow complementary metal oxide semiconductor imaging sensor with analog on-chip processing

    International Nuclear Information System (INIS)

    Gu Quan; Hayes-Gill, Barrie R.; Morgan, Stephen P.

    2008-01-01

    A 4x4 pixel array with analog on-chip processing has been fabricated within a 0.35 μm complementary metal oxide semiconductor process as a prototype sensor for laser Doppler blood flow imaging. At each pixel the bandpass and frequency weighted filters necessary for processing laser Doppler blood flow signals have been designed and fabricated. Because of the space constraints of implementing an accurate ω 0.5 filter at the pixel level, this has been approximated using the ''roll off'' of a high-pass filter with a cutoff frequency set at 10 kHz. The sensor has been characterized using a modulated laser source. Fixed pattern noise is present that is demonstrated to be repeatable across the array and can be calibrated. Preliminary blood flow results on a finger before and after occlusion demonstrate that the sensor array provides the potential for a system that can be scaled to a larger number of pixels for blood flow imaging

  6. An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

    Directory of Open Access Journals (Sweden)

    Ismail Cevik

    2015-03-01

    Full Text Available An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT-based power management system (PMS is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  7. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-03-06

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  8. Maximization of imaging resolution in optical wireless sensor/lab-on-chip/SoC networks with solar cells.

    Science.gov (United States)

    Arnon, Shlomi

    2010-09-01

    The availability of sophisticated and low-cost hardware on a single chip, for example, CMOS cameras, CPU, DSP, processors and communication transceivers, optics, microfluidics, and micromechanics, has fostered the development of system-on-chip (SoC) technology, such as lab-on-chip or wireless multimedia sensor networks (WMSNs). WMSNs are networks of wirelessly interconnected devices on a chip that are able to ubiquitously retrieve multimedia content such as video from the environment and transfer it to a central location for additional processing. In this paper, we study WMSNs that include an optical wireless communication transceiver that uses light to transmit the information. One of the primary challenges in SoC design is to attain adequate resources like energy harvesting using solar cells in addition to imaging and communication capabilities, all within stringent spatial limitations while maximizing system performances. There is an inevitable trade-off between enhancing the imaging resolution and the expense of reducing communication capacity and energy harvesting capabilities, on one hand, and increasing the communication or the solar cell size to the detriment of the imaging resolution, on the other hand. We study these trade-offs, derive a mathematical model to maximize the resolution of the imaging system, and present a numerical example that demonstrates maximum imaging resolution. Our results indicate that an eighth-order polynomial with only two constants provides the required area allocation between the different functionalities.

  9. Pixel-super-resolved lensfree holography using adaptive relaxation factor and positional error correction

    Science.gov (United States)

    Zhang, Jialin; Chen, Qian; Sun, Jiasong; Li, Jiaji; Zuo, Chao

    2018-01-01

    Lensfree holography provides a new way to effectively bypass the intrinsical trade-off between the spatial resolution and field-of-view (FOV) of conventional lens-based microscopes. Unfortunately, due to the limited sensor pixel-size, unpredictable disturbance during image acquisition, and sub-optimum solution to the phase retrieval problem, typical lensfree microscopes only produce compromised imaging quality in terms of lateral resolution and signal-to-noise ratio (SNR). In this paper, we propose an adaptive pixel-super-resolved lensfree imaging (APLI) method to address the pixel aliasing problem by Z-scanning only, without resorting to subpixel shifting or beam-angle manipulation. Furthermore, an automatic positional error correction algorithm and adaptive relaxation strategy are introduced to enhance the robustness and SNR of reconstruction significantly. Based on APLI, we perform full-FOV reconstruction of a USAF resolution target across a wide imaging area of {29.85 mm2 and achieve half-pitch lateral resolution of 770 nm, surpassing 2.17 times of the theoretical Nyquist-Shannon sampling resolution limit imposed by the sensor pixel-size (1.67 μm). Full-FOV imaging result of a typical dicot root is also provided to demonstrate its promising potential applications in biologic imaging.

  10. Applications of holographic on-chip microscopy (Conference Presentation)

    Science.gov (United States)

    Ozcan, Aydogan

    2017-02-01

    My research focuses on the use of computation/algorithms to create new optical microscopy, sensing, and diagnostic techniques, significantly improving existing tools for probing micro- and nano-objects while also simplifying the designs of these analysis tools. In this presentation, I will introduce a set of computational microscopes which use lens-free on-chip imaging to replace traditional lenses with holographic reconstruction algorithms. Basically, 3D images of specimens are reconstructed from their "shadows" providing considerably improved field-of-view (FOV) and depth-of-field, thus enabling large sample volumes to be rapidly imaged, even at nanoscale. These new computational microscopes routinely generate benefit of this technology is that it lends itself to field-portable and cost-effective designs which easily integrate with smartphones to conduct giga-pixel tele-pathology and microscopy even in resource-poor and remote settings where traditional techniques are difficult to implement and sustain, thus opening the door to various telemedicine applications in global health. Through the development of similar computational imagers, I will also report the discovery of new 3D swimming patterns observed in human and animal sperm. One of this newly discovered and extremely rare motion is in the form of "chiral ribbons" where the planar swings of the sperm head occur on an osculating plane creating in some cases a helical ribbon and in some others a twisted ribbon. Shedding light onto the statistics and biophysics of various micro-swimmers' 3D motion, these results provide an important example of how biomedical imaging significantly benefits from emerging computational algorithms/theories, revolutionizing existing tools for observing various micro- and nano-scale phenomena in innovative, high-throughput, and yet cost-effective ways.

  11. Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

    Science.gov (United States)

    Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

    2011-11-01

    Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

  12. A System-on-Chip Solution for Point-of-Care Ultrasound Imaging Systems: Architecture and ASIC Implementation.

    Science.gov (United States)

    Kang, Jeeun; Yoon, Changhan; Lee, Jaejin; Kye, Sang-Bum; Lee, Yongbae; Chang, Jin Ho; Kim, Gi-Duck; Yoo, Yangmo; Song, Tai-kyong

    2016-04-01

    In this paper, we present a novel system-on-chip (SOC) solution for a portable ultrasound imaging system (PUS) for point-of-care applications. The PUS-SOC includes all of the signal processing modules (i.e., the transmit and dynamic receive beamformer modules, mid- and back-end processors, and color Doppler processors) as well as an efficient architecture for hardware-based imaging methods (e.g., dynamic delay calculation, multi-beamforming, and coded excitation and compression). The PUS-SOC was fabricated using a UMC 130-nm NAND process and has 16.8 GFLOPS of computing power with a total equivalent gate count of 12.1 million, which is comparable to a Pentium-4 CPU. The size and power consumption of the PUS-SOC are 27×27 mm(2) and 1.2 W, respectively. Based on the PUS-SOC, a prototype hand-held US imaging system was implemented. Phantom experiments demonstrated that the PUS-SOC can provide appropriate image quality for point-of-care applications with a compact PDA size ( 200×120×45 mm(3)) and 3 hours of battery life.

  13. On-Chip hyperspetral imaging system for portable IR spectroscopy applications, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Hyperspectral middlewave infrared and longwave infrared (MWIR/LWIR) imaging systems capable of obtaining hundreds of narrow band (10-15 nm) spectral information of...

  14. Imaging through scattering microfluidic channels by digital holography for information recovery in lab on chip.

    Science.gov (United States)

    Bianco, V; Paturzo, M; Gennari, O; Finizio, A; Ferraro, P

    2013-10-07

    We tackle the problem of information recovery and imaging through scattering microfluidic chips by means of digital holography (DH). In many cases the chip can become opalescent due to residual deposits settling down the inner channel faces, biofilm formation, scattering particle uptake by the channel cladding or its damaging by corrosive substances, or even by condensing effect on the exterior channels walls. In these cases white-light imaging is severely degraded and no information is obtainable at all about the flowing samples. Here we investigate the problem of counting and estimating velocity of cells flowing inside a scattering chip. Moreover we propose and test a method based on the recording of multiple digital holograms to retrieve improved phase-contrast images despite the strong scattering effect. This method helps, thanks to DH, to recover information which, otherwise, would be completely lost.

  15. Indium antimonide infrared CCD linear imaging arrays with on-chip preprocessing

    Science.gov (United States)

    Thom, R. D.; Koch, T. L.; Parrish, W. J.

    1978-01-01

    A description is presented of the fabrication of a new InSb CCD chip based on an improved process which eliminates the limitations inherent with the earlier techniques. This process includes planar junction formation and an aluminum and SiO2 material system which is amenable to state-of-the-art chemical and plasma delineation techniques. Further, the new chip integrates for the first time in monolithic format InSb IR detectors with an InSb CCD. The reported experiments represent the first operation of an InSb infrared CCD array. In addition to fuller characterization of the 20-element charge-coupled infrared imaging device, several factors which influence device performance are currently being addressed. These include surface state density, the CCD output circuit, and storage time (dark current).

  16. Sparsity-Based Pixel Super Resolution for Lens-Free Digital In-line Holography.

    Science.gov (United States)

    Song, Jun; Leon Swisher, Christine; Im, Hyungsoon; Jeong, Sangmoo; Pathania, Divya; Iwamoto, Yoshiko; Pivovarov, Misha; Weissleder, Ralph; Lee, Hakho

    2016-04-21

    Lens-free digital in-line holography (LDIH) is a promising technology for portable, wide field-of-view imaging. Its resolution, however, is limited by the inherent pixel size of an imaging device. Here we present a new computational approach to achieve sub-pixel resolution for LDIH. The developed method is a sparsity-based reconstruction with the capability to handle the non-linear nature of LDIH. We systematically characterized the algorithm through simulation and LDIH imaging studies. The method achieved the spatial resolution down to one-third of the pixel size, while requiring only single-frame imaging without any hardware modifications. This new approach can be used as a general framework to enhance the resolution in nonlinear holographic systems.

  17. Dynamics of cell and tissue growth acquired by means of extended field of view lensfree microscopy.

    Science.gov (United States)

    Momey, F; Coutard, J-G; Bordy, T; Navarro, F; Menneteau, M; Dinten, J-M; Allier, C

    2016-02-01

    In this paper, we discuss a new methodology based on lensfree imaging to perform wound healing assay with unprecedented statistics. Our video lensfree microscopy setup is a simple device featuring only a CMOS sensor and a semi coherent illumination system. Yet it is a powerful mean for the real-time monitoring of cultivated cells. It presents several key advantages, e.g. integration into standard incubator, compatibility with standard cell culture protocol, simplicity and ease of use. It can perform the follow-up in a large field of view (25 mm(2)) of several crucial parameters during the culture of cells i.e. their motility, their proliferation rate or their death. Consequently the setup can gather large statistics both in space and time. Here we uses this facility in the context of wound healing assay to perform label-free measurements of the velocities of the fronts of proliferation of the cell layer as a function of time by means of particle image velocimetry (PIV) processing. However, for such tissue growth experiments, the field of view of 25 mm(2) remains not sufficient and results can be biased depending on the position of the device with respect to the recipient of the cell culture. Hence, to conduct exhaustive wound healing assays, we propose to enlarge the field of view up to 10 cm(2) through a raster scan, by moving the source/sensor with respect to the Petri dish. We have performed acquisitions of wound healing assay (keratinocytes HaCaT) both in real-time (25 mm(2)) and in final point (10 cm(2)) to assess the combination of velocimetry measurements and final point wide field imaging. In the future, we aim at combining directly our extended field of view acquisitions (>10 cm(2)) with real time ability inside the incubator.

  18. Fully Automated On-Chip Imaging Flow Cytometry System with Disposable Contamination-Free Plastic Re-Cultivation Chip

    Directory of Open Access Journals (Sweden)

    Tomoyuki Kaneko

    2011-06-01

    Full Text Available We have developed a novel imaging cytometry system using a poly(methyl methacrylate (PMMA based microfluidic chip. The system was contamination-free, because sample suspensions contacted only with a flammable PMMA chip and no other component of the system. The transparency and low-fluorescence of PMMA was suitable for microscopic imaging of cells flowing through microchannels on the chip. Sample particles flowing through microchannels on the chip were discriminated by an image-recognition unit with a high-speed camera in real time at the rate of 200 event/s, e.g., microparticles 2.5 μm and 3.0 μm in diameter were differentiated with an error rate of less than 2%. Desired cells were separated automatically from other cells by electrophoretic or dielectrophoretic force one by one with a separation efficiency of 90%. Cells in suspension with fluorescent dye were separated using the same kind of microfluidic chip. Sample of 5 μL with 1 × 106 particle/mL was processed within 40 min. Separated cells could be cultured on the microfluidic chip without contamination. The whole operation of sample handling was automated using 3D micropipetting system. These results showed that the novel imaging flow cytometry system is practically applicable for biological research and clinical diagnostics.

  19. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2016-01-01

    On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range.......On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range....

  20. Yeast viability and concentration analysis using lens-free computational microscopy and machine learning

    Science.gov (United States)

    Feizi, Alborz; Zhang, Yibo; Greenbaum, Alon; Guziak, Alex; Luong, Michelle; Chan, Raymond Yan Lok; Berg, Brandon; Ozkan, Haydar; Luo, Wei; Wu, Michael; Wu, Yichen; Ozcan, Aydogan

    2017-03-01

    Research laboratories and the industry rely on yeast viability and concentration measurements to adjust fermentation parameters such as pH, temperature, and pressure. Beer-brewing processes as well as biofuel production can especially utilize a cost-effective and portable way of obtaining data on cell viability and concentration. However, current methods of analysis are relatively costly and tedious. Here, we demonstrate a rapid, portable, and cost-effective platform for imaging and measuring viability and concentration of yeast cells. Our platform features a lens-free microscope that weighs 70 g and has dimensions of 12 × 4 × 4 cm. A partially-coherent illumination source (a light-emitting-diode), a band-pass optical filter, and a multimode optical fiber are used to illuminate the sample. The yeast sample is directly placed on a complementary metal-oxide semiconductor (CMOS) image sensor chip, which captures an in-line hologram of the sample over a large field-of-view of >20 mm2. The hologram is transferred to a touch-screen interface, where a trained Support Vector Machine model classifies yeast cells stained with methylene blue as live or dead and measures cell viability as well as concentration. We tested the accuracy of our platform against manual counting of live and dead cells using fluorescent exclusion staining and a bench-top fluorescence microscope. Our regression analysis showed no significant difference between the two methods within a concentration range of 1.4 × 105 to 1.4 × 106 cells/mL. This compact and cost-effective yeast analysis platform will enable automatic quantification of yeast viability and concentration in field settings and resource-limited environments.

  1. Reconfigurable Networks-on-Chip

    CERN Document Server

    Chen, Sao-Jie; Tsai, Wen-Chung; Hu, Yu-Hen

    2012-01-01

    This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.   Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.     From the Foreword: Overall this book shows important advances over the...

  2. On-chip data communication

    NARCIS (Netherlands)

    Schinkel, Daniel

    2011-01-01

    On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and

  3. On-chip optical processing

    Science.gov (United States)

    Motamedi, M. Edward; Wu, Ming C.; Pister, Kristofer S. J.

    1996-09-01

    Microoptical components, such as diffractive and refractive microlenses, micromirrors, beam splitter and beam combining have recently received considerable attention in the optics R&D centers and finally in the manufacturing community. This achievement is due to MEM technology that demonstrated major improvements in overall performance/cost of optical systems while offering the possibility of relatively rapid transition to products for military, industrial and consumer markets. Because of these technology advances, an industrial infrastructure is rapidly becoming established to provide combining microoptical components and MEM-based microactuators for on-chip optical processing. Optical systems that once were considered to be impractical due to the limitations of bulk optics can now easily be designed and fabricated with all required optical paths, signal conditioning, and electronic controls, integrated on a single chip. On-chip optical processing will enhance the performance of devices such as focal plane optical concentrator, smart actuators, color separation, beam shaping, FDDI switch, digital micromirror devices (DMDs), and miniature optical scanners. In this paper we review advances in microoptical components developed at Rockwell Science Center. We also review the potential of on-chip optical processing and recent achievement of free-space integrated optics and microoptical bench components developed at UCLA, and DMDs developed at Texas Instruments.

  4. New Lens-Free X-ray Source for Laboratory Nano-CT with 50-nm Spatial Resolution

    Science.gov (United States)

    Sasov, A.; Pauwels, B.; Bruyndonckx, P.; Liu, X.

    2011-09-01

    X-ray optics, such as zone plates, are often used to obtain a spatial resolution better than 100 nm in x-ray projection images. Such types of optics are not always suited for tomographic imaging due to their limited depth of focus, which restricts the size of the specimen to a few microns. To overcome these limitations, we developed a new lens-free setup for a nano-CT system. Spatial resolution of nano-CT systems is mainly defined by x-ray source performance. It is dependent on target shape and focusing of the electron beam. The typical way to improve spatial resolution is based on replacement of the bulk metal target to thin film. It allows getting submicron spot size, but significantly reduces x-ray flux. To overcome flux limitation without compromising with spatial resolution, we invented a new type of target shaped as a rod or needle towards the camera. It allows us to reach 50-nm resolution with reasonable flux.

  5. On-Chip Detection of Cellular Activity

    Science.gov (United States)

    Almog, R.; Daniel, R.; Vernick, S.; Ron, A.; Ben-Yoav, H.; Shacham-Diamand, Y.

    The use of on-chip cellular activity monitoring for biological/chemical sensing is promising for environmental, medical and pharmaceutical applications. The miniaturization revolution in microelectronics is harnessed to provide on-chip detection of cellular activity, opening new horizons for miniature, fast, low cost and portable screening and monitoring devices. In this chapter we survey different on-chip cellular activity detection technologies based on electrochemical, bio-impedance and optical detection. Both prokaryotic and eukaryotic cell-on-chip technologies are mentioned and reviewed.

  6. Towards Dependable Network-on-Chip Architectures

    NARCIS (Netherlands)

    Chen, C.

    2015-01-01

    The aggressive semiconductor technology scaling provides the means for doubling the amount of transistors on a single chip each and every 18 months. To efficiently utilize these vast chip resources, Multi-Processor Systems on Chip (MPSoCs) integrated with a Network-on-Chip (NoC) communication

  7. Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method.

    Science.gov (United States)

    Chao, Calvin Yi-Ping; Tu, Honyih; Wu, Thomas Meng-Hsiu; Chou, Kuo-Yu; Yeh, Shang-Fu; Yin, Chin; Lee, Chih-Lin

    2017-11-23

    A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model.

  8. Micro-electro-fluidic grids for nematodes: a lens-less, image-sensor-less approach for on-chip tracking of nematode locomotion.

    Science.gov (United States)

    Liu, Peng; Martin, Richard J; Dong, Liang

    2013-02-21

    This paper reports on the development of a lens-less and image-sensor-less micro-electro-fluidic (MEF) approach for real-time monitoring of the locomotion of microscopic nematodes. The technology showed promise for overcoming the constraint of the limited field of view of conventional optical microscopy, with relatively low cost, good spatial resolution, and high portability. The core of the device was microelectrode grids formed by orthogonally arranging two identical arrays of microelectrode lines. The two microelectrode arrays were spaced by a microfluidic chamber containing a liquid medium of interest. As a nematode (e.g., Caenorhabditis elegans) moved inside the chamber, the invasion of part of its body into some intersection regions between the microelectrodes caused changes in the electrical resistance of these intersection regions. The worm's presence at, or absence from, a detection unit was determined by a comparison between the measured resistance variation of this unit and a pre-defined threshold resistance variation. An electronic readout circuit was designed to address all the detection units and read out their individual electrical resistances. By this means, it was possible to obtain the electrical resistance profile of the whole MEF grid, and thus, the physical pattern of the swimming nematode. We studied the influence of a worm's body on the resistance of an addressed unit. We also investigated how the full-frame scanning and readout rates of the electronic circuit and the dimensions of a detection unit posed an impact on the spatial resolution of the reconstructed images of the nematode. Other important issues, such as the manufacturing-induced initial non-uniformity of the grids and the electrotaxic behaviour of nematodes, were also studied. A drug resistance screening experiment was conducted by using the grids with a good resolution of 30 × 30 μm(2). The phenotypic differences in the locomotion behaviours (e.g., moving speed and oscillation

  9. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  10. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  11. SVM classifier on chip for melanoma detection.

    Science.gov (United States)

    Afifi, Shereen; GholamHosseini, Hamid; Sinha, Roopak

    2017-07-01

    Support Vector Machine (SVM) is a common classifier used for efficient classification with high accuracy. SVM shows high accuracy for classifying melanoma (skin cancer) clinical images within computer-aided diagnosis systems used by skin cancer specialists to detect melanoma early and save lives. We aim to develop a medical low-cost handheld device that runs a real-time embedded SVM-based diagnosis system for use in primary care for early detection of melanoma. In this paper, an optimized SVM classifier is implemented onto a recent FPGA platform using the latest design methodology to be embedded into the proposed device for realizing online efficient melanoma detection on a single system on chip/device. The hardware implementation results demonstrate a high classification accuracy of 97.9% and a significant acceleration factor of 26 from equivalent software implementation on an embedded processor, with 34% of resources utilization and 2 watts for power consumption. Consequently, the implemented system meets crucial embedded systems constraints of high performance and low cost, resources utilization and power consumption, while achieving high classification accuracy.

  12. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  13. On-chip mode division multiplexing technologies

    DEFF Research Database (Denmark)

    Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

    2016-01-01

    Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... using one-dimensional (1D) photonic crystal silicon waveguides. We furthermore use the fabricated devices to demonstrate on-chip point-to-point mode division multiplexing transmission, and all-optical signal processing by mode-selective wavelength conversion. Finally, we report an efficient silicon...

  14. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous......, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written...

  15. Communication architectures for systems-on-chip

    CERN Document Server

    Ayala, Jose L

    2011-01-01

    A presentation of state-of-the-art approaches from an industrial applications perspective, Communication Architectures for Systems-on-Chip shows professionals, researchers, and students how to attack the problem of data communication in the manufacture of SoC architectures. With its lucid illustration of current trends and research improving the performance, quality, and reliability of transactions, this is an essential reference for anyone dealing with communication mechanisms for embedded systems, systems-on-chip, and multiprocessor architectures--or trying to overcome existing limitations.

  16. Chromosome Conformation Capture on Chip (4C)

    DEFF Research Database (Denmark)

    Leblanc, Benjamin Olivier; Comet, Itys; Bantignies, Frédéric

    2016-01-01

    4C methods are useful to investigate dependencies between regulatory mechanisms and chromatin structures by revealing the frequency of chromatin contacts between a locus of interest and remote sequences on the chromosome. In this chapter we describe a protocol for the data analysis of microarray-...... to analyze ChIP-on-chip data on broadly distributed chromatin components such as histone marks....

  17. System-on-Chip Design and Implementation

    Science.gov (United States)

    Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.

    2010-01-01

    The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant…

  18. On-chip cell analysis platform: Implementation of contact fluorescence microscopy in microfluidic chips

    Science.gov (United States)

    Takehara, Hiroaki; Kazutaka, Osawa; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    2017-09-01

    Although fluorescence microscopy is the gold standard tool for biomedical research and clinical applications, their use beyond well-established laboratory infrastructures remains limited. The present study investigated a novel on-chip cell analysis platform based on contact fluorescence microscopy and microfluidics. Combined use of a contact fluorescence imager based on complementary metal-oxide semiconductor technology and an ultra-thin glass bottom microfluidic chip enabled both to observe living cells with minimal image distortion and to ease controlling and handling of biological samples (e.g. cells and biological molecules) in the imaged area. A proof-of-concept experiment of on-chip detection of cellular response to endothelial growth factor demonstrated promising use for the recently developed on-chip cell analysis platform. Contact fluorescence microscopy has numerous desirable features including compatibility with plastic microfluidic chips and compatibility with the electrical control system, and thus will fulfill the requirements of a fully automated cell analysis system.

  19. Microengineered physiological biomimicry: organs-on-chips.

    Science.gov (United States)

    Huh, Dongeun; Torisawa, Yu-suke; Hamilton, Geraldine A; Kim, Hyun Jung; Ingber, Donald E

    2012-06-21

    Microscale engineering technologies provide unprecedented opportunities to create cell culture microenvironments that go beyond current three-dimensional in vitro models by recapitulating the critical tissue-tissue interfaces, spatiotemporal chemical gradients, and dynamic mechanical microenvironments of living organs. Here we review recent advances in this field made over the past two years that are focused on the development of 'Organs-on-Chips' in which living cells are cultured within microfluidic devices that have been microengineered to reconstitute tissue arrangements observed in living organs in order to study physiology in an organ-specific context and to develop specialized in vitro disease models. We discuss the potential of organs-on-chips as alternatives to conventional cell culture models and animal testing for pharmaceutical and toxicology applications. We also explore challenges that lie ahead if this field is to fulfil its promise to transform the future of drug development and chemical safety testing.

  20. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  1. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  2. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  3. Various On-Chip Sensors with Microfluidics for Biological Applications

    Directory of Open Access Journals (Sweden)

    Hun Lee

    2014-09-01

    Full Text Available In this paper, we review recent advances in on-chip sensors integrated with microfluidics for biological applications. Since the 1990s, much research has concentrated on developing a sensing system using optical phenomena such as surface plasmon resonance (SPR and surface-enhanced Raman scattering (SERS to improve the sensitivity of the device. The sensing performance can be significantly enhanced with the use of microfluidic chips to provide effective liquid manipulation and greater flexibility. We describe an optical image sensor with a simpler platform for better performance over a larger field of view (FOV and greater depth of field (DOF. As a new trend, we review consumer electronics such as smart phones, tablets, Google glasses, etc. which are being incorporated in point-of-care (POC testing systems. In addition, we discuss in detail the current optical sensing system integrated with a microfluidic chip.

  4. On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

    Directory of Open Access Journals (Sweden)

    Jian Lu

    2008-01-01

    Full Text Available A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC. We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

  5. Architecture, On-Chip Network and Programming Interface Concept for Multiprocessor System-on-Chip

    OpenAIRE

    Samman, Faizal Arya

    2017-01-01

    in Proc. of the International Conference onSmart Green Technology in Electrical and Information Systems (ICSGTEIS), 2016, publised in IEEE Explorer (indexed by SCOPUS) This paper presents a system architecture, data communnication scheme and application programming interface model or concept for a multiprocessor system based on a network-on-chip (NoC) platform. Each processing node connected to a mesh node has its own local (instruction and data) memory portion, and a global (shared) memor...

  6. Interconnects and On-Chip Data Communication Techniques

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria

    Global on-chip communication is rapidly becoming a speed and power bottleneck in CMOS circuits. In this paper, a ‘mixed-signal’ approach is taken to analyze on-chip interconnects and it is investigated how data-rates can be improved. It is shown that complex signaling schemes such as OFDM and CDMA

  7. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  8. An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable System-on-Chip

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria

    This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial

  9. An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria

    This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial

  10. Biosensors-on-chip: a topical review

    Science.gov (United States)

    Chen, Sensen; Shamsi, Mohtashim H.

    2017-08-01

    This review will examine the integration of two fields that are currently at the forefront of science, i.e. biosensors and microfluidics. As a lab-on-a-chip (LOC) technology, microfluidics has been enriched by the integration of various detection tools for analyte detection and quantitation. The application of such microfluidic platforms is greatly increased in the area of biosensors geared towards point-of-care diagnostics. Together, the merger of microfluidics and biosensors has generated miniaturized devices for sample processing and sensitive detection with quantitation. We believe that microfluidic biosensors (biosensors-on-chip) are essential for developing robust and cost effective point-of-care diagnostics. This review is relevant to a variety of disciplines, such as medical science, clinical diagnostics, LOC technologies including MEMs/NEMs, and analytical science. Specifically, this review will appeal to scientists working in the two overlapping fields of biosensors and microfluidics, and will also help new scientists to find their directions in developing point-of-care devices.

  11. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...... facilitating IP reuse by standard socket access points. Two types of services are available: connection-less best-effort routing and connection-oriented guaranteed service (GS) routing. This paper presents the core-centric programming model for establishing and using GS connections in MANGO. We show how OCP...

  12. On-chip cell analysis platform: Implementation of contact fluorescence microscopy in microfluidic chips

    Directory of Open Access Journals (Sweden)

    Hiroaki Takehara

    2017-09-01

    Full Text Available Although fluorescence microscopy is the gold standard tool for biomedical research and clinical applications, their use beyond well-established laboratory infrastructures remains limited. The present study investigated a novel on-chip cell analysis platform based on contact fluorescence microscopy and microfluidics. Combined use of a contact fluorescence imager based on complementary metal-oxide semiconductor technology and an ultra-thin glass bottom microfluidic chip enabled both to observe living cells with minimal image distortion and to ease controlling and handling of biological samples (e.g. cells and biological molecules in the imaged area. A proof-of-concept experiment of on-chip detection of cellular response to endothelial growth factor demonstrated promising use for the recently developed on-chip cell analysis platform. Contact fluorescence microscopy has numerous desirable features including compatibility with plastic microfluidic chips and compatibility with the electrical control system, and thus will fulfill the requirements of a fully automated cell analysis system.

  13. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  14. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  15. Signal processing for on-chip space division multiplexing

    DEFF Research Database (Denmark)

    Peucheret, Christophe; Ding, Yunhong; Xu, Jing

    2015-01-01

    Our recent results on the demonstration of on-chip mode-division multiplexing are reviewed, with special emphasis on nonlinear all-optical signal processing. Mode-selective parametric processes are demonstrated in a silicon-on-insulator waveguide.......Our recent results on the demonstration of on-chip mode-division multiplexing are reviewed, with special emphasis on nonlinear all-optical signal processing. Mode-selective parametric processes are demonstrated in a silicon-on-insulator waveguide....

  16. An overview about Networks-on-Chip with multicast suppor

    OpenAIRE

    Berejuck, Marcelo Daniel

    2016-01-01

    Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed sharedmemory,clock synchronization, replication, or barrier synchronization are examples of these re...

  17. Reliability, Availability and Serviceability of Networks-on-Chip

    CERN Document Server

    Cota, Érika; Soares Lubaszewski, Marcelo

    2012-01-01

    This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

  18. Integrated Millimeter-Wave Antennas for On-Chip Communication

    Directory of Open Access Journals (Sweden)

    S. Zainud-Deen

    2016-03-01

    Full Text Available This paper introduces the design and analysis of circularly polarized (CP and dual-polarized on-chip microstrip antennas for wireless communication at 60 GHz. The CP on-chip antenna consists of a circular aluminum patch with two overlapped circular slots fed by the transmission line. The radiation characteristics of the CP have been analyzed using the finite integration technique and finite element method based electromagnetic solvers. The CP antenna introduces left-hand circular polarization and employs as on-chip transmitter. A design of dual-polarized on-chip microstrip antenna at 60 GHz is investigated and is employed as on-chip receiver. The dual ports of the dual polarized antenna are designed with high isolation between them in order to be used as a two on-chip receivers. The radiation characteristics of the dual-port antenna have been calculated. The effect of the separation distance between the CP-antenna and the dual-polarized antenna on the same chip has been investigated. The performance parameters like the reflection coefficient, transmission coefficient, and the transmission gain of the two antennas at different separation distances have been introduced.

  19. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  20. On-chip steering of entangled photons in nonlinear photonic crystals.

    Science.gov (United States)

    Leng, H Y; Yu, X Q; Gong, Y X; Xu, P; Xie, Z D; Jin, H; Zhang, C; Zhu, S N

    2011-08-16

    One promising technique for working toward practical photonic quantum technologies is to implement multiple operations on a monolithic chip, thereby improving stability, scalability and miniaturization. The on-chip spatial control of entangled photons will certainly benefit numerous applications, including quantum imaging, quantum lithography, quantum metrology and quantum computation. However, external optical elements are usually required to spatially control the entangled photons. Here we present the first experimental demonstration of on-chip spatial control of entangled photons, based on a domain-engineered nonlinear photonic crystal. We manipulate the entangled photons using the inherent properties of the crystal during the parametric downconversion, demonstrating two-photon focusing and beam-splitting from a periodically poled lithium tantalate crystal with a parabolic phase profile. These experimental results indicate that versatile and precise spatial control of entangled photons is achievable. Because they may be operated independent of any bulk optical elements, domain-engineered nonlinear photonic crystals may prove to be a valuable ingredient in on-chip integrated quantum optics.

  1. Effect of on-chip filter on Coulomb blockade thermometer

    International Nuclear Information System (INIS)

    Roschier, L; Penttilä, J S; Gunnarsson, D; Prunnila, M; Meschke, M; Savin, A

    2012-01-01

    Coulomb Blockade Thermometer (CBT) is a primary thermometer based on electric conductance of normal tunnel junction arrays. One limitation for CBT use at the lowest temperatures has been due to environmental noise heating. To improve on this limitation, we have done measurements on CBT sensors fabricated with different on-chip filtering structures in a dilution refrigerator with a base temperature of 10 mK. The CBT sensors were produced with a wafer scale tunnel junction process. We present how the different on-chip filtering schemes affect the limiting saturation temperatures and show that CBT sensors with proper on-chip filtering work at temperatures below 20 mK and are tolerant to noisy environment.

  2. The ReNoC Reconfigurable Network-on-Chip

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo; Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2011-01-01

    This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility....... The article presents three novel algorithms that synthesize an application-specific NoC topology, map it onto the physical ReNoC architecture, and create deadlock-free, application-specific routing algorithms. We apply our algorithms to a mixture of real and synthetic applications and target three different...

  3. Advances on Microsized On-Chip Lithium-Ion Batteries.

    Science.gov (United States)

    Liu, Lixiang; Weng, Qunhong; Lu, Xueyi; Sun, Xiaolei; Zhang, Lin; Schmidt, Oliver G

    2017-12-01

    Development of microsized on-chip batteries plays an important role in the design of modern micro-electromechanical systems, miniaturized biomedical sensors, and many other small-scale electronic devices. This emerging field intimately correlates with the topics of rechargeable batteries, nanomaterials, on-chip microfabrication, etc. In recent years, a number of novel designs are proposed to increase the energy and power densities per footprint area, as well as other electrochemical performances of microsized lithium-ion batteries. These advances may guide the pathway for the future development of microbatteries. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  5. Modelling, Synthesis, and Configuration of Networks-on-Chips

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo

    is an analytical method for deriving the worst-case traffic pattern caused by an application and the cache-coherence protocol in a cache-coherent shared-memory system. The contributions related to network-on-chip optimization problems consist of two parts: The development and evaluation of six heuristics...

  6. Exploration within the Network-on-Chip Paradigm

    NARCIS (Netherlands)

    Wolkotte, P.T.

    2009-01-01

    A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Its functionality and maximum clock frequency grew steadily over the years. Due to the continuous increase of the number of transistors available on-chip and the operational

  7. LABS, cells and organs on chip : Technologies and biomedical applications

    NARCIS (Netherlands)

    Van Den Berg, Albert

    2017-01-01

    Over the past few decades both micro/ nanofabrication and microfluidics technologies have been crucial for the rapid development of Lab on a Chip systems. Here we present a few examples of this. Firstly, a capillary electrophoresis system on chip for blood analysis will be presented. Secondly, we

  8. Field Programmable Gate Arrays with Hardwired Networks on Chip

    NARCIS (Netherlands)

    Wahlah, M.A.

    2012-01-01

    Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual

  9. Nano lab-on-chip systems for biomedical and environmental ...

    African Journals Online (AJOL)

    In recent years, nano lab-on-chip (NLOC) has emerged as a powerful tool for biosensing and an active area of research particularly in DNA genetic and genetic related investigations. Compared with conventional sensing techniques, distinctive advantages of using NLOC for biomedicine and other related area include ...

  10. On-chip integrated lasers for biophotonic applications

    DEFF Research Database (Denmark)

    Mappes, Timo; Wienhold, Tobias; Bog, Uwe

    Meeting the need of biomedical users, we develop disposable Lab-on-a-Chip systems based on commercially available polymers. We are combining passive microfluidics with active optical elements on-chip by integrating multiple solid-state and liquid-core lasers. While covering a wide range of laser ...

  11. Customizing and hardwiring on-chip interconnects in FPGAs

    NARCIS (Netherlands)

    Hur, J.Y.

    2011-01-01

    This thesis presents our investigations on how to efficiently utilize on-chip wires to improve network performance in reconfigurable hardware. A fieldprogrammable gate array (FPGA), as a key component in a modern reconfigurable platform, accommodates many-millions of wires and the on-demand

  12. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    Directory of Open Access Journals (Sweden)

    Xin Wang

    2007-01-01

    Full Text Available Two network-on-chip (NoC designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

  13. A Formal Approach to the Verification of Networks on Chip

    Directory of Open Access Journals (Sweden)

    Schmaltz Julien

    2009-01-01

    Full Text Available Abstract The current technology allows the integration on a single die of complex systems-on-chip (SoCs that are composed of manufactured blocks (IPs, interconnected through specialized networks on chip (NoCs. IPs have usually been validated by diverse techniques (simulation, test, formal verification and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

  14. On-chip Magnetic Separation and Cell Encapsulation in Droplets

    Science.gov (United States)

    Chen, A.; Byvank, T.; Bharde, A.; Miller, B. L.; Chalmers, J. J.; Sooryakumar, R.; Chang, W.-J.; Bashir, R.

    2012-02-01

    The demand for high-throughput single cell assays is gaining importance because of the heterogeneity of many cell suspensions, even after significant initial sorting. These suspensions may display cell-to-cell variability at the gene expression level that could impact single cell functional genomics, cancer, stem-cell research and drug screening. The on-chip monitoring of individual cells in an isolated environment could prevent cross-contamination, provide high recovery yield and ability to study biological traits at a single cell level These advantages of on-chip biological experiments contrast to conventional methods, which require bulk samples that provide only averaged information on cell metabolism. We report on a device that integrates microfluidic technology with a magnetic tweezers array to combine the functionality of separation and encapsulation of objects such as immunomagnetically labeled cells or magnetic beads into pico-liter droplets on the same chip. The ability to control the separation throughput that is independent of the hydrodynamic droplet generation rate allows the encapsulation efficiency to be optimized. The device can potentially be integrated with on-chip labeling and/or bio-detection to become a powerful single-cell analysis device.

  15. On-chip microsystems in silicon: opportunities and limitations

    Science.gov (United States)

    Wolffenbuttel, R. F.

    1996-03-01

    Integrated on-chip micro-instrumentation systems in silicon are complete data acquisition systems on a single chip. This concept has appeared to be the ultimate solution in many applications, as it enables in principle the metamorphosis of a basic sensing element, affected with many shortcomings, into an on-chip data acquisition unit that provides an output digital data stream in a standard format not corrupted by sensor non-idealities. Market acceptance would be maximum, as no special knowledge about the internal operation is required, self-test and self-calibration can be included and the dimensions are not different from those of the integrated circuit. The various aspects that are relevant in estimating the constraints for successful implementation of the integrated silicon smart sensor will be outlined in comparison with the properties of more conventional sensor fabrication technologies. It will be shown that the acceptance of on-chip functional integration in an application depends primarily on the added value in terms of improved specification or functionality that the resulting device provides in that application. The economic viability is therefore decisive rather than the technological constraints. This is in contrast to the traditional technology push prevailing in sensor research over market pull mechanisms.

  16. On-chip High-Voltage Generator Design

    CERN Document Server

    Tanzawa, Toru

    2013-01-01

    This book describes high-voltage generator design with switched-capacitor multiplier techniques.  The author provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.   ·         Shows readers how to design charge pump circuits with lower voltage operation, higher power efficiency, and smaller circuit area; ·         Describes comprehensive circuits and systems design of on-chip high-voltage generators; ·         Covers all the component circuit blocks, including charge pumps, pump regulators, level shifters, oscillators, and references.

  17. 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2014-04-01

    A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

  18. An on-chip silicon compact triplexer based on cascaded tilted multimode interference couplers

    Science.gov (United States)

    Chen, Jingye; Liu, Penghao; Shi, Yaocheng

    2018-03-01

    An on-chip triplexer based on cascaded tilted multimode interference (MMI) couplers has been demonstrated to separate the 1310 nm wavelength band into one port and 1490 nm and 1550 nm wavelength bands into the other two ports respectively. By utilizing the dispersive self-imaging and pseudo self-imaging, the device length is not critically determined by the common multiple of beat lengths for different wavelengths. The total device size can be reduced to ∼450 μm, which is half of the butterfly structure reported. The whole device, fabricated with only one fully-etching step, is characterized with <-15 dB low crosstalk (CT) and ∼1 dB insertion loss (IL).

  19. GaN directional couplers for on-chip optical interconnect

    Science.gov (United States)

    Yuan, Jialei; Gao, Xumin; Yang, Yongchao; Zhu, Guixia; Yuan, Wei; Choi, Hoi Wai; Zhang, Zhiyu; Wang, Yongjin

    2017-04-01

    Here, we propose, fabricate and characterize GaN directional couplers for on-chip optical interconnect on a GaN-on-silicon platform. Suspended InGaN/GaN multiple-quantum-well diodes are adopted for both the transmitter and the receiver, and GaN directional couplers are used to achieve the light coupling between suspended waveguides that are directly connected to the transmitter and the receiver. The proposed on-chip optical interconnects are experimentally demonstrated by light propagation and in-plane data transmission using visible light. The light propagation images directly show that the emitted light can be laterally coupled into the suspended waveguide, and the guided light from the input waveguide then couples to the coupled waveguide due to the overlapped slab. The receiver detects the transmitted light from the coupled waveguide to complete the in-plane visible light communication process, as confirmed by pseudo-random binary sequence data and eye diagrams at the transmission rate of 30 Mbps.

  20. On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

    Science.gov (United States)

    Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

    2014-07-10

    Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

  1. Aging-Aware Routing Algorithms for Network-on-Chips

    OpenAIRE

    Bhardwaj, Kshitij

    2012-01-01

    Network-on-Chip (NoC) architectures have emerged as a better replacement of the traditional bus-based communication in the many-core era. However, continuous technology scaling has made aging mechanisms, such as Negative Bias Temperature Instability (NBTI) and electromigration, primary concerns in NoC design. In this work, a novel system-level aging model is proposed to model the effects of aging in NoCs, caused due to (a) asymmetric communication patterns between the network nodes, and (b) r...

  2. A Time-predictable Memory Network-on-Chip

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Chong, David VH; Puffitsch, Wolfgang

    2014-01-01

    To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for time-predictable memory...... arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without...

  3. Advancing Software Development for a Multiprocessor System-on-Chip

    Directory of Open Access Journals (Sweden)

    Stephen Bique

    2007-06-01

    Full Text Available A low-level language is the right tool to develop applications for some embedded systems. Notwithstanding, a high-level language provides a proper environment to develop the programming tools. The target device is a system-on-chip consisting of an array of processors with only local communication. Applications include typical streaming applications for digital signal processing. We describe the hardware model and stress the advantages of a flexible device. We introduce IDEA, a graphical integrated development environment for an array. A proper foundation for software development is a UML and standard programming abstractions in object-oriented languages.

  4. Custom Topology Generation for Network-on-Chip

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo; Sparsø, Jens

    2007-01-01

    This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration...... around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces...

  5. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  6. Models and formal verification of multiprocessor system-on-chips

    DEFF Research Database (Denmark)

    Brekling, Aske Wiid; Hansen, Michael Reichhardt; Madsen, Jan

    2008-01-01

    , the configuration of the execution platform and the mapping of the application onto this platform. The computational model provides a basis for formal analysis of systems. The model is translated to timed automata and a tool for system verification and simulation has been developed using Uppaal as backend. We...... a discrete model of computation for such systems and characterize the size of the computation tree it suffices to consider when checking for schedulability. Analysis of multiprocessor system on chips is a major challenge due to the freedom of interrelated choices concerning the application level...

  7. A VLSI System-on-Chip for Particle Detectors

    CERN Document Server

    AUTHOR|(CDS)2078019

    In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

  8. Microarchitecture of network-on-chip routers a designer's perspective

    CERN Document Server

    Dimitrakopoulos, Giorgos; Seitanidis, Ioannis

    2014-01-01

    This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a

  9. On-chip integrated lasers for biophotonic applications

    DEFF Research Database (Denmark)

    Mappes, Timo; Wienhold, Tobias; Bog, Uwe

    Meeting the need of biomedical users, we develop disposable Lab-on-a-Chip systems based on commercially available polymers. We are combining passive microfluidics with active optical elements on-chip by integrating multiple solid-state and liquid-core lasers. While covering a wide range of laser...... emission wavelengths, the chips have the size of microscope cover slips and use optical and fluidic interconnects only. Here, we present our latest realizations of integrated optofluidic lasers using whispering gallery mode or distributed feedback laser cavities....

  10. On-chip RF-to-optical transducer

    DEFF Research Database (Denmark)

    Simonsen, Anders; Tsaturyan, Yeghishe; Seis, Yannick

    2016-01-01

    interferometer. The coupling was mediated by a mechanical oscillator forming a mechanically compliant capacitor biased with a DC voltage. The latter enhances the electromechanical interaction all the way to the strong coupling regime. That scheme allowed optical detection of electronic signals with effective...... noise temperatures far below the actual temperature of the mechanical element. On-chip integration of the electrical, mechanical and optical elements is necessary for an implementation of the transduction scheme that is viable for commercial applications. Reliable assembly of a strongly coupled...

  11. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  12. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...... of temperature reduction, timing and area overhead to the general method, which enlarges the circuit area uniformly. A case study analyzes the design of Floating Point Units (FPU) from an energy and a thermal perspective. For the division operation, we compare different implementations and illustrate the impact...

  13. System on chip module configured for event-driven architecture

    Science.gov (United States)

    Robbins, Kevin; Brady, Charles E.; Ashlock, Tad A.

    2017-10-17

    A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

  14. Parametric dense stereovision implementation on a system-on chip (SoC).

    Science.gov (United States)

    Gardel, Alfredo; Montejo, Pablo; García, Jorge; Bravo, Ignacio; Lázaro, José L

    2012-01-01

    This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps) of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time.

  15. On-Chip Correlator for Passive Wireless SAW Multisensor Systems

    Directory of Open Access Journals (Sweden)

    Liqiang Xie

    2016-01-01

    Full Text Available For decoding the asynchronous superposition of response signals from different sensors, it is a challenge to achieve correlation in a code division multiplexing (CDM based passive wireless surface acoustic wave (SAW multisensor system. Therefore, an on-chip correlator scheme is developed in this paper. In contrast to conventional CDM-based systems, this novel scheme enables the correlations to be operated at the SAW sensors, instead of the reader. Thus, the response signals arriving at the reader are the result of cross-correlation on the chips. It is then easy for the reader to distinguish the sensor that is matched with the interrogating signal. The operation principle, signal analysis, and simulation of the novel scheme are described in the paper. The simulation results show the response signals from the correlations of the sensors. A clear spike pulse is presented in the response signals, when a sensor code is matched with the interrogating code. Simulations verify the feasibility of the on-chip correlator concept.

  16. 3D Printing of Organs-On-Chips

    Science.gov (United States)

    Yi, Hee-Gyeong; Lee, Hyungseok; Cho, Dong-Woo

    2017-01-01

    Organ-on-a-chip engineering aims to create artificial living organs that mimic the complex and physiological responses of real organs, in order to test drugs by precisely manipulating the cells and their microenvironments. To achieve this, the artificial organs should to be microfabricated with an extracellular matrix (ECM) and various types of cells, and should recapitulate morphogenesis, cell differentiation, and functions according to the native organ. A promising strategy is 3D printing, which precisely controls the spatial distribution and layer-by-layer assembly of cells, ECMs, and other biomaterials. Owing to this unique advantage, integration of 3D printing into organ-on-a-chip engineering can facilitate the creation of micro-organs with heterogeneity, a desired 3D cellular arrangement, tissue-specific functions, or even cyclic movement within a microfluidic device. Moreover, fully 3D-printed organs-on-chips more easily incorporate other mechanical and electrical components with the chips, and can be commercialized via automated massive production. Herein, we discuss the recent advances and the potential of 3D cell-printing technology in engineering organs-on-chips, and provides the future perspectives of this technology to establish the highly reliable and useful drug-screening platforms. PMID:28952489

  17. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  18. 3D Printing of Organs-On-Chips.

    Science.gov (United States)

    Yi, Hee-Gyeong; Lee, Hyungseok; Cho, Dong-Woo

    2017-01-25

    Organ-on-a-chip engineering aims to create artificial living organs that mimic the complex and physiological responses of real organs, in order to test drugs by precisely manipulating the cells and their microenvironments. To achieve this, the artificial organs should to be microfabricated with an extracellular matrix (ECM) and various types of cells, and should recapitulate morphogenesis, cell differentiation, and functions according to the native organ. A promising strategy is 3D printing, which precisely controls the spatial distribution and layer-by-layer assembly of cells, ECMs, and other biomaterials. Owing to this unique advantage, integration of 3D printing into organ-on-a-chip engineering can facilitate the creation of micro-organs with heterogeneity, a desired 3D cellular arrangement, tissue-specific functions, or even cyclic movement within a microfluidic device. Moreover, fully 3D-printed organs-on-chips more easily incorporate other mechanical and electrical components with the chips, and can be commercialized via automated massive production. Herein, we discuss the recent advances and the potential of 3D cell-printing technology in engineering organs-on-chips, and provides the future perspectives of this technology to establish the highly reliable and useful drug-screening platforms.

  19. On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

    Directory of Open Access Journals (Sweden)

    Valery Sklyarov

    2016-01-01

    Full Text Available Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1 designed in FPGAs and (2 implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems.

  20. 3D Printing of Organs-On-Chips

    Directory of Open Access Journals (Sweden)

    Hee-Gyeong Yi

    2017-01-01

    Full Text Available Organ-on-a-chip engineering aims to create artificial living organs that mimic the complex and physiological responses of real organs, in order to test drugs by precisely manipulating the cells and their microenvironments. To achieve this, the artificial organs should to be microfabricated with an extracellular matrix (ECM and various types of cells, and should recapitulate morphogenesis, cell differentiation, and functions according to the native organ. A promising strategy is 3D printing, which precisely controls the spatial distribution and layer-by-layer assembly of cells, ECMs, and other biomaterials. Owing to this unique advantage, integration of 3D printing into organ-on-a-chip engineering can facilitate the creation of micro-organs with heterogeneity, a desired 3D cellular arrangement, tissue-specific functions, or even cyclic movement within a microfluidic device. Moreover, fully 3D-printed organs-on-chips more easily incorporate other mechanical and electrical components with the chips, and can be commercialized via automated massive production. Herein, we discuss the recent advances and the potential of 3D cell-printing technology in engineering organs-on-chips, and provides the future perspectives of this technology to establish the highly reliable and useful drug-screening platforms.

  1. Lab-on-chip systems for integrated bioanalyses.

    Science.gov (United States)

    Conde, João Pedro; Madaboosi, Narayanan; Soares, Ruben R G; Fernandes, João Tiago S; Novo, Pedro; Moulas, Geraud; Chu, Virginia

    2016-06-30

    Biomolecular detection systems based on microfluidics are often called lab-on-chip systems. To fully benefit from the miniaturization resulting from microfluidics, one aims to develop 'from sample-to-answer' analytical systems, in which the input is a raw or minimally processed biological, food/feed or environmental sample and the output is a quantitative or qualitative assessment of one or more analytes of interest. In general, such systems will require the integration of several steps or operations to perform their function. This review will discuss these stages of operation, including fluidic handling, which assures that the desired fluid arrives at a specific location at the right time and under the appropriate flow conditions; molecular recognition, which allows the capture of specific analytes at precise locations on the chip; transduction of the molecular recognition event into a measurable signal; sample preparation upstream from analyte capture; and signal amplification procedures to increase sensitivity. Seamless integration of the different stages is required to achieve a point-of-care/point-of-use lab-on-chip device that allows analyte detection at the relevant sensitivity ranges, with a competitive analysis time and cost. © 2016 The Author(s). Published by Portland Press Limited on behalf of the Biochemical Society.

  2. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz

    KAUST Repository

    Nafe, Mahmoud

    2015-08-04

    Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip. Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated. In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface

  3. Chalcogenide based rib waveguide for compact on-chip supercontinuum sources in mid-infrared domain

    Science.gov (United States)

    Saini, Than Singh; Tiwari, Umesh Kumar; Sinha, Ravindra Kumar

    2017-08-01

    We have designed and analysed a rib waveguide structure in recently reported Ga-Sb-S based highly nonlinear chalcogenide glass for nonlinear applications. The proposed waveguide structure possesses a very high nonlinear coefficient and can be used to generate broadband supercontinuum in mid-infrared domain. The reported design of the chalcogenide waveguide offers two zero dispersion values at 1800 nm and 2900 nm. Such rib waveguide structure is suitable to generate efficient supercontinuum generation ranging from 500 - 7400 μm. The reported waveguide can be used for the realization of the compact on-chip supercontinuum sources which are highly applicable in optical imaging, optical coherence tomography, food quality control, security and sensing.

  4. Structural characteristics of carbon nanofibers for on-chip interconnect applications

    International Nuclear Information System (INIS)

    Ominami, Yusuke; Ngo, Quoc; Austin, Alexander J.; Yoong, Hans; Yang, Cary Y.; Cassell, Alan M.; Cruden, Brett A.; Li Jun; Meyyappan, M.

    2005-01-01

    In this letter, we compare the structures of plasma-enhanced chemical vapor deposition of Ni-catalyzed and Pd-catalyzed carbon nanofibers (CNFs) synthesized for on-chip interconnect applications with scanning transmission electron microscopy (STEM). The Ni-catalyzed CNF has a conventional fiberlike structure and many graphitic layers that are almost parallel to the substrate at the CNF base. In contrast, the Pd-catalyzed CNF has a multiwall nanotubelike structure on the sidewall spanning the entire CNF. The microstructure observed in the Pd-catalyzed fibers at the CNF-metal interface has the potential to lower contact resistance significantly, as our electrical measurements using current-sensing atomic force microscopy indicate. A structural model is presented based on STEM image analysis

  5. Organ-on-chip models of cancer metastasis for future personalized medicine: From chip to the patient.

    Science.gov (United States)

    Caballero, D; Kaushik, S; Correlo, V M; Oliveira, J M; Reis, R L; Kundu, S C

    2017-12-01

    Most cancer patients do not die from the primary tumor but from its metastasis. Current in vitro and in vivo cancer models are incapable of satisfactorily predicting the outcome of various clinical treatments on patients. This is seen as a serious limitation and efforts are underway to develop a new generation of highly predictive cancer models with advanced capabilities. In this regard, organ-on-chip models of cancer metastasis emerge as powerful predictors of disease progression. They offer physiological-like conditions where the (hypothesized) mechanistic determinants of the disease can be assessed with ease. Combined with high-throughput characteristics, the employment of organ-on-chip technology would allow pharmaceutical companies and clinicians to test new therapeutic compounds and therapies. This will permit the screening of a large battery of new drugs in a fast and economic manner, to accelerate the diagnosis of the disease in the near future, and to test personalized treatments using cells from patients. In this review, we describe the latest advances in the field of organ-on-chip models of cancer metastasis and their integration with advanced imaging, screening and biosensing technologies for future precision medicine applications. We focus on their clinical applicability and market opportunities to drive us forward to the next generation of tumor models for improved cancer patient theranostics. Copyright © 2017 Elsevier Ltd. All rights reserved.

  6. The next generation platform for System-on-Chip; Neste generasjons plattform for System-on-Chip

    Energy Technology Data Exchange (ETDEWEB)

    Tallaksen, Espen

    2002-07-01

    An increasing demand for including analog functionality in order to have a complete system on one chip requires a new step in the methodology: second-generation System-on-Chip (SoC) platforms. The capacity, or amount of functionality, which can be put into an ASIC (Application Specific Integrated Circuit) chip is doubled for each one and a half year. The design methodology has not kept up with this development, which has resulted in a gap between what can go into the ASIC physically and our ability to do it in practice. This design gap is increasing and has led to increased attention to design efficiency. The semi conductor industry has introduced concepts such as Intellectual Property (P), Virtual Components (VC), System-on-Chip (SoC) and Platform Based Design (PBD). Digital design has been in focus, since traditionally it is digital design that has given momentum to the development of ASIC methodology and it is above all the digital part that increases in functionality. Today, however, the market increasingly demands increased analog functionality to have a complete system on one single chip.

  7. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  8. Photonic crystal biosensors towards on-chip integration.

    Science.gov (United States)

    Threm, Daniela; Nazirizadeh, Yousef; Gerken, Martina

    2012-08-01

    Photonic crystal technology has attracted large interest in the last years. The possibility to generate highly sensitive sensor elements with photonic crystal structures is very promising for medical or environmental applications. The low-cost fabrication on the mass scale is as advantageous as the compactness and reliability of photonic crystal biosensors. The possibility to integrate microfluidic channels together with photonic crystal structures allows for highly compact devices. This article reviews different types of photonic crystal sensors including 1D photonic crystal biosensors, biosensors with photonic crystal slabs, photonic crystal waveguide biosensors and biosensors with photonic crystal microcavities. Their applications in biomolecular and pathogen detection are highlighted. The sensitivities and the detection limits of the different biosensors are compared. The focus is on the possibilities to integrate photonic crystal biosensors on-chip. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. On-Chip Architecture for Self-Homodyned Nonclassical Light

    Science.gov (United States)

    Fischer, Kevin A.; Kelaita, Yousif A.; Sapra, Neil V.; Dory, Constantin; Lagoudakis, Konstantinos G.; Müller, Kai; Vučković, Jelena

    2017-04-01

    In the last decade, there has been remarkable progress on the practical integration of on-chip quantum photonic devices, yet quantum-state generators remain an outstanding challenge. Simultaneously, the quantum-dot photonic-crystal-resonator platform has demonstrated a versatility for creating nonclassical light with tunable quantum statistics thanks to a newly discovered self-homodyning interferometric effect that preferentially selects the quantum light over the classical light when using an optimally tuned Fano resonance. In this work, we propose a general structure for the cavity quantum electrodynamical generation of quantum states from a waveguide-integrated version of the quantum-dot photonic-crystal-resonator platform, which is specifically tailored for preferential quantum-state transmission. We support our results with rigorous finite-difference time-domain and quantum-optical simulations and show how our proposed device can serve as a robust generator of highly pure single- and even multiphoton states.

  10. On-chip deposition of carbon nanotubes using CMOS microhotplates

    International Nuclear Information System (INIS)

    Haque, M S; Teo, K B K; Rupensinghe, N L; Ali, S Z; Haneef, I; Maeng, Sunglyul; Park, J; Udrea, F; Milne, W I

    2008-01-01

    The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 deg. C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required

  11. On-Chip generation of polymer microcapsules through droplet coalescence

    Science.gov (United States)

    Eqbal, Md Danish; Gundabala, Venkat; Gundabala lab Team

    Alginate microbeads and microcapsules have numerous applications in drug delivery, tissue engineering and other biomedical areas due to their unique properties. Microcapsules with liquid core are of particular interest in the area of cell encapsulation. Various methods such as coacervation, emulsification, micro-nozzle, etc. exist for the generation of microbeads and microcapsules. However, these methods have several drawbacks like coagulation, non-uniformity, and polydispersity. In this work we present a method for complete on chip generation of alginate microcapsules (single core as well as double core) through the use of droplet merging technique. For this purpose, a combined Coflow and T-junction configuration is implemented in a hybrid glass-PDMS (Polydimethylsiloxane) microfluidic device. Efficient generation is achieved through precise matching of the generation rates of the coalescing drops. Through this approach, microcapsules with intact single and double (liquid) cores surrounded by alginate shell have been successfully generated and characterized.

  12. Lab-on-chip components for molecular detection

    Science.gov (United States)

    Adam, Tijjani; Dhahi, Th S.; Mohammed, Mohammed; Hashim, U.; Noriman, N. Z.; Dahham, Omar S.

    2017-09-01

    We successfully fabricated Lab on chip components and integrated for possible use in biomedical application. The sensor was fabricated by using conventional photolithography method integrated with PDMS micro channels for smooth delivery of sample to the sensing domain. The sensor was silanized and aminated with 3-Aminopropyl triethoxysilane (APTES) to functionalize the surface with biomolecules and create molecular binding chemistry. The resulting Si-O-Si- components were functionalized with oligonucleotides probe of HPV, which interacted with the single stranded HPV DNA target to create a field across on the device. The fabrication, immobilization and hybridization processes were characterized with current voltage (I-V) characterization (KEITHLEY, 6487). The sensor show selectivity for the HPV DNA target in a linear range from concentration 0.1 nM to 1 µM. This strategy presented a simple, rapid and sensitive platform for HPV detection and would become a powerful tool for pathogenic microorganisms screening in clinical diagnosis.

  13. Endocrine system on chip for a diabetes treatment model.

    Science.gov (United States)

    Nguyen, Dao Thi Thuy; van Noort, Danny; Jeong, In-Kyung; Park, Sungsu

    2017-02-21

    The endocrine system is a collection of glands producing hormones which, among others, regulates metabolism, growth and development. One important group of endocrine diseases is diabetes, which is caused by a deficiency or diminished effectiveness of endogenous insulin. By using a microfluidic perfused 3D cell-culture chip, we developed an 'endocrine system on chip' to potentially be able to screen drugs for the treatment of diabetes by measuring insulin release over time. Insulin-secreting β-cells are located in the pancreas, while L-cells, located in the small intestines, stimulate insulin secretion. Thus, we constructed a co-culture of intestinal-pancreatic cells to measure the effect of glucose on the production of glucagon-like peptide-1 (GLP-1) from the L-cell line (GLUTag) and insulin from the pancreatic β-cell line (INS-1). After three days of culture, both cell lines formed aggregates, exhibited 3D cell morphology, and showed good viability (>95%). We separately measured the dynamic profile of GLP-1 and insulin release at glucose concentrations of 0.5 and 20 mM, as well as the combined effect of GLP-1 on insulin production at these glucose concentrations. In response to glucose stimuli, GLUTag and INS-1 cells produced higher amounts of GLP-1 and insulin, respectively, compared to a static 2D cell culture. INS-1 combined with GLUTag cells exhibited an even higher insulin production in response to glucose stimulation. At higher glucose concentrations, the diabetes model on chip showed faster saturation of the insulin level. Our results suggest that the endocrine system developed in this study is a useful tool for observing dynamical changes in endocrine hormones (GLP-1 and insulin) in a glucose-dependent environment. Moreover, it can potentially be used to screen GLP-1 analogues and natural insulin and GLP-1 stimulants for diabetes treatment.

  14. On-chip training for cellular neural networks using iterative annealing

    Science.gov (United States)

    Feiden, Dirk; Tetzlaff, Ronald

    2003-04-01

    Cellular Neural Network-Universal Machines (CNN-UM) are analog devices, which are excellently suited for image processing. A big challenge thereby is the determination of CNN templates for special image processing tasks. In many cases appropriate templates can only be found by a parameter optimization. The determination of templates for complex applications in the area of CNN is usually performed by using a CNN software simulator. Unfortunately, in many cases the determined templates cannot be used in hardware realizations of CNN caused by realization effects. In order to find robust templates, which are not only working on CNN simulators, but also on hardware implementations, we present in this contribution a new kind of on-chip-multi-template-training. Furthermore, as a possible application, we will also present a CNN-based solution of the problem of Pattern Matching, which is a processing step in many areas of image processing, like e.g. in Motion Estimation, Image- and Video-Compression.

  15. Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology

    OpenAIRE

    Leroy, Anthony

    2006-01-01

    Ce mémoire traite des systèmes intégrés sur puce (System-on-Chip) à faible consommation d'énergie tels que ceux qui seront utilisés dans les équipements portables de future génération (ordinateurs de poche (PDA), téléphones mobiles). S'agissant d'équipements alimentés par des batteries, la consommation énergétique est un problème critique. Ces plateformes contiendront probablement une douzaine de coeurs de processeur et une quantité importante de mémoire embarquée. Une architecture de communi...

  16. Omphale: Streamlining the Communication for Jobs in a Multi Processor System on Chip

    NARCIS (Netherlands)

    Bijlsma, T.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria; Jansen, P.G.

    2007-01-01

    Our Multi Processor System on Chip (MPSoC) template provides processing tiles that are connected via a network on chip. A processing tile contains a processing unit and a Scratch Pad Memory (SPM). This paper presents the Omphale tool that performs the first step in mapping a job, represented by a

  17. On-chip graphene electrode, methods of making, and methods of use

    KAUST Repository

    Nayak, Pranati

    2018-01-25

    Embodiments of the present disclosure provide a device including an on-chip electrode platform including one or more three dimensional laser scribed graphene electrodes, methods of making the on-chip electrode platform, methods of analyzing (e.g., detecting, quantifying, and the like) chemicals and biochemicals, and the like.

  18. Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

    NARCIS (Netherlands)

    Hansson, A.; Goossens, K.; Rãdulescu, A.

    2007-01-01

    Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions

  19. Microfluidic organ-on-chip technology for blood-brain barrier research.

    Science.gov (United States)

    van der Helm, Marinke W; van der Meer, Andries D; Eijkel, Jan C T; van den Berg, Albert; Segerink, Loes I

    2016-01-01

    Organs-on-chips are a new class of microengineered laboratory models that combine several of the advantages of current in vivo and in vitro models. In this review, we summarize the advances that have been made in the development of organ-on-chip models of the blood-brain barrier (BBBs-on-chips) and the challenges that are still ahead. The BBB is formed by specialized endothelial cells and separates blood from brain tissue. It protects the brain from harmful compounds from the blood and provides homeostasis for optimal neuronal function [corrected]. Studying BBB function and dysfunction is important for drug development and biomedical research. Microfluidic BBBs-on-chips enable real-time study of (human) cells in an engineered physiological microenvironment, for example incorporating small geometries and fluid flow as well as sensors. Examples of BBBs-on-chips in literature already show the potential of more realistic microenvironments and the study of organ-level functions. A key challenge in the field of BBB-on-chip development is the current lack of standardized quantification of parameters such as barrier permeability and shear stress. This limits the potential for direct comparison of the performance of different BBB-on-chip models to each other and existing models. We give recommendations for further standardization in model characterization and conclude that the rapidly emerging field of BBB-on-chip models holds great promise for further studies in BBB biology and drug development.

  20. A lab-on-chip for malaria diagnosis and surveillance.

    Science.gov (United States)

    Taylor, Brian J; Howell, Anita; Martin, Kimberly A; Manage, Dammika P; Gordy, Walter; Campbell, Stephanie D; Lam, Samantha; Jin, Albert; Polley, Spencer D; Samuel, Roshini A; Atrazhev, Alexey; Stickel, Alex J; Birungi, Josephine; Mbonye, Anthony K; Pilarski, Linda M; Acker, Jason P; Yanow, Stephanie K

    2014-05-09

    Access to timely and accurate diagnostic tests has a significant impact in the management of diseases of global concern such as malaria. While molecular diagnostics satisfy this need effectively in developed countries, barriers in technology, reagent storage, cost and expertise have hampered the introduction of these methods in developing countries. In this study a simple, lab-on-chip PCR diagnostic was created for malaria that overcomes these challenges. The platform consists of a disposable plastic chip and a low-cost, portable, real-time PCR machine. The chip contains a desiccated hydrogel with reagents needed for Plasmodium specific PCR. Chips can be stored at room temperature and used on demand by rehydrating the gel with unprocessed blood, avoiding the need for sample preparation. These chips were run on a custom-built instrument containing a Peltier element for thermal cycling and a laser/camera setup for amplicon detection. This diagnostic was capable of detecting all Plasmodium species with a limit of detection for Plasmodium falciparum of 2 parasites/μL of blood. This exceeds the sensitivity of microscopy, the current standard for diagnosis in the field, by ten to fifty-fold. In a blind panel of 188 patient samples from a hyper-endemic region of malaria transmission in Uganda, the diagnostic had high sensitivity (97.4%) and specificity (93.8%) versus conventional real-time PCR. The test also distinguished the two most prevalent malaria species in mixed infections, P. falciparum and Plasmodium vivax. A second blind panel of 38 patient samples was tested on a streamlined instrument with LED-based excitation, achieving a sensitivity of 96.7% and a specificity of 100%. These results describe the development of a lab-on-chip PCR diagnostic from initial concept to ready-for-manufacture design. This platform will be useful in front-line malaria diagnosis, elimination programmes, and clinical trials. Furthermore, test chips can be adapted to detect other

  1. Parametric Dense Stereovision Implementation on a System-on Chip (SoC

    Directory of Open Access Journals (Sweden)

    Pablo Montejo

    2012-02-01

    Full Text Available This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time.

  2. Pipelined multiprocessor system-on-chip for multimedia

    CERN Document Server

    Javaid, Haris

    2014-01-01

    This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint.  A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.   ·         Describes the ...

  3. Multimedia Terminal System-on-Chip Design and Simulation

    Directory of Open Access Journals (Sweden)

    Barbieri Ivano

    2005-01-01

    Full Text Available This paper proposes a design approach based on integrated architectural and system-on-chip (SoC simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW digital signal processors (DSPs, the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

  4. Hardware implementation of on -chip learning using re configurable FPGAS

    International Nuclear Information System (INIS)

    Kelash, H.M.; Sorour, H.S; Mahmoud, I.I.; Zaki, M; Haggag, S.S.

    2009-01-01

    The multilayer perceptron (MLP) is a neural network model that is being widely applied in the solving of diverse problems. A supervised training is necessary before the use of the neural network.A highly popular learning algorithm called back-propagation is used to train this neural network model. Once trained, the MLP can be used to solve classification problems. An interesting method to increase the performance of the model is by using hardware implementations. The hardware can do the arithmetical operations much faster than software. In this paper, a design and implementation of the sequential mode (stochastic mode) of backpropagation algorithm with on-chip learning using field programmable gate arrays (FPGA) is presented, a pipelined adaptation of the on-line back propagation algorithm (BP) is shown.The hardware implementation of forward stage, backward stage and update weight of backpropagation algorithm is also presented. This implementation is based on a SIMD parallel architecture of the forward propagation the diagnosis of the multi-purpose research reactor of Egypt accidents is used to test the proposed system

  5. On-chip skin color detection using a triple-well CMOS process

    Science.gov (United States)

    Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

    2004-03-01

    In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

  6. Computational sensing of herpes simplex virus using a cost-effective on-chip microscope

    KAUST Repository

    Ray, Aniruddha

    2017-07-03

    Caused by the herpes simplex virus (HSV), herpes is a viral infection that is one of the most widespread diseases worldwide. Here we present a computational sensing technique for specific detection of HSV using both viral immuno-specificity and the physical size range of the viruses. This label-free approach involves a compact and cost-effective holographic on-chip microscope and a surface-functionalized glass substrate prepared to specifically capture the target viruses. To enhance the optical signatures of individual viruses and increase their signal-to-noise ratio, self-assembled polyethylene glycol based nanolenses are rapidly formed around each virus particle captured on the substrate using a portable interface. Holographic shadows of specifically captured viruses that are surrounded by these self-assembled nanolenses are then reconstructed, and the phase image is used for automated quantification of the size of each particle within our large field-of-view, ~30 mm2. The combination of viral immuno-specificity due to surface functionalization and the physical size measurements enabled by holographic imaging is used to sensitively detect and enumerate HSV particles using our compact and cost-effective platform. This computational sensing technique can find numerous uses in global health related applications in resource-limited environments.

  7. A Novel Architecture for Adaptive Traffic Control in Network on Chip using Code Division Multiple Access Technique

    OpenAIRE

    Fatemeh. Dehghani; Shahram. Darooei

    2016-01-01

    Network on chip has emerged as a long-term and effective method in Multiprocessor System-on-Chip communications in order to overcome the bottleneck in bus based communication architectures. Efficiency and performance of network on chip is so dependent on the architecture and structure of the network. In this paper a new structure and architecture for adaptive traffic control in network on chip using Code Division Multiple Access technique is presented. To solve the problem of synchronous acce...

  8. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  9. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard...

  10. Design and FPGA-implementation of multilayer neural networks with on-chip learning

    International Nuclear Information System (INIS)

    Haggag, S.S.M.Y

    2008-01-01

    Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

  11. A system-level multiprocessor system-on-chip modeling framework

    DEFF Research Database (Denmark)

    Virk, Kashif Munir; Madsen, Jan

    2004-01-01

    We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip...... and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient...

  12. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  13. Tunable metamaterial-induced transparency with gate-controlled on-chip graphene metasurface.

    Science.gov (United States)

    Chen, Zan Hui; Tao, Jin; Gu, Jia Hua; Li, Jian; Hu, Di; Tan, Qi Long; Zhang, Fengchun; Huang, Xu Guang

    2016-12-12

    We propose and numerically investigate a gate-controlled on-chip graphene metasurface consisting of a monolayer graphene sheet and silicon photonic crystal-like substrate, to achieve an electrically-tunable induced transparency. The operation mechanism of the induced transparency of the on-chip graphene metasurface is analyzed. The tunable optical properties with different gate-voltages and polarizations have been discussed. Additionally, the spectral feature of the on-chip graphene metasurface as a function of the refractive index of the local environment is also investigated. The result shows that the on-chip graphene metasurface as a refractive index sensor can achieve an overall figure of merit of 8.89 in infrared wavelength range. Our study suggests that the proposed structure is potentially attractive as optoelectronic modulators and refractive index sensors.

  14. Essential issues in SOC design designing complex systems-on-chip

    CERN Document Server

    Lin, Youn-long Steve

    2007-01-01

    Covers issues related to system-on-chip (SoC) design. This book covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.

  15. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    (clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic......Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

  16. A new 2D mesh routing approach for networks on chip Une nouvelle ...

    African Journals Online (AJOL)

    Keywords: Networks on chip, Dynamic routing algorithm, Clustering, Mesh topology, Systems on chip. Résumé. Dans le passé, les systèmes embarqués et numériques ont été confinés surtout aux systèmes informatiques. Aujourd'hui, ces systèmes sont appliqués dans un grand nombre de domaines et d'appareils tels que ...

  17. On-chip RF-to-optical transducer (Conference Presentation)

    Science.gov (United States)

    Simonsen, Anders; Tsaturyan, Yeghishe; Seis, Yannick; Schmid, Silvan; Schliesser, Albert; Polzik, Eugene S.

    2016-04-01

    Recent advances in the fabrication of nano- and micromechanical elements enable the realization of high-quality mechanical resonators with masses so small that the forces from optical photons can have a significant impact on their motion. This facilitates a strong interaction between mechanical motion and light, or phonons and photons. This interaction is the corner stone of the field of optomechanics and allows, for example, for ultrasensitive detection and manipulation of mechanical motion using laser light. Remarkably, today these techniques can be extended into the quantum regime, in which fundamental fluctuations of light and mechanics govern the system's behavior. Micromechanical elements can also interact strongly with other physical systems, which is the central aspect of many micro-electro-mechanical based sensors. Micromechanical elements can therefore act as a bridge between these diverse systems, plus technologies that utilize them, and the mature toolbox of optical techniques that routinely operates at the quantum limit. In a previous work [1], we demonstrated such a bridge by realizing simultaneous coupling between an electronic LC circuit and a quantum-noise limited optical interferometer. The coupling was mediated by a mechanical oscillator forming a mechanically compliant capacitor biased with a DC voltage. The latter enhances the electromechanical interaction all the way to the strong coupling regime. That scheme allowed optical detection of electronic signals with effective noise temperatures far below the actual temperature of the mechanical element. On-chip integration of the electrical, mechanical and optical elements is necessary for an implementation of the transduction scheme that is viable for commercial applications. Reliable assembly of a strongly coupled electromechanical device, and inclusion of an optical cavity for enhanced optical readout, are key features of the new platform. Both can be achieved with standard cleanroom fabrication

  18. Object Recognition System-on-Chip Using the Support Vector Machines

    Directory of Open Access Journals (Sweden)

    Houzet Dominique

    2005-01-01

    Full Text Available The first aim of this work is to propose the design of a system-on-chip (SoC platform dedicated to digital image and signal processing, which is tuned to implement efficiently multiply-and-accumulate (MAC vector/matrix operations. The second aim of this work is to implement a recent promising neural network method, namely, the support vector machine (SVM used for real-time object recognition, in order to build a vision machine. With such a reconfigurable and programmable SoC platform, it is possible to implement any SVM function dedicated to any object recognition problem. The final aim is to obtain an automatic reconfiguration of the SoC platform, based on the results of the learning phase on an objects' database, which makes it possible to recognize practically any object without manual programming. Recognition can be of any kind that is from image to signal data. Such a system is a general-purpose automatic classifier. Many applications can be considered as a classification problem, but are usually treated specifically in order to optimize the cost of the implemented solution. The cost of our approach is more important than a dedicated one, but in a near future, hundreds of millions of gates will be common and affordable compared to the design cost. What we are proposing here is a general-purpose classification neural network implemented on a reconfigurable SoC platform. The first version presented here is limited in size and thus in object recognition performances, but can be easily upgraded according to technology improvements.

  19. Antennas for Terahertz Applications: Focal Plane Arrays and On-chip Non-contact Measurement Probes

    Science.gov (United States)

    Trichopoulos, Georgios C.

    . Additionally, a butterfly-shaped antenna layout is introduced that enables broadband imaging. The alternative design presented here, allows for video-rate imaging in the 0.6--1.2 THz band and maintains a small antenna footprint, resulting in densely packed FPAs. In both antenna designs, we optimize the impedance matching between the antennas and the integrated electronic devices, thus achieving optimum responsivity levels for high sensitivity and low noise performance. Subsequently, we present the design details of the first THz camera and the first THz camera images captured. With the realized THz camera, imaging of concealed objects is achieved with computer tomography system that allows rapid cross-sectional imaging (˜2 min). For the design and analysis of the THz camera performance, we developed an in-house hybrid electromagnetic model, combining full-wave and high-frequency computational methods. The antenna radiation and impedance computation is first carried out using full-wave modeling of the FPA. Subsequently, we employ scalar diffraction theory to compute the field distribution at any point in space. Thus, the hybrid electromagnetic model allows fast and accurate design of THz antennas and modeling of the complete THz imaging system. Finally, motivated by the novel THz antenna layouts and the quasioptical techniques, we developed a novel non-contact probe measurement method for on-chip device characterization. In the THz regime, traditional contact probes are too small and fragile, thus inhibiting accurate and reliable circuit measurements. By integrating the device under test (DUT) with THz antennas that act as the measurement probes, we may couple the incident and reflected signal from and to the network analyzer without residing to any physical connection.

  20. A solvent resistant lab-on-chip platform for radiochemistry applications.

    Science.gov (United States)

    Rensch, Christian; Lindner, Simon; Salvamoser, Ruben; Leidner, Stephanie; Böld, Christoph; Samper, Victor; Taylor, David; Baller, Marko; Riese, Stefan; Bartenstein, Peter; Wängler, Carmen; Wängler, Björn

    2014-07-21

    The application of microfluidics to the synthesis of Positron Emission Tomography (PET) tracers has been explored for more than a decade. Microfluidic benefits such as superior temperature control have been successfully applied to PET tracer synthesis. However, the design of a compact microfluidic platform capable of executing a complete PET tracer synthesis workflow while maintaining prospects for commercialization remains a significant challenge. This study uses an integral system design approach to tackle commercialization challenges such as the material to process compatibility with a path towards cost effective lab-on-chip mass manufacturing from the start. It integrates all functional elements required for a simple PET tracer synthesis into one compact radiochemistry platform. For the lab-on-chip this includes the integration of on-chip valves, on-chip solid phase extraction (SPE), on-chip reactors and a reversible fluid interface while maintaining compatibility with all process chemicals, temperatures and chip mass manufacturing techniques. For the radiochemistry device it includes an automated chip-machine interface enabling one-move connection of all valve actuators and fluid connectors. A vial-based reagent supply as well as methods to transfer reagents efficiently from the vials to the chip has been integrated. After validation of all those functional elements, the microfluidic platform was exemplarily employed for the automated synthesis of a Gastrin-releasing peptide receptor (GRP-R) binding the PEGylated Bombesin BN(7-14)-derivative ([(18)F]PESIN) based PET tracer.

  1. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  2. A Review of Some Superconducting Technologies for AtLAST: Parametric Amplifiers, Kinetic Inductance Detectors, and On-Chip Spectrometers

    Science.gov (United States)

    Noroozian, Omid

    2018-01-01

    The current state of the art for some superconducting technologies will be reviewed in the context of a future single-dish submillimeter telescope called AtLAST. The technologies reviews include: 1) Kinetic Inductance Detectors (KIDs), which have now been demonstrated in large-format kilo-pixel arrays with photon background-limited sensitivity suitable for large field of view cameras for wide-field imaging. 2) Parametric amplifiers - specifically the Traveling-Wave Kinetic Inductance (TKIP) amplifier - which has enormous potential to increase sensitivity, bandwidth, and mapping speed of heterodyne receivers, and 3) On-chip spectrometers, which combined with sensitive direct detectors such as KIDs or TESs could be used as Multi-Object Spectrometers on the AtLAST focal plane, and could provide low-medium resolution spectroscopy of 100 objects at a time in each field of view.

  3. A compact and integrated immunoassay with on-chip dispensing and magnetic particle handling.

    Science.gov (United States)

    Zirath, Helene; Peham, Johannes R; Schnetz, Guntram; Coll, Albert; Brandhoff, Lukas; Spittler, Andreas; Vellekoop, Michael J; Redl, Heinz

    2016-02-01

    We present a compact diagnostic platform for a rapid and sensitive detection of plasma biomarkers. The platform consists of a disposable microfluidic polymer chip, a processing device including a lens-free and cost efficient sensor system and a setup for dispersion of magnetic particles. The biomarkers of interest are quantified by magnetic bead based immunoassays with chemiluminescent readout technology. With a novel system for dispersion and manipulation of the magnetic particles in combination with chemiluminescence detection, the sensitivity of the immunoassay is improved and enables a rapid assay in a microfluidic format. In the disposable chip, extra chambers for storage and dispensing of biomarker specific reagents are integrated, which reduce the need of external dosing devices and thereby the cost of the platform is decreased. Plasma biomarkers for monitoring of sepsis could be quantified at 10 pg/mL concentrations within a total time of 30 min by the present system. This contribution is a fundamental step towards the development of an automatic and compact Point-of-Care testing device for monitoring of patients at the intensive care unit.

  4. On-chip spin-controlled orbital angular momentum directional coupling

    Science.gov (United States)

    Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

    2018-01-01

    Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

  5. Blood cleaner on-chip design for artificial human kidney manipulation

    Science.gov (United States)

    Suwanpayak, N; Jalil, MA; Aziz, MS; Ismail, FD; Ali, J; Yupapin, PP

    2011-01-01

    A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells) can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney), and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications. PMID:21720507

  6. Blood cleaner on-chip design for artificial human kidney manipulation.

    Science.gov (United States)

    Suwanpayak, N; Jalil, M A; Aziz, M S; Ismail, F D; Ali, J; Yupapin, P P

    2011-01-01

    A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells) can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney), and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.

  7. A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

    Directory of Open Access Journals (Sweden)

    WANG, J.

    2012-11-01

    Full Text Available In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.

  8. Simulation-based Modeling Frameworks for Networked Multi-processor System-on-Chip

    DEFF Research Database (Denmark)

    Mahadevan, Shankar

    2006-01-01

    : namely ARTS and RIPE, that allows to model hardware (computation time, power consumption, network latency, caching effect, etc.) and software (application partition and mapping, operating system scheduling, interrupt handling, etc.) aspects from system-level to cycle-true abstraction. Thereby, we can......This thesis deals with modeling aspects of multi-processor system-on-chip (MpSoC) design affected by the on-chip interconnect, also called the Network-on-Chip (NoC), at various levels of abstraction. To begin with, we undertook a comprehensive survey of research and design practices of networked Mp...... realistically model the application executing on the architecture. This includes e.g. accurate modeling of synchronization, cache refills, context switching effects, so on, which are critically dependent on the architecture and the performance of the NoC. The foundation of the ARTS model is abstract tasks...

  9. On-chip optical phase locking of single growth monolithically integrated Slotted Fabry Perot lasers.

    Science.gov (United States)

    Morrissey, P E; Cotter, W; Goulding, D; Kelleher, B; Osborne, S; Yang, H; O'Callaghan, J; Roycroft, B; Corbett, B; Peters, F H

    2013-07-15

    This work investigates the optical phase locking performance of Slotted Fabry Perot (SFP) lasers and develops an integrated variable phase locked system on chip for the first time to our knowledge using these lasers. Stable phase locking is demonstrated between two SFP lasers coupled on chip via a variable gain waveguide section. The two lasers are biased differently, one just above the threshold current of the device with the other at three times this value. The coupling between the lasers can be controlled using the variable gain section which can act as a variable optical attenuator or amplifier depending on bias. Using this, the width of the stable phase locking region on chip is shown to be variable.

  10. Integrated Photonic Orbital Angular Momentum Multiplexing and Demultiplexing on Chip

    Science.gov (United States)

    2014-10-31

    curves for various commercially available BCB formulations. ....................................... 81 Figure 134 BCB degree of polymerization as a...function of temperature and time. ................................... 82 Figure 135 SEM image of ultra-thin BCB bonding layer between Si and InP...wafers, obtained using 1:12 BCB : mesitylene solution

  11. Applications of geological labs on chip for CO2 storage issues

    International Nuclear Information System (INIS)

    Morais, Sandy

    2016-01-01

    CO 2 geological storage in deep saline aquifers represents a mediation solution for reducing the anthropogenic CO 2 emissions. Consequently, this kind of storage requires adequate scientific knowledge to evaluate injection scenarios, estimate reservoir capacity and assess leakage risks. In this context, we have developed and used high pressure/high temperature micro-fluidic tools to investigate the different mechanisms associated with CO 2 geological storage in deep saline aquifers. The silicon-Pyrex 2D porous networks (Geological Labs On Chips) can replicate the reservoir p,T conditions (25 ≤ T ≤ 50 C, 50 ≤ p ≤ 10 MPa), geological and topological properties. This thesis manuscript first highlights the strategies developed during this work to fabricate the GLoCs and to access to global characteristics of our porous media such as porosity and permeability, which are later compared to numerical modelling results. The carbon dioxide detection in GLoCs mimicking p,T conditions of geological reservoirs by using the direct integration of optical fiber for IR spectroscopy is presented. I then detail the strategies for following the dissolution of carbonates in GLoCs with X-rays laminography experiments.Then, the manuscript focuses on the use of GLoCs to investigate each CO 2 trapping mechanism at the pore scale. The direct optical visualization and image processing allow us to follow the evolution of the injected CO 2 /aqueous phase within the reservoir, including displacement mechanisms and pore saturation levels. Eventually, I present the ongoing works such as experiments with reactive brines and hydrates formations in porous media [fr

  12. Globally Stable Microresonator Turing Pattern Formation for Coherent High-Power THz Radiation On-Chip

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yang, Shang-Hua; Yu, Mingbin; Kwong, Dim-Lee; Zelevinsky, T.; Jarrahi, Mona; Wong, Chee Wei

    2017-10-01

    In nonlinear microresonators driven by continuous-wave (cw) lasers, Turing patterns have been studied in the formalism of the Lugiato-Lefever equation with emphasis on their high coherence and exceptional robustness against perturbations. Destabilization of Turing patterns and the transition to spatiotemporal chaos, however, limit the available energy carried in the Turing rolls and prevent further harvest of their high coherence and robustness to noise. Here, we report a novel scheme to circumvent such destabilization, by incorporating the effect of local mode hybridizations, and we attain globally stable Turing pattern formation in chip-scale nonlinear oscillators with significantly enlarged parameter space, achieving a record-high power-conversion efficiency of 45% and an elevated peak-to-valley contrast of 100. The stationary Turing pattern is discretely tunable across 430 GHz on a THz carrier, with a fractional frequency sideband nonuniformity measured at 7.3 ×10-14 . We demonstrate the simultaneous microwave and optical coherence of the Turing rolls at different evolution stages through ultrafast optical correlation techniques. The free-running Turing-roll coherence, 9 kHz in 200 ms and 160 kHz in 20 minutes, is transferred onto a plasmonic photomixer for one of the highest-power THz coherent generations at room temperature, with 1.1% optical-to-THz power conversion. Its long-term stability can be further improved by more than 2 orders of magnitude, reaching an Allan deviation of 6 ×10-10 at 100 s, with a simple computer-aided slow feedback control. The demonstrated on-chip coherent high-power Turing-THz system is promising to find applications in astrophysics, medical imaging, and wireless communications.

  13. On-chip generation of high-dimensional entangled quantum states and their coherent control.

    Science.gov (United States)

    Kues, Michael; Reimer, Christian; Roztocki, Piotr; Cortés, Luis Romero; Sciara, Stefania; Wetzel, Benjamin; Zhang, Yanbing; Cino, Alfonso; Chu, Sai T; Little, Brent E; Moss, David J; Caspani, Lucia; Azaña, José; Morandotti, Roberto

    2017-06-28

    Optical quantum states based on entangled photons are essential for solving questions in fundamental physics and are at the heart of quantum information science. Specifically, the realization of high-dimensional states (D-level quantum systems, that is, qudits, with D > 2) and their control are necessary for fundamental investigations of quantum mechanics, for increasing the sensitivity of quantum imaging schemes, for improving the robustness and key rate of quantum communication protocols, for enabling a richer variety of quantum simulations, and for achieving more efficient and error-tolerant quantum computation. Integrated photonics has recently become a leading platform for the compact, cost-efficient, and stable generation and processing of non-classical optical states. However, so far, integrated entangled quantum sources have been limited to qubits (D = 2). Here we demonstrate on-chip generation of entangled qudit states, where the photons are created in a coherent superposition of multiple high-purity frequency modes. In particular, we confirm the realization of a quantum system with at least one hundred dimensions, formed by two entangled qudits with D = 10. Furthermore, using state-of-the-art, yet off-the-shelf telecommunications components, we introduce a coherent manipulation platform with which to control frequency-entangled states, capable of performing deterministic high-dimensional gate operations. We validate this platform by measuring Bell inequality violations and performing quantum state tomography. Our work enables the generation and processing of high-dimensional quantum states in a single spatial mode.

  14. Liquids on-chip: direct storage and release employing micro-perforated vapor barrier films.

    Science.gov (United States)

    Czurratis, Daniel; Beyl, Yvonne; Grimm, Alexander; Brettschneider, Thomas; Zinober, Sven; Lärmer, Franz; Zengerle, Roland

    2015-07-07

    Liquids on-chip describes a reagent storage concept for disposable pressure driven Lab-on-Chip (LoC) devices, which enables liquid storage in reservoirs without additional packaging. On-chip storage of liquids can be considered as one of the major challenges for the commercial break through of polymer-based LoC devices. Especially the ability for long-term storage and reagent release on demand are the most important aspects for a fully developed technology. On-chip storage not only replaces manual pipetting, it creates numerous advantages: fully automated processing, ease of use, reduction of contamination and transportation risks. Previous concepts for on-chip storage are based on liquid packaging solutions (e.g. stick packs, blisters, glass ampoules), which implicate manufacturing complexity and additional pick and place processes. That is why we prefer on-chip storage of liquids directly in reservoirs. The liquids are collected in reservoirs, which are made of high barrier polymers or coated by selected barrier layers. Therefore, commonly used polymers for LoC applications as cyclic olefin polymer (COP) and polycarbonate (PC) were investigated in the context of novel polymer composites. To ensure long-term stability the reservoirs are sealed with a commercially available barrier film by hot embossing. The barrier film is structured by pulsed laser ablation, which installs rated break points without affecting the barrier properties. A flexible membrane is actuated through pneumatic pressure for reagent release on demand. The membrane deflection breaks the barrier film and leads to efficient cleaning of the reservoirs in order to provide the liquids for further processing.

  15. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  16. An on-chip programmable instrumentation microsystem for gastrointestinal telemetry applications.

    Science.gov (United States)

    Wang, Lei; Hammond, Paul; Johannesson, Erik; Tang, Tong Boon; Astaras, Alexandros; Cumming, David R S; Beaumont, Steve P; Murray, Alan F; Cooper, Jonathan M

    2004-01-01

    We have developed an integrated circuit microsystem instrument using a design methodology akin to that for system-on-chip microelectronics. The microsystem is optimised for low-power gastrointestinal telemetry applications and includes mixed-signal sensor circuits, programmable digital system, a feedback clock control loop and RF circuits that were integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3 V CMOS process. Unintended signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes has been minimised. Tests show that the wireless instrument-on-chip worked as intended.

  17. Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

    OpenAIRE

    Hansson, Andreas; Goossens, Kees; Rădulescu, Andrei

    2007-01-01

    Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions introduce message dependencies that affect deadlock properties of the SoC as a whole. Even when NoC and IP dependency graphs are cycle-free in isolation, put together they may stil...

  18. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2008-01-01

    This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long...... on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology....

  19. Advanced Technology for Ultra-Low Power System-on-Chip (SoC)

    Science.gov (United States)

    2017-06-01

    AFRL-RY-WP-TR-2017-0115 ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON-CHIP (SoC) Jason Woo, Weicong Li, and Peng Lu University of California...Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law , no person...September 2015 – 31 March 2017 4. TITLE AND SUBTITLE ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON- CHIP (SoC) 5a. CONTRACT NUMBER FA8650-15-1-7574 5b

  20. On-Chip SDM Switching for Unicast, Multicast and Traffic Grooming in Data Center Networks

    DEFF Research Database (Denmark)

    Kamchevska, Valerija; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    This paper reports on the use of a novel photonic integrated circuit that facilitates multicast and grooming in an optical data center architecture. The circuit allows for on-chip spatial multiplexing and demultiplexing as well as fiber core switching. Using this device, we experimentally verify...... that multicast and/or grooming can be successfully performed along the full range of output ports, for different group size and different power ratio. Moreover, we experimentally demonstrate SDM transmission and 5 Tbit/s switching using the on-chip fiber switch with integrated fan-in/fan-out devices and achieve...

  1. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP

    OpenAIRE

    Mahmood, Adnan; Mohammed, Zaheer Ahmed

    2009-01-01

    Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing tec...

  2. Embedded 3D Graphics Core for FPGA-based System-on-Chip Applications

    DEFF Research Database (Denmark)

    Holten-Lund, Hans Erik

    2005-01-01

    , and the video display which periodically reads from memory to display the final rendered graphics. The graphics core uses internal scratch-pad memory to reduce its external bandwidth requirement, this is achieved by implementing a tile-based rendering algorithm. Reduced external bandwidth means that the power...... such as a VRML viewer. The 3D graphics core is connected to a PLB 64-bit on-chip bus, and can render graphics into an on-chip tile buffer, which is later copied, using bus-master DMA transfers, to the frame-buffer in external DDR SDRAM memory. This memory is shared between the CPU, the 3D graphics core...

  3. Autonomic networking-on-chip bio-inspired specification, development, and verification

    CERN Document Server

    Cong-Vinh, Phan

    2011-01-01

    Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system. The FIRST Book to Assess Research Results, Opportunities, & Trends in ""BioChipNets"" The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent re

  4. Standardized and modular microfluidic platform for fast lab on chip system development

    NARCIS (Netherlands)

    Dekker, Stefan; van den Berg, Albert; Odijk, Mathieu; Lee, Abraham; DeVoe, Don

    2017-01-01

    This paper reports a modular microfluidic system with standardized parts, enabling rapid prototyping of lab on chip systems. Herewith contributing to the technology transfer from academy to industry. The use of standardized parts also makes it possible to design a microfluidic systems in a top down

  5. A Network Traffic Generator Model for Fast Network-on-Chip Simulation

    DEFF Research Database (Denmark)

    Mahadevan, Shankar; Angiolini, Frederico; Storgaard, Michael

    2005-01-01

    For Systems-on-Chip (SoCs) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast...

  6. Technology for On-Chip Qubit Control with Microfabricated Surface Ion Traps

    Energy Technology Data Exchange (ETDEWEB)

    Highstrete, Clark [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Quantum Information Sciences Dept.; Scott, Sean Michael [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). RF/Optoelectronics Dept.; Nordquist, Christopher D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). RF/Optoelectronics Dept.; Sterk, Jonathan David [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Photonic Microsystem Technologies Dept.; Maunz, Peter Lukas Wilhelm [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Photonic Microsystem Technologies Dept.; Tigges, Christopher P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Photonic Microsystem Technologies Dept.; Blain, Matthew Glenn [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Photonic Microsystem Technologies Dept.; Heller, Edwin J. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Microsystems Integration Dept.; Stevens, James E. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). MESAFab Operations 2 Dept.

    2013-11-01

    Trapped atomic ions are a leading physical system for quantum information processing. However, scalability and operational fidelity remain limiting technical issues often associated with optical qubit control. One promising approach is to develop on-chip microwave electronic control of ion qubits based on the atomic hyperfine interaction. This project developed expertise and capabilities at Sandia toward on-chip electronic qubit control in a scalable architecture. The project developed a foundation of laboratory capabilities, including trapping the 171Yb+ hyperfine ion qubit and developing an experimental microwave coherent control capability. Additionally, the project investigated the integration of microwave device elements with surface ion traps utilizing Sandia’s state-of-the-art MEMS microfabrication processing. This effort culminated in a device design for a multi-purpose ion trap experimental platform for investigating on-chip microwave qubit control, laying the groundwork for further funded R&D to develop on-chip microwave qubit control in an architecture that is suitable to engineering development.

  7. Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2010-01-01

    Abstract—This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair

  8. Overview of status and challenges of system testing on chip with embedded DRAMS

    Science.gov (United States)

    Falter, T.; Richter, D.

    2000-05-01

    The combination of logic together with DRAM as a system on chip (SOC) has many advantages for a large variety of computing and network applications. The goal of testing a system is to detect the fabrication caused faults in order to guarantee the defined quality. The increasing size of memories, shrinking dimensions, higher demands on application (frequency and temperature range) and quality cause new problems and higher costs of testing. On the other hand the pressure to serve the market with low cost products forces the test engineer to reduce test costs by reducing test times and using low cost test equipment. Different solutions are discussed in this paper in order to meet these challenges. The variety of test approaches for testing SOC with embedded DRAMs reaches from testing with completely chip external test logic, a simple on-chip test logic up to a full blown built-in self test (BIST) on chip. Which choice is the right one depends on different criteria e.g. memory size, quality demands and application of the product. As an example the modular embedded DRAM core concept from Infineon Technologies is discussed, which includes a dedicated modular test concept based on on-chip integration of a test controller.

  9. A new 2D mesh routing approach for networks on chip Une nouvelle ...

    African Journals Online (AJOL)

    Traditionally, embedded systems and digital electronics technology were confined to computer systems. Today, embedded systems and systems on chip are applied in a wide range of areas such as television, communication systems, radar, military systems, medical instrumentation, and consumer electronics use digital ...

  10. DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

    NARCIS (Netherlands)

    Stefanov, T.; Pimentel, A.; Nikolov, H.; Ha, S.; Teich, J.

    2017-01-01

    The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design

  11. MEMS-based wavelength and orbital angular momentum demultiplexer for on-chip applications

    DEFF Research Database (Denmark)

    Lyubopytov, Vladimir; Porfirev, Alexey P.; Gurbatov, Stanislav O.

    2017-01-01

    Summary form only given. We demonstrate a new tunable MEMS-based WDM&OAM Fabry-Pérot filter for simultaneous wavelength (WDM) and Orbital Angular Momentum (OAM) (de)multiplexing. The WDM&OAM filter is suitable for dense on-chip integration and dedicated for the next generation of optical...

  12. On-chip COMA cache-coherence protocol for microgrids of microthreaded cores

    NARCIS (Netherlands)

    Zhang, L.; Jesshope, C.

    2008-01-01

    This paper describes an on-chip COMA cache coherency protocol to support the microthread model of concurrent program composition. The model gives a sound basis for building multi-core computers as it captures concurrency, abstracts communication and identifies resources, such as processor groups

  13. An integrated fritless column for on-chip capillary electrochromatography with conventional stationary phases

    NARCIS (Netherlands)

    Ceriotti, Laura; De Rooij, Nico F.; Verpoorte, Elisabeth

    2002-01-01

    A new polymer device for use with conventional particulate stationary phases for on-chip, fritless, capillary electrochromatography (CEC) has been realized. The structure includes an injector and a tapered column in which the particles of the stationary phase are retained and stabilized. The chips

  14. On-chip measurement of the Brownian relaxation frequency of magnetic beads using magnetic tunneling junctions

    DEFF Research Database (Denmark)

    Donolato, M.; Sogne, E.; Dalslet, Bjarke Thomas

    2011-01-01

    We demonstrate the detection of the Brownian relaxation frequency of 250 nm diameter magnetic beads using a lab-on-chip platform based on current lines for exciting the beads with alternating magnetic fields and highly sensitive magnetic tunnel junction (MTJ) sensors with a superparamagnetic free...

  15. A low-cost 2D fluorescence detection system for mm sized beads on-chip

    NARCIS (Netherlands)

    Segerink, Loes Irene; Koster, Maarten J.; Sprenkels, A.J.; van den Berg, Albert

    2012-01-01

    In this paper we describe a compact fluorescence detection system for on-chip analysis of beads, comprising a low-cost optical HD-DVD pickup. The complete system consists of a fluorescence detection unit, a control unit and a microfluidic chip containing microchannels and optical markers. With these

  16. Versatile laser microfabrication techniques for lab-on-chip devices in ...

    Indian Academy of Sciences (India)

    2014-02-06

    Feb 6, 2014 ... The technology for the development of fully integrated lab-on-chip devices is still at a nascent stage considering the complexity of integration, the various effects of the micro domain that requires one to revisit one's intuitive perceptions of the physical world, and the multidisciplinary nature of the topic.

  17. An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, A.; Goossens, Kees

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  18. Low-Power, High-Speed Transceivers for Network-on-Chip Communication

    NARCIS (Netherlands)

    Schinkel, Daniel; Mensink, E.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present

  19. On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

    Science.gov (United States)

    Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

    2017-08-30

    Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

  20. A Metaheuristic Scheduler for Time Division Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Sparsø, Jens; Pedersen, Mark Ruvald

    2014-01-01

    This paper presents a metaheuristic scheduler for inter-processor communication in multi-processor platforms using time division multiplexed (TDM) networks on chip (NOC). Compared to previous works, the scheduler handles a broader and more general class of platforms. Another contribution, which has...

  1. On-chip tunable long-period grating devices based on liquid crystal photonic bandgap fibers

    DEFF Research Database (Denmark)

    Wei, Lei; Weirich, Johannes; Alkeskjold, Thomas Tanggaard

    2009-01-01

    We design and fabricate an on-chip tunable long-period grating device by integrating a liquid crystal photonic bandgap fiber on silicon structures. The transmission axis of the device can be electrically rotated in steps of 45° as well as switched on and off with the response time...

  2. Waveguide filter-based on-chip differentiator for microwave photonic signal processing

    NARCIS (Netherlands)

    Taddei, Caterina; Nguyen, T.H.Yen; Zhuang, L.; Hoekman, M.; Leinse, Arne; Heideman, Rene; van Dijk, Paul; Roeloffzen, C.G.H.

    2013-01-01

    We propose and demonstrate a waveguide filterbased on-chip differentiator for microwave photonic signal processing. The system principle allows the operation of arbitrary-order differentiation. The realized device is constructed using the basic building blocks of photonic integrated circuits, and

  3. On-chip tunable long-period gratings in liquid crystal infiltrated photonic crystal fibers

    DEFF Research Database (Denmark)

    Wei, Lei; Weirich, Johannes; Alkeskjold, Thomas Tanggaard

    2009-01-01

    An on-chip tunable long-period grating device in a liquid crystal infiltrated photonic crystal fiber is experimentally demonstrated. The depth and position of the notch are tuned electrically and thermally. The transmission axis can be electrically controlled as well as switched on and off....

  4. An area-efficient network interface for a TDM-based Network-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens; Kasapaki, Evangelia; Schoeberl, Martin

    2013-01-01

    Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The functionality of a NI is to bridge between the read/write transaction interfaces used by the cores and the packet-streaming interface...

  5. Two-Dimensional Programmable Manipulation of Magnetic Nanoparticles on-Chip

    DEFF Research Database (Denmark)

    Sarella, Anandakumar; Torti, Andrea; Donolato, Marco

    2014-01-01

    A novel device is designed for on-chip selective trap and two-dimensional remote manipulation of single and multiple fluid-borne magnetic particles using field controlled magnetic domain walls in circular nanostructures. The combination of different ring-shaped nanostructures and field sequences ...

  6. Versatile laser microfabrication techniques for lab-on-chip devices in ...

    Indian Academy of Sciences (India)

    2014-02-06

    Feb 6, 2014 ... to fabricate microchips for lab-on-chip (LOC) applications in general and uranium analysis in water samples as a specific ... Point-of-care (POC) biomedical devices need to be fabricated using a cost. Pramana – J. ... the fabrication of microfluidic chips to be used in uranium detection in water samples. 2.

  7. Self-Powered Functional Device Using On-Chip Power Generation

    KAUST Repository

    Hussain, Muhammad Mustafa

    2012-01-26

    An apparatus, system, and method for a self-powered device using on-chip power generation. In some embodiments, the apparatus includes a substrate, a power generation module on the substrate, and a power storage module on the substrate. The power generation module may include a thermoelectric generator made of bismuth telluride.

  8. Integration of a Pulse Generator on Chip Into a Compact Ultrawideband Antenna

    NARCIS (Netherlands)

    Vorobyov, A.V.; Bagga, S.; Yarovoy, A.G.; Haddad, S.A.P.; Serdijn, W.A.; Long, J.R.; Irahhauten, Z.; Ligthart, L.P.

    For impulse radio ultrawideband communications an “antenna plus generator” system is co-designed and an on chip generator is integrated into the antenna. This approach does away with the need for intermediate transmission lines conventionally placed between an RF device/generator and an antenna and

  9. CoMPSoC: A Template for Composable and Predictable Multi-Processor System on Chips

    NARCIS (Netherlands)

    Hansson, A.; Goossens, Kees; Bekooij, Marco Jan Gerrit; Huisken, Jos

    2009-01-01

    A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as

  10. Nanotechnology and the Developing World: Lab-on-Chip Technology for Health and Environmental Applications

    Science.gov (United States)

    Mehta, Michael D.

    2008-01-01

    This article argues that advances in nanotechnology in general, and lab-on-chip technology in particular, have the potential to benefit the developing world in its quest to control risks to human health and the environment. Based on the "risk society" thesis of Ulrich Beck, it is argued that the developed world must realign its science and…

  11. Simple and stable transendothelial electrical resistance measurement in organs-on-chips

    NARCIS (Netherlands)

    van der Helm, Marieke Willemijn; Odijk, Mathieu; Frimat, Jean-Philippe; Eijkel, Jan C.T.; van den Berg, Albert; Segerink, Loes Irene

    2015-01-01

    Measuring transendothelial electrical resistance (TEER) is a popular way to monitor cellular barrier tightness in organs-on-chips. However, in these devices integrated electrodes often block sight on the cells and the measured part often includes fluid-filled channels with variable resistance.

  12. Aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services.

    NARCIS (Netherlands)

    Hansson, A.; Subburaman, Mahesh; Goossens, Kees

    To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput

  13. An integrated lab-on-chip for rapid identification and simultaneous differentiation of tropical pathogens.

    Science.gov (United States)

    Tan, Jeslin J L; Capozzoli, Monica; Sato, Mitsuharu; Watthanaworawit, Wanitda; Ling, Clare L; Mauduit, Marjorie; Malleret, Benoît; Grüner, Anne-Charlotte; Tan, Rosemary; Nosten, François H; Snounou, Georges; Rénia, Laurent; Ng, Lisa F P

    2014-01-01

    Tropical pathogens often cause febrile illnesses in humans and are responsible for considerable morbidity and mortality. The similarities in clinical symptoms provoked by these pathogens make diagnosis difficult. Thus, early, rapid and accurate diagnosis will be crucial in patient management and in the control of these diseases. In this study, a microfluidic lab-on-chip integrating multiplex molecular amplification and DNA microarray hybridization was developed for simultaneous detection and species differentiation of 26 globally important tropical pathogens. The analytical performance of the lab-on-chip for each pathogen ranged from 102 to 103 DNA or RNA copies. Assay performance was further verified with human whole blood spiked with Plasmodium falciparum and Chikungunya virus that yielded a range of detection from 200 to 4×105 parasites, and from 250 to 4×107 PFU respectively. This lab-on-chip was subsequently assessed and evaluated using 170 retrospective patient specimens in Singapore and Thailand. The lab-on-chip had a detection sensitivity of 83.1% and a specificity of 100% for P. falciparum; a sensitivity of 91.3% and a specificity of 99.3% for P. vivax; a positive 90.0% agreement and a specificity of 100% for Chikungunya virus; and a positive 85.0% agreement and a specificity of 100% for Dengue virus serotype 3 with reference methods conducted on the samples. Results suggested the practicality of an amplification microarray-based approach in a field setting for high-throughput detection and identification of tropical pathogens.

  14. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate

  15. Organs-on-Chips in Drug Development: The Importance of Involving Stakeholders in Early Health Technology Assessment

    NARCIS (Netherlands)

    Middelkamp, Heleen H.T.; van der Meer, Andries Dirk; Hummel, J. Marjan; Stamatialis, Dimitrios; Mummery, Christine Lindsay; Passier, Petrus Christianus Johannes Josephus; IJzerman, Maarten Joost

    2016-01-01

    Organs-on-chips are three-dimensional, microfluidic cell culture systems that simulate the function of tissues and organ subunits. Organ-on-chip systems are expected to contribute to drug candidate screening and the reduction of animal tests in preclinical drug development and may increase

  16. Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays

    Science.gov (United States)

    Pain, Bedabrata

    The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also suppresses spatial noise that results from response non-uniformities of photo-detectors, leading to background limited infrared detector readout performance. Two new, low-power, compact, current memory circuits, optimized for operation at ultra-low current levels required in infrared-detection, are presented. The first one is a self-cascading current memory that increases the output impedance, and the second one is a novel, switch feed-through reducing current memory, implemented using error-current feedback. This circuit can operate with a residual absolute -error of less than 0.1%. The storage-time of the memory is long enough to also find applications in neural network circuits. In addition, a voltage-mode, accurate, low-offset, low-power, high-uniformity, random-access sample-and-hold cell, implemented using a CCD with feedback, is also presented for use in background-suppression and neural network applications. A new, low noise, ultra-low level signal readout technique, implemented by individually counting photo-electrons within the detection pixel, is presented. The output of each unit-cell is a digital word corresponding to the intensity of the photon flux, and the readout is noise free. This technique requires the use of unit-cell amplifiers that feature ultra-high-gain, low-power, self-biasing capability and noise in sub-electron levels. Both single-input and differential-input implementations of such amplifiers are investigated. A noise analysis technique is presented for analyzing sampled

  17. Multi-angle lensless digital holography for depth resolved imaging on a chip

    Science.gov (United States)

    Su, Ting-Wei; Isikman, Serhan O.; Bishara, Waheb; Tseng, Derek; Erlinger, Anthony; Ozcan, Aydogan

    2010-01-01

    A multi-angle lensfree holographic imaging platform that can accurately characterize both the axial and lateral positions of cells located within multi-layered micro-channels is introduced. In this platform, lensfree digital holograms of the micro-objects on the chip are recorded at different illumination angles using partially coherent illumination. These digital holograms start to shift laterally on the sensor plane as the illumination angle of the source is tilted. Since the exact amount of this lateral shift of each object hologram can be calculated with an accuracy that beats the diffraction limit of light, the height of each cell from the substrate can be determined over a large field of view without the use of any lenses. We demonstrate the proof of concept of this multi-angle lensless imaging platform by using light emitting diodes to characterize various sized microparticles located on a chip with sub-micron axial and lateral localization over ~60 mm2 field of view. Furthermore, we successfully apply this lensless imaging approach to simultaneously characterize blood samples located at multi-layered micro-channels in terms of the counts, individual thicknesses and the volumes of the cells at each layer. Because this platform does not require any lenses, lasers or other bulky optical/mechanical components, it provides a compact and high-throughput alternative to conventional approaches for cytometry and diagnostics applications involving lab on a chip systems. PMID:20588819

  18. Preservation of Cell Structure, Metabolism, and Biotransformation Activity of Liver-On-Chip Organ Models by Hypothermic Storage.

    Science.gov (United States)

    Gröger, Marko; Dinger, Julia; Kiehntopf, Michael; Peters, Frank T; Rauen, Ursula; Mosig, Alexander S

    2018-01-01

    The liver is a central organ in the metabolization of nutrition, endogenous and exogenous substances, and xenobiotic drugs. The emerging organ-on-chip technology has paved the way to model essential liver functions as well as certain aspects of liver disease in vitro in liver-on-chip models. However, a broader use of this technology in biomedical research is limited by a lack of protocols that enable the short-term preservation of preassembled liver-on-chip models for stocking or delivery to researchers outside the bioengineering community. For the first time, this study tested the ability of hypothermic storage of liver-on-chip models to preserve cell viability, tissue morphology, metabolism and biotransformation activity. In a systematic study with different preservation solutions, liver-on-chip function can be preserved for up to 2 d using a derivative of the tissue preservation solution TiProtec, containing high chloride ion concentrations and the iron chelators LK614 and deferoxamine, supplemented with polyethylene glycol (PEG). Hypothermic storage in this solution represents a promising method to preserve liver-on-chip function for at least 2 d and allows an easier access to liver-on-chip technology and its versatile and flexible use in biomedical research. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. On-chip microlasers for biomolecular detection via highly localized deposition of a multifunctional phospholipid ink.

    Science.gov (United States)

    Bog, Uwe; Laue, Thomas; Grossmann, Tobias; Beck, Torsten; Wienhold, Tobias; Richter, Benjamin; Hirtz, Michael; Fuchs, Harald; Kalt, Heinz; Mappes, Timo

    2013-07-21

    We report on a novel approach to realize on-chip microlasers, by applying highly localized and material-saving surface functionalization of passive photonic whispering gallery mode microresonators. We apply dip-pen nanolithography on a true three-dimensional structure. We coat solely the light-guiding circumference of pre-fabricated poly(methyl methacrylate) resonators with a multifunctional molecular ink. The functionalization is performed in one single fabrication step and simultaneously provides optical gain as well as molecular binding selectivity. This allows for a direct and flexible realization of on-chip microlasers, which can be utilized as biosensors in optofluidic lab-on-a-chip applications. In a proof-of-concept we show how this highly localized molecule deposition suffices for low-threshold lasing in air and water, and demonstrate the capability of the ink-lasers as biosensors in a biotin-streptavidin binding experiment.

  20. High frequency acoustic on-chip integration for particle characterization and manipulation in microfluidics

    Science.gov (United States)

    Li, Sizhe; Carlier, Julien; Toubal, Malika; Liu, Huiqin; Campistron, Pierre; Callens, Dorothée; Nassar, Georges; Nongaillard, Bertrand; Guo, Shishang

    2017-10-01

    This letter presents a microfluidic device that integrates high frequency (650 MHz) bulk acoustic waves for the realization of particle handling on-chip. The core structure of the microfluidic chip is made up of a confocal lens, a vertical reflection wall, and a ZnO film transducer coupled with a silicon substrate for exciting acoustic beams. The excited acoustic waves propagate in bulk silicon and are then guided by a 45° silicon mirror into the suspensions in the microchannel; afterwards, the acoustic energy is focused on particles by the confocal lens and reflected by a reflection wall. Parts of the reflected acoustic energy backtrack into the transducer, and acoustic attenuation measurements are characterized for particle detection. Meanwhile, a strong acoustic streaming phenomenon can be seen around the reflection wall, which is used to implement particle manipulation. This platform opens a frontier for on-chip integration of high sensitivity acoustic characterization and localized acoustic manipulation in microfluidics.

  1. Widely Tunable On-Chip Microwave Circulator for Superconducting Quantum Circuits

    Directory of Open Access Journals (Sweden)

    Benjamin J. Chapman

    2017-11-01

    Full Text Available We report on the design and performance of an on-chip microwave circulator with a widely (GHz tunable operation frequency. Nonreciprocity is created with a combination of frequency conversion and delay, and requires neither permanent magnets nor microwave bias tones, allowing on-chip integration with other superconducting circuits without the need for high-bandwidth control lines. Isolation in the device exceeds 20 dB over a bandwidth of tens of MHz, and its insertion loss is small, reaching as low as 0.9 dB at select operation frequencies. Furthermore, the device is linear with respect to input power for signal powers up to hundreds of fW (≈10^{3} circulating photons, and the direction of circulation can be dynamically reconfigured. We demonstrate its operation at a selection of frequencies between 4 and 6 GHz.

  2. Core-shell magnetic nanoparticles for on-chip RF inductors

    KAUST Repository

    Koh, Kisik

    2013-01-01

    FeNi3 based core-shell magnetic nanoparticles are demonstrated as the magnetic core material for on-chip, radio frequency (RF) inductors. FeNi3 nanoparticles with 50-150 nm in diameter with 15-20 nm-thick SiO2 coating are chemically synthesized and deposited on a planar inductor as the magnetic core to enhance both inductance (L) and quality factor (Q) of the inductor. Experimentally, the ferromagnetic resonant frequency of the on-chip inductors based on FeNi3 core-shell nanoparticles has been shown to be over several GHz. A post-CMOS process has been developed to integrate the magnetic nanoparticles to a planar inductor and inductance enhancements up to 50% of the original magnitude with slightly enhanced Q-factor up to 1 GHz have been achieved. © 2013 IEEE.

  3. Soft error evaluation and vulnerability analysis in Xilinx Zynq-7010 system-on chip

    Energy Technology Data Exchange (ETDEWEB)

    Du, Xuecheng; He, Chaohui; Liu, Shuhuan, E-mail: liushuhuan@mail.xjtu.edu.cn; Zhang, Yao; Li, Yonghong; Xiong, Ceng; Tan, Pengkang

    2016-09-21

    Radiation-induced soft errors are an increasingly important threat to the reliability of modern electronic systems. In order to evaluate system-on chip's reliability and soft error, the fault tree analysis method was used in this work. The system fault tree was constructed based on Xilinx Zynq-7010 All Programmable SoC. Moreover, the soft error rates of different components in Zynq-7010 SoC were tested by americium-241 alpha radiation source. Furthermore, some parameters that used to evaluate the system's reliability and safety were calculated using Isograph Reliability Workbench 11.0, such as failure rate, unavailability and mean time to failure (MTTF). According to fault tree analysis for system-on chip, the critical blocks and system reliability were evaluated through the qualitative and quantitative analysis.

  4. Debugging systems-on-chip communication-centric and abstraction-based techniques

    CERN Document Server

    Vermeulen, Bart

    2014-01-01

    This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly.  Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors.  The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug ...

  5. Modeling, analysis and optimization of network-on-chip communication architectures

    CERN Document Server

    Ogras, Umit Y

    2013-01-01

    Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

  6. On-chip high-voltage generator design design methodology for charge pumps

    CERN Document Server

    Tanzawa, Toru

    2016-01-01

    This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

  7. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...... to the transaction-level model. The thesis, as a whole makes contributions by describing a design methodology for networked multiprocessor embedded systems at three layers of abstraction from system-level through transaction-level to the cycle accurate level as well as demonstrating it practically by implementing...

  8. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  9. A survey of research and practices of network-on-chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar

    2006-01-01

    . This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling......The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures...... are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative....

  10. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  11. On-chip signal amplification of magnetic bead-based immunoassay by aviating magnetic bead chains.

    Science.gov (United States)

    Jalal, Uddin M; Jin, Gyeong Jun; Eom, Kyu Shik; Kim, Min Ho; Shim, Joon S

    2017-11-06

    In this work, a Lab-on-a-Chip (LOC) platform is used to electromagnetically actuate magnetic bead chains for an enhanced immunoassay. Custom-made electromagnets generate a magnetic field to form, rotate, lift and lower the magnetic bead chains (MBCs). The cost-effective, disposable LOC platform was made with a polymer substrate and an on-chip electrochemical sensor patterned via the screen-printing process. The movement of the MBCs is controlled to improve the electrochemical signal up to 230% when detecting beta-type human chorionic gonadotropin (β-hCG). Thus, the proposed on-chip MBC-based immunoassay is applicable for rapid, qualitative electrochemical point-of-care (POC) analysis. Copyright © 2017 Elsevier B.V. All rights reserved.

  12. Lab-on-chip for liquid biopsy (LoC-LB) based on dielectrophoresis.

    Science.gov (United States)

    Mathew, Bobby; Alazzam, Anas; Khashan, Saud; Abutayeh, Mohammad

    2017-03-01

    This short communication presents the proof-of-concept of a novel dielectrophoretic lab-on-chip for identifying/separating circulating tumor cells for purposes of liquid biopsy. The device consists of a polydimethylsiloxane layer, containing a microchannel, bonded on a glass substrate that holds two sets of planar interdigitated transducer electrodes. The lab-on-chip is operated at a frequency that enables dielectrophoretic force to sort cells, based on type, along the lateral direction. The operating frequency ensures attraction force toward the electrodes on cancer cells and repulsion force toward the center of the microchannel on other cells. Initial tests for demonstrating proof-of-concept have successfully identified/separated green fluorescent protein-labelled MDA-MB-231 breast cancer cells from a mixture of the same and regular blood cells suspended in low conductivity sucrose/dextrose medium. Copyright © 2016 Elsevier B.V. All rights reserved.

  13. On-chip nanofluidic integration of acoustic sensors towards high Q in liquid

    Science.gov (United States)

    Liang, Ji; Liu, Zifeng; Zhang, Hongxiang; Liu, Bohua; Zhang, Menglun; Zhang, Hao; Pang, Wei

    2017-11-01

    This paper reports an on-chip acoustic sensor comprising a piston-mode film bulk acoustic resonator and a monolithically integrated nanochannel. The resonator with the channel exhibits a resonance frequency (f) of 2.5 GHz and a quality (Q) factor of 436 in deionized water. The f × Q product is as high as 1.1 × 1012, which is the highest among all the acoustic wave sensors in the liquid phase. The sensor consumes 2 pl liquid volume and thus greatly saves the precious assays in biomedical testing. The Q factor is investigated, and real-time viscosity tests of glucose solution are demonstrated. The highly miniaturized and integrated sensor is capable to be arrayed with readout-circuitry, which opens an avenue for portable applications and lab-on-chip systems.

  14. Integrated Magneto-Optical Devices for On-Chip Photonic Systems

    Science.gov (United States)

    2017-09-01

    AFRL-RY-WP-TR-2017-0164 INTEGRATED MAGNETO-OPTICAL DEVICES FOR ON-CHIP PHOTONIC SYSTEMS Caroline Ross and Juejun Hu Massachusetts Institute of...Technology SEPTEMBER 2017 Final Report Approved for public release; distribution is unlimited. See additional restrictions described on inside pages STINFO...any patented invention that may relate to them. This report is the result of contracted fundamental research deemed exempt from public affairs

  15. On-Chip Manipulation of Protein-Coated Magnetic Beads via Domain-Wall Conduits

    DEFF Research Database (Denmark)

    Donolato, Marco; Vavassori, Paolo; Gobbi, Marco

    2010-01-01

    Geometrically constrained magnetic domain walls (DWs) in magnetic nanowires can be manipulated at the nanometer scale. The inhomogeneous magnetic stray field generated by a DW can capture a magnetic nanoparticle in solution. On-chip nanomanipulation of individual magnetic beads coated with proteins...... is demonstrated through the motion of geometrically constrained DWs in specially designed magnetic nanoconduits fully integrated in a lab-on-a-chip platform....

  16. Slow-light enhanced sensing with an on-chip Fano system (Conference Presentation)

    Science.gov (United States)

    Bera, Arijit; Kuittinen, Markku; Honkanen, Seppo; Roussey, Matthieu

    2017-02-01

    Integrated silicon photonics promises efficient on-chip solutions for chemical and bio-molecule sensing for faster and reliable disease diagnostics. By integrating a sensor with a light source and a detector, a compact lab-on-chip sensing device is possible to realize. To increase the sensing efficiency, slot waveguide geometry is preferable due to the high confinement of the mode within the cover material. When two different light-paths in a structure interfere with each other, causing the superposition of a Lorenzian response with the background radiation continuum, a Fano lineshape occurs. This sharp resonance leads to a superior refractive index sensing capability. To develop a compact on-chip Fano-resonant platform for chemical sensing, we used a merged photonic crystal - slot waveguide (MPCSW) structure as the basic building block. It contains slot waveguides merged with Bragg gratings, formed by periodic patterning of the rails. A defect between the two Bragg grating sections forms a resonant cavity. In addition to the enhancement due to the confinement of light in the slot waveguide, the highly dispersive nature of the Bragg grating leads to slow light effect at the resonance. Three MPCSW structures are parallel-coupled to form an on-chip Fano system. By changing the refractive index of the cover material, we found a sensitivity as high as 775 nm/RIU. Moreover, the group index at the resonance of our Fano system is as high as ng = 500, due to the effect of slow light. We obtain vast increase in the refractive index sensitivity of the device.

  17. An integrated lab-on-chip for rapid identification and simultaneous differentiation of tropical pathogens.

    Directory of Open Access Journals (Sweden)

    Jeslin J L Tan

    Full Text Available Tropical pathogens often cause febrile illnesses in humans and are responsible for considerable morbidity and mortality. The similarities in clinical symptoms provoked by these pathogens make diagnosis difficult. Thus, early, rapid and accurate diagnosis will be crucial in patient management and in the control of these diseases. In this study, a microfluidic lab-on-chip integrating multiplex molecular amplification and DNA microarray hybridization was developed for simultaneous detection and species differentiation of 26 globally important tropical pathogens. The analytical performance of the lab-on-chip for each pathogen ranged from 102 to 103 DNA or RNA copies. Assay performance was further verified with human whole blood spiked with Plasmodium falciparum and Chikungunya virus that yielded a range of detection from 200 to 4×105 parasites, and from 250 to 4×107 PFU respectively. This lab-on-chip was subsequently assessed and evaluated using 170 retrospective patient specimens in Singapore and Thailand. The lab-on-chip had a detection sensitivity of 83.1% and a specificity of 100% for P. falciparum; a sensitivity of 91.3% and a specificity of 99.3% for P. vivax; a positive 90.0% agreement and a specificity of 100% for Chikungunya virus; and a positive 85.0% agreement and a specificity of 100% for Dengue virus serotype 3 with reference methods conducted on the samples. Results suggested the practicality of an amplification microarray-based approach in a field setting for high-throughput detection and identification of tropical pathogens.

  18. Active 2D materials for on-chip nanophotonics and quantum optics

    Energy Technology Data Exchange (ETDEWEB)

    Shiue, Ren-Jye; Efetov, Dmitri K.; Grosso, Gabriele; Peng, Cheng; Fong, Kin Chung; Englund, Dirk

    2017-01-01

    Abstract

    Two-dimensional materials have emerged as promising candidates to augment existing optical networks for metrology, sensing, and telecommunication, both in the classical and quantum mechanical regimes. Here, we review the development of several on-chip photonic components ranging from electro-optic modulators, photodetectors, bolometers, and light sources that are essential building blocks for a fully integrated nanophotonic and quantum photonic circuit.

  19. Automated fabrication of photopatterned gelatin hydrogels for organ-on-chips applications.

    Science.gov (United States)

    Nawroth, Janna C; Scudder, Lisa L; Halvorson, Ryan T; Tresback, Jason; Ferrier, John P; Sheehy, Sean P; Cho, Alex; Kannan, Suraj; Sunyovszki, Ilona; Goss, Josue A; Campbell, Patrick H; Parker, Kevin Kit

    2018-01-16

    Organ-on-chip platforms aim to improve preclinical models for organ-level responses to novel drug compounds. Heart-on-a-chip assays in particular require tissue engineering techniques that rely on labor-intensive photolithographic fabrication or resolution-limited 3D printing of micropatterned substrates, which limits turnover and flexibility of prototyping. We present a rapid and automated method for large scale on-demand micropatterning of gelatin hydrogels for organ-on-chip applications using a novel biocompatible laser-etching approach. Fast and automated micropatterning is achieved via photosensitization of gelatin using riboflavin-5'phosphate followed by UV laser-mediated photoablation of the gel surface in user-defined patterns only limited by the resolution of the 15 μm wide laser focal point. Using this photopatterning approach, we generated microscale surface groove and pillar structures with feature dimensions on the order of 10-30 μm. The standard deviation of feature height was 0.3 μm, demonstrating robustness and reproducibility. Importantly, the UV-patterning process is non-destructive and does not alter gelatin micromechanical properties. Furthermore, as a quality control step, UV-patterned heart chip substrates were seeded with rat or human cardiac myocytes, and we verified that the resulting cardiac tissues achieved structural organization, contractile function, and long-term viability comparable to manually patterned gelatin substrates. Start-to-finish, UV-patterning shortened the time required to design and manufacture micropatterned gelatin substrates for heart-on-chip applications by up to 60% compared to traditional lithography-based approaches, providing an important technological advance enroute to automated and continuous manufacturing of organ-on-chips.

  20. Multifunctional System-on-Glass for Lab-on-Chip applications.

    Science.gov (United States)

    Petrucci, G; Caputo, D; Lovecchio, N; Costantini, F; Legnini, I; Bozzoni, I; Nascetti, A; de Cesare, G

    2017-07-15

    Lab-on-Chip are miniaturized systems able to perform biomolecular analysis in shorter time and with lower reagent consumption than a standard laboratory. Their miniaturization interferes with the multiple functions that the biochemical procedures require. In order to address this issue, our paper presents, for the first time, the integration on a single glass substrate of different thin film technologies in order to develop a multifunctional platform suitable for on-chip thermal treatments and on-chip detection of biomolecules. The proposed System on-Glass hosts thin metal films acting as heating sources; hydrogenated amorphous silicon diodes acting both as temperature sensors to monitor the temperature distribution and photosensors for the on-chip detection and a ground plane ensuring that the heater operation does not affect the photodiode currents. The sequence of the technological steps, the deposition temperatures of the thin films and the parameters of the photolithographic processes have been optimized in order to overcome all the issues of the technological integration. The device has been designed, fabricated and tested for the implementation of DNA amplification through the Polymerase Chain Reaction (PCR) with thermal cycling among three different temperatures on a single site. The glass has been connected to an electronic system that drives the heaters and controls the temperature and light sensors. It has been optically and thermally coupled with another glass hosting a microfluidic network made in polydimethylsiloxane that includes thermally actuated microvalves and a PCR process chamber. The successful DNA amplification has been verified off-chip by using a standard fluorometer. Copyright © 2016 Elsevier B.V. All rights reserved.

  1. Methods for Trustworthy Design of On-Chip Bus Interconnect for General-Purpose Processors

    Science.gov (United States)

    2012-03-01

    Clock CTL Control CPU Central Processing Unit DCR Device Control Register DDR Double Data Rate DES Data Encryption Standard DIFT Dynamic...Encryption and Integrity Checking Engine PLB Processor Local Bus RAM Random Access Memory RMW Read-Modify-Write ROM Read Only Memory RSA Rivest...Figure 11 depicts the standard AMBA version 3.0 topology [11]. Figure 11. AMBA architecture (From [11]). Timer High-bandwidth on-chip RAM B R I

  2. Advances in piezoelectric thin films for acoustic biosensors, acoustofluidics and lab-on-chip applications

    OpenAIRE

    Fu, Yong Qing; Luo, Jack; Nguyen, Nam-Trung; Walton, Anthony; Flewitt, Andrew; Zu, Xiao-Tao; Li, Yifan; McHale, Glen; Matthews, Allan; Iborra, Enrique; Du, Hejun; Milne, William

    2017-01-01

    Recently, piezoelectric thin films including zinc oxide (ZnO) and aluminium nitride (AlN) have found a broad range of lab-on-chip applications such as biosensing, particle/cell concentrating, sorting/patterning, pumping, mixing, nebulisation and jetting. Integrated acoustic wave sensing/microfluidic devices have been fabricated by depositing these piezoelectric films onto a number of substrates such as silicon, ceramics, diamond, quartz, glass, and more recently also polymer, metallic foils a...

  3. Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

    OpenAIRE

    Teuscher, Christof

    2007-01-01

    Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up se...

  4. Legal Protection on IP Cores for System-on-Chip Designs

    Science.gov (United States)

    Kinoshita, Takahiko

    The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

  5. On-chip photonic memory elements employing phase-change materials.

    Science.gov (United States)

    Rios, Carlos; Hosseini, Peiman; Wright, C David; Bhaskaran, Harish; Pernice, Wolfram H P

    2014-03-05

    Phase-change materials integrated into nanophotonic circuits provide a flexible way to realize tunable optical components. Relying on the enormous refractive-index contrast between the amorphous and crystalline states, such materials are promising candidates for on-chip photonic memories. Nonvolatile memory operation employing arrays of microring resonators is demonstrated as a route toward all-photonic chipscale information processing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Blood cleaner on-chip design for artificial human kidney manipulation

    Directory of Open Access Journals (Sweden)

    Suwanpayak N

    2011-05-01

    Full Text Available N Suwanpayak1, MA Jalil2, MS Aziz3, FD Ismail3, J Ali3, PP Yupapin11Nanoscale Science and Engineering Research Alliance (N'SERA, Advanced Research Center for Photonics, Faculty of Science, King Mongkut's Institute of Technology, Ladkrabang, Bangkok, Thailand; 2Ibnu Sina Institute of Fundamental Science Studies (IIS, 3Institute of Advanced Photonics Science, Nanotechnology Research Alliance, Universiti Teknologi Malaysia, Johor Bahru, MalaysiaAbstract: A novel design of a blood cleaner on-chip using an optical waveguide known as a PANDA ring resonator is proposed. By controlling some suitable parameters, the optical vortices (gradient optical fields/wells can be generated and used to form the trapping tools in the same way as optical tweezers. In operation, the trapping force is formed by the combination between the gradient field and scattering photons by using the intense optical vortices generated within the PANDA ring resonator. This can be used for blood waste trapping and moves dynamically within the blood cleaner on-chip system (artificial kidney, and is performed within the wavelength routers. Finally, the blood quality test is exploited by the external probe before sending to the destination. The advantage of the proposed kidney on-chip system is that the unwanted substances can be trapped and filtered from the artificial kidney, which can be available for blood cleaning applications.Keywords: optical trapping, blood dialysis, blood cleaner, human kidney manipulation

  7. On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

    Science.gov (United States)

    Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

    2018-04-01

    The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

  8. Micro-opto-electro-mechanical devices and on-chip optical processing

    Science.gov (United States)

    Motamedi, M. Edward; Wu, Ming C.; Pister, Kristofer S.

    1997-05-01

    Micro-optical components, such as diffractive and refractive microlenses, micromirrors, beamsplitters, and beam combiners, have recently received considerable attention in the optics R&D centers and finally in the manufacturing community. This achievement is due to micro-electro- mechanical (MEM) technology that has demonstrated major improvements in overall performance and cost of optical systems while offering the possibility of relatively rapid transition to products for military, industrial, and consumer markets. Because of these technology advances, an industrial infrastructure is rapidly becoming established to combine micro-optical components and MEM-based microactuators for on-chip optical processing. Optical systems that once were considered to be impractical due to the limitations of bulk optics can now easily be designed and fabricated with all required optical paths, signal conditioning, and electronic controls integrated on a single chip. On-chip optical processing will enhance the performance of devices such as focal-plane optical concentrators, smart actuators, color separators, beam shapers, fiber data distribution interface (FDDI) switches, digital micromirror devices (DMDs), and miniature optical scanners. We review advances in micro-optical components developed at the Rockwell Science Center. We also review the potential of on-chip optical processing and the recent achievement of free-space integrated optics and micro- optical bench components developed at UCLA, and DMDs developed at Texas Instruments.

  9. An on-chip, multichannel droplet sorter using standing surface acoustic waves (SSAW)

    Science.gov (United States)

    Li, Sixing; Ding, Xiaoyun; Guo, Feng; Chen, Yuchao; Lapsley, Michael Ian; Lin, Sz-Chin Steven; Wang, Lin; McCoy, J. Philip; Cameron, Craig E.; Huang, Tony Jun

    2014-01-01

    The emerging field of droplet microfluidics requires effective on-chip handling and sorting of droplets. In this work, we demonstrate a microfluidic device that is capable of sorting picoliter water-in-oil droplets into multiple outputs using standing surface acoustic waves (SSAW). This device integrates a single-layer microfluidic channel with interdigital transducers (IDTs) to achieve on-chip droplet generation and sorting. Within the SSAW field, water-in-oil droplets experience an acoustic radiation force and are pushed towards the acoustic pressure node. As a result, by tuning the frequency of the SSAW excitation, the position of the pressure nodes can be changed and droplets can be sorted to different outlets at rates up to 222 droplets s−1. With its advantages in simplicity, controllability, versatility, non-invasiveness, and capability to be integrated with other on-chip components such as droplet manipulation and optical detection units, the technique presented here could be valuable for the development of droplet-based micro total analysis systems (μTAS). PMID:23647057

  10. An on-chip, multichannel droplet sorter using standing surface acoustic waves.

    Science.gov (United States)

    Li, Sixing; Ding, Xiaoyun; Guo, Feng; Chen, Yuchao; Lapsley, Michael Ian; Lin, Sz-Chin Steven; Wang, Lin; McCoy, J Philip; Cameron, Craig E; Huang, Tony Jun

    2013-06-04

    The emerging field of droplet microfluidics requires effective on-chip handling and sorting of droplets. In this work, we demonstrate a microfluidic device that is capable of sorting picoliter water-in-oil droplets into multiple outputs using standing surface acoustic waves (SSAW). This device integrates a single-layer microfluidic channel with interdigital transducers (IDTs) to achieve on-chip droplet generation and sorting. Within the SSAW field, water-in-oil droplets experience an acoustic radiation force and are pushed toward the acoustic pressure node. As a result, by tuning the frequency of the SSAW excitation, the position of the pressure nodes can be changed and droplets can be sorted to different outlets at rates up to 222 droplets s(-1). With its advantages in simplicity, controllability, versatility, noninvasiveness, and capability to be integrated with other on-chip components such as droplet manipulation and optical detection units, the technique presented here could be valuable for the development of droplet-based micro total analysis systems (μTAS).

  11. On-chip sample preparation for complete blood count from raw blood.

    Science.gov (United States)

    Nguyen, John; Wei, Yuan; Zheng, Yi; Wang, Chen; Sun, Yu

    2015-03-21

    This paper describes a monolithic microfluidic device capable of on-chip sample preparation for both RBC and WBC measurements from whole blood. For the first time, on-chip sample processing (e.g. dilution, lysis, and filtration) and downstream single cell measurement were fully integrated to enable sample preparation and single cell analysis from whole blood on a single device. The device consists of two parallel sub-systems that perform sample processing and electrical measurements for measuring RBC and WBC parameters. The system provides a modular environment capable of handling solutions of various viscosities by adjusting the length of channels and precisely controlling mixing ratios, and features a new 'offset' filter configuration for increased duration of device operation. RBC concentration, mean corpuscular volume (MCV), cell distribution width, WBC concentration and differential are determined by electrical impedance measurement. Experimental characterization of over 100,000 cells from 10 patient blood samples validated the system's capability for performing on-chip raw blood processing and measurement.

  12. Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Feng Wang

    2015-01-01

    Full Text Available Network-on-Chip (NoC is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

  13. Manually operatable on-chip bistable pneumatic microstructures for microfluidic manipulations.

    Science.gov (United States)

    Chen, Arnold; Pan, Tingrui

    2014-09-07

    Bistable microvalves are of particular interest because of their distinct nature of requiring energy consumption only during the transition between the open and closed states. This characteristic can be highly advantageous in reducing the number of external inputs and the complexity of control circuitries since microfluidic devices as contemporary lab-on-a-chip platforms are transferring from research settings to low-resource environments with high integrability and a small form factor. In this paper, we first present manually operatable, on-chip bistable pneumatic microstructures (BPMs) for microfluidic manipulation. The structural design and operation of the BPM devices can be readily integrated into any pneumatically powered microfluidic network consisting of pneumatic and fluidic channels. It is mainly composed of a vacuum activation chamber (VAC) and a pressure release chamber (PRC), of which users have direct control through finger pressing to switch either to the bistable vacuum state (VS) or the atmospheric state (AS). We have integrated multiple BPM devices into a 4-to-1 microfluidic multiplexor to demonstrate on-chip digital flow switching from different sources. Furthermore, we have shown its clinical relevance in a point-of-care diagnostic chip that processes blood samples to identify the distinct blood types (A/B/O) on-chip.

  14. On-Chip Waveguide Coupling of a Layered Semiconductor Single-Photon Source.

    Science.gov (United States)

    Tonndorf, Philipp; Del Pozo-Zamudio, Osvaldo; Gruhler, Nico; Kern, Johannes; Schmidt, Robert; Dmitriev, Alexander I; Bakhtinov, Anatoly P; Tartakovskii, Alexander I; Pernice, Wolfram; Michaelis de Vasconcellos, Steffen; Bratschitsch, Rudolf

    2017-09-13

    Fully integrated quantum technology based on photons is in the focus of current research, because of its immense potential concerning performance and scalability. Ideally, the single-photon sources, the processing units, and the photon detectors are all combined on a single chip. Impressive progress has been made for on-chip quantum circuits and on-chip single-photon detection. In contrast, nonclassical light is commonly coupled onto the photonic chip from the outside, because presently only few integrated single-photon sources exist. Here, we present waveguide-coupled single-photon emitters in the layered semiconductor gallium selenide as promising on-chip sources. GaSe crystals with a thickness below 100 nm are placed on Si 3 N 4 rib or slot waveguides, resulting in a modified mode structure efficient for light coupling. Using optical excitation from within the Si 3 N 4 waveguide, we find nonclassicality of generated photons routed on the photonic chip. Thus, our work provides an easy-to-implement and robust light source for integrated quantum technology.

  15. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Directory of Open Access Journals (Sweden)

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  16. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  17. Integration of microcoils for on-chip immunosensors based on magnetic nanoparticles capture

    Directory of Open Access Journals (Sweden)

    Olivier Lefebvre

    2017-04-01

    Full Text Available Immunoassays using magnetic nanoparticles (MNP are generally performed under the control of permanent magnet close to the micro-tube of reaction. Using a magnet gives a powerful method for driving MNP but remains unreliable or insufficient for a fully integrated immunoassay on lab-on-chip. The aim of this study is to develop a novel lab-on-chip concept for high efficient immunoassays to detect ovalbumin (Biodefense model molecule with microcoils employed for trapping MNP during the biofunctionalization steps. The objectives are essentially to optimize their efficiency for biological recognition by assuring a better bioactivity (antibodies-ovalbumin, and detect small concentrations of the targeted protein (~10 pg/mL. In this work, we studied the response of immunoassays complex function of ovalbumin concentration. The impact of MNP diameter in the biografting protocol was studied and permitted to choose a convenient MNP size for efficient biorecognition. We realized different immunoassays by controlling MNP in test tube and in microfluidic device using a permanent magnet. The comparison between these two experiments allows us to highlight an improvement of the limit of detection in microfluidic conditions by controlling MNP trapping with a magnet. Keywords: Bacteria, Lab-on-chip, ELISA, Magnetic nanoparticles, Ovalbumin, Microcoils, Fluorescent microscopy

  18. Integrated lab-on-chip biosensing systems based on magnetic particle actuation--a comprehensive review.

    Science.gov (United States)

    van Reenen, Alexander; de Jong, Arthur M; den Toonder, Jaap M J; Prins, Menno W J

    2014-06-21

    The demand for easy to use and cost effective medical technologies inspires scientists to develop innovative lab-on-chip technologies for point-of-care in vitro diagnostic testing. To fulfill medical needs, the tests should be rapid, sensitive, quantitative, and miniaturizable, and need to integrate all steps from sample-in to result-out. Here, we review the use of magnetic particles actuated by magnetic fields to perform the different process steps that are required for integrated lab-on-chip diagnostic assays. We discuss the use of magnetic particles to mix fluids, to capture specific analytes, to concentrate analytes, to transfer analytes from one solution to another, to label analytes, to perform stringency and washing steps, and to probe biophysical properties of the analytes, distinguishing methodologies with fluid flow and without fluid flow (stationary microfluidics). Our review focuses on efforts to combine and integrate different magnetically actuated assay steps, with the vision that it will become possible in the future to realize integrated lab-on-chip biosensing assays in which all assay process steps are controlled and optimized by magnetic forces.

  19. Adaptive Code Division Multiple Access Protocol for Wireless Network-on-Chip Architectures

    Science.gov (United States)

    Vijayakumaran, Vineeth

    Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol

  20. Highly-integrated lab-on-chip system for point-of-care multiparameter analysis.

    Science.gov (United States)

    Schumacher, Soeren; Nestler, Jörg; Otto, Thomas; Wegener, Michael; Ehrentreich-Förster, Eva; Michel, Dirk; Wunderlich, Kai; Palzer, Silke; Sohn, Kai; Weber, Achim; Burgard, Matthias; Grzesiak, Andrzej; Teichert, Andreas; Brandenburg, Albrecht; Koger, Birgit; Albers, Jörg; Nebling, Eric; Bier, Frank F

    2012-02-07

    A novel innovative approach towards a marketable lab-on-chip system for point-of-care in vitro diagnostics is reported. In a consortium of seven Fraunhofer Institutes a lab-on-chip system called "Fraunhofer ivD-platform" has been established which opens up the possibility for an on-site analysis at low costs. The system features a high degree of modularity and integration. Modularity allows the adaption of common and established assay types of various formats. Integration lets the system move from the laboratory to the point-of-need. By making use of the microarray format the lab-on-chip system also addresses new trends in biomedicine. Research topics such as personalized medicine or companion diagnostics show that multiparameter analyses are an added value for diagnostics, therapy as well as therapy control. These goals are addressed with a low-cost and self-contained cartridge, since reagents, microfluidic actuators and various sensors are integrated within the cartridge. In combination with a fully automated instrumentation (read-out and processing unit) a diagnostic assay can be performed in about 15 min. Via a user-friendly interface the read-out unit itself performs the assay protocol, data acquisition and data analysis. So far, example assays for nucleic acids (detection of different pathogens) and protein markers (such as CRP and PSA) have been established using an electrochemical read-out based on redoxcycling or an optical read-out based on total internal reflectance fluorescence (TIRF). It could be shown that the assay performance within the cartridge is similar to that found for the same assay in a microtiter plate. Furthermore, recent developments are the integration of sample preparation and polymerase chain reaction (PCR) on-chip. Hence, the instrument is capable of providing heating-and-cooling cycles necessary for DNA-amplification. In addition to scientific aspects also the production of such a lab-on-chip system was part of the development since

  1. Dynamic On-Chip micro Temperature and Flow Sensor for miniaturized lab-on-a-chip instruments

    Data.gov (United States)

    National Aeronautics and Space Administration — The purpose of this project is to design, fabricate, and characterize a Dynamic On-Chip Flow and Temperature Sensor (DOCFlaTS) to mature and enable miniaturized...

  2. A system-on-chip digital pH meter for use in a wireless diagnostic capsule

    OpenAIRE

    Hammond, P.A.; Ali, D.; Cumming, D.R.S.

    2005-01-01

    This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is de...

  3. Immuno-MALDI-MS in Human Plasma and On-Chip Biomarker Characterizations at the Femtomole Level

    Directory of Open Access Journals (Sweden)

    Wilfrid Boireau

    2012-11-01

    Full Text Available Immuno-SPR-MS is the combination of immuno-sensors in biochip format with mass spectrometry. This association of instrumentation allows the detection and the quantification of proteins of interest by SPR and their molecular characterization by additional MS analysis. However, two major bottlenecks must be overcome for a wide diffusion of the SPR-MS analytical platform: (i To warrant all the potentialities of MS, an enzymatic digestion step must be developed taking into account the spot formats on the biochip and (ii the biological relevancy of such an analytical solution requires that biosensing must be performed in complex media. In this study, we developed a procedure for the detection and the characterization at ~1 µg/mL of the LAG3 protein spiked in human plasma. The analytical performances of this new method was established, particularly its specificity (S/N > 9 and sensitivity (100% of LAG3 identification with high significant mascot score >68 at the femtomole level. The collective and automated on-chip MALDI-MS imaging and analysis based on peptidic fragments opens numerous applications in the fields of proteomics and diagnosis.

  4. A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

    Science.gov (United States)

    Santoli, S.

    The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

  5. A Bio-Inspired Hybrid Thermal Management Approach for 3-D Network-on-Chip Systems.

    Science.gov (United States)

    Dash, Ranjita; Risco-Martin, Jose L; Turuk, Ashok Kumar; Ayala, Jose L; Pangracious, Vinod; Majumdar, Amartya

    2017-12-01

    3-D network-on-chip (NoC) systems are getting popular among the integrated circuit (IC) manufacturer because of reduced latency, heterogeneous integration of technologies on a single chip, high yield, and consumption of less interconnecting power. However, the addition of functional units in the -direction has resulted in higher on-chip temperature and appearance of local hotspots on the die. The increase in temperature degrades the performance, lifetime, and reliability, and increases the maintenance cost of 3-D ICs. To keep the heat within an acceptable limit, floorplanning is the widely accepted solution. Proper arrangement of functional units across different layers can lead to uniform thermal distribution in the chip. For systems with high density of elements, few hotspots cannot be eliminated in the floorplanning approach. To overcome, liquid microchannel cooling technology has emerged as an efficient and scalable solution for 3-D NoC. In this paper, we propose a novel hybrid algorithm combining both floorplanning, and liquid microchannel placement to alleviate the hotspots in high-density systems. A mathematical model is proposed to deal with heat transfer due to diffusion and convention. The proposed approach is independent of topology. Three different topologies: 3-D stacked homogeneous mesh architecture, 3-D stacked heterogeneous mesh architecture, and 3-D stacked ciliated mesh architecture are considered to check the effectiveness of the proposed algorithm in hotspot reduction. A thermal comparison is made with and without the proposed thermal management approach for the above architectures considered. It is observed that there is a significant reduction in on-chip temperature when the proposed thermal management approach is applied.

  6. On-Chip integration of sample pretreatment and Multiplex polymerase chain reaction (PCR) for DNA analysis

    DEFF Research Database (Denmark)

    Brivio, Monica; Snakenborg, Detlef; Søgaard, E.

    2008-01-01

    In this paper we present a modular lab-on-a-chip system for integrated sample pre-treatment (PT) by magnetophoresis and DNA amplification by polymerase chain reaction (PCR). It consists of a polymer-based microfluidic chip mounted on a custom-made thermocycler (Figure 1) and includes a simple...... and efficient method for switching the liquid flow between the PT and PCR chamber. Purification of human genomic DNA from EDTA-treated blood and multiplex PCR were successfully carried out on-chip using the developed lab-on-a-chip system....

  7. On-chip optical filter comprising Fabri-Perot resonator structure and spectrometer

    Energy Technology Data Exchange (ETDEWEB)

    Han, Seunghoon; Horie, Yu; Faraon, Andrei; Arbabi, Amir

    2018-04-10

    An on-chip optical filter having Fabri-Perot resonators and a spectrometer may include a first sub-wavelength grating (SWG) reflecting layer and a second SWG reflecting layer facing each other. A plurality of Fabri-Perot resonators are formed by the first SWG reflecting layer and the second SWG reflecting layer facing each other. Each of the Fabri-Perot resonators may transmit light corresponding to a resonance wavelength of the Fabri-Perot resonator. The resonance wavelengths of the Fabri-Perot resonators may be determined according to duty cycles of grating patterns.

  8. Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

    DEFF Research Database (Denmark)

    Müller, Christoph; Kasapaki, Evangelia; Sørensen, Rasmus Bo

    2014-01-01

    Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example...... is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented...

  9. On-chip detection of radiation guided by dielectric-loaded plasmonic waveguides

    DEFF Research Database (Denmark)

    Han, Z.; Radko, I. P.; Mazurski, N.

    2015-01-01

    ) substrate supplied with aluminum pads facilitating electrical connections, with the gold pad being perforated in a specific location below the DLSPPWs in order to allow a portion of the DLSPPW-guided radiation to leak into the Si-substrate, where it is absorbed and electrically detected. We present two......We report a novel approach for on-chip electrical detection of the radiation guided by dielectric-loaded surface plasmon polariton waveguides (DLSPPW) and DLSPPW-based components. The detection is realized by fabricating DLSPPW components on the surface of a gold (Au) pad supported by a silicon (Si...

  10. Identification of microfluidic two-phase flow patterns in lab-on-chip devices.

    Science.gov (United States)

    Yang, Zhaochu; Dong, Tao; Halvorsen, Einar

    2014-01-01

    This work describes a capacitive sensor for identification of microfluidic two-phase flow in lab-on-chip devices. With interdigital electrodes and thin insulation layer utilized, this sensor is capable of being integrated with the microsystems easily. Transducing principle and design considerations are presented with respect to the microfluidic gas/liquid flow patterns. Numerical simulation results verify the operational principle. And the factors affecting the performance of the sensor are discussed. Besides, a feasible process flow for the fabrication is also proposed.

  11. A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Brandner, Florian; Sparsø, Jens

    2012-01-01

    This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We...... presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented...

  12. On-chip measurements of Brownian relaxation vs. concentration of 40nm magnetic beads

    DEFF Research Database (Denmark)

    Østerberg, Frederik Westergaard; Rizzi, Giovanni; Hansen, Mikkel Fougt

    2012-01-01

    We present on-chip Brownian relaxation measurements on a logarithmic dilution series of 40 nm beads dispersed in water with bead concentrations between 16 mu g/ml and 4000 mu g/ml. The measurements are performed using a planar Hall effect bridge sensor at frequencies up to 1 MHz. No external fields...... are needed as the beads are magnetized by the field generated by the applied sensor bias current. We show that the Brownian relaxation frequency can be extracted from fitting the Cole-Cole model to measurements for bead concentrations of 64 mu g/ml or higher and that the measured dynamic magnetic response...

  13. On-Chip Microplasmas for the Detection of Radioactive Cesium Contamination in Seawater

    Directory of Open Access Journals (Sweden)

    Joshua B. Joffrion

    2017-08-01

    Full Text Available On-chip microplasmas have previously been used in designing a compact and portable device for identifying pollutants in a water sample. By exciting a liquid sample with a high energy microdischarge and recording the spectral wavelengths emitted, the individual elements in the liquid are distinguishable. In particular, this study focuses on cesium, a contaminant from nuclear incidents such as the collapse of the nuclear power plant in Fukushima, Japan. This article shows that not only can the presence of cesium be clearly determined at concentrations as low as 10 ppb, but the relative concentration contained in the sample can be determined through the discharges’ relative spectral intensity.

  14. Composable Flexible Real-time Packet Scheduling for Networks on-Chip

    Science.gov (United States)

    2012-05-16

    the packets at the flow’s source. 2) Preemptive EDF Scheduling: As wormhole flow control allows sending packets sent flit-by-flit, we could employ a...analysis of wormhole based heterogeneous noc. In Proceedings of the 2011 Fifth ACM/IEEE International Symposium on Networks-on-Chip, NOCS ’11, pages 161–168...Computer Architecture, ISCA ’08, pages 89–100, Washington, DC, USA, 2008. IEEE Computer Society. [14] Sunggu Lee. Real-time wormhole channels. Journal of

  15. Amplification of biological targets via on-chip culture for biosensing

    Energy Technology Data Exchange (ETDEWEB)

    Harper, Jason C.; Edwards, Thayne L.; Carson, Bryan; Finley, Melissa; Arndt, William

    2018-01-02

    The present invention, in part, relates to methods and apparatuses for on-chip amplification and/or detection of various targets, including biological targets and any amplifiable targets. In some examples, the microculture apparatus includes a single-use, normally-closed fluidic valve that is initially maintained in the closed position by a valve element bonded to an adhesive coating. The valve is opened using a magnetic force. The valve element includes a magnetic material or metal. Such apparatuses and methods are useful for in-field or real-time detection of targets, especially in limited resource settings.

  16. CLOSED FORM MODELING OF CROSSTALK FOR DISTRIBUTED RLCG ON-CHIP INTERCONNECTS USING DIFFERENCE MODEL APPROACH

    Directory of Open Access Journals (Sweden)

    Rajib Kar

    2010-03-01

    Full Text Available On chip interconnect plays a dominant role on the circuit performance in both analog and digital domains. Interconnects can no longer be treated as mere delays or lumped RC networks. Crosstalk, ringing and reflections are just some of the issues that need to be addressed for the efficient design of high speed VLSI circuits. In order to accurately model these high frequency effects, inductance had been taken into consideration. Within this frequency range, the most accurate simulation model for on-chip VLSI interconnects was the distributed RLC model. Unfortunately, this model has many limitations at much higher of operating frequency used in today’s VLSI design. This can lead to inaccurate simulations if not modeled properly. At even higher frequency the conductance metrics has become a dominant factor and has to be taken into consideration for accurate modeling of the different on-chip performance parameters. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. With the increase in frequency and interconnection length due to the increase in the number of on-chip devices, the lossy components are prevailing than the lossless components. With the reduction of pitch between the adjacent wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase in capacitances results the introduction of noise which is capable of propagating a logical fault. An inaccurate estimation of the crosstalk could be the origin of the malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor and victim nets. The aggressor net carries a signal that couples to the victim net through the parasitic capacitances [13]. To determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. This paper

  17. Magnetic Tunnel Junction-Based On-Chip Microwave Phase and Spectrum Analyzer

    Science.gov (United States)

    Fan, Xin; Chen, Yunpeng; Xie, Yunsong; Kolodzey, James; Wilson, Jeffrey D.; Simons, Rainee N.; Xiao, John Q.

    2014-01-01

    A magnetic tunnel junction (MTJ)-based microwave detector is proposed and investigated. When the MTJ is excited by microwave magnetic fields, the relative angle between the free layer and pinned layer alternates, giving rise to an average resistance change. By measuring the average resistance change, the MTJ can be utilized as a microwave power sensor. Due to the nature of ferromagnetic resonance, the frequency of an incident microwave is directly determined. In addition, by integrating a mixer circuit, the MTJ-based microwave detector can also determine the relative phase between two microwave signals. Thus, the MTJbased microwave detector can be used as an on-chip microwave phase and spectrum analyzer.

  18. A Metaheuristic Scheduler for Time Division Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Sparsø, Jens; Pedersen, Mark Ruvald

    This report presents a metaheuristic scheduler for inter-processor communication in multi-core platforms using time division multiplexed (TDM) networks on chip (NOC). Input to the scheduler is a specification of the target multi-core platform and a specification of the application. Compared...... that this is possible with only negligible impact on the schedule period. We evaluate the scheduler with seven different applications from the MCSL NOC benchmark suite. We observe that the metaheuristics perform better than the greedy solution. In the special case of all-to-all communication with equal bandwidths...

  19. Mach-Zehnder-based optical router design for photonic networks on chip

    Science.gov (United States)

    Yaghoubi, Elham; Reshadi, Midia; Hosseinzadeh, Mehdi

    2015-03-01

    We design and simulate six- and seven-port optical routers based on Mach-Zehnder interferometer switches that are suitable for photonic networks-on-chip. The routers are composed of 12 and 22 switching elements as the possible 30 input/output and 42 input/output routing paths are verified at a data transmission rate of 20 Gbps for six- and seven-port optical routers, respectively. We use an OptiSystem simulator to evaluate the proposed optical routers from the aspects of insertion loss, Q-factor and minimum bit error ratio.

  20. A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2007-01-01

    regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity......Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked...... is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system...

  1. A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in asynchronous Network-on-Chip. We present a novel scheduling discipline called Asynchronous Latency Guarantee (ALG......) scheduling, which provides latency and bandwidth guarantees in accessing a shared media, e.g. a physical link shared between a number of virtual channels. ALG overcomes the drawbacks of existing scheduling disciplines, in particular the coupling between latency and bandwidth guarantees. A 0.12 &956;m CMOS...

  2. Webcam camera as a detector for a simple lab-on-chip time based approach.

    Science.gov (United States)

    Wongwilai, Wasin; Lapanantnoppakhun, Somchai; Grudpan, Supara; Grudpan, Kate

    2010-05-15

    A modification of a webcam camera for use as a small and low cost detector was demonstrated with a simple lab-on-chip reactor. Real time continuous monitoring of the reaction zone could be done. Acid-base neutralization with phenolphthalein indicator was used as a model reaction. The fading of pink color of the indicator when the acidic solution diffused into the basic solution zone was recorded as the change of red, blue and green colors (%RBG.) The change was related to acid concentration. A low cost portable semi-automation analysis system was achieved.

  3. Random number generator based on an integrated laser with on-chip optical feedback

    Science.gov (United States)

    Verschaffelt, Guy; Khoder, Mulham; Van der Sande, Guy

    2017-11-01

    We discuss the design and testing of a laser integrated with a long on-chip optical feedback section. The device and feedback section have been fabricated on a generic photonic integration platform using only standard building blocks. We have been able to integrate a 10 cm feedback length on a footprint of 5.5 mm2. By controlling the amount of feedback, we achieve chaotic dynamics in the long-cavity regime and show that the resulting dynamics is sufficiently complex in order to generate random bits based on the chaotic intensity fluctuation at a rate of 500 Mbits/s.

  4. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally-Synchronous......We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...

  5. An acoustic on-chip goniometer for room temperature macromolecular crystallography.

    Science.gov (United States)

    Burton, C G; Axford, D; Edwards, A M J; Gildea, R J; Morris, R H; Newton, M I; Orville, A M; Prince, M; Topham, P D; Docker, P T

    2017-12-05

    This paper describes the design, development and successful use of an on-chip goniometer for room-temperature macromolecular crystallography via acoustically induced rotations. We present for the first time a low cost, rate-tunable, acoustic actuator for gradual in-fluid sample reorientation about varying axes and its utilisation for protein structure determination on a synchrotron beamline. The device enables the efficient collection of diffraction data via a rotation method from a sample within a surface confined droplet. This method facilitates efficient macromolecular structural data acquisition in fluid environments for dynamical studies.

  6. Ultra-fast quantitative imaging using ptychographic iterative engine based digital micro-mirror device

    Science.gov (United States)

    Sun, Aihui; Tian, Xiaolin; Kong, Yan; Jiang, Zhilong; Liu, Fei; Xue, Liang; Wang, Shouyu; Liu, Cheng

    2018-01-01

    As a lensfree imaging technique, ptychographic iterative engine (PIE) method can provide both quantitative sample amplitude and phase distributions avoiding aberration. However, it requires field of view (FoV) scanning often relying on mechanical translation, which not only slows down measuring speed, but also introduces mechanical errors decreasing both resolution and accuracy in retrieved information. In order to achieve high-accurate quantitative imaging with fast speed, digital micromirror device (DMD) is adopted in PIE for large FoV scanning controlled by on/off state coding by DMD. Measurements were implemented using biological samples as well as USAF resolution target, proving high resolution in quantitative imaging using the proposed system. Considering its fast and accurate imaging capability, it is believed the DMD based PIE technique provides a potential solution for medical observation and measurements.

  7. Improved color metrics in solid-state lighting via utilization of on-chip quantum dots

    Science.gov (United States)

    Mangum, Benjamin D.; Landes, Tiemo S.; Theobald, Brian R.; Kurtin, Juanita N.

    2017-02-01

    While Quantum Dots (QDs) have found commercial success in display applications, there are currently no widely available solid state lighting products making use of QD nanotechnology. In order to have real-world success in today's lighting market, QDs must be capable of being placed in on-chip configurations, as remote phosphor configurations are typically much more expensive. Here we demonstrate solid-state lighting devices made with on-chip QDs. These devices show robust reliability under both dry and wet high stress conditions. High color quality lighting metrics can easily be achieved using these narrow, tunable QD downconverters: CRI values of Ra > 90 as well as R9 values > 80 are readily available when combining QDs with green phosphors. Furthermore, we show that QDs afford a 15% increase in overall efficiency compared to traditional phosphor downconverted SSL devices. The fundamental limit of QD linewidth is examined through single particle QD emission studies. Using standard Cd-based QD synthesis, it is found that single particle linewidths of 20 nm FWHM represent a lower limit to the narrowness of QD emission in the near term.

  8. On-chip bioassay using immobilized sensing bacteria in three-dimensional microfluidic network.

    Science.gov (United States)

    Tani, Hirofumi; Maehana, Koji; Kamidate, Tamio

    2007-01-01

    An on-chip whole-cell bioassay has been carried out using Escherichia coli tester strains for genotoxicity. In this assay format, the mutagen-responsive bioluminescence (BL) strains are immobilized in a chip assembly in which a silicon chip is placed between two poly(dimethylsiloxane) (PDMS) chips. In the chip assembly, microchannels fabricated on the two separate PDMS layers are connected via perforated microwells on the Si chip, and thus a three-dimensional microfluidic network is constructed. The strains mixed with agarose are loaded from the channels on one of the two PDMS layers into the wells on Si chip, followed by gelation. Induction of the expression of firefly luciferase in the tester strains and BL reaction are successively carried out by filling the channels on another PDMS layer with samples containing inducer (genotoxic substance) and then adenosine triphosphate/luciferin mixture, respectively. BL emission from each of the wells can be monitored by using a charge-coupled device camera to obtain an overall picture of the chip. The on-chip format based on a three-dimensional microfluidic network provides a combinatorial bioassay for multiple samples with multiple tester strains in a simple chip assembly. Thus, the presented method could be applied not only to various microbial sensing applications but also to other (bio)chemical analyses.

  9. Designing 2D and 3D network-on-chip architectures

    CERN Document Server

    Tatas, Konstantinos; Soudris, Dimitrios; Jantsch, Axel

    2014-01-01

    This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

  10. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    Directory of Open Access Journals (Sweden)

    Chih-Ting Lin

    2012-08-01

    Full Text Available A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

  11. A HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIP ARCHITECTURE INCORPORATING MEMORY ALLOCATION

    Directory of Open Access Journals (Sweden)

    T.Thillaikkarasi

    2010-06-01

    Full Text Available This paper describes the development of a Multiprocessor System-on-Chip (MPSoC with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time constraints onto the heterogeneous multiprocessor System on Chip (SoC architectures and focuses on a memory allocation step which is based on an integer linear programming model. An application is modeled as Kahn Process Network (KPN which makes the parallelism present in the application explicit. The main contribution of our work is an MILP based approach which can be used to map the KPN of streaming applications with data dependent behavior and interleaved computation and communication. Our solution minimizes hardware cost while taking into account the performance constraints. One of the salient features of our work is that it takes into account the additional overheads because of data communication conflicts. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application.

  12. Marker Pen Lithography for Flexible and Curvilinear On-Chip Energy Storage

    KAUST Repository

    Jiang, Qiu

    2015-07-14

    On-chip energy storage using microsupercapacitors can serve the dual role of supplementing batteries for pulse power delivery, and replacement of bulky electrolytic capacitors in ac-line filtering applications. Despite complexity and processing costs, microfabrication techniques are being employed in fabricating a great variety of microsupercapacitor devices. Here, a simple, cost-effective, and versatile strategy is proposed to fabricate flexible and curvilinear microsupercapacitors (MSCs). The protocol involves writing sacrificial ink patterns using commercial marker pens on rigid, flexible, and curvilinear substrates. It is shown that this process can be used in both lift-off and etching modes, and the possibility of multistack design of active materials using simple pen lithography is demonstrated. As a prototype, this method is used to produce conducting polymer MSCs involving both poly(3,4-ethylenedioxythiophene), polyaniline, and metal oxide (MnO2) electrode materials. Typical values of energy density in the range of 5-11 mWh cm-3 at power densities of 1-6 W cm-3 are achieved, which is comparable to thin film batteries and superior to the carbon and metal oxide based microsupercapacitors reported in the literature. The simplicity and broad scope of this innovative strategy can open up new avenues for easy and scalable fabrication of a wide variety of on-chip energy storage devices. © 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim.

  13. Diatomite Photonic Crystals for Facile On-Chip Chromatography and Sensing of Harmful Ingredients from Food.

    Science.gov (United States)

    Kong, Xianming; Yu, Qian; Li, Erwen; Wang, Rui; Liu, Qing; Wang, Alan X

    2018-03-31

    Diatomaceous earth-otherwise called diatomite-is essentially composed of hydrated biosilica with periodic nanopores. Diatomite is derived from fossilized remains of diatom frustules and possesses photonic-crystal features. In this paper, diatomite simultaneously functions as the matrix of the chromatography plate and the substrate for surface-enhanced Raman scattering (SERS), by which the photonic crystal-features could enhance the optical field intensity. The on-chip separation performance of the device was confirmed by separating and detecting industrial dye (Sudan I) in an artificial aqueous mixture containing 4-mercaptobenzoic acid (MBA), where concentrated plasmonic Au colloid was casted onto the analyte spot for SERS measurement. The plasmonic-photonic hybrid mode between the Au nanoparticles (NP) and the diatomite layer could supply nearly 10 times the increment of SERS signal (MBA) intensity compared to the common silica gel chromatography plate. Furthermore, this lab-on-a-chip photonic crystal device was employed for food safety sensing in real samples and successfully monitored histamine in salmon and tuna. This on-chip food sensor can be used as a cheap, robust, and portable sensing platform for monitoring for histamine or other harmful ingredients at trace levels in food products.

  14. Embedded memory design for multi-core and systems on chip

    CERN Document Server

    Mohammad, Baker

    2014-01-01

    This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit ...

  15. Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Yin Zhen Tei

    2014-01-01

    Full Text Available This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC. As the number of intellectual property (IP cores in multiprocessor system-on-chip (MPSoC increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA. The initial population of GA is initialized with network partitioning (NP while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

  16. On-chip multicomponent system made with an InGaN directional coupler.

    Science.gov (United States)

    Zhang, Fenghua; Shi, Zheng; Gao, Xumin; Qin, Chuan; Zhang, Shuai; Jiang, Yan; Wu, Fan; Wang, Yongjin

    2018-04-15

    An on-chip multicomponent system is implemented on a III-nitride-on-silicon platform by integrating a transmitter, InGaN waveguide, InGaN directional coupler, and receivers onto a single chip. The transmitter and the receiver share an identical InGaN/GaN multiple-quantum-well (MQW) diode structure and are produced by using the same wafer-level process flow. The receiver sensitively responds to the short-wavelength half of the emission spectrum of the transmitter, thus realizing the multicomponent system with the capability for inplane light communication. A SiO 2 isolation layer is employed to decrease the p-n junction capacitance, thus improving the modulation rate without modifying the MQW structure. The wire-bonded monolithic multicomponent system experimentally demonstrates inplane data transmission at 80 Mbps and spatial light communication at 100 Mbps, paving the way for diverse applications from on-chip power monitoring to inplane light communication in the visible light spectrum.

  17. A compact HTS bandpass microstrip filter with novel coupling structure for on-chip integration

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Ting, E-mail: ting.zhang@csiro.au [CSIRO ICT Centre, Epping, NSW 1710 (Australia); Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science, Shanghai 200050 (China); Du, Jia [CSIRO Materials Science and Engineering, PO Box 218, Lindfield, NSW 2070 (Australia); Guo, Yingjie Jay [CSIRO ICT Centre, Epping, NSW 1710 (Australia); Sun, Xiaowei [Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science, Shanghai 200050 (China)

    2013-12-15

    Highlights: •A novel coupling scheme is used to introduce two transmission zeros using only three resonators. •The filter has a low insertion loss at 40 K, and a wide stopband with good rejection. •The filter has compactness and high-selectivity. •The filter is a suitable candidate for on-chip integration of HTS receiver front-ends. -- Abstract: A compact low-complexity high-selectivity high-temperature superconducting (HTS) microstrip bandpass filter is presented in this paper, which consists of only three half-wavelength resonators. A novel coupling scheme is used to provide a pair of transmission zeros outside the passband, so that the selectivity of the filter is improved. The filter is fabricated on an MgO substrate with YBa{sub 2}Cu{sub 3}O{sub 7−x} (YBCO) coating. Measurement result shows an in-band insertion loss at 0.5 dB, a sharp slope, and a stopband rejection better than 20 dB. The compactness and high-selectivity features make the filter suitable for on-chip integration of HTS receiver front-ends.

  18. On-chip real-time single-copy polymerase chain reaction in picoliter droplets

    Energy Technology Data Exchange (ETDEWEB)

    Beer, N R; Hindson, B; Wheeler, E; Hall, S B; Rose, K A; Kennedy, I; Colston, B

    2007-04-20

    The first lab-on-chip system for picoliter droplet generation and PCR amplification with real-time fluorescence detection has performed PCR in isolated droplets at volumes 10{sup 6} smaller than commercial real-time PCR systems. The system utilized a shearing T-junction in a silicon device to generate a stream of monodisperse picoliter droplets that were isolated from the microfluidic channel walls and each other by the oil phase carrier. An off-chip valving system stopped the droplets on-chip, allowing them to be thermal cycled through the PCR protocol without droplet motion. With this system a 10-pL droplet, encapsulating less than one copy of viral genomic DNA through Poisson statistics, showed real-time PCR amplification curves with a cycle threshold of {approx}18, twenty cycles earlier than commercial instruments. This combination of the established real-time PCR assay with digital microfluidics is ideal for isolating single-copy nucleic acids in a complex environment.

  19. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  20. Intelligent On/Off Dynamic Link Management for On-Chip Networks

    Directory of Open Access Journals (Sweden)

    Andreas G. Savva

    2012-01-01

    Full Text Available Networks-on-chips (NoCs provide scalable on-chip communication and are expected to be the dominant interconnection architectures in multicore and manycore systems. Power consumption, however, is a major limitation in NoCs today, and researchers have been constantly working on reducing both dynamic and static power. Among the NoC components, links that connect the NoC routers are the most power-hungry components. Several attempts have been made to reduce the link power consumption at both the circuit level and the system level. Most past research efforts have proposed selective on/off link state switching based on system-level information based on link utilization levels. Most of these proposed algorithms focus on a pessimistic and simple static threshold mechanism which determines whether or not a link should be turned on/off. This paper presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status (i.e., expected future utilization link levels, where links are turned off and on via the use of a small and scalable neural network. Simulation results with various synthetic traffic models over various network topologies show that the proposed work can reach up to 13% power savings when compared to a trivial threshold computation, at very low (<4% hardware overheads.

  1. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  2. Nature-inspired interconnects for self-assembled large-scale network-on-chip designs

    Science.gov (United States)

    Teuscher, Christof

    2007-06-01

    Future nanoscale electronics built up from an Avogadro number of components need efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the networks-on-chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design tradeoffs and properties of an irregular, abstract, yet physically plausible three-dimensional (3D) small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, number of switch nodes, and distribution of long- versus short-range connections, and measure the network's relevant communication characteristics. We further explore the robustness against link failures and the ability and efficiency to solve a simple toy problem, the synchronization task. The results confirm that (1) computation in irregular assemblies is a promising and disruptive computing paradigm for self-assembled nanoscale electronics and (2) that 3D small-world interconnect fabrics with a power-law decaying distribution of shortcut lengths are physically plausible and have major advantages over local two-dimensional and 3D regular topologies.

  3. Fast Detection Anti-Collision Algorithm for RFID System Implemented On-Chip

    Science.gov (United States)

    Sampe, Jahariah; Othman, Masuri

    This study presents a proposed Fast Detection Anti-Collision Algorithm (FDACA) for Radio Frequency Identification (RFID) system. Our proposed FDACA is implemented on-chip using Application Specific Integrated Circuit (ASIC) technology and the algorithm is based on the deterministic anti-collision technique. The FDACA is novel in terms of a faster identification by reducing the number of iterations during the identification process. The primary FDACA also reads the identification (ID) bits at once regardless of its length. It also does not require the tags to remember the instructions from the reader during the communication process in which the tags are treated as address carrying devices only. As a result simple, small, low cost and memoryless tags can be produced. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx Synthesis Technology (XST). The system is implemented in hardware using Field Programmable Grid Array (FPGA) board for real time verification. From the verification results it can be shown that the FDACA system enables to identify the tags without error until the operating frequency of 180 MHZ. Finally the FDACA system is implemented on chip using 0.18 μm Library, Synopsys Compiler and tools. From the resynthesis results it shows that the identification rate of the proposed FDACA system is 333 Mega tags per second with the power requirement of 3.451 mW.

  4. Advances in liquid biopsy on-chip for cancer management: Technologies, biomarkers, and clinical analysis.

    Science.gov (United States)

    Tadimety, Amogha; Closson, Andrew; Li, Cathy; Yi, Song; Shen, Ting; Zhang, John X J

    2018-02-01

    Liquid biopsy, as a minimally invasive method of gleaning insight into the dynamics of diseases through a patient fluid sample, has been growing in popularity for cancer diagnosis, prognosis, and monitoring. While many technologies have been developed and validated in research laboratories, there has also been a push to expand these technologies into other clinical settings and as point of care devices. In this article, we discuss and evaluate microchip-based technologies for circulating tumor cell (CTC), exosome, and circulating tumor nucleic acid (ctNA) capture, detection, and analysis. Such integrated systems streamline otherwise multiple-step, manual operations to get a sample-to-answer quantitation. In addition, analysis of disease biomarkers is suited to point of care settings because of ease of use, low consumption of sample and reagents, and high throughput. We also cover the basics of biomarkers and their detection in biological fluid samples suitable for liquid biopsy on-chip. We focus on emerging technologies that process a small patient sample with high spatial-temporal resolution and derive clinically meaningful results through on-chip biomarker sensing and downstream molecular analysis in a simple workflow. This critical review is meant as a resource for those interested in developing technologies for capture, detection, and analysis platforms for liquid biopsy in a variety of settings.

  5. An Implantable Cardiovascular Pressure Monitoring System with On-Chip Antenna and RF Energy Harvesting

    Directory of Open Access Journals (Sweden)

    Yu-Chun Liu

    2015-08-01

    Full Text Available An implantable wireless system with on-chip antenna for cardiovascular pressure monitor is studied. The implantable device is operated in a batteryless manner, powered by an external radio frequency (RF power source. The received RF power level can be sensed and wirelessly transmitted along with blood pressure signal for feedback control of the external RF power. The integrated electronic system, consisting of a capacitance-to-voltage converter, an adaptive RF powering system, an RF transmitter and digital control circuitry, is simulated using a TSMC 0.18 μm CMOS technology. The implanted RF transmitter circuit is combined with a low power voltage-controlled oscillator resonating at 5.8 GHz and a power amplifier. For the design, the simulation model is setup using ADS and HFSS software. The dimension of the antenna is 1 × 0.6 × 4.8 mm3 with a 1 × 0.6 mm2 on-chip circuit which is small enough to place in human carotid artery.

  6. Priming nanoparticle-guided diagnostics and therapeutics towards human organs-on-chips microphysiological system

    Science.gov (United States)

    Choi, Jin-Ha; Lee, Jaewon; Shin, Woojung; Choi, Jeong-Woo; Kim, Hyun Jung

    2016-10-01

    Nanotechnology and bioengineering have converged over the past decades, by which the application of multi-functional nanoparticles (NPs) has been emerged in clinical and biomedical fields. The NPs primed to detect disease-specific biomarkers or to deliver biopharmaceutical compounds have beena validated in conventional in vitro culture models including two dimensional (2D) cell cultures or 3D organoid models. However, a lack of experimental models that have strong human physiological relevance has hampered accurate validation of the safety and functionality of NPs. Alternatively, biomimetic human "Organs-on-Chips" microphysiological systems have recapitulated the mechanically dynamic 3D tissue interface of human organ microenvironment, in which the transport, cytotoxicity, biocompatibility, and therapeutic efficacy of NPs and their conjugates may be more accurately validated. Finally, integration of NP-guided diagnostic detection and targeted nanotherapeutics in conjunction with human organs-on-chips can provide a novel avenue to accelerate the NP-based drug development process as well as the rapid detection of cellular secretomes associated with pathophysiological processes.

  7. Genotyping of KRAS Mutational Status by the In-Check Lab-on-Chip Platform.

    Science.gov (United States)

    Guarnaccia, Maria; Iemmolo, Rosario; San Biagio, Floriana; Alessi, Enrico; Cavallaro, Sebastiano

    2018-01-05

    The KRAS oncogene is involved in the pathogenesis of several types of cancer, particularly colorectal cancer (CRC). The most frequent mutations in this gene are associated with poor survival, increased tumor aggressiveness and resistance to therapy with anti-epidermal growth factor receptor (EGFR) antibodies. For this reason, KRAS mutation testing has become increasingly common in clinical practice for personalized cancer treatments of CRC patients. Detection methods for KRAS mutations are currently expensive, laborious, time-consuming and often lack of diagnostic sensitivity and specificity. In this study, we describe the development of a Lab-on-Chip assay for genotyping of KRAS mutational status. This assay, based on the In-Check platform, integrates microfluidic handling, a multiplex polymerase chain reaction (PCR) and a low-density microarray. This integrated sample-to-result system enables the detection of KRAS point mutations, including those occurring in codons 12 and 13 of exon 2, 59 and 61 of exon 3, 117 and 146 of exon 4. Thanks to its miniaturization, automation, rapid analysis, minimal risk of sample contamination, increased accuracy and reproducibility of results, this Lab-on-Chip platform may offer immediate opportunities to simplify KRAS genotyping into clinical routine.

  8. Genotyping of KRAS Mutational Status by the In-Check Lab-on-Chip Platform

    Directory of Open Access Journals (Sweden)

    Maria Guarnaccia

    2018-01-01

    Full Text Available The KRAS oncogene is involved in the pathogenesis of several types of cancer, particularly colorectal cancer (CRC. The most frequent mutations in this gene are associated with poor survival, increased tumor aggressiveness and resistance to therapy with anti-epidermal growth factor receptor (EGFR antibodies. For this reason, KRAS mutation testing has become increasingly common in clinical practice for personalized cancer treatments of CRC patients. Detection methods for KRAS mutations are currently expensive, laborious, time-consuming and often lack of diagnostic sensitivity and specificity. In this study, we describe the development of a Lab-on-Chip assay for genotyping of KRAS mutational status. This assay, based on the In-Check platform, integrates microfluidic handling, a multiplex polymerase chain reaction (PCR and a low-density microarray. This integrated sample-to-result system enables the detection of KRAS point mutations, including those occurring in codons 12 and 13 of exon 2, 59 and 61 of exon 3, 117 and 146 of exon 4. Thanks to its miniaturization, automation, rapid analysis, minimal risk of sample contamination, increased accuracy and reproducibility of results, this Lab-on-Chip platform may offer immediate opportunities to simplify KRAS genotyping into clinical routine.

  9. Ultra-Low Threshold Power On-Chip Optical Parametric Oscillation in AlGaAs-On-Insulator Microresonator

    DEFF Research Database (Denmark)

    Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

    2015-01-01

    We present a record-low threshold power of 7 mW at ~1.55 µm for on-chip optical parametric oscillation using a high quality factor micro-ring-resonator in a new nonlinear photonics platform: AlGaAs-on-insulator......We present a record-low threshold power of 7 mW at ~1.55 µm for on-chip optical parametric oscillation using a high quality factor micro-ring-resonator in a new nonlinear photonics platform: AlGaAs-on-insulator...

  10. Analysis of Protein-DNA Interaction by Chromatin Immunoprecipitation and DNA Tiling Microarray (ChIP-on-chip).

    Science.gov (United States)

    Gao, Hui; Zhao, Chunyan

    2018-01-01

    Chromatin immunoprecipitation (ChIP) has become the most effective and widely used tool to study the interactions between specific proteins or modified forms of proteins and a genomic DNA region. Combined with genome-wide profiling technologies, such as microarray hybridization (ChIP-on-chip) or massively parallel sequencing (ChIP-seq), ChIP could provide a genome-wide mapping of in vivo protein-DNA interactions in various organisms. Here, we describe a protocol of ChIP-on-chip that uses tiling microarray to obtain a genome-wide profiling of ChIPed DNA.

  11. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    OpenAIRE

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis trans...

  12. A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed For Evolvability

    DEFF Research Database (Denmark)

    Patou, François; Dimaki, Maria; Svendsen, Winnie Edith

    2015-01-01

    Unprecedented knowledge levels in life sciences along with technological advances in micro- and nanotechnologies and microfluidics have recently conditioned the advent of Lab-on-Chip (LoC) devices for In-Vitro Medical Testing (IVMT). Combined with smart-mobile technologies, LoCs are pervasively...... giving rise to opportunities to better diagnose disease, predict and monitor personalised treatment efficacy, or provide healthcare decision-making support at the Point-of-Care (PoC). Although made increasingly available to the consumer market, the adoption of LoC-based PoC In-Vitro Medical Testing (IVMT...... for this work. We introduce a smart-mobile and LoC-based system architecture designed for evolvability. By propagating LoC programmability, instrumentation, and control tools to the highlevel abstraction smart-mobile software layer, our architecture facilitates the realisation of new use...

  13. On-chip magnetically actuated robot with ultrasonic vibration for single cell manipulations.

    Science.gov (United States)

    Hagiwara, Masaya; Kawahara, Tomohiro; Yamanishi, Yoko; Masuda, Taisuke; Feng, Lin; Arai, Fumihito

    2011-06-21

    This paper presents an innovative driving method for an on-chip robot actuated by permanent magnets in a microfluidic chip. A piezoelectric ceramic is applied to induce ultrasonic vibration to the microfluidic chip and the high-frequency vibration reduces the effective friction on the MMT significantly. As a result, we achieved 1.1 micrometre positioning accuracy of the microrobot, which is 100 times higher accuracy than without vibration. The response speed is also improved and the microrobot can be actuated with a speed of 5.5 mm s(-1) in 3 degrees of freedom. The novelty of the ultrasonic vibration appears in the output force as well. Contrary to the reduction of friction on the microrobot, the output force increased twice as much by the ultrasonic vibration. Using this high accuracy, high speed, and high power microrobot, swine oocyte manipulations are presented in a microfluidic chip.

  14. Variable-Width Datapath for On-Chip Network Static Power Reduction

    Energy Technology Data Exchange (ETDEWEB)

    Michelogiannakis, George; Shalf, John

    2013-11-13

    With the tight power budgets in modern large-scale chips and the unpredictability of application traffic, on-chip network designers are faced with the dilemma of designing for worst- case bandwidth demands and incurring high static power overheads, or designing for an average traffic pattern and risk degrading performance. This paper proposes adaptive bandwidth networks (ABNs) which divide channels and switches into lanes such that the network provides just the bandwidth necessary in each hop. ABNs also activate input virtual channels (VCs) individually and take advantage of drowsy SRAM cells to eliminate false VC activations. In addition, ABNs readily apply to silicon defect tolerance with just the extra cost for detecting faults. For application traffic, ABNs reduce total power consumption by an average of 45percent with comparable performance compared to single-lane power-gated networks, and 33percent compared to multi-network designs.

  15. An Asynchronous Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia

    applied at its endpoints, the NIs. Overall this thesis presents the design and implementation of Argo, and the analysis of its elastic behavior. It shows that Argo provides hard real-time guarantees in a straightforward way, it has an efficient implementation and it is time-elastic....... the elasticity and its limits. A quantitative analysis models the Argo behavior using timed-graph models and worstcase timing separation of events analysis to evaluate the elasticity of Argo. The results show that the skew absorbed by the network of routers can be two or more cycles, depending on the frequency......Multi-processor architectures using networks-on-chip (NOCs) for communication are becoming the standard approach in the development of embedded systems and general purpose platforms. Typically, multi-processor platforms follow a globally asynchronous locally synchronous (GALS) timing organization...

  16. A novel single-step, multipoint calibration method for instrumented Lab-on-Chip systems

    DEFF Research Database (Denmark)

    Pfreundt, Andrea; Patou, François; Zulfiqar, Azeem

    2014-01-01

    Despite recent and substantial advances in biosensing, information and communication, and Lab-on-Chip (LoC) technologies, the success of Point-of-Care (PoC) diagnostics and monitoring systems is still challenged by stringent requirements for robustness, cost-effectiveness, and system integration....... The pitfalls of PoC system adoption can be addressed early in the system design phase. They require a multidisciplinary design approach supported by systems engineering tools and methods. Considering this, we here present both a model and an implementation of a simple and rapid calibration scheme...... for instrument-based PoC blood biomarker analysis systems. Motivated by the complexity of associating high-accuracy biosensing using silicon nanowire field effect transistors with ease of use for the PoC system user, we propose a novel one-step, multipoint calibration method for LoC-based systems. Our approach...

  17. A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

    CERN Document Server

    Fiergolski, Adrian

    2017-01-01

    The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

  18. Perforated hollow-core optical waveguides for on-chip atomic spectroscopy and gas sensing.

    Science.gov (United States)

    Giraud-Carrier, M; Hill, C; Decker, T; Black, J A; Schmidt, H; Hawkins, A

    2016-03-28

    A hollow-core waveguide structure for on-chip atomic spectroscopy is presented. The devices are based on Anti-Resonant Reflecting Optical Waveguides and may be used for a wide variety of applications which rely on the interaction of light with gases and vapors. The designs presented here feature short delivery paths of the atomic vapor into the hollow waveguide. They also have excellent environmental stability by incorporating buried solid-core waveguides to deliver light to the hollow cores. Completed chips were packaged with an Rb source and the F = 3 ≥ F' = 2, 3, 4 transitions of the D2 line in 85 Rb were monitored for optical absorption. Maximum absorption peak depths of 9% were measured.

  19. Lab-On-Chip Clinorotation System for Live-Cell Microscopy Under Simulated Microgravity

    Science.gov (United States)

    Yew, Alvin G.; Atencia, Javier; Chinn, Ben; Hsieh, Adam H.

    2013-01-01

    Cells in microgravity are subject to mechanical unloading and changes to the surrounding chemical environment. How these factors jointly influence cellular function is not well understood. We can investigate their role using ground-based analogues to spaceflight, where mechanical unloading is simulated through the time-averaged nullification of gravity. The prevailing method for cellular microgravity simulation is to use fluid-filled containers called clinostats. However, conventional clinostats are not designed for temporally tracking cell response, nor are they able to establish dynamic fluid environments. To address these needs, we developed a Clinorotation Time-lapse Microscopy (CTM) system that accommodates lab-on- chip cell culture devices for visualizing time-dependent alterations to cellular behavior. For the purpose of demonstrating CTM, we present preliminary results showing time-dependent differences in cell area between human mesenchymal stem cells (hMSCs) under modeled microgravity and normal gravity.

  20. On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers

    Science.gov (United States)

    Chattopadhyay, Goutam; Mehdi, Imran; Schlecht, Erich T.; Lee, Choonsup; Siles, Jose V.; Maestrini, Alain E.; Thomas, Bertrand; Jung, Cecile D.

    2013-01-01

    A 1.6-THz power-combined Schottky frequency tripler was designed to handle approximately 30 mW input power. The design of Schottky-based triplers at this frequency range is mainly constrained by the shrinkage of the waveguide dimensions with frequency and the minimum diode mesa sizes, which limits the maximum number of diodes that can be placed on the chip to no more than two. Hence, multiple-chip power-combined schemes become necessary to increase the power-handling capabilities of high-frequency multipliers. The design presented here overcomes difficulties by performing the power-combining directly on-chip. Four E-probes are located at a single input waveguide in order to equally pump four multiplying structures (featuring two diodes each). The produced output power is then recombined at the output using the same concept.

  1. On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

    Science.gov (United States)

    Siles Perez, Jose Vicente (Inventor); Chattopadhyay, Goutam (Inventor); Lee, Choonsup (Inventor); Schlecht, Erich T. (Inventor); Jung-Kubiak, Cecile D. (Inventor); Mehdi, Imran (Inventor)

    2015-01-01

    A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

  2. On-chip detection of gel transition temperature using a novel micro-thermomechanical method.

    Directory of Open Access Journals (Sweden)

    Tsenguun Byambadorj

    Full Text Available We present a new thermomechanical method and a platform to measure the phase transition temperature at microscale. A thin film metal sensor on a membrane simultaneously measures both temperature and mechanical strain of the sample during heating and cooling cycles. This thermomechanical principle of operation is described in detail. Physical hydrogel samples are prepared as a disc-shaped gels (200 μm thick and 1 mm diameter and placed between an on-chip heater and sensor devices. The sol-gel transition temperature of gelatin solution at various concentrations, used as a model physical hydrogel, shows less than 3% deviation from in-depth rheological results. The developed thermomechanical methodology is promising for precise characterization of phase transition temperature of thermogels at microscale.

  3. A Novel Analytical Model for Network-on-Chip using Semi-Markov Process

    Directory of Open Access Journals (Sweden)

    WANG, J.

    2011-02-01

    Full Text Available Network-on-Chip (NoC communication architecture is proposed to resolve the bottleneck of Multi-processor communication in a single chip. In this paper, a performance analytical model using Semi-Markov Process (SMP is presented to obtain the NoC performance. More precisely, given the related parameters, SMP is used to describe the behavior of each channel and the header flit routing time on each channel can be calculated by analyzing the SMP. Then, the average packet latency in NoC can be calculated. The accuracy of our model is illustrated through simulation. Indeed, the experimental results show that the proposed model can be used to obtain NoC performance and it performs better than the state-of-art models. Therefore, our model can be used as a useful tool to guide the NoC design process.

  4. On-Chip High-Finesse Fabry-Perot Microcavities for Optical Sensing and Quantum Information

    Directory of Open Access Journals (Sweden)

    Mohammad H. Bitarafan

    2017-07-01

    Full Text Available For applications in sensing and cavity-based quantum computing and metrology, open-access Fabry-Perot cavities—with an air or vacuum gap between a pair of high reflectance mirrors—offer important advantages compared to other types of microcavities. For example, they are inherently tunable using MEMS-based actuation strategies, and they enable atomic emitters or target analytes to be located at high field regions of the optical mode. Integration of curved-mirror Fabry-Perot cavities on chips containing electronic, optoelectronic, and optomechanical elements is a topic of emerging importance. Micro-fabrication techniques can be used to create mirrors with small radius-of-curvature, which is a prerequisite for cavities to support stable, small-volume modes. We review recent progress towards chip-based implementation of such cavities, and highlight their potential to address applications in sensing and cavity quantum electrodynamics.

  5. Gain Enhanced On-Chip Folded Dipole Antenna Utilizing Artificial Magnetic Conductor at 94 GHz

    KAUST Repository

    Nafe, Mahmoud

    2017-09-05

    On-chip antennas suffer from low gain values and distorted radiation patterns due to lossy and high permittivity Si substrate. An ideal solution would be to isolate the lossy Si substrate from the antenna through a Perfect Electric Conductor (PEC) ground plane, however the typical CMOS stack up which has multiple metal layers embedded in a thin oxide layer does not permit this. In this work, an Artificial Magnetic Conductor (AMC) reflecting surface has been utilized to isolate the Si substrate from the antenna. Contrary to the previous reports, the AMC structure is completely embedded in the thin oxide layer with the ground plane above the Si substrate. In this approach, the AMC surface acts for the first time as both a reflector and a silicon shield. As a result the antenna radiation pattern is not distorted and its gain is improved by 8 dB. The fabricated prototype demonstrates good impedance and radiation characteristics.

  6. Advances in Sensors-Centric Microprocessors and System-on-Chip

    Directory of Open Access Journals (Sweden)

    Juan A. Gómez-Pulido

    2012-04-01

    Full Text Available Sensors-based systems are nowadays an extended technology for many markets due to their great potential in the collection of data from the environment and the processing of such data for different purposes. A typical example is the wireless sensor devices, where the outer temperature, humidity, luminosity and many other parameters can be acquired, measured and processed in order to build useful and fascinating applications that contribute to human welfare. In this scenario, the processing architectures of the sensors-based systems play a very important role. The requirements that are necessary for many such applications (real-time processing, low-power consumption, reduced size, reliability, security and many others means that research on advanced architectures of Microprocessors and System-on-Chips (SoC is needed to design and implement a successful product. In this sense, there are many challenges and open questions in this area that need to be addressed. [...

  7. A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

    Directory of Open Access Journals (Sweden)

    Onur Derin

    2011-01-01

    propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC. We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

  8. High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors

    Energy Technology Data Exchange (ETDEWEB)

    Deligianni, Hariklia; Gallagher, William J.; Mason, Maurice; O' Sullivan, Eugene J.; Romankiw, Lubomyr T.; Wang, Naigang

    2017-10-17

    An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.

  9. On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

    Science.gov (United States)

    Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

    2017-07-12

    Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

  10. A System on Chip approach to enhanced learning in interdisciplinary robotics

    DEFF Research Database (Denmark)

    Sørensen, Anders Stengaard; Falsig, Simon

    2011-01-01

    the framework in an embedded systems course and various student projects, and have found that it greatly enhance the students abilities to control hardware from software, and dramatically reduce the time spent on software $\\leftrightarrow$ hardware interfacing. As the framework is also scalable, it can support......p, li { white-space: pre-wrap; } To sustain interdisciplinary teaching and learning in the rapidly growing and diversifying field of robotics, we have successfully employed FPGA based System on Chip (SoC) technology to provide abstraction between high level software and low level IO/ and control...... hardware. Our approach is to provides students with a simple FPGA based framework for hardware access, and hardware I/O development, which is independent of computer platform and programming language, and enable the students to add to, or change I/O hardware in accordance with their skills. We have tested...

  11. Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    for receiving results. This allows a stateless and possibly pipelined hardware accelerator to be shared in an interleaved fashion without any form of reservation, and this opens for interesting area-performance trade-offs. The design is developed with a focus on time-predictability, areaefficiency, and FPGA...... in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel...... implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor....

  12. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...... routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower...

  13. Development of a Surface Micromachined On-Chip Flat Disk Micropump

    Directory of Open Access Journals (Sweden)

    M. I. KILANI

    2009-08-01

    Full Text Available The paper presents research progress in the development of a surface micromachined flat disk micropump which employs the viscous and centrifugal effects acting on a layer of fluid sandwiched between a rotating flat disk and a stationary plate. The pump is fabricated monolithically on-chip using Sandia’s Ultraplanar Multilevel MEMS Technology (SUMMiT™ where an electrostatic comb-drive Torsional Ratcheting Actuator (TRA drives the flat disk through a geared transmission. The paper reviews available analytical models for flow geometries similar to that of the described pump, and presents a set of experiments which depict its performance and possible failure modes. Those experiments highlight future research directions in the development of electrostatically-actuated, CMOS-compatible, surface micromachined pumps.

  14. Integration of on-chip peristaltic pumps and injection valves with microchip electrophoresis and electrochemical detection.

    Science.gov (United States)

    Bowen, Amanda L; Martin, R Scott

    2010-08-01

    A microfluidic approach that integrates peristaltic pumping from an on-chip reservoir with injection valves, microchip electrophoresis and electrochemical detection is described. Fabrication and operation of both the peristaltic pumps and injection valves were optimized to ensure efficient pumping and discrete injections. The final device uses the peristaltic pumps to continuously direct sample from a reservoir containing a mixture of analytes to injection valves that are coupled with microchip electrophoresis and amperometric detection. The separation and direct detection of dopamine and norepinephrine were possible with this approach and the utility of the device was demonstrated by monitoring the stimulated release of these neurotransmitters from a layer of cells introduced into the microchip. It is also shown that this pumping/reservoir approach can be expanded to multiple reservoirs and pumps, where one reservoir can be addressed individually or multiple reservoirs sampled simultaneously.

  15. A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End.

    Science.gov (United States)

    Merenda, Massimo; Felini, Corrado; Della Corte, Francesco G

    2018-01-02

    In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern.

  16. Biosensors in Health Care: The Milestones Achieved in Their Development towards Lab-on-Chip-Analysis

    Directory of Open Access Journals (Sweden)

    Suprava Patel

    2016-01-01

    Full Text Available Immense potentiality of biosensors in medical diagnostics has driven scientists in evolution of biosensor technologies and innovating newer tools in time. The cornerstone of the popularity of biosensors in sensing wide range of biomolecules in medical diagnostics is due to their simplicity in operation, higher sensitivity, ability to perform multiplex analysis, and capability to be integrated with different function by the same chip. There remains a huge challenge to meet the demands of performance and yield to its simplicity and affordability. Ultimate goal stands for providing point-of-care testing facility to the remote areas worldwide, particularly the developing countries. It entails continuous development in technology towards multiplexing ability, fabrication, and miniaturization of biosensor devices so that they can provide lab-on-chip-analysis systems to the community.

  17. Biologically-inspired On-chip Learning in Pulsed Neural Networks

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Woodburn, Robin

    1999-01-01

    Self-learning chips to implement many popular ANN (artificial neural network) algorithms are very difficult to design. We explain why this is so and say what lessons previous work teaches us in the design of self-learning systems. We offer a contribution to the "biologically-inspired" approach......, explaining what we mean by this term and providing an example of a robust, self-learning design that can solve simple classical-conditioning tasks, We give details of the design of individual circuits to perform component functions, which can then be combined into a network to solve the task. We argue...... that useful conclusions as to the future of on-chip learning can be drawn from this work....

  18. Optimization of applied voltages for on-chip concentration of DNA using nanoslit

    Science.gov (United States)

    Azuma, Naoki; Itoh, Shintaro; Fukuzawa, Kenji; Zhang, Hedong

    2017-12-01

    On-chip sample concentration is an effective pretreatment to improve the detection sensitivity of lab-on-a-chip devices for biochemical analysis. In a previous study, we successfully achieved DNA sample concentration using a nanoslit fabricated in the microchannel of a device designed for DNA size separation. The nanoslit was a channel with a depth smaller than the diameter of a random coil-shaped DNA molecule. The concentration was achieved using the entropy trap at the boundary between the microchannel and the nanoslit. DNA molecules migrating toward the nanoslit owing to electrophoresis were trapped in front of the nanoslit and the concentration was enhanced over time. In this study, we successfully maximize the molecular concentration by optimizing the applied voltage for electrophoresis and verifying the effect of temperature. In addition, we propose a model formula that predicts the molecular concentration, the validity of which is confirmed through comparison with experimental results.

  19. On-chip switch for reconfigurable mode-multiplexing optical network.

    Science.gov (United States)

    Sun, Chunlei; Yu, Yu; Chen, Guanyu; Zhang, Xinliang

    2016-09-19

    The switching and routing is essential for an advanced and reconfigurable optical network, and great efforts have been done for traditional single-mode system. We propose and demonstrate an on-chip switch compatible with mode-division multiplexing system. By controlling the induced phase difference, the functionalities of dynamically routing data channels can be achieved. The proposed switch is experimentally demonstrated with low insertion loss of ~1 dB and high extinction ratio of ~20 dB over the C-band for OFF-ON switchover. For further demonstration, the non-return-to-zero on-off keying signals at 10 Gb/s carried on the two spatial modes are successfully processed. Open and clear eye diagrams can be observed and the bit error rate measurements indicate a good data routing performance.

  20. Micromachined On-Chip Dielectric Resonator Antenna Operating at 60 GHz

    KAUST Repository

    Sallam, Mai

    2015-06-01

    This paper presents a novel cylindrical Dielectric Resonator Antenna (DRA) suitable for millimeter-wave on-chip systems. The antenna was fabricated from a single high resistivity silicon wafer via micromachining technology. The new antenna was characterized using HFSS and experimentally with good agreement been found between the simulations and experiment. The proposed DRA has good radiation characteristics, where its gain and radiation efficiency are 7 dBi and 79.35%, respectively. These properties are reasonably constant over the working frequency bandwidth of the antenna. The return loss bandwidth was 2.23 GHz, which corresponds to 3.78% around 60 GHz. The antenna was primarily a broadside radiator with -15 dB cross polarization level.

  1. Quantitative design space exploration of routing-switches for Network-on-Chip

    Directory of Open Access Journals (Sweden)

    M. C. Neuenhahn

    2008-05-01

    Full Text Available Future Systems-on-Chip (SoC will consist of many embedded functional units like e.g. embedded processor cores, memories or FPGA like structures. These SoCs will have huge communication demands, which can not be fulfilled by bus-based communication systems. Possible solutions to this problem are so called Networks-on-Chip (NoC.

    These NoCs basically consist of network-interfaces which integrate functional units into the NoC and routing-switches which connect the network-interfaces. Here, VLSI-based routing-switch implementations are presented. The characteristics of these NoCs like performance and costs (e.g. silicon area respectively logic elements, power dissipation depend on a variety of parameters. As a routing-switch is a key component of a NoC, the costs and performance of routing-switches are compared for different parameter combinations. Evaluated parameters are for example data word length, architecture of the routing-switch (parallel vs. centralized implementation and routing-algorithm.

    The performance and costs of routing-switches were evaluated using an FPGA-based NoC-emulator. In addition different routing-switches were implemented using a 90 nm standard-cell library to determine the maximum clock frequency, power-dissipation and area of a VLSI-implementation. The power consumption was determined by simulating the extracted layout of the routing-switches. Finally, these results are benchmarked to other routing-switch implementations like Aetheral and xpipes.

  2. Graphene nanoribbon field effect transistor for nanometer-size on-chip temperature sensor

    Science.gov (United States)

    Banadaki, Yaser M.; Srivastava, Ashok; Sharifi, Safura

    2016-04-01

    Graphene has been extensively investigated as a promising material for various types of high performance sensors due to its large surface-to-volume ratio, remarkably high carrier mobility, high carrier density, high thermal conductivity, extremely high mechanical strength and high signal-to-noise ratio. The power density and the corresponding die temperature can be tremendously high in scaled emerging technology designs, urging the on-chip sensing and controlling of the generated heat in nanometer dimensions. In this paper, we have explored the feasibility of a thin oxide graphene nanoribbon (GNR) as nanometer-size temperature sensor for detecting local on-chip temperature at scaled bias voltages of emerging technology. We have introduced an analytical model for GNR FET for 22nm technology node, which incorporates both thermionic emission of high-energy carriers and band-to-band-tunneling (BTBT) of carriers from drain to channel regions together with different scattering mechanisms due to intrinsic acoustic phonons and optical phonons and line-edge roughness in narrow GNRs. The temperature coefficient of resistivity (TCR) of GNR FET-based temperature sensor shows approximately an order of magnitude higher TCR than large-area graphene FET temperature sensor by accurately choosing of GNR width and bias condition for a temperature set point. At gate bias VGS = 0.55 V, TCR maximizes at room temperature to 2.1×10-2 /K, which is also independent of GNR width, allowing the design of width-free GNR FET for room temperature sensing applications.

  3. Advanced Nanofabrication Process Development for Self-Powered System-on-Chip

    KAUST Repository

    Rojas, Jhonathan Prieto

    2010-11-01

    In this work the development of a Self-Powered System-On-Chip is explored by examining two components of process development in different perspectives. On one side, an energy component is approached from a biochemical standpoint where a Microbial Fuel Cell (MFC) is built with standard microfabrication techniques, displaying a novel electrode based on Carbon Nanotubes (CNTs). The fabrication process involves the formation of a micrometric chamber that hosts an enhanced CNT-based anode. Preliminary results are promising, showing a high current density (113.6mA/m2) compared with other similar cells. Nevertheless many improvements can be done to the main design and further characterization of the anode will give a more complete understanding and bring the device closer to a practical implementation. On a second point of view, nano-patterning through silicon nitride spacer width control is developed, aimed at producing alternative sub-100nm device fabrication with the potential of further scaling thanks to nanowire based structures. These nanostructures are formed from a nano-pattern template, by using a bottom-up fabrication scheme. Uniformity and scalability of the process are demonstrated and its potential described. An estimated area of 0.120μm2 for a 6T-SRAM (Static Random Access Memory) bitcell (6 devices) can be achieved. In summary, by using a novel sustainable energy component and scalable nano-patterning for logic and computing module, this work has successfully collected the essential base knowledge and joined two different elements that synergistically will contribute for the future implementation of a Self-Powered System-on-Chip.

  4. The response of silicon PNCCD sensors with aluminium on-chip filter to visible light, UV- and X-ray radiation

    Energy Technology Data Exchange (ETDEWEB)

    Granato, Stefanie

    2012-10-18

    There are various scientific applications, from astronomical observations to free electron lasers, that make use of X-ray semiconductor detectors like PNCCDs. The PNCCD is a pixelized semiconductor detector for simultaneous X-ray imaging and spectroscopy. For the seven PNCCD cameras of the eROSITA space telescope, a radiation entrance window including an on-chip optical blocking filter has been designed. The blocking filter is a necessity to minimize electron generation by visible light and UV radiation affecting X-ray spectroscopy. A PNCCD with such a blocking filter has not been used so far in astronomy. The following work deals with the analysis of the response of PNCCDs with on-chip filter. This includes the study of photon absorption and emission processes as well as the transport of electrons inside the detector entrance window. Furthermore it comprises the experimental characterization of the detector properties regarding the attenuation of light as well as their X-ray spectral redistribution function and quantum efficiency. With the ability to reveal the involved physical processes, the PNCCD is subject of analysis and measurement device at the same time. In addition to the results of the measurements, simulations of the solid state physics inside the detector are presented. A Geant4 Monte-Carlo code is extended by the treatment of charge loss in the entrance window and is verified by comparison with experimental data. Reproducing the chain of processes from photon absorption to charge collection, this work provides a detailed understanding of the formation of PNCCD spectra. The spectral features observed in the measurements are attributed to their point of origin inside the detector volume and explained by the model. The findings of this work allow high precision analysis of spectra of silicon detectors, e.g. of the eROSITA data, based on the presented detailed spectral response model.

  5. The response of silicon PNCCD sensors with aluminium on-chip filter to visible light, UV- and X-ray radiation

    International Nuclear Information System (INIS)

    Granato, Stefanie

    2012-01-01

    There are various scientific applications, from astronomical observations to free electron lasers, that make use of X-ray semiconductor detectors like PNCCDs. The PNCCD is a pixelized semiconductor detector for simultaneous X-ray imaging and spectroscopy. For the seven PNCCD cameras of the eROSITA space telescope, a radiation entrance window including an on-chip optical blocking filter has been designed. The blocking filter is a necessity to minimize electron generation by visible light and UV radiation affecting X-ray spectroscopy. A PNCCD with such a blocking filter has not been used so far in astronomy. The following work deals with the analysis of the response of PNCCDs with on-chip filter. This includes the study of photon absorption and emission processes as well as the transport of electrons inside the detector entrance window. Furthermore it comprises the experimental characterization of the detector properties regarding the attenuation of light as well as their X-ray spectral redistribution function and quantum efficiency. With the ability to reveal the involved physical processes, the PNCCD is subject of analysis and measurement device at the same time. In addition to the results of the measurements, simulations of the solid state physics inside the detector are presented. A Geant4 Monte-Carlo code is extended by the treatment of charge loss in the entrance window and is verified by comparison with experimental data. Reproducing the chain of processes from photon absorption to charge collection, this work provides a detailed understanding of the formation of PNCCD spectra. The spectral features observed in the measurements are attributed to their point of origin inside the detector volume and explained by the model. The findings of this work allow high precision analysis of spectra of silicon detectors, e.g. of the eROSITA data, based on the presented detailed spectral response model.

  6. On-chip microreactor system for the production of nano-emulsion loaded liposomes: towards targeted delivery of lipophilic drugs

    NARCIS (Netherlands)

    Langelaan, M.L.P.; Emmelkamp, J.; Segers, M.J.A.; Lenting, H.B.M.

    2011-01-01

    An on-chip microreactor system for the production of novel nano-biodevices is presented. This nano-biodevice consists of a nano-emulsion loaded with lipophilic drugs, entrapped in liposomes. These nano-biodevices can be equipped with targeting molecules for higher drug efficiency. The microreactor

  7. A facile method for urinary phenylalanine measurement on paper-based lab-on-chip for PKU therapy monitoring.

    Science.gov (United States)

    Messina, M A; Meli, C; Conoci, S; Petralia, S

    2017-12-04

    A miniaturized paper-based lab-on-chip (LoC) was developed for the facile measurement of urinary Phe (phenylalanine) level on PKU (Phenylketonuria) treated patient. This system permits the monitoring of Phe in a dynamic range concentration of 20-3000 μM.

  8. Rapid, Semiautomated Quantification of Bacterial Cells in Freshwater by Using a Microfluidic Device for On-Chip Staining and Counting▿

    OpenAIRE

    Yamaguchi, Nobuyasu; Torii, Masashi; Uebayashi, Yuko; Nasu, Masao

    2010-01-01

    A microfluidic device-based system for the rapid and semiautomated counting of bacteria in freshwater was fabricated and examined. Bacteria in groundwater and in potable water, as well as starved Escherichia coli O157:H7 spiked in pond water, were able to be on-chip stained and enumerated within 1 h using this system.

  9. On-chip low-profile nano-horn metal-clad optical cavity with much improved performance

    OpenAIRE

    Li, Zheng; Choo, Hyuck

    2014-01-01

    We propose an on-chip nano-horm-shaped metal-clad cavity. The proposed device is 0.8 µm in height-half the size of the previously reported devices— and achieves the quality factor of 1000 and effective volume of 0.31(λ/n)^3.

  10. Fiber free plug and play on-chip scattering cytometer module – for implementation in microfluidic point of care devices

    DEFF Research Database (Denmark)

    Jensen, Thomas Glasdam; Kutter, Jörg Peter

    2010-01-01

    In this paper, we report on recent progress toward the development of a plug and play on-chip cytometer based on light scattering. By developing a device that does not depend on the critical alignment and cumbersome handling of fragile optical fibers, we approach a device that is suitable for non...

  11. On-chip Detection of Rolling Circle Amplified DNA Molecules from Bacillus Globigii spores and Vibrio Cholerae

    DEFF Research Database (Denmark)

    Østerberg, Frederik Westergaard; Rizzi, Giovanni; Donolato, Marco

    2014-01-01

    For the first time DNA coils formed by rolling circle amplification are quantified on-chip by Brownian relaxation measurements on magnetic nanobeads using a magnetoresistive sensor. No external magnetic fields are required besides the magnetic field arising from the current through the sensor...

  12. On-chip patch antenna on InP substrate for short-range wireless communication at 140 GHz

    DEFF Research Database (Denmark)

    Dong, Yunfeng; Johansen, Tom Keinicke; Zhurbenko, Vitaliy

    2017-01-01

    This paper presents the design of an on-chip patch antenna on indium phosphide (InP) substrate for short-range wireless communication at 140 GHz. The antenna shows a simulated gain of 5.3 dBi with 23% bandwidth at 140 GHz and it can be used for either direct chip-to-chip communication or chip...

  13. On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

    NARCIS (Netherlands)

    Zhang, X.; Kerkhoff, Hans G.; Vermeulen, Bart

    2010-01-01

    Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since

  14. Toward improved myocardial maturity in an organ-on-chip platform with immature cardiac myocytes.

    Science.gov (United States)

    Sheehy, Sean P; Grosberg, Anna; Qin, Pu; Behm, David J; Ferrier, John P; Eagleson, Mackenzie A; Nesmith, Alexander P; Krull, David; Falls, James G; Campbell, Patrick H; McCain, Megan L; Willette, Robert N; Hu, Erding; Parker, Kevin K

    2017-11-01

    In vitro studies of cardiac physiology and drug response have traditionally been performed on individual isolated cardiomyocytes or isotropic monolayers of cells that may not mimic desired physiological traits of the laminar adult myocardium. Recent studies have reported a number of advances to Heart-on-a-Chip platforms for the fabrication of more sophisticated engineered myocardium, but cardiomyocyte immaturity remains a challenge. In the anisotropic musculature of the heart, interactions between cardiac myocytes, the extracellular matrix (ECM), and neighboring cells give rise to changes in cell shape and tissue architecture that have been implicated in both development and disease. We hypothesized that engineered myocardium fabricated from cardiac myocytes cultured in vitro could mimic the physiological characteristics and gene expression profile of adult heart muscle. To test this hypothesis, we fabricated engineered myocardium comprised of neonatal rat ventricular myocytes with laminar architectures reminiscent of that observed in the mature heart and compared their sarcomere organization, contractile performance characteristics, and cardiac gene expression profile to that of isolated adult rat ventricular muscle strips. We found that anisotropic engineered myocardium demonstrated a similar degree of global sarcomere alignment, contractile stress output, and inotropic concentration-response to the β-adrenergic agonist isoproterenol. Moreover, the anisotropic engineered myocardium exhibited comparable myofibril related gene expression to muscle strips isolated from adult rat ventricular tissue. These results suggest that tissue architecture serves an important developmental cue for building in vitro model systems of the myocardium that could potentially recapitulate the physiological characteristics of the adult heart. Impact statement With the recent focus on developing in vitro Organ-on-Chip platforms that recapitulate tissue and organ-level physiology

  15. Three-dimensional on-chip continuous-flow polymerase chain reaction employing a single heater.

    Science.gov (United States)

    Wu, Wenming; Lee, Nae Yoon

    2011-06-01

    Multi-step temperature control in a polymerase chain reaction (PCR) is a limiting factor in device miniaturization and portability. In this study, we propose the fabrication of a three-dimensional (3D) microdevice employing a single heater to minimize temperature control required for an on-chip continuous-flow PCR as well as the overall footprint by stacking the device in multi-layers. Two poly(dimethylsiloxane) (PDMS) layers with differing thicknesses are vertically stacked with their microchannel-engraved sides facing down. Through-holes are made in the thicker PDMS layer, which is sandwiched between a glass substrate at the bottom and the thinner PDMS layer at the top. In this way, a fluidic conduit is realized in a 3D configuration. The assembled 3D microdevice is then placed onto a heater glass-side down. The interface of the two PDMS layers displays a relatively lower temperature than that of the PDMS and glass layers due to the low thermal conductivity of the PDMS and its physical distance from the heater. The denaturation temperature can be controlled by adjusting the temperature of the heater, while the annealing/extension temperature can be controlled automatically by molding the thicker bottom PDMS layer into the appropriate thickness calculated using a numerical derivation proposed in this study. In this way, a cumbersome temperature measurement step is eliminated. DNA amplification was successfully carried out using the proposed 3D fluidic microdevice, and the intensity of the resulting amplicon was comparable to that obtained using a thermal cycler. This novel concept of adopting a single heating source greatly simplifies the temperature control issue present in an on-chip continuous-flow PCR. It also allows the use of a commercialized hot plate as a potential heat source, paving the way for device miniaturization and portability in a highly cost-effective manner. In this study, a simple and facile technique to make arrays of through-holes for the

  16. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  17. Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer

    Directory of Open Access Journals (Sweden)

    Alberto Parini

    2012-01-01

    Full Text Available This work presents a bottom-up abstraction procedure based on the design-flow FDTD + SystemC suitable for the modelling of optical Networks-on-Chip. In this procedure, a complex network is decomposed into elementary switching elements whose input-output behavior is described by means of scattering parameters models. The parameters of each elementary block are then determined through 2D-FDTD simulation, and the resulting analytical models are exported within functional blocks in SystemC environment. The inherent modularity and scalability of the S-matrix formalism are preserved inside SystemC, thus allowing the incremental composition and successive characterization of complex topologies typically out of reach for full-vectorial electromagnetic simulators. The consistency of the outlined approach is verified, in the first instance, by performing a SystemC analysis of a four-input, four-output ports switch and making a comparison with the results of 2D-FDTD simulations of the same device. Finally, a further complex network encompassing 160 microrings is investigated, the losses over each routing path are calculated, and the minimum amount of power needed to guarantee an assigned BER is determined. This work is a basic step in the direction of an automatic technology-aware network-level simulation framework capable of assembling complex optical switching fabrics, while at the same time assessing the practical feasibility and effectiveness at the physical/technological level.

  18. Aluminum nitride as nonlinear optical material for on-chip frequency comb generation and frequency conversion

    Directory of Open Access Journals (Sweden)

    Jung Hojoong

    2016-06-01

    Full Text Available A number of dielectric materials have been employed for on-chip frequency comb generation. Silicon based dielectrics such as silicon dioxide (SiO2 and silicon nitride (SiN are particularly attractive comb materials due to their low optical loss and maturity in nanofabrication. They offer third-order Kerr nonlinearity (χ(3, but little second-order Pockels (χ(2 effect. Materials possessing both strong χ(2 and χ(3 are desired to enable selfreferenced frequency combs and active control of comb generation. In this review, we introduce another CMOS-compatible comb material, aluminum nitride (AlN,which offers both second and third order nonlinearities. A review of the advantages of AlN as linear and nonlinear optical material will be provided, and fabrication techniques of low loss AlN waveguides from the visible to infrared (IR region will be discussed.We will then show the frequency comb generation including IR, red, and green combs in high-Q AlN micro-rings from single CW IR laser input via combination of Kerr and Pockels nonlinearity. Finally, the fast speed on-off switching of frequency comb using the Pockels effect of AlN will be shown,which further enriches the applications of the frequency comb.

  19. Programmable System-on-Chip (PSoC) Embedded Readout Designs for Liquid Helium Level Sensors.

    Science.gov (United States)

    Parasakthi, C; Gireesan, K; Usha Rani, R; Sheela, O K; Janawadkar, M P

    2014-08-01

    This article reports the development of programmable system-on-chip (PSoC)-based embedded readout designs for liquid helium level sensors using resistive liquid vapor discriminators. The system has been built for the measurement of liquid helium level in a concave-bottomed, helmet-shaped, fiber-reinforced plastic cryostat for magnetoencephalography. This design incorporates three carbon resistors as cost-effective sensors, which are mounted at desired heights inside the cryostat and were used to infer the liquid helium level by measuring their temperature-dependent resistance. Localized electrical heating of the carbon resistors was used to discriminate whether the resistor is immersed in liquid helium or its vapor by exploiting the difference in the heat transfer rates in the two environments. This report describes a single PSoC chip for the design and development of a constant current source to drive the three carbon resistors, a multiplexer to route the sensor outputs to the analog-to-digital converter (ADC), a buffer to avoid loading of the sensors, an ADC for digitizing the data, and a display using liquid crystal display cum light-emitting diode modules. The level sensor readout designed with a single PSoC chip enables cost-effective and reliable measurement system design. © 2014 Society for Laboratory Automation and Screening.

  20. Performance analysis of general purpose and digital signal processor kernels for heterogeneous systems-on-chip

    Directory of Open Access Journals (Sweden)

    T. von Sydow

    2003-01-01

    Full Text Available Various reasons like technology progress, flexibility demands, shortened product cycle time and shortened time to market have brought up the possibility and necessity to integrate different architecture blocks on one heterogeneous System-on-Chip (SoC. Architecture blocks like programmable processor cores (DSP- and GPP-kernels, embedded FPGAs as well as dedicated macros will be integral parts of such a SoC. Especially programmable architecture blocks and associated optimization techniques are discussed in this contribution. Design space exploration and thus the choice which architecture blocks should be integrated in a SoC is a challenging task. Crucial to this exploration is the evaluation of the application domain characteristics and the costs caused by individual architecture blocks integrated on a SoC. An ATE-cost function has been applied to examine the performance of the aforementioned programmable architecture blocks. Therefore, representative discrete devices have been analyzed. Furthermore, several architecture dependent optimization steps and their effects on the cost ratios are presented.

  1. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    Science.gov (United States)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STAR- Dundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITAR- free and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  2. Integration of systems biology with organs-on-chips to humanize therapeutic development

    Science.gov (United States)

    Edington, Collin D.; Cirit, Murat; Chen, Wen Li Kelly; Clark, Amanda M.; Wells, Alan; Trumper, David L.; Griffith, Linda G.

    2017-02-01

    "Mice are not little people" - a refrain becoming louder as the gaps between animal models and human disease become more apparent. At the same time, three emerging approaches are headed toward integration: powerful systems biology analysis of cell-cell and intracellular signaling networks in patient-derived samples; 3D tissue engineered models of human organ systems, often made from stem cells; and micro-fluidic and meso-fluidic devices that enable living systems to be sustained, perturbed and analyzed for weeks in culture. Integration of these rapidly moving fields has the potential to revolutionize development of therapeutics for complex, chronic diseases, including those that have weak genetic bases and substantial contributions from gene-environment interactions. Technical challenges in modeling complex diseases with "organs on chips" approaches include the need for relatively large tissue masses and organ-organ cross talk to capture systemic effects, such that current microfluidic formats often fail to capture the required scale and complexity for interconnected systems. These constraints drive development of new strategies for designing in vitro models, including perfusing organ models, as well as "mesofluidic" pumping and circulation in platforms connecting several organ systems, to achieve the appropriate physiological relevance.

  3. A programmable microsystem using system-on-chip for real-time biotelemetry.

    Science.gov (United States)

    Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

    2005-07-01

    A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

  4. Design of bus-on-chip core for micro-satellite avionics

    Science.gov (United States)

    Liu, Youjun; You, Zheng; Li, Bin; Zhang, Xiangqi; Meng, Ziyang

    2007-11-01

    This paper discusses a layout of bus-on-chip core referring to SoC thinking which is composed of six sections based on a physical chip of FPGA: multi-Processor cache coherence unit, external bus control module, TT&C module, Ethernet Mac interface, EDAC/DMA module, and AMBA bridges. Multi-processor cache coherence unit, as a key part of the bus core, is used to serve the rapid parallel computing by means of the breakthrough of write/read speed of EMS memory and enhances the reliability of OBC with the service of supporting the hot standby of redundancy and the reconfiguration of fault-tolerance. External bus control module is made to support the PnP of external components applying varieties of buses, which is designed by means of soft-core in order to adapt the variation of macro-design and improve the flexibility of external application. TT&C module is the interface of subsystems of telemetry, telecommand and communication, which involves the protocols of HDLC. Ethernet Mac interface based on TCP/IP acts as the access of ISL for formation flying, constellation, etc. EDAC/DMA module mainly manages the data exchange between AMBA bus and RAM, and assigns DMA for the payloads.

  5. Area and Power Modeling for Networks-on-Chip with Layout Awareness

    Directory of Open Access Journals (Sweden)

    Paolo Meloni

    2007-01-01

    Full Text Available Networks-on-Chip (NoCs are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.

  6. Fishing on chips: up-and-coming technological advances in analysis of zebrafish and Xenopus embryos.

    Science.gov (United States)

    Zhu, Feng; Skommer, Joanna; Huang, Yushi; Akagi, Jin; Adams, Dany; Levin, Michael; Hall, Chris J; Crosier, Philip S; Wlodkowic, Donald

    2014-11-01

    Biotests performed on small vertebrate model organisms provide significant investigative advantages as compared with bioassays that employ cell lines, isolated primary cells, or tissue samples. The main advantage offered by whole-organism approaches is that the effects under study occur in the context of intact physiological milieu, with all its intercellular and multisystem interactions. The gap between the high-throughput cell-based in vitro assays and low-throughput, disproportionally expensive and ethically controversial mammal in vivo tests can be closed by small model organisms such as zebrafish or Xenopus. The optical transparency of their tissues, the ease of genetic manipulation and straightforward husbandry, explain the growing popularity of these model organisms. Nevertheless, despite the potential for miniaturization, automation and subsequent increase in throughput of experimental setups, the manipulation, dispensing and analysis of living fish and frog embryos remain labor-intensive. Recently, a new generation of miniaturized chip-based devices have been developed for zebrafish and Xenopus embryo on-chip culture and experimentation. In this work, we review the critical developments in the field of Lab-on-a-Chip devices designed to alleviate the limits of traditional platforms for studies on zebrafish and clawed frog embryo and larvae. © 2014 International Society for Advancement of Cytometry. © 2014 International Society for Advancement of Cytometry.

  7. Electronic radon monitoring with the CMOS System-on-Chip AlphaRad

    Energy Technology Data Exchange (ETDEWEB)

    Higueret, S. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France); Husson, D. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France)], E-mail: Daniel.Husson@ires.in2p3.fr; Le, T.D.; Nourreddine, A. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France); Michielsen, N. [Institut de Radioprotection et de Surete Nucleaire (IRSN, DSU-SERAC-LPMA), BP 68, 91192 Gif-sur-Yvette Cedex (France)

    2008-01-11

    The development of the integrated circuit AlphaRad as a new System-on-Chip for detection of {alpha}-particles has already been reported. This paper deals with electronic monitoring of atmospheric radon, which is one of the promising applications of the chip. The future electronic radon monitor (ERM) is designed to be compact, inexpensive, operating at low voltage and fully stand-alone. We present here the complete electronic board of the future ERM: it is made of three independent AlphaRad chips running in parallel, mounted on a small printed-circuit board which includes a numeric block for data treatment based on a Xilinx programmable gate array. The maximal counting rate of the AlphaRad chip has been pushed to at least 3x10{sup 6} {alpha}-particles cm{sup -2}. The complete system for detection of the solid aerosols will be published separately, and this paper will focus on the electronic board alone. Already 20 times faster than our first measurement with a CMOS pixel sensor, the system was tested at low and high activities, showing an excellent linearity for {sup 222}Rn levels up to 80 kBq m{sup -3}.

  8. Primary single event effect studies on Xilinx 28-nm System-on-Chip (SoC)

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Yao [Xi’an Jiaotong University, Xi’an, Shaanxi 710049 (China); Liu, Shuhuan, E-mail: shuhuanliu@126.com [Xi’an Jiaotong University, Xi’an, Shaanxi 710049 (China); Du, Xuecheng; Yuan, Yuan; He, Chaohui [Xi’an Jiaotong University, Xi’an, Shaanxi 710049 (China); Ren, Xiaotang [Peking University, Beijing 100000 (China); Du, Xiaozhi; Li, Yonghong [Xi’an Jiaotong University, Xi’an, Shaanxi 710049 (China)

    2016-09-21

    Single Event Effect (SEE) on Xilinx 28-nm System-on-Chip (SoC) was investigated by both simulation and experiments in this study. In the simulation process, typical structure of NAND gate and flip-flop in SoC were designed using Cadence tool. Various kinds of radiation were simulated as pulsed current source in consideration of multilayer wiring and energy loss before reaching the sensitive area. The circuit modules were simulated as SEE occurred and malfunctioned when pulsed current source existed. The changes of the circuit modules output were observed when pulsed current signals were placed at different sensitive nodes or the circuit operated under different conditions. The sensitive nodes in typical modules and the possible reasons of test program malfunction were primarily studied. In the experimental process, SoC chip was irradiated with α particles, protons and laser respectively. The irradiation test results showed that Single Event Upset (SEU) occurred in typical modules of SoC, in accordance with the simulation results.

  9. System on chip thermal vacuum sensor based on standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Li Jinfeng; Tang Zhenan; Wang Jiaqi, E-mail: ljf970204@yahoo.com.c [Department of Electronic Engineering, Dalian University of Technology, Dalian 116024 (China)

    2009-03-15

    An on-chip microelectromechanical system was fabricated in a 0.5 mum standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 10{sup 5} Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/ Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 omega resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  10. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Energy Technology Data Exchange (ETDEWEB)

    Claus, R., E-mail: claus@slac.stanford.edu

    2016-07-11

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  11. The System Power Control Unit Based on the On-Chip Wireless Communication System

    Directory of Open Access Journals (Sweden)

    Tiefeng Li

    2013-01-01

    Full Text Available Currently, the on-chip wireless communication system (OWCS includes 2nd-generation (2G, 3rd-generation (3G, and long-term evolution (LTE communication subsystems. To improve the power consumption of OWCS, a typical architecture design of system power control unit (SPCU is given in this paper, which can not only make a 2G, a 3G, and an LTE subsystems enter sleep mode, but it can also wake them up from sleep mode via the interrupt. During the sleep mode period, either the real-time sleep timer or the global system for mobile (GSM communication sleep timer can be used individually to arouse the corresponding subsystem. Compared to previous sole voltage supplies on the OWCS, a 2G, a 3G, or an LTE subsystem can be independently configured with three different voltages and frequencies in normal work mode. In the meantime, the voltage supply monitor, which is an important part in the SPCU, can significantly guard the voltage of OWCS in real time. Finally, the SPCU may implement dynamic voltage and frequency scaling (DVFS for a 2G, a 3G, or an LTE subsystem, which is automatically accomplished by the hardware.

  12. Time-of-flight thermal flowrate sensor for lab-on-chip applications.

    Science.gov (United States)

    Berthet, Helene; Jundt, Jacques; Durivault, Jerome; Mercier, Bruno; Angelescu, Dan

    2011-01-21

    We describe a thermal microflowrate sensor for measuring liquid flow velocity in microfluidic channels, which is capable of providing a highly accurate response independent of the thermal and physical properties of the working liquid. The sensor consists of a rectangular channel containing a heater and several temperature detectors microfabricated on suspended silicon bridges. Heat pulses created by the heater are advected downstream by the flow and are detected using the temperature detector bridges. By injecting a pseudo-stochastic thermal signal at the heater and performing a cross correlation between the detected and the injected signals, we can measure the single-pulse response of the system with excellent signal-to-noise ratio and hence deduce the thermal signal time-of-flight from heater to detector. Combining results from several detector bridges allows us to eliminate diffusion effects, and thus calculate the flow velocity with excellent accuracy and linearity over more than two orders of magnitude. The experimental results obtained with several test fluids closely agree with data from finite element analysis. We developed a phenomenological model which supports and explains the observed sensor response. Several fully functional sensor prototypes were built and characterized, proving the feasibility and providing a critical component to microfluidic lab-on-chip applications where accurate flow measurements are of importance.

  13. On-Chip All-Optical Switching and Memory by Silicon Photonic Crystal Nanocavities

    Directory of Open Access Journals (Sweden)

    Masaya Notomi

    2008-01-01

    Full Text Available We review our recent studies on all-optical switching and memory operations based on thermo-optic and carrier-plasma nonlinearities both induced by two-photon absorption in silicon photonic crystal nanocavities. Owing to high-Q and small volume of these photonic crystal cavities, we have demonstrated that the switching power can be largely reduced. In addition, we demonstrate that the switching time is also reduced in nanocavity devices because of their short diffusion time. These features are important for all-optical nonlinear processing in silicon photonics technologies, since silicon is not an efficient optical nonlinear material. We discuss the effect of the carrier diffusion process in our devices, and demonstrate improvement in terms of the response speed by employing ion-implantation process. Finally, we show that coupled bistable devices lead to all-optical logic, such as flip-flop operation. These results indicate that a nanocavity-based photonic crystal platform on a silicon chip may be a promising candidate for future on-chip all-optical information processing in a largely integrated fashion.

  14. Real-time machine vision FPGA implementation for microfluidic monitoring on Lab-on-Chips.

    Science.gov (United States)

    Sotiropoulou, Calliope-Louisa; Voudouris, Liberis; Gentsos, Christos; Demiris, Athanasios M; Vassiliadis, Nikolaos; Nikolaidis, Spyridon

    2014-04-01

    A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring on Lab-On-Chips is presented in this paper. The machine vision system is designed to follow continuous or plug flows, for which the menisci of the fluids are always visible. The system discriminates between the front or "head" of the flow and the back or "tail" and is able to follow flows with a maximum speed of 20 mm/sec in circular channels of a diameter of 200 μm (corresponding to approx. 60 μl/sec ). It is designed to be part of a complete Point-of-Care system, which will be portable and operate in non-ideal laboratory conditions. Thus, it is able to cope with noise due to lighting conditions and small LoC displacements during the experiment execution. The machine vision system can be used for a variety of LoC devices, without the need for fiducial markers (such as redundancy patterns) for its operation. The underlying application requirements called for a complete hardware implementation. The architecture uses a variety of techniques to improve performance and minimize memory access requirements. The system input is 8 bit grayscale uncompressed video of up to 1 Mpixel resolution. The system uses an operating frequency of 170 Mhz and achieves a computational time of 13.97 ms (worst case), which leads to a throughput of 71.6 fps for 1 Mpixel video resolution.

  15. On-chip bio-analyte detection utilizing the velocity of magnetic microparticles in a fluid

    KAUST Repository

    Giouroudi, Ioanna

    2011-03-22

    A biosensing principle utilizing the motion of suspended magnetic microparticles in a microfluidic system is presented. The system utilizes the innovative concept of the velocity dependence of magnetic microparticles (MPs) due to their volumetric change when analyte is attached to their surface via antibody–antigen binding. When the magnetic microparticles are attracted by a magnetic field within a microfluidic channel their velocity depends on the presence of analyte. Specifically, their velocity decreases drastically when the magnetic microparticles are covered by (nonmagnetic) analyte (LMPs) due to the increased drag force in the opposite direction to that of the magnetic force. Experiments were carried out as a proof of concept. A promising 52% decrease in the velocity of the LMPs in comparison to that of the MPs was measured when both of them were accelerated inside a microfluidic channel using an external permanent magnet. The presented biosensing methodology offers a compact and integrated solution for a new kind of on-chip analysis with potentially high sensitivity and shorter acquisition time than conventional laboratory based systems.

  16. On-chip free beam optics on a polymer-based photonic integration platform.

    Science.gov (United States)

    Happach, M; de Felipe, D; Conradi, H; Friedhoff, V N; Schwartz, E; Kleinert, M; Brinker, W; Zawadzki, C; Keil, N; Hofmann, W; Schell, M

    2017-10-30

    This paper presents on-chip free beam optics on polymer-based photonic components. Due to the circumstance that waveguide-based optics allows no direct beam access we use Gradient index (GRIN) lenses assembled into the chip to collimate the beam from the waveguides. This enables low loss power transmission over a length of 1432 µm. Even though the beam propagates through air it is possible to create a resonator with a wavelength shift of 0.002 nm/°C, hence the allowed deviations from the ITU-T grid (100 GHz) are met for ± 20 °C. In order to guarantee reliable laser stability, it is necessary to implement optical isolators at the output of the laser. This requires the insertion of bulk material into the chip and is realized by a 1050 µm thick coated glass. Due to the large gap of the free-space section, it is possible to combine different resonators together. This demonstrates the feasibility of an integrated wavelength-meter.

  17. On-chip immunoassay of a cardiac biomarker in serum using a polyester-toner microchip.

    Science.gov (United States)

    Kim, Ah Rahn; Kim, Joo Yeon; Choi, Kihwan; Chung, Doo Soo

    2013-05-15

    An on-chip immunoassay to detect C-reactive protein (CRP) was performed using a polyester-toner (PT) microchip. CRP is a highly conserved plasma protein responding to inflammation and is used for clinical purposes to diagnose an inflammatory state. For rapid analysis and specific interactions in immunoassays, extensive studies using microfluidic chips have been carried out. Recently, a simple technique to fabricate a disposable PT microchip by a direct printing process was developed and several applications were introduced. One major drawback of the PT microchip, however, is the poor separation performance due to the quality of the microfluidic structures. This problem for a PT microchip can be overcome using a cleavable tag immunoassay, which requires minimal separation performance. After analytes are conjugated onto antibodies which are immobilized on the surface of microbeads placed on the PT microchip, a second group of fluorescently tagged antibodies are added and complexed with the analytes. The tag is then cleaved and the solution containing the cleaved tag is analyzed by electrophoresis. The time needed for the complete analysis to be carried out on a PT microchip was less than 35 min. The dynamic range of the CRP in 10-fold diluted serum was 0.3-100 mg/L and the limit of detection was 0.3 mg/L, which demonstrated the possibility of a quantitative analysis of CRP in serum in clinical trials. Copyright © 2013 Elsevier B.V. All rights reserved.

  18. Analog Multilayer Perceptron Circuit with On-chip Learning: Portable Electronic Nose

    Science.gov (United States)

    Pan, Chih-Heng; Tang, Kea-Tiong

    2011-09-01

    This article presents an analog multilayer perceptron (MLP) neural network circuit with on-chip back propagation learning. This low power and small area analog MLP circuit is proposed to implement as a classifier in an electronic nose (E-nose). Comparing with the E-nose using microprocessor or FPGA as a classifier, the E-nose applying analog circuit as a classifier can be faster and much smaller, demonstrate greater power efficiency and be capable of developing a portable E-nose [1]. The system contains four inputs, four hidden neurons, and only one output neuron; this simple structure allows the circuit to have a smaller area and less power consumption. The circuit is fabricated using TSMC 0.18 μm 1P6M CMOS process with 1.8 V supply voltage. The area of this chip is 1.353×1.353 mm2 and the power consumption is 0.54 mW. Post-layout simulations show that the proposed analog MLP circuit can be successively trained to identify three kinds of fruit odors.

  19. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    International Nuclear Information System (INIS)

    Claus, R.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  20. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    ATLAS CSC Collaboration; The ATLAS collaboration

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

  1. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)664042

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

  2. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

    2016-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

  3. Low-Cost Allocator Implementations for Networks-on-Chip Routers

    Directory of Open Access Journals (Sweden)

    Min Zhang

    2009-01-01

    Full Text Available Cost-effective Networks-on-Chip (NoCs routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA and the generic switch allocator (SA of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

  4. A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

    Science.gov (United States)

    Claus, R.; ATLAS Collaboration

    2016-07-01

    The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

  5. Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  6. On-Chip Testing Schemes of Through-Silicon-Vias (TSVs in 3D Stacked ICs

    Directory of Open Access Journals (Sweden)

    Shadi MS. Harb

    2017-07-01

    Full Text Available This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs in 3D ICs technology. 3D Gunning Transceiver Logic (GTL I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient performance of TSVs. In addition, Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ring-based oscillator test structure is proposed and simulated based on a high performance fully tunable electrical circuit pi-model where a single and coupled TSVs with ground-signal-ground (GSG and ground-signal-signal-ground (GSSG 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. Simulation results are presented using the Keysight/Agilent Advance Design System (ADS and a standard 0.25 µm CMOS process.

  7. A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

    CERN Document Server

    Claus, Richard; The ATLAS collaboration

    2015-01-01

    The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thro...

  8. On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices.

    Science.gov (United States)

    Zhao, Wenfeng; Sun, Biao; Wu, Tong; Yang, Zhi

    2018-02-01

    On-chip neural data compression is an enabling technique for wireless neural interfaces that suffer from insufficient bandwidth and power budgets to transmit the raw data. The data compression algorithm and its implementation should be power and area efficient and functionally reliable over different datasets. Compressed sensing is an emerging technique that has been applied to compress various neurophysiological data. However, the state-of-the-art compressed sensing (CS) encoders leverage random but dense binary measurement matrices, which incur substantial implementation costs on both power and area that could offset the benefits from the reduced wireless data rate. In this paper, we propose two CS encoder designs based on sparse measurement matrices that could lead to efficient hardware implementation. Specifically, two different approaches for the construction of sparse measurement matrices, i.e., the deterministic quasi-cyclic array code (QCAC) matrix and -sparse random binary matrix [-SRBM] are exploited. We demonstrate that the proposed CS encoders lead to comparable recovery performance. And efficient VLSI architecture designs are proposed for QCAC-CS and -SRBM encoders with reduced area and total power consumption.

  9. Improving lumen maintenance by nanopore array dispersed quantum dots for on-chip light emitting diodes

    Science.gov (United States)

    Chen, Quan; Yang, Fan; Wan, Renzhuo; Fang, Dong

    2017-12-01

    The temperature stability of quantum dots (QDs), which is crucial for integrating into high power light-emitting diodes (LEDs) in the on-chip configuration, needs to be further improved. In this letter, we report warm white LEDs, where CdSe/ZnS nanoparticles were incorporated into a porous anodic alumina (PAA) matrix with a chain structure by the self-assembly method. Experiments demonstrate that the QD concentration range in toluene solvent from 1% mg/μl to 1.2% mg/μl in combination with the PAA matrix shows the best luminous property. To verify the reliability of the as-prepared device, a comparison experiment was conducted. It indicates excellent lumen maintenance of the light source and less chromaticity coordinate shift under accelerated life testing conditions. Experiments also prove that optical depreciation was only up to 4.6% of its initial value after the 1500 h aging test at the junction temperature of 76 °C.

  10. Mimicking the Kidney: A Key Role in Organ-on-Chip Development

    Directory of Open Access Journals (Sweden)

    Roberto Paoli

    2016-07-01

    Full Text Available Pharmaceutical drug screening and research into diseases call for significant improvement in the effectiveness of current in vitro models. Better models would reduce the likelihood of costly failures at later drug development stages, while limiting or possibly even avoiding the use of animal models. In this regard, promising advances have recently been made by the so-called “organ-on-chip” (OOC technology. By combining cell culture with microfluidics, biomedical researchers have started to develop microengineered models of the functional units of human organs. With the capacity to mimic physiological microenvironments and vascular perfusion, OOC devices allow the reproduction of tissue- and organ-level functions. When considering drug testing, nephrotoxicity is a major cause of attrition during pre-clinical, clinical, and post-approval stages. Renal toxicity accounts for 19% of total dropouts during phase III drug evaluation—more than half the drugs abandoned because of safety concerns. Mimicking the functional unit of the kidney, namely the nephron, is therefore a crucial objective. Here we provide an extensive review of the studies focused on the development of a nephron-on-chip device.

  11. Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

    DEFF Research Database (Denmark)

    Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly

    2016-01-01

    -pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz...... was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA(1/2), which is superior among microcavity lasers. This shows a high potential for a very high speed at low......For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have...

  12. On-Chip Facile Preparation of Monodisperse Resorcinol Formaldehyde (RF Resin Microspheres

    Directory of Open Access Journals (Sweden)

    Jianmei Wang

    2018-01-01

    Full Text Available Monodisperse resorcinol formaldehyde resin (RF microspheres are an important polymeric material because of their rich surface functional group and uniform structural characteristics and have been increasingly applied as an electrode material, catalyst support, absorbent, and carbon microsphere precursor. The polymerization conditions, such as the gelation/solidification temperature and the residence time, can largely influence the physical properties and the formation of the 3D polymeric network of the RF microspheres as well as the carbon microspheres. However, few studies have reported on the complexity of the gelation and solidification processes of resol. In this work, we developed a new RF microsphere preparation device that contains three units: a droplet generation unit, a curing unit, and a collection unit. In this system, we controlled the gelation and solidification processes of the resol and observed its curing behavior, which helped us to uncover the curing mechanism of resol. Finally, we obtained the optimized polymerization parameters, obtaining uniform RF microspheres with a variation coefficient of 4.94%. The prepared porous RF microspheres presented a high absorption ability, reaching ~90% at 10 min. Thus, our method demonstrated the practicality of on-chip monodisperse microspheres synthesis. The product was useful in drug delivery and adsorbing large poisonous molecules.

  13. Systems-on-chip approach for real-time simulation of wheel-rail contact laws

    Science.gov (United States)

    Mei, T. X.; Zhou, Y. J.

    2013-04-01

    This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

  14. Optical biosensor based on a silicon nanowire ridge waveguide for lab on chip applications

    Science.gov (United States)

    Gamal, Rania; Ismail, Yehea; Swillam, Mohamed A.

    2015-04-01

    We propose a novel sensor using a silicon nanowire ridge waveguide (SNRW). This waveguide is comprised of an array of silicon nanowires on an insulator substrate that has the envelope of a ridge waveguide. The SNRW inherently maximizes the overlap between the material-under-test and the incident light wave by introducing voids to the otherwise bulk structure. When a sensing sample is injected, the voids within the SNRW adopt the refractive index of the material-under-test. Hence, the strong contribution of the material-under-test to the overall modal effective index will greatly augment the sensitivity. Additionally, the ridge structure provides a fabrication convenience as it covers the entire substrate, ensuring that the etching process would not damage the substrate. Finite-difference time-domain simulations are conducted and showed that the percentage change in the effective index due to a 1% change in the surrounding environment is more than 170 times the change perceived in an evanescent-detection based bulk silicon ridge waveguide. Moreover, the SNRW proves to be more sensitive than recent other, non-evanescent sensors. In addition, the detection limit for this structure was revealed to be as small as 10-8. A compact bimodal waveguide based on SNRW is designed and tested. It delivers high sensitivity values that offer comparable performance to similar low-index light-guiding sensing configurations; however, our proposed structure has much smaller footprints and allows high dense integration for lab-on-chip applications.

  15. A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

    Directory of Open Access Journals (Sweden)

    Amir Charif

    2017-01-01

    Full Text Available 3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV, 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlock-free routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

  16. Integrated confocal Raman probe combined with a free-form reflector based lab-on-chip

    Science.gov (United States)

    Liu, Qing; Barbieri, Giancarlo; Thienpont, Hugo; Ottevaere, Heidi

    2017-08-01

    Raman spectroscopy is a powerful tool for analytical measurements in many applications. Traditional Raman spectroscopic analyses require bulky equipment, considerable time of signal acquisition and manual sampling of substances under test. In this paper, we take a step from bulky and manual consuming laboratory testing towards lab-on-chip (LOC) analyses. We miniaturize the Raman spectroscopic system by combining a free-form reflector based polymer LOC with a customized Raman probe. By using the confocal detection principle, we aim to enhance the detection of the Raman signals from the substance of interest due to the suppression of the background Raman signal from the polymer of the chip. Next to the LOC we miniaturize the external optical components, surrounding the reflector embedding optofluidic chip, and assemble these in a Raman probe. We evaluate the misalignment tolerance of internal optics (LOC) and external optics (Raman probe) by non-sequential ray tracing which shows that off-axis misalignment is around ±400μm and the maximum working distance of our Raman probe is 71mm. Using this probe, the system could be implemented as a portable reader unit containing the external optics, in which a low-cost, robust and mass manufacturable microfluidic LOC containing a freeform reflector is inserted, to enable confocal Raman spectroscopy measurements.

  17. Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

    Directory of Open Access Journals (Sweden)

    Wu Hao

    2017-01-01

    Full Text Available We propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG, which consists of a metal strip, a silicon core, and a silicon oxide (SiO2 insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

  18. A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis

    Directory of Open Access Journals (Sweden)

    Shirish Bahirat

    2016-05-01

    Full Text Available Network on Chip (NoC architectures have emerged in recent years as scalable communication fabrics to enable high bandwidth data transfers in chip multiprocessors (CMPs. These interconnection architectures still need to conquer many challenges, e.g., significant power consumption and high data transfer latencies. Hybrid electro-photonic NoCs have been recently proposed as a solution to mitigate some of these challenges. However, with increasing application complexity, hardware dependencies, and performance variability, optimization of hybrid photonic NoCs requires traversing a massive design space. To date, prior work on software tools for rapid automated NoC synthesis have mainly focused on electrical NoCs. In this article, we propose a novel suite of software tools for effectively synthesizing hybrid photonic NoCs. We formulate and solve the synthesis problem using four search-based optimization heuristics: (1 Ant Colony Optimization (ACO; (2 Particle Swarm Optimization (PSO; (3 Genetic Algorithm (GA; and (4 Simulated Annealing (SA. Our experimental results show significant promise for the ACO and PSO based heuristics. Our novel implementation of PSO achieves an average of 64% energy-delay product improvements over GA and 53% improvement over SA; while our novel ACO implementation achieves 107% energy-delay product improvements over GA and 62% improvement over SA.

  19. An Impedance-Based Mold Sensor with on-Chip Optical Reference

    Directory of Open Access Journals (Sweden)

    Poornachandra Papireddy Vinayaka

    2016-09-01

    Full Text Available A new miniaturized sensor system with an internal optical reference for the detection of mold growth is presented. The sensor chip comprises a reaction chamber provided with a culture medium that promotes the growth of mold species from mold spores. The mold detection is performed by measuring impedance changes with integrated electrodes fabricated inside the reaction chamber. The impedance change in the culture medium is caused by shifts in the pH (i.e., from 5.5 to 8 as the mold grows. In order to determine the absolute pH value without the need for calibration, a methyl red indicator dye has been added to the culture medium. It changes the color of the medium as the pH passes specific values. This colorimetric principle now acts as a reference measurement. It also allows the sensitivity of the impedance sensor to be established in terms of impedance change per pH unit. Major mold species that are involved in the contamination of food, paper and indoor environments, like Fusarium oxysporum, Fusarium incarnatum, Eurotium amstelodami, Aspergillus penicillioides and Aspergillus restrictus, have been successfully analyzed on-chip.

  20. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  1. Engineering challenges for instrumenting and controlling integrated organ-on-chip systems.

    Science.gov (United States)

    Wikswo, John P; Block, Frank E; Cliffel, David E; Goodwin, Cody R; Marasco, Christina C; Markov, Dmitry A; McLean, David L; McLean, John A; McKenzie, Jennifer R; Reiserer, Ronald S; Samson, Philip C; Schaffer, David K; Seale, Kevin T; Sherrod, Stacy D

    2013-03-01

    The sophistication and success of recently reported microfabricated organs-on-chips and human organ constructs have made it possible to design scaled and interconnected organ systems that may significantly augment the current drug development pipeline and lead to advances in systems biology. Physiologically realistic live microHuman (μHu) and milliHuman (mHu) systems operating for weeks to months present exciting and important engineering challenges such as determining the appropriate size for each organ to ensure appropriate relative organ functional activity, achieving appropriate cell density, providing the requisite universal perfusion media, sensing the breadth of physiological responses, and maintaining stable control of the entire system, while maintaining fluid scaling that consists of ~5 mL for the mHu and ~5 μL for the μHu. We believe that successful mHu and μHu systems for drug development and systems biology will require low-volume microdevices that support chemical signaling, microfabricated pumps, valves and microformulators, automated optical microscopy, electrochemical sensors for rapid metabolic assessment, ion mobility-mass spectrometry for real-time molecular analysis, advanced bioinformatics, and machine learning algorithms for automated model inference and integrated electronic control. Toward this goal, we are building functional prototype components and are working toward top-down system integration.

  2. Performance of an on-chip superconducting circulator for quantum microwave systems

    Science.gov (United States)

    Chapman, Benjamin; Rosenthal, Eric; Moores, Bradley; Kerckhoff, Joseph; Mates, J. A. B.; Hilton, G. C.; Vale, L. R.; Ullom, J. N.; LalumíEre, Kevin; Blais, Alexandre; Lehnert, K. W.

    Microwave circulators enforce a single propagation direction for signals in an electrical network. Unfortunately, commercial circulators are bulky, lossy, and cannot be integrated close to superconducting circuits because they require strong ( kOe) magnetic fields produced by permanent magnets. Here we report on the performance of an on-chip, active circulator for superconducting microwave circuits, which uses no permanent magnets. Non-reciprocity is achieved by actively modulating reactive elements around 100 MHz, giving roughly a factor of 50 in the separation between signal and control frequencies, which facilitates filtering. The circulator's active components are dynamically tunable inductors constructed with arrays of dc-SQUIDs in series. Array inductance is tuned by varying the magnetic flux through the SQUIDs with fields weaker than 1 Oe. Although the instantaneous bandwidth of the device is narrow, the operation frequency is tunable between 4 and 8 GHz. This presentation will describe the device's theory of operation and compare its measured performance to design goals. This work is supported by the ARO under contract W911NF-14-1-0079 and the National Science Foundation under Grant Number 1125844.

  3. A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones

    Science.gov (United States)

    Le, Huy-Binh; Ryu, Seung-Tak; Lee, Sang-Gug

    An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18µm CMOS technology, and the simulation results show 86dB of dynamic range with 4.5µVrms of input-referred noise for an audio bandwidth of 20kHz and a total harmonic distortion (THD) of 1% at 90mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95dB at 1kHz. The proposed design dissipates 125µA and can operate over a wide supply voltage range of 1.6V to 3.3V.

  4. On-chip mitochondrial assay microfluidic devices and protein nanopore/nanotube hybrid transistor

    Science.gov (United States)

    Lim, Taesun

    Tremendous efforts to understand the cause, mechanism of development and the way to treat various diseases as well as an early diagnosis have been made so far and people are still working hardly on these researches. Even now, countless people are suffering from diseases such as Alzhemer's disease, Parkinson's disease, diabetes and cancer without knowing clues to cure their diseases completely. Generally speaking, we still have a long way to go through to comprehensively figure out these our long-lasting homeworks. One of possible solutions is to merge current advanced technology and science together to find a powerful synergetic effect for a specific purpose that can be tailored depending on user's need. Here this research tried to put nanotechnology and biological science together to find a way to resolve current challenges by developing a new generation of the analytical sensing device. Mitochondrial functions and biological roles in regulating life and death control will be discussed indicating mitochondrion is a crucial organism to monitor to obtain important information regarding degenerative diseases and aging process. On-chip mitochondrial functional assay microsensor that could facilitate the mitochondrial evaluation will be extensively demonstrated and discussed in both technical and biological perspectives. The novel fusion technological approach will be demonstrated by combining artificial cell membrane with carbon nanotube electronics to interrogate interactions between biomolecules and electronic circuitries. In addition, molecular dynamics at the cell membrane could be investigated closely which can help understand the cell-cell communication and the regulation of ion transport.

  5. New movable plate for efficient millimeter wave vertical on-chip antenna

    KAUST Repository

    Marnat, Loic

    2013-04-01

    A new movable plate concept is presented in this paper to realize mm-wave vertical on-chip antennas through MEMS based post-processing steps in a CMOS compatible process. By virtue of its vertical position, the antenna is isolated from the lossy Si substrate and hence performs with a better efficiency as compared to the horizontal position. In addition, the movable plate concept enables polarization diversity by providing both horizontal and vertical polarizations on the same chip. Through a first iteration fractal bowtie antenna design, dual band (60 and 77 GHz) operation is demonstrated in both horizontal and vertical positions without any change in dimensions or use of switches for two different mediums (Si and air). To support the movable plate concept, the transmission line and antenna are designed on a flexible polyamide, where the former has been optimized to operate in the bent position. The design is highly suitable for compact, low cost and efficient SoC solutions. © 1963-2012 IEEE.

  6. Statistical Investigation of the Mechanical and Geometrical Properties of Polysilicon Films through On-Chip Tests

    Directory of Open Access Journals (Sweden)

    Ramin Mirzazadeh

    2018-01-01

    Full Text Available In this work, we provide a numerical/experimental investigation of the micromechanics-induced scattered response of a polysilicon on-chip MEMS testing device, whose moving structure is constituted by a slender cantilever supporting a massive perforated plate. The geometry of the cantilever was specifically designed to emphasize the micromechanical effects, in compliance with the process constraints. To assess the effects of the variability of polysilicon morphology and of geometrical imperfections on the experimentally observed nonlinear sensor response, we adopt statistical Monte Carlo analyses resting on a coupled electromechanical finite element model of the device. For each analysis, the polysilicon morphology was digitally built through a Voronoi tessellation of the moving structure, whose geometry was in turn varied by sampling out of a uniform probability density function the value of the over-etch, considered as the main source of geometrical imperfections. The comparison between the statistics of numerical and experimental results is adopted to assess the relative significance of the uncertainties linked to variations in the micro-fabrication process, and the mechanical film properties due to the polysilicon morphology.

  7. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  8. Semipolar III–nitride quantum well waveguide photodetector integrated with laser diode for on-chip photonic system

    KAUST Repository

    Shen, Chao

    2017-02-28

    A high-performance waveguide photodetector (WPD) integrated with a laser diode (LD) sharing the single InGaN/GaN quantum well active region is demonstrated on a semipolar GaN substrate. The photocurrent of the integrated WPD is effectively tuned by the emitted optical power from the LD. The responsivity ranges from 0.018 to 0.051 A/W with increasing reverse bias from 0 to 10 V. The WPD shows a large 3 dB modulation bandwidth of 230 MHz. The integrated device, being used for power monitoring and on-chip communication, paves the way towards the eventual realization of a III–nitride on-chip photonic system.

  9. Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks

    Science.gov (United States)

    Zhou, Linjie; Djordjevic, Stevan S.; Proietti, Roberto; Ding, Dan; Yoo, S. J. B.; Amirtharajah, Rajeevan; Akella, Venkatesh

    2009-06-01

    With recent advances in silicon nanophotonics, optical crossbars based on CMOS-compatible microring resonators have emerged as viable on-chip optical interconnection networks to deliver high-bandwidth communication at low power dissipation with a small footprint. This paper describes the design, fabrication and evaluation of an arbitration-free passive crossbar based on a microring resonator matrix that can be used to route wavelength division multiplexing (WDM) signals across the chip. The salient feature of the proposed design is the ability to support multicasting and many-to-one communication efficiently (without arbitration), which makes it suitable for implementing cache coherency protocols and on-chip interconnect in future many-core processors.

  10. Gain enhancement of low profile on-chip dipole antenna via Artificial Magnetic Conductor at 94 GHz

    KAUST Repository

    Nafe, Mahmoud

    2015-04-13

    The bottleneck for realizing high efficiency System-on-Chip is integrating the antenna on the lossy silicon substrate. To shield the antenna from the silicon, a ground plane can be used. However, the ultra-thin oxide does not provide enough separation between the antenna and the ground plane. In this work, we demonstrate one of the highest reported gains to date for low profile 94 GHz on-chip dipole antenna while the ground plane is in the lowest metal in the oxide (M1). This is achieved by optimizing an Artificial Magnetic Conductor (AMC) structure midway the antenna and M1. The dipole antenna without the AMC has a gain of − 11 dBi while with the AMC structure a gain of + 4.8 dBi and hence achieving a gain enhancement of + 15.8 dB.

  11. On-chip single-copy real-time reverse-transcription PCR in isolated picoliter droplets

    Energy Technology Data Exchange (ETDEWEB)

    Beer, N R; Wheeler, E; Lee-Houghton, L; Watkins, N; Nasarabadi, S; Hebert, N; Leung, P; Arnold, D; Bailey, C; Colston, B

    2007-12-19

    The first lab-on-chip system for picoliter droplet generation and RNA isolation, followed by reverse transcription, and PCR amplification with real-time fluorescence detection in the trapped droplets has been developed. The system utilized a shearing T-junction in a fused silica device to generate a stream of monodisperse picoliter-scale droplets that were isolated from the microfluidic channel walls and each other by the oil phase carrier. An off-chip valving system stopped the droplets on-chip, allowing thermal cycling for reverse transcription and subsequent PCR amplification without droplet motion. This combination of the established real-time reverse transcription-PCR assay with digital microfluidics is ideal for isolating single-copy RNA and virions from a complex environment, and will be useful in viral discovery and gene-profiling applications.

  12. A system-on-chip digital pH meter for use in a wireless diagnostic capsule.

    Science.gov (United States)

    Hammond, Paul A; Ali, Danish; Cumming, David R S

    2005-04-01

    This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units.

  13. Biomimetic engineering of a generic cell-on-membrane architecture by microfluidic engraving for on-chip bioassays.

    Science.gov (United States)

    Lee, Sang-Wook; Noh, Ji-Yoon; Park, Seung Chul; Chung, Jin-Ho; Lee, Byoungho; Lee, Sin-Doo

    2012-05-22

    We develop a biomimetic cell-on-membrane architecture in close-volume format which allows the interfacial biocompatibility and the reagent delivery capability for on-chip bioassays. The key concept lies in the microfluidic engraving of lipid membranes together with biological cells on a supported substrate with topographic patterns. The simultaneous engraving process of a different class of fluids is promoted by the front propagation of an air-water interface inside a flow-cell. This highly parallel, microfluidic cell-on-membrane approach opens a door to the natural biocompatibility in mimicking cellular stimuli-response behavior essential for diverse on-chip bioassays that can be precisely controlled in the spatial and temporal manner.

  14. On Asymptotic Analysis of Packet and Wormhole Switched Routing Algorithm for Application-Specific Networks-on-Chip

    Directory of Open Access Journals (Sweden)

    Nitin

    2012-01-01

    Full Text Available The application of the multistage interconnection networks (MINs in systems-on-chip (SoC and networks-on-chip (NoC is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous problems, a new method is proposed that uses MIN to provide intra-(global communication among application-specific NoCs in networks-in-package (NiP. For this, four fault-tolerant parallel algorithms are proposed. It allows different NoCs to communicate in parallel using either fault-tolerant irregular Penta multistage interconnection network (PNN or fault-tolerant regular Hexa multistage interconnection network (HXN. These two are acting as an interconnects-on-chip (IoC in NiP. Both IoC use packet switching and wormhole switching to route packets from source NoC to destination NoC. The results are compared in terms of packet losses and wormhole switching which comes out to be better than packet switching. The comparison of IoC on cost and MTTR concluded that the HXN has the higher cost than the PNN, but MTTR values of the HXN are low in comparison to the PNN. This signifies that the ability to tolerate faults and online repairing of the HXN is higher and faster than the PNN.

  15. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  16. On-chip two-mode division multiplexing using tapered directional coupler-based mode multiplexer and demultiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Xu, Jing; Da Ros, Francesco

    2013-01-01

    Abstract: We demonstrate a novel on-chip two-mode division multiplexing circuit using a tapered directional coupler-based TE0&TE1 mode multiplexer and demultiplexer on the silicon-on-insulator platform. A low insertion loss (0.3 dB), low mode crosstalk (< −16 dB), wide bandwidth (~100 nm), and la......Abstract: We demonstrate a novel on-chip two-mode division multiplexing circuit using a tapered directional coupler-based TE0&TE1 mode multiplexer and demultiplexer on the silicon-on-insulator platform. A low insertion loss (0.3 dB), low mode crosstalk (...), and large fabrication tolerance (20 nm) are measured. An on-chip mode multiplexing experiment is carried out on the fabricated circuit with non return-to-zero (NRZ) on-off keying (OOK) signals at 40 Gbit/s. The experimental results show clear eye diagrams and moderate power penalty for both TE0 and TE1...

  17. Controlling On-chip Optical Radiation with All-Dielectric Antennas: Reconfigurable Interconnects and Lab-on-achip Devices

    Science.gov (United States)

    Lechago, S.; García-Meca, C.; Griol, A.; Martí, J.

    2018-01-01

    Aimed to improve the flexibility of optical network-on-a-chip topologies, unguided optical interconnects using plasmonic nanoantennas or dielectric phased arrays have been proposed. However, the bulky footprints of the latter, and both the low directivity figures and high losses of the former, together with complicated excitation schemes, limit their use for on-chip optical interconnects. Here, we introduce a novel concept of on-chip CMOS-compatible wireless optical system based on the use of smartly-engineered broadband easily-fed antennas, which not only overcomes the aforementioned drawbacks but also opens a wide range of applications in several fields. To illustrate its potential, several unprecedented on-chip wireless applications are outlined and experimentally demonstrated. This includes the verification of broadband highly-directive wireless data transmission at speeds as high as 160 Gbit·s‑1 over mm-scale links, the realization of fully-reconfigurable wireless beam steering device and the validation of an ultra-compact integrated contactless microflow cytometer.

  18. High-bit rate ultra-compact light routing with mode-selective on-chip nanoantennas.

    Science.gov (United States)

    Guo, Rui; Decker, Manuel; Setzpfandt, Frank; Gai, Xin; Choi, Duk-Yong; Kiselev, Roman; Chipouline, Arkadi; Staude, Isabelle; Pertsch, Thomas; Neshev, Dragomir N; Kivshar, Yuri S

    2017-07-01

    Optical nanoantennas provide a promising pathway toward advanced manipulation of light waves, such as directional scattering, polarization conversion, and fluorescence enhancement. Although these functionalities were mainly studied for nanoantennas in free space or on homogeneous substrates, their integration with optical waveguides offers an important "wired" connection to other functional optical components. Taking advantage of the nanoantenna's versatility and unrivaled compactness, their imprinting onto optical waveguides would enable a marked enhancement of design freedom and integration density for optical on-chip devices. Several examples of this concept have been demonstrated recently. However, the important question of whether nanoantennas can fulfill functionalities for high-bit rate signal transmission without degradation, which is the core purpose of many integrated optical applications, has not yet been experimentally investigated. We introduce and investigate directional, polarization-selective, and mode-selective on-chip nanoantennas integrated with a silicon rib waveguide. We demonstrate that these nanoantennas can separate optical signals with different polarizations by coupling the different polarizations of light vertically to different waveguide modes propagating into opposite directions. As the central result of this work, we show the suitability of this concept for the control of optical signals with ASK (amplitude-shift keying) NRZ (nonreturn to zero) modulation [10 Gigabit/s (Gb/s)] without significant bit error rate impairments. Our results demonstrate that waveguide-integrated nanoantennas have the potential to be used as ultra-compact polarization-demultiplexing on-chip devices for high-bit rate telecommunication applications.

  19. On-chip cell lysis by antibacterial non-leaching reusable quaternary ammonium monolithic column.

    Science.gov (United States)

    Aly Saad Aly, Mohamed; Gauthier, Mario; Yeow, John

    2016-02-01

    Reusable antibacterial non-leaching monolithic columns polymerized in microfluidic channels designed for on-chip cell lysis applications were obtained by the photoinitiated free radical copolymerization of diallyldimethylammonium chloride (DADMAC) and ethylene glycol diacrylate (EGDA) in the presence of a porogenic solvent. The microfluidic channels were fabricated in cross-linked poly(methyl methacrylate) (X-PMMA) substrates by laser micromachining. The monolithic columns have the ability to inhibit the growth of, kill and efficiently lyse Gram-positive Micrococcus luteus (Schroeter) (ATCC 4698) and Kocuria rosea (ATCC 186), and Gram-negative bacteria Pseudomonas putida (ATCC 12633) and Escherichia coli (ATCC 35218) by mechanically shearing the bacterial membrane when forcing the cells to pass through the narrow pores of the monolithic column, and simultaneously disintegrating the cell membrane by physical contact with the antibacterial surface of the column. Cell lysis was confirmed by off-chip PCR without the need for further purification. The influence of the cross-linking monomer on bacterial growth inhibition, leaching, lysis efficiency of the monolithic column and its mechanical stability within the microfluidic channel were investigated and analyzed for three different cross-linking monomers: ethylene glycol dimethacrylate (EGDA), ethylene glycol dimethacrylate (EGDMA) and 1,6-hexanediol dimethacrylate (1,6-HDDMA). Furthermore, the bonding efficiency of two X-PMMA substrates with different cross-linking levels was studied. The monolithic columns were shown to be stable, non-leaching, and reusable for over 30 lysis cycles without significant performance degradation or DNA carryover when they were back-flushed between lysis cycles.

  20. All Optical Fast Fourier Transform On Chip with Heating Tunability Design, Simulation, Fabrication, and Performance Analysis

    Science.gov (United States)

    Nejadriahi, Hani

    was incorporated to the on chip performance analysis.

  1. On-chip ultrasonic manipulation of microparticles by using the flexural vibration of a glass substrate.

    Science.gov (United States)

    Yamamoto, Ryota; Koyama, Daisuke; Matsukawa, Mami

    2017-08-01

    As biotechnology develops, techniques for manipulating and separating small particles such as cells and DNA are required in the life sciences. This paper investigates on-chip manipulation of microparticles in small channels by using ultrasonic vibration. The chip consists of a rectangular glass substrate with a cross-shaped channel (cross-section: 2.0×2.0mm 2 ) and four lead zirconate titanate transducers attached to the substrate's four corners. To efficiently generate the flexural vibration mode on the chip, we used finite element analysis to optimize the configurations of the glass substrate and transducers. Silicon carbide microparticles with an average diameter of 50μm were immersed in the channels, which were filled with ethanol. By applying an in-phase input voltage of 75V at 225kHz to the four transducers, a flexural vibration mode with a wavelength of 13mm was excited on the glass substrate, and this flexural vibration generated an acoustic standing wave in the channel. The particles could be trapped at the nodal lines of the standing wave. By controlling the driving phase difference between the two pairs of transducers, the vibrational distribution of the substrate could be moved along the channels so that the acoustic standing wave moved in the same direction. The trapped particles could be manipulated by the two-phase drive, and the transport direction could be switched at the junction of the channels orthogonally by changing the combination of the driving condition to four transducers. Copyright © 2016 Elsevier B.V. All rights reserved.

  2. Selection of aptamers specific for glycated hemoglobin and total hemoglobin using on-chip SELEX.

    Science.gov (United States)

    Lin, Hsin-I; Wu, Ching-Chu; Yang, Ching-Hsuan; Chang, Ko-Wei; Lee, Gwo-Bin; Shiesh, Shu-Chu

    2015-01-21

    Blood glycated hemoglobin (HbA1c) levels reflecting average glucose concentrations over the past three months are fundamental for the diagnosis, monitoring, and risk assessment of diabetes. It has been hypothesized that aptamers, which are single-stranded DNAs or RNAs that demonstrate high affinity to a large variety of molecules ranging from small drugs, metabolites, or proteins, could be used for the measurement of HbA1c. Aptamers are selected through an in vitro process called systematic evolution of ligands by exponential enrichment (SELEX), and they can be chemically synthesized with high reproducibility at relatively low costs. This study therefore aimed to select HbA1c- and hemoglobin (Hb)-specific single-stranded DNA aptamers using an on-chip SELEX protocol. A microfluidic SELEX chip was developed to continuously and automatically carry out multiple rounds of SELEX to screen specific aptamers for HbA1c and Hb. HbA1c and Hb were first coated onto magnetic beads. Following several rounds of selection and enrichment with a randomized 40-mer DNA library, specific oligonucleotides were selected. The binding specificity and affinity were assessed by competitive and binding assays. Using the developed microfluidic system, the incubation and partitioning times were greatly decreased, and the entire process was shortened dramatically. Both HbA1c- and Hb-specific aptamers selected by the microfluidic system showed high specificity and affinity (dissociation constant, Kd = 7.6 ± 3.0 nM and 7.3 ± 2.2 nM for HbA1c and Hb, respectively). With further refinements in the assay, these aptamers may replace the conventional antibodies for in vitro diagnostics applications in the near future.

  3. On-Chip Microfluidic Components for In Situ Analysis, Separation, and Detection of Amino Acids

    Science.gov (United States)

    Zheng, Yun; Getty, Stephanie; Dworkin, Jason; Balvin, Manuel; Kotecki, Carl

    2013-01-01

    The Astrobiology Analytical Laboratory at GSFC has identified amino acids in meteorites and returned cometary samples by using liquid chromatography-electrospray ionization time-of-flight mass spectrometry (LCMS). These organic species are key markers for life, having the property of chirality that can be used to distinguish biological from non-biological amino acids. One of the critical components in the benchtop instrument is liquid chromatography (LC) analytical column. The commercial LC analytical column is an over- 250-mm-long and 4.6-mm-diameter stainless steel tube filled with functionized microbeads as stationary phase to separate the molecular species based on their chemistry. Miniaturization of this technique for spaceflight is compelling for future payloads for landed missions targeting astrobiology objectives. A commercial liquid chromatography analytical column consists of an inert cylindrical tube filled with a stationary phase, i.e., microbeads, that has been functionalized with a targeted chemistry. When analyte is sent through the column by a pressurized carrier fluid (typically a methanol/ water mixture), compounds are separated in time due to differences in chemical interactions with the stationary phase. Different species of analyte molecules will interact more strongly with the column chemistry, and will therefore take longer to traverse the column. In this way, the column will separate molecular species based on their chemistry. A lab-on-chip liquid analysis tool was developed. The microfluidic analytical column is capable of chromatographically separating biologically relevant classes of molecules based on their chemistry. For this analytical column, fabrication, low leak rate, and stationary phase incorporation of a serpentine microchannel were demonstrated that mimic the dimensions of a commercial LC column within a 5 10 1 mm chip. The microchannel in the chip has a 75- micrometer-diameter oval-shaped cross section. The serpentine

  4. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  5. Polysilicon nanogap lab-on-chip facilitates multiplex analyses with single analyte.

    Science.gov (United States)

    Balakrishnan, Sharma Rao; Hashim, U; Gopinath, Subash C B; Poopalan, P; Ramayya, H R; Veeradasan, P; Haarindraprasad, R; Ruslinda, A R

    2016-10-15

    Rationally designed biosensing system supports multiplex analyses is warranted for medical diagnosis to determine the level of analyte interaction. The chemically functionalized novel multi-electrode polysilicon nanogap (PSNG) lab-on-chip is designed in this study, facilitates multiplex analyses for a single analyte. On the fabricated 69nm PSNG, biocompatibility and structural characteristics were verified for the efficient binding of Human Chorionic Gonadotropin (hCG). With the assistance of microfluidics, hCG sample was delivered via single-injection to 3-Aminopropyl(triethoxy)silane (APTES) and Glycidoxypropyl(trimethoxy)silane (GPMS) modified PSNG electrodes and the transduced signal was used to investigate the dielectric mechanisms for multiplex analyses. The results from amperometric response and impedance measurement delivered the scale of interaction between anti-hCG antibody and hCG that exhibited 6.5 times higher sensitivity for the chemical linker, APTES than GPMS. Under optimized experimental conditions, APTES and GPMS modified immunosensor has a limit of detection as 0.56mIU/ml and 2.93mIU/ml (at S/N=3), with dissociation constants (Kd) of 5.65±2.5mIU/ml and 7.28±2.6mIU/ml, respectively. These results suggest that multiplex analysis of single target could enhance the accuracy of detection and reliable for real-time comparative analyses. The designed PSNG is simple, feasible, requires low sample consumption and could be applied for any given multiplex analyses. Copyright © 2015 Elsevier B.V. All rights reserved.

  6. Images

    Data.gov (United States)

    National Aeronautics and Space Administration — Images for the website main pages and all configurations. The upload and access points for the other images are: Website Template RSW images BSCW Images HIRENASD...

  7. Extended QoS modelling based on multi-application environment in network on chip

    Science.gov (United States)

    Saadaoui, Abdelkader; Nasri, Salem

    2015-01-01

    Until now, there is no standard method of the quality of service (QoS) measurement and fewer techniques have been used to provide its definition. Therefore, researchers are looking for a projection of QoS on quantifiable space, since it is qualitative, subjective and not measurable. However, a few tentatives have studied QoS parameter estimation. Many applications in network on chip (NoC) present variable QoS parameters such as packet loss rate (PLR), end-to-end delay (EED) and throughput (Thp). However, there are a few papers that have developed different methods to modelise QoS in NoC. Their QoS presentation does not provide a multi-application parameter arbiter. Independently of the approach used, an important challenge associated with QoS provision is the development of an efficient and flexible way to monitor QoS. The originality of our approach is based on a proposition of a QoS-intellectual property module in NoC architecture to improve network performances. We implement an extended approach of QoS metrics modelling for NoC on multi-parameter and multi-application environment. The QoS metrics model is based on QoS parameters such as PLR, EED and Thp for different applications. To validate this work, a dynamic routing simulation for 4 × 4 mesh NoC behaviour under three different applications, namely transmission control protocol, variable bit rate and constant bit rate, is considered. To achieve an ideal network behaviour, load balancing on NoC with multiple concurrent applications is improved using QoS metrics measurement based on dynamic routing. The results have shown that extended QoS modelling approach is easy and cheap to implement in hardware-software quantifiable representation. Thus, implementing a quantifiable representation of QoS can be used to provide a NoC services arbiter. QoS arbiter interacts with other routers to ensure flit flow and QoS modelling to provide a QoS value.

  8. A low power on-chip class-E power amplifier for remotely powered implantable sensor systems

    Science.gov (United States)

    Ture, Kerim; Kilinc, Enver G.; Dehollain, Catherine

    2015-06-01

    This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the required high inductance values which make the on-chip integration of the power amplifier difficult. The designed power amplifier is fully integrated in the remotely powered sensor system and fabricated in 0.18 μm CMOS process. The power is transferred to the implantable sensor system at 13.56 MHz by using an inductively coupled remote powering link. The induced AC voltage on the implant coil is converted into a DC voltage by a passive full-wave rectifier. A voltage regulator is used to suppress the ripples and create a clean and stable 1.8 V supply voltage for the sensor and communication blocks. The data collected from the sensors is transmitted by on-off keying modulated low-power transmitter at 1.2 GHz frequency. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. An additional output network is used for the power amplifier which makes the integration of the power amplifier fully on-chip. The integrated power amplifier with 0.2 V supply voltage has a drain efficiency of 31.5% at -10 dBm output power for 50 Ω load. The measurement results verify the functionality of the power amplifier and the remotely powered implantable sensor system. The data communication is also verified by using a commercial 50 Ω chip antenna and has 600 kbps data rate at 1 m communication distance.

  9. Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

    2006-11-15

    The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

  10. Uniform droplet splitting and detection using Lab-on-Chip flow cytometry on a microfluidic PDMS device

    DEFF Research Database (Denmark)

    Kunstmann-Olsen, Casper; Hanczyc, Martin; Hoyland, James

    2016-01-01

    A PDMS chip is fabricated using soft lithography and applied to investigate the formation and division of nitrobenzene (NB) droplets in a two-phase system stabilized by oleic acid. Using an integrated on-chip flow cytometer setup, effected with optical fibers, droplet size distributions...... are analyzed in situ based on optical signal intensities. By controlling the hydrodynamic flow focusing, uniform droplets of sizes between 100 μm and 300 μm are created with precise size control. Cross-flow shearing allows one to divide these droplets into anything from 2 to 9 individual droplets, depending...... on flow parameters....

  11. Embedded software design and programming of multiprocessor system-on-chip simulink and system C case studies

    CERN Document Server

    Popovici, Katalin; Jerraya, Ahmed A; Wolf, Marilyn

    2010-01-01

    Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access).Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tediou

  12. An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar; Olsen, Rasmus Grøndahl

    2005-01-01

    The demand for IP reuse and system level scalability in System-on-Chip (SoC) designs is growing. Network-onchip (NoC) constitutes a viable solution space to emerging SoC design challenges. In this paper we describe an OCP compliant network adapter (NA) architecture for the MANGO NoC. The NA...... decouples communication and computation, providing memory-mapped OCP transactions based on primitive message-passing services of the network. Also, it facilitates GALS-type systems, by adapting to the clockless network. This helps leverage a modular SoC design flow. We evaluate performance and cost of 0...

  13. Reference-Frame-Independent Quantum-Key-Distribution Server with a Telecom Tether for an On-Chip Client

    Science.gov (United States)

    Zhang, P.; Aungskunsiri, K.; Martín-López, E.; Wabnig, J.; Lobino, M.; Nock, R. W.; Munns, J.; Bonneau, D.; Jiang, P.; Li, H. W.; Laing, A.; Rarity, J. G.; Niskanen, A. O.; Thompson, M. G.; O'Brien, J. L.

    2014-04-01

    We demonstrate a client-server quantum key distribution (QKD) scheme. Large resources such as laser and detectors are situated at the server side, which is accessible via telecom fiber to a client requiring only an on-chip polarization rotator, which may be integrated into a handheld device. The detrimental effects of unstable fiber birefringence are overcome by employing the reference-frame-independent QKD protocol for polarization qubits in polarization maintaining fiber, where standard QKD protocols fail, as we show for comparison. This opens the way for quantum enhanced secure communications between companies and members of the general public equipped with handheld mobile devices, via telecom-fiber tethering.

  14. Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

    Science.gov (United States)

    Hsieh, I.-Wei

    In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic

  15. A Low-Power and Low-Voltage Power Management Strategy for On-Chip Micro Solar Cells

    Directory of Open Access Journals (Sweden)

    Ismail Cevik

    2015-01-01

    Full Text Available Fundamental characteristics of on-chip micro solar cell (MSC structures were investigated in this study. Several MSC structures using different layers in three different CMOS processes were designed and fabricated. Effects of PN junction structure and process technology on solar cell performance were measured. Parameters for low-power and low-voltage implementation of power management strategy and boost converter based circuits utilizing fractional voltage maximum power point tracking (FVMPPT algorithm were determined. The FVMPPT algorithm works based on the fraction between the maximum power point operation voltage and the open circuit voltage of the solar cell structure. This ratio is typically between 0.72 and 0.78 for commercially available poly crystalline silicon solar cells that produce several watts of power under typical daylight illumination. Measurements showed that the fractional voltage ratio is much higher and fairly constant between 0.82 and 0.85 for on-chip mono crystalline silicon micro solar cell structures that produce micro watts of power. Mono crystalline silicon solar cell structures were observed to result in better power fill factor (PFF that is higher than 74% indicating a higher energy harvesting efficiency.

  16. Scalable fabrication of high-power graphene micro-supercapacitors for flexible and on-chip energy storage.

    Science.gov (United States)

    El-Kady, Maher F; Kaner, Richard B

    2013-01-01

    The rapid development of miniaturized electronic devices has increased the demand for compact on-chip energy storage. Microscale supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. However, conventional micro-fabrication techniques have proven to be cumbersome in building cost-effective micro-devices, thus limiting their widespread application. Here we demonstrate a scalable fabrication of graphene micro-supercapacitors over large areas by direct laser writing on graphite oxide films using a standard LightScribe DVD burner. More than 100 micro-supercapacitors can be produced on a single disc in 30 min or less. The devices are built on flexible substrates for flexible electronics and on-chip uses that can be integrated with MEMS or CMOS in a single chip. Remarkably, miniaturizing the devices to the microscale results in enhanced charge-storage capacity and rate capability. These micro-supercapacitors demonstrate a power density of ~200 W cm-3, which is among the highest values achieved for any supercapacitor.

  17. Smart Integrated Sensor for Multiple Detections of Glucose and L-Lactate Using On-Chip Electrochemical System

    Directory of Open Access Journals (Sweden)

    Tomoyuki Yamazaki

    2011-01-01

    Full Text Available Multiple sensor electrodes, a supplementary electrode, a reference electrode, and signal-processing circuits were integrated on a single chip to develop a chip-shaped electrochemical sensing system. L-lactate and glucose were measured using on-chip working electrodes modified by polyion complex to immobilize lactate oxidase and glucose oxidase, respectively. Cyclic voltammetry measurements were conducted using an on-chip potentiostat. Selective and quantitative detection of glucose and L-lactate and the interference behavior were studied. Hydrogen peroxide generated by enzymatic reactions was detected by an increase in anodic oxidation current. Reaction currents at +0.7 V versus Ag/AgCl were used to obtain calibration plots. The measured dynamic ranges for L-lactate and glucose were 0.2–1.0 mM and 2.0–8.0 mM, respectively. The sensitivities were 65 nA/mM and 15 nA/mM, respectively, using a working electrode of 0.5 mm2. The 3σ detection limit was 0.19 mM and 1.1 mM, respectively. We have achieved multiple biomaterial detections on a circuit-equipped single chip. This integrated electrochemical sensor chip could be the best candidate for realizing point-of-care testing due to its portability and potential for mass production.

  18. Development of a lab-on-chip electrochemical biosensor for water quality analysis based on microalgal photosynthesis.

    Science.gov (United States)

    Tsopela, A; Laborde, A; Salvagnac, L; Ventalon, V; Bedel-Pereira, E; Séguy, I; Temple-Boyer, P; Juneau, P; Izquierdo, R; Launay, J

    2016-05-15

    The present work was dedicated to the development of a lab-on-chip device for water toxicity analysis and more particularly herbicide detection in water. It consists in a portable system for on-site detection composed of three-electrode electrochemical microcells, integrated on a fluidic platform constructed on a glass substrate. The final goal is to yield a system that gives the possibility of conducting double, complementary detection: electrochemical and optical and therefore all materials used for the fabrication of the lab-on-chip platform were selected in order to obtain a device compatible with optical technology. The basic detection principle consisted in electrochemically monitoring disturbances in metabolic photosynthetic activities of algae induced by the presence of Diuron herbicide. Algal response, evaluated through oxygen (O2) monitoring through photosynthesis was different for each herbicide concentration in the examined sample. A concentration-dependent inhibition effect of the herbicide on photosynthesis was demonstrated. Herbicide detection was achieved through a range (blank - 1 µM Diuron herbicide solution) covering the limit of maximum acceptable concentration imposed by Canadian government (0.64 µM), using a halogen white light source for the stimulation of algal photosynthetic apparatus. Superior sensitivity results (limit of detection of around 0.1 µM) were obtained with an organic light emitting diode (OLED), having an emission spectrum adapted to algal absorption spectrum and assembled on the final system. Copyright © 2015 Elsevier B.V. All rights reserved.

  19. Integration of on-chip FET switches with dopantless Si/SiGe quantum dot structures for high throughput testing

    Science.gov (United States)

    Ward, Daniel; Savage, Donald; Lagally, Max; Coppersmith, Susan; Eriksson, Mark

    2013-03-01

    In the last few years, significant research on dopantless Si/SiGe planar quantum dot structures has occurred. One of the limiting factors is that typically only a single double-dot structure can be cooled down in a dilution refrigerator at time due to the limited number of electrical connections available. We report on our recent work to create samples with four sets of double-dots on a single chip that can all be tested in a single cool down through the introduction of on-chip FET switches. In our samples the four double-dot structures have their depletion gates and ohmic contacts connected in parallel, minimizing the number of connections. We energize accumulation gates for the device under test such that the other dot structures do not contribute to the measurements. Our double-dot structures require five accumulation gates, which limits scaling due to limited fridge wiring capacity. To alleviate this problem and to test integration approaches for cryogenic quantum dot devices we fabricated a series of on-chip FET switches to form a multiplexer for the accumulation gates. Using the multiplexer we can wire up four double-dot structures using just 23 connections instead of the 34 required without it. As more devices are added the scaling benefits increase exponentially.

  20. A versatile lab-on-chip test platform to characterize elementary deformation mechanisms and electromechanical couplings in nanoscopic objects

    Science.gov (United States)

    Pardoen, Thomas; Colla, Marie-Sthéphane; Idrissi, Hosni; Amin-Ahmadi, Behnam; Wang, Binjie; Schryvers, Dominique; Bhaskar, Umesh K.; Raskin, Jean-Pierre

    2016-03-01

    A nanomechanical on-chip test platform has recently been developed to deform under a variety of loading conditions freestanding thin films, ribbons and nanowires involving submicron dimensions. The lab-on-chip involves thousands of elementary test structures from which the elastic modulus, strength, strain hardening, fracture, creep properties can be extracted. The technique is amenable to in situ transmission electron microscopy (TEM) investigations to unravel the fundamental underlying deformation and fracture mechanisms that often lead to size-dependent effects in small-scale samples. The method allows addressing electrical and magnetic couplings as well in order to evaluate the impact of large mechanical stress levels on different solid-state physics phenomena. We had the chance to present this technique in details to Jacques Friedel in 2012 who, unsurprisingly, made a series of critical and very relevant suggestions. In the spirit of his legacy, the paper will address both mechanics of materials related phenomena and couplings with solids state physics issues.

  1. Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

    Directory of Open Access Journals (Sweden)

    Angelo Kuti Lusala

    2012-01-01

    Full Text Available A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the proposed router architectures. 7 × 7 mesh NoCs were simulated in SystemC. Simulation results show that the probability of establishing paths through the NoC increases with the number of sub-channels and has its highest value when combining SDM with TDM, thereby significantly reducing contention in the NoC.

  2. Package-friendly piezoresistive pressure sensors with on-chip integrated packaging-stress-suppressed suspension (PS3) technology

    International Nuclear Information System (INIS)

    Wang, Jiachou; Li, Xinxin

    2013-01-01

    An on-chip integrated packaging-stress-suppressed suspension (PS 3 ) technology for a packaging-stress-free pressure sensor is proposed and developed. With a MIS (microholes interetch and sealing) micromachining process implemented only from the front-side of a single-side polished (1 1 1) silicon wafer, a compact cantilever-shaped PS 3 is on-chip integrated surrounding a piezoresistive pressure-sensing structure to provide a packaging-process/substrate-friendly method for low-cost but high-performance sensor applications. With the MIS process, the chip size of the PS 3 -enclosed pressure sensor is as small as 0.8 mm × 0.8 mm. Compared with a normal pressure sensor without PS 3 (but with an identical pressure-sensing structure), the proposed pressure sensor has the same sensitivity of 0.046 mV kPa −1 (3.3 V) −1 . However, without using the thermal compensation technique, a temperature coefficient of offset of only 0.016% °C −1 FS is noted for the sensor with PS 3 , which is about 15 times better than that for the sensor without PS 3 . Featuring effective isolation and elimination of the influence from packaging stress, the PS 3 technique is promising to be widely used for packaging-friendly mechanical sensors. (paper)

  3. On-chip fabrication of alkali-metal vapor cells utilizing an alkali-metal source tablet

    International Nuclear Information System (INIS)

    Tsujimoto, K; Hirai, Y; Sugano, K; Tsuchiya, T; Tabata, O; Ban, K; Mizutani, N

    2013-01-01

    We describe a novel on-chip microfabrication technique for the alkali-metal vapor cell of an optically pumped atomic magnetometer (OPAM), utilizing an alkali-metal source tablet (AMST). The newly proposed AMST is a millimeter-sized piece of porous alumina whose considerable surface area holds deposited alkali-metal chloride (KCl) and barium azide (BaN 6 ), source materials that effectively produce alkali-metal vapor at less than 400 °C. Our experiments indicated that the most effective pore size of the AMST is between 60 and 170 µm. The thickness of an insulating glass spacer holding the AMST was designed to confine generated alkali metal to the interior of the vapor cell during its production, and an integrated silicon heater was designed to seal the device using a glass frit, melted at an optimum temperature range of 460–490 °C that was determined by finite element method thermal simulation. The proposed design and AMST were used to successfully fabricate a K cell that was then operated as an OPAM with a measured sensitivity of 50 pT. These results demonstrate that the proposed concept for on-chip microfabrication of alkali-metal vapor cells may lead to effective replacement of conventional glassworking approaches. (paper)

  4. A lab-on-chip cell-based biosensor for label-free sensing of water toxicants.

    Science.gov (United States)

    Liu, F; Nordin, A N; Li, F; Voiculescu, I

    2014-04-07

    This paper presents a lab-on-chip biosensor containing an enclosed fluidic cell culturing well seeded with live cells for rapid screening of toxicants in drinking water. The sensor is based on the innovative placement of the working electrode for the electrical cell-substrate impedance sensing (ECIS) technique as the top electrode of a quartz crystal microbalance (QCM) resonator. Cell damage induced by toxic water will cause a decrease in impedance, as well as an increase in the resonant frequency. For water toxicity tests, the biosensor's unique capabilities of performing two complementary measurements simultaneously (impedance and mass-sensing) will increase the accuracy of detection while decreasing the false-positive rate. Bovine aortic endothelial cells (BAECs) were used as toxicity sensing cells. The effects of the toxicants, ammonia, nicotine and aldicarb, on cells were monitored with both the QCM and the ECIS technique. The lab-on-chip was demonstrated to be sensitive to low concentrations of toxicants. The responses of BAECs to toxic samples occurred during the initial 5 to 20 minutes depending on the type of chemical and concentrations. Testing the multiparameter biosensor with aldicarb also demonstrated the hypothesis that using two different sensors to monitor the same cell monolayer provides cross validation and increases the accuracy of detection. For low concentrations of aldicarb, the variations in impedance measurements are insignificant in comparison with the shifts of resonant frequency monitored using the QCM resonator. A highly linear correlation between signal shifts and chemical concentrations was demonstrated for each toxicant.

  5. On-chip food safety monitoring: multi-analyte screening with imaging surface plasmon resonance-based biosensor

    NARCIS (Netherlands)

    Rebe, S.

    2010-01-01

    Food safety is an increasing health concern, recognised and promoted by many
    institutions across the globe. Food products can be contaminated with pathogenic
    microorganisms, environmental pollutants, veterinary drug residues, allergens and toxins.
    Public health concerns which have

  6. Slow Light Based On-Chip High Resolution Fourier Transform Spectrometer For Geostationary Imaging of Atmospheric Greenhouse Gases, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Fourier transform spectroscopy (FTS) in infrared wavelength range is an effective measure for global greenhouse gas monitoring. However, conventional FTS instruments...

  7. Real time on-chip sequential adaptive principal component analysis for data feature extraction and image compression

    Science.gov (United States)

    Duong, T. A.

    2004-01-01

    In this paper, we present a new, simple, and optimized hardware architecture sequential learning technique for adaptive Principle Component Analysis (PCA) which will help optimize the hardware implementation in VLSI and to overcome the difficulties of the traditional gradient descent in learning convergence and hardware implementation.

  8. Energy transfer phenomena and radiative processes in silicon nitride based materials for on-chip photonics applications

    Science.gov (United States)

    Li, Rui

    Rare-earth (RE) doping of silicon-based structures provides a valuable approach for light-emitting devices which could be monolithically integrated atop the widespread silicon electronics platform and enables inexpensive integration of on-chip optical components. However, the small excitable fraction of RE ions and the substantial free carrier losses in Si nanostructures severely limit the possibility to achieve net optical gain using traditional Er doped materials, such as Er doped Si-rich oxides (Er:SRO). On the other hand, a novel material platform based on RE-doped silicon nitride (RE:Six) materials has recently revealed unique advantages for on-chip light source. Based on a variety of light emission spectroscopic techniques and rate equation modeling, light emission and energy transfer phenomena were studied to quantitatively assess the benefits of the novel Er and Nd doped SiNx (Er: SiN x and Nd:SiNx) material platform compared to the standard Er:SRO. Efficient energy transfer and nanosecond-time dynamics from SiN x matrices to RE ions with two orders of magnitude larger coupling coefficient than Er:SRO were demonstrated for the first time. The origin of this energy transfer was shown to consist of non-resonant phonon-mediated coupling by temperature-dependent experiments. In addition, a tradeoff between excitation efficiency by energy transfer and emission efficiency, determined by excess Si concentration, was discovered and studied. Although carrier absorption and non-radiative recombination jeopardize the observation of optical gain, differential loss measurements under femtosecond pulsed excitation resulted in the bleaching of the Er ground state absorption by energy transfer in Er:SiN x materials, which bears great hope for the engineering of Si-based lasers. On the other hand, with a superior 4-level system, Nd:SiNx is promising to lase with a lower threshold. To make use of the better field confinement in SiNx due to its higher refractive index, RE

  9. Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC Interconectado por una Networks-on-Chip (NoC

    Directory of Open Access Journals (Sweden)

    Wilson Mauricio Chicaiza

    2013-11-01

    Full Text Available En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC. Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

  10. Non-Magnetic On-Chip Resonant Acousto-Optic Isolator at 780 nm

    Science.gov (United States)

    2017-08-04

    interactions to break the propagation symmetry of light using a unidirectional acoustic pump. This acoustic wave was transduced using an RF-driven SAW...4: Microscope images of the completed non-reciprocal optical modulator. ........................... 5 Fig 5: (Left) Phase matching situation in the...efficiency (percentage of light scattered, or insertion loss) reached its highest value of 17% at 17.8 dBm RF drive power

  11. Rolled-Up Optical and Electronic Components for On-Chip Integrative Applications

    Science.gov (United States)

    2013-10-10

    attracted broad interest to create new three- dimensional electronics such as wrapable solar cells , pressure sensors and paper displays. The adaption to...microscopy (SEM) image of the tube array is presented in Fig. 4(b). By ALD coating, a controllable red shift of Transverse Magnetic (TM) polarized...fabricated in this way to detect and analyze individual cells , biomolecules, and their bioactivities. 3.2 Three-dimensional confinement in asymmetric

  12. Capacitance Variation Induced by Microfluidic Two-Phase Flow across Insulated Interdigital Electrodes in Lab-On-Chip Devices

    Directory of Open Access Journals (Sweden)

    Tao Dong

    2015-01-01

    Full Text Available Microfluidic two-phase flow detection has attracted plenty of interest in various areas of biology, medicine and chemistry. This work presents a capacitive sensor using insulated interdigital electrodes (IDEs to detect the presence of droplets in a microchannel. This droplet sensor is composed of a glass substrate, patterned gold electrodes and an insulation layer. A polydimethylsiloxane (PDMS cover bonded to the multilayered structure forms a microchannel. Capacitance variation induced by the droplet passage was thoroughly investigated with both simulation and experimental work. Olive oil and deionized water were employed as the working fluids in the experiments to demonstrate the droplet sensor. The results show a good sensitivity of the droplet with the appropriate measurement connection. This capacitive droplet sensor is promising to be integrated into a lab-on-chip device for in situ monitoring/counting of droplets or bubbles.

  13. Test scheduling optimization for 3D network-on-chip based on cloud evolutionary algorithm of Pareto multi-objective

    Science.gov (United States)

    Xu, Chuanpei; Niu, Junhao; Ling, Jing; Wang, Suyan

    2018-03-01

    In this paper, we present a parallel test strategy for bandwidth division multiplexing under the test access mechanism bandwidth constraint. The Pareto solution set is combined with a cloud evolutionary algorithm to optimize the test time and power consumption of a three-dimensional network-on-chip (3D NoC). In the proposed method, all individuals in the population are sorted in non-dominated order and allocated to the corresponding level. Individuals with extreme and similar characteristics are then removed. To increase the diversity of the population and prevent the algorithm from becoming stuck around local optima, a competition strategy is designed for the individuals. Finally, we adopt an elite reservation strategy and update the individuals according to the cloud model. Experimental results show that the proposed algorithm converges to the optimal Pareto solution set rapidly and accurately. This not only obtains the shortest test time, but also optimizes the power consumption of the 3D NoC.

  14. Study on a Real-Time BEAM System for Diagnosis Assistance Based on a System on Chips Design

    Directory of Open Access Journals (Sweden)

    Kung-Wei Chang

    2013-05-01

    Full Text Available As an innovative as well as an interdisciplinary research project, this study performed an analysis of brain signals so as to establish BrainIC as an auxiliary tool for physician diagnosis. Cognition behavior sciences, embedded technology, system on chips (SOC design and physiological signal processing are integrated in this work. Moreover, a chip is built for real-time electroencephalography (EEG processing purposes and a Brain Electrical Activity Mapping (BEAM system, and a knowledge database is constructed to diagnose psychosis and body challenges in learning various behaviors and signals antithesis by a fuzzy inference engine. This work is completed with a medical support system developed for the mentally disabled or the elderly abled.

  15. A 10-b 50-MS/s 820- μW SAR ADC With On-Chip Digital Calibration.

    Science.gov (United States)

    Yoshioka, Masato; Ishikawa, Kiyoshi; Takayama, Takeshi; Tsukamoto, Sanroku

    2010-12-01

    This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm(2) .

  16. On-chip reconfigurable optical add-drop multiplexer for hybrid wavelength/mode-division-multiplexing systems.

    Science.gov (United States)

    Wang, Shipeng; Feng, Xianglian; Gao, Shiming; Shi, Yaocheng; Dai, Tingge; Yu, Hui; Tsang, Hon-Ki; Dai, Daoxin

    2017-07-15

    A silicon-based on-chip reconfigurable optical add-drop multiplexer (ROADM) is presented for hybrid wavelength-division-multiplexing-mode-division-multiplexing systems. The present ROADM consists of a four-channel mode demultiplexer, four wavelength-selective thermo-optic switches based on microring resonators, and a four-channel mode multiplexer. With the present ROADM, one can add/drop one of wavelength channels of any mode to/from the multimode bus waveguide successfully with an excess loss of 2-5 dB and an extinction ratio of ∼20  dB over a wavelength range of 1525-1555 nm.

  17. AlphaRad, a new integrated CMOS System-on-Chip for high efficiency alpha particles counting

    Energy Technology Data Exchange (ETDEWEB)

    Husson, D. [Universite Louis Pasteur and IPHC (UMR7178), 23 Rue du Loess, BP 28, F-67037, Strasbourg, Cedex 2 (France)]. E-mail: husson@lepsi.in2p3.fr; Bozier, A. [InESS (UMR7163), F-67037 Strasbourg, Cedex 2 (France); Higueret, S. [IPHC - UMR7178, 23 Rue du Loess, BP 28, F-67037 Strasbourg, Cedex 2 (France); Le, T.D. [IPHC - UMR7178, 23 Rue du Loess, BP 28, F-67037 Strasbourg, Cedex 2 (France); Nourreddine, A. [Universite Louis Pasteur and IPHC (UMR7178), 23 Rue du Loess, BP 28, F-67037, Strasbourg, Cedex 2 (France)

    2006-12-21

    An integrated System-on-Chip (SoC) has been designed in 0.6{mu}m CMOS mixed analog/digital technology, and tested for high rate alpha particle counting. The sensor is the most innovative part of the chip, with a total active area of 2x2.5mmx5mm. The two-stage charge-to-voltage amplification scheme includes a numerical block for offset compensation. Designed with a gain of 700, the chip has been tested in alpha sources: a very high signal over noise ratio was obtained, leading to a detection efficiency of 5MeV alpha particles close to 100%. The chip is working at room temperature and has been tested up to 300kHz reset frequency. Future applications of this SoC will focus on detection of fast and thermal neutrons free of gamma contamination.

  18. Simultaneous measurement of sensor-protein dynamics and motility of a single cell by on-chip microcultivation system

    Directory of Open Access Journals (Sweden)

    Kawagishi Ikuro

    2004-04-01

    Full Text Available Abstract Measurement of the correlation between sensor-protein expression, motility and environmental change is important for understanding the adaptation process of cells during their change of generation. We have developed a novel assay exploiting the on-chip cultivation system, which enabled us to observe the change of the localization of expressed sensor-protein and the motility for generations. Localization of the aspartate sensitive sensor protein at two poles in Escherichia coli decreased quickly after the aspartate was added into the cultivation medium. However, it took more than three generations for recovering the localization after the removal of aspartate from the medium. Moreover, the tumbling frequency was strongly related to the localization of the sensor protein in a cell. The results indicate that the change of the spatial localization of sensor protein, which was inherited for more than three generations, may contribute to cells, motility as the inheritable information.

  19. Development and applications of a multi-purpose digital controller with a System-on-Chip FPGA for accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Kurimoto, Yoshinori, E-mail: kurimoto@post.j-parc.jp [High Energy Accelerator Research Organization (KEK), Ibaraki 319-1195 (Japan); Nakamura, Keigo [Department of Physics, Kyoto University, Kyoto 606-8502 (Japan)

    2016-12-21

    J-PARC Main Ring (MR) is a high intensity proton synchrotron which accelerates protons from 3 GeV to 30 GeV. It has operated at a beam intensity of 390 kW and an upgrade toward the megawatt rating is scheduled. For higher beam intensity, some of the accelerator components require more intelligent and complicated functions. To consolidate such functions among various components, we developed multi-purpose digital boards using a System-on-Chip Field-Programmable Gated Array (SoC FPGA). In this paper, we describe the details of our developed boards as well as their possible applications. As an application of the boards, we have successfully performed the measurement of the betatron amplitude function during beam acceleration in J-PARC MR. The experimental setup and results of the measurement are also described in detail.

  20. Dual-Polarized On-Chip Antenna for 300 GHz Full-Duplex Communication System

    Directory of Open Access Journals (Sweden)

    Linyan Guo

    2017-01-01

    Full Text Available This paper presents a novel design of compact orthogonally polarized on-chip antenna to realize 300 GHz full-duplex communication system with high isolation. It consists of a dipole antenna for horizontal polarization and a disk-loaded monopole antenna for vertical polarization. They are in good cross-polarization state with more than 90 dB of self-interference suppression and then can be used to achieve good isolation between transmitting and receiving antennas. In addition, two dual-polarized antennas have been adopted in two separated transceivers to study their isolation performance. Furthermore, this compact antenna only occupies an active area of 390 μm × 300 μm × 78 μm and can be used for multiple-input multiple-output application as well.

  1. Pulse Generator for Ultrasonic Piezoelectric Transducer Arrays Based on a Programmable System-on-Chip (PSoC

    Directory of Open Access Journals (Sweden)

    Pedro Acevedo

    2017-04-01

    Full Text Available This paper describes the design of a pulse generator to excite PZT and PVDF ultrasonic transducer arrays, based on the Programmable System-on-Chip (PSoC module. In this module, using programmable logic different pulses were implemented; these pulses are required in ultrasonic applications for multiple channels to excite PZT and PVDF transducer arrays. To excite multiple elements, bursts are required which can be generated simultaneously or out of phase, generating dynamic wave fronts. For medical applications where bidirectional blood flow is detected burst and quadrature pulses are used. These pulses can be generated independently or in combinations, as simultaneous pulses, shift pulses or burst. This module can operate with programmable frequencies from 3-74 MHz; its programming may be versatile covering a wide range of ultrasonic applications.

  2. Supporting Symmetric 128-bit AES in Networked Embedded Systems: An Elliptic Curve Key Establishment Protocol-on-Chip

    Directory of Open Access Journals (Sweden)

    Roshan Duraisamy

    2007-02-01

    Full Text Available The secure establishment of cryptographic keys for symmetric encryption via key agreement protocols enables nodes in a network of embedded systems and remote agents to communicate securely in an insecure environment. In this paper, we propose a pure hardware implementation of a key agreement protocol, which uses the elliptic curve Diffie-Hellmann and digital signature algorithms and enables two parties, a remote agent and a networked embedded system, to establish a 128-bit symmetric key for encryption of all transmitted data via the advanced encryption scheme (AES. The resulting implementation is a protocol-on-chip that supports full 128-bit equivalent security (PoC-128. The PoC-128 has been implemented in an FPGA, but it can also be used as an IP within different embedded applications. As 128-bit security is conjectured valid for the foreseeable future, the PoC-128 goes well beyond the state of art in securing networked embedded devices.

  3. Capacitance variation induced by microfluidic two-phase flow across insulated interdigital electrodes in lab-on-chip devices.

    Science.gov (United States)

    Dong, Tao; Barbosa, Cátia

    2015-01-26

    Microfluidic two-phase flow detection has attracted plenty of interest in various areas of biology, medicine and chemistry. This work presents a capacitive sensor using insulated interdigital electrodes (IDEs) to detect the presence of droplets in a microchannel. This droplet sensor is composed of a glass substrate, patterned gold electrodes and an insulation layer. A polydimethylsiloxane (PDMS) cover bonded to the multilayered structure forms a microchannel. Capacitance variation induced by the droplet passage was thoroughly investigated with both simulation and experimental work. Olive oil and deionized water were employed as the working fluids in the experiments to demonstrate the droplet sensor. The results show a good sensitivity of the droplet with the appropriate measurement connection. This capacitive droplet sensor is promising to be integrated into a lab-on-chip device for in situ monitoring/counting of droplets or bubbles.

  4. Analysis of single-cell differences by use of an on-chip microculture system and optical trapping.

    Science.gov (United States)

    Wakamoto, Y; Inoue, I; Moriguchi, H; Yasuda, K

    2001-09-01

    A method is described for continuous observation of isolated single cells that enables genetically identical cells to be compared; it uses an on-chip microculture system and optical tweezers. Photolithography is used to construct microchambers with 5-microm-high walls made of thick photoresist (SU-8) on the surface of a glass slide. These microchambers are connected by a channel through which cells are transported, by means of optical tweezers, from a cultivation microchamber to an analysis microchamber, or from the analysis microchamber to a waste microchamber. The microchambers are covered with a semi-permeable membrane to separate them from nutrient medium circulating through a "cover chamber" above. Differential analysis of isolated direct descendants of single cells showed that this system could be used to compare genetically identical cells under contamination-free conditions. It should thus help in the clarification of heterogeneous phenomena, for example unequal cell division and cell differentiation.

  5. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

    Directory of Open Access Journals (Sweden)

    Jim Harkin

    2009-01-01

    Full Text Available FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE, incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

  6. A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

    Science.gov (United States)

    Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

    2012-01-01

    This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

  7. Hybrid subtractive-additive-welding microfabrication for lab-on-chip applications via single amplified femtosecond laser source

    Science.gov (United States)

    Jonušauskas, Linas; Rekštytė, Sima; Buividas, Ričardas; Butkus, Simas; Gadonas, Roaldas; Juodkazis, Saulius; Malinauskas, Mangirdas

    2017-09-01

    An approach employing ultrafast laser hybrid subtractive-additive microfabrication, which combines ablation, three-dimensional nanolithography, and welding, is proposed for the realization of a lab-on-chip (LOC) device. A single amplified Yb:KGW femtosecond (fs)-pulsed laser source is shown to be suitable for fabricating microgrooves in glass slabs, polymerization of fine-meshes microfilter out of hybrid organic-inorganic photopolymer SZ2080 inside them, and, finally, sealing the whole chip with cover glass into a single monolithic piece. The created microfluidic device proved its particle sorting function by separating 1- and 10-μm polystyrene spheres in an aqueous mixture. All together, this proves that laser microfabrication based on a single amplified fs laser source is a flexible and versatile approach for the hybrid subtractive-additive manufacturing of functional mesoscale multimaterial LOC devices.

  8. On-chip hybrid photonic-plasmonic light concentrator for nanofocusing in an integrated silicon photonics platform.

    Science.gov (United States)

    Luo, Ye; Chamanzar, Maysamreza; Apuzzo, Aniello; Salas-Montiel, Rafael; Nguyen, Kim Ngoc; Blaize, Sylvain; Adibi, Ali

    2015-02-11

    The enhancement and confinement of electromagnetic radiation to nanometer scale have improved the performances and decreased the dimensions of optical sources and detectors for several applications including spectroscopy, medical applications, and quantum information. Realization of on-chip nanofocusing devices compatible with silicon photonics platform adds a key functionality and provides opportunities for sensing, trapping, on-chip signal processing, and communications. Here, we discuss the design, fabrication, and experimental demonstration of light nanofocusing in a hybrid plasmonic-photonic nanotaper structure. We discuss the physical mechanisms behind the operation of this device, the coupling mechanisms, and how to engineer the energy transfer from a propagating guided mode to a trapped plasmonic mode at the apex of the plasmonic nanotaper with minimal radiation loss. Optical near-field measurements and Fourier modal analysis carried out using a near-field scanning optical microscope (NSOM) show a tight nanofocusing of light in this structure to an extremely small spot of 0.00563(λ/(2n(rmax)))(3) confined in 3D and an exquisite power input conversion of 92%. Our experiments also verify the mode selectivity of the device (low transmission of a TM-like input mode and high transmission of a TE-like input mode). A large field concentration factor (FCF) of about 4.9 is estimated from our NSOM measurement with a radius of curvature of about 20 nm at the apex of the nanotaper. The agreement between our theory and experimental results reveals helpful insights about the operation mechanism of the device, the interplay of the modes, and the gradual power transfer to the nanotaper apex.

  9. All-MXene (2D titanium carbide) solid-state microsupercapacitors for on-chip energy storage

    KAUST Repository

    Peng, You-Yu

    2016-08-01

    On-chip energy storage is a rapidly evolving research topic, opening doors for integration of batteries and supercapacitors at microscales on rigid and flexible platforms. Recently, a new class of two-dimensional (2D) transition metal carbides and nitrides (so-called MXenes) has shown great promise in electrochemical energy storage applications. Here, we report the fabrication of all-MXene (Ti3C2Tx) solid-state interdigital microsupercapacitors by employing a solution spray-coating, followed by a photoresist-free direct laser cutting method. Our prototype devices consisted of two layers of Ti3C2Tx with two different flake sizes. The bottom layer was stacked large-size MXene flakes (typical lateral dimensions of 3-6 μm) serving mainly as current collectors. The top layer was made of small-size MXene flakes (~1 μm) with a large number of defects and edges as the electroactive layer responsible for energy storage. Compared to Ti3C2Tx micro-supercapacitors with platinum current collectors, the all-MXene devices exhibited much lower contact resistance, higher capacitances and better rate-capabilities. The areal and volumetric capacitances of ~27 mF cm-2 and ~337 F cm-3, respectively, at a scan rate of 20 mV s-1 were achieved. The devices also demonstrated their excellent cyclic stability, with 100% capacitance retention after 10,000 cycles at a scan rate of 50 mV s-1. This study opens up a plethora of possible designs for high-performance on-chip devices employing different chemistries, flake sizes and morphologies of MXenes and their heterostructures.

  10. A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Pezzarossa, Luca; Schoeberl, Martin

    2017-01-01

    to all slave nodes for a 16-core plat- form in between 500 and 3500 clock cycles. The results also show that the hardware cost for an FPGA implementation of our architecture is considerably smaller than other network-on-chips with similar re- configuration functionalities, and that the worst-case time...

  11. Lab-on-chip system combining a microfluidic-ELISA with an array of amorphous silicon photosensors for the detection of celiac disease epitopes

    Directory of Open Access Journals (Sweden)

    Francesca Costantini

    2015-12-01

    The correct operation of the developed lab-on-chip has been demonstrated using rabbit serum in the microfluidic ELISA. In particular, optimizing the dilution factors of both sera and Ig-HRP samples in the flowing solutions, the specific and non-specific antibodies against GPs can be successfully distinguished, showing the suitability of the presented device to effectively screen celiac disease epitopes.

  12. A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm

  13. Chip based common-path optical coherence tomography system with an on-chip microlens and multi-reference suppression algorithm

    NARCIS (Netherlands)

    Chang, Lantian; Weiss, Nicolás; van Leeuwen, Ton G.; Pollnau, Markus; de Ridder, René M.; Wörhoff, Kerstin; Subramaniam, Vinod; Kanger, Johannes S.

    2016-01-01

    We demonstrate an integrated optical probe including an on-chip microlens for a common-path swept-source optical coherence tomography system. This common-path design uses the end facet of the silicon oxynitride waveguide as the reference plane, thus eliminating the need of a space-consuming and

  14. Chip based common-path optical coherence tomography system with an on-chip microlens and multi-reference suppresion algorithm

    NARCIS (Netherlands)

    Chang, Lantian; Weiss, Nicolas; van Leeuwen, Ton; Pollnau, Markus; de Ridder, R.M.; Worhoff, Kerstin; Subramaniam, Vinod; Kanger, Johannes S.

    2016-01-01

    We demonstrate an integrated optical probe including an on-chip microlens for a common-path swept-source optical coherence tomography system. This common-path design uses the end facet of the silicon oxynitride waveguide as the reference plane, thus eliminating the need of a space-consuming and

  15. A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS.

    Science.gov (United States)

    Liu, Xu; Huang, Xiwei; Jiang, Yu; Xu, Hang; Guo, Jing; Hou, Han Wei; Yan, Mei; Yu, Hao

    2017-08-01

    Based on a 3.2-Megapixel 1.1- μm-pitch super-resolution (SR) CMOS image sensor in a 65-nm backside-illumination process, a lens-free microfluidic cytometer for complete blood count (CBC) is demonstrated in this paper. Backside-illumination improves resolution and contrast at the device level with elimination of surface treatment when integrated with microfluidic channels. A single-frame machine-learning-based SR processing is further realized at system level for resolution correction with minimum hardware resources. The demonstrated microfluidic cytometer can detect the platelet cells (< 2 μm) required in CBC, hence is promising for point-of-care diagnostics.

  16. Measuring biotherapeutic viscosity and degradation on-chip with particle diffusometry.

    Science.gov (United States)

    Clayton, K N; Lee, D; Wereley, S T; Kinzer-Ursem, T L

    2017-11-21

    In the absence of efficient ways to test drug stability and efficacy, pharmaceuticals that have been stored outside of set temperature conditions are destroyed, often at great cost. This is especially problematic for biotherapeutics, which are highly sensitive to temperature fluctuations. Current platforms for assessing the stability of protein-based biotherapeutics in high throughput and in low volumes are unavailable outside of research and development laboratories and are not efficient for use in production, quality control, distribution, or clinical settings. In these alternative environments, microanalysis platforms could provide significant advantages for the characterization of biotherapeutic degradation. Here we present particle diffusometry (PD), a new technique to study degradation of biotherapeutic solutions. PD uses a simple microfluidic chip and microscope setup to calculate the Brownian motion of particles in a quiescent solution using a variation of particle image velocimetry (PIV) fundamentals. We show that PD can be used to measure the viscosity of protein solutions to discriminate native protein from degraded samples as well as to determine the change in viscosity as a function of therapeutic concentration. PD viscosity analysis is applied to two particularly important biotherapeutic preparations: insulin, a commonly used protein for diabetic patients, and monoclonal antibodies which are an emerging class of biotherapeutics used to treat a variety of diseases such as autoimmune disorders and cancer. PD-based characterization of solution viscosity is a new tool for biotherapeutic analysis, and owing to its easy setup could readily be implemented at key points of the pharmaceutical delivery chain and in clinical settings.

  17. Smartphone technology can be transformative to the deployment of lab-on-chip diagnostics.

    Science.gov (United States)

    Erickson, David; O'Dell, Dakota; Jiang, Li; Oncescu, Vlad; Gumus, Abdurrahman; Lee, Seoho; Mancuso, Matthew; Mehta, Saurabh

    2014-09-07

    The rapid expansion of mobile technology is transforming the biomedical landscape. By 2016 there will be 260 M active smartphones in the US and millions of health accessories and software "apps" running off them. In parallel with this have come major technical achievements in lab-on-a-chip technology leading to incredible new biochemical sensors and molecular diagnostic devices. Despite these advancements, the uptake of lab-on-a-chip technologies at the consumer level has been somewhat limited. We believe that the widespread availability of smartphone technology and the capabilities they offer in terms of computation, communication, social networking, and imaging will be transformative to the deployment of lab-on-a-chip type technology both in the developed and developing world. In this paper we outline why we believe this is the case, the new business models that may emerge, and detail some specific application areas in which this synergy will have long term impact, namely: nutrition monitoring and disease diagnostics in limited resource settings.

  18. Fiscal 2000 research achievement report on the research and development of advanced design technologies for system-on-chip; 2000 nendo system on chip sentan sekkei gijutsu no kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-05-01

    Efforts were made to develop technologies for rapid improvement in SoC (system on chip) design productivity. In concrete terms, the concept of V-core (virtual core) was introduced into SoC design for the establishment of reusing technology and design automation in the uppermost stream region of designing. Activities were conducted in the two fields of (1) research and development of V-core based design technology and (2) research and development of a V-core database. Efforts exerted in field (1) aimed at the research and development of system specifications description technology, architecture generation technology, soft V-core internal structure optimization technology, optimized RTL (register transfer level) description generation technology, and system performance verification technology. In field (2), efforts were made to develop core database technology, core development support tools, core verification technology, and design assets verification technology. The system specifications description technology is a technique to define SoC system level specifications (degree of model abstraction). (NEDO)

  19. ISO/OSI compliant network-on-chip implementation for CNN applications

    Science.gov (United States)

    Malki, Suleyman; Hansson, Andreas; Spaanenburg, Lambert; Akesson, Benny

    2005-06-01

    The paper investigates the potential for a packet switching network for real-time image processing by a Cellular Neural Network (CNN) implemented on a Field-Programmable Gate-Array (FPGA). The implementation of a CNN requires several parameter restrictions with respect to the universal concept. For instance, the number representation and the cloning template are often confined to respectively 8 bits and a neighborhood of 1. It has been shown that optimal (i.e. minimal level) CNN architectures as derived from a morphological specification of the desired operation lead to arbitrarily large templates. A subsequent transformation step can turn this into a sequence of smaller templates for a specified hardware platform. The existence of a generic platform that can already handle the universal CNN architecture for prototyping and verification eliminates this need for technology-driven performance degradation. The proposed packet switcher consists of a physical layer where the CNN nodal function is performed, a data-link layer where the nodal data are maintained, a network layer with the packet receiver and sender and the actual switch as element of the transport layer. This ISO/OSI compliant level-wise structure monitors the network parameters and autonomously adjusts for the size of the neighborhood. It separates the broadcast of the network variables from the actual computation, allowing each to be executed at its own speed. The concept is tested on a re-design of the ILVA architecture and has been shown to handle arbitrary neighborhoods and precision at a comparable size and speed (1 node per BlockRAM / multiplier module @220 MHz clock).

  20. Rearrangeable and exchangeable optical module with system-on-chip for wearable functional near-infrared spectroscopy system.

    Science.gov (United States)

    Funane, Tsukasa; Numata, Takashi; Sato, Hiroki; Hiraizumi, Shinsuke; Hasegawa, Yuichi; Kuwabara, Hidenobu; Hasegawa, Kiyoshi; Kiguchi, Masashi

    2018-01-01

    We developed a system-on-chip (SoC)-incorporated light-emitting diode (LED) and avalanche photodiode (APD) modules to improve the usability and flexibility of a fiberless wearable functional near-infrared spectroscopy (fNIRS) system. The SoC has a microprocessing unit and programmable circuits. The time division method and the lock-in method were used for separately detecting signals from different positions and signals of different wavelengths, respectively. Each module autonomously works for this time-divided-lock-in measurement with a high sensitivity for haired regions. By supplying [Formula: see text] of power and base and data clocks, the LED module emits both 730- and 855-nm wavelengths of light, amplitudes of which are modulated in each lock-in frequency generated from the base clock, and the APD module provides the lock-in detected signals synchronizing with the data clock. The SoC provided many functions, including automatic-power-control of the LED, automatic judgment of detected power level, and automatic-gain-control of the programmable gain amplifier. The number and the arrangement of modules can be adaptively changed by connecting this exchangeable modules in a daisy chain and setting the parameters dependent on the probing position. Therefore, users can configure a variety of arrangements (single- or multidistance combinations) of them with this module-based system.

  1. Influence of Electric Fields and Conductivity on Pollen Tube Growth assessed via Electrical Lab-on-Chip

    Science.gov (United States)

    Agudelo, Carlos; Packirisamy, Muthukumaran; Geitmann, Anja

    2016-01-01

    Pollen tubes are polarly growing plant cells that are able to rapidly respond to a combination of chemical, mechanical, and electrical cues. This behavioural feature allows them to invade the flower pistil and deliver the sperm cells in highly targeted manner to receptive ovules in order to accomplish fertilization. How signals are perceived and processed in the pollen tube is still poorly understood. Evidence for electrical guidance in particular is vague and highly contradictory. To generate reproducible experimental conditions for the investigation of the effect of electric fields on pollen tube growth we developed an Electrical Lab-on-Chip (ELoC). Pollen from the species Camellia displayed differential sensitivity to electric fields depending on whether the entire cell or only its growing tip was exposed. The response to DC fields was dramatically higher than that to AC fields of the same strength. However, AC fields were found to restore and even promote pollen growth. Surprisingly, the pollen tube response correlated with the conductivity of the growth medium under different AC frequencies—consistent with the notion that the effect of the field on pollen tube growth may be mediated via its effect on the motion of ions. PMID:26804186

  2. Lab-in-a-tube: ultracompact components for on-chip capture and detection of individual micro-/nanoorganisms.

    Science.gov (United States)

    Smith, Elliot J; Xi, Wang; Makarov, Denys; Mönch, Ingolf; Harazim, Stefan; Bolaños Quiñones, Vladimir A; Schmidt, Christine K; Mei, Yongfeng; Sanchez, Samuel; Schmidt, Oliver G

    2012-05-08

    A review of present and future on-chip rolled-up devices, which can be used to develop lab-in-a-tube total analysis systems, is presented. Lab-in-a-tube is the integration of numerous rolled-up components into a single device constituting a microsystem of hundreds/thousands of independent units on a chip, each individually capable of sorting, detecting and analyzing singular organisms. Such a system allows for a scale-down of biosensing systems, while at the same time increasing the data collection through a large, smart array of individual biosensors. A close look at these ultracompact components which have been developed over the past decade is given. Methods for the capture of biomaterial are laid out and progress of cell culturing in three-dimensional scaffolding is detailed. Rolled-up optical sensors based on photoluminescence, optomechanics, optofluidics and metamaterials are presented. Magnetic sensors are introduced as well as electrical components including heating, energy storage and resistor devices.

  3. Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

    Science.gov (United States)

    Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

    2018-01-01

    Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

  4. High-resolution, on-chip RF photonic signal processor using Brillouin gain shaping and RF interference.

    Science.gov (United States)

    Choudhary, Amol; Liu, Yang; Morrison, Blair; Vu, Khu; Choi, Duk-Yong; Ma, Pan; Madden, Stephen; Marpaung, David; Eggleton, Benjamin J

    2017-07-19

    Integrated microwave photonics has strongly emerged as a next-generation technology to address limitations of conventional RF electronics for wireless communications. High-resolution RF signal processing still remains a challenge due to limitations in technology that offer sub-GHz spectral resolution, in particular at high carrier frequencies. In this paper, we present an on-chip high-resolution RF signal processor, capable of providing high-suppression spectral filtering, large phase shifts and ns-scale time delays. This was achieved through tailoring of the Brillouin gain profiles using Stokes and anti-Stokes resonances combined with RF interferometry on a low-loss photonic chip with strong opto-acoustic interactions. Using an optical power of <40 mW, reconfigurable filters with a bandwidth of ~20 MHz and an extinction ratio in excess of 30 dB are synthesized. Through the concept of vector addition of RF signals we demonstrate, almost an order of magnitude amplification in the phase and delay compared to devices purely based upon the slow-light effect of Brillouin scattering. This concept allows for versatile and power-efficient manipulation of the amplitude and phase of RF signals on a photonic chip for applications in wireless communications including software defined radios and beam forming.

  5. System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

    Directory of Open Access Journals (Sweden)

    Daniel D. Gajski

    2008-07-01

    Full Text Available The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

  6. Phagocytic response to fully controlled plural stimulation of antigens on macrophage using on-chip microcultivation system

    Directory of Open Access Journals (Sweden)

    Wakamoto Yuichi

    2006-08-01

    Full Text Available Abstract To understand the control mechanism of innate immune response in macrophages, a series of phagocytic responses to plural stimulation of antigens on identical cells was observed. Two zymosan particles, which were used as antigens, were put on different surfaces of a macrophage using optical tweezers in an on-chip single-cell cultivation system, which maintains isolated conditions of each macrophage during their cultivation. When the two zymosan particles were attached to the macrophage simultaneously, the macrophage responded and phagocytosed both of the antigens simultaneously. In contrast, when the second antigen was attached to the surface after the first phagocytosis had started, the macrophage did not respond to the second stimulation during the first phagocytosis; the second phagocytosis started only after the first process had finished. These results indicate that (i phagocytosis in a macrophage is not an independent process when there are plural stimulations; (ii the response of the macrophage to the second stimulation is related to the time" delay from the first stimulation. Stimulations that occur at short time intervals resulted in simultaneous phagocytosis, while a second stimulation that is delayed long enough might be neglected until the completion of the first phagocytic process.

  7. System on chip (SoC) microcontrollers (μC) as digitisers for ion beam analysis (IBA) instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J., E-mail: harry.j@whitlow.se

    2016-09-15

    Data digitisation of the analogue signals from detectors to digital data is an essential process in ion beam analysis (IBA). The low-cost, easy availability and development environments that have a low learning threshold makes system-on-chip (SoC) microcontrollers (μC) attractive for this task. These μC combine, on one die, analogue and digital inputs and outputs with serial USB interfaces, which opens up simple implementation of tailor-made interfaces for specific IBA measurement systems. We have investigated the design and performance limitations based on development of three different digitisation interfaces for IBA. These were a two-channel nuclear instrumentation module (NIM) ADC event mode interface (EMI) for a high-resolution magnetic RBS spectrometer, a simple headless-multi-channel analyser (MCA) and a combined dual channel headless MCA and EMI. It is shown that SoC μC based interfaces for digitisation of analogue spectroscopy pulses in IBA systems can be implemented for material costs less than 100 €. The performance of the SoC devices for many IBA applications is close to what can be achieved with state-of-the-art instruments. The simple pulse spectroscopy interface circuit and software are included in the auxiliary archive.

  8. Simulation of Ion Source’s Control System on Cyclotron using Programmable System on Chip (PSoC

    Directory of Open Access Journals (Sweden)

    R.S. Darmawan

    2011-12-01

    Full Text Available Cyclotron is an ion accelerator machine with spiral beam path. Ion source system is one of the main systems which its function is to produce ions that will be accelerated. In order to obtain maximum ion current, the ion source must be equipped with a control system that control mechanical system that will adjust the position of the ion source. The mechanical system able to make adjustment in three different axis, that is x, y and z axis. The mechanical system consists of a stepper motor and a set of gears. The control system using Programmable System on Chip (PSoC utilizes its user module from the Random Sequence group, that is 8-bit Pseudo Random Sequence Generator (PRS8.For x and y axis, if the stepper motor rotate one rotation that means the support will be pushed or pulled 2.5 mm. While for z axis if the stepper motor rotate one rotation that means the support will be pushed or pulled 0.83 mm. The largest deviation of the stepper motor is 2° with error percentage is 1.09%. The mean value of step of the stepper motor is 2.03 step per second

  9. System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

    Directory of Open Access Journals (Sweden)

    Dömer Rainer

    2008-01-01

    Full Text Available Abstract The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

  10. Extremely broadband, on-chip optical nonreciprocity enabled by mimicking nonlinear anti-adiabatic quantum jumps near exceptional points.

    Science.gov (United States)

    Choi, Youngsun; Hahn, Choloong; Yoon, Jae Woong; Song, Seok Ho; Berini, Pierre

    2017-01-20

    Time-asymmetric state-evolution properties while encircling an exceptional point are presently of great interest in search of new principles for controlling atomic and optical systems. Here, we show that encircling-an-exceptional-point interactions that are essentially reciprocal in the linear interaction regime make a plausible nonlinear integrated optical device architecture highly nonreciprocal over an extremely broad spectrum. In the proposed strategy, we describe an experimentally realizable coupled-waveguide structure that supports an encircling-an-exceptional-point parametric evolution under the influence of a gain saturation nonlinearity. Using an intuitive time-dependent Hamiltonian and rigorous numerical computations, we demonstrate strictly nonreciprocal optical transmission with a forward-to-backward transmission ratio exceeding 10 dB and high forward transmission efficiency (∼100%) persisting over an extremely broad bandwidth approaching 100 THz. This predicted performance strongly encourages experimental realization of the proposed concept to establish a practical on-chip optical nonreciprocal element for ultra-short laser pulses and broadband high-density optical signal processing.

  11. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-04-01

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

  12. Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.

    Science.gov (United States)

    Dolev, Danny; Függer, Matthias; Posch, Markus; Schmid, Ulrich; Steininger, Andreas; Lenzen, Christoph

    2014-06-01

    We present the first implementation of a distributed clock generation scheme for Systems-on-Chip that recovers from an unbounded number of arbitrary transient faults despite a large number of arbitrary permanent faults. We devise self-stabilizing hardware building blocks and a hybrid synchronous/asynchronous state machine enabling metastability-free transitions of the algorithm's states. We provide a comprehensive modeling approach that permits to prove, given correctness of the constructed low-level building blocks, the high-level properties of the synchronization algorithm (which have been established in a more abstract model). We believe this approach to be of interest in its own right, since this is the first technique permitting to mathematically verify, at manageable complexity, high-level properties of a fault-prone system in terms of its very basic components. We evaluate a prototype implementation, which has been designed in VHDL, using the Petrify tool in conjunction with some extensions, and synthesized for an Altera Cyclone FPGA.

  13. Obstacle Recognition Based on Machine Learning for On-Chip LiDAR Sensors in a Cyber-Physical System

    Directory of Open Access Journals (Sweden)

    Fernando Castaño

    2017-09-01

    Full Text Available Collision avoidance is an important feature in advanced driver-assistance systems, aimed at providing correct, timely and reliable warnings before an imminent collision (with objects, vehicles, pedestrians, etc.. The obstacle recognition library is designed and implemented to address the design and evaluation of obstacle detection in a transportation cyber-physical system. The library is integrated into a co-simulation framework that is supported on the interaction between SCANeR software and Matlab/Simulink. From the best of the authors’ knowledge, two main contributions are reported in this paper. Firstly, the modelling and simulation of virtual on-chip light detection and ranging sensors in a cyber-physical system, for traffic scenarios, is presented. The cyber-physical system is designed and implemented in SCANeR. Secondly, three specific artificial intelligence-based methods for obstacle recognition libraries are also designed and applied using a sensory information database provided by SCANeR. The computational library has three methods for obstacle detection: a multi-layer perceptron neural network, a self-organization map and a support vector machine. Finally, a comparison among these methods under different weather conditions is presented, with very promising results in terms of accuracy. The best results are achieved using the multi-layer perceptron in sunny and foggy conditions, the support vector machine in rainy conditions and the self-organized map in snowy conditions.

  14. Obstacle Recognition Based on Machine Learning for On-Chip LiDAR Sensors in a Cyber-Physical System.

    Science.gov (United States)

    Castaño, Fernando; Beruvides, Gerardo; Haber, Rodolfo E; Artuñedo, Antonio

    2017-09-14

    Collision avoidance is an important feature in advanced driver-assistance systems, aimed at providing correct, timely and reliable warnings before an imminent collision (with objects, vehicles, pedestrians, etc.). The obstacle recognition library is designed and implemented to address the design and evaluation of obstacle detection in a transportation cyber-physical system. The library is integrated into a co-simulation framework that is supported on the interaction between SCANeR software and Matlab/Simulink. From the best of the authors' knowledge, two main contributions are reported in this paper. Firstly, the modelling and simulation of virtual on-chip light detection and ranging sensors in a cyber-physical system, for traffic scenarios, is presented. The cyber-physical system is designed and implemented in SCANeR. Secondly, three specific artificial intelligence-based methods for obstacle recognition libraries are also designed and applied using a sensory information database provided by SCANeR. The computational library has three methods for obstacle detection: a multi-layer perceptron neural network, a self-organization map and a support vector machine. Finally, a comparison among these methods under different weather conditions is presented, with very promising results in terms of accuracy. The best results are achieved using the multi-layer perceptron in sunny and foggy conditions, the support vector machine in rainy conditions and the self-organized map in snowy conditions.

  15. Efficient on-chip hotspot removal combined solution of thermoelectric cooler and mini-channel heat sink

    International Nuclear Information System (INIS)

    Hao, Xiaohong; Peng, Bei; Xie, Gongnan; Chen, Yi

    2016-01-01

    Highlights: • A combined solution of thermoelectric cooler (TEC) and mini-channel heat sink to remove the hotspot of the chip has been proposed. • The TEC's mathematical model is established to assess its work performance. • A comparative study on the proposed efficient On-Chip Hotspot Removal Combined Solution. - Abstract: Hotspot will significantly degrade the reliability and performance of the electronic equipment. The efficient removal of hotspot can make the temperature distribution uniform, and ensure the reliable operation of the electronic equipment. This study proposes a combined solution of thermoelectric cooler (TEC) and mini-channel heat sink to remove the hotspot of the chip in the electronic equipment. Firstly, The TEC's mathematical model is established to assess its work performance under different boundary conditions. Then, the hotspot removal capability of the TEC is discussed for different cooling conditions, which has shown that the combined equipment has better hotspot removal capability compared with others. Finally, A TEC is employed to investigate the hotspot removal capacity of the combined solution, and the results have indicated that it can effectively remove hotspot in the diameter of 0.5 mm, the power density of 600W/cm 2 when its working current is 3A and heat transfer thermal resistance is 0 K/W.

  16. Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography.

    Science.gov (United States)

    Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

    2018-04-11

    The development of multinode quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates, and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of preselected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multimode interference beamsplitter via in situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with g (2) (0) = 0.13 ± 0.02. Due to its high patterning resolution as well as spectral and spatial control, in situ electron beam lithography allows for integration of preselected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way toward multinode, fully integrated quantum photonic chips.

  17. GPGPU accelerated Krylov methods for compact modeling of on-chip passive integrated structures within the Chameleon-RF workflow

    Directory of Open Access Journals (Sweden)

    Sebastian Gim

    2012-11-01

    Full Text Available Continued device scaling into the nanometer region and high frequencies of operation well into the multi-GHz region has given rise to new effects that previously had negligible impact but now present greater challenges and unprecedented complexity to designing successful mixed-signal silicon. The Chameleon-RF project was conceived to address these challenges. Creative use of domain decomposition, multi grid techniques or reduced order modeling techniques (ROM can be selectively applied at all levels of the process to efficiently prune down degrees of freedom (DoFs. However, the simulation of complex systems within a reasonable amount of time remains a computational challenge. This paper presents work done in the incorporation of GPGPU technology to accelerate Krylov based algorithms used for compact modeling of on-chip passive integrated structures within the workflow of the Chameleon-RF project. Based upon insight gained from work done above, a novel GPGPU accelerated algorithm was developed for the Krylov ROM (kROM methods and is described here for the benefit of the wider community.

  18. System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan R.

    2015-05-01

    New radar applications need to perform complex algorithms and process large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression for real-time transceiver optimization are presented, they are based on a System-on-Chip architecture for Xilinx devices. This study also evaluates the performance of dedicated coprocessor as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through the high performance AXI buses, to perform floating-point operations, control the processing blocks, and communicate with external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band tested together with a low-cost channel emulator for different types of waveforms.

  19. Rapid Development of System-on-Chip (SoC for Network-Enabled Visible Light Communications

    Directory of Open Access Journals (Sweden)

    Trio Adiono

    2018-03-01

    Full Text Available Visible Light Communication (VLC is an emerging optical communication technology with rapid development nowadays. VLC is considered as a compliment and successor of radio-frequency (RF wireless communication. There are various typical implementations of VLC in which one of them is for exchanging data TCP/IP packets, thus the user can browse the internet as in established Wireless fidelity (Wi-Fi technology. Briefly, we can call it by Light fidelity (Li-Fi. This paper described the design and implementation of System-on-Chip (SoC subsystem for Li-Fi application where the implemented SoC consists of hardware (H/W and software (S/W. In the H/W aspect, Physical Layer (PHY is made by using UART communication with Ethernet connection to communicate with Host/Device personal-computer (PC. In the S/W aspect, Xillinux operating system (OS is used. The H/W- as well as S/W-SoC, are realized in FPGA Zybo Zynq-7000 EPP development board. The functional test result shows (without optical channel or Zybo-to-Zybo only that the implemented SoC is working as expected. It is able to exchange TCP/IP packets between two PCs. Moreover, Ethernet connection has bandwidth up to 83.6 Mbps and PHY layer baud rate has bandwidth up to 921600 bps.

  20. Si nanopatterning by reactive ion etching through an on-chip self-assembled porous anodic alumina mask

    Science.gov (United States)

    Gianneta, Violetta; Olziersky, Antonis; Nassiopoulou, Androula G.

    2013-02-01

    We report on Si nanopatterning through an on-chip self-assembled porous anodic alumina (PAA) masking layer using reactive ion etching based on fluorine chemistry. Three different gases/gas mixtures were investigated: pure SF6, SF6/O2, and SF6/CHF3. For the first time, a systematic investigation of the etch rate and process anisotropy was performed. It was found that in all cases, the etch rate through the PAA mask was 2 to 3 times lower than that on non-masked areas. With SF6, the etching process is, as expected, isotropic. By the addition of O2, the etch rate does not significantly change, while anisotropy is slightly improved. The lowest etch rate and the best anisotropy were obtained with the SF6/CHF3 gas mixture. The pattern of the hexagonally arranged pores of the alumina film is, in this case, perfectly transferred to the Si surface. This is possible both on large areas and on restricted pre-defined areas on the Si wafer.