WorldWideScience

Sample records for junctionless nanowire transistors

  1. A Vertically Integrated Junctionless Nanowire Transistor.

    Science.gov (United States)

    Lee, Byung-Hyun; Hur, Jae; Kang, Min-Ho; Bang, Tewook; Ahn, Dae-Chul; Lee, Dongil; Kim, Kwang-Hee; Choi, Yang-Kyu

    2016-03-09

    A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

  2. Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor.

    Science.gov (United States)

    Chen, Lin; Cai, Fuxi; Otuonye, Ugo; Lu, Wei D

    2016-01-13

    Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 μA/μm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.

  3. In-situ doped junctionless polysilicon nanowires field effect transistors for low-cost biosensors

    DEFF Research Database (Denmark)

    Zulfiqar, Azeem; Patou, François; Pfreundt, Andrea

    2017-01-01

    Silicon nanowire (SiNW) field effect transistor based biosensors have already been proven to be a promising tool to detect biomolecules. However, the most commonly used fabrication techniques involve expensive Silicon-On-Insulator (SOI) wafers, E-beam lithography and ion-implantation steps....... In the work presented here, a top down approach to fabricate SiNW junctionless field effect biosensors using novel in-situ doped polysilicon is demonstrated. The p-type polysilicon is grown with an optimum boron concentration that gives a good metal-silicon electrical contact while maintaining the doping...... level at a low enough level to provide a good sensitivity for the biosensor. The silicon nanowires are patterned using standard photolithography and a wet etch method. The metal contacts are made from magnetron sputtered TiW and e-beam evaporation of gold. The passivation of electrodes has been done...

  4. Electric-field-dependent charge delocalization from dopant atoms in silicon junctionless nanowire transistor

    Science.gov (United States)

    Wang, Hao; Han, Wei-Hua; Zhao, Xiao-Song; Zhang, Wang; Lyu, Qi-Feng; Ma, Liu-Hong; Yang, Fu-Hua

    2016-10-01

    We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping (below 30 K) and nearest-neighbor hopping (above 30 K). The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source-drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K. Project supported partly by the National Key R & D Program of China (Grant No. 2016YFA02005003) and the National Natural Science Foundation of China (Grant Nos. 61376096 and 61327813).

  5. Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

    Science.gov (United States)

    Liu-Hong, Ma; Wei-Hua, Han; Hao, Wang; Qi-feng, Lyu; Wang, Zhang; Xiang, Yang; Fu-Hua, Yang

    2016-06-01

    Silicon junctionless nanowire transistor (JNT) is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate. The performances of the transistor, i.e., current drive, threshold voltage, subthreshold swing (SS), and electron mobility are evaluated. The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K. The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to 50 K, which is attributed to the electron transport through one-dimensional (1D) subbands formed in the nanowire. Besides, the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1, implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties. This approach provides a potential application for nanoscale device patterning. Project supported by the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126) and the National Basic Research Program of China (Grant No. 2010CB934104).

  6. Design and analysis of vertical-channel gallium nitride (GaN) junctionless nanowire transistors (JNT).

    Science.gov (United States)

    Seo, Jae Hwa; Yoon, Young Jun; Lee, Hwan Gi; Yoo, Gwan Min; Jo, Young-Woo; Son, Dong-Hyeok; Lee, Jung-Hee; Cho, Eou-Sik; Cho, Seongjae; Kang, In Man

    2014-11-01

    Vertical-channel gallium nitride (GaN) junctionless nanowire transistor (JNT) has been designed and characterized by technology computer-aided design (TCAD) simulations. Various characteristics such as wide bandgap, strong polariztion field, and high electron velocity make GaN one of the attractive materials in advanced electronics in recent times. Nanowire-structured GaN can be applicable to various transistors for enhanced electrical performances by its geometrical feature. In this paper, we analyze the direct-current (DC) characteristics depending on various channel doping concentrations (N(ch)) and nanowire radii (R(NW)). Furthermore, the radio-frequency (RF) characteristics under optimized conditions are extracted by small-signal equivalent circuit modeling. For the optimally designed vertical GaN JNT demonstrated on-state current (I(on)) of 345 μA/μm and off-state current (I(off)) of 3.7 x 10(-18) A/μm with a threshold voltage (V(t)) of 0.22 V, and subthreshold swing (S) of 68 mV/dec. Besides, f(T) and f(max) under different operating conditions (gate voltage, V(GS)) have been obtained.

  7. Low-temperature study of array of dopant atoms on transport behaviors in silicon junctionless nanowire transistor

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Hao; Han, Weihua, E-mail: weihua@semi.ac.cn; Li, Xiaoming; Zhang, Yanbo; Yang, Fuhua [Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2014-09-28

    We demonstrate temperature-dependent quantum transport characteristics in silicon junctionless nanowire transistor fabricated on Silicon-on-Insulator substrate by the femtosecond laser lithography. Clear drain-current oscillations originated from dopant-induced quantum dots are observed in the initial stage of the conduction for the silicon nanowire channel at low temperatures. Arrhenius plot of the conductance indicates the transition temperature of 30 K from variable-range hopping to nearest-neighbor hopping, which can be well explained under Mott formalism. The transition of electron hopping behavior is the interplay result between the thermal activation and the Coulomb interaction.

  8. Junctionless Cooper pair transistor

    Energy Technology Data Exchange (ETDEWEB)

    Arutyunov, K. Yu., E-mail: konstantin.yu.arutyunov@jyu.fi [National Research University Higher School of Economics , Moscow Institute of Electronics and Mathematics, 101000 Moscow (Russian Federation); P.L. Kapitza Institute for Physical Problems RAS , Moscow 119334 (Russian Federation); Lehtinen, J.S. [VTT Technical Research Centre of Finland Ltd., Centre for Metrology MIKES, P.O. Box 1000, FI-02044 VTT (Finland)

    2017-02-15

    Highlights: • Junctionless Cooper pair box. • Quantum phase slips. • Coulomb blockade and gate modulation of the Coulomb gap. - Abstract: Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current–voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

  9. Simulation and Finite Element Analysis of Electrical Characteristics of Gate-all-Around Junctionless Nanowire Transistors

    Directory of Open Access Journals (Sweden)

    Neel Chatterjee

    2016-03-01

    Full Text Available Gate all around nanowire transistors is one of the widely researched semiconductor devices, which has shown possibility of further miniaturization of semiconductor devices. This structure promises better current controllability and also lowers power consumption. In this paper, Silicon and Indium Antimonide based nanowire transistors have been designed and simulated using Multiphysics simulation software to investigate on its electrical properties. Simulations have been carried out to study band bending, drain current and current density inside the device for changing gate voltages. Further analytical model of the device is developed to explain the physical mechanism behind the operation of the device to support the simulation result.

  10. Junctionless Cooper pair transistor

    Science.gov (United States)

    Arutyunov, K. Yu.; Lehtinen, J. S.

    2017-02-01

    Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current-voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

  11. Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography

    Directory of Open Access Journals (Sweden)

    Arash Dehzangi

    2011-01-01

    Full Text Available Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronics in order to decrease the energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM and wet etching on p-type Silicon On Insulator (SOI wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA. Results: We observed in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage decreased the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, making the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased.

  12. Silicon junctionless field effect transistors as room temperature terahertz detectors

    Energy Technology Data Exchange (ETDEWEB)

    Marczewski, J., E-mail: jmarcz@ite.waw.pl; Tomaszewski, D.; Zaborowski, M. [Institute of Electron Technology, al. Lotnikow 32/46, 02-668 Warsaw (Poland); Knap, W. [Institute of High Pressure Physics of the Polish Academy of Sciences, ul. Sokolowska 29/37, 01-142 Warsaw (Poland); Laboratory Charles Coulomb, Montpellier University & CNRS, Place E. Bataillon, Montpellier 34095 (France); Zagrajek, P. [Institute of Optoelectronics, Military University of Technology, ul. gen. S. Kaliskiego 2, 00-908 Warsaw (Poland)

    2015-09-14

    Terahertz (THz) radiation detection by junctionless metal-oxide-semiconductor field-effect transistors (JL MOSFETs) was studied and compared with THz detection using conventional MOSFETs. It has been shown that in contrast to the behavior of standard transistors, the junctionless devices have a significant responsivity also in the open channel (low resistance) state. The responsivity for a photolithographically defined JL FET was 70 V/W and the noise equivalent power 460 pW/√Hz. Working in the open channel state may be advantageous for THz wireless and imaging applications because of its low thermal noise and possible high operating speed or large bandwidth. It has been proven that the junctionless MOSFETs can also operate in a zero gate bias mode, which enables simplification of the THz array circuitry. Existing models of THz detection by MOSFETs were considered and it has been demonstrated that the process of detection by these junctionless devices cannot be explained within the framework of the commonly accepted models and therefore requires a new theoretical approach.

  13. An Analytical Universal Model for Symmetric Double Gate Junctionless Transistors

    Directory of Open Access Journals (Sweden)

    N. Bora

    2016-06-01

    Full Text Available An analytical surface potential based universal model for the drain current voltage characteristics of Symmetric Double gate (DG junctionless field effect transistors is presented. This novel universal model is valid for all operating regions from depletion to inversion regions of operations. The primary conduction mechanism is governed by the bulk current where the channel becomes fully depleted in turning it off. This model has been validated by using TCAD device simulating software. The comparison shows high accuracy of the proposed model.

  14. Impact of series resistance on the operation of junctionless transistors

    Science.gov (United States)

    Jeon, Dae-Young; Park, So Jeong; Mouis, Mireille; Barraud, Sylvain; Kim, Gyu-Tae; Ghibaudo, Gérard

    2017-03-01

    Transconductance (gm) and its derivative (dgm/dVg) of junctionless transistors (JLTs), considered as a possible candidate for future CMOS technology, show their unique operation properties such as bulk neutral and surface accumulation conduction. However, source/drain series resistance (Rsd) causes significant degradation of intrinsic gm and dgm/dVg behavior in JLTs. In this letter, the Rsd effects on the operation of JLTs were investigated in detail and also verified with analytical modeling equations. This work provides helpful information for a better understanding of the operation mechanism of JLTs with de-embedded Rsd effects.

  15. Compact core model for Symmetric Double-Gate Junctionless Transistors

    Science.gov (United States)

    Cerdeira, A.; Ávila, F.; Íñiguez, B.; de Souza, M.; Pavanello, M. A.; Estrada, M.

    2014-04-01

    A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation.

  16. High frequency top-down junction-less silicon nanowire resonators

    Science.gov (United States)

    Koumela, Alexandra; Hentz, Sébastien; Mercier, Denis; Dupré, Cécilia; Ollier, Eric; X-L Feng, Philip; Purcell, Stephen T.; Duraffourg, Laurent

    2013-11-01

    We report here the first realization of top-down silicon nanowires (SiNW) transduced by both junction-less field-effect transistor (FET) and the piezoresistive (PZR) effect. The suspended SiNWs are among the smallest top-down SiNWs reported to date, featuring widths down to ˜20 nm. This has been achieved thanks to a 200 mm-wafer-scale, VLSI process fully amenable to monolithic CMOS co-integration. Thanks to the very small dimensions, the conductance of the silicon nanowire can be controlled by a nearby electrostatic gate. Both the junction-less FET and the previously demonstrated PZR transduction have been performed with the same SiNW. These self-transducing schemes have shown similar signal-to-background ratios, and the PZR transduction has exhibited a relatively higher output signal. Allan deviation (σA) of the same SiNW has been measured with both schemes, and we obtain σA ˜ 20 ppm for the FET detection and σA ˜ 3 ppm for the PZR detection at room temperature and low pressure. Orders of magnitude improvements are expected from tighter electrostatic control via changes in geometry and doping level, as well as from CMOS integration. The compact, simple topology of these elementary SiNW resonators opens up new paths towards ultra-dense arrays for gas and mass sensing, time keeping or logic switching systems on the SiNW-CMOS platform.

  17. Sidewall spacer optimization for steep switching junctionless transistors

    Science.gov (United States)

    Gupta, Manish; Kranti, Abhinav

    2016-06-01

    In this work, we analyze the impact of a high permittivity (high-κ) sidewall spacer and gate dielectric on the occurrence of sub-60 mV/decade subthreshold swing (S-swing) in symmetrical junctionless (JL) double gate (DG) transistors. It is shown that steep S-swing values (≤10 mV/decade) can be achieved in JL devices with a combination of a high permittivity (high-κ) gate dielectric and a narrow low permittivity (low-κ) sidewall spacer. Implementation of a wider high-κ spacer will diminish the degree of impact ionization by the influence of the fringing component of the gate electric field, and will not be useful for steep off-to-on current transition. A wider spacer with low-κ and a narrow spacer with high-κ permittivity will be useful to limit the latching effect that can occur at lower temperatures (250 K). For high temperature operation, the decrease in the impact ionization rate can be compensated by designing a JL transistor with a thicker silicon film. The work demonstrates opportunities to enhance impact ionization at sub bandgap voltages, and proposes optimal guidelines for selecting a sidewall spacer to facilitate steep switching in JL transistors.

  18. A Dynamic Simulation on Single Gate Junctionless Field Effect Transistor Based on Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    Roya Norani

    Full Text Available We study the I-V characteristics of single gate junctionless field effect transistor by device simulation. The sample FET is simulated at different channel lengths and the I-V curve changes due to variations of and channel length have been systematically ...

  19. Silicon nanowire transistors

    CERN Document Server

    Bindal, Ahmet

    2016-01-01

    This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

  20. Modeling and simulation study of novel Double Gate Ferroelectric Junctionless (DGFJL) transistor

    Science.gov (United States)

    Mehta, Hema; Kaur, Harsupreet

    2016-09-01

    In this work we have proposed an analytical model for Double Gate Ferroelectric Junctionless Transistor (DGFJL), a novel device, which incorporates the advantages of both Junctionless (JL) transistor and Negative Capacitance phenomenon. A complete drain current model has been developed by using Landau-Khalatnikov equation and parabolic potential approximation to analyze device behavior in different operating regions. It has been demonstrated that DGFJL transistor acts as a step-up voltage transformer and exhibits subthreshold slope values less than 60 mV/dec. In order to assess the advantages offered by the proposed device, extensive comparative study has been done with equivalent Double Gate Junctionless Transistor (DGJL) transistor with gate insulator thickness same as ferroelectric gate stack thickness of DGFJL transistor. It is shown that incorporation of ferroelectric layer can overcome the variability issues observed in JL transistors. The device has been studied over a wide range of parameters and bias conditions to comprehensively investigate the device design guidelines to obtain a better insight into the application of DGFJL as a potential candidate for future technology nodes. The analytical results so derived from the model have been verified with simulated results obtained using ATLAS TCAD simulator and a good agreement has been found.

  1. Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs

    Science.gov (United States)

    Scarlet, S. Priscilla; Ambika, R.; Srinivasan, R.

    2017-07-01

    In this paper, the effect of eccentricity on Junction-based Silicon Nanowire FET, Junction-based Silicon Nanotube FET, Junctionless-based Silicon Nanowire FET, and Junctionless-based Silicon Nanotube FET is investigated. Three kinds of eccentric structures are considered here. The impact of eccentricity on effective gate oxide thickness thereby gate oxide capacitance, and effective channel width are studied using 3D numerical simulations. Average radius of an ellipse is used to generate a model which captures the impact of eccentricity on gate oxide capacitance, and verified using TCAD simulations in MOS nanowire structure. The impact of eccentricity on ON current (ION), OFF current (IOFF), ION/IOFF ratio, and Unity gain cutoff frequency are investigated. Eccentricity increases the effective gate oxide thickness, the effective channel width, ION, and IOFF but reduces ION/IOFF ratio.

  2. Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

    Energy Technology Data Exchange (ETDEWEB)

    Dib, E., E-mail: elias.dib@for.unipi.it [Dipartimento di Ingegneria dell' Informazione, Università di Pisa, 56122 Pisa (Italy); Carrillo-Nuñez, H. [Integrated Systems Laboratory ETH Zürich, Gloriastrasse 35, 8092 Zürich (Switzerland); Cavassilas, N.; Bescond, M. [IM2NP, UMR CNRS 6242, Bât. IRPHE, Technopôle de Château-Gombert, 13384 Marseille Cedex 13 (France)

    2016-01-28

    Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

  3. Back-gate effects and mobility characterization in junctionless transistor

    Science.gov (United States)

    Parihar, Mukta Singh; Liu, Fanyu; Navarro, Carlos; Barraud, Sylvain; Bawedin, Maryline; Ionica, Irina; Kranti, Abhinav; Cristoloveanu, Sorin

    2016-11-01

    This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation.

  4. Compact model for short-channel symmetric double-gate junctionless transistors

    Science.gov (United States)

    Ávila-Herrera, F.; Cerdeira, A.; Paz, B. C.; Estrada, M.; Íñiguez, B.; Pavanello, M. A.

    2015-09-01

    In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

  5. Junctionless nanowire TFET with built-in N-P-N bipolar action: Physics and operational principle

    Science.gov (United States)

    Rahimian, Morteza; Fathipour, Morteza

    2016-12-01

    In this paper, we present a novel junctionless nanowire tunneling FET (JN-TFET) in which the source region is divided into an n+ as well as a p+ type region. We will show that this structure can provide a built-in n-p-n bipolar junction transistor (BJT) action in the on state of the device. In this regime, tunneling of electrons from the source valence band into the channel conduction band enhances the hole concentration in the p+ source region. Also, the potential in this region is increased, which drives a built-in BJT transistor by forward biasing the base-emitter junction. Thus, the BJT current adds up to the normal tunneling current in the JN-TFET. Owing to the sharp switching of the JN-TFET and the high BJT current gain, the overall performance of the device, herein called "BJN-TFET," is improved. On-state currents as high as 2.17 × 10-6 A/μm and subthreshold swings as low as ˜50 mV/dec at VDS = 1 V are achieved.

  6. Nanowire Field-Effect Transistors: Sensing Simplicity?

    NARCIS (Netherlands)

    Mescher, M.

    2014-01-01

    Silicon nanowires are structures made from silicon with at least one spatial dimension in the nanometer regime (1-100 nm). From these nanowires, silicon nanowire field-effect transistors can be constructed. Since their introduction in 2001 silicon nanowire field-effect transistors have been studied

  7. Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric

    Science.gov (United States)

    Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

    2016-12-01

    In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferroelectric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart using numerical simulation. The steep subthreshold swing (SS detail. The low off-state current and high on/off current ratio could be obtained even for ultra-small transistors by optimizing the device parameters. NC-DG-JLTs have a great potential for low power dissipation applications.

  8. Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects

    Science.gov (United States)

    Kumari, Vandana; Modi, Neel; Saxena, Manoj; Gupta, Mridula

    2015-05-01

    In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.

  9. Nanowire Field-Effect Transistors: Sensing Simplicity?

    OpenAIRE

    Mescher, M

    2014-01-01

    Silicon nanowires are structures made from silicon with at least one spatial dimension in the nanometer regime (1-100 nm). From these nanowires, silicon nanowire field-effect transistors can be constructed. Since their introduction in 2001 silicon nanowire field-effect transistors have been studied because of their promising application as selective sensors for biological and chemical species. Their large surface-to-volume ratio promises an increased sensitivity compared to conventional, plan...

  10. Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

    Science.gov (United States)

    Rewari, Sonam; Nath, Vandana; Haldar, Subhasis; Deswal, S. S.; Gupta, R. S.

    2016-12-01

    In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I on/ I off ratio directing improved digital performance at higher channel lengths, reduced channel resistance ( R ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage ( V EA) which shows the capability for high-gain amplification and higher g m/ g d directing high intrinsic dc gain. Higher f Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g m3. Reduction in g m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

  11. Fabrication and characterization of junctionless carbon nanotube field effect transistor for cholesterol detection

    Science.gov (United States)

    Barik, Md. Abdul; Dutta, Jiten Ch.

    2014-08-01

    We have reported fabrication and characterization of polyaniline (PANI)/zinc oxide (ZnO) membrane-based junctionless carbon nanotube field effect transistor deposited on indium tin oxide glass plate for the detection of cholesterol (0.5-22.2 mM). Cholesterol oxidase (ChOx) has been immobilized on the PANI/ZnO membrane by physical adsorption technique. Electrical response has been recorded using digital multimeter (Agilent 3458A) in the presence of phosphate buffer saline of 50 mM, pH 7.0, and 0.9% NaCl contained in a glass pot. The results of response studies for cholesterol reveal linearity as 0.5-16.6 mM and improved sensitivity of 60 mV/decade in good agreement with Nernstian limit ˜59.2 mV/decade. The life time of this sensor has been found up to 5 months and response time of 1 s. The limit of detection with regression coefficient (r) ˜ 0.998 and Michaelis-Menten constant (Km) were found to be ˜0.25 and 1.4 mM, respectively, indicating high affinity of ChOx to cholesterol. The results obtained in this work show negligible interference with glucose and urea.

  12. Fabrication and characterization of junctionless carbon nanotube field effect transistor for cholesterol detection

    Energy Technology Data Exchange (ETDEWEB)

    Barik, Md. Abdul, E-mail: abdulnpl@gmail.com; Dutta, Jiten Ch. [Department of Electronics and Communication Engineering, Tezpur University, Napaam, Tezpur, Assam 784028 (India)

    2014-08-04

    We have reported fabrication and characterization of polyaniline (PANI)/zinc oxide (ZnO) membrane-based junctionless carbon nanotube field effect transistor deposited on indium tin oxide glass plate for the detection of cholesterol (0.5–22.2 mM). Cholesterol oxidase (ChOx) has been immobilized on the PANI/ZnO membrane by physical adsorption technique. Electrical response has been recorded using digital multimeter (Agilent 3458A) in the presence of phosphate buffer saline of 50 mM, pH 7.0, and 0.9% NaCl contained in a glass pot. The results of response studies for cholesterol reveal linearity as 0.5–16.6 mM and improved sensitivity of 60 mV/decade in good agreement with Nernstian limit ∼59.2 mV/decade. The life time of this sensor has been found up to 5 months and response time of 1 s. The limit of detection with regression coefficient (r) ∼ 0.998 and Michaelis-Menten constant (K{sub m}) were found to be ∼0.25 and 1.4 mM, respectively, indicating high affinity of ChOx to cholesterol. The results obtained in this work show negligible interference with glucose and urea.

  13. An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

    Science.gov (United States)

    Fan-Yu, Liu; Heng-Zhu, Liu; Bi-Wei, Liu; Yu-Feng, Guo

    2016-04-01

    In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SOI FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. Project supported by the Research Program of the National University of Defense Technology (Grant No. JC 13-06-04).

  14. Back-gated Nb-doped MoS2 junctionless field-effect-transistors

    Directory of Open Access Journals (Sweden)

    Gioele Mirabelli

    2016-02-01

    Full Text Available Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb. The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM and Transmission Electron Microscopy (TEM. To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm−3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM structure, showing a promising contact resistivity of 1.05 × 10−7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

  15. High temperature performance of Si:HfO2 based long channel Double Gate Ferroelectric Junctionless Transistors

    Science.gov (United States)

    Mehta, Hema; Kaur, Harsupreet

    2017-03-01

    In this work, we present a study that explores the suitability of Double Gate Ferroelectric Junctionless Transistor (DGFJL) incorporating Si:HfO2 for high temperature applications. At present, very few studies are focussed on Si:HfO2 to investigate its integrability in the present CMOS design space. Therefore, in the present study, using analytical modeling and TCAD simulations, it is demonstrated that Si:HfO2 based DGFJL exhibits superior performance in terms of substantial gain, reduced leakage currents, improved current drivability and high Ion/Ioff ratio at elevated temperatures as compared to the DGJL counterpart. The study, thus, highlights the fact that DGFJL is a potential candidate for device applications at high temperatures.

  16. Vertical Nanowire High-Frequency Transistors

    OpenAIRE

    Johansson, Sofia

    2014-01-01

    This thesis explores a novel transistor technology based on vertical InAs nanowires, which could be considered both for low-power high-frequency analog applications and for replacing Si CMOS in the continued scaling of digital electronics. The potential of this device - the vertical InAs nanowire MOSFET – lies in the combination of the outstanding transport properties of InAs and the improved electrostatic control of the gate-all-around geometry. Three generations of the vertical InAs nanowir...

  17. Vertically Integrated Multiple Nanowire Field Effect Transistor.

    Science.gov (United States)

    Lee, Byung-Hyun; Kang, Min-Ho; Ahn, Dae-Chul; Park, Jun-Young; Bang, Tewook; Jeon, Seung-Bae; Hur, Jae; Lee, Dongil; Choi, Yang-Kyu

    2015-12-09

    A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

  18. Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

    Directory of Open Access Journals (Sweden)

    Farhad Larki

    2012-12-01

    Full Text Available A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015 silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.

  19. Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

    2017-04-01

    In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

  20. Valley-engineered ultra-thin silicon for high-performance junctionless transistors

    Science.gov (United States)

    Kim, Seung-Yoon; Choi, Sung-Yool; Hwang, Wan Sik; Cho, Byung Jin

    2016-07-01

    Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.

  1. Vertical Nanowire High-Frequency Transistors

    OpenAIRE

    Johansson, Sofia

    2014-01-01

    This thesis explores a novel transistor technology based on vertical InAs nanowires, which could be considered both for low-power high-frequency analog applications and for replacing Si CMOS in the continued scaling of digital electronics. The potential of this device - the vertical InAs nanowire MOSFET – lies in the combination of the outstanding transport properties of InAs and the improved electrostatic control of the gate-all-around geometry. Three generations of the vertical InAs nano...

  2. Nanowire field effect transistors principles and applications

    CERN Document Server

    Jeong, Yoon-Ha

    2014-01-01

    Nanowire Field Effect Transistor: Basic Principles and Applications” places an emphasis on the application aspects of nanowire field effect transistors (NWFET). Device physics and electronics are discussed in a compact manner, together with the p-n junction diode and MOSFET, the former as an essential element in NWFET and the latter as a general background of the FET. During this discussion, the photo-diode, solar cell, LED, LD, DRAM, flash EEPROM and sensors are highlighted to pave the way for similar applications of NWFET. Modeling is discussed in close analogy and comparison with MOSFETs. Contributors focus on processing, electrostatic discharge (ESD) and application of NWFET. This includes coverage of solar and memory cells, biological and chemical sensors, displays and atomic scale light emitting diodes. Appropriate for scientists and engineers interested in acquiring a working knowledge of NWFET as well as graduate students specializing in this subject.

  3. Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

    Science.gov (United States)

    Roy, Debapriya; Biswas, Abhijit

    2016-09-01

    Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

  4. A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

    Science.gov (United States)

    Raksharam; Dutta, Aloke K.

    2017-04-01

    In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

  5. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

    Science.gov (United States)

    Najmzadeh, Mohammad; Berthomé, Matthieu; Sallese, Jean-Michel; Grabinski, Wladek; Ionescu, Adrian M.

    2014-08-01

    In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 × 1019 cm-3 n-type channel doping, 5-20 nm Si nanowire width together with 2 nm SiO2 gate oxide thickness were used in the quasistationary TCAD device simulations of 100 nm long channel devices (VDS = 100 mV, T = 300 K). All the extensive studies were performed in strong accumulation regime, as a first step, using a constant electron mobility model (100 cm2/V s). The effects of non-uniform electron density due to corners and quantum confinement effects are investigated. Suppressing the bias-dependency of various key MOSFET parameters e.g. series resistance, by contact engineering, and the product of channel width and gate-channel capacitance, CWeff, by rounding the sharp corners, to improve the accuracy of mobility extraction in strong accumulation is addressed in details. A significant bias-dependent series resistance modulation is reported in GAA Si nanowire junctionless nMOSFETs, leading to a significant electron mobility extraction inaccuracy of ∼50% in strong accumulation regime.

  6. Silicon nanowire field effect transistor for biosensing

    Science.gov (United States)

    Chen, Yu

    Detection and recognition of chemical ions and biological molecules are important in basic science as well as in pharmacology and medicine. Nanotechnology has made it possible to greatly enhance detection sensitivity through the use of nanowires, nanotubes, nanocrystals, nanocantilevers, and quantum dots as sensing platforms. In this work silicon nanowires are used as the conductance channel between the source and drain of a FET (field effect transistor) device and the biomolecular binding on the surface of nanowire modifies the conductance like a change in gate voltage. Due to the high surface-to-volume ratio and unique character of the silicon nanowires, this device has significant advantages in real-time, label-free and highly sensitive detection of a wide range of species, including proteins, nucleic acids and other small molecules. Here we present a biosensor fabricated from CMOS (complementary metal-oxide-semiconductor) compatible top-down methods including electron beam lithography. This method enables scalable manufacturing of multiple sensor arrays with high efficiency. In a systematic study of the device characteristics with different wire widths, we have found the sensitivity of the device increases when wire width decreases. By operating the device in appropriate bias region, the sensitivity of the device can be improved without doping or high temperature annealing. Not only can this device be used to detect the concentration of proteins and metabolites like urea or glucose, but also dynamic information like the dissociation constant can be extracted from the measurement. The device is also used to detect the clinically related cancer antigen CA 15.3 and shows potential application in cancer studies.

  7. An air gap moderates the performance of nanowire array transistors

    Science.gov (United States)

    Yang, Tong; Mehta, Jeremy S.; Mativetsky, Jeffrey M.

    2017-03-01

    Solution-processed nanowires are promising for low-cost and flexible electronics. When depositing nanowires from solution, due to stacking of the nanowires, an air gap exists between the substrate and much of the active material. Here, using confocal Raman spectroscopy, we quantify the thickness of the air gap in transistors comprising organic semiconductor nanowires. The average air gap thickness is found to be unexpectedly large, being at least three times larger than the nanowire diameter, leading to a significant impact on transistor performance. The air gap acts as an additional dielectric layer that reduces the accumulation of charge carriers due to a gate voltage. Conventional determination of the charge carrier mobility ignores the presence of an air gap, resulting in an overestimate of charge carrier accumulation and an underestimate of charge carrier mobility. It is shown that the larger the air gap, the larger the mobility correction (which can be greater than an order of magnitude) and the larger the degradation in on–off current ratio. These results demonstrate the importance of minimizing the air gap and of taking the air gap into consideration when analyzing the electrical performance of transistors consisting of stacked nanowires. This finding is applicable to all types of stacked one-dimensional materials including organic and inorganic nanowires, and carbon nanotubes.

  8. Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

    Science.gov (United States)

    Hara, Akito; Nishimura, Yuya; Ohsawa, Hiroki

    2017-03-01

    Low-temperature (LT) polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) are viable contenders for use in the backplanes of flat-panel displays and in systems-on-glass because of their superior electrical properties compared with silicon and oxide semiconductors. However, LT poly-Ge shows strong p-type characteristics. Therefore, it is not easy to reduce the leakage current using a single-gate structure such as a top-gate or bottom-gate structure. In this study, self-aligned planar metal double-gate p-channel junctionless LT poly-Ge TFTs are fabricated on a glass substrate using a 15-nm-thick solid-phase crystallized poly-Ge film and aluminum-induced lateral metallization source-drain regions (Al-LM-SD). A nominal field-effect mobility of 19 cm2 V-1 s-1 and an on/off ratio of 2 × 103 were obtained by optimizing the Al-LM-SD on a glass substrate through a simple, inexpensive LT process.

  9. Ballistic modeling of InAs nanowire transistors

    Science.gov (United States)

    Jansson, Kristofer; Lind, Erik; Wernersson, Lars-Erik

    2016-01-01

    In this work, the intrinsic performance of InAs nanowire transistors is evaluated in the ballistic limit. A self-consistent Schrödinger-Poisson solver is utilized in the cylindrical geometry, while accounting for conduction band non-parabolicity. The transistor characteristics are derived from simulations of ballistic transport within the nanowire. Using this approach, the performance is calculated for a continuous range of nanowire diameters and the transport properties are mapped. A transconductance exceeding 4S /mm is predicted at a gate overdrive of 0.5V and it is shown that the performance is improved with scaling. Furthermore, the influence from including self-consistency and non-parabolicity in the band structure simulations is quantified. It is demonstrated that the effective mass approximation underestimates the transistor performance due to the highly non-parabolic conduction band in InAs. Neglecting self-consistency severely overestimates the device performance, especially for thick nanowires. The error introduced by both of these approximations gets increasingly worse under high bias conditions.

  10. Reconfigurable quadruple quantum dots in a silicon nanowire transistor

    Energy Technology Data Exchange (ETDEWEB)

    Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F. [Hitachi Cambridge Laboratory, J. J. Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Tagliaferri, M. L. V. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Dipartimento di Scienza dei Materiali, Universit di Milano-Bicocca, Via Cozzi 53, 20125 Milano (Italy); Vinet, M. [CEA/LETI-MINATEC, CEA-Grenoble, 17 rue des martyrs, F-38054 Grenoble (France); Sanquer, M. [SPSMS, UMR-E CEA/UJF-Grenoble 1, INAC, 17 rue des Martyrs, 38054 Grenoble (France); Ferguson, A. J. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom)

    2016-05-16

    We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

  11. Ferromagnetic germanide in Ge nanowire transistors for spintronics application.

    Science.gov (United States)

    Tang, Jianshi; Wang, Chiu-Yen; Hung, Min-Hsiu; Jiang, Xiaowei; Chang, Li-Te; He, Liang; Liu, Pei-Hsuan; Yang, Hong-Jie; Tuan, Hsing-Yu; Chen, Lih-Juann; Wang, Kang L

    2012-06-26

    To explore spintronics applications for Ge nanowire heterostructures formed by thermal annealing, it is critical to develop a ferromagnetic germanide with high Curie temperature and take advantage of the high-quality interface between Ge and the formed ferromagnetic germanide. In this work, we report, for the first time, the formation and characterization of Mn(5)Ge(3)/Ge/Mn(5)Ge(3) nanowire transistors, in which the room-temperature ferromagnetic germanide was found through the solid-state reaction between a single-crystalline Ge nanowire and Mn contact pads upon thermal annealing. The atomically clean interface between Mn(5)Ge(3) and Ge with a relatively small lattice mismatch of 10.6% indicates that Mn(5)Ge(3) is a high-quality ferromagnetic contact to Ge. Temperature-dependent I-V measurements on the Mn(5)Ge(3)/Ge/Mn(5)Ge(3) nanowire heterostructure reveal a Schottky barrier height of 0.25 eV for the Mn(5)Ge(3) contact to p-type Ge. The Ge nanowire field-effect transistors built on the Mn(5)Ge(3)/Ge/Mn(5)Ge(3) heterostructure exhibit a high-performance p-type behavior with a current on/off ratio close to 10(5), and a hole mobility of 150-200 cm(2)/(V s). Temperature-dependent resistance of a fully germanided Mn(5)Ge(3) nanowire shows a clear transition behavior near the Curie temperature of Mn(5)Ge(3) at about 300 K. Our findings of the high-quality room-temperature ferromagnetic Mn(5)Ge(3) contact represent a promising step toward electrical spin injection into Ge nanowires and thus the realization of high-efficiency spintronic devices for room-temperature applications.

  12. Electronic polymers and DNA self-assembled in nanowire transistors.

    Science.gov (United States)

    Hamedi, Mahiar; Elfwing, Anders; Gabrielsson, Roger; Inganäs, Olle

    2013-02-11

    Aqueous self-assembly of DNA and molecular electronic materials can lead to the creation of innumerable copies of identical devices, and inherently programmed complex nanocircuits. Here self-assembly of a water soluble and highly conducting polymer PEDOT-S with DNA in aqueous conditions is shown. Orientation and assembly of the conducting DNA/PEDOT-S complex into electrochemical DNA nanowire transistors is demonstrated.

  13. Gas Sensors Based on Semiconducting Nanowire Field-Effect Transistors

    Directory of Open Access Journals (Sweden)

    Ping Feng

    2014-09-01

    Full Text Available One-dimensional semiconductor nanostructures are unique sensing materials for the fabrication of gas sensors. In this article, gas sensors based on semiconducting nanowire field-effect transistors (FETs are comprehensively reviewed. Individual nanowires or nanowire network films are usually used as the active detecting channels. In these sensors, a third electrode, which serves as the gate, is used to tune the carrier concentration of the nanowires to realize better sensing performance, including sensitivity, selectivity and response time, etc. The FET parameters can be modulated by the presence of the target gases and their change relate closely to the type and concentration of the gas molecules. In addition, extra controls such as metal decoration, local heating and light irradiation can be combined with the gate electrode to tune the nanowire channel and realize more effective gas sensing. With the help of micro-fabrication techniques, these sensors can be integrated into smart systems. Finally, some challenges for the future investigation and application of nanowire field-effect gas sensors are discussed.

  14. Nanowire transistors physics of devices and materials in one dimension

    CERN Document Server

    Colinge, Jean-Pierre

    2016-01-01

    From quantum mechanical concepts to practical circuit applications, this book presents a self-contained and up-to-date account of the physics and technology of nanowire semiconductor devices. It includes a unified account of the critical ideas central to low-dimensional physics and transistor physics which equips readers with a common framework and language to accelerate scientific and technological developments across the two fields. Detailed descriptions of novel quantum mechanical effects such as quantum current oscillations, the metal-to-semiconductor transition and the transition from classical transistor to single-electron transistor operation are described in detail, in addition to real-world applications in the fields of nanoelectronics, biomedical sensing techniques, and advanced semiconductor research. Including numerous illustrations to help readers understand these phenomena, this is an essential resource for researchers and professional engineers working on semiconductor devices and materials in ...

  15. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    Science.gov (United States)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration

  16. Nanowire Tunnel Field Effect Transistors: Prospects and Pitfalls

    Science.gov (United States)

    Sylvia, Somaia Sarwat

    The tunnel field effect transistor (TFET) has the potential to operate at lower voltages and lower power than the field effect transistor (FET). The TFET can circumvent the fundamental thermal limit of the inverse subthreshold slope (S) by exploiting interband tunneling of non-equilibrium "cold" carriers. The conduction mechanism in the TFET is governed by band-to-band tunneling which limits the drive current. TFETs built with III-V materials like InAs and InSb can produce enough tunneling current because of their small direct bandgap. Our simulation results show that although they require highly degenerate source doping to support the high electric fields in the tunnel region, the devices achieve minimum inverse subthreshold slopes of 30 mV/dec. In subthreshold, these devices experience both regimes of voltage-controlled tunneling and cold-carrier injection. Numerical results based on a discretized 8-band k.p model are compared to analytical WKB theory. For both regular FETs and TFETs, direct channel tunneling dominates the leakage current when the physical gate length is reduced to 5 nm. Therefore, a survey of materials is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The tunneling effective mass gives the best indication of the relative size of the tunnel currents. Si gives the lowest overall tunnel current for both the conduction and valence band and, therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. Our numerical simulation shows that the finite number, random placement, and discrete nature of the dopants in the source of an InAs nanowire (NW) TFET affect both the mean value and the variance of the drive current and the inverse subthreshold slope. The discrete doping model gives an average drive current and an inverse subthreshold slope that are less than those predicted from the homogeneous doping model. The doping density required to achieve a target drive current is

  17. A silicon carbide nanowire field effect transistor for DNA detection.

    Science.gov (United States)

    Fradetal, L; Bano, E; Attolini, G; Rossi, F; Stambouli, V

    2016-06-10

    This work reports on the label-free electrical detection of DNA molecules for the first time, using silicon carbide (SiC) as a novel material for the realization of nanowire field effect transistors (NWFETs). SiC is a promising semiconductor for this application due to its specific characteristics such as chemical inertness and biocompatibility. Non-intentionally n-doped SiC NWs are first grown using a bottom-up vapor-liquid-solid (VLS) mechanism, leading to the NWs exhibiting needle-shaped morphology, with a length of approximately 2 μm and a diameter ranging from 25 to 60 nm. Then, the SiC NWFETs are fabricated and functionalized with DNA molecule probes via covalent coupling using an amino-terminated organosilane. The drain current versus drain voltage (I d-V d) characteristics obtained after the DNA grafting and hybridization are reported from the comparative and simultaneous measurements carried out on the SiC NWFETs, used either as sensors or references. As a representative result, the current of the sensor is lowered by 22% after probe DNA grafting and by 7% after target DNA hybridization, while the current of the reference does not vary by more than ±0.6%. The current decrease confirms the field effect induced by the negative charges of the DNA molecules. Moreover, the selectivity, reproducibility, reversibility and stability of the studied devices are emphasized by de-hybridization, non-complementary hybridization and re-hybridization experiments. This first proof of concept opens the way for future developments using SiC-NW-based sensors.

  18. Quantum confinement induced performance enhancement in sub-5-nm lithographic Si nanowire transistors.

    Science.gov (United States)

    Trivedi, Krutarth; Yuk, Hyungsang; Floresca, Herman Carlo; Kim, Moon J; Hu, Walter

    2011-04-13

    We demonstrate lithographically fabricated Si nanowire field effect transistors (FETs) with long Si nanowires of tiny cross sectional size (∼3-5 nm) exhibiting high performance without employing complementarily doped junctions or high channel doping. These nanowire FETs show high peak hole mobility (as high as over 1200 cm(2)/(V s)), current density, and drive current as well as low drain leakage current and high on/off ratio. Comparison of nanowire FETs with nanobelt FETs shows enhanced performance is a result of significant quantum confinement in these 3-5 nm wires. This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.

  19. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  20. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  1. High performance In2O3 nanowire transistors using organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Ishikawa, Fumiaki; Chen, Pochiang; Chang, Hsiao-Kang; Zhou, Chongwu; Ha, Young-geun; Liu, Jun; Facchetti, Antonio; Marks, Tobin J.; Janes, David B.

    2008-06-01

    We report the fabrication of high performance nanowire transistors (NWTs) using In2O3 nanowires as the active channel and a self-assembled nanodielectric (SAND) as the gate insulator. The SAND-based single In2O3 NWTs are controlled by individually addressed gate electrodes. These devices exhibit n-type transistor characteristics with an on-current of ˜25μA for a single In2O3 nanowire at 2.0Vds, 2.1Vgs, a subthreshold slope of 0.2V/decade, an on-off current ratio of 106, and a field-effect mobility of ˜1450cm2/Vs. These results demonstrate that SAND-based In2O3 NWTs are promising candidates for high performance nanoscale logic technologies.

  2. Resonant tunnelling features in a suspended silicon nanowire single-hole transistor

    Energy Technology Data Exchange (ETDEWEB)

    Llobet, Jordi; Pérez-Murano, Francesc, E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Institut de Microelectrònica de Barcelona (IMB-CNM CSIC), Campus UAB, E-08193 Bellaterra, Catalonia (Spain); Krali, Emiljana; Wang, Chen; Jones, Mervyn E.; Durrani, Zahid A. K., E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Department of Electrical and Electronic Engineering, Imperial College London, South Kensington, London SW7 2AZ (United Kingdom); Arbiol, Jordi [Institució Catalana de Recerca i Estudis Avançats (ICREA) and Institut Català de Nanociència i Nanotecnologia (ICN2), Campus UAB, 08193 Bellaterra, Catalonia (Spain); CELLS-ALBA Synchrotron Light Facility, 08290 Cerdanyola, Catalonia (Spain)

    2015-11-30

    Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.

  3. Selective-Area Growth of InAs Nanowires on Ge and Vertical Transistor Application.

    Science.gov (United States)

    Tomioka, Katsuhiro; Izhizaka, Fumiya; Fukui, Takashi

    2015-11-11

    III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/μm, and the transconductance was 2.2 mS/μm at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multigate planar Ge FETs.

  4. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea

    with nanowire sensors functionalized using different modification schemes. To facilitate functionalization and measurement and as a first step towards integration into a point-of-care device, several microfluidic tools were developed for sample delivery to the sensor surface and as a modular platform......This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

  5. High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics

    OpenAIRE

    Li-Fan Shen; SenPo Yip; Zai-xing Yang; Ming Fang; TakFu Hung; Pun, Edwin Y. B.; Ho, Johnny C.

    2015-01-01

    Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using c...

  6. Analytical Model of Subthreshold Drain Current Characteristics of Ballistic Silicon Nanowire Transistors

    Directory of Open Access Journals (Sweden)

    Wanjie Xu

    2015-01-01

    Full Text Available A physically based subthreshold current model for silicon nanowire transistors working in the ballistic regime is developed. Based on the electric potential distribution obtained from a 2D Poisson equation and by performing some perturbation approximations for subband energy levels, an analytical model for the subthreshold drain current is obtained. The model is further used for predicting the subthreshold slopes and threshold voltages of the transistors. Our results agree well with TCAD simulation with different geometries and under different biasing conditions.

  7. A Robust Highly Aligned DNA Nanowire Array-Enabled Lithography for Graphene Nanoribbon Transistors.

    Science.gov (United States)

    Kang, Seok Hee; Hwang, Wan Sik; Lin, Zhiqun; Kwon, Se Hun; Hong, Suck Won

    2015-12-01

    Because of its excellent charge carrier mobility at the Dirac point, graphene possesses exceptional properties for high-performance devices. Of particular interest is the potential use of graphene nanoribbons or graphene nanomesh for field-effect transistors. Herein, highly aligned DNA nanowire arrays were crafted by flow-assisted self-assembly of a drop of DNA aqueous solution on a flat polymer substrate. Subsequently, they were exploited as "ink" and transfer-printed on chemical vapor deposited (CVD)-grown graphene substrate. The oriented DNA nanowires served as the lithographic resist for selective removal of graphene, forming highly aligned graphene nanoribbons. Intriguingly, these graphene nanoribbons can be readily produced over a large area (i.e., millimeter scale) with a high degree of feature-size controllability and a low level of defects, rendering the fabrication of flexible two terminal devices and field-effect transistors.

  8. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

    OpenAIRE

    2016-01-01

    Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires’ suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-sca...

  9. ON current enhancement of nanowire Schottky barrier tunnel field effect transistors

    Science.gov (United States)

    Takei, Kohei; Hashimoto, Shuichiro; Sun, Jing; Zhang, Xu; Asada, Shuhei; Xu, Taiyu; Matsukawa, Takashi; Masahara, Meishoku; Watanabe, Takanobu

    2016-04-01

    Silicon nanowire Schottky barrier tunnel field effect transistors (NW-SBTFETs) are promising structures for high performance devices. In this study, we fabricated NW-SBTFETs to investigate the effect of nanowire structure on the device characteristics. The NW-SBTFETs were operated with a backgate bias, and the experimental results demonstrate that the ON current density is enhanced by narrowing the width of the nanowire. We confirmed using the Fowler-Nordheim plot that the drain current in the ON state mainly comprises the quantum tunneling component through the Schottky barrier. Comparison with a technology computer aided design (TCAD) simulation revealed that the enhancement is attributed to the electric field concentration at the corners of cross-section of the NW. The study findings suggest an effective approach to securing the ON current by Schottky barrier width modulation.

  10. Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?

    KAUST Repository

    Fahad, Hossain M.

    2012-06-27

    Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.

  11. Quantum Mechanical Analysis of GaN Nanowire Transistor for High Voltage Applications

    Directory of Open Access Journals (Sweden)

    Neel Chatterjee

    2016-12-01

    Full Text Available The paper presents the quantum mechanical analysis of Gallium Nitride nanowire transistor. The effect of high k gate dielectric and different gate metals on the electrical characteristics of the device is studied. Nanowire width has been reduced to have a proper control on the device characteristics at reduced gate length. A high value of drain current is obtained at gate length of 10 nm and nanowire radius equal to 10 nm, is obtained. Also high voltage operation of the device upto 40 volts has been shown. A flatter transconductance curve is obtained which shows the linearity of the device. The results obtained are comparable with the experimental and simulated data reported in literature

  12. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors

    Science.gov (United States)

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Wang, Di; Hahn, Horst; Dasgupta, Subho

    2016-10-01

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm2 V-1 s-1.

  13. Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors

    Science.gov (United States)

    Baldauf, Tim; Heinzig, André; Trommer, Jens; Mikolajick, Thomas; Weber, Walter Michael

    2017-02-01

    Mechanical stress is an established and important tool of the semiconductor industry to improve the performance of modern transistors. It is well understood for the enhancement of carrier mobility but rather unexplored for the control of the tunneling probability for injection dominated research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable Schottky FETs. In this work, the effect of stress on the tunneling probability and overall transistor characteristics is studied by three-dimensional device simulations in the example of reconfigurable silicon nanowire Schottky barrier transistors using two independently gated Schottky junctions. To this end, four different stress sources are investigated. The effects of mechanical stress on the average effective tunneling mass and on the multi-valley band structure applying the deformation potential theory are being considered. The transfer characteristics of strained transistors in n- and p-configuration and corresponding charge carrier tunneling are analyzed with respect to the current ratio between electron and hole conduction. For the implementation of these devices into complementary circuits, the mandatory current ratio of unity can be achieved by appropriate mechanical stress either by nanowire oxidation or the application of a stressed top layer.

  14. Dopant induced single electron tunneling within the sub-bands of single silicon NW tri-gate junctionless n-MOSFET

    Science.gov (United States)

    Uddin, Wasi; Georgiev, Yordan M.; Maity, Sarmistha; Das, Samaresh

    2017-09-01

    We report 1D electron transport of silicon junctionless tri-gate n-type transistor at 4.2 K. The step like curve observed in the current voltage characteristic suggests 1D transport. Besides the current steps for 1D transport, we found multiple spikes within individual steps, which we relate to inter-band single electron tunneling, mediated by the charged dopants available in the channel region. Clear Coulomb diamonds were observed in the stability diagram of the device. It is shown that a uniformly doped silicon nanowire can provide us the window for the single electron tunnelling. Back-gate versus front-gate color plot, where current is in a color scale, shows a crossover of the increased conduction region. This is a clear indication of the dopant-dopant interaction. It has been shown that back-gate biasing can be used to tune the coupling strength between the dopants.

  15. Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors

    Science.gov (United States)

    Yoon, Jun-Sik; Kim, Kihyun; Baek, Chang-Ki

    2017-01-01

    We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or creating a nanowire array. The off-state current is also manageable for power saving through selective epitaxial growth at the top-side nanowire region. CS TFETs with an EOT of 0.8 nm and an aspect ratio of 20 for the core nanowire region provide the largest drain current ranges with point SS values below 60 mV/dec and superior on/off current ratio under all operation voltages of 0.5, 0.7, and 1.0 V. These devices are promising for low-power applications at low fabrication cost and high device density.

  16. Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors

    Science.gov (United States)

    Yoon, Jun-Sik; Kim, Kihyun; Baek, Chang-Ki

    2017-01-01

    We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or creating a nanowire array. The off-state current is also manageable for power saving through selective epitaxial growth at the top-side nanowire region. CS TFETs with an EOT of 0.8 nm and an aspect ratio of 20 for the core nanowire region provide the largest drain current ranges with point SS values below 60 mV/dec and superior on/off current ratio under all operation voltages of 0.5, 0.7, and 1.0 V. These devices are promising for low-power applications at low fabrication cost and high device density. PMID:28112273

  17. Effects of piezoelectric potential on the transport characteristics of metal-ZnO nanowire-metal field effect transistor

    KAUST Repository

    Gao, Zhiyuan

    2009-01-01

    We have investigated the effects of piezoelectric potential in a ZnO nanowire on the transport characteristics of the nanowire based field effect transistor through numerical calculations and experimental observations. Under different straining conditions including stretching, compressing, twisting, and their combination, a piezoelectric potential is created throughout the nanowire to modulatealternate the transport property of the metal-ZnO nanowire contacts, resulting in a switch between symmetric and asymmetric contacts at the two ends, or even turning an Ohmic contact type into a diode. The commonly observed natural rectifying behavior of the as-fabricated ZnO nanowire can be attributed to the strain that was unpurposely created in the nanowire during device fabrication and material handling. This work provides further evidence on piezopotential governed electronic transport and devices, e.g., piezotronics.

  18. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

    Science.gov (United States)

    Guerfi, Youssouf; Larrieu, Guilhem

    2016-04-01

    Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

  19. Quantum transport of a nanowire field-effect transistor with complex phonon self–energy

    Energy Technology Data Exchange (ETDEWEB)

    Valin, R., E-mail: r.valinferreiro@swansea.ac.uk; Aldegunde, M., E-mail: m.a.aldegunderodriguez@swansea.ac.uk; Martinez, A., E-mail: a.e.Martinez@swansea.ac.uk [Electronic Systems Design Centre, College of Engineering, Swansea University, SA2 8PP (United Kingdom); Barker, J. R., E-mail: john.barker@glasgow.ac.uk [School of Engineering, University of Glasgow, G12 8LT (United Kingdom)

    2014-08-28

    In this work, the impact of the real part of the phonon self-energy on the transfer characteristics of a silicon nanowire transistor is investigated. The physical effects of the real part of the self-energy are to create a broadening and a shift on the density of states. This increases the drain current in the sub–threshold region and decreases it in the above–the–threshold region. In the first region, the current is increased as a result of an increase of charge in the middle of the channel. In the second one, the electrostatic self–consistency or the enforcement of charge neutrality in the channel reduces the current because a substantial amount of electrons are under the first subband and have imaginary wave vectors. The change in the phonon–limited mobility due to the real part of self–energy is evaluated for a nanowire transistor and a nanowire in which there is not source to drain barrier. We also assess the validity of Mathiessen's rule using the self–consistent NEGF simulations and the Kubo–Greenwood formalism.

  20. Gated Hall Effect Measurements on Selectively grown InGaAs Nanowires.

    Science.gov (United States)

    Lindelöw, Fredrik Gustav; Zota, Cezar; Lind, Erik

    2017-02-23

    InGaAs nanowires is one of the promising material systems of replacing silicon in future CMOS transistors, due to its high electron mobility, in combination with the excellent electrostatic control from the tri-gate geometry. In this article, we report on gated Hall measurements on single and multiple In0.85Ga0.15As nanowires, selectively grown in a Hall bridge geometry with nanowire widths down to 50 nm and thicknesses of 10 nm. The gated nanowires can be used as junctionless transistors, which allows for a simplified device processing as no regrowth of contact layer or ion implantation is needed, which is especially beneficial as transistor dimensions are scaled down. The analysis shows that the InGaAs layer has a carrier concentration above 10^19 cm^-3, with a Hall carrier mobility of around 1000 cm^2V^-1s^-1. The gated Hall measurements reveal an increased carrier concentration as a function of applied gate voltage, with an increasing mobility for narrow nanowires but no significant effect on larger nanowires.

  1. Field-effect memory transistors based on arrays of nanowires of a ferroelectric polymer

    Science.gov (United States)

    Cai, Ronggang; Kassa, Hailu G.; Marrani, Alessio; van Breemen, Albert J. J. M.; Gelinck, Gerwin H.; Nysten, Bernard; Hu, Zhijun; Jonas, Alain M.

    2015-09-01

    Ferroelectric poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE), is increasingly used in organic non-volatile memory devices, e.g., in ferroelectric field effect transistors (FeFETs). Here, we report on FeFETs integrating nanoimprinted arrays of P(VDF-TrFE) nanowires. Two previously-unreported architectures are tested, the first one consisting of stacked P(VDF-TrFE) nanowires placed over a continuous semiconducting polymer film; the second one consisting of a nanostriped blend layer wherein the semiconducting and ferroelectric components alternate regularly. The devices exhibit significant reversible memory effects, with operating voltages reduced compared to their continuous film equivalent, and with different possible geometries of the channels of free charge carriers accumulating in the semiconductor.

  2. Probing the local environment of a superconductor-proximitized nanowire using single electron transistors

    Science.gov (United States)

    Pei, Fei; Cassidy, Maja; Plissard, Sebastien; Car, Diana; Bakkers, Erik; Kouwenhoven, Leo

    2014-03-01

    Majorana bound states are predicted to arise in semiconducting nanowires with strong spin-orbit coupling that are proximity-coupled to a s-wave superconductor and exposed to a magnetic field. Recent tunneling spectroscopy experiments have shown signatures of Majorana bound states through the existence of a peak in conductance that remains fixed to zero bias over a wide range in magnetic fields. Observation of the delocalized nature of these states remains an outstanding challenge. Here we present measurements of a InSb nanowire proximitized by a central superconducting contact. Normal metal leads allow tunneling spectroscopy from each end of the wire, while nearby single electron transistors provide simultaneous information on the local environment both within the proximitized wire and at each end.

  3. Sensing Responses Based on Transfer Characteristics of InAs Nanowire Field-Effect Transistors.

    Science.gov (United States)

    Tseng, Alex C; Lynall, David; Savelyev, Igor; Blumin, Marina; Wang, Shiliang; Ruda, Harry E

    2017-07-16

    Nanowire-based field-effect transistors (FETs) have demonstrated considerable promise for a new generation of chemical and biological sensors. Indium arsenide (InAs), by virtue of its high electron mobility and intrinsic surface accumulation layer of electrons, holds properties beneficial for creating high performance sensors that can be used in applications such as point-of-care testing for patients diagnosed with chronic diseases. Here, we propose devices based on a parallel configuration of InAs nanowires and investigate sensor responses from measurements of conductance over time and FET characteristics. The devices were tested in controlled concentrations of vapour containing acetic acid, 2-butanone and methanol. After adsorption of analyte molecules, trends in the transient current and transfer curves are correlated with the nature of the surface interaction. Specifically, we observed proportionality between acetic acid concentration and relative conductance change, off current and surface charge density extracted from subthreshold behaviour. We suggest the origin of the sensing response to acetic acid as a two-part, reversible acid-base and redox reaction between acetic acid, InAs and its native oxide that forms slow, donor-like states at the nanowire surface. We further describe a simple model that is able to distinguish the occurrence of physical versus chemical adsorption by comparing the values of the extracted surface charge density. These studies demonstrate that InAs nanowires can produce a multitude of sensor responses for the purpose of developing next generation, multi-dimensional sensor applications.

  4. Analysis of nanowire transistor based nitrogen dioxide gas sensor – A simulation study

    Directory of Open Access Journals (Sweden)

    Gaurav Saxena

    2015-06-01

    Full Text Available Sensors sensitivity, selectivity and stability has always been a prime design concern for gas sensors designers. Modeling and simulation of gas sensors aids the designers in improving their performance. In this paper, different routes for the modeling and simulation of a semiconducting gas sensor is presented. Subsequently, by employing one of the route, the response of Zinc Oxide nanowire transistor towards nitrogen dioxide ambient is simulated. In addition to the sensing mechanism, simulation study of gas species desorption by applying a recovery voltage is also presented.

  5. Influence of anharmonic phonon decay on self-heating in Si nanowire transistors

    Energy Technology Data Exchange (ETDEWEB)

    Rhyner, Reto, E-mail: rhyner@iis.ee.ethz.ch; Luisier, Mathieu, E-mail: mluisier@iis.ee.ethz.ch [Integrated Systems Laboratory, ETH Zürich, Gloriastr. 35, 8092 Zürich (Switzerland)

    2014-08-11

    Anharmonic phonon-phonon scattering is incorporated into an electro-thermal quantum transport approach based on the nonequilibrium Green's function formalism. Electron-phonon and phonon-phonon interactions are taken into account through scattering self-energies solved in the self-consistent Born approximation. While studying self-heating effects in ultra-scaled Si nanowire transistors, it is found that the phonon decay process softens the artificial accumulation of high energy phonons caused by electron relaxations close to the drain region. This leads to an increase of the device current in the ON-state and a reduction of the effective lattice temperature.

  6. Carrier injection engineering in nanowire transistors via dopant and shape monitoring of the access regions

    Energy Technology Data Exchange (ETDEWEB)

    Berrada, Salim, E-mail: s.berrada@insa.ueuromed.org; Bescond, Marc, E-mail: marc.bescond@im2np.fr; Cavassilas, Nicolas; Raymond, Laurent; Lannoo, Michel [IM2NP UMR CNRS 7334, Aix-Marseille Université, Technopôle de Château Gombert, 60 Rue Frédéric Joliot Curie, Bâtiment Néel,13453 Marseille (France)

    2015-10-12

    This work theoretically studies the influence of both the geometry and the discrete nature of dopants of the access regions in ultra-scaled nanowire transistors. By means of self-consistent quantum transport simulations, we show that discrete dopants induce quasi-localized states which govern carrier injection into the channel. Carrier injection can be enhanced by taking advantage of the dielectric confinement occurring in these access regions. We demonstrate that the optimization of access resistance can be obtained by a careful control of shape and dopant position. These results pave the way for contact resistance engineering in forthcoming device generations.

  7. Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

    Science.gov (United States)

    Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

    2016-01-01

    The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

  8. Unlocking the Origin of Superior Performance of a Si-Ge Core-Shell Nanowire Quantum Dot Field Effect Transistor.

    Science.gov (United States)

    Dhungana, Kamal B; Jaishi, Meghnath; Pati, Ranjit

    2016-07-13

    The sustained advancement in semiconducting core-shell nanowire technology has unlocked a tantalizing route for making next generation field effect transistor (FET). Understanding how to control carrier mobility of these nanowire channels by applying a gate field is the key to developing a high performance FET. Herein, we have identified the switching mechanism responsible for the superior performance of a Si-Ge core-shell nanowire quantum dot FET over its homogeneous Si counterpart. A quantum transport approach is used to investigate the gate-field modulated switching behavior in electronic current for ultranarrow Si and Si-Ge core-shell nanowire quantum dot FETs. Our calculations reveal that for the ON state, the gate-field induced transverse localization of the wave function restricts the carrier transport to the outer (shell) layer with the pz orbitals providing the pathway for tunneling of electrons in the channels. The higher ON state current in the Si-Ge core-shell nanowire FET is attributed to the pz orbitals that are distributed over the entire channel; in the case of Si nanowire, the participating pz orbital is restricted to a few Si atoms in the channel resulting in a smaller tunneling current. Within the gate bias range considered here, the transconductance is found to be substantially higher in the case of a Si-Ge core-shell nanowire FET than in a Si nanowire FET, which suggests a much higher mobility in the Si-Ge nanowire device.

  9. A radio-frequency single-electron transistor based on an InAs/InP heterostructure nanowire

    DEFF Research Database (Denmark)

    Nilsson, Henrik A.; Duty, Tim; Abay, Simon

    2008-01-01

    We demonstrate radio frequency single-electron transistors fabricated from epitaxially grown InAs/InP heterostructure nanowires. Two sets of double-barrier wires with different barrier thicknesses were grown. The wires were suspended 15 nm above a metal gate electrode. Electrical measurements on ...

  10. Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors.

    Science.gov (United States)

    Sultan, Suhana M; Ditshego, Nonofo J; Gunn, Robert; Ashburn, Peter; Chong, Harold Mh

    2014-01-01

    This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm(2)/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm(2)/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing.

  11. Fabrication of SiC nanowire thin-film transistors using dielectrophoresis

    Institute of Scientific and Technical Information of China (English)

    Dai Zhenqing; Zhang Liying; Chen Changxin; Qian Bingjian; Xu Dong; Chen Haiyan; Wei Liangming; Zhang Yafei

    2012-01-01

    The selection of solvents for SiC nanowires (NWs) in a dielectrophoretic process is discussed theoretically and experimentally.From the viewpoints of dielectrophoresis force and torque,volatility,as well as toxicity,isopropanol (IPA) is considered as a proper candidate.By using the dielectrophoretic process,SiC NWs are aligned and NW thin films are prepared.The densities of the aligned SiC NWs are 2 μm-1,4 μm-1,6 μm-1,which corresponds to SiC NW concentrations of 0.1 μg/μL,0.3μg/μL and 0.5 μg/μL,respectively.Thin-film transistors are fabricated based on the aligned SiC NWs of 6 μm-1.The mobility of a typical device is estimated to be 13.4 cm2/(V.s).

  12. ZnO nanowire network transistors based on a self-assembly method

    Institute of Scientific and Technical Information of China (English)

    Dai Zhenqing; Chen Changxin; Zhang Yaozhong; Wei Liangming; Zhang Jing; Xu Dong; Zhang Yafei

    2012-01-01

    Dense,uniform ZnO nanowire (NW) networks are prepared by using a simple and sufficient selfassembly method.In this method,ZnO NWs are modified with aminopropyltriethoxysilane (APTES) to form positively charged amine-terminated surfaces.The modified ZnO NWs are adsorbed on negatively charged SiO2/Si substrates to form ZnO NW networks by the electrostatic interaction in an aqueous solution.Field-effect transistors (FETs) are fabricated and studied based on the ZnO NW networks.For a typical device with an NW density of 2.8 μm-2,it exhibits a current on/off ratio of 2.4 × 105,a transconductance of 336 nS,and a field-effect mobility of 27.4 cm2/(V·s).

  13. Investigation of drift effect on silicon nanowire field effect transistor based pH sensor

    Science.gov (United States)

    Kim, Sihyun; Kwon, Dae Woong; Lee, Ryoongbin; Kim, Dae Hwan; Park, Byung-Gook

    2016-06-01

    It is widely accepted that the operation mechanism of pH-sensitive ion sensitive field effect transistor (ISFET) can be divided into three categories; reaction of surface sites, chemical modification of insulator surface, and ionic diffusion into the bulk of insulator. The first mechanism is considered as the main operation mechanism of pH sensors due to fast response, while the others with relatively slow responses disturb accurate pH detection. In this study, the slow responses (often called drift effects) are investigated in silicon nanowire (SiNW) pH-sensitive ISFETs. Based on the dependence on the channel type of SiNW, liquid gate bias, and pH, it is clearly revealed that the drift of n-type SiNW results from H+ diffusion into the insulator whereas that of p-type SiNW is caused by chemical modification (hydration) of the insulator.

  14. Analytic modeling of a depletion-mode cylindrical surrounding-gate nanowire field-effect transistor.

    Science.gov (United States)

    Yu, Yun Seop; Park, Hyung-Kun

    2012-07-01

    A compact model for depletion-mode p-type cylindrical surrounding-gate nanowire field-effect transistors (SGNWFETs) is proposed. The SGNWFET model consists of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic SGNWFET. Based on the electrostatic method, the intrinsic SGNWFET model was derived from current conduction mechanisms attributed to bulk charges through the center neutral region, in addition to accumulation charges through the surface accumulation region. The authors' previously developed Schottky diode model was used for the M-S contacts. The new model was applied to an advanced design system (ADS), whereby the intrinsic part of the SGNWFET and the Schottky diode were developed using the Verilog-A language. The results of the simulation of the newly developed SGNWFET model reproduced the experiment results considerably well.

  15. A highly pH-sensitive nanowire field-effect transistor based on silicon on insulator

    Directory of Open Access Journals (Sweden)

    Denis E. Presnov

    2013-05-01

    Full Text Available Background: An experimental and theoretical study of a silicon-nanowire field-effect transistor made of silicon on insulator by CMOS-compatible methods is presented.Results: A maximum Nernstian sensitivity to pH change of 59 mV/pH was obtained experimentally. The maximum charge sensitivity of the sensor was estimated to be on the order of a thousandth of the electron charge in subthreshold mode.Conclusion: The sensitivity obtained for our sensor built in the CMOS-compatible top-down approach does not yield to the one of sensors built in bottom-up approaches. This provides a good background for the development of CMOS-compatible probes with primary signal processing on-chip.

  16. Electrical properties of flexible multi-channel Si nanowire field-effect transistors depending on the number of Si nanowires.

    Science.gov (United States)

    Kim, Do Hoon; Lee, Su Jeong; Lee, Sang Hoon; Myoung, Jae-Min

    2016-05-25

    Flexible multi-channel Si nanowire (NW) field-effect transistors (FETs) were investigated to determine the effect of the number of Si NWs. The Langmuir-Blodgett method was applied for the formation of well-aligned Si NW monolayers, and an ion-gel with a high dielectric constant was used as a gate insulator in a top-gate TFT structure to secure flexibility. Like typical nanoelectronic devices, the drain current changed with the number of Si NWs. However, unlike previous reports, the mobility of the multi-channel Si NW FETs increased from 42.8 to 124.6 cm(2) V(-1) s(-1) as the number of Si NWs was increased from 1 to 58. To verify the feasibility of our approach, the electrical performance of the TFTs fabricated on a flexible polyimide (PI) substrate was analyzed in respect of the bending strain (0.08-1.51%) and bending cycle (up to 12 000 cycles). As the number of Si NWs was increased, the trade-off between electrical and mechanical properties during bending tests was confirmed, and the appropriate number of Si NWs was optimized for a flexible FET with excellent performance.

  17. A sub kBT/q semimetal nanowire field effect transistor

    Science.gov (United States)

    Ansari, L.; Fagas, G.; Gity, F.; Greer, J. C.

    2016-08-01

    The key challenge for nanoelectronics technologies is to identify the designs that work on molecular length scales, provide reduced power consumption relative to classical field effect transistors (FETs), and that can be readily integrated at low cost. To this end, a FET is introduced that relies on the quantum effects arising for semimetals patterned with critical dimensions below 5 nm, that intrinsically has lower power requirements due to its better than a "Boltzmann tyranny" limited subthreshold swing (SS) relative to classical field effect devices, eliminates the need to form heterojunctions, and mitigates against the requirement for abrupt doping profiles in the formation of nanowire tunnel FETs. This is achieved through using a nanowire comprised of a single semimetal material while providing the equivalent of a heterojunction structure based on shape engineering to avail of the quantum confinement induced semimetal-to-semiconductor transition. Ab initio calculations combined with a non-equilibrium Green's function formalism for charge transport reveals tunneling behavior in the OFF state and a resonant conduction mechanism for the ON state. A common limitation to tunnel FET (TFET) designs is related to a low current in the ON state. A discussion relating to the semimetal FET design to overcome this limitation while providing less than 60 meV/dec SS at room temperature is provided.

  18. High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

    KAUST Repository

    Huang, Ruo-Gu

    2011-06-24

    We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV) and low subthreshold swing (~80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. © 2011 Tsinghua University Press and Springer-Verlag Berlin Heidelberg.

  19. Technology demonstration of a novel poly-Si nanowire thin film transistor

    Science.gov (United States)

    Liu, Libin; Liang, Renrong; Shan, Bolin; Xu, Jun; Wang, Jing

    2016-11-01

    A simple process flow method for the fabrication of poly-Si nanowire thin film transistors (NW-TFTs) without advanced lithographic tools is introduced in this paper. The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique. The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs (used as a control). The as-demonstrated NW-TFT exhibits a small subthreshold swing (191 mV/dec), a high ON/OFF ratio (8.5 × 107), a low threshold voltage (1.12 V), a decreased OFF-state current, and a low drain-induced-barrier lowering value (70.11 mV/V). The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT. The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel. Project supported by the National Key Research and Development Program of China (Grant Nos. 2016YFA0302300 and 2016YFA0200404), the National Natural Science Foundation of China (Grant No. 61306105), the National Science and Technology Major Project of China (Grant No. 2011ZX02708-002), the Tsinghua University Initiative Scientific Research Program, China and the Tsinghua National Laboratory for Information Science and Technology (TNList) Cross-discipline Foundation, China.

  20. Mobility enhancement of SnO2 nanowire transistors gated with a nanogranular SiO2 solid electrolyte.

    Science.gov (United States)

    Sun, Jia; Huang, Wenlong; Qian, Chuan; Yang, Junliang; Gao, Yongli

    2014-01-21

    Field-effect transistors (FETs) based on semiconducting nanowires are the most fundamental electronic elements for exploring charge transport as well as possible applications in functional nanoelectronics. Here, we report the effect of different gate dielectrics on the electrical performance of SnO2 nanowire FETs. By using solid-electrolytes with large electric-double-layer (EDL) capacitance as gate dielectrics, both low-voltage operation and high gating efficiency can be obtained. Electrical transport measurements indicate that the nanowire FETs gated by solid-electrolytes show improved electrical performances in terms of on-current, sub-threshold swing, and mobility, in comparison to those gated by traditional thermally grown dielectrics. The observed performance improvement is possibly due to the reduction of the contact-resistance and the Schottky barrier at the semiconductor/metal junctions.

  1. Nanowire-organic thin film transistor integration and scale up towards developing sensor array for biomedical sensing applications

    Science.gov (United States)

    Kumar, Prashanth S.; Hankins, Phillip T.; Rai, Pratyush; Varadan, Vijay K.

    2010-04-01

    Exploratory research works have demonstrated the capability of conducting nanowire arrays in enhancing the sensitivity and selectivity of bio-electrodes in sensing applications. With the help of different surface manipulation techniques, a wide range of biomolecules have been successfully immobilized on these nanowires. Flexible organic electronics, thin film transistor (TFT) fabricated on flexible substrate, was a breakthrough that enabled development of logic circuits on flexible substrate. In many health monitoring scenarios, a series of biomarkers, physical properties and vital signals need to be observed. Since the nano-bio-electrodes are capable of measuring all or most of them, it has been aptly suggested that a series of electrode (array) on single substrate shall be an excellent point of care tool. This requires an efficient control system for signal acquisition and telemetry. An array of flexible TFTs has been designed that acts as active matrix for controlled switching of or scanning by the sensor array. This array is a scale up of the flexible organic TFT that has been fabricated and rigorously tested in previous studies. The integration of nanowire electrodes to the organic electronics was approached by growing nanowires on the same substrate as TFTs and fl ip chip packaging, where the nanowires and TFTs are made on separate substrates. As a proof of concept, its application has been explored in various multi-focal biomedical sensing applications, such as neural probes for monitoring neurite growth, dopamine, and neuron activity; myocardial ischemia for spatial monitoring of myocardium.

  2. Observation of diameter dependent carrier distribution in nanowire-based transistors

    Energy Technology Data Exchange (ETDEWEB)

    Schulze, A; Hantschel, T; Eyben, P; Verhulst, A S; Rooyackers, R; Vandooren, A; Mody, J; Nazir, A; Leonelli, D; Vandervorst, W, E-mail: Andreas.Schulze@imec.be [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)

    2011-05-06

    The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.

  3. Proton radiation hardness of single-nanowire transistors using robust organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Lee, Kangho; Janes, David B.; Dwivedi, Ramesh C.; Baffour-Awuah, Habibah; Wilkins, R.; Yoon, Myung-Han; Facchetti, Antonio; Mark, Tobin J.

    2006-08-01

    In this contribution, the radiation tolerance of single ZnO nanowire field-effect transistors (NW-FETs) fabricated with a self-assembled superlattice (SAS) gate insulator is investigated and compared with that of ZnO NW-FETs fabricated with a 60nm SiO2 gate insulator. A total-radiation dose study was performed using 10MeV protons at doses of 5.71 and 285krad(Si ). The threshold voltage (Vth) of the SAS-based ZnO NW-FETs is not shifted significantly following irradiation at these doses. In contrast, Vth parameters of the SiO2-based ZnO NW-FETs display average shifts of ˜-4.0 and ˜-10.9V for 5.71 and 285krad(Si ) H+ irradiation, respectively. In addition, little change is observed in the subthreshold characteristics (off current, subthreshold slope) of the SAS-based ZnO NW-FETs following H+ irradiation. These results strongly argue that the bulk oxide trap density and interface trap density formed within the SAS and/or at the SAS-ZnO NW interface during H+ irradiation are significantly lower than those for the corresponding SiO2 gate dielectrics. The radiation-robust SAS-based ZnO NW-FETs are thus promising candidates for future space-based applications in electronics and flexible displays.

  4. Tuning the electrical properties of Si nanowire field-effect transistors by molecular engineering.

    Science.gov (United States)

    Bashouti, Muhammad Y; Tung, Raymond T; Haick, Hossam

    2009-12-01

    Exposed facets of n-type silicon nanowires (Si NWs) fabricated by a top-down approach are successfully terminated with different organic functionalities, including 1,3-dioxan-2-ethyl, butyl, allyl, and propyl-alcohol, using a two-step chlorination/alkylation method. X-ray photoemission spectroscopy and spectroscopic ellipsometry establish the bonding and the coverage of these molecular layers. Field-effect transistors fabricated from these Si NWs displayed characteristics that depended critically on the type of molecular termination. Without molecules the source-drain conduction is unable to be turned off by negative gate voltages as large as -20 V. Upon adsorption of organic molecules there is an observed increase in the "on" current at large positive gate voltages and also a reduction, by several orders of magnitude, of the "off" current at large negative gate voltages. The zero-gate voltage transconductance of molecule-terminated Si NW correlates with the type of organic molecule. Adsorption of butyl and 1,3-dioxan-2-ethyl molecules improves the channel conductance over that of the original SiO(2)-Si NW, while adsorption of molecules with propyl-alcohol leads to a reduction. It is shown that a simple assumption based on the possible creation of surface states alongside the attachment of molecules may lead to a qualitative explanation of these electrical characteristics. The possibility and potential implications of modifying semiconductor devices by tuning the distribution of surface states via the functionality of attached molecules are discussed.

  5. Hybrid porphyrin-silicon nanowire field-effect transistor by opto-electrical excitation.

    Science.gov (United States)

    Seol, Myeong-Lok; Choi, Sung-Jin; Choi, Ji-Min; Ahn, Jae-Hyuk; Choi, Yang-Kyu

    2012-09-25

    A porphyrin-silicon nanowire (Si-NW) hybrid field-effect transistor is introduced. The hybrid device has separate electrical and optical gates surrounding the Si-NW channel. Porphyrin, a component of chlorophyll, is employed as an optical gate to modulate the potential of the Si-NW channel. Due to the independently formed hybrid gates, both optical and electrical excitation can effectively modulate the device. The exposed porphyrin optical gate responds to the optical excitation, and independently formed electrical gates respond to the electrical excitation. Charge transfer characteristics between a semiconductor channel and the porphyrin optical gate are deeply investigated. Optical, electrical, and opto-electrical excitation methods are employed to analyze the charging and discharging behaviors. Of these methods, opto-electrical excitation enables the strongest charge transfer because the inversion electron formation by an electrical pulse and the photoinduced charge transfer by an optical stimulus are affected simultaneously. Discharging processes, such as rapid discharging, exponential detrapping, and the formation of metastable states are also analyzed.

  6. Complementary metal oxide semiconductor-compatible silicon nanowire biofield-effect transistors as affinity biosensors.

    Science.gov (United States)

    Duan, Xuexin; Rajan, Nitin K; Izadi, Mohammad Hadi; Reed, Mark A

    2013-11-01

    Affinity biosensors use biorecognition elements and transducers to convert a biochemical event into a recordable signal. They provides the molecule binding information, which includes the dynamics of biomolecular association and dissociation, and the equilibrium association constant. Complementary metal oxide semiconductor-compatible silicon (Si) nanowires configured as a field-effect transistor (NW FET) have shown significant advantages for real-time, label-free and highly sensitive detection of a wide range of biomolecules. Most research has focused on reducing the detection limit of Si-NW FETs but has provided less information about the real binding parameters of the biomolecular interactions. Recently, Si-NW FETs have been demonstrated as affinity biosensors to quantify biomolecular binding affinities and kinetics. They open new applications for NW FETs in the nanomedicine field and will bring such sensor technology a step closer to commercial point-of-care applications. This article summarizes the recent advances in bioaffinity measurement using Si-NW FETs, with an emphasis on the different approaches used to address the issues of sensor calibration, regeneration, binding kinetic measurements, limit of detection, sensor surface modification, biomolecule charge screening, reference electrode integration and nonspecific molecular binding.

  7. Schottky barrier and contact resistance of InSb nanowire field-effect transistors

    Science.gov (United States)

    Fan, Dingxun; Kang, N.; Gorji Ghalamestani, Sepideh; Dick, Kimberly A.; Xu, H. Q.

    2016-07-01

    Understanding of the electrical contact properties of semiconductor nanowire (NW) field-effect transistors (FETs) plays a crucial role in the use of semiconducting NWs as building blocks for future nanoelectronic devices and in the study of fundamental physics problems. Here, we report on a study of the contact properties of Ti/Au, a widely used contact metal combination, when contacting individual InSb NWs via both two-probe and four-probe transport measurements. We show that a Schottky barrier of height {{{Φ }}}{{SB}}˜ 20 {{meV}} is present at the metal-InSb NW interfaces and its effective height is gate-tunable. The contact resistance ({R}{{c}}) in the InSb NWFETs is also analyzed by magnetotransport measurements at low temperatures. It is found that {R}{{c}} in the on-state exhibits a pronounced magnetic field-dependent feature, namely it is increased strongly with increasing magnetic field after an onset field {B}{{c}}. A qualitative picture that takes into account magnetic depopulation of subbands in the NWs is provided to explain the observation. Our results provide solid experimental evidence for the presence of a Schottky barrier at Ti/Au-InSb NW interfaces and can be used as a basis for design and fabrication of novel InSb NW-based nanoelectronic devices and quantum devices.

  8. The RFET—a reconfigurable nanowire transistor and its application to novel electronic circuits and systems

    Science.gov (United States)

    Mikolajick, T.; Heinzig, A.; Trommer, J.; Baldauf, T.; Weber, W. M.

    2017-04-01

    With CMOS scaling reaching physical limits in the next decade, new approaches are required to enhance the functionality of electronic systems. Reconfigurability on the device level promises to realize more complex systems with a lower device count. In the last five years a number of interesting concepts have been proposed to realize such a device level reconfiguration. Among these the reconfigurable field effect transistor (RFET), a device that can be configured between an n-channel and p-channel behavior by applying an electrical signal, can be considered as an end-of-roadmap extension of current technology with only small modifications and even simplifications to the process flow. This article gives a review on the RFET basics and current status. In the first sections state-of-the-art of reconfigurable devices will be summarized and the RFET will be introduced together with related devices based on silicon nanowire technology. The device optimization with respect to device symmetry and performance will be discussed next. The potential of the RFET device technology will then be shown by discussing selected circuit implementations making use of the unique advantages of this device concept. The basic device concept was also extended towards applications in flexible devices and sensors, also extending the capabilities towards so-called More-than-Moore applications where new functionalities are implemented in CMOS-based processes. Finally, the prospects of RFET device technology will be discussed.

  9. Enhanced sensing of nonpolar volatile organic compounds by silicon nanowire field effect transistors.

    Science.gov (United States)

    Paska, Yair; Stelzner, Thomas; Christiansen, Silke; Haick, Hossam

    2011-07-26

    Silicon nanowire field effect transistors (Si NW FETs) are emerging as powerful sensors for direct detection of biological and chemical species. However, the low sensitivity of the Si NW FET sensors toward nonpolar volatile organic compounds (VOCs) is problematic for many applications. In this study, we show that modifying Si NW FETs with a silane monolayer having a low fraction of Si-O-Si bonds between the adjacent molecules greatly enhances the sensitivity toward nonpolar VOCs. This can be explained in terms of an indirect sensor-VOC interaction, whereby the nonpolar VOC molecules induce conformational changes in the organic monolayer, affecting (i) the dielectric constant and/or effective dipole moment of the organic monolayer and/or (ii) the density of charged surface states at the SiO(2)/monolayer interface. In contrast, polar VOCs are sensed directly via VOC-induced changes in the Si NW charge carriers, most probably due to electrostatic interaction between the Si NW and polar VOCs. A semiempirical model for the VOC-induced conductivity changes in the Si NW FETs is presented and discussed.

  10. GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors

    Science.gov (United States)

    Yu, Feng; Yao, Shengbo; Römer, Friedhard; Witzigmann, Bernd; Schimpke, Tilman; Strassburg, Martin; Bakin, Andrey; Schumacher, Hans Werner; Peiner, Erwin; Suryo Wasisto, Hutomo; Waag, Andreas

    2017-03-01

    Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

  11. Transistors

    CERN Document Server

    Kendall, E J M

    2013-01-01

    Transistors covers the main thread of transistor development. This book is organized into 2 parts encompassing 19, and starts with an overview of the semi-conductor physics pertinent to the understanding of transistors, as well as features and applications of the point contact devices and junction devices. The subsequent part deals with the modulation of conductance of thin films of conductors by surface charges, the metal-semi conductor, and the semi-conductor triode. These topics are followed by discussions on the nature of the forward current, physical principles in transistor, the hole inj

  12. Effects of bias stress on ZnO nanowire field-effect transistors fabricated with organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Janes, David B.; Lu, Gang; Facchetti, Antonio; Marks, Tobin J.

    2006-11-01

    The effects of bias stress (gate stress or drain stress) on nanowire field-effect transistor (NW-FET) stability were investigated as a function of stress bias and stress time. The n-channel NW-FETs used a nanoscopic self-assembled organic gate insulator, and each device contained a single ZnO nanowire. Before stress, the off current is limited by a leakage current in the 1nA range, which increases as the gate to source bias becomes increasingly negative. The devices also exhibited significant changes in threshold voltage (Vth) and off current over 500 repeated measurement sweeps. The leakage current was significantly reduced after gate stress, but not after drain stress. Vth variations observed upon successive bias sweeps for devices following gate stress or drain stress were smaller than the Vth variation of unstressed devices. These observations suggest that gate stress and drain stress modify the ZnO nanowire-gate insulator interface, which can reduce electron trapping at the surface and therefore reduce the off current levels and variations in Vth. These results confirm that gate and drain stresses are effective means to stabilize device operation and provide high performance transistors with impressive reliabilities.

  13. Catching the electron in action in real space inside a Ge-Si core-shell nanowire transistor.

    Science.gov (United States)

    Jaishi, Meghnath; Pati, Ranjit

    2017-09-21

    Catching the electron in action in real space inside a semiconductor Ge-Si core-shell nanowire field effect transistor (FET), which has been demonstrated (J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature, 2006, 441, 489) to outperform the state-of-the-art metal oxide semiconductor FET, is central to gaining unfathomable access into the origin of its functionality. Here, using a quantum transport approach that does not make any assumptions on electronic structure, charge, and potential profile of the device, we unravel the most probable tunneling pathway for electrons in a Ge-Si core-shell nanowire FET with orbital level spatial resolution, which demonstrates gate bias induced decoupling of electron transport between the core and the shell region. Our calculation yields excellent transistor characteristics as noticed in the experiment. Upon increasing the gate bias beyond a threshold value, we observe a rapid drop in drain current resulting in a gate bias driven negative differential resistance behavior and switching in the sign of trans-conductance. We attribute this anomalous behavior in drain current to the gate bias induced modification of the carrier transport pathway from the Ge core to the Si shell region of the nanowire channel. A new experiment involving a four probe junction is proposed to confirm our prediction on gate bias induced decoupling.

  14. Photoelectric probing of the interfacial trap density-of-states in ZnO nanowire field-effect transistors.

    Science.gov (United States)

    Raza, Syed Raza Ali; Lee, Young Tack; Chang, Youn-Gyoung; Jeon, Pyo Jin; Kim, Jae Hoon; Ha, Ryong; Choi, Heon-Jin; Im, Seongil

    2013-02-28

    We have fabricated transparent top-gate ZnO nanowire (NW) field effect transistors (FETs) on glass and measured their trap density-of-states (DOS) at the dielectric/ZnO NW interface with monochromatic photon beams during their operation. Our photon-probe method showed clear signatures of charge trap DOS at the interface, located near 2.3, 2.7, and 2.9 eV below the conduction band edge. The DOS information was utilized for the photo-detecting application of our transparent NW-FETs, which demonstrated fast and sensitive photo-detection of visible lights.

  15. A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Wei-Chen; Lin, Horng-Chih; Lin, Zer-Ming; Huang, Tiao-Yuan [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan (China); Hsu, Chin-Tsai, E-mail: hclin@faculty.nctu.edu.tw [National Nano Device Laboratories, Hsinchu, 300, Taiwan (China)

    2010-10-29

    Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 {mu}m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.

  16. Flexible, low-voltage, and low-hysteresis PbSe nanowire field-effect transistors.

    Science.gov (United States)

    Kim, David K; Lai, Yuming; Vemulkar, Tarun R; Kagan, Cherie R

    2011-12-27

    We report low-hysteresis, ambipolar bottom gold contact, colloidal PbSe nanowire (NW) field-effect transistors (FETs) by chemically modifying the silicon dioxide (SiO(2)) gate dielectric surface to overcome carrier trapping at the NW-gate dielectric interface. While water bound to silanol groups at the SiO(2) surface are believed to give rise to hysteresis in FETs of a wide range of nanoscale materials, we show that dehydration and silanization are insufficient in reducing PbSe NW FET hysteresis. Encapsulating PbSe NW FETs in cured poly(methyl) methacrylate (PMMA), dehydrates and uniquely passivates the SiO(2) surface, to form low-hysteresis FETs. Annealing predominantly p-type ambipolar PbSe NW FETs switches the FET behavior to predominantly n-type ambipolar, both with and without PMMA passivation. Heating the PbSe NW devices desorbs surface bound oxygen, even present in the atmosphere of an inert glovebox. Upon cooling, overtime oxygen readsorption switches the FET polarity to predominantly p-type ambipolar behavior, but PMMA encapsulation maintains low hysteresis. Unfortunately PMMA is sensitive to most solvents and heat treatments and therefore its application for nanostructured material deposition and doping is limited. Seeking a robust, general platform for low-hysteresis FETs we explored a variety of hydroxyl-free substrate surfaces, including silicon nitride, polyimide, and parylene, which show reduced electron trapping, but still large hysteresis. We identified a robust dielectric stack by assembling octadecylphosphonic acid (ODPA) on aluminum oxide (Al(2)O(3)) to form low-hysteresis FETs. We further integrated the ODPA/Al(2)O(3) gate dielectric stack on flexible substrates to demonstrate low-hysteresis, low-voltage FETs, and the promise of these nanostructured materials in flexible, electronic circuitry.

  17. Surface potential variations on a silicon nanowire transistor in biomolecular modification and detection

    Energy Technology Data Exchange (ETDEWEB)

    Tsai, Chia-Chang; Chiang, Pei-Ling; Lin, Tsung-Wu; Chen, Yit-Tsong [Institute of Atomic and Molecular Sciences, Academia Sinica, PO Box 23-166, Taipei 106, Taiwan (China); Sun, Chih-Jung; Tsai, Ming-Hsueh [Department of Chemistry, National Taiwan University, No. 1, Section 4, Roosevelt Road, Taipei 106, Taiwan (China); Chang, Yun-Chorng, E-mail: ychang6@mail.ncku.edu.tw, E-mail: ytcchem@ntu.edu.tw [Institute of Electro-Optical Science and Engineering, National Cheng Kung University, No. 1, Ta-Hsueh Road, Tainan 701, Taiwan (China)

    2011-04-01

    Using a silicon nanowire field-effect transistor (SiNW-FET) for biomolecule detections, we selected 3-(mercaptopropyl)trimethoxysilane (MPTMS), N-[6-(biotinamido)hexyl]-3{sup '}-(2{sup '}-pyridyldithio) propionamide (biotin-HPDP), and avidin, respectively, as the designated linker, receptor, and target molecules as a study model, where the biotin molecules were modified on the SiNW-FET to act as a receptor for avidin. We applied high-resolution scanning Kelvin probe force microscopy (KPFM) to detect the modified/bound biomolecules by measuring the induced change of the surface potential ({Delta}{Phi}{sup s}) on the SiNW-FET under ambient conditions. After biotin-immobilization and avidin-binding, the {Delta}{Phi}{sup s} on the SiNW-FET characterized by KPFM was demonstrated to correlate to the conductance change inside the SiNW-FET acquired in aqueous solution. The {Delta}{Phi}{sup s} values on the SiNW-FET caused by the same biotin-immobilization and avidin-binding were also measured from drain current versus gate voltage curves (I{sub d}-V{sub g}) in both aqueous condition and dried state. For comparison, we also study the {Delta}{Phi}{sup s} values on a Si wafer caused by the same biotin-immobilization and avidin-binding through KPFM and {zeta} potential measurements. This study has demonstrated that the surface potential measurement on a SiNW-FET by KPFM can be applied as a diagnostic tool that complements the electrical detection with a SiNW-FET sensor. Although the KPFM experiments were carried out under ambient conditions, the measured surface properties of a SiNW-FET are qualitatively valid compared with those obtained by other biosensory techniques performed in liquid environment.

  18. High-performance single-crystalline arsenic-doped indium oxide nanowires for transparent thin-film transistors and active matrix organic light-emitting diode displays.

    Science.gov (United States)

    Chen, Po-Chiang; Shen, Guozhen; Chen, Haitian; Ha, Young-geun; Wu, Chao; Sukcharoenchoke, Saowalak; Fu, Yue; Liu, Jun; Facchetti, Antonio; Marks, Tobin J; Thompson, Mark E; Zhou, Chongwu

    2009-11-24

    We report high-performance arsenic (As)-doped indium oxide (In(2)O(3)) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diode (AMOLED) displays. The As-doped In(2)O(3) nanowires were synthesized using a laser ablation process and then fabricated into TTFTs with indium-tin oxide (ITO) as the source, drain, and gate electrodes. The nanowire TTFTs on glass substrates exhibit very high device mobilities (approximately 1490 cm(2) V(-1) s(-1)), current on/off ratios (5.7 x 10(6)), steep subthreshold slopes (88 mV/dec), and a saturation current of 60 microA for a single nanowire. By using a self-assembled nanodielectric (SAND) as the gate dielectric, the device mobilities and saturation current can be further improved up to 2560 cm(2) V(-1) s(-1) and 160 microA, respectively. All devices exhibit good optical transparency (approximately 81% on average) in the visible spectral range. In addition, the nanowire TTFTs were utilized to control green OLEDs with varied intensities. Furthermore, a fully integrated seven-segment AMOLED display was fabricated with a good transparency of 40% and with each pixel controlled by two nanowire transistors. This work demonstrates that the performance enhancement possible by combining nanowire doping and self-assembled nanodielectrics enables silicon-free electronic circuitry for low power consumption, optically transparent, high-frequency devices assembled near room temperature.

  19. Ab-initio simulations of higher Miller index Si:SiO{sub 2} interfaces for fin field effect transistor and nanowire transistors

    Energy Technology Data Exchange (ETDEWEB)

    Li, Hongfei; Guo, Yuzheng; Robertson, John [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom); Okuno, Y. [Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science Park, Hsinchu, Taiwan (China)

    2016-02-07

    Models of three representative higher Miller index interfaces, Si(310):SiO{sub 2}, Si(410):SiO{sub 2}, and Si(331):SiO{sub 2}, have been built by an ab-initio molecular dynamics method. We show that each interface can be made as a fully bonded network without any defects and has a reasonable electronic structure for use in fin field effect transistors or gate-all-around nanowire devices. The differences in numbers of oxygen bridges are attributed to the intermediate sub-oxide components and the atomic step structure. The interface bonding schemes to passivate different densities of dangling bonds on different facets are also analyzed.

  20. Controlling the threshold voltage of SnO2 nanowire transistors with dual in-plane-gate structures gated by chitosan proton conductors

    Science.gov (United States)

    Liu, Huixuan; Tan, Rongri

    2017-05-01

    We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to -1.0 V, we tuned the threshold voltage of these transistors from -0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

  1. A top-gate GaN nanowire metal-semiconductor field effect transistor with improved channel electrostatic control

    Science.gov (United States)

    Gačević, Ž.; López-Romero, D.; Juan Mangas, T.; Calleja, E.

    2016-01-01

    A uniformly n-type doped GaN:Si nanowire (NW), with a diameter of d = 90 nm and a length of 1.2 μm, is processed into a metal-semiconductor field effect transistor (MESFET) with a semi-cylindrical top Ti/Au Schottky gate. The FET is in a normally-ON mode, with the threshold at -0.7 V and transconductance of gm ˜ 2 μS (the transconductance normalized with NW diameter gm/d > 22 mS/mm). It enters the saturation mode at VDS ˜ 4.5 V, with the maximum measured drain current IDS = 5.0 μA and the current density exceeding JDS > 78 kA/cm2.

  2. The ITO-capped WO{sub 3} nanowires biosensor based on field-effect transistor in label-free protein sensing

    Energy Technology Data Exchange (ETDEWEB)

    Shariati, Mohsen [Sharif University of Technology, Institute for Nanoscience and Nanotechnology, Tehran (Iran, Islamic Republic of)

    2017-05-15

    The fabrication of ITO-capped WO{sub 3} nanowires associated with their bio-sensing properties in field-effect transistor diagnostics basis as a biosensor has been reported. The bio-sensing property for manipulated nanowires elucidated that the grown nanostructures were very sensitive to protein. The ITO-capped WO{sub 3} nanowires biosensor showed an intensive bio-sensing activity against reliable protein. Polylysine strongly charged bio-molecule was applied as model system to demonstrate the implementation of materialized biosensor. The employed sensing mechanism was 'label-free' and depended on bio-molecule's intrinsic charge. For nanowires synthesis, the vapor-liquid-solid mechanism was used. Nanowires were beyond a few hundred nanometers in lengths and around 15-20 nm in diameter, while the globe cap's size on the nanowires was around 15-25 nm. The indium tin oxide (ITO) played as catalyst in nanofabrication for WO{sub 3} nanowires growth and had outstanding role in bio-sensing especially for bio-molecule adherence. In applied electric field presence, the fabricated device showed the great potential to enhance medical diagnostics. (orig.)

  3. Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

    Science.gov (United States)

    Al-Ameri, Talib; Georgiev, Vihar P.; Sadi, Toufik; Wang, Yijiao; Adamu-Lema, Fikru; Wang, Xingsheng; Amoroso, Salvatore M.; Towie, Ewan; Brown, Andrew; Asenov, Asen

    2017-03-01

    In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations and and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

  4. Methods for rapid frequency-domain characterization of leakage currents in silicon nanowire-based field-effect transistors

    Directory of Open Access Journals (Sweden)

    Tomi Roinila

    2014-07-01

    Full Text Available Silicon nanowire-based field-effect transistors (SiNW FETs have demonstrated the ability of ultrasensitive detection of a wide range of biological and chemical targets. The detection is based on the variation of the conductance of a nanowire channel, which is caused by the target substance. This is seen in the voltage–current behavior between the drain and source. Some current, known as leakage current, flows between the gate and drain, and affects the current between the drain and source. Studies have shown that leakage current is frequency dependent. Measurements of such frequency characteristics can provide valuable tools in validating the functionality of the used transistor. The measurements can also be an advantage in developing new detection technologies utilizing SiNW FETs. The frequency-domain responses can be measured by using a commercial sine-sweep-based network analyzer. However, because the analyzer takes a long time, it effectively prevents the development of most practical applications. Another problem with the method is that in order to produce sinusoids the signal generator has to cope with a large number of signal levels. This may become challenging in developing low-cost applications. This paper presents fast, cost-effective frequency-domain methods with which to obtain the responses within seconds. The inverse-repeat binary sequence (IRS is applied and the admittance spectroscopy between the drain and source is computed through Fourier methods. The methods is verified by experimental measurements from an n-type SiNW FET.

  5. Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors

    Science.gov (United States)

    van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

    2016-06-01

    We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (high voltage gain (~6) and ultralow static power dissipation (high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (high voltage gain (~6) and ultralow static power dissipation (high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr01040g

  6. Controllable electrical properties of metal-doped In2O3 nanowires for high-performance enhancement-mode transistors.

    Science.gov (United States)

    Zou, Xuming; Liu, Xingqiang; Wang, Chunlan; Jiang, Ying; Wang, Yong; Xiao, Xiangheng; Ho, Johnny C; Li, Jinchai; Jiang, Changzhong; Xiong, Qihua; Liao, Lei

    2013-01-22

    In recent years, In(2)O(3) nanowires (NWs) have been widely explored in many technological areas due to their excellent electrical and optical properties; however, most of these devices are based on In(2)O(3) NW field-effect transistors (FETs) operating in the depletion mode, which induces relatively higher power consumption and fancier circuit integration design. Here, n-type enhancement-mode In(2)O(3) NW FETs are successfully fabricated by doping different metal elements (Mg, Al, and Ga) in the NW channels. Importantly, the resulting threshold voltage can be effectively modulated through varying the metal (Mg, Ga, and Al) content in the NWs. A series of scaling effects in the mobility, transconductance, threshold voltage, and source-drain current with respect to the device channel length are also observed. Specifically, a small gate delay time (0.01 ns) and high on-current density (0.9 mA/μm) are obtained at 300 nm channel length. Furthermore, Mg-doped In(2)O(3) NWs are then employed to fabricate NW parallel array FETs with a high saturation current (0.5 mA), on/off ratio (>10(9)), and field-effect mobility (110 cm(2)/V·s), while the subthreshold slope and threshold voltage do not show any significant changes. All of these results indicate the great potency for metal-doped In(2)O(3) NWs used in the low-power, high-performance thin-film transistors.

  7. High-performance ambipolar self-assembled Au/Ag nanowire based vertical quantum dot field effect transistor

    Science.gov (United States)

    Song, Xiaoxian; Zhang, Yating; Zhang, Haiting; Yu, Yu; Cao, Mingxuan; Che, Yongli; Wang, Jianlong; Dai, Haitao; Yang, Junbo; Ding, Xin; Yao, Jianquan

    2016-10-01

    Most lateral PbSe quantum dot field effect transistors (QD FETs) show a low on current/off current (I on/I off) ratio in charge transport measurements. A new strategy to provide generally better performance is to design PbSe QD FETs with vertical architecture, in which the structure parameters can be tuned flexibly. Here, we fabricated a novel room-temperature operated vertical quantum dot field effect transistor with a channel of 580 nm, where self-assembled Au/Ag nanowires served as source transparent electrodes and PbSe quantum dots as active channels. Through investigating the electrical characterization, the ambipolar device exhibited excellent characteristics with a high I on/I off current ratio of about 1 × 105 and a low sub-threshold slope (0.26 V/decade) in the p-type regime. The all-solution processing vertical architecture provides a convenient way for low cost, large-area integration of the device.

  8. EDITORIAL: Nanowires Nanowires

    Science.gov (United States)

    Jagadish, Chennupati

    2010-02-01

    Nanowires are considered as building blocks for the next generation of electronics, photonics, sensors and energy applications. One-dimensional nanostructures offer unique opportunities to control the density of states of semiconductors, and in turn their electronic and optical properties. Nanowires allow the growth of axial heterostructures without the constraints of lattice mismatch. This provides flexibility to create heterostructures of a broad range of materials and allows integration of compound semiconductor based optoelectronic devices with silicon based microelectronics. Nanowires are widely studied and the number of papers published in the field is growing exponentially with time. Already nanowire lasers, nanowire transistors, nanowire light emitting diodes, nanowire sensors and nanowire solar cells have been demonstrated. This special issue on semiconductor nanowires features 17 invited papers from leading experts in the field. In this special issue, the synthesis and growth of semiconductor nanowires of a broad range of materials have been addressed. Both axial and radial heterostructures and their structural properties have been discussed. Electrical transport properties of nanowires have been presented, as well as optical properties and carrier dynamics in a range of nanowires and nanowire heterostructures. Devices such as nanowire lasers and nanowire sensors have also been discussed. I would like to thank the Editorial Board of the journal for suggesting this special issue and inviting me to serve as the Guest Editor. Sincere thanks are due to all the authors for their contributions to this special issue. I am grateful to the reviewers and editorial staff at Semiconductor Science and Technology and the Institute of Physics Publishing for their excellent efforts. Special thanks are due to Dr Claire Bedrock for coordinating this special issue.

  9. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Science.gov (United States)

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  10. Light-gated single CdSe nanowire transistor: photocurrent saturation and band gap extraction

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Yang, E-mail: yangzh08@gmail.com; Chakraborty, Ritun; Kudera, Stefan; Krahne, Roman, E-mail: roman.krahne@iit.it [Istituto Italiano di Tecnologia, Nanochemistry department (Italy)

    2015-11-15

    CdSe nanowires are popular building blocks for many optoelectronic devices mainly owing to their direct band gap in the visible range of the spectrum. Here we investigate the optoelectronic properties of single CdSe nanowires fabricated by colloidal synthesis, in terms of their photocurrent–voltage characteristics and photoconductivity spectra recorded at 300 and 18 K. The photocurrent is identified as the secondary photocurrent, which gives rise to a photoconductive gain of ∼35. We observe a saturation of the photocurrent beyond a certain voltage bias that can be related to the finite drift velocity of electrons. From the photoconductivity spectra, we determine the band gap energy of the nanowires as ∼1.728 eV, and we resolve low-energy peaks that can be associated with sub-bandgap states.Graphical Abstract.

  11. High-Performance Photo-Modulated Thin-Film Transistor Based on Quantum dots/Reduced Graphene Oxide Fragment-Decorated ZnO Nanowires

    Institute of Scientific and Technical Information of China (English)

    Zhi Tao; Zichen Zhang; Yi-an Huang; Xiang Liu; Jing Chen; Wei Lei; Xiaofeng Wang; Lingfeng Pan; Jiangyong Pan; Qianqian Huang

    2016-01-01

    In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of CdSe quantum dots and reduced graphene oxide (RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 A W-1 and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.

  12. Memristive behavior in a junctionless flash memory cell

    Energy Technology Data Exchange (ETDEWEB)

    Orak, Ikram [Vocational School of Health Services, Bingöl University, 12000 Bingöl (Turkey); Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl (Turkey); Ürel, Mustafa; Dana, Aykutlu, E-mail: aykutlu@unam.bilkent.edu.tr [UNAM Institute of Materials Science and Nanotechnology, Bilkent University, 06800 Ankara (Turkey); Bakan, Gokhan [Faculty of Engineering, Antalya International University, 07190 Antalya (Turkey)

    2015-06-08

    We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

  13. Memristive behavior in a junctionless flash memory cell

    Science.gov (United States)

    Orak, Ikram; Ürel, Mustafa; Bakan, Gokhan; Dana, Aykutlu

    2015-06-01

    We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, Al2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, Roff/Ron ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

  14. Fabrication and photoelectrical characteristics of ZnO nanowire field-effect transistors

    Institute of Scientific and Technical Information of China (English)

    Fu Xiaojun; Zhang Haiying; Guo Changxin; Xu Jingbo; Li Ming

    2009-01-01

    rease by almost half of the source-drain current (Ids, from 560 nA to 320 nA) due to drain-induced barrier lowering.Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.

  15. All-(111) surface silicon nanowire field effect transistor devices: Effects of surface preparations

    NARCIS (Netherlands)

    Masood, Muhammad Nasir; Carlen, Edwin T.; Berg, van den Albert

    2014-01-01

    Etching/hydrogen termination of All-(111) surface silicon nanowire field effect (SiNW-FET) devices developed by conventional photolithography and plane dependent wet etchings is studied with X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM) and

  16. Nanowire Lasers

    OpenAIRE

    Couteau C.; Larrue A.; Wilhelm C.; Soci C.

    2015-01-01

    We review principles and trends in the use of semiconductor nanowires as gain media for stimulated emission and lasing. Semiconductor nanowires have recently been widely studied for use in integrated optoelectronic devices, such as light-emitting diodes (LEDs), solar cells, and transistors. Intensive research has also been conducted in the use of nanowires for subwavelength laser systems that take advantage of their quasione- dimensional (1D) nature, fl...

  17. Sub-15 nm gate-all-around field effect transistors on vertical silicon nanowires

    Science.gov (United States)

    Larrieu, G.; Guerfi, Y.; Han, X. L.; Clément, N.

    2017-04-01

    A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.

  18. Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

    Science.gov (United States)

    Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

    2015-02-04

    Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli.

  19. High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: effects of metal contacts and ozone treatment

    Energy Technology Data Exchange (ETDEWEB)

    Ju, Sanghyun [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States); Lee, Kangho [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States); Yoon, Myung-Han [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Facchetti, Antonio [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Marks, Tobin J [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Janes, David B [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States)

    2007-04-18

    High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using a nanoscopic self-assembled organic gate insulator and characterized in terms of conventional device performance metrics. To optimize device performance and understand the effects of interface properties, devices were fabricated with both Al and Au/Ti source/drain contacts, and device electrical properties were characterized following annealing and ozone treatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current (I{sub on}) of {approx}4 {mu}A at 0.9 V{sub gs} and 1.0 V{sub ds}, a threshold voltage (V{sub th}) of 0.2 V, a subthreshold slope (S) of {approx}130 mV/decade, an on-off current ratio (I{sub on}:I{sub off}) of {approx}10{sup 7}, and a field effect mobility ({mu}{sub eff}) of {approx}1175 cm{sup 2} V{sup -1} s{sup -1}. In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metrics after SiO{sub 2} passivation. A 2D device simulation was performed to explain the enhanced device performance in terms of changes in interfacial trap and fixed charge densities.

  20. High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: effects of metal contacts and ozone treatment

    Science.gov (United States)

    Ju, Sanghyun; Lee, Kangho; Yoon, Myung-Han; Facchetti, Antonio; Marks, Tobin J.; Janes, David B.

    2007-04-01

    High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using a nanoscopic self-assembled organic gate insulator and characterized in terms of conventional device performance metrics. To optimize device performance and understand the effects of interface properties, devices were fabricated with both Al and Au/Ti source/drain contacts, and device electrical properties were characterized following annealing and ozone treatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current (Ion) of ~4 µA at 0.9 Vgs and 1.0 Vds, a threshold voltage (Vth) of 0.2 V, a subthreshold slope (S) of ~130 mV/decade, an on-off current ratio (Ion:Ioff) of ~107, and a field effect mobility (μeff) of ~1175 cm2 V-1 s-1. In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metrics after SiO2 passivation. A 2D device simulation was performed to explain the enhanced device performance in terms of changes in interfacial trap and fixed charge densities.

  1. Multiple Schottky Barrier-Limited Field-Effect Transistors on a Single Si Nanowire with an Intrinsic Doping Gradient.

    Science.gov (United States)

    Barreda, Jorge L; Keiper, Timothy D; Zhang, Mei; Xiong, Peng

    2017-03-09

    In comparison to conventional (channel-limited) field-effect transistors (FETs), Schottky barrier-limited FETs possess some unique characteristics which make them attractive candidates for some electronic and sensing applications. Consequently, modulation of the nano Schottky barrier at a metal-semiconductor interface promises higher performance for chemical and biomolecular sensor applications when compared to conventional FETs with Ohmic contacts. However, the fabrication and optimization of devices with a combination of ideal Ohmic and Schottky contacts as the source and drain respectively present many challenges. We address this issue by utilizing Si nanowires (NWs) synthesized by a chemical vapor deposition process which yields a pronounced doping gradient along the length of the NWs. Devices with a series of metal contacts on a single Si NW are fabricated in a single lithography and metallization process. The graded doping profile of the NW is manifested in monotonic increases in the channel and junction resistances and variation of the nature of the contacts from Ohmic to Schottky of increasing effective barrier height along the NW. Hence multiple single Schottky junction-limited FETs with extreme asymmetry and high reproducibility are obtained on an individual NW. A definitive correlation between increasing Schottky-barrier height and enhanced gate modulation is revealed. Having access to systematically varying Schottky barrier contacts on the same NW device provides an ideal platform for identifying optimal device characteristics for sensing and electronic applications.

  2. Pseudopotential-based electron quantum transport: Theoretical formulation and application to nanometer-scale silicon nanowire transistors

    Energy Technology Data Exchange (ETDEWEB)

    Fang, Jingtian, E-mail: jingtian.fang@utdallas.edu; Vandenberghe, William G.; Fu, Bo; Fischetti, Massimo V. [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas 75080 (United States)

    2016-01-21

    We present a formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials. This formalism offers explicit atomistic wavefunctions and an accurate band structure, enabling a detailed study of the characteristics of devices with a nanometer-scale channel and body. Assuming externally applied potentials that change slowly along the electron-transport direction, we invoke the envelope-wavefunction approximation to apply the open boundary conditions and to develop the transport equations. We construct the full-band open boundary conditions (self-energies of device contacts) from the complex band structure of the contacts. We solve the transport equations and present the expressions required to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gate-all-around (GAA) silicon nanowire field-effect transistor with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of ∼66 mV/decade and a drain-induced barrier-lowering of ∼2.5 mV/V. Our theoretical calculations predict that low-dimensionality channels in a 3D GAA architecture are able to meet the performance requirements of future devices in terms of SS swing and electrostatic control.

  3. Pseudopotential-based electron quantum transport: Theoretical formulation and application to nanometer-scale silicon nanowire transistors

    Science.gov (United States)

    Fang, Jingtian; Vandenberghe, William G.; Fu, Bo; Fischetti, Massimo V.

    2016-01-01

    We present a formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials. This formalism offers explicit atomistic wavefunctions and an accurate band structure, enabling a detailed study of the characteristics of devices with a nanometer-scale channel and body. Assuming externally applied potentials that change slowly along the electron-transport direction, we invoke the envelope-wavefunction approximation to apply the open boundary conditions and to develop the transport equations. We construct the full-band open boundary conditions (self-energies of device contacts) from the complex band structure of the contacts. We solve the transport equations and present the expressions required to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gate-all-around (GAA) silicon nanowire field-effect transistor with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of ˜66 mV/decade and a drain-induced barrier-lowering of ˜2.5 mV/V. Our theoretical calculations predict that low-dimensionality channels in a 3D GAA architecture are able to meet the performance requirements of future devices in terms of SS swing and electrostatic control.

  4. Unusual impact of electron-phonon scattering in Si nanowire field-effect-transistors: A possible route for energy harvesting

    Science.gov (United States)

    Nag Chowdhury, Basudev; Chattopadhyay, Sanatan

    2016-09-01

    In the current work, the impact of electron-phonon scattering phenomena on the transport behaviour of silicon nanowire field-effect-transistors with sub-mean free path channel length has been investigated by developing a theoretical model that incorporates the responses of carrier effective mass mismatch between the channel and source/drain. For this purpose, a set of relevant quantum field equations has been solved by non-equilibrium Green's function formalism. The obtained device current for a particular set of biases is found to decrease due to phonon scattering below a certain doping level of source/drain, above which it is observed to enhance anomalously. Analyses of the quantified scattering lifetime and power dissipation at various confinement modes of the device indicates that such unusual enhancement of current is originated from the power served by phonons instead of associated decay processes. The power generation has been observed to improve by using high-k materials as gate insulator. Such results may contribute significantly to the future nano-electronic applications for energy harvesting.

  5. Magnetic-composite-modified polycrystalline silicon nanowire field-effect transistor for vascular endothelial growth factor detection and cancer diagnosis.

    Science.gov (United States)

    Chen, Hsiao-Chien; Qiu, Jian-Tai; Yang, Fu-Liang; Liu, Yin-Chih; Chen, Min-Cheng; Tsai, Rung-Ywan; Yang, Hung-Wei; Lin, Chia-Yi; Lin, Chu-Chi; Wu, Tzong-Shoon; Tu, Yi-Ming; Xiao, Min-Cong; Ho, Chia-Hua; Huang, Chien-Chao; Lai, Chao-Sung; Hua, Mu-Yi

    2014-10-01

    This study proposes a vascular endothelial growth factor (VEGF) biosensor for diagnosing various stages of cervical carcinoma. In addition, VEGF concentrations at various stages of cancer therapy are determined and compared to data obtained by computed tomography (CT) and cancer antigen 125 (CA-125). The increase in VEGF concentrations during operations offers useful insight into dosage timing during cancer therapy. This biosensor uses Avastin as the biorecognition element for the potential cancer biomarker VEGF and is based on a n-type polycrystalline silicon nanowire field-effect transistor (poly-SiNW-FET). Magnetic nanoparticles with poly[aniline-co-N-(1-one-butyric acid) aniline]-Fe3O4 (SPAnH-Fe3O4) shell-core structures are used as carriers for Avastin loading and provide rapid purification due to their magnetic properties, which prevent the loss of bioactivity; furthermore, the high surface area of these structures increases the quantity of Avastin immobilized. Average concentrations in human blood for species that interfere with detection specificity are also evaluated. The detection range of the biosensor for serum samples covers the results expected from both healthy individuals and cancer patients.

  6. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    Science.gov (United States)

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  7. Low-voltage antimony-doped SnO2 nanowire transparent transistors gated by microporous SiO2-based proton conductors

    Institute of Scientific and Technical Information of China (English)

    Xuan Rui-Jie; Liu Hui-Xuan

    2012-01-01

    A battery drivable low-voltage transparent lightly antimony(Sb)-doped SnO2 nanowire electric-double-layer (EDL)field-effect transistor (FET) is fabricated on an ITO glass substrate at room temperature.An ultralow operation voltage of 1 V is obtained on account of an untralarge specific gate capacitance (~ 2.14 μF/cm2) directly bound up with mobile ions-induced EDL (sandwiched between the top and bottom electrodes) effect.The transparent FET shows excellent electric characteristics with a field-effect mobility of 54.43 cm2/V.s,current on/off ration of 2 × 104,and subthreshold gate voltage swing (S =dVgs/d(logIds)) of 140 mV/decade.The threshold voltage Vth (0.1 V) is estimated which indicates that the SnO2 namowire transistor operates in an n-type enhanced mode.Such a low-voltage transparent nanowire transistor gated by a microporous SiO2-based solid electrolyte is very promising for battery-powered portable nanoscale sensors.

  8. Indium arsenide nanowire field-effect transistors for pH and biological sensing

    Energy Technology Data Exchange (ETDEWEB)

    Upadhyay, S.; Krogstrup, P.; Nygård, J., E-mail: nygard@nbi.dk [Center for Quantum Devices and Nanoscience Center, Niels Bohr Institute, University of Copenhagen, Universitetsparken 5, DK-2100 Copenhagen (Denmark); Frederiksen, R.; Lloret, N.; Martinez, K. L. [Bio-Nanotechnology and Nanomedicine Laboratory, Department of Chemistry and Nanoscience Center, University of Copenhagen, Universitetsparken 5, DK-2100 Copenhagen (Denmark); De Vico, L.; Jensen, J. H. [Department of Chemistry, University of Copenhagen, Universitetsparken 5, DK-2100 Copenhagen (Denmark)

    2014-05-19

    Indium Arsenide is a high mobility semiconductor with a surface electron accumulation layer that allows ohmic electrical contact to metals. Here, we present nanowire devices based on this material as a platform for chemical and biological sensing. The sensing principle involves the binding of a charged species at the sensor surface transduced via field effect into a change in current flowing through the sensor. We show the sensitivity of the platform to the H{sup +} ion concentration in solution as proof of principle and demonstrate the sensitivity to larger charged protein species. The sensors are highly reproducible and reach a detection limit of 10 pM for Avidin.

  9. Contact-enhanced transparent silver nanowire network for all solution-based top-contact metal-oxide thin-film transistors.

    Science.gov (United States)

    Kim, Yong-Hoon; Kim, Tae-Hyoung; Lee, Yeji; Kim, Jong-Woong; Kim, Jaekyun; Park, Sung Kyu

    2014-11-01

    In this paper, we investigate contact-enhanced transparent silver nanowire (Ag NW) network for solution-processed metal-oxide thin-film transistors (TFTs). Mechanical roll pressing was applied to a bar-coated Ag NW film to enhance the inter-nanowire connectivity. As a result, the sheet resistance of the Ag NW film was decreased from 119.5 ψ/square to 92.4 ψ/square, and more stable and enhanced TFT characteristics were achieved when the roll-pressed Ag NW was employed as source/drain electrodes. In addition, a non-acidic wet etching method was developed to pattern the Ag NW electrodes to construct top-contact geometry indium-gallium-zinc oxide TFTs. From the results, it is believed that the mechanical roll pressing and non-acidic wet etching method may be utilized in realizing all solution-based transparent metal-oxide TFTs.

  10. Detection of chemical substances in water using an oxide nanowire transistor covered with a hydrophobic nanoparticle thin film as a liquid-vapour separation filter

    Science.gov (United States)

    Lim, Taekyung; Lee, Jonghun; Ju, Sanghyun

    2016-08-01

    We have developed a method to detect the presence of small amounts of chemical substances in water, using a Al2O3 nanoparticle thin film covered with phosphonic acid (HDF-PA) self-assembled monolayer. The HDF-PA self-assembled Al2O3 nanoparticle thin film acts as a liquid-vapour separation filter, allowing the passage of chemical vapour while blocking liquids. Prevention of the liquid from contacting the SnO2 nanowire and source-drain electrodes is required in order to avoid abnormal operation. Using this characteristic, the concentration of chemical substances in water could be evaluated by measuring the current changes in the SnO2 nanowire transistor covered with the HDF-PA self-assembled Al2O3 nanoparticle thin film.

  11. Detection of chemical substances in water using an oxide nanowire transistor covered with a hydrophobic nanoparticle thin film as a liquid-vapour separation filter

    Directory of Open Access Journals (Sweden)

    Taekyung Lim

    2016-08-01

    Full Text Available We have developed a method to detect the presence of small amounts of chemical substances in water, using a Al2O3 nanoparticle thin film covered with phosphonic acid (HDF-PA self-assembled monolayer. The HDF-PA self-assembled Al2O3 nanoparticle thin film acts as a liquid-vapour separation filter, allowing the passage of chemical vapour while blocking liquids. Prevention of the liquid from contacting the SnO2 nanowire and source-drain electrodes is required in order to avoid abnormal operation. Using this characteristic, the concentration of chemical substances in water could be evaluated by measuring the current changes in the SnO2 nanowire transistor covered with the HDF-PA self-assembled Al2O3 nanoparticle thin film.

  12. Realization of size controllable graphene micro/nanogap with a micro/nanowire mask method for organic field-effect transistors

    DEFF Research Database (Denmark)

    Liao, Zhiyu; Wan, Qing; Liu, Huixuan;

    2011-01-01

    A size controllable graphene micro/nanogap fabrication method using micro/nanowire as mask is presented. The gap dimension can be adjusted by the diameter of the mask wire. As a typical application, copper phthalocyanine (CuPc) film organic field-effect transistors (OFETs) were fabricated...... with the graphene micro/nanogap bottom electrodes. The ultrathin thickness of the graphene, combined with its good compatibility with organic semiconductors, and high electrical conductivity produced high-performance CuPc film device with mobility at 0.053 cm(2)/Vs and on/off ratio at 10(5), showing promising...

  13. Photoinduced current and emission induced by current in a nanowire transistor: Temperature dependence

    Indian Academy of Sciences (India)

    Darehdor Mahvash Arabi; Shahtahmassebi Nasser

    2016-03-01

    In this paper, we present a theoretical study on a light emitting and current carrying nanosystem, in the nonzero temperature regime. The system under consideration is a semiconducting nanowire sandwiched between two semi-infinite metallic electrodes. The study was performed using the Keldysh nonequilibrium Green’s function method. We systematically investigate the photoinduced current and the light emission induced by this electronic current in the presence of gate voltage. The temperature dependence of these processes are also investigated in the temperature range of 3–300 K. Our study shows that, the photoinduced current is due to the transfer of electrons from highest occupied molecular orbital (HOMO) to the lowest unoccupied molecularorbital (LUMO). Thus, the separation of electron from the electron–hole pair creates a free electron which is responsible for the observed photoinduced current. The same conclusion is also arrived at for the reverse process of light emission under the influence of the electronic current.

  14. Non-Faradaic electrical impedimetric investigation of the interfacial effects of neuronal cell growth and differentiation on silicon nanowire transistors.

    Science.gov (United States)

    Lin, Shu-Ping; Vinzons, Lester U; Kang, Yu-Shan; Lai, Tung-Yen

    2015-05-13

    Silicon nanowire field-effect transistor (SiNW FET) devices have been interfaced with cells; however, their application for noninvasive, real-time monitoring of interfacial effects during cell growth and differentiation on SiNW has not been fully explored. Here, we cultured rat adrenal pheochromocytoma (PC12) cells, a type of neural progenitor cell, directly on SiNW FET devices to monitor cell adhesion during growth and morphological changes during neuronal differentiation for a period of 5-7 d. Monitoring was performed by measuring the non-Faradaic electrical impedance of the cell-SiNW FET system using a precision LCR meter. Our SiNW FET devices exhibited changes in impedance parameters during cell growth and differentiation because of the negatively charged cell membrane, seal resistance, and membrane capacitance at the cell/SiNW interface. It was observed that during both PC12 cell growth and neuronal differentiation, the impedance magnitude increased and the phase shifted to more negative values. However, impedance changes during cell growth already plateaued 3 d after seeding, while impedance changes continued until the last observation day during differentiation. Our results also indicate that the frequency shift to above 40 kHz after growth factor induction resulted from a larger coverage of cell membrane on the SiNWs due to distinctive morphological changes according to vinculin staining. Encapsulation of PC12 cells in a hydrogel scaffold resulted in a lack of trend in impedance parameters and confirmed that impedance changes were due to the cells. Moreover, cytolysis of the differentiated PC12 cells led to significant changes in impedance parameters. Equivalent electrical circuits were used to analyze the changes in impedance values during cell growth and differentiation. The technique employed in this study can provide a platform for performing investigations of growth-factor-induced progenitor cell differentiation.

  15. High frequency III-V nanowire MOSFETs

    Science.gov (United States)

    Lind, Erik

    2016-09-01

    III-V nanowire transistors are promising candidates for very high frequency electronics applications. The improved electrostatics originating from the gate-all-around geometry allow for more aggressive scaling as compared with planar field-effect transistors, and this can lead to device operation at very high frequencies. The very high mobility possible with In-rich devices can allow very high device performance at low operating voltages. GaN nanowires can take advantage of the large band gap for high voltage operation. In this paper, we review the basic physics and device performance of nanowire field- effect transistors relevant for high frequency performance. First, the geometry of lateral and vertical nanowire field-effect transistors is introduced, with special emphasis on the parasitic capacitances important for nanowire geometries. The basic important high frequency transistor metrics are introduced. Secondly, the scaling properties of gate-all-around nanowire transistors are introduced, based on geometric length scales, demonstrating the scaling possibilities of nanowire transistors. Thirdly, to model nanowire transistor performance, a two-band non-parabolic ballistic transistor model is used to efficiently calculate the current and transconductance as a function of band gap and nanowire size. The intrinsic RF metrics are also estimated. Finally, experimental state-of-the-art nanowire field-effect transistors are reviewed and benchmarked, lateral and vertical transistor geometries are explored, and different fabrication routes are highlighted. Lateral devices have demonstrated operation up to 350 GHz, and vertical devices up to 155 GHz.

  16. Biosensor based on a silicon nanowire field-effect transistor functionalized by gold nanoparticles for the highly sensitive determination of prostate specific antigen.

    Science.gov (United States)

    Presnova, Galina; Presnov, Denis; Krupenin, Vladimir; Grigorenko, Vitaly; Trifonov, Artem; Andreeva, Irina; Ignatenko, Olga; Egorov, Alexey; Rubtsova, Maya

    2017-02-15

    We have demonstrated label-free and real-time detection of prostate specific antigen (PSA) in human serum using silicon nanowire field effect transistors (NW FETs) with Schottky contacts (Si-Ti). The NW FETs were fabricated from SOI material using high-resolution e-beam lithography, thin film vacuum deposition and reactive-ion etching processes eliminating complicated processes of doping and thermal annealing. This allowed substantial simplifying the transistors manufacturing. A new method for covalent immobilization of half-fragments of antibodies on silicon modified by 3-glycidopropyltrimethoxysilane with thiol groups and 5nm gold nanoparticles (GNPs) was established. NW FETs functionalized by GNPs revealed extremely high pH sensitivity of 70mV/pH and enhanced electrical performance in the detection of antigen due to enhanced surface/volume ratio, favorable orientation of antibody active sites and approaching the source of the electric field close to the transistor surface. Si NWFETs were applied for quantitative detection of PSA in a buffer and human serum diluted 1/100. Response time was about 5-10s, and analysis time per sample was 1min. The limit of PSA detection was of 23fg/mL, concentration range of 23fg/mL-500ng/mL (7 orders of magnitude). The PSA concentrations determined by the NW FETs in serum were compared with well-established ELISA method. The results matched well with the correlation coefficient of 0.97.

  17. Effect of Surface-optical Phonons on the Charge Transport in Wrap-gated Semiconducting Nanowire Field-effect Transistors

    Science.gov (United States)

    Konar, Aniruddha; Fang, Tian; Jena, Debdeep

    2010-03-01

    Surface phonons (SO-phonons) arise at the boundary of two different dielectric mediums. Though the effect of electron-surface phonon scattering on low-filed charge transport has been studied extensively for thin Si-MOSFET [1] and graphene [2], its effect on the 1D nanowire devices has not studied so far. Vibrating diploes in polar gate-dielectric induces a time-varying potential inside the nanowires. The frequencies of these time-varying fields have been calculated by implementing electrostatic boundary conditions at different interfaces of nanowire-dielectric-metal system. Our calculation shows that the electron-SO phonon interaction strength decays exponentially from the gate-nanowire interface towards the nanowire axis. Electron-SO phonon scattering rate has been calculated using Boltzmann transport equation under relaxation time approximation. We find that for thin nanowires (radius 1-20 nm), electron-SO phonon scattering rate is comparable to other dominant scattering mechanisms (such as impurity and bulk optical phonon scatterings) and reduces carrier mobility significantly. Calculating surface-phonon limited mobility of Si nanowires on various available common dielectrics, we have predicted the optimum choice of gate-dielectrics for nanowire-based electronic devices. [4pt] [1] M. V. Fischetti et. al J. Appl. Phys. 90 4581 (2001). [0pt] [2] A. Konar et. al. arXiv: 0902.0819.

  18. Device and Circuit Codesign Strategy for Application to Low-Noise Amplifier Based on Silicon Nanowire Metal-Oxide-Semiconductor Field Effect Transistors

    Science.gov (United States)

    Seongjae Cho,; Hee-Sauk Jhon,; Jung Hoon Lee,; Se Hwan Park,; Hyungcheol Shin,; Byung-Gook Park,

    2010-04-01

    In this study, a full-range approach from device level to circuit level design is performed for RF application of silicon nanowire (SNW) metal-oxide-semiconductor field effect transistors (MOSFETs). Both DC and AC analyses have been conducted to confirm the advantages of an SNW MOSFET over the conventional planar (CPL) MOSFET device having dimensional equivalence. Besides the intrinsic characteristic parameters, the extrinsic resistance and capacitance caused by wiring components are extracted from each device. On the basis of these intrinsic and extrinsic parameters, a multi-fingered 5.8 GHz low-noise amplifier (LNA) design adopting SNW MOSFETs has been achieved, which shows an improved gain of 17.5 dB and a noise figure of 3.1 dB over a CPL MOSFET LNA.

  19. Multiplex electrical detection of avian influenza and human immunodeficiency virus with an underlap-embedded silicon nanowire field-effect transistor.

    Science.gov (United States)

    Kim, Jee-Yeon; Ahn, Jae-Hyuk; Moon, Dong-Il; Park, Tae Jung; Lee, Sang Yup; Choi, Yang-Kyu

    2014-05-15

    The label-free electrical detection of the binding of antibodies and antigens of avian influenza (AI) and human immunodeficiency (HIV) viruses is demonstrated through an underlap-embedded silicon (Si) nanowire field-effect transistor. The proposed sensor was fabricated on a silicon bulk wafer by a top-down process. Specifically, a Si nanowire was fabricated by a combined isotropic and anisotropic patterning technique, which is one route plasma etching process. The sensor was fabricated by a self-aligned process to the gate with tilted implantation, and it allows precise control of the underlap region. This was problematic in earlier underlap field-effect transistors fabricated by a conventional gate-last process. As a sensing metric to detect the binding of a targeted antibody, the transfer characteristic change was traced. Before and after differences between the antibody binding results were caused by changes in the channel potential on the underlap region due to the charge effect arising from the biomolecules; this is also supported by a simulation. Furthermore, the multiplex detection of AI and HIV is demonstrated, showing distinctive selectivity in each case. Thus, the proposed device has inherent benefits for the label-free, electrical, and multiplex detection of biomolecules. Moreover, its processes are compatible with commercialized technology presently used to fabricate semiconductor devices. This advantage is attractive for those involved in the construction of a point-of-care testing (POCT) system on a chip involving simple, low-cost and low-risk fabrication processes of novel structures and materials.

  20. Interface Passivation and Trap Reduction via a Solution-Based Method for Near-Zero Hysteresis Nanowire Field-Effect Transistors.

    Science.gov (United States)

    Constantinou, Marios; Stolojan, Vlad; Rajeev, Kiron Prabha; Hinder, Steven; Fisher, Brett; Bogart, Timothy D; Korgel, Brian A; Shkunov, Maxim

    2015-10-14

    In this letter, we demonstrate a solution-based method for a one-step deposition and surface passivation of the as-grown silicon nanowires (Si NWs). Using N,N-dimethylformamide (DMF) as a mild oxidizing agent, the NWs' surface traps density was reduced by over 2 orders of magnitude from 1×10(13) cm(-2) in pristine NWs to 3.7×10(10) cm(-2) in DMF-treated NWs, leading to a dramatic hysteresis reduction in NW field-effect transistors (FETs) from up to 32 V to a near-zero hysteresis. The change of the polyphenylsilane NW shell stoichiometric composition was confirmed by X-ray photoelectron spectroscopy analysis showing a 35% increase in fully oxidized Si4+ species for DMF-treated NWs compared to dry NW powder. Additionally, a shell oxidation effect induced by DMF resulted is a more stable NW FET performance with steady transistor currents and only 1.5 V hysteresis after 1000 h of air exposure.

  1. Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

    Science.gov (United States)

    Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

    2016-08-23

    We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

  2. NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors with high-k Al(2)O(3) gate layers.

    Science.gov (United States)

    Yeom, Donghyuk; Keem, Kihyun; Kang, Jeongmin; Jeong, Dong-Young; Yoon, Changjoon; Kim, Dongseung; Kim, Sangsig

    2008-07-02

    Electrical characteristics of NOT and NAND logic circuits fabricated using top-gate ZnO nanowire field-effect transistors (FETs) with high-k Al(2)O(3) gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whose I(on)/I(off) ratios were as high as ∼10(8) were connected in series in a single ZnO nanowire channel, sharing a common source electrode. Its voltage transfer characteristics exhibited an inverting operation and its logic swing was 98%. In addition, the characteristics of a NAND logic circuit composed of three top-gate FETs connected in series in a single nanowire channel are discussed in this paper.

  3. Investigation on phonon scattering in a GaAs nanowire field effect transistor using the non-equilibrium Green's function formalism

    Energy Technology Data Exchange (ETDEWEB)

    Price, A., E-mail: A.C.PRICE.625036@swansea.ac.uk; Martinez, A. [College of Engineering, Swansea University, Swansea (United Kingdom)

    2015-04-28

    Using quantum transport simulations, the impact of electron-phonon scattering on the transfer characteristic of a gate-all-around nanowire (GaAs) field effect transistor (NWFET) has been thoroughly investigated. The Non-Equilibrium Green's Function formalism in the effective mass approximation using a decoupled mode decomposition has been deployed. NWFETs of different dimensions have been considered, and scattering mechanisms including acoustic, optical and polar optical phonons have been included. The effective masses were extracted from tight binding simulations. High and low drain bias have been considered. We found substantial source to drain tunnelling current and significant impact of phonon scattering on the performance of the NWFET. At low drain bias, for a 2.2 × 2.2 nm{sup 2} cross-section transistor, scattering caused a 72%, 77%, and 81% decrease in the on-current for a 6 nm, 10 nm, and 20 nm channel length, respectively. This reduction in the current due to scattering is influenced by the increase in the tunnelling current. We include the percentage tunnelling for each valley at low and high drain bias. It was also found that the strong quantisation caused the relative position of the valleys to vary with the cross-section. This had a large effect on the overall tunnelling current. The phonon-limited mobility was also calculated, finding a mobility of 950 cm{sup 2}/V s at an inversion charge density of 10{sup 12 }cm{sup −2} for a 4.2 × 4.2 nm{sup 2} cross-section device.

  4. Dopant-Free GaN/AlN/AlGaN Radial Nanowire Heterostructures as High Electron Mobility Transistors

    Science.gov (United States)

    2016-06-07

    heterostructures. In summary, we have synthesized dislocation-free single- crystal GaN/AlN/Al0 25Ga0 75N nanowire heterostructures with well-controlled...were synthesized on a c-plane Al2O3 substrate in a MOCVD reactor (Thomas Swan Scientific Equipment Ltd.) using trimethylgallium, trimethylaluminium...and ammonia as Ga, Al, and N sources, respectively. We deposited 0.01 M nickel nitrate solution as the nickel nanocluster precursor. GaN cores were

  5. Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors

    Science.gov (United States)

    Gupta, Manish; Kranti, Abhinav

    2016-11-01

    In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade‑1) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.

  6. Isolation and Identification of Post-Transcriptional Gene Silencing-Related Micro-RNAs by Functionalized Silicon Nanowire Field-effect Transistor

    Science.gov (United States)

    Chen, Kuan-I.; Pan, Chien-Yuan; Li, Keng-Hui; Huang, Ying-Chih; Lu, Chia-Wei; Tang, Chuan-Yi; Su, Ya-Wen; Tseng, Ling-Wei; Tseng, Kun-Chang; Lin, Chi-Yun; Chen, Chii-Dong; Lin, Shih-Shun; Chen, Yit-Tsong

    2015-11-01

    Many transcribed RNAs are non-coding RNAs, including microRNAs (miRNAs), which bind to complementary sequences on messenger RNAs to regulate the translation efficacy. Therefore, identifying the miRNAs expressed in cells/organisms aids in understanding genetic control in cells/organisms. In this report, we determined the binding of oligonucleotides to a receptor-modified silicon nanowire field-effect transistor (SiNW-FET) by monitoring the changes in conductance of the SiNW-FET. We first modified a SiNW-FET with a DNA probe to directly and selectively detect the complementary miRNA in cell lysates. This SiNW-FET device has 7-fold higher sensitivity than reverse transcription-quantitative polymerase chain reaction in detecting the corresponding miRNA. Next, we anchored viral p19 proteins, which bind the double-strand small RNAs (ds-sRNAs), on the SiNW-FET. By perfusing the device with synthesized ds-sRNAs of different pairing statuses, the dissociation constants revealed that the nucleotides at the 3‧-overhangs and pairings at the terminus are important for the interactions. After perfusing the total RNA mixture extracted from Nicotiana benthamiana across the device, this device could enrich the ds-sRNAs for sequence analysis. Finally, this bionanoelectronic SiNW-FET, which is able to isolate and identify the interacting protein-RNA, adds an additional tool in genomic technology for the future study of direct biomolecular interactions.

  7. Nanowire Lasers

    Science.gov (United States)

    Couteau, C.; Larrue, A.; Wilhelm, C.; Soci, C.

    2015-05-01

    We review principles and trends in the use of semiconductor nanowires as gain media for stimulated emission and lasing. Semiconductor nanowires have recently been widely studied for use in integrated optoelectronic devices, such as light-emitting diodes (LEDs), solar cells, and transistors. Intensive research has also been conducted in the use of nanowires for subwavelength laser systems that take advantage of their quasione- dimensional (1D) nature, flexibility in material choice and combination, and intrinsic optoelectronic properties. First, we provide an overview on using quasi-1D nanowire systems to realize subwavelength lasers with efficient, directional, and low-threshold emission. We then describe the state of the art for nanowire lasers in terms of materials, geometry, andwavelength tunability.Next,we present the basics of lasing in semiconductor nanowires, define the key parameters for stimulated emission, and introduce the properties of nanowires. We then review advanced nanowire laser designs from the literature. Finally, we present interesting perspectives for low-threshold nanoscale light sources and optical interconnects. We intend to illustrate the potential of nanolasers inmany applications, such as nanophotonic devices that integrate electronics and photonics for next-generation optoelectronic devices. For instance, these building blocks for nanoscale photonics can be used for data storage and biomedical applications when coupled to on-chip characterization tools. These nanoscale monochromatic laser light sources promise breakthroughs in nanophotonics, as they can operate at room temperature, can potentially be electrically driven, and can yield a better understanding of intrinsic nanomaterial properties and surface-state effects in lowdimensional semiconductor systems.

  8. Nanowire Lasers

    Directory of Open Access Journals (Sweden)

    Couteau C.

    2015-05-01

    Full Text Available We review principles and trends in the use of semiconductor nanowires as gain media for stimulated emission and lasing. Semiconductor nanowires have recently been widely studied for use in integrated optoelectronic devices, such as light-emitting diodes (LEDs, solar cells, and transistors. Intensive research has also been conducted in the use of nanowires for subwavelength laser systems that take advantage of their quasione- dimensional (1D nature, flexibility in material choice and combination, and intrinsic optoelectronic properties. First, we provide an overview on using quasi-1D nanowire systems to realize subwavelength lasers with efficient, directional, and low-threshold emission. We then describe the state of the art for nanowire lasers in terms of materials, geometry, andwavelength tunability.Next,we present the basics of lasing in semiconductor nanowires, define the key parameters for stimulated emission, and introduce the properties of nanowires. We then review advanced nanowire laser designs from the literature. Finally, we present interesting perspectives for low-threshold nanoscale light sources and optical interconnects. We intend to illustrate the potential of nanolasers inmany applications, such as nanophotonic devices that integrate electronics and photonics for next-generation optoelectronic devices. For instance, these building blocks for nanoscale photonics can be used for data storage and biomedical applications when coupled to on-chip characterization tools. These nanoscale monochromatic laser light sources promise breakthroughs in nanophotonics, as they can operate at room temperature, can potentially be electrically driven, and can yield a better understanding of intrinsic nanomaterial properties and surface-state effects in lowdimensional semiconductor systems.

  9. Analytical Modeling of Electric Field Distribution in Dual Material Junctionless Surrounding Gate MOSFETs

    Directory of Open Access Journals (Sweden)

    P. Suveetha Dhanaselvam

    2014-10-01

    Full Text Available In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs (JLDMSG is developed. Junctionless is a device that has similar characteristics like junction based devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short channel effects effectively than other devices. In this paper, surface potential and electric field distribution is modelled. The proposed surface potential model is compared with the existing central potential model. It is observed that the short channel effects (SCE is reduced and the performance is better than the existing method.

  10. Light-matter interactions in semiconductor nanowires: Light-effect transistor and light-induced changes in electron-phonon coupling and electrical characteristics

    Science.gov (United States)

    Marmon, Jason Kendrick

    This dissertation explores three related embodiments of light-matter interactions at the micro- and nano-scales, and is focused towards tangible device applications. The first topic provides a fundamentally different transistor or electronic switch mechanism, which is termed a light-effect transistor (LET). The LET, unlike exotic techniques, provides a practical and viable approach using existing fabrication processes. Electronic devices at the nanoscale operate within the ballistic regime, where the dominate source of energy loss comes from impurity scattering. As a LET does not require extrinsic doping, it circumvents this issue. Electron-phonon coupling, however, is the second largest source, and it is a pertinent and important parameter affecting electronic conductivity and energy efficiency, such as in LETs. The third topic is laser writing, or the use of a laser to perform post-growth modifications, to achieve specific optical and electrical characteristics. A LET offers electronic-optical hybridization at the component level, which can continue Moore's law to the quantum region without requiring a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily utilized to achieve unique functionalities without increasing chip space. LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification, are explored. Prototype cadmium selenide (CdSe) nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 1.0x10 6 with a source-drain voltage of 1.43 V, gate-power of 260 nW, and a subthreshold swing of 0.3 nW/decade (excluding losses). The LET platform offers new electronic-optical integration strategies and high speed and low energy electronic and optical computing approaches. Electron-phonon coupling is typically studied as an intrinsic property, which

  11. Integrating silicon nanowire field effect transistor, microfluidics and air sampling techniques for real-time monitoring biological aerosols.

    Science.gov (United States)

    Shen, Fangxia; Tan, Miaomiao; Wang, Zhenxing; Yao, Maosheng; Xu, Zhenqiang; Wu, Yan; Wang, Jindong; Guo, Xuefeng; Zhu, Tong

    2011-09-01

    Numerous threats from biological aerosol exposures, such as those from H1N1 influenza, SARS, bird flu, and bioterrorism activities necessitate the development of a real-time bioaerosol sensing system, which however is a long-standing challenge in the field. Here, we developed a real-time monitoring system for airborne influenza H3N2 viruses by integrating electronically addressable silicon nanowire (SiNW) sensor devices, microfluidics and bioaerosol-to-hydrosol air sampling techniques. When airborne influenza H3N2 virus samples were collected and delivered to antibody-modified SiNW devices, discrete nanowire conductance changes were observed within seconds. In contrast, the conductance levels remained relatively unchanged when indoor air or clean air samples were delivered. A 10-fold increase in virus concentration was found to give rise to about 20-30% increase in the sensor response. The selectivity of the sensing device was successfully demonstrated using H1N1 viruses and house dust allergens. From the simulated aerosol release to the detection, we observed a time scale of 1-2 min. Quantitative polymerase chain reaction (qPCR) tests revealed that higher virus concentrations in the air samples generally corresponded to higher conductance levels in the SiNW devices. In addition, the display of detection data on remote platforms such as cell phone and computer was also successfully demonstrated with a wireless module. The work here is expected to lead to innovative methods for biological aerosol monitoring, and further improvements in each of the integrated elements could extend the system to real world applications.

  12. Advances in nanowire bioelectronics

    Science.gov (United States)

    Zhou, Wei; Dai, Xiaochuan; Lieber, Charles M.

    2017-01-01

    Semiconductor nanowires represent powerful building blocks for next generation bioelectronics given their attractive properties, including nanometer-scale footprint comparable to subcellular structures and bio-molecules, configurable in nonstandard device geometries readily interfaced with biological systems, high surface-to-volume ratios, fast signal responses, and minimum consumption of energy. In this review article, we summarize recent progress in the field of nanowire bioelectronics with a focus primarily on silicon nanowire field-effect transistor biosensors. First, the synthesis and assembly of semiconductor nanowires will be described, including the basics of nanowire FETs crucial to their configuration as biosensors. Second, we will introduce and review recent results in nanowire bioelectronics for biomedical applications ranging from label-free sensing of biomolecules, to extracellular and intracellular electrophysiological recording.

  13. Analytic Circuit Model of Ballistic Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor for Transient Analysis

    Science.gov (United States)

    Numata, Tatsuhiro; Uno, Shigeyasu; Kamakura, Yoshinari; Mori, Nobuya; Nakazato, Kazuo

    2013-04-01

    A fully analytic and explicit model of device properties in the ballistic transport in gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed, which enables circuit simulations. The electrostatic potential distribution in the wire cross section is approximated by a parabolic function. Using the applied potential, the energy levels of electrons are analytically obtained in terms of a single unknown parameter by perturbation theory. Ballistic current is obtained in terms of an unknown parameter using the analytic expression of the electron energy level and the current equation for ballistic transport. We analytically derive the parameter with a one-of-a-kind approximate methodology. With the obtained parameter, the fully analytic and explicit model of device properties such as energy levels, ballistic current, and effective capacitance is derived with satisfactory accuracy compared with the numerical simulation results. Finally, we perform a transient simulation using a circuit simulator, introducing our model to it as a Verilog-A script.

  14. SYNTHESIS OF COPPER NANOWIRES

    OpenAIRE

    POLAT, Sevim; Tigan, Doğancan

    2015-01-01

    Nanotechnology is the science and engineering of functional systems conducted at nanoscale that is between 1 and 100 nanometers. In the past years, it has been demonstrated that nanowires can be used in many areas, increasing their popularity. These areas primarily include ap-plications related to energy, environment and electronics. In these applications, many prototype products have been demonstrated with nan-owires, such as solar cells, flexible displays, transistors and light emitting dio...

  15. Performance analysis of junctionless double gate VeSFET considering the effects of thermal variation - An explicit 2D analytical model

    Science.gov (United States)

    Chaudhary, Tarun; Khanna, Gargi

    2017-03-01

    The purpose of this paper is to explore junctionless double gate vertical slit field effect transistor (JLDG VeSFET) with reduced short channel effects and to develop an analytical threshold voltage model for the device considering the impact of thermal variations for the very first time. The model has been derived by solving 2D Poisson's equation and the effects of variation in temperature on various electrical parameters of the device such as Rout, drain current, mobility, subthreshold slope and DIBL has been studied and described in the paper. The model provides a deep physical insight of the device behavior and is also very helpful in contributing to the design space exploration for JLDG VeSFET. The proposed model is verified with simulative analysis at different radii of the device and it has been observed that there is a good agreement between the analytical model and simulation results.

  16. 3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY

    KAUST Repository

    Fahad, Hossain M.

    2014-03-01

    scaling on silicon, the amount of current generated per device has to be increased while keeping short channel effects and off-state leakage at bay. The objective of this doctoral thesis is the investigation of an innovative vertical silicon based architecture called the silicon nanotube field effect transistor (Si NTFET). This topology incorporates a dual inner/outer core/shell gate stack strategy to control the volume inversion properties in a hollow silicon 1D quasi-nanotube under a tight electrostatic configuration. Together with vertically aligned source and drain, the Si NTFET is capable of very high on-state performance (drive current) in an area-efficient configuration as opposed to arrays of gate-all-around nanowires, while maintaining leakage characteristics similar to a single nanowire. Such a device architecture offsets the need of device arraying that is needed with fin and nanowire architectures. Extensive simulations are used to validate the potential benefits of Si NTFETs over GAA NWFETs on a variety of platforms such as conventional MOSFETs, tunnel FETs, junction-less FETs. This thesis demonstrates a novel CMOS compatible process flow to fabricate vertical nanotube transistors that offer a variety of advantages such as lithography-independent gate length definition, integration of epitaxially grown silicon nanotubes with spacer based gate dielectrics and abrupt in-situ doped source/drain junctions. Experimental measurement data will showcase the various materials and processing challenges in fabricating these devices. Finally, an extension of this work to topologically transformed wavy channel FinFETs is also demonstrated keeping in line with the theme of area efficient high-performance electronics.

  17. Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions

    Science.gov (United States)

    Chebaki, E.; Djeffal, F.; Ferhati, H.; Bentrcia, T.

    2016-04-01

    In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

  18. Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

    Institute of Scientific and Technical Information of China (English)

    Ngoc Huynh Van; Jae-Hyun Lee; Dongmok Whang; Dae Joon Kang

    2015-01-01

    A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)). We overcame the interfacial layer problem by incorporating P(VDF-TrFE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFF ratio higher than 102.

  19. 2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect Transistors and Their Application.

    Science.gov (United States)

    Zhang, Pengpeng; Mayer, Theresa S; Jackson, Thomas N

    2007-08-01

    Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

  20. Transparent p-type SnO nanowires with unprecedented hole mobility among oxide semiconductors

    KAUST Repository

    Caraveo-Frescas, J. A.

    2013-11-25

    p-type tin monoxide (SnO) nanowire field-effect transistors with stable enhancement mode behavior and record performance are demonstrated at 160 °C. The nanowire transistors exhibit the highest field-effect hole mobility (10.83 cm2 V−1 s−1) of any p-type oxide semiconductor processed at similar temperature. Compared to thin film transistors, the SnO nanowire transistors exhibit five times higher mobility and one order of magnitude lower subthreshold swing. The SnO nanowire transistors show three times lower threshold voltages (−1 V) than the best reported SnO thin film transistors and fifteen times smaller than p-type Cu 2O nanowire transistors. Gate dielectric and process temperature are critical to achieving such performance.

  1. Reconfigurable nanowire electronics - A review

    Science.gov (United States)

    Weber, W. M.; Heinzig, A.; Trommer, J.; Martin, D.; Grube, M.; Mikolajick, T.

    2014-12-01

    Reconfigurable nanowire transistors merge the electrical properties of unipolar n- and p-type FETs into a single type of device with identic technology, geometry and composition. These four-terminal nanowire transistors employ an electric signal to dynamically program unipolar n- or p-type behavior. More than reducing the technological complexity, they open up the possibility of dynamically programming the functions of circuits at the device level, i.e. enabling a fine-grain reconfiguration of complex functions. We will review different reconfigurable concepts, analyze the transport properties and finally assess their maturity for building circuits.

  2. A detailed coupled-mode-space non-equilibrium Green's function simulation study of source-to-drain tunnelling in gate-all-around Si nanowire metal oxide semiconductor field effect transistors

    Science.gov (United States)

    Seoane, N.; Martinez, A.

    2013-09-01

    In this paper we present a 3D quantum transport simulation study of source-to-drain tunnelling in gate-all-around Si nanowire transistors by using the non-equilibrium Green's function approach. The impact of the channel length, device cross-section, and drain and gate applied biases on the source-to-drain tunnelling is examined in detail. The overall effect of tunnelling on the ID-VG characteristics is also investigated. Tunnelling in devices with channel lengths of 10 nm or less substantially enhances the off-current. This enhancement is more important at high drain biases and at larger cross-sections where the sub-threshold slope is substantially degraded. A less common effect is the increase in the on-current due to the tunnelling which contributes as much as 30% of the total on-current. This effect is almost independent of the cross-section, and it depends weakly on the studied channel lengths.

  3. Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Ajayan, J.

    2016-09-01

    This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

  4. Transport characterization in nanowires using an electrical nanoprobe

    Science.gov (United States)

    Talin, A. A.; Léonard, F.; Katzenmeyer, A. M.; Swartzentruber, B. S.; Picraux, S. T.; Toimil-Molares, M. E.; Cederberg, J. G.; Wang, X.; Hersee, S. D.; Rishinaramangalum, A.

    2010-02-01

    Electrical transport in semiconductor nanowires is commonly measured in a field effect transistor configuration, with lithographically defined source, drain and in some cases, top gate electrodes. This approach is labor intensive, requires high-end fabrication equipment, exposes the nanowires to extensive processing chemistry and places practical limitations on minimum nanowire length. Here we describe an alternative, simple method for characterizing electrical transport in nanowires directly on the growth substrate, without any need for post growth processing. Our technique is based on contacting nanowires using a nano-manipulator probe retrofitted inside of a scanning electron microscope. Using this approach, we characterize electrical transport in GaN nanowires grown by catalyst-free selective epitaxy, as well as InAs and Ge nanowires grown by a Au-catalyzed vapor solid liquid technique. We find that in situations where contacts are not limiting carrier injection (GaN and InAs nanowires), electrical transport transitions from Ohmic conduction at low bias to space-charge-limited conduction at higher bias. Using this transition and a theory of space-charge-limited transport which accounts for the high aspect ratio nanowires, we extract the mobility and the free carrier concentration. For Ge nanowires, we find that the Au catalyst forms a Schottky contact resulting in rectifying current-voltage characteristics, which are strongly dependent on the nanowire diameter. This dependence arises due to an increase in depletion width at decreased nanowire diameter and carrier recombination at the nanowire surface.

  5. Transistor Effect in Improperly Connected Transistors.

    Science.gov (United States)

    Luzader, Stephen; Sanchez-Velasco, Eduardo

    1996-01-01

    Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

  6. Studies of photoconductivity and field effect transistor behavior in examining drift mobility, surface depletion, and transient effects in Si-doped GaN nanowires in vacuum and air

    Energy Technology Data Exchange (ETDEWEB)

    Sanford, N. A.; Robins, L. H.; Blanchard, P. T.; Bertness, K. A.; Schlager, J. B.; Sanders, A. W. [NIST, Physical Measurement Laboratory, Division 686, 325 Broadway, Boulder, Colorado 80305 (United States); Soria, K.; Klein, B. [School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332 (United States); Eller, B. S. [Department of Physics, Arizona State University, Tempe, Arizona 85287 (United States)

    2013-05-07

    Variable intensity photoconductivity (PC) performed under vacuum at 325 nm was used to estimate drift mobility ({mu}) and density ({sigma}{sub s}) of negative surface charge for c-axis oriented Si-doped GaN nanowires (NWs). In this approach, we assumed that {sigma}{sub s} was responsible for the equilibrium surface band bending ( Empty-Set ) and surface depletion in the absence of illumination. The NWs were grown by molecular beam epitaxy to a length of approximately 10 {mu}m and exhibited negligible taper. The free carrier concentration (N) was separately measured using Raman scattering which yielded N = (2.5 {+-} 0.3) Multiplication-Sign 10{sup 17} cm{sup -3} for the growth batch studied under 325 nm excitation. Saturation of the PC was interpreted as a flatband condition whereby Empty-Set was eliminated via the injection of photogenerated holes. Measurements of dark and saturated photocurrents, N, NW dimensions, and dimensional uncertainties, were used as input to a temperature-dependent cylindrical Poisson equation based model, yielding {sigma}{sub s} in the range of (3.5 to 7.5) Multiplication-Sign 10{sup 11} cm{sup -2} and {mu} in the range of (850 to 2100) cm{sup 2}/(V s) across the (75 to 194) nm span of individual NW diameters examined. Data illustrating the spectral dependence and polarization dependence of the PC are also presented. Back-gating these devices, and devices from other growth batches, as field effect transistors (FETs) was found to not be a reliable means to estimate transport parameters (e.g., {mu} and {sigma}{sub s}) due to long-term current drift. The current drift was ascribed to screening of the FET back gate by injected positive charge. We describe how these gate charging effects can be exploited as a means to hasten the otherwise long recovery time of NW devices used as photoconductive detectors. Additionally, we present data illustrating comparative drift effects under vacuum, room air, and dry air for both back-gated NW FETs and top

  7. Semiconductor nanowires and templates for electronic applications

    Energy Technology Data Exchange (ETDEWEB)

    Ying, Xiang

    2009-07-15

    catalyzed germanium nanowires, a small process window has been determined where high aspect-ratio nanowires show single crystalline structure. Compositional analysis has been performed via electron energy loss spectroscopy (EELS) to monitor the presence of indium and bismuth in the nanowires. Both catalysts could be identified, validating their role as catalysts. A combined atomic force microscopy (AFM) and Raman spectroscopy characterization on single core-shell nanowires gives clear evidence of finite-size effects on the electron-phonon coupling, as well as the presence of strain. Field effect transistors were fabricated using gold, bismuth and indium catalyzed germanium nanowires. Initial room-temperature and temperature dependent transport measurements on gold and bismuth catalyzed nanowires show field effects. Indium catalyzed germanium nanowires show insulating behavior. (orig.)

  8. Organic Nanowires

    DEFF Research Database (Denmark)

    Balzer, Frank; Schiek, Manuela; Al-Shamery, Katharina;

    Single crystalline nanowires from fluorescing organic molecules like para-phenylenes or thiophenes are supposed to become key elements in future integrated optoelectronic devices [1]. For a sophisticated design of devices based on nanowires the basic principles of the nanowire formation have...

  9. Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

    Science.gov (United States)

    Trivedi, Nitin; Kumar, Manoj; Haldar, Subhasis; Deswal, S. S.; Gupta, Mridula; Gupta, R. S.

    2017-09-01

    A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/ I OFF ratio.

  10. Assembly of Ultra-Dense Nanowire-Based Computing Systems

    Science.gov (United States)

    2006-06-30

    TERMS nanowire;core/shell nanowire heterostructures; nonvolatile diode switch; nanowire/ ferroelectric heterostructures; nonvolatile nanowire transistor...scattering. To define the potential of Ge/Si NW heterostructures as high-performance FETs we have fabricated devices using thin HfO2 and ZrO2 high-K...for device B (L= 190 nm, 4 nm HfO2 dielectric) with blue, red and green data points corresponding to Vds values of -1, -0.1 and -0.01 V, respectively

  11. Failure mechanisms and electromechanical coupling in semiconducting nanowires

    Directory of Open Access Journals (Sweden)

    Peng B.

    2010-06-01

    Full Text Available One dimensional nanostructures, like nanowires and nanotubes, are increasingly being researched for the development of next generation devices like logic gates, transistors, and solar cells. In particular, semiconducting nanowires with a nonsymmetric wurtzitic crystal structure, such as zinc oxide (ZnO and gallium nitride (GaN, have drawn immense research interests due to their electromechanical coupling. The designing of the future nanowire-based devices requires component-level characterization of individual nanowires. In this paper, we present a unique experimental set-up to characterize the mechanical and electromechanical behaviour of individual nanowires. Using this set-up and complementary atomistic simulations, mechanical properties of ZnO nanowires and electromechanical properties of GaN nanowires were investigated. In ZnO nanowires, elastic modulus was found to depend on nanowire diameter decreasing from 190 GPa to 140 GPa as the wire diameter increased from 5 nm to 80 nm. Inconsistent failure mechanisms were observed in ZnO nanowires. Experiments revealed a brittle fracture, whereas simulations using a pairwise potential predicted a phase transformation prior to failure. This inconsistency is addressed in detail from an experimental as well as computational perspective. Lastly, in addition to mechanical properties, preliminary results on the electromechanical properties of gallium nitride nanowires are also reported. Initial investigations reveal that the piezoresistive and piezoelectric behaviour of nanowires is different from bulk gallium nitride.

  12. A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

    Science.gov (United States)

    Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

    2015-05-01

    A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson's equation is solved in channel region by a method of series expansion similar to Green's function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

  13. Realization of Silicon nanotube tunneling FET on junctionless structure using single and multiple gate workfunction

    Science.gov (United States)

    Ambika, R.; Keerthana, N.; Srinivasan, R.

    2017-01-01

    In this paper, we demonstrate the operation of a Silicon Nanotube Tunneling FET on junctionless structure using 3D numerical simulations. P-I-N band structure thereby the tunneling operation is achieved by placing side gates and applying appropriate side gate biases. Single work function, with the same main and side gates workfunctions and multiple workfunction, with different main and side gates workfunctions are explored to achieve Tunneling FET. ON current, OFF current, Sub-threshold swing, Threshold voltage, trans-conductance and unity gain frequency are extracted for both single and multiple gate workfunctions based devices and compared with the conventional Silicon nanotube tunnel FET. For the same OFF current, the proposed devices show better performance with respect to ON current and sub-threshold swing compared to the conventional Silicon nano tube tunnel FET.

  14. Superconducting transistor

    Science.gov (United States)

    Gray, Kenneth E.

    1979-01-01

    A superconducting transistor is formed by disposing three thin films of superconducting material in a planar parallel arrangement and insulating the films from each other by layers of insulating oxides to form two tunnel junctions. One junction is biased above twice the superconducting energy gap and the other is biased at less than twice the superconducting energy gap. Injection of quasiparticles into the center film by one junction provides a current gain in the second junction.

  15. Bulk-quantity synthesis and electrical properties of SnO{sub 2} nanowires prepared by pulsed delivery

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Z.W., E-mail: cnzwchen@yahoo.com.cn [Shanghai Applied Radiation Institute, Institute of Nanochemistry and Nanobiology, School of Environmental and Chemical Engineering, Shanghai University, Shanghai 200444 (China); Department of Physics and Materials Science, City University of Hong Kong, Tat Chee Avenue, Kowloon Tong (Hong Kong); Jiao, Z. [Shanghai Applied Radiation Institute, Institute of Nanochemistry and Nanobiology, School of Environmental and Chemical Engineering, Shanghai University, Shanghai 200444 (China); Wu, M.H., E-mail: mhwu@staff.shu.edu.cn [Shanghai Applied Radiation Institute, Institute of Nanochemistry and Nanobiology, School of Environmental and Chemical Engineering, Shanghai University, Shanghai 200444 (China); Shek, C.H.; Wu, C.M.L.; Lai, J.K.L. [Department of Physics and Materials Science, City University of Hong Kong, Tat Chee Avenue, Kowloon Tong (Hong Kong)

    2009-06-15

    Tin dioxide nanowires have been realized via pulsed laser deposition techniques based on a sintered cassiterite SnO{sub 2} target, being deposited on Si (1 0 0) substrates at room temperature. X-ray diffraction indicated that the nanowires show the tetragonal rutile structure in the form of SnO{sub 2}. Transmission electron microscopy revealed that the nanowires are structurally perfect and uniform, and diameters range from 10 nm to 30 nm, and lengths of several hundreds nanometers to a few micrometers. Selected area electron diffraction and high-resolution transmission electron microscopy verified that the nanowires grow along the [1 1 0] growth direction. Electric properties were investigated by connecting a single SnO{sub 2} nanowire in field-effect transistor configuration. The SnO{sub 2} nanowires based on field-effect transistor devices exhibited that the SnO{sub 2} nanowires prepared by our method hold better electrical properties.

  16. Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

    Science.gov (United States)

    Chatterjee, Sulagna; Chattopadhyay, Sanatan

    2016-10-01

    An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

  17. Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes

    Science.gov (United States)

    Huang, Wen-Hsien; Shieh, Jia-Min; Shen, Chang-Hong; Huang, Tzu-En; Wang, Hsing-Hsiang; Yang, Chih-Chao; Hsieh, Tung-Ying; Hsieh, Jin-Long; Yeh, Wen-Kuan

    2016-06-01

    A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 × 1018 cm-3 and high crystallinity (Raman FWHM ˜ 4.54 cm-1). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an Ion/Ioff ratio over 105 and drain-induced barrier lowering of 168 mV/V. Moreover, the fast programming speed of 100 μs-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics.

  18. Magnetic bipolar transistor

    OpenAIRE

    Fabian, Jaroslav; Zutic, Igor; Sarma, S. Das

    2003-01-01

    A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin. It is shown that electrical spin injection through the transistor is possible in the forward active regime. It is predicted that the current amplification of the transistor can be tuned by spin.

  19. Tunneling and Transport in Nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Goldman, Allen M. [Univ. of Minnesota, Minneapolis, MN (United States)

    2016-08-16

    The goal of this program was to study new physical phenomena that might be relevant to the performance of conductive devices and circuits of the smallest realizable feature sizes possible using physical rather than biological techniques. Although the initial scientific work supported involved the use of scanning tunneling microscopy and spectroscopy to ascertain the statistics of the energy level distribution of randomly sized and randomly shaped quantum dots, or nano-crystals, the main focus was on the investigation of selected properties, including superconductivity, of conducting and superconducting nanowires prepared using electron-beam-lithography. We discovered a magnetic-field-restoration of superconductivity in out-of-equilibrium nanowires driven resistive by current. This phenomenon was explained by the existence of a state in which dissipation coexisted with nonvanishing superconducting order. We also produced ultra-small superconducting loops to study a predicted anomalous fluxoid quantization, but instead, found a magnetic-field-dependent, high-resistance state, rather than superconductivity. Finally, we developed a simple and controllable nanowire in an induced charged layer near the surface of a masked single-crystal insulator, SrTiO3. The layer was induced using an electric double layer transistor employing an ionic liquid (IL). The transport properties of the induced nanowire resembled those of collective electronic transport through an array of quantum dots.

  20. Tunneling and Transport in Nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Goldman, Allen M. [Univ. of Minnesota, Minneapolis, MN (United States)

    2016-08-16

    The goal of this program was to study new physical phenomena that might be relevant to the performance of conductive devices and circuits of the smallest realizable feature sizes possible using physical rather than biological techniques. Although the initial scientific work supported involved the use of scanning tunneling microscopy and spectroscopy to ascertain the statistics of the energy level distribution of randomly sized and randomly shaped quantum dots, or nano-crystals, the main focus was on the investigation of selected properties, including superconductivity, of conducting and superconducting nanowires prepared using electron-beam-lithography. We discovered a magnetic-field-restoration of superconductivity in out-of-equilibrium nanowires driven resistive by current. This phenomenon was explained by the existence of a state in which dissipation coexisted with nonvanishing superconducting order. We also produced ultra-small superconducting loops to study a predicted anomalous fluxoid quantization, but instead, found a magnetic-field-dependent, high-resistance state, rather than superconductivity. Finally, we developed a simple and controllable nanowire in an induced charged layer near the surface of a masked single-crystal insulator, SrTiO3. The layer was induced using an electric double layer transistor employing an ionic liquid (IL). The transport properties of the induced nanowire resembled those of collective electronic transport through an array of quantum dots.

  1. Nanowire photonics

    Directory of Open Access Journals (Sweden)

    Peter J. Pauzauskie

    2006-10-01

    Full Text Available The development of integrated electronic circuitry ranks among the most disruptive and transformative technologies of the 20th century. Even though integrated circuits are ubiquitous in modern life, both fundamental and technical constraints will eventually test the limits of Moore's law. Nanowire photonic circuitry constructed from myriad one-dimensional building blocks offers numerous opportunities for the development of next-generation optical information processors and spectroscopy. However, several challenges remain before the potential of nanowire building blocks is fully realized. We cover recent advances in nanowire synthesis, characterization, lasing, integration, and the eventual application to relevant technical and scientific questions.

  2. Ballistic Phosphorene Transistor

    Science.gov (United States)

    2015-11-19

    contact metals to change transistor characteristics. Through studying transistor behaviors with various channel lengths, the contact resistance can be...Thus, phosphorene can potentially overcome the challenges of all other 2D materials for ultra-scaled thin-body low-power transistor applications thereby...field-effect transistors (FETs), and discuss a scheme for using various contact metals to change transistor characteristics. Through studying

  3. Super-Joule heating in graphene and silver nanowire network

    Energy Technology Data Exchange (ETDEWEB)

    Maize, Kerry [Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Das, Suprem R.; Sadeque, Sajia; Mohammed, Amr M. S.; Shakouri, Ali, E-mail: shakouri@purdue.edu, E-mail: alam@purdue.edu; Janes, David B.; Alam, Muhammad A., E-mail: shakouri@purdue.edu, E-mail: alam@purdue.edu [Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907 (United States)

    2015-04-06

    Transistors, sensors, and transparent conductors based on randomly assembled nanowire networks rely on multi-component percolation for unique and distinctive applications in flexible electronics, biochemical sensing, and solar cells. While conduction models for 1-D and 1-D/2-D networks have been developed, typically assuming linear electronic transport and self-heating, the model has not been validated by direct high-resolution characterization of coupled electronic pathways and thermal response. In this letter, we show the occurrence of nonlinear “super-Joule” self-heating at the transport bottlenecks in networks of silver nanowires and silver nanowire/single layer graphene hybrid using high resolution thermoreflectance (TR) imaging. TR images at the microscopic self-heating hotspots within nanowire network and nanowire/graphene hybrid network devices with submicron spatial resolution are used to infer electrical current pathways. The results encourage a fundamental reevaluation of transport models for network-based percolating conductors.

  4. Towards high mobility InSb nanowire devices

    Science.gov (United States)

    Gül, Önder; van Woerkom, David J.; van Weperen, Ilse; Car, Diana; Plissard, Sébastien R.; Bakkers, Erik P. A. M.; Kouwenhoven, Leo P.

    2015-05-01

    We study the low-temperature electron mobility of InSb nanowires. We extract the mobility at 4.2 K by means of field effect transport measurements using a model consisting of a nanowire-transistor with contact resistances. This model enables an accurate extraction of device parameters, thereby allowing for a systematic study of the nanowire mobility. We identify factors affecting the mobility, and after optimization obtain a field effect mobility of ˜ 2.5× {{10}4} cm2 V-1 s-1. We further demonstrate the reproducibility of these mobility values which are among the highest reported for nanowires. Our investigations indicate that the mobility is currently limited by adsorption of molecules to the nanowire surface and/or the substrate.

  5. Tri-gate InGaAs-OI junctionless FETs with PE-ALD Al2O3 gate dielectric and H2/Ar anneal

    Science.gov (United States)

    Djara, Vladimir; Czornomaz, Lukas; Deshpande, Veeresh; Daix, Nicolas; Uccelli, Emanuele; Caimi, Daniele; Sousa, Marilyne; Fompeyrine, Jean

    2016-01-01

    We present a tri-gate In0.53Ga0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n-In0.53Ga0.47As channel doped to 1018/cm3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2O3 presents a bandgap of 7.0 eV, a k-value of 8.1 and a breakdown field of 8-10.5 MV/cm. A post-fabrication H2/Ar anneal applied to the PE-ALD Al2O3/In0.53Ga0.47As-OI gate stack yielded a low density of interface traps (Dit) of 7 × 1011/cm2 eV at Ec - E = -0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2O3/HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53Ga0.47As. The H2/Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2/Ar anneal, the long-channel (10 μm) device featured a threshold voltage (VT) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III-V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2/Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.

  6. Fabrication of reliable semiconductor nanowires by controlling crystalline structure.

    Science.gov (United States)

    Kim, Sangdan; Lim, Taekyung; Ju, Sanghyun

    2011-07-29

    One-dimensional SnO(2) nanomaterials with wide bandgap characteristics are attractive for flexible and/or transparent displays and high-performance nano-electronics. In this study, the crystallinity of SnO(2) nanowires was regulated by controlling their growth temperatures. Moreover, the correlation of the crystallinity of nanowires with optical and electrical characteristics was analyzed. When SnO(2) nanowires were grown at temperatures below 900 °C, they showed various growth directions and abnormal discontinuity in their crystal structures. On the other hand, most nanowires grown at 950 °C exhibited a regular growth trend in the direction of [100]. In addition, the low temperature photoluminescence measurement revealed that the higher growth temperatures of nanowires gradually decreased the 500 nm peak rather than the 620 nm peak. The former peak is derived from the surface defect related to the shallow energy level and affects nanowire surface states. Owing to crystallinity and defects, the threshold voltage range (maximum-minimum) of SnO(2) nanowire transistors was 1.5 V at 850 °C, 1.1 V at 900 °C, and 0.5 V at 950 °C, with dispersion characteristics dramatically decreased. This study successfully demonstrated the effects of nanowire crystallinity on optical and electrical characteristics. It also suggested that the optical and electrical characteristics of nanowire transistors could be regulated by controlling their growth temperatures in the course of producing SnO(2) nanowires.

  7. SnO2Nanowire Arrays and Electrical Properties Synthesized by Fast Heating a Mixture of SnO2and CNTs Waste Soot

    Directory of Open Access Journals (Sweden)

    Zhou Zhi-Hua

    2009-01-01

    Full Text Available Abstract SnO2nanowire arrays were synthesized by fast heating a mixture of SnO2and the carbon nanotubes waste soot by high-frequency induction heating. The resultant SnO2nanowires possess diameters from 50 to 100 nm and lengths up to tens of mircrometers. The field-effect transistors based on single SnO2nanowire exhibit that as-synthesized nanowires have better transistor performance in terms of transconductance and on/off ratio. This work demonstrates a simple technique to the growth of nanomaterials for application in future nanoelectronic devices.

  8. Quantifying signal changes in nano-wire based biosensors

    DEFF Research Database (Denmark)

    De Vico, Luca; Sørensen, Martin Hedegård; Iversen, Lars

    2011-01-01

    In this work, we present a computational methodology for predicting the change in signal (conductance sensitivity) of a nano-BioFET sensor (a sensor based on a biomolecule binding another biomolecule attached to a nano-wire field effect transistor) upon binding its target molecule. The methodolog...

  9. Nanowires and nanobelts, v.2 nanowires and nanobelts of functional materials

    CERN Document Server

    Wang, Zhong Lin

    2010-01-01

    Nanowires, nanobelts, nanoribbons, nanorods ..., are a new class of quasi-one-dimensional materials that have been attracting a great research interest in the last few years. These non-carbon based materials have been demonstrated to exhibit superior electrical, optical, mechanical and thermal properties, and can be used as fundamental building blocks for nano-scale science and technology, ranging from chemical and biological sensors, field effect transistors to logic circuits. Nanocircuits built using semiconductor nanowires demonstrated were declared a ""breakthrough in science"" by Science

  10. STABILIZED TRANSISTOR AMPLIFIER

    Science.gov (United States)

    Noe, J.B.

    1963-05-01

    A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

  11. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    Science.gov (United States)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  12. Zapping thin film transistors

    NARCIS (Netherlands)

    Golo-Tosic, N.; Kuper, F.G.; Mouthaan, A.J.

    2002-01-01

    It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD

  13. Compact Nanowire Sensors Probe Microdroplets.

    Science.gov (United States)

    Schütt, Julian; Ibarlucea, Bergoi; Illing, Rico; Zörgiebel, Felix; Pregl, Sebastian; Nozaki, Daijiro; Weber, Walter M; Mikolajick, Thomas; Baraban, Larysa; Cuniberti, Gianaurelio

    2016-08-10

    The conjunction of miniature nanosensors and droplet-based microfluidic systems conceptually opens a new route toward sensitive, optics-less analysis of biochemical processes with high throughput, where a single device can be employed for probing of thousands of independent reactors. Here we combine droplet microfluidics with the compact silicon nanowire based field effect transistor (SiNW FET) for in-flow electrical detection of aqueous droplets one by one. We chemically probe the content of numerous (∼10(4)) droplets as independent events and resolve the pH values and ionic strengths of the encapsulated solution, resulting in a change of the source-drain current ISD through the nanowires. Further, we discuss the specificities of emulsion sensing using ion sensitive FETs and study the effect of droplet sizes with respect to the sensor area, as well as its role on the ability to sense the interior of the aqueous reservoir. Finally, we demonstrate the capability of the novel droplets based nanowire platform for bioassay applications and carry out a glucose oxidase (GOx) enzymatic test for glucose detection, providing also the reference readout with an integrated parallel optical detector.

  14. Nanowires: properties, applications and synthesis via porous anodic aluminium oxide template

    Indian Academy of Sciences (India)

    Jaya Sarkar; Gobinda Gopal Khan; A Basumallick

    2007-06-01

    Quasi one-dimensional nanowires possess unique electrical, electronic, thermoelectrical, optical, magnetic and chemical properties, which are different from that of their parent counterpart. The physical properties of nanowires are influenced by the morphology of the nanowires, diameter dependent band gap, carrier density of states etc. Nanowires hold lot of promises for different applications. Basic electronic devices like junction diodes, transistors, FETs and logic gates can be fabricated by using semiconductor and superlattice nanowires. Thermoelectric cooling system can be fabricated by using metallic nanowires. Semiconductor nanowire junctions can be used for different opto-electronic applications. Moreover, periodic arrays of magnetic nanowires hold high potential for recording media application. Nanowires are also potential candidates for sensor and bio-medical applications. In the present article, the physical and chemical properties of nanowires along with their probable applications in different fields have been reviewed in detail. The review also includes highlights of the synthesis of nanowires via porous anodic aluminium oxide template since the technique is simple, cost-effective and a low temperature technique.

  15. Screening model for nanowire surface-charge sensors in liquid

    DEFF Research Database (Denmark)

    Sørensen, Martin Hedegård; Mortensen, Asger; Brandbyge, Mads

    2007-01-01

    The conductance change of nanowire field-effect transistors is considered a highly sensitive probe for surface charge. However, Debye screening of relevant physiological liquid environments challenge device performance due to competing screening from the ionic liquid and nanowire charge carriers......., and the length of the functionalization molecules. The analytical results are compared to finite-element calculations on a realistic geometry. ©2007 American Institute of Physics........ The authors discuss this effect within Thomas-Fermi and Debye-Hückel theory and derive analytical results for cylindrical wires which can be used to estimate the sensitivity of nanowire surface-charge sensors. They study the interplay between the nanowire radius, the Thomas-Fermi and Debye screening lengths...

  16. Large displacement of a static bending nanowire with surface effects

    Science.gov (United States)

    Liu, J. L.; Mei, Y.; Xia, R.; Zhu, W. L.

    2012-07-01

    Nanowires are widely used as building blocks of micro/nano devices, such as micro-sensors, probes, transistors and actuators in micro/nano-electro-mechanical systems (M/NEMS) and biotechnology. In this study, we investigated the large deformation behavior of a nanowire in consideration of its surface effects (surface elasticity and residual surface stress). For nanowires of large displacements with different boundary conditions, we established the governing equation set in combination with the residual surface stress and surface elasticity. Then a computer program of shooting method by using the commercial software MathCAD was developed to solve the boundary value problem numerically. Furthermore, the influences of surface effects on the large and infinitesimal deformation of the nanowires were quantitatively compared. These findings are beneficial to understanding the mechanism of the surface effects, and can also provide some inspirations to characterize the mechanical properties of nano-materials, and engineer new micro/nano-scaled devices.

  17. Gate-modulated transport properties and mechanism for nanowire cross junction based on SnO2 semiconductor

    Science.gov (United States)

    Chen, Xi; Tong, Yanhong; Wang, Guorui; Tang, Qingxin; Liu, Yichun

    2015-12-01

    The transport properties and mechanism of the three-terminal field-effect nanowire cross junction have been systematically investigated. An interesting phenomenon, such as applied voltage bias on nanowire cross junction makes the ON/OFF current ratio of the transistor improved by over 2 orders of magnitude, has been observed. Different from the two-terminal nanowire cross junctions, the cross junction induced potential barrier in three-terminal counterparts is found to be capable to prevent the current of the top semiconductor nanowire from injecting into the bottom nanowire at off state, while to make the current of the top semiconductor nanowire contribute to the current of the bottom nanowire at on state, resulting in the current switch between on state and off state by the gate voltage modulation.

  18. Towards low-dimensional hole systems in Be-doped GaAs nanowires

    Science.gov (United States)

    Ullah, A. R.; Gluschke, J. G.; Krogstrup, P.; Sørensen, C. B.; Nygård, J.; Micolich, A. P.

    2017-03-01

    GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly doped nanowires and inability to reach a clear off-state under gating for the highly doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio ˜ {10}4, and sub-threshold slope 50 mV/dec at T=4 K. Lastly, we made a device featuring a moderately doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantisation highlighting the potential for future quantum device studies in this material system.

  19. A novel WS2 nanowire-nanoflake hybrid material synthesized from WO3 nanowires in sulfur vapor

    Science.gov (United States)

    Asres, Georgies Alene; Dombovari, Aron; Sipola, Teemu; Puskás, Robert; Kukovecz, Akos; Kónya, Zoltán; Popov, Alexey; Lin, Jhih-Fong; Lorite, Gabriela S.; Mohl, Melinda; Toth, Geza; Lloyd Spetz, Anita; Kordas, Krisztian

    2016-05-01

    In this work, WS2 nanowire-nanoflake hybrids are synthesized by the sulfurization of hydrothermally grown WO3 nanowires. The influence of temperature on the formation of products is optimized to grow WS2 nanowires covered with nanoflakes. Current-voltage and resistance-temperature measurements carried out on random networks of the nanostructures show nonlinear characteristics and negative temperature coefficient of resistance indicating that the hybrids are of semiconducting nature. Bottom gated field effect transistor structures based on random networks of the hybrids show only minor modulation of the channel conductance upon applied gate voltage, which indicates poor electrical transport between the nanowires in the random films. On the other hand, the photo response of channel current holds promise for cost-efficient solution process fabrication of photodetector devices working in the visible spectral range.

  20. Nanoelectronics and quantum transport based on semiconductor nanowires

    Science.gov (United States)

    Lieber, Charles

    2010-03-01

    Semiconductor nanowires represent a uniquely powerful platform for exploring a diverse range of physical phenomena at the nanoscale due to the demonstrated capabilities of rational design and precise control of diameter, composition, morphology electronic properties during synthesis. In this talk, we will review advances of nanowires as high performance transistor and quantum devices with a focus on the prototypical Ge/Si core/shell nanowire heterostructure model system. First, a clean one-dimensional hole gas is formed due to band structure design, which sustains ballistic transport up to room temperature. Large subband spacing indicates a truly one-dimensional channel. Second, field-effect transistors utilizing Ge/Si nanowire heterostructure as the active channel are discussed with results demonstrating that these devices can outperform state-of-the-art Si MOSFETs. Third, the scaling of transistors with sub-100 nm channels are discussed with respect to pushing performance limit. Measurements and analyses show that devices with channel lengths down to 40 nm operate close to the ballistic limit and provide an intrinsic speed of 2 THz. Finally, advances in top-gate defined multi-quantum dot devices are reviewed, where control of contact transparency is used to enable studies in different quantum regimes. A fully tunable double quantum dot with integrated charge sensor is demonstrated. The characterization of charge transport and spin states, as well as its promise as a long coherence time spin qubit will be discussed.

  1. Electrochemical synthesis of ultrafast and gram-scale surfactant-free tellurium nanowires by gas-solid transformation and their applications as supercapacitor electrodes for p-doping of graphene transistors.

    Science.gov (United States)

    Tsai, Hung-Wei; Yaghoubi, Alireza; Chan, Tsung-Cheng; Wang, Chun-Chieh; Liu, Wei-Ting; Liao, Chien-Neng; Lu, Shih-Yuan; Chen, Lih-Juann; Chueh, Yu-Lun

    2015-05-01

    We herein report a gas-solid transformation mechanism for the surfactant-free synthesis of Te NWs at room temperature by electrolysis of bulk Bi2Te3 using H2Te gas. Te NWs, with an average diameter below 20 nm, grow along the [001] direction due to the unique spiral chains in the crystal structure and show an enhanced Raman scattering effect, a broad absorption band over the range of 350-750 nm and an emission band over the range of 400-700 nm in the photoluminescence spectrum. In terms of device applications, we demonstrate how Te NWs can be directly applied as a p-type dopant source in order to shift the Dirac point in ambipolar field effect graphene transistors. Finally, the favorable capacitive properties of Te NWs are established as supercapacitor electrodes with negligible internal resistance and excellent electrochemical reversibility and a specific capacitance of 24 F g(-1).

  2. From Classical to Quantum Transistor

    Directory of Open Access Journals (Sweden)

    Sanjeev Kumar

    2009-05-01

    Full Text Available In this article the classical transistor and the basic physics underlying the operation of single electron transistor are presented; a brief history of transistor and current technological issues are discussed.

  3. From Classical to Quantum Transistor

    OpenAIRE

    Sanjeev Kumar

    2009-01-01

    In this article the classical transistor and the basic physics underlying the operation of single electron transistor are presented; a brief history of transistor and current technological issues are discussed.

  4. Joule heating in nanowires

    OpenAIRE

    Fangohr, H.; Chernyshenko, D.; Franchin, Matteo; Fischbacher, Thomas; Meier, G.

    2011-01-01

    We study the effect of Joule heating from electric currents flowing through ferromagnetic nanowires on the temperature of the nanowires and on the temperature of the substrate on which the nanowires are grown. The spatial current density distribution, the associated heat generation, and diffusion of heat is simulated within the nanowire and the substrate. We study several different nanowire and constriction geometries as well as different substrates: (thin) silicon nitride membranes, (thick) ...

  5. Silicon nanowire arrays as learning chemical vapour classifiers

    Energy Technology Data Exchange (ETDEWEB)

    Niskanen, A O; Colli, A; White, R; Li, H W; Spigone, E; Kivioja, J M, E-mail: antti.niskanen@nokia.com [Nokia Research Center, Broers Building, 21 JJ Thomson Avenue, Cambridge CB3 0FA (United Kingdom)

    2011-07-22

    Nanowire field-effect transistors are a promising class of devices for various sensing applications. Apart from detecting individual chemical or biological analytes, it is especially interesting to use multiple selective sensors to look at their collective response in order to perform classification into predetermined categories. We show that non-functionalised silicon nanowire arrays can be used to robustly classify different chemical vapours using simple statistical machine learning methods. We were able to distinguish between acetone, ethanol and water with 100% accuracy while methanol, ethanol and 2-propanol were classified with 96% accuracy in ambient conditions.

  6. Si/Ge hetero-structure nanotube tunnel field effect transistor

    KAUST Repository

    Hanna, A. N.

    2015-01-07

    We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.

  7. Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Wen-Hsien; Shen, Chang-Hong; Wang, Hsing-Hsiang; Yang, Chih-Chao; Hsieh, Tung-Ying; Hsieh, Jin-Long; Yeh, Wen-Kuan [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Shieh, Jia-Min, E-mail: jmshieh@narlabs.org.tw, E-mail: jmshieh@faculty.nctu.edu.tw [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China); Huang, Tzu-En [Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China)

    2016-06-13

    A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 × 10{sup 18 }cm{sup −3} and high crystallinity (Raman FWHM ∼ 4.54 cm{sup −1}). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I{sub on}/I{sub off} ratio over 10{sup 5} and drain-induced barrier lowering of 168 mV/V. Moreover, the fast programming speed of 100 μs–1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics.

  8. Chemical Sensing with Nanowires

    Science.gov (United States)

    Penner, Reginald M.

    2012-07-01

    Transformational advances in the performance of nanowire-based chemical sensors and biosensors have been achieved over the past two to three years. These advances have arisen from a better understanding of the mechanisms of transduction operating in these devices, innovations in nanowire fabrication, and improved methods for incorporating receptors into or onto nanowires. Nanowire-based biosensors have detected DNA in undiluted physiological saline. For silicon nanowire nucleic acid sensors, higher sensitivities have been obtained by eliminating the passivating oxide layer on the nanowire surface and by substituting uncharged protein nucleic acids for DNA as the capture strands. Biosensors for peptide and protein cancer markers, based on both semiconductor nanowires and nanowires of conductive polymers, have detected these targets at physiologically relevant concentrations in both blood plasma and whole blood. Nanowire chemical sensors have also detected several gases at the parts-per-million level. This review discusses these and other recent advances, concentrating on work published in the past three years.

  9. Nanowire Optoelectronics

    Directory of Open Access Journals (Sweden)

    Wang Zhihuan

    2015-12-01

    Full Text Available Semiconductor nanowires have been used in a variety of passive and active optoelectronic devices including waveguides, photodetectors, solar cells, light-emitting diodes (LEDs, lasers, sensors, and optical antennas. We review the optical properties of these nanowires in terms of absorption, guiding, and radiation of light, which may be termed light management. Analysis of the interaction of light with long cylindrical/hexagonal structures with subwavelength diameters identifies radial resonant modes, such as Leaky Mode Resonances, or Whispering Gallery modes. The two-dimensional treatment should incorporate axial variations in “volumetric modes,”which have so far been presented in terms of Fabry–Perot (FP, and helical resonance modes. We report on finite-difference timedomain (FDTD simulations with the aim of identifying the dependence of these modes on geometry (length, width, tapering, shape (cylindrical, hexagonal, core–shell versus core-only, and dielectric cores with semiconductor shells. This demonstrates how nanowires (NWs form excellent optical cavities without the need for top and bottommirrors. However, optically equivalent structures such as hexagonal and cylindrical wires can have very different optoelectronic properties meaning that light management alone does not sufficiently describe the observed enhancement in upward (absorption and downward transitions (emission of light inNWs; rather, the electronic transition rates should be considered. We discuss this “rate management” scheme showing its strong dimensional dependence, making a case for photonic integrated circuits (PICs that can take advantage of the confluence of the desirable optical and electronic properties of these nanostructures.

  10. Semiconductor Nanowires from Materials Science and Device Physics Perspectives

    Science.gov (United States)

    Samuelson, Lars

    2005-03-01

    Realization of extremely down-scaled devices gives tough challenges related to technology and materials science. One reason for the concern is that top-down fabricated nano-devices tend to have their properties dominated by process-induced damage, rendering ultra-small devices not so useful. Alternatively, bottom-up fabrication methods may allow dimensions on the scale even below 10 nm, still with superb device properties. I will in this talk describe our research on catalytically induced growth of semiconductor nanowires. Our method uses catalytic gold nanoparticles, allowing tight control of diameter as well as position of where the nanowire grows, with our work completely focused on epitaxially nucleated nanowires in which the nanowire structure can be seen as a coherent, monolithic extension of the crystalline substrate material. One of the most important achievements in this field of research is the realization of atomically abrupt heterostructures within nanowires, in which the material composition can be altered within only one or a few monolayers, thus allowing 1D heterostructure devices to be realized. This has allowed a variety of quantum devices to be realized, such as single-electron transistors, resonant tunneling devices as well as memory storage devices. A related recent field of progress has been the realization of ideally nucleated III-V nanowires on Si substrates, cases where we have also reported functioning III-V heterostructure device structures on Si. All of these device related challenges evolve from an improved understanding of the materials science involved in nucleation of nanowires, in altering of composition of the growing nanowire, in control of the growth direction etc. I will give examples of these materials science issues and will especially dwell on the opportunities to form new kinds of materials, e.g. as 3D complex nanowire structures, resembling nanotrees or nanoforests.

  11. Long term stability of nanowire nanoelectronics in physiological environments.

    Science.gov (United States)

    Zhou, Wei; Dai, Xiaochuan; Fu, Tian-Ming; Xie, Chong; Liu, Jia; Lieber, Charles M

    2014-03-12

    Nanowire nanoelectronic devices have been exploited as highly sensitive subcellular resolution detectors for recording extracellular and intracellular signals from cells, as well as from natural and engineered/cyborg tissues, and in this capacity open many opportunities for fundamental biological research and biomedical applications. Here we demonstrate the capability to take full advantage of the attractive capabilities of nanowire nanoelectronic devices for long term physiological studies by passivating the nanowire elements with ultrathin metal oxide shells. Studies of Si and Si/aluminum oxide (Al2O3) core/shell nanowires in physiological solutions at 37 °C demonstrate long-term stability extending for at least 100 days in samples coated with 10 nm thick Al2O3 shells. In addition, investigations of nanowires configured as field-effect transistors (FETs) demonstrate that the Si/Al2O3 core/shell nanowire FETs exhibit good device performance for at least 4 months in physiological model solutions at 37 °C. The generality of this approach was also tested with in studies of Ge/Si and InAs nanowires, where Ge/Si/Al2O3 and InAs/Al2O3 core/shell materials exhibited stability for at least 100 days in physiological model solutions at 37 °C. In addition, investigations of hafnium oxide-Al2O3 nanolaminated shells indicate the potential to extend nanowire stability well beyond 1 year time scale in vivo. These studies demonstrate that straightforward core/shell nanowire nanoelectronic devices can exhibit the long term stability needed for a range of chronic in vivo studies in animals as well as powerful biomedical implants that could improve monitoring and treatment of disease.

  12. Direct-write fabrication of a nanoscale digital logic element on a single nanowire

    Energy Technology Data Exchange (ETDEWEB)

    Roy, Somenath; Gao Zhiqiang, E-mail: sroy@ibn.a-star.edu.sg [Institute of Bioengineering and Nanotechnology, 31 Biopolis Way, 138669 (Singapore)

    2010-06-18

    In this paper we report on the 'direct-write' fabrication and electrical characteristics of a nanoscale logic inverter, integrating enhancement-mode (E-mode) and depletion-mode (D-mode) field-effect transistors (FETs) on a single zinc oxide (ZnO) nanowire. 'Direct-writing' of platinum metal electrodes and a dielectric layer is executed on individual single-crystalline ZnO nanowires using either a focused electron beam (FEB) or a focused ion beam (FIB). We fabricate a top-gate FET structure, in which the gate electrode wraps around the ZnO nanowire, resulting in a more efficient gate response than the conventional back-gate nanowire transistors. For E-mode device operation, the gate electrode (platinum) is deposited directly onto the ZnO nanowire by a FEB, which creates a Schottky barrier and in turn a fully depleted channel. Conversely, sandwiching an insulating layer between the FIB-deposited gate electrode and the nanowire channel makes D-mode operation possible. Integrated E- and D-mode FETs on a single nanowire exhibit the characteristics of a direct-coupled FET logic (DCFL) inverter with a high gain and noise margin.

  13. Direct-write fabrication of a nanoscale digital logic element on a single nanowire

    Science.gov (United States)

    Roy, Somenath; Gao, Zhiqiang

    2010-06-01

    In this paper we report on the 'direct-write' fabrication and electrical characteristics of a nanoscale logic inverter, integrating enhancement-mode (E-mode) and depletion-mode (D-mode) field-effect transistors (FETs) on a single zinc oxide (ZnO) nanowire. 'Direct-writing' of platinum metal electrodes and a dielectric layer is executed on individual single-crystalline ZnO nanowires using either a focused electron beam (FEB) or a focused ion beam (FIB). We fabricate a top-gate FET structure, in which the gate electrode wraps around the ZnO nanowire, resulting in a more efficient gate response than the conventional back-gate nanowire transistors. For E-mode device operation, the gate electrode (platinum) is deposited directly onto the ZnO nanowire by a FEB, which creates a Schottky barrier and in turn a fully depleted channel. Conversely, sandwiching an insulating layer between the FIB-deposited gate electrode and the nanowire channel makes D-mode operation possible. Integrated E- and D-mode FETs on a single nanowire exhibit the characteristics of a direct-coupled FET logic (DCFL) inverter with a high gain and noise margin.

  14. Towards low-dimensional hole systems in Be-doped GaAs nanowires

    DEFF Research Database (Denmark)

    Ullah, A. R.; Gluschke, J. G.; Jeppesen, Peter Krogstrup

    2017-01-01

    GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly confined 0D and 1D hole systems with strong spin–orbit effects, motivating...... our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top......}^{4}$, and sub-threshold slope 50 mV/dec at $T=4$ K. Lastly, we made a device featuring a moderately doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance...

  15. Suppression of superconductivity in thin Nb nanowires fabricated in the vortex cores of superfluid helium

    Energy Technology Data Exchange (ETDEWEB)

    Gordon, Eugene B., E-mail: Gordon.eb@gmail.com [Institute of Problems of Chemical Physics RAS, Semenov Avenue 1, 142432 Chernogolovka, Moscow Region (Russian Federation); Bezryadin, Alexey V. [Department of Physics, University of Illinois at Urbana-Champaign, Urbana, IL 61874 (United States); Karabulin, Alexander V. [Institute of Problems of Chemical Physics RAS, Semenov Avenue 1, 142432 Chernogolovka, Moscow Region (Russian Federation); National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Kashirskoe Highway 31, 115409 Moscow (Russian Federation); Matyushenko, Vladimir I. [The Branch of Talrose Institute for Energy Problems of Chemical Physics RAS, Semenov Avenue 1/10, 142432 Chernogolovka, Moscow Region (Russian Federation); Khodos, Igor I. [Institute of Microelectronics Technology and High Purity Materials RAS, Institutskaya Street 6, 142432 Chernogolovka, Moscow Region (Russian Federation)

    2015-09-15

    Highlights: • Laser ablation in superfluid helium allows producing thin nanowires of any metal. • Nb nanowires, about 4 nm in diameter, form in the cores of superfluid vortices. • Our oxide-free Nb nanowires exhibit a quantum superconductor-to-insulator transition. • The insulating behavior in Nb wires is explained in terms of quantum phase slips. • Such nanowires can be used in superconducting phase-slip qubits and transistors. - Abstract: Nanowires of niobium, platinum and indium–lead In{sub 88}Pb{sub 12} alloy with diameters of 4.2, 3.6 and 8 nm, respectively, were grown in quantized vortices of superfluid helium, and the dependences of their resistance on temperature have been studied. Through a detailed comparison of these dependences we present evidence that superconducting niobium wires allow a high rate of quantum phase slip. This phase slippage leads to a phase transition to an insulating state at T → 0.

  16. Understanding and Controlling the Growth of Monodisperse CdS Nanowires in Solution

    DEFF Research Database (Denmark)

    Xi, Lifei; Tan, Winnie Xiu Wen; Boothroyd, Chris;

    2008-01-01

    diffusion rate of the precursor and hence low reactivity. Therefore, ODPA is good for generating nearly monodisperse and high aspect ratio US nanowires. Our nanowires have a high degree of dispersibility and thus can be easily processed for potential applications as solar cells and transistors. Finally......Cadmium sulfide (CdS) nanowires with a monodisperse diameter of 3.5 nm and length of about 600 nm were successfully synthesized using a simple and reproducible hot coordination solvents method. Structural characterization showed that the one-dimensional nanowires grow along the [001] direction......, we propose that the ODPA-to-Cd mole ratio is the key factor affecting the morphology of the nanowires because it affects both the cleavage rate of the P=S double bond and the nucleation/growth rate of the anisotropic nanocrystals. In addition, it was found that Cd-ODPA complexes give rise to a low...

  17. A Review on the Electrochemical Sensors and Biosensors Composed of Nanowires as Sensing Material

    Directory of Open Access Journals (Sweden)

    Shen-Ming Chen

    2008-01-01

    Full Text Available The development and application of nanowires for electrochemical sensors and biosensors are reviewed in this article. Next generation sensor platforms will require significant improvements in sensitivity, specificity and parallelism in order to meet the future needs in variety of fields. Sensors made of nanowires exploit some fundamental nanoscopic effect in order to meet these requirements. Nanowires are new materials, which have the characteristic of low weight with extraordinary mechanical, electrical, thermal and multifunctional properties. The advantages such as size scale, aspect ratio and other properties of nanowires are especially apparent in the use of electrical sensors such as electrochemical sensors and in the use of field-effect transistors. The preparation methods of nanowires and their properties are discussed along with their advantages towards electrochemical sensors and biosensors. Some key results from each article are summarized, relating the concept and mechanism behind each sensor, with experimental conditions as well as their behavior at different conditions.

  18. Novel approach to the growth and characterization of aligned epitaxial gallium nitride nanowires

    Science.gov (United States)

    Henry, Tania Alicia

    Nanowire devices are potential building blocks for complex electronic circuitry, however, challenges such as in-place alignment, precise positioning and nanowire device integration need to be addressed. In this work selective area grown (SAG), micron sized gallium nitride (GaN) mesas were used as growth substrates for lateral epitaxial GaN nanowire arrays. The thermodynamically stable mesa facets provide a crystallographic match for directed nanowire synthesis by minimizing the surface energy at the interface between the nanowire and substrate Nanowires grow from the sidewalls of GaN mesas forming parallel and hexagonal networks. Alignment occurs in the nonpolar m-axis and semipolar directions respectively. Gallium nitride nanowires are interconnected between thermodynamically stable and smooth pyramidal (10ll) , and (1l22) surfaces of adjacent GaN mesas, and they also grow from a single mesa to form free-standing nanowire cantilevers. The synthesis of lateral free-standing nanowires has led to exciting studies of their structural, electrical, and optical properties. Characterization of the electrical properties is carried out by in situ probing of single nanowires on the growth substrate inside a scanning electron microscope (SEM). The current transport is found to be largely dominated by thermionic field emission and Fowler-Nordheim tunneling, and is significantly limited by a large contact resistance at the probe-nanowire interface. The carrier concentration and mobilities of the probed nanowires are extracted and are in agreement with standard field effects transistors (FETs) fabricated from nanowires grown using similar growth conditions. These results reveal that electrical probing of lateral GaN nanowires is a reliable means of characterizing their electrical properties once the interface resistance between the probe and nanowire is considered. The optical properties of the nanowires were investigated. Photon emission at 3.26 eV dominated the

  19. Gate field induced switching of electronic current in Si-Ge Core-Shell nanowire quantum dots: A first principles study

    Science.gov (United States)

    Dhungana, Kamal B.; Jaishi, Meghnath; Pati, Ranjit

    Core-shell nanowires are formed by varying the radial composition of the nanowires. One of the most widely studied core-shell nanowire groups in recent years is the Si-Ge and Ge-Si core-shell nanowires. Compared to their pristine counterparts, they are reported to have superior electronic properties. For example, the scaled ON state current value in a Ge-Si core-shell nanowire field effect transistor (FET) is reported to be three to four times higher than that observed in state-of-the-art-metal oxide semiconductor FET (MOSFET) (Nature, 441, 489 (2006)). Here, we study the transport properties of the pristine Si and Si-Ge core-shell nanowire quantum dots of similar dimension to understand the superior performance of Si-Ge core-shell nanowire field effect transistor. Our calculations yield excellent gate field induced switching behavior in current for both pristine Si and Si-Ge core-shell hetero-structure nanowire quantum dots. The threshold gate bias for ON/OFF switching in the Si-Ge core-shell nanowire is found to be much smaller than that found in the pristine Si nanowire. A single particle many-body Green's function approach in conjunction with density functional theory is employed to calculate the electronic current.

  20. Magnetic and superconducting nanowires

    DEFF Research Database (Denmark)

    Piraux, L.; Encinas, A.; Vila, L.

    2005-01-01

    magnetic and superconducting nanowires. Using different approaches entailing measurements on both single wires and arrays, numerous interesting physical properties have been identified in relation to the nanoscopic dimensions of these materials. Finally, various novel applications of the nanowires are also...

  1. Vertical nanowire architectures

    DEFF Research Database (Denmark)

    Vlad, A.; Mátéfl-Tempfli, M.; Piraux, L.

    2010-01-01

    Nanowires and statistics: A statistical process for reading ultradense arrays of nanostructured materials is presented (see image). The experimental realization is achieved through selective nanowire growth using porous alumina templates. The statistical patterning approach is found to provide ri...

  2. Multi-diameter silicon nanowires: Fabrication, characterization, and modeling

    Science.gov (United States)

    Alagoz, Arif Sinan

    Nanotechnology is a rapidly expanding interdisciplinary field offering novel devices for broad range of applications. Quantum effects and surface to volume ratio of nanostructures are strongly size dependent, and redefine material properties at nanoscale. Silicon is one of the most promising materials for next generation nanostructured transistors, photonics devices, Li-ion batteries, photovoltaic solar cells, and thermoelectric energy generators. Since electrical, optical, and mechanical properties of nanostructures strongly depend on their shape, size, periodicity, and crystal structure; it is crucial to control these parameters in order to optimize device performance for targeted applications. This dissertation is intended to develop a low-cost, low-temperature, high-throughput, and large-area nanowire fabrication method that can produce well-ordered arrays of hierarchical single-crystal silicon nanowires at large scale by using nanosphere lithography and metal-assisted chemical etching. Nanowire morphology was characterized by using scanning electron microscope and optical properties of nanowire arrays were modeled with the help of finite-difference-time domain method. These novel multi-diameter silicon nanowire arrays have the potential applications in many fields including but not limited to next generation nanowire solar cells to field ionization gas sensors.

  3. Specific and reversible immobilization of histidine-tagged proteins on functionalized silicon nanowires

    DEFF Research Database (Denmark)

    Liu, Yi-Chi; Rieben, Nathalie Ines; Iversen, Lars;

    2010-01-01

    Silicon nanowire (Si NW)-based field effect transistors (FETs) have shown great potential as biosensors (bioFETs) for ultra-sensitive and label-free detection of biomolecular interactions. Their sensitivity depends not only on the device properties, but also on the function of the biological reco...

  4. Ion-step method for surface potential sensing of silicon nanowires

    NARCIS (Netherlands)

    Chen, Songyue; Nieuwkasteele, van Jan W.; Berg, van den Albert; Eijkel, Jan C.T.

    2016-01-01

    This paper presents a novel stimulus-response method for surface potential sensing of silicon nanowire (Si NW) field-effect transistors. When an "ion-step" from low to high ionic strength is given as a stimulus to the gate oxide surface, an increase of double layer capacitance is therefore expected.

  5. Metal-organic polyhedra-coated si nanowires for the sensitive detection of trace explosives

    NARCIS (Netherlands)

    Cao, Anping; Zhu, Wei; Shang, Jin; Klootwijk, Johan H.; Sudhölter, Ernst J.R.; Huskens, Jurriaan; Smet, de Louis

    2017-01-01

    Surface-modified silicon nanowire-based field-effect transistors (SiNW-FETs) have proven to be a promising platform for molecular recognition in miniature sensors. In this work, we present a novel nanoFET/device for the sensitive and selective detection of explosives based on affinity layers of

  6. MMP-2 detective silicon nanowire biosensor using enzymatic cleavage reaction.

    Science.gov (United States)

    Choi, Jin-Ha; Kim, Han; Kim, Hyun-Soo; Um, Soong Ho; Choi, Jeong-Woo; Oh, Byung-Keun

    2013-04-01

    Matrix metalloproteinases are proteolytic enzymes that play a significant role in tissue remodeling related with various pathological and physiological processes such as tissue repair, angiogenesis, cirrhosis, morphogenesis, arthritis, and metastasis. Especially, MMP-2 has been shown to be related with benign prostatic hyperplasia and prostate cancer. Therefore, there is a need to make sensors with high sensitivity that can measure MMP-2 concentrations precisely. Silicon nanowires have been used in the development of high sensitive chemical sensors and biosensors. The high sensitivity of silicon nanowire based sensor originates in its high surface to volume ratio and ability to field-effect induced local charge transfers. In this study, 100 nm silicon nanowire based field-effect transistors (FET) device was fabricated by electron-beam lithography and MMP-2 was successfully measured by conductance versus time characteristics within 1 pM to 100 nM.

  7. Measuring surface state density and energy distribution in InAs nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Halpern, Eliezer; Cohen, Gilad; Gross, Shahar; Henning, Alexander; Matok, Max; Rosenwaks, Yossi [Department of Physical Electronics, School of Electrical Engineering, Tel-Aviv University (Israel); Kretinin, Andrey V. [School of Physics and Astronomy, University of Manchester (United Kingdom); Shtrikman, Hadas [Department of Condensed Matter Physics, Braun Center for Submicrometer Research, Weizmann Institute of Science, Rehovot (Israel)

    2014-02-15

    Semiconducting nanowires are expected to have applications in various areas as transistors, sensors, resonators, solar cells, and thermoelectric systems. Understanding the surface properties is crucial for the fabrication of high-performance devices. Due to the large surface-to-volume ratio of nanowires, their surface electronic properties, like surface states, can a have a large effect on the performance of both electronic and optoelectronic devices. At present, determination of the surface state density depends on a combination of experimental measurements of the capacitance and/or drain current, in a nanowire field-effect transistor, and a fitting to simulation. This technique follows certain assumptions, which can severely harm the accuracy of the extracted density of states. In this report, we demonstrate a direct measurement of the surface state density of individual InAs and silicon nanowires. The method is based on measuring the surface potential of a nanowire field-effect transistor, with respect to a changing gate bias. The extracted density of states at the surface helps to explain various electronic phenomena in such devices. (copyright 2014 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  8. High Power Switching Transistor

    Science.gov (United States)

    Hower, P. L.; Kao, Y. C.; Carnahan, D. C.

    1983-01-01

    Improved switching transistors handle 400-A peak currents and up to 1,200 V. Using large diameter silicon wafers with twice effective area as D60T, form basis for D7 family of power switching transistors. Package includes npn wafer, emitter preform, and base-contact insert. Applications are: 25to 50-kilowatt high-frequency dc/dc inverters, VSCF converters, and motor controllers for electrical vehicles.

  9. Graphene transistors for bioelectronics

    OpenAIRE

    Hess, Lucas H.; Seifert, Max; Garrido, Jose A.

    2013-01-01

    This paper provides an overview on graphene solution-gated field effect transistors (SGFETs) and their applications in bioelectronics. The fabrication and characterization of arrays of graphene SGFETs is presented and discussed with respect to competing technologies. To obtain a better understanding of the working principle of solution-gated transistors, the graphene-electrolyte interface is discussed in detail. The in-vitro biocompatibility of graphene is assessed by primary neuron cultures....

  10. Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

    Science.gov (United States)

    Cai, Ronggang; Kassa, Hailu G.; Haouari, Rachid; Marrani, Alessio; Geerts, Yves H.; Ruzié, Christian; van Breemen, Albert J. J. M.; Gelinck, Gerwin H.; Nysten, Bernard; Hu, Zhijun; Jonas, Alain M.

    2016-03-01

    Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction intrinsic to the nanostructured hybrid layer offers opportunities for the development of strongly miniaturized ferroelectric and piezoelectric devices.Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction

  11. Transistor-based interface circuitry

    Science.gov (United States)

    Taubman, Matthew S.

    2007-02-13

    Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

  12. Nanowire Growth for Photovoltaics

    DEFF Research Database (Denmark)

    Holm, Jeppe Vilstrup

    Solar cells commercial success is based on an efficiency/cost calculation. Nanowire solar cells is one of the foremost candidates to implement third generation photo voltaics, which are both very efficient and cheap to produce. This thesis is about our progress towards commercial nanowire solar...... cells. Resonance effects between the light and nanowire causes an inherent concentration of the sunlight into the nanowires, and means that a sparse array of nanowires (less than 5% of the area) can absorb all the incoming light. The resonance effects, as well as a graded index of refraction, also traps...... the light. The concentration and light trapping means that single junction nanowire solar cells have a higher theoretical maximum efficiency than equivalent planar solar cells. We have demonstrated the built-in light concentration of nanowires, by growing, contacting and characterizing a solar cell...

  13. Stability of Organic Nanowires

    DEFF Research Database (Denmark)

    Balzer, F.; Schiek, M.; Wallmann, I.;

    2011-01-01

    The morphological stability of organic nanowires over time and under thermal load is of major importance for their use in any device. In this study the growth and stability of organic nanowires from a naphthyl end-capped thiophene grown by organic molecular beam deposition is investigated via...... atomic force microscopy (AFM). Aging experiments under ambient conditions already show substantial morphological changes. Nanoscopic organic clusters, which initially coexist with the nanowires, vanish within hours. Thermal annealing of nanowire samples leads to even more pronounced morphology changes......, such as a strong decrease in nanowire number density, a strong increase in nanowire height, and the formation of new types of crystallites. This happens even before sublimation of organic material starts. These experiments also shine new light on the formation process of the nanowires....

  14. Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

    Science.gov (United States)

    Alvarado, J.; Flores, P.; Romero, S.; Ávila-Herrera, F.; González, V.; Soto-Cruz, B. S.; Cerdeira, A.

    2016-07-01

    A physically based model of the double-gate juntionless transistor which is capable of describing accumulation and depletion regions is implemented in Verilog-A in order to perform DC circuit simulations. Analytical description of the difference of potentials between the center and the surface of the silicon layer allows the determination of the mobile charges. Furthermore, mobility degradation, series resistance, as well as threshold voltage roll-off, drain saturation voltage, channel shortening and velocity saturation are also considered. In order to provide this model to all of the community, the implementation of this model is performed in Ngspice, which is a free circuit simulation with an ADMS interface to integrate Verilog-A models. Validation of the model implementation is done through 2D numerical simulations of transistors with 1 μ {{m}} and 40 {{nm}} silicon channel length and 1 × 1019 or 5× {10}18 {{{cm}}}-3 doping concentration of the silicon layer with 10 and 15 {{nm}} silicon thickness. Good agreement between the numerical simulated behavior and model implementation is obtained, where only eight model parameters are used.

  15. Charge Noise in Organic Electrochemical Transistors

    Science.gov (United States)

    Stoop, Ralph L.; Thodkar, Kishan; Sessolo, Michele; Bolink, Henk J.; Schönenberger, Christian; Calame, Michel

    2017-01-01

    Organic electrochemical transistors (OECTs) are increasingly studied as transducers in sensing applications. While much emphasis has been placed on analyzing and maximizing the OECT signal, noise has been mostly ignored, although it determines the resolution of the sensor. The major contribution to the noise in sensing devices is the 1 /f noise, dominant at low frequency. In this work, we demonstrate that the 1 /f noise in OECTs follows a charge-noise model, which reveals that the noise is due to charge fluctuations in proximity or within the bulk of the channel material. We present the noise scaling behavior with gate voltage, channel dimensions, and polymer thickness. Our results suggest the use of large area channels in order to maximize the signal-to-noise ratio (SNR) for biochemical and electrostatic sensing applications. A comparison with the literature shows that the magnitude of the noise in OECTs is similar to that observed in graphene transistors, and only slightly higher than that found in carbon nanotubes and silicon nanowire devices. In a model ion-sensing experiment with OECTs, we estimate crucial parameters such as the characteristic SNR and the corresponding limit of detection.

  16. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  17. Quantum thermal transistor

    CERN Document Server

    Joulain, Karl; Ezzahri, Younès; Ordonez-Miranda, Jose

    2016-01-01

    We demonstrate that a thermal transistor can be made up with a quantum system of 3 interacting subsystems , coupled to a thermal reservoir each. This thermal transistor is analogous to an electronic bipolar one with the ability to control the thermal currents at the collector and at the emitter with the imposed thermal current at the base. This is achieved determining the heat fluxes by means of the strong-coupling formalism. For the case of 3 interacting spins, in which one of them is coupled to the other 2, that are not directly coupled, it is shown that high amplification can be obtained in a wide range of energy parameters and temperatures. The proposed quantum transistor could, in principle, be used to develop devices such as a thermal modulator and a thermal amplifier in nano systems.

  18. The resonant body transistor.

    Science.gov (United States)

    Weinstein, Dana; Bhave, Sunil A

    2010-04-14

    This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer.

  19. Quantum Thermal Transistor.

    Science.gov (United States)

    Joulain, Karl; Drevillon, Jérémie; Ezzahri, Younès; Ordonez-Miranda, Jose

    2016-05-20

    We demonstrate that a thermal transistor can be made up with a quantum system of three interacting subsystems, coupled to a thermal reservoir each. This thermal transistor is analogous to an electronic bipolar one with the ability to control the thermal currents at the collector and at the emitter with the imposed thermal current at the base. This is achieved by determining the heat fluxes by means of the strong-coupling formalism. For the case of three interacting spins, in which one of them is coupled to the other two, that are not directly coupled, it is shown that high amplification can be obtained in a wide range of energy parameters and temperatures. The proposed quantum transistor could, in principle, be used to develop devices such as a thermal modulator and a thermal amplifier in nanosystems.

  20. Nanotubes and nanowires

    Indian Academy of Sciences (India)

    C N R Rao; A Govindaraj

    2001-10-01

    Synthesis and characterization of nanotubes and nanowires constitute an important part of nanoscience since these materials are essential bui lding units for several devices. We have prepared aligned carbon nanotube bundles and Y-junction nanotubes by the pyrolysis of appropriate organic precursors. The aligned bundles are useful for field emission display while the Y-junction nanotubes are likely to be useful as nanochips since they exhibit diode properties at the junction. By making use of carbon nanotubes, nanowires of metals, metal oxides and GaN have be en obt a ined. Both the oxide and GaN nanowires are single crystalline. Gold nanowires exhibit plasmon bands varying markedly with the aspect ratio. GaN nanowires show excellent photoluminescence characteristics. It has been possible to synthesise nanotubes and nanowires of metal chalcogenides by employing different strategies.

  1. Dimensional effects in semiconductor nanowires; Dimensionseffekte in Halbleiternanodraehten

    Energy Technology Data Exchange (ETDEWEB)

    Stichtenoth, Daniel

    2008-06-23

    . Furthermore, GaAs nanowires were implanted with zinc ions. Electrical measurements on individual nanowires show a conductivity rise by four orders of magnitude. This points to a successful p-type doping. In a lithographic process ZnO nanowires were fabricated to field effect transistors (FET). Depending on the diameter and processing these FETs show carrier concentrations up to 10{sup 20} cm{sup -3} and mobilities up to 4800 cm{sup 2}/(Vs). Finally, a simple scalable process for the production of ZnO nanowire light emitting diodes (LED) is presented. The electro-luminescence of the nanowire LED is dominated by near band gap transitions, i.e. in the UV. It can be explained by tunnel injection from the p-silicon substrate into the ZnO nanowires. The light is mainly emitted from the end faces of the nanowires. This way the diameter of the light sources is defined by the diameter of the nanowires. (orig.)

  2. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates

    Science.gov (United States)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-01

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints.Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02041k

  3. Joule heating in nanowires

    Science.gov (United States)

    Fangohr, Hans; Chernyshenko, Dmitri S.; Franchin, Matteo; Fischbacher, Thomas; Meier, Guido

    2011-08-01

    We study the effect of Joule heating from electric currents flowing through ferromagnetic nanowires on the temperature of the nanowires and on the temperature of the substrate on which the nanowires are grown. The spatial current density distribution, the associated heat generation, and diffusion of heat are simulated within the nanowire and the substrate. We study several different nanowire and constriction geometries as well as different substrates: (thin) silicon nitride membranes, (thick) silicon wafers, and (thick) diamond wafers. The spatially resolved increase in temperature as a function of time is computed. For effectively three-dimensional substrates (where the substrate thickness greatly exceeds the nanowire length), we identify three different regimes of heat propagation through the substrate: regime (i), where the nanowire temperature increases approximately logarithmically as a function of time. In this regime, the nanowire temperature is well described analytically by You [Appl. Phys. Lett.APPLAB0003-695110.1063/1.2399441 89, 222513 (2006)]. We provide an analytical expression for the time tc that marks the upper applicability limit of the You model. After tc, the heat flow enters regime (ii), where the nanowire temperature stays constant while a hemispherical heat front carries the heat away from the wire and into the substrate. As the heat front reaches the boundary of the substrate, regime (iii) is entered, where the nanowire and substrate temperature start to increase rapidly. For effectively two-dimensional substrates (where the nanowire length greatly exceeds the substrate thickness), there is only one regime in which the temperature increases logarithmically with time for large times, before the heat front reaches the substrate boundary. We provide an analytical expression, valid for all pulse durations, that allows one to accurately compute this temperature increase in the nanowire on thin substrates.

  4. Decoupling single nanowire mobilities limited by surface scattering and bulk impurity scattering

    Energy Technology Data Exchange (ETDEWEB)

    Khanal, D. R.; Levander, A. X.; Wu, J. [Department of Materials Science and Engineering, University of California, Berkeley, California 94720 (United States); Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Yu, K. M.; Liliental-Weber, Z.; Walukiewicz, W. [Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Grandal, J.; Sanchez-Garcia, M. A.; Calleja, E. [Department of Ingenieria Electronica-ISOM, Universidad Politecnica, Ciudad Universitaria, 28040 Madrid (Spain)

    2011-08-01

    We demonstrate the isolation of two free carrier scattering mechanisms as a function of radial band bending in InN nanowires via universal mobility analysis, where effective carrier mobility is measured as a function of effective electric field in a nanowire field-effect transistor. Our results show that Coulomb scattering limits effective mobility at most effective fields, while surface roughness scattering only limits mobility under very high internal electric fields. High-energy {alpha} particle irradiation is used to vary the ionized donor concentration, and the observed decrease in mobility and increase in donor concentration are compared to Hall effect results of high-quality InN thin films. Our results show that for nanowires with relatively high doping and large diameters, controlling Coulomb scattering from ionized dopants should be given precedence over surface engineering when seeking to maximize nanowire mobility.

  5. Accelerating the life of transistors

    Science.gov (United States)

    Haochun, Qi; Changzhi, Lü; Xiaoling, Zhang; Xuesong, Xie

    2013-06-01

    Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 104 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 103. Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation.

  6. Accelerating the life of transistors

    Institute of Scientific and Technical Information of China (English)

    Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

    2013-01-01

    Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object,the test of accelerating life is conducted in constant temperature and humidity,and then the data are statistically analyzed with software developed by ourselves.According to degradations of such sensitive parameters as the reverse leakage current of transistors,the lifetime order of transistors is about more than 104 at 100 ℃ and 100% relative humidity (RH) conditions.By corrosion fracture of transistor outer leads and other failure modes,with the failure truncated testing,the average lifetime rank of transistors in different distributions is extrapolated about 103.Failure mechanism analyses of degradation of electrical parameters,outer lead fracture and other reasons that affect transistor lifetime are conducted.The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation.

  7. Flexible 2D RF Nanoelectronics based on Layered Semiconductor Transistor (NBIT III)

    Science.gov (United States)

    2016-11-10

    poly(4-styrenesulfonate), metal grids, graphene, carbon nanotubes , nanotube – polymer composites, and silver nanowire (Ag NW) meshes. Among the...semiconductor, thermionic emission and/or tunneling will allow electron transport during transistor operation. According to Das et al., thermionic...increased barrier height prevents electron transport from metal to MoS2. Since this off-current is dominated by thermionic emission and both samples

  8. Schottky barrier heights at the interfaces between pure-phase InAs nanowires and metal contacts

    Energy Technology Data Exchange (ETDEWEB)

    Feng, Boyong; Huang, Shaoyun, E-mail: syhuang@pku.edu.cn, E-mail: hqxu@pku.edu.cn; Wang, Jiyin [Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871 (China); Pan, Dong; Zhao, Jianghua [State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Xu, H. Q., E-mail: syhuang@pku.edu.cn, E-mail: hqxu@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871 (China); Division of Solid-State Physics, Lund University, Box 118, S-221 00 Lund (Sweden)

    2016-02-07

    Understanding of the Schottky barriers formed at metal contact-InAs nanowire interfaces is of great importance for the development of high-performance InAs nanowire nanoelectronic and quantum devices. Here, we report a systematical study of InAs nanowire field-effect transistors (FETs) and the Schottky barrier heights formed at the contact-nanowire interfaces. The InAs nanowires employed are grown by molecular beam epitaxy and are high material quality single crystals, and the devices are made by directly contacting the nanowires with a series of metals of different work functions. The fabricated InAs nanowire FET devices are characterized by electrical measurements at different temperatures and the Schottky barrier heights are extracted from the measured temperature and gate-voltage dependences of the channel current. We show that although the work functions of the contact metals are widely spread, the Schottky barrier heights are determined to be distributed over 35–55 meV, showing a weak but not negligible dependence on the metals. The deduced Fermi level in the InAs nanowire channels is found to be in the band gap and very close to the conduction band. The physical origin of the results is discussed in terms of Fermi level pinning by the surface states of the InAs nanowires and a shift in pinned Fermi level induced by the metal-related interface states.

  9. A Matterwave Transistor Oscillator

    CERN Document Server

    Caliga, Seth C; Zozulya, Alex A; Anderson, Dana Z

    2012-01-01

    A triple-well atomtronic transistor combined with forced RF evaporation is used to realize a driven matterwave oscillator circuit. The transistor is implemented using a metalized compound glass and silicon substrate. On-chip and external currents produce a cigar-shaped magnetic trap, which is divided into transistor source, gate, and drain regions by a pair of blue-detuned optical barriers projected onto the magnetic trap through a chip window. A resonant laser beam illuminating the drain portion of the atomtronic transistor couples atoms emitted by the gate to the vacuum. The circuit operates by loading the source with cold atoms and utilizing forced evaporation as a power supply that produces a positive chemical potential in the source, which subsequently drives oscillation. High-resolution in-trap absorption imagery reveals gate atoms that have tunneled from the source and establishes that the circuit emits a nominally mono-energetic matterwave with a frequency of 23.5(1.0) kHz by tunneling from the gate, ...

  10. Towards the ultimate transistor

    Science.gov (United States)

    Natelson, Douglas

    2009-06-01

    The first transistor, made more than 60 years ago at Bell Labs, was a couple of inches across. Today, a typical laptop computer uses a processor chip that contains well over a billion transistors, each one with electrodes separated by less than 50 nm of silicon, which is less than a thousandth of the diameter of a human hair. This continual drive for miniaturization, with the density of transistors doubling roughly every two years, was first noted by Intel co-founder Gordon Moore in 1965, and has been such a mainstay of electronics development that it is now enshrined as "Moore's law". These billions of transistors are made by "top down" methods that involve depositing thin layers of materials, patterning nano-scale stencils and effectively carving away the unwanted bits. The incredible success of this approach is almost impossible to overstate. The end result is billions of individual components on a single chip, essentially all working perfectly and continuously for years on end. No other manufactured technology comes remotely close in reliability or cost-per-widget.

  11. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  12. Contact resistance and overlapping capacitance in flexible sub-micron long oxide thin-film transistors for above 100 MHz operation

    Science.gov (United States)

    Münzenrieder, Niko; Salvatore, Giovanni A.; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Vogt, Christian; Cantarella, Giuseppe; Tröster, Gerhard

    2014-12-01

    In recent years new forms of electronic devices such as electronic papers, flexible displays, epidermal sensors, and smart textiles have become reality. Thin-film transistors (TFTs) are the basic blocks of the circuits used in such devices and need to operate above 100 MHz to efficiently treat signals in RF systems and address pixels in high resolution displays. Beyond the choice of the semiconductor, i.e., silicon, graphene, organics, or amorphous oxides, the junctionless nature of TFTs and its geometry imply some limitations which become evident and important in devices with scaled channel length. Furthermore, the mechanical instability of flexible substrates limits the feature size of flexible TFTs. Contact resistance and overlapping capacitance are two parasitic effects which limit the transit frequency of transistors. They are often considered independent, while a deeper analysis of TFTs geometry imposes to handle them together; in fact, they both depend on the overlapping length (LOV) between source/drain and the gate contacts. Here, we conduct a quantitative analysis based on a large number of flexible ultra-scaled IGZO TFTs. Devices with three different values of overlap length and channel length down to 0.5 μm are fabricated to experimentally investigate the scaling behavior of the transit frequency. Contact resistance and overlapping capacitance depend in opposite ways on LOV. These findings establish routes for the optimization of the dimension of source/drain contact pads and suggest design guidelines to achieve megahertz operation in flexible IGZO TFTs and circuits.

  13. Micro-Photoluminescence (micro-PL) Study of Core Shell GaAs/GaAsSb Nanowires Grown by Self-Assisted Molecular Beam Epitaxy

    Science.gov (United States)

    2015-06-18

    transistor (FET) and light emitting diode (LED) applications. In this thesis, room temperature and low temperature (4K) micro- photoluminescence (micro...public release; distribution is unlimited. Micro- Photoluminescence (micro-PL) Study of Core-Shell GaAs/GaAsSb Nanowires grown by Self-Assisted Molecular...U.S. Army Research Office P.O. Box 12211 Research Triangle Park, NC 27709-2211 GaAsSb, Core Shell Nanowires, Micro Photoluminescence

  14. Nanowire Photovoltaic Devices

    Science.gov (United States)

    Forbes, David

    2015-01-01

    Firefly Technologies, in collaboration with the Rochester Institute of Technology and the University of Wisconsin-Madison, developed synthesis methods for highly strained nanowires. Two synthesis routes resulted in successful nanowire epitaxy: direct nucleation and growth on the substrate and a novel selective-epitaxy route based on nanolithography using diblock copolymers. The indium-arsenide (InAs) nanowires are implemented in situ within the epitaxy environment-a significant innovation relative to conventional semiconductor nanowire generation using ex situ gold nanoparticles. The introduction of these nanoscale features may enable an intermediate band solar cell while simultaneously increasing the effective absorption volume that can otherwise limit short-circuit current generated by thin quantized layers. The use of nanowires for photovoltaics decouples the absorption process from the current extraction process by virtue of the high aspect ratio. While no functional solar cells resulted from this effort, considerable fundamental understanding of the nanowire epitaxy kinetics and nanopatterning process was developed. This approach could, in principle, be an enabling technology for heterointegration of dissimilar materials. The technology also is applicable to virtual substrates. Incorporating nanowires onto a recrystallized germanium/metal foil substrate would potentially solve the problem of grain boundary shunting of generated carriers by restricting the cross-sectional area of the nanowire (tens of nanometers in diameter) to sizes smaller than the recrystallized grains (0.5 to 1 micron(exp 2).

  15. Nanowire Growth for Photovoltaics

    DEFF Research Database (Denmark)

    Holm, Jeppe Vilstrup

    -catalyzed nanowire growth, and grown GaAs1−xPx nanowires with different inclusions of P(x) directly on silicon. The incorporation of P was generally higher in nanowires than for planar growth at identical P flux percentage. More interestingly, the percentage of P in the nanowire was found to be a concave function...... of the percentage of P in the flux, while for planar growth it was a convex function. We have demonstrated GaAs0.8P0.2 nanowires and further grown a shell surrounding the core with the same composition. The lattice matched GaAsP core-shell nanowire were doped to produce radial p-i-n junctions in each...... of the nanowires, some of which were removed from their growth substrate and turned into single nanowire solar cells (SNWSC). The best device showed a conversion efficiency of 6.8% under 1.5AMG 1-sun illumination. In order to improve the efficiency a surface passivating shell consisting of highly doped, wide...

  16. Multi-quantum-well nanowire heterostructures for wavelength-controlled lasers

    Science.gov (United States)

    Qian, Fang; Li, Yat; Gradečak, Silvija; Park, Hong-Gyu; Dong, Yajie; Ding, Yong; Wang, Zhong Lin; Lieber, Charles M.

    2008-09-01

    Rational design and synthesis of nanowires with increasingly complex structures can yield enhanced and/or novel electronic and photonic functions. For example, Ge/Si core/shell nanowires have exhibited substantially higher performance as field-effect transistors and low-temperature quantum devices compared with homogeneous materials, and nano-roughened Si nanowires were recently shown to have an unusually high thermoelectric figure of merit. Here, we report the first multi-quantum-well (MQW) core/shell nanowire heterostructures based on well-defined III-nitride materials that enable lasing over a broad range of wavelengths at room temperature. Transmission electron microscopy studies show that the triangular GaN nanowire cores enable epitaxial and dislocation-free growth of highly uniform (InGaN/GaN)n quantum wells with n=3, 13 and 26 and InGaN well thicknesses of 1-3nm. Optical excitation of individual MQW nanowire structures yielded lasing with InGaN quantum-well composition-dependent emission from 365 to 494nm, and threshold dependent on quantum well number, n. Our work demonstrates a new level of complexity in nanowire structures, which potentially can yield free-standing injection nanolasers.

  17. Semiconductor nanowire lasers

    Science.gov (United States)

    Eaton, Samuel W.; Fu, Anthony; Wong, Andrew B.; Ning, Cun-Zheng; Yang, Peidong

    2016-06-01

    The discovery and continued development of the laser has revolutionized both science and industry. The advent of miniaturized, semiconductor lasers has made this technology an integral part of everyday life. Exciting research continues with a new focus on nanowire lasers because of their great potential in the field of optoelectronics. In this Review, we explore the latest advancements in the development of nanowire lasers and offer our perspective on future improvements and trends. We discuss fundamental material considerations and the latest, most effective materials for nanowire lasers. A discussion of novel cavity designs and amplification methods is followed by some of the latest work on surface plasmon polariton nanowire lasers. Finally, exciting new reports of electrically pumped nanowire lasers with the potential for integrated optoelectronic applications are described.

  18. One-flux theory of saturated drain current in nanoscale transistors

    Science.gov (United States)

    Tang, Ting-wei; Fischetti, Massimo V.; Jin, Seonghoon; Sano, Nobuyuki

    2012-12-01

    We present an expression for the saturated drain current in nanoscale transistors based on multiple reflections of carriers at the virtual source from two adjacent scattering "black boxes". Under certain assumptions and simplifications this new expression reduces to the well known Lundstrom's formula and also to the recent model by Giusi et al. Six macroscopic parameters appear in the 'exact' form of this model. We do not discuss how to derive physical expressions for these parameters. Rather, we emphasize the limitations of Lundstrom's model when applied to nanoscale transistors. Some existing formulae for the carrier backscattering coefficient are examined and compared to our results. We verify our model through a consistency test based on simulation data of a 10 nm gate-length silicon nanowire transistor.

  19. Graphene Hot-electron Transistors

    OpenAIRE

    Vaziri, Sam

    2016-01-01

    Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis...

  20. TRANSISTOR HIGH VOLTAGE POWER SUPPLY

    Science.gov (United States)

    Driver, G.E.

    1958-07-15

    High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

  1. Silicon nanowire charge-trap memory incorporating self-assembled iron oxide quantum dots.

    Science.gov (United States)

    Huang, Ruo-Gu; Heath, James R

    2012-11-19

    Charge-trap non-volatile memory devices based upon the precise integration of quantum dot storage elements with silicon nanowire field-effect transistors are described. Template-assisted assembly yields an ordered array of FeO QDs within the trenches that separate highly aligned SiNWs, and injected charges are reversibly stored via Fowler-Nordheim tunneling into the QDs. Stored charges shift the transistor threshold voltages, providing the basis for a memory device. Quantum dot size is found to strongly influence memory performance metrics.

  2. Mesoscopic photon heat transistor

    DEFF Research Database (Denmark)

    Ojanen, T.; Jauho, Antti-Pekka

    2008-01-01

    We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir-Wingreen-Landauer-typ......We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir......-Wingreen-Landauer-type of conductance formula, which gives the photonic heat current through an arbitrary circuit element coupled to two dissipative reservoirs at finite temperatures. As an illustration we present an exact solution for the case when the intermediate circuit can be described as an electromagnetic resonator. We discuss...

  3. Polarization induced doped transistor

    Energy Technology Data Exchange (ETDEWEB)

    Xing, Huili (Grace); Jena, Debdeep; Nomoto, Kazuki; Song, Bo; Zhu, Mingda; Hu, Zongyang

    2016-06-07

    A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

  4. Elimination of gold diffusion in the heterostructure core/shell growth of high performance Ge/Si nanowire HFETs

    Energy Technology Data Exchange (ETDEWEB)

    Picraux, Samuel T [Los Alamos National Laboratory; Dayeh, Shadi A [Los Alamos National Laboratory

    2010-01-01

    Radial heterostructure nanowires offer the possibility of surface, strain, band-edge and modulution-doped engineering for optimizing performance of nanowire transistors. Synthesis of such heterostructures is non-trivial and is typically accompanied with Au diffusion on the nanowire sidewalls that result in rough morphology and undesired whisker growth. Here, they report a novel growth procedure to synthesize Ge/Si core/multi-shell nanowires by engineering the growth interface between the Au seed and the nanowire sidewalls. Single crystal Ge/Si core/multi-shell nanowires are used to fabricate side-by-side FET transistors with and without Au diffusion. Elimination of Au diffusion in the synthesis of such structures led to {approx} 2X improvement in hole field-effect mobility, transconductances and currents. Initial prototype devices with a 10 nm PECVD nitride gate dielectric resulted in a record maximum on current of 430 {micro}A/V (I{sub DS}L{sub G}/{pi}DV{sub DS}), {approx} 2X higher than ever achieved before in a p-type FET.

  5. Nanowire-based thermoelectrics

    Science.gov (United States)

    Ali, Azhar; Chen, Yixi; Vasiraju, Venkata; Vaddiraju, Sreeram

    2017-07-01

    Research on thermoelectrics has seen a huge resurgence since the early 1990s. The ability of tuning a material’s electrical and thermal transport behavior upon nanostructuring has led to this revival. Nevertheless, thermoelectric performances of nanowires and related materials lag far behind those achieved with thin-film superlattices and quantum dot-based materials. This is despite the fact that nanowires offer many distinct advantages in enhancing the thermoelectric performances of materials. The simplicity of the strategy is the first and foremost advantage. For example, control of the nanowire diameters and their surface roughnesses will aid in enhancing their thermoelectric performances. Another major advantage is the possibility of obtaining high thermoelectric performances using simpler nanowire chemistries (e.g., elemental and binary compound semiconductors), paving the way for the fabrication of thermoelectric modules inexpensively from non-toxic elements. In this context, the topical review provides an overview of the current state of nanowire-based thermoelectrics. It concludes with a discussion of the future vision of nanowire-based thermoelectrics, including the need for developing strategies aimed at the mass production of nanowires and their interface-engineered assembly into devices. This eliminates the need for trial-and-error strategies and complex chemistries for enhancing the thermoelectric performances of materials.

  6. Tunable diameter electrostatically formed nanowire for high sensitivity gas sensing

    Institute of Scientific and Technical Information of China (English)

    Alex Henning; Nandhini Swaminathan; Andrey Godkin; Gil Shalev; Iddo Amit; Yossi Rosenwaks

    2015-01-01

    We report on an electrostatically formed nanowire (EFN)-based sensor with tunable diameters in the range of 16 nm to 46 nm and demonstrate an EFN- based field-effect transistor as a highly sensitive and robust room temperature gas sensor. The device was carefully designed and fabricated using standard integrated processing to achieve the 16 nm EFN that can be used for sensing without any need for surface modification. The effective diameter for the EFN was determined using Kelvin probe force microscopy accompanied by three- dimensional electrostatic simulations. We show that the EFN transistor is capable of detecting 100 parts per million of ethanol gas with bare SiO2.

  7. Silicon nanowire hybrid photovoltaics

    KAUST Repository

    Garnett, Erik C.

    2010-06-01

    Silicon nanowire Schottky junction solar cells have been fabricated using n-type silicon nanowire arrays and a spin-coated conductive polymer (PEDOT). The polymer Schottky junction cells show superior surface passivation and open-circuit voltages compared to standard diffused junction cells with native oxide surfaces. External quantum efficiencies up to 88% were measured for these silicon nanowire/PEDOT solar cells further demonstrating excellent surface passivation. This process avoids high temperature processes which allows for low-cost substrates to be used. © 2010 IEEE.

  8. The Analysis of Characteristics in Dry and Wet Environments of Silicon Nanowire-Biosensor.

    Science.gov (United States)

    Choi, Hyoun Mo; Shin, Dong Jae; Lee, Jung Han; Mo, Hyun-Sun; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Kim, Dae Hwan; Park, Jisun

    2016-05-01

    Our study investigates differences in sensitivity of dry and wet environment in the field of biosensing experiment in detail and depth. The sensitivity of biosensing varies by means of surrounding conditions of silicon nanowire field effect transistor (SiNW FET). By examining charged polymer reaction in the silicon nanowire transistor (SiNW), we have discovered that the threshold voltage (V(T)) shift and change of subthreshold slope (SS) in wet environment are smaller than that of the air. Furthermore, we analyzed the sensitivity through modifying electrolyte concentration in the wet condition, and confirmed that V(T) shift increases in low concentration condition of phosphate buffered saline (PBS) due to the Debye length. We believe that the results we have found in this study would be the cornerstone in contributing to advanced biosensing experiment in the future.

  9. High-performance silicon nanowire bipolar phototransistors

    Science.gov (United States)

    Tan, Siew Li; Zhao, Xingyan; Chen, Kaixiang; Crozier, Kenneth B.; Dan, Yaping

    2016-07-01

    Silicon nanowires (SiNWs) have emerged as sensitive absorbing materials for photodetection at wavelengths ranging from ultraviolet (UV) to the near infrared. Most of the reports on SiNW photodetectors are based on photoconductor, photodiode, or field-effect transistor device structures. These SiNW devices each have their own advantages and trade-offs in optical gain, response time, operating voltage, and dark current noise. Here, we report on the experimental realization of single SiNW bipolar phototransistors on silicon-on-insulator substrates. Our SiNW devices are based on bipolar transistor structures with an optically injected base region and are fabricated using CMOS-compatible processes. The experimentally measured optoelectronic characteristics of the SiNW phototransistors are in good agreement with simulation results. The SiNW phototransistors exhibit significantly enhanced response to UV and visible light, compared with typical Si p-i-n photodiodes. The near infrared responsivities of the SiNW phototransistors are comparable to those of Si avalanche photodiodes but are achieved at much lower operating voltages. Compared with other reported SiNW photodetectors as well as conventional bulk Si photodiodes and phototransistors, the SiNW phototransistors in this work demonstrate the combined advantages of high gain, high photoresponse, low dark current, and low operating voltage.

  10. Biofunctionalized Magnetic Nanowires

    KAUST Repository

    Kosel, Jurgen

    2013-12-19

    Magnetic nanowires can be used as an alternative method overcoming the limitations of current cancer treatments that lack specificity and are highly cytotoxic. Nanowires are developed so that they selectively attach to cancer cells via antibodies, potentially destroying them when a magnetic field induces their vibration. This will transmit a mechanical force to the targeted cells, which is expected to induce apoptosis on the cancer cells.

  11. Intrinsically stretchable and healable semiconducting polymer for organic transistors

    Science.gov (United States)

    Oh, Jin Young; Rondeau-Gagné, Simon; Chiu, Yu-Cheng; Chortos, Alex; Lissel, Franziska; Wang, Ging-Ji Nathan; Schroeder, Bob C.; Kurosawa, Tadanori; Lopez, Jeffrey; Katsumata, Toru; Xu, Jie; Zhu, Chenxin; Gu, Xiaodan; Bae, Won-Gyu; Kim, Yeongin; Jin, Lihua; Chung, Jong Won; Tok, Jeffrey B.-H.; Bao, Zhenan

    2016-11-01

    Thin-film field-effect transistors are essential elements of stretchable electronic devices for wearable electronics. All of the materials and components of such transistors need to be stretchable and mechanically robust. Although there has been recent progress towards stretchable conductors, the realization of stretchable semiconductors has focused mainly on strain-accommodating engineering of materials, or blending of nanofibres or nanowires into elastomers. An alternative approach relies on using semiconductors that are intrinsically stretchable, so that they can be fabricated using standard processing methods. Molecular stretchability can be enhanced when conjugated polymers, containing modified side-chains and segmented backbones, are infused with more flexible molecular building blocks. Here we present a design concept for stretchable semiconducting polymers, which involves introducing chemical moieties to promote dynamic non-covalent crosslinking of the conjugated polymers. These non-covalent crosslinking moieties are able to undergo an energy dissipation mechanism through breakage of bonds when strain is applied, while retaining high charge transport abilities. As a result, our polymer is able to recover its high field-effect mobility performance (more than 1 square centimetre per volt per second) even after a hundred cycles at 100 per cent applied strain. Organic thin-film field-effect transistors fabricated from these materials exhibited mobility as high as 1.3 square centimetres per volt per second and a high on/off current ratio exceeding a million. The field-effect mobility remained as high as 1.12 square centimetres per volt per second at 100 per cent strain along the direction perpendicular to the strain. The field-effect mobility of damaged devices can be almost fully recovered after a solvent and thermal healing treatment. Finally, we successfully fabricated a skin-inspired stretchable organic transistor operating under deformations that might be

  12. Intrinsically stretchable and healable semiconducting polymer for organic transistors.

    Science.gov (United States)

    Oh, Jin Young; Rondeau-Gagné, Simon; Chiu, Yu-Cheng; Chortos, Alex; Lissel, Franziska; Wang, Ging-Ji Nathan; Schroeder, Bob C; Kurosawa, Tadanori; Lopez, Jeffrey; Katsumata, Toru; Xu, Jie; Zhu, Chenxin; Gu, Xiaodan; Bae, Won-Gyu; Kim, Yeongin; Jin, Lihua; Chung, Jong Won; Tok, Jeffrey B-H; Bao, Zhenan

    2016-11-17

    Thin-film field-effect transistors are essential elements of stretchable electronic devices for wearable electronics. All of the materials and components of such transistors need to be stretchable and mechanically robust. Although there has been recent progress towards stretchable conductors, the realization of stretchable semiconductors has focused mainly on strain-accommodating engineering of materials, or blending of nanofibres or nanowires into elastomers. An alternative approach relies on using semiconductors that are intrinsically stretchable, so that they can be fabricated using standard processing methods. Molecular stretchability can be enhanced when conjugated polymers, containing modified side-chains and segmented backbones, are infused with more flexible molecular building blocks. Here we present a design concept for stretchable semiconducting polymers, which involves introducing chemical moieties to promote dynamic non-covalent crosslinking of the conjugated polymers. These non-covalent crosslinking moieties are able to undergo an energy dissipation mechanism through breakage of bonds when strain is applied, while retaining high charge transport abilities. As a result, our polymer is able to recover its high field-effect mobility performance (more than 1 square centimetre per volt per second) even after a hundred cycles at 100 per cent applied strain. Organic thin-film field-effect transistors fabricated from these materials exhibited mobility as high as 1.3 square centimetres per volt per second and a high on/off current ratio exceeding a million. The field-effect mobility remained as high as 1.12 square centimetres per volt per second at 100 per cent strain along the direction perpendicular to the strain. The field-effect mobility of damaged devices can be almost fully recovered after a solvent and thermal healing treatment. Finally, we successfully fabricated a skin-inspired stretchable organic transistor operating under deformations that might be

  13. REGENERATIVE TRANSISTOR AMPLIFIER

    Science.gov (United States)

    Kabell, L.J.

    1958-11-25

    Electrical circults for use in computers and the like are described. particularly a regenerative bistable transistor amplifler which is iurned on by a clock signal when an information signal permits and is turned off by the clock signal. The amplifier porforms the above function with reduced power requirements for the clock signal and circuit operation. The power requirements are reduced in one way by employing transformer coupling which increases the collector circuit efficiency by eliminating the loss of power in the collector load resistor.

  14. Nanowire structures and electrical devices

    Science.gov (United States)

    Bezryadin, Alexey; Remeika, Mikas

    2010-07-06

    The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.

  15. Bandgap engineering in a nanowire: self-assembled 0, 1 and 2D quantum structures

    Directory of Open Access Journals (Sweden)

    Jordi Arbiol

    2013-06-01

    Full Text Available Inherent to the nanowire morphology is the exciting possibility of fabricating materials organized at the nanoscale in three dimensions. Composition and structure can be varied along and across the nanowire, as well as within coaxial shells. This opens up a manifold of possibilities in nanoscale materials science and engineering which is only possible with a nanowire as a starting structure. As the variation in composition and structure is accompanied by a change in the band structure, it is possible to confine carriers within the nanowire. Interestingly, this results in the formation of local two, one and zero-dimensional structures from an electronic point of view within the nanowire. This novel palette of nano-structures paves the way toward novel applications in many engineering domains such as lasers, high-mobility transistors, quantum information and energy harvesting. In the present review we summarize and give an overview on recent achievements in the design and growth of advanced quantum structures starting from nanowire templates. The quantum structures presented have been grown by molecular beam epitaxy and correspond to different confinement approaches: quantum wells (2D, quantum wires (1D and quantum dots (0D.

  16. Modifying the band gap and optical properties of Germanium nanowires by surface termination

    Science.gov (United States)

    Legesse, Merid; Fagas, Giorgos; Nolan, Michael

    2017-02-01

    Semiconductor nanowires, based on silicon (Si) or germanium (Ge) are leading candidates for many ICT applications, including next generation transistors, optoelectronics, gas and biosensing and photovoltaics. Key to these applications is the possibility to tune the band gap by changing the diameter of the nanowire. Ge nanowires of different diameter have been studied with H termination, but, using ideas from chemistry, changing the surface terminating group can be used to modulate the band gap. In this paper we apply the generalised gradient approximation of density functional theory (GGA-DFT) and hybrid DFT to study the effect of diameter and surface termination using -H, -NH2 and -OH groups on the band gap of (001), (110) and (111) oriented germanium nanowires. We show that the surface terminating group allows both the magnitude and the nature of the band gap to be changed. We further show that the absorption edge shifts to longer wavelength with the -NH2 and -OH terminations compared to the -H termination and we trace the origin of this effect to valence band modifications upon modifying the nanowire with -NH2 or -OH. These results show that it is possible to tune the band gap of small diameter Ge nanowires over a range of ca. 1.1 eV by simple surface chemistry.

  17. n-Type Doping of Vapor–Liquid–Solid Grown GaAs Nanowires

    Directory of Open Access Journals (Sweden)

    Gutsche Christoph

    2011-01-01

    Full Text Available Abstract In this letter, n-type doping of GaAs nanowires grown by metal–organic vapor phase epitaxy in the vapor–liquid–solid growth mode on (111B GaAs substrates is reported. A low growth temperature of 400°C is adjusted in order to exclude shell growth. The impact of doping precursors on the morphology of GaAs nanowires was investigated. Tetraethyl tin as doping precursor enables heavily n-type doped GaAs nanowires in a relatively small process window while no doping effect could be found for ditertiarybutylsilane. Electrical measurements carried out on single nanowires reveal an axially non-uniform doping profile. Within a number of wires from the same run, the donor concentrations ND of GaAs nanowires are found to vary from 7 × 1017 cm-3 to 2 × 1018 cm-3. The n-type conductivity is proven by the transfer characteristics of fabricated nanowire metal–insulator-semiconductor field-effect transistor devices.

  18. Molybdenum oxide nanowires: synthesis & properties

    Directory of Open Access Journals (Sweden)

    Liqiang Mai

    2011-07-01

    Full Text Available Molybdenum oxide nanowires have been found to show promise in a diverse range of applications, ranging from electronics to energy storage and micromechanics. This review focuses on recent research on molybdenum oxide nanowires: from synthesis and device assembly to fundamental properties. The synthesis of molybdenum oxide nanowires will be reviewed, followed by a discussion of recent progress on molybdenum oxide nanowire based devices and an examination of their properties. Finally, we conclude by considering future developments.

  19. Lipid nanotube or nanowire sensor

    Science.gov (United States)

    Noy, Aleksandr; Bakajin, Olgica; Letant, Sonia; Stadermann, Michael; Artyukhin, Alexander B.

    2009-06-09

    A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or nanowire operatively connected to the gate electrode, the source electrode, and the drain electrode; a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer.

  20. Bio-functionalization of silicon carbide nanostructures for SiC nanowire-based sensors realization.

    Science.gov (United States)

    Fradetal, L; Stambouli, V; Bano, E; Pelissier, B; Choi, J H; Ollivier, M; Latu-Romain, L; Boudou, T; Pignot-Paintrand, I

    2014-05-01

    The bio-functionalization process consisting in grafting desoxyribo nucleic acid via aminopropyl-triethoxysilane is performed on several kinds of silicon carbide nanostructures. Prior, the organic layer is characterized on planar surface with fluorescence microscopy and X-ray photoelectron spectroscopy. Then, the functionalization is performed on two kinds of nanopillar arrays. One is composed of top-down SiC nanopillars with a wide pitch of 5 microm while the other one is a dense array (pitch: 200 nm) of core-shell Si-SiC nanowires obtained by carburization of silicon nanowires. Depending on both the pillar morphology and the pitch, different results in term of DNA surface coverages are obtained, as seen from fluorescence microscopy images. Particularly, in the case of the wide pitch array, it has been shown that the DNA molecules are located all along the nanopillars. To achieve a DNA sensor based on a nanowire-field effect transistor, the functionalization must be conducted on a single SiC nanowire or nanopillar that constitutes the channel of the field effect transistor. The localization of the functionalization in a small area around the nanostructures guarantees high performances to the sensor. In this aim, the functionalization process is combined with common microelectronics techniques of lithography and lift-off. The DNA immobilization is investigated by fluorescence microscopy and atomic force microscopy.

  1. Large-scale electrohydrodynamic organic nanowire printing, lithography, and electronics

    Science.gov (United States)

    Lee, Tae-Woo

    2014-03-01

    Although the many merits of organic nanowires (NWs), a reliable process for controllable and large-scale assembly of highly-aligned NW parallel arrays based on ``individual control (IC)'' of NWs must be developed since inorganic NWs are mainly grown vertically on substrates and thus have been transferred to the target substrates by any of several non-individually controlled (non-IC) methods such as contact-printing technologies with unidirectional massive alignment, and the random dispersion method with disordered alignment. Controlled alignment and patterning of individual semiconducting NWs at a desired position in a large area is a major requirement for practical electronic device applications. Large-area, high-speed printing of highly-aligned individual NWs that allows control of the exact numbers of wires, and dimensions and their orientations, and its use in high-speed large-area nanolithography is a significant challenge for practical applications. Here we use a high-speed electrohydrodynamic organic nanowire printer to print large-area organic semiconducting nanowire arrays directly on device substrates in an accurately individually-controlled manner; this method also enables sophisticated large-area nanowire lithography for nano-electronics. We achieve an unprecedented high maximum field-effect mobility up to 9.7 cm2 .V-1 .s-1 with extremely low contact resistance (<5.53 Ω . cm) even in nano-channel transistors based on single-stranded semiconducting NWs. We also demonstrate complementary inverter circuit arrays consist of well-aligned p-type and n-type organic semiconducting NWs. Extremely fast nanolithography using printed semiconducting nanowire arrays provide a very simple, reliable method of fabricating large-area and flexible nano-electronics.

  2. The Novel Semiconductor Nanowire Heterostructures

    Institute of Scientific and Technical Information of China (English)

    J.Q.Hu; Y.Bando; J.H.Zhan; D.Golberg

    2007-01-01

    1 Results If one-dimensional heterostructures with a well-defined compositional profile along the wire radial or axial direction can be realized within semiconductor nanowires, new nano-electronic devices,such as nano-waveguide and nano-capcipator, might be obtained. Here,we report the novel semiconducting nanowire heterostructures:(1) Si/ZnS side-to-side biaxial nanowires and ZnS/Si/ZnS sandwich-like triaxial nanowires[1],(2) Ga-Mg3N2 and Ga-ZnS metal-semiconductor nanowire heterojunctions[2-3]and (3) ...

  3. Nanowire mesh solar fuels generator

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Peidong; Chan, Candace; Sun, Jianwei; Liu, Bin

    2016-05-24

    This disclosure provides systems, methods, and apparatus related to a nanowire mesh solar fuels generator. In one aspect, a nanowire mesh solar fuels generator includes (1) a photoanode configured to perform water oxidation and (2) a photocathode configured to perform water reduction. The photocathode is in electrical contact with the photoanode. The photoanode may include a high surface area network of photoanode nanowires. The photocathode may include a high surface area network of photocathode nanowires. In some embodiments, the nanowire mesh solar fuels generator may include an ion conductive polymer infiltrating the photoanode and the photocathode in the region where the photocathode is in electrical contact with the photoanode.

  4. Research Update: Nanoscale electrochemical transistors in correlated oxides

    Science.gov (United States)

    Kanki, Teruo; Tanaka, Hidekazu

    2017-04-01

    Large reversible changes of the electronic transport properties of solid-state oxide materials induced by electrochemical fields have received much attention as a new research avenue in iontronics. In this research update, dramatic transport changes in vanadium dioxide (VO2) nanowires were demonstrated by electric field-induced hydrogenation at room temperature through the nanogaps separated by humid air in a field-effect transistor structure with planar-type gates. This unique structure allowed us to investigate hydrogen intercalation and diffusion behavior in VO2 channels with respect to both time and space. Our results will contribute to further strategic researches to examine fundamental chemical and physical properties of devices and develop iontronic applications, as well as offering new directions to explore emerging functions for sensing, energy, and neuromorphologic devices combining ionic and electronic behaviors in solid-state materials.

  5. A spin filter transistor made of topological Weyl semimetal

    Energy Technology Data Exchange (ETDEWEB)

    Shi, Zhangsheng; Wang, Maoji; Wu, Jiansheng, E-mail: wujs@sustc.edu.cn [Department of Physics, South University of Science and Technology of China, Shenzhen (China)

    2015-09-07

    Topological boundary states (TBSs) in Weyl semimetal (WSM) thin film can induce tunneling. Such TBSs are spin polarized inducing spin-polarized current, which can be used to build a spin-filter transistor (SFT) in spintronics. The WSM thin film can be viewed as a series of decoupled quantum anomalous Hall insulator (QAHI) wires connected in parallel, so compared with the proposed SFT made of QAHI nanowire, this SFT has a broader working energy region and easier to be manipulated. And within a narrow region outside this energy domain, the 2D WSM is with very low conductance, so it makes a good on/off switch device with controllable chemical potential induced by liquid ion gate. We also construct a loop device made of 2D WSM with inserted controllable flux to control the polarized current.

  6. Property of individual conducting-polymer nanowires: conductance and FET devices

    Science.gov (United States)

    Hashizume, Tomihiro

    2006-03-01

    Electronic devices using organic molecules and nanowires have been intensively studied in dream of a smart life utilizing charming functions of organic materials, that are thin, light, flexible and yet inexpensive and safe for environment. A key step for measuring the property of organic nanowires and evaluating the performance of the nanowire devices is how to access them by appropriate nanoscopic methods. Scanning probe microscopy (SPM) based nanofabrication (SP nanofabrication) has been used to fabricate two- or four-probe fine electrodes and several kinds of nanowires made of conducting polymers have been evaluated by SPM and the fine electrodes made with Pt thin film fabricated on SiO2/doped Si or sapphire substrates [1,2]. We have tested conductivity of single poly (3,4-ethylenedioxythiophene) / poly (styrenesulfonate) (PEDOT/PSS) nanowires. After cutting each nanowires placed on the fine electrodes, the current was checked and we were able to confirm that the conductivity was derived from the PEDOT nanowires themselves. The temperature dependence of the conductivity was explained by the quasi one-dimensional variable range hopping (VRH) model. We also will discuss on the field-effect-transistor (FET) made of a single nanowire. In collaboration with: S. Heike, M. Fujimori, Y. Suwa (ARL), H. Ichihara, S. Samitsu, A. Inomata, T. Shimomura, K. Ito (Univ. Tokyo), K. Miki, T. Ohno (NIMS), H. Mizuseki (IMR), Y. Terada, H. Shigekawa (Univ. Tsukuba). [1] J. P. Hill, W. Jin, A. Kosaka, T. Fukushima, H. Ichihara, T. Shimomura, K. Ito, T. Hashizume, N. Ishii, and T. Aida, Science 304, 1481 (2004). [2] S. Samitsu, T. Shimomura, K. Ito, S. Heike, M. Fujimori, S. Heike, and T. Hashizume, Appl. Phys. Lett., 86, 233103 (2005).

  7. Semiconductors for organic transistors

    Directory of Open Access Journals (Sweden)

    Antonio Facchetti

    2007-03-01

    Full Text Available Organic molecules/polymers with a π-conjugated (heteroaromatic backbone are capable of transporting charge and interact efficiently with light. Therefore, these systems can act as semiconductors in opto-electronic devices similar to inorganic materials. However, organic chemistry offers tools for tailoring materials' functional properties via modifications of the molecular/monomeric units, opening new possibilities for inexpensive device manufacturing. This article reviews the fundamental aspects behind the structural design/realization of p- (hole transporting and n-channel (electron-transporting semiconductors for organic field-effect transistors (OFETs. An introduction to OFET principles and history, as well as of the state-of-the-art organic semiconductor structure and performance of OFETs is provided.

  8. Piezoresistive boron doped diamond nanowire

    Science.gov (United States)

    Sumant, Anirudha V.; Wang, Xinpeng

    2016-09-13

    A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

  9. Piezoresistive boron doped diamond nanowire

    Energy Technology Data Exchange (ETDEWEB)

    Sumant, Anirudha V.; Wang, Xinpeng

    2017-07-04

    A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

  10. Group IV nanotube transistors for next generation ubiquitous computing

    KAUST Repository

    Fahad, Hossain M.

    2014-06-04

    Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However, this performance gain happens at the expense of arraying multiple devices (fins) per operation bit, due to their ultra-narrow dimensions (width) originated limited number of charges to induce appreciable amount of drive current. Additionally arraying degrades device off-state leakage and increases short channel characteristics, resulting in reduced chip level energy-efficiency. In this paper, a novel nanotube device (NTFET) topology based on conventional group IV (Si, SiGe) channel materials is discussed. This device utilizes a core/shell dual gate strategy to capitalize on the volume-inversion properties of an ultra-thin (< 10 nm) group IV nanotube channel to minimize leakage and short channel effects while maximizing performance in an area-efficient manner. It is also shown that the NTFET is capable of providing a higher output drive performance per unit chip area than an array of gate-all-around nanowires, while maintaining the leakage and short channel characteristics similar to that of a single gate-all-around nanowire, the latter being the most superior in terms of electrostatic gate control. In the age of big data and the multitude of devices contributing to the internet of things, the NTFET offers a new transistor topology alternative with maximum benefits from performance-energy efficiency-functionality perspective. © (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

  11. Magnetoimpedance of Permalloy nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Getlawi, Saleh; Gao, Haibin; Koblischka, Michael; Hartmann, Uwe [Inst. of Experimental Physics, Saarland University, P.O. Box 151150, 66041 Saarbruecken (Germany)

    2011-07-01

    The magneto-impedance (MI) effect was studied extensively on amorphous wires, ribbons, and on multilayer thin films. This effect involves huge changes of the complex impedance of soft magnetic materials upon applying an external magnetic field. In this contribution we explore the MI effect on Permalloy nanowires. Nanowires of lengths of 40-60 mu and widths of 200-400 nm were prepared by electron beam lithography (EBL) and a lift-off process. Electrodes for the transport measurements and platinum contacts were fabricated by focused-ion-beam(FIB)-based methods. Magnetic force microscopy (MFM) was employed to observe the magnetic domain structures of the nanowires. For high frequency measurement, the sample was placed on a microwave transmission line consisting of two gold microstrip lines. MI measurements were performed in the range from 10 MHz to 3 GHz.

  12. Gate-enclosed NMOS transistors

    Institute of Scientific and Technical Information of China (English)

    Fan Xue; Li Ping; Li Wei; Zhang Bin; Xie Xiaodong; Wang Gang; Hu Bin; Zhai Yahong

    2011-01-01

    In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process.By comparing the minimum W/L ratios and transistor areas,it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed.Furthermore,by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio,it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%.It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors,since it is targeted only toward the two-edged transistor.A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.

  13. Electrodeposition of Cobalt Nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Ahn, Sungbok; Hong, Kimin [Chungnam National Univ., Daejeon (Korea, Republic of)

    2013-03-15

    We developed an electroplating process of cobalt nanowires of which line-widths were between 70 and 200 nm. The plating electrolyte was made of CoSO{sub 4} and an organic additive, dimethyldithiocarbamic acid ester sodium salt (DAESA). DAESA in plating electrolytes had an accelerating effect and reduced the surface roughness of plated cobalt thin films. We obtained void-free cobalt nanowires when the plating current density was 6.25 mA/cm{sup 2} and DAESA concentration was 1 mL/L.

  14. EDITORIAL: Nanowires for energy Nanowires for energy

    Science.gov (United States)

    LaPierre, Ray; Sunkara, Mahendra

    2012-05-01

    This special issue of Nanotechnology focuses on studies illustrating the application of nanowires for energy including solar cells, efficient lighting and water splitting. Over the next three decades, nanotechnology will make significant contributions towards meeting the increased energy needs of the planet, now known as the TeraWatt challenge. Nanowires in particular are poised to contribute significantly in this development as presented in the review by Hiralal et al [1]. Nanowires exhibit light trapping properties that can act as a broadband anti-reflection coating to enhance the efficiency of solar cells. In this issue, Li et al [2] and Wang et al [3] present the optical properties of silicon nanowire and nanocone arrays. In addition to enhanced optical properties, core-shell nanowires also have the potential for efficient charge carrier collection across the nanowire diameter as presented in the contribution by Yu et al [4] for radial junction a-Si solar cells. Hybrid approaches that combine organic and inorganic materials also have potential for high efficiency photovoltaics. A Si-based hybrid solar cell is presented by Zhang et al [5] with a photoconversion efficiency of over 7%. The quintessential example of hybrid solar cells is the dye-sensitized solar cell (DSSC) where an organic absorber (dye) coats an inorganic material (typically a ZnO nanostructure). Herman et al [6] present a method of enhancing the efficiency of a DSSC by increasing the hetero-interfacial area with a unique hierarchical weeping willow ZnO structure. The increased surface area allows for higher dye loading, light harvesting, and reduced charge recombination through direct conduction along the ZnO branches. Another unique ZnO growth method is presented by Calestani et al [7] using a solution-free and catalyst-free approach by pulsed electron deposition (PED). Nanowires can also make more efficient use of electrical power. Light emitting diodes, for example, will eventually become the

  15. Semiconductor-oxide heterostructured nanowires using postgrowth oxidation.

    Science.gov (United States)

    Wallentin, Jesper; Ek, Martin; Vainorious, Neimantas; Mergenthaler, Kilian; Samuelson, Lars; Pistol, Mats-Erik; Reine Wallenberg, L; Borgström, Magnus T

    2013-01-01

    Semiconductor-oxide heterointerfaces have several electron volts high-charge carrier potential barriers, which may enable devices utilizing quantum confinement at room temperature. While a single heterointerface is easily formed by oxide deposition on a crystalline semiconductor, as in MOS transistors, the amorphous structure of most oxides inhibits epitaxy of a second semiconductor layer. Here, we overcome this limitation by separating epitaxy from oxidation, using postgrowth oxidation of AlP segments to create axial and core-shell semiconductor-oxide heterostructured nanowires. Complete epitaxial AlP-InP nanowire structures were first grown in an oxygen-free environment. Subsequent exposure to air converted the AlP segments into amorphous aluminum oxide segments, leaving isolated InP segments in an oxide matrix. InP quantum dots formed on the nanowire sidewalls exhibit room temperature photoluminescence with small line widths (down to 15 meV) and high intensity. This optical performance, together with the control of heterostructure segment length, diameter, and position, opens up for optoelectrical applications at room temperature.

  16. Lithographically patterned nanowire electrodeposition

    Science.gov (United States)

    Xiang, Chengxiang

    Lithographically patterned nanowire electrodeposition (LPNE) is a new method for fabricating polycrystalline metal nanowires using electrodeposition. In LPNE, a sacrificial metal (M1 = silver or nickel) layer, 5 - 100 nm in thickness, is first vapor deposited onto a glass, oxidized silicon, or Kapton polymer film. A photoresist (PR) layer is then deposited, photopatterned, and the exposed Ag or Ni is removed by wet etching. The etching duration is adjusted to produce an undercut ≈300 nm in width at the edges of the exposed PR. This undercut produces a horizontal trench with a precisely defined height equal to the thickness of theM1 layer. Within this trench, a nanowire of metal M2 is electrodeposited (M2 = gold, platinum, palladium, or bismuth). Finally the PR layer and M1 layer are removed. The nanowire height and width can be independently controlled down to minimum dimensions of 5 nm (h) and 11 nm (w), for example, in the case of platinum. These nanowires can be 1 cm in total length. We measure the temperature-dependent resistance of 100 um sections of Au and Pd wires in order to estimate an electrical grain size for comparison with measurements by X-ray diffraction and transmission electron microscopy. Nanowire arrays can be postpatterned to produce two-dimensional arrays of nanorods. Nanowire patterns can also be overlaid one on top of another by repeating the LPNE process twice in succession to produce, for example, arrays of low-impedance, nanowirenanowire junctions. The resistance, R, of single gold nanowires was measured in situ during electrooxidation in aqueous 0.10 M sulfuric acid. Electrooxidation caused the formation of a gold oxide that is approximately 0.8 monolayers (ML) in thickness at +1.1 V vs saturated mercurous sulfate reference electrode (MSE) based upon coulometry and ex situ X-ray photoelectron spectroscopic analysis. As the gold nanowires were electrooxidized, R increased by an amount that depended on the wire thickness, ranging from

  17. Cylindrical Field Effect Transistor: A Full Volume Inversion Device

    KAUST Repository

    Fahad, Hossain M.

    2010-12-01

    The increasing demand for high performance as well as low standby power devices has been the main reason for the aggressive scaling of conventional CMOS transistors. Current devices are at the 32nm technology node. However, due to physical limitations as well as increase in short-channel effects, leakage, power dissipation, this scaling trend cannot continue and will eventually hit a barrier. In order to overcome this, alternate device topologies have to be considered altogether. Extensive research on ultra thin body double gate FETs and gate all around nanowire FETs has shown a lot of promise. Under strong inversion, these devices have demonstrated increased performance over their bulk counterparts. This is mainly attributed to full carrier inversion in the body. However, these devices are still limited by lithographic and processing challenges making them unsuitable for commercial production. This thesis explores a unique device structure called the CFET (Cylindrical Field Effect Transistors) which also like the above, relies on complete inversion of carriers in the body/bulk. Using dual gates; an outer and an inner gate, full-volume inversion is possible with benefits such as enhanced drive currents, high Ion/Ioff ratios and reduced short channel effects.

  18. Tunnel field-effect transistors as energy-efficient electronic switches.

    Science.gov (United States)

    Ionescu, Adrian M; Riel, Heike

    2011-11-16

    Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

  19. Nanowire Photonic Systems

    Science.gov (United States)

    2009-12-22

    analogy with the etching technique used to delineate the axial p-i-n diode regions, an SEM image of the cross-section of a radial p-i-n Si-nanowire...on Adaptive Nanostructures and Nanodevices (CRANN), Dublin, Ireland Plenary Address: “The Opportunities & Challenges Facing Nanotechnology” 7

  20. Electrical characterization of chemical and dielectric passivation of InAs nanowires

    Science.gov (United States)

    Holloway, Gregory W.; Haapamaki, Chris M.; Kuyanov, Paul; LaPierre, Ray R.; Baugh, Jonathan

    2016-11-01

    The native oxide at the surface of III-V nanowires, such as InAs, can be a major source of charge noise and scattering in nanowire-based electronics, particularly for quantum devices operated at low temperatures. Surface passivation provides a means to remove the native oxide and prevent its regrowth. Here, we study the effects of surface passivation and conformal dielectric deposition by measuring electrical conductance through nanowire field effect transistors treated with a variety of surface preparations. By extracting field effect mobility, subthreshold swing, threshold shift with temperature, and the gate hysteresis for each device, we infer the relative effects of the different treatments on the factors influencing transport. It is found that a combination of chemical passivation followed by deposition of an aluminum oxide dielectric shell yields the best results compared to the other treatments, and comparable to untreated nanowires. Finally, it is shown that an entrenched, top-gated device using an optimally treated nanowire can successfully form a stable double quantum dot at low temperatures. The device has excellent electrostatic tunability owing to the conformal dielectric layer and the combination of local top gates and a global back gate.

  1. The Electrostatically Formed Nanowire: A Novel Platform for Gas-Sensing Applications

    Directory of Open Access Journals (Sweden)

    Gil Shalev

    2017-02-01

    Full Text Available The electrostatically formed nanowire (EFN gas sensor is based on a multiple-gate field-effect transistor with a conducting nanowire, which is not defined physically; rather, the nanowire is defined electrostatically post-fabrication, by using appropriate biasing of the different surrounding gates. The EFN is fabricated by using standard silicon processing technologies with relaxed design rules and, thereby, supports the realization of a low-cost and robust gas sensor, suitable for mass production. Although the smallest lithographic definition is higher than half a micrometer, appropriate tuning of the biasing of the gates concludes a conducting channel with a tunable diameter, which can transform the conducting channel into a nanowire with a diameter smaller than 20 nm. The tunable size and shape of the nanowire elicits tunable sensing parameters, such as sensitivity, limit of detection, and dynamic range, such that a single EFN gas sensor can perform with high sensitivity and a broad dynamic range by merely changing the biasing configuration. The current work reviews the design of the EFN gas sensor, its fabrication considerations and process flow, means of electrical characterization, and preliminary sensing performance at room temperature, underlying the unique and advantageous tunable capability of the device.

  2. Electro-physical characterization of individual and arrays of ZnO nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Mallampati, Bhargav [Department of Electrical Engineering, University of North Texas, 1155 Union Circle, Denton, Texas 76203 (United States); Singh, Abhay; Philipose, U. [Department of Physics, University of North Texas, 1155 Union Circle, Denton, Texas 76203 (United States); Shik, Alex; Ruda, Harry E. [Centre for Advanced Nanotechnology, University of Toronto, Toronto M5S 3E3 (Canada)

    2015-07-21

    Capacitance measurements were made on an array of parallel ZnO nanowires embedded in a polymer matrix and provided with two electrodes perpendicular to the nanowires. The capacitance monotonically increased, and saturated at large negative (depleting) and large positive (accumulating) voltages. A qualitative explanation for this behavior is presented, taking into account specific features of quasi-one-dimensional screening. The increasing or decreasing character of the capacitance-voltage characteristics were determined by the conductivity type of the nanowires, which in our case was n-type. A dispersion of the experimental capacitance was observed over the entire frequency range of 1 kHz to 5 MHz. This phenomenon is explained by the slow discharge of the nanowires through the thin dielectric layer that separates them from the top electrode. Separate measurements on individual identical nanowires in a field effect transistor configuration yielded an electron concentration and mobility of approximately 10{sup 17 }cm{sup −3} and 150 cm{sup 2}/Vs, respectively, at room temperature.

  3. Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

    Science.gov (United States)

    Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

    2016-04-26

    We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

  4. Passivated ambipolar black phosphorus transistors

    Science.gov (United States)

    Yue, Dewu; Lee, Daeyeong; Jang, Young Dae; Choi, Min Sup; Nam, Hye Jin; Jung, Duk-Young; Yoo, Won Jong

    2016-06-01

    We report the first air-passivated ambipolar BP transistor formed by applying benzyl viologen, which serves as a surface charge transfer donor for BP flakes. The passivated BP devices exhibit excellent stability under both an ambient atmosphere and vacuum; their transistor performance is maintained semi-permanently. Unlike their intrinsic p-type properties, passivated BP devices present advantageous ambipolar properties with much higher electron mobility up to ~83 cm2 V-1 s-1 from 2-terminal measurement at 300 K, compared to other reported studies on n-type BP transistors. On the basis of the n-type doping effect that originated from benzyl viologen, we also systematically investigated the BP thickness dependence of our devices on electrical properties, in which we found the best electron transport performance to be attained when an ~10 nm thick BP flake was used.We report the first air-passivated ambipolar BP transistor formed by applying benzyl viologen, which serves as a surface charge transfer donor for BP flakes. The passivated BP devices exhibit excellent stability under both an ambient atmosphere and vacuum; their transistor performance is maintained semi-permanently. Unlike their intrinsic p-type properties, passivated BP devices present advantageous ambipolar properties with much higher electron mobility up to ~83 cm2 V-1 s-1 from 2-terminal measurement at 300 K, compared to other reported studies on n-type BP transistors. On the basis of the n-type doping effect that originated from benzyl viologen, we also systematically investigated the BP thickness dependence of our devices on electrical properties, in which we found the best electron transport performance to be attained when an ~10 nm thick BP flake was used. Electronic supplementary information (ESI) available: Transfer characteristics of BP field effect transistors (BV1-BV4) (Fig. S1 and S2 and Table S1); output characteristics of BP field effect transistors in different directions (Fig. S3

  5. Nanowire growth process modeling and reliability models for nanodevices

    Science.gov (United States)

    Fathi Aghdam, Faranak

    . This work is an early attempt that uses a physical-statistical modeling approach to studying selective nanowire growth for the improvement of process yield. In the second research work, the reliability of nano-dielectrics is investigated. As electronic devices get smaller, reliability issues pose new challenges due to unknown underlying physics of failure (i.e., failure mechanisms and modes). This necessitates new reliability analysis approaches related to nano-scale devices. One of the most important nano-devices is the transistor that is subject to various failure mechanisms. Dielectric breakdown is known to be the most critical one and has become a major barrier for reliable circuit design in nano-scale. Due to the need for aggressive downscaling of transistors, dielectric films are being made extremely thin, and this has led to adopting high permittivity (k) dielectrics as an alternative to widely used SiO2 in recent years. Since most time-dependent dielectric breakdown test data on bilayer stacks show significant deviations from a Weibull trend, we have proposed two new approaches to modeling the time to breakdown of bi-layer high-k dielectrics. In the first approach, we have used a marked space-time self-exciting point process to model the defect generation rate. A simulation algorithm is used to generate defects within the dielectric space, and an optimization algorithm is employed to minimize the Kullback-Leibler divergence between the empirical distribution obtained from the real data and the one based on the simulated data to find the best parameter values and to predict the total time to failure. The novelty of the presented approach lies in using a conditional intensity for trap generation in dielectric that is a function of time, space and size of the previous defects. In addition, in the second approach, a k-out-of-n system framework is proposed to estimate the total failure time after the generation of more than one soft breakdown.

  6. Logarithmic current-measuring transistor circuits

    DEFF Research Database (Denmark)

    Højberg, Kristian Søe

    1967-01-01

    Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

  7. Gate-induced transition between metal-type and thermally activated transport in self-catalyzed MBE-grown InAs nanowires.

    Science.gov (United States)

    Blömers, C; Rieger, T; Grap, T; Raux, M; Lepsa, M I; Lüth, H; Grützmacher, D; Schäpers, Th

    2013-08-16

    Electronic transport properties of InAs nanowires are studied systematically. The nanowires are grown by molecular beam epitaxy on a SiOx-covered GaAs wafer, without using foreign catalyst particles. Room-temperature measurements revealed relatively high resistivity and low carrier concentration values, which correlate with the low background doping obtained by our growth method. Transport parameters, such as resistivity, mobility, and carrier concentration, show a relatively large spread that is attributed to variations in surface conditions. For some nanowires the conductivity has a metal-type dependence on temperature, i.e. decreasing with decreasing temperature, while other nanowires show the opposite temperature behavior, i.e. temperature-activated characteristics. An applied gate voltage in a field-effect transistor configuration can switch between the two types of behavior. The effect is explained by the presence of barriers formed by potential fluctuations.

  8. Electric Conductivity of Phosphorus Nanowires

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jing-Xiang; LI Hui; ZHANG Xue-Qing; LIEW Kim-Meow

    2009-01-01

    We present the structures and electrical transport properties of nanowires made from different strands of phosphorus chains encapsulated in carbon nanotubes. Optimized by density function theory, our results indicate that the conductance spectra reveal an oscillation dependence on the size of wires. It can be seen from the density of states and current-voltage curves that the structure of nanowires affects their properties greatly. Among them,the DNA-like double-helical phosphorus nanowire exhibits the distinct characteristic of an approximately linear I - V relationship and has a higher conductance than others. The transport properties of phosphorus nanowires are highly correlated with their microstructures.

  9. Growth and Characterization of Silicon Carbide (SiC) Nanowires by Chemical Vapor Deposition (CVD) for Electronic Device Applications

    Science.gov (United States)

    Moore, Karina

    In recent years nanowires have gained a generous amount of interest because of the possible application of nanowires within electronic devices. A nanowire is a one dimensional semiconductor nanostructure with a diameter less than 100 nm. Nanowires have the potential to be a replacement for the present day complimentary metal oxide semiconductor (CMOS) technology; it is believed by 2020, a 5--6 nm gate length within field effect transistors (FET) would be realized and cease further miniaturization of electronic devices. SiC processes several unique chemical and physical properties that make it an attractive alternative to Si as a semiconductor material. Silicon carbide's properties make it a perfect candidate for applications such as high temperature sensors, x-ray emitters and high radiation sensors. The main objective of this thesis is to successfully grow silicon carbide nanowires on silicon substrates with the assistance of a metal catalyst, by the process of chemical vapor deposition (CVD). The contributions made by the work carried out in this thesis are broad. This is the first study that has carried out a comprehensive investigation into a wide range of metal catalyst for the growth of SiC nanowires by the process of chemical vapor deposition. The study proved that the surface tension interactions between the silicon substrate and the metal catalyst are the controlling factor in the determination of the diameter of the nanowires grown. This study also proved that the silicon substrate orientation has no impact on the growth of the nanowires, similar growth patterns occurred on both Si and Si substrates. The nanowires grown were characterized by a variety of different methods including scanning electron microscopy (SEM), energy dispersive x-ray spectroscopy (EDS) and raman spectroscopy. The effect of temperature, growth temperature, growth time and the catalyst type used are investigated to determine the most suitable conditions necessary for SiC nanowire

  10. Contact resistance and overlapping capacitance in flexible sub-micron long oxide thin-film transistors for above 100 MHz operation

    Energy Technology Data Exchange (ETDEWEB)

    Münzenrieder, Niko, E-mail: muenzenrieder@ife.ee.ethz.ch; Salvatore, Giovanni A.; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Vogt, Christian; Cantarella, Giuseppe; Tröster, Gerhard [Electronics Laboratory Swiss Federal Institute of Technology (ETH) Zürich, Gloriastrasse 35, 8092 Zürich (Switzerland)

    2014-12-29

    In recent years new forms of electronic devices such as electronic papers, flexible displays, epidermal sensors, and smart textiles have become reality. Thin-film transistors (TFTs) are the basic blocks of the circuits used in such devices and need to operate above 100 MHz to efficiently treat signals in RF systems and address pixels in high resolution displays. Beyond the choice of the semiconductor, i.e., silicon, graphene, organics, or amorphous oxides, the junctionless nature of TFTs and its geometry imply some limitations which become evident and important in devices with scaled channel length. Furthermore, the mechanical instability of flexible substrates limits the feature size of flexible TFTs. Contact resistance and overlapping capacitance are two parasitic effects which limit the transit frequency of transistors. They are often considered independent, while a deeper analysis of TFTs geometry imposes to handle them together; in fact, they both depend on the overlapping length (L{sub OV}) between source/drain and the gate contacts. Here, we conduct a quantitative analysis based on a large number of flexible ultra-scaled IGZO TFTs. Devices with three different values of overlap length and channel length down to 0.5 μm are fabricated to experimentally investigate the scaling behavior of the transit frequency. Contact resistance and overlapping capacitance depend in opposite ways on L{sub OV}. These findings establish routes for the optimization of the dimension of source/drain contact pads and suggest design guidelines to achieve megahertz operation in flexible IGZO TFTs and circuits.

  11. Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

    Science.gov (United States)

    Huang, Wen-Hsien; Shieh, Jia-Min; Kao, Ming-Hsuan; Shen, Chang-Hong; Huang, Tzu-En; Wang, Hsing-Hsiang; Yang, Chih-Chao; Hsieh, Tung-Ying; Hsieh, Jin-Long; Yu, Peichen; Yeh, Wen-Kuan

    2017-02-01

    A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 × 1019 cm-3 and a narrow Raman FWHM of 3.9 cm-1. Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I on/I off ratio of 6 × 104, V th of -0.3 V, and a subthreshold swing of 237 mV/dec at V d of 1 V and DIBL of 101 mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics.

  12. Highly effective field-effect mobility amorphous InGaZnO TFT mediated by directional silver nanowire arrays.

    Science.gov (United States)

    Liu, Hung-Chuan; Lai, Yi-Chun; Lai, Chih-Chung; Wu, Bing-Shu; Zan, Hsiao-Wen; Yu, Peichen; Chueh, Yu-Lun; Tsai, Chuang-Chuang

    2015-01-14

    In this work, we demonstrate sputtered amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a record high effective field-effect mobility of 174 cm(2)/V s by incorporating silver nanowire (AgNW) arrays to channel electron transport. Compared to the reference counterpart without nanowires, the over 5-fold enhancement in the effective field-effect mobility exhibits clear dependence on the orientation as well as the surface coverage ratio of silver nanowires. Detailed material and device analyses reveal that during the room-temperature IGZO sputtering indium and oxygen diffuse into the nanowire matrix while the nanowire morphology and good contact between IGZO and nanowires are maintained. The unchanged morphology and good interfacial contact lead to high mobility and air-ambient-stable characteristics up to 3 months. Neither hysteresis nor degraded bias stress reliability is observed. The proposed AgNW-mediated a-IGZO TFTs are promising for development of large-scale, flexible, transparent electronics.

  13. Electrostatics of Silicon Nano Transistor

    Directory of Open Access Journals (Sweden)

    Lalit Singh

    2011-01-01

    Full Text Available Nano Transistor represents a unique system for exploring physical phenomena pertaining to charge transport at the nano scale and is expected to play a critical role in future evolution of electronic and optoelectronic devices. This paper summarizes some of the essential electrostatics of nano Metal Oxide Semiconductor Field effect Transistor (MOSFET and their electrical properties. Though the general focus of this work is on surface potential yet the first part presents a brief discussion of the independence of charge at the top of the barrier in the channel of MOS Transistor on Drain voltage. The quantum capacitance is discussed at length. The superposition theorem is used, thereafter, to obtain an expression for self consistent potential in the channel. Finally the I-V characteristics of the device are explored using Landauer formalism. The simulated results for a device are observed to represent the realistic behaviour of the device.

  14. Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

    Science.gov (United States)

    Buddharaju, K. D.; Singh, N.; Rustagi, S. C.; Teo, Selin H. G.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L.

    2008-09-01

    We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON-OFF transitions with high voltage-gains (e.g., ΔVOUT/ΔVIN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of VDD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-à-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.

  15. Development of self-assembling nanowires containing electronically active oligothiophenes

    Science.gov (United States)

    Tsai, Wei-Wen

    This dissertation discusses the development of conductive one-dimensional nanowires from self-assembling oligothiophene molecules. Self-assembly has been demonstrated to be a promising alternative approach towards high performance, solution processable, and low-cost organic electronics. One of the many challenges in this field is the control of supramolecular morphologies of ordered structures containing pi-conjugated moieties. This research demonstrated several successful strategies to achieve self assembly of conductive nanowires using synergistic interactions combining pi stacking and hydrogen bonding. The first approach used was to develop a hairpin-shaped sexithiophene molecule, which features two arms of the conjugated structure. The diamidocyclohexyl headgroup of this molecule successfully directs the self-assembly from hydrogen bonding among the amides, forming high-aspect-ratio one-dimensional nanowires with well-defined diameters of 3.0 +/- 0.3 nm. The molecular orientation in the nanostructures promotes formation of sexithiophene H and J aggregates that facilitate efficient charge transport. Organic field-effect transistors were fabricated to reveal improved intrinsic hole mobility from films of the nanostructures, 3.46 x 10-6 cm2V-1s-1, which is one order of magnitude higher than films cast from unassembled molecules. Bulk heterojunction solar cells were developed from this molecule and fullerenes utilizing solution-phase fabrication methods. Intimate mix of the molecule and phenyl-C61-butyric acid methyl ester creates structured interfaces for efficient exciton splitting. The charge carrier mobilities of each material are improved by self-assembly in solution and thermal-energy assisted phase separation.The photovoltaic devices achieved the highest open-circuit voltage of 0.62 V, short-circuit current of 1.79 mA/cm2, fill factor of 35%, and power conversion efficiency of 0.48%. Another strategy to one-dimensional nanowires studied here involved the

  16. Electronic components, tubes and transistors

    CERN Document Server

    Dummer, G W A

    1965-01-01

    Electronic Components, Tubes and Transistors aims to bridge the gap between the basic measurement theory of resistance, capacitance, and inductance and the practical application of electronic components in equipments. The more practical or usage aspect of electron tubes and semiconductors is given emphasis over theory. The essential characteristics of each main type of component, tube, and transistor are summarized. This book is comprised of six chapters and begins with a discussion on the essential characteristics in terms of the parameters usually required in choosing a resistor, including s

  17. Tunneling field effect transistor technology

    CERN Document Server

    Chan, Mansun

    2016-01-01

    This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

  18. Ideal Channel Field Effect Transistors

    Science.gov (United States)

    2010-03-01

    transistors and composite channel InAlAs/InGaAs/lnP/InAlAs high electron mobility transistors ( HEMTs ), which have taken the full advantage of the matched...lattice constant (or pseudomorphic growth). However, for the most popular wide bandgap semiconductor GaN and SiC, the lattice mismatch between GaN ...critical thickness of InN on GaN is about one monolayer. To marry the advantages offered by both narrow bandgap and wide bandgap semiconductors, we

  19. Superconductor-insulator transition in nanowires and nanowire arrays

    NARCIS (Netherlands)

    Mooij, J.E.; Schön, G.; Shnirman, A.; Fuse, T.; Harmans, C.J.P.M.; Rotzinger, H.; Verbruggen, A.H.

    2015-01-01

    Superconducting nanowires are the dual elements to Josephson junctions, with quantum phase-slip (QPS) processes replacing the tunneling of Cooper pairs. When the QPS amplitude ES is much smaller than the inductive energy EL, the nanowire responds as a superconducting inductor. When the inductive ene

  20. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  1. Controlling the transport properties of InAs nanowires by Si doping

    Energy Technology Data Exchange (ETDEWEB)

    Weis, Karl; Wirths, Stephan; Winden, Andreas; Sladek, Kamil; Schaepers, Thomas; Hardtdegen, Hilde; Lueth, Hans; Demarina, Nataliya; Gruetzmacher, Detlev [Institut fuer Bio- und Nanosysteme (IBN), Forschungszentrum Juelich (Germany); JARA, Fundamentals of Future Information Technology (Germany); Weirich, Thomas [Gemeinschaftslabor fuer Elektronenmikroskopie, RWTH Aachen (Germany); JARA, Fundamentals of Future Information Technology (Germany)

    2011-07-01

    InAs nanowires are attractive building blocks for nanoelectronic devices, e. g. field-effect transistors. For concrete applications, it is important to understand the interplay between their crystal structure and transport properties. By doping, the latter can be tuned. We fabricated InAs nanowires by selective-area metal-organic vapour phase epitaxy. Using Si{sub 2} H{sub 6} as a dopant, samples with five different doping levels, each set comprising 30 to 100 nanowires (typical length and diameter: 3 {mu} m and 100 nm, respectively), were prepared. From I-V measurements and field effect transistor measurements using a SiO{sub 2} back gate, we get a clear positive correlation between doping level and conductivity/carrier concentration/mobility. The conductivity can be tuned between (12.9{+-} 0.8) S/cm and (560 {+-} 120) S/cm. Furthermore, transmission electron micrographs show an influence of doping on the crystal structure of the wires. Magneto-transport measurements are performed to quantify the effect of stacking faults on the conductivity. At low temperatures around 4 K, the I-V characteristics show indications of single electron tunneling.

  2. Aging of Organic Nanowires

    DEFF Research Database (Denmark)

    Balzer, Frank; Schiek, Manuela; Osadnik, Andreas

    2012-01-01

    attribute, making them especially interesting for light generation in OLEDs and for light-harvesting devices such as solar cells. Functionalization of the molecules allows the customization of optical and electrical properties. However, aging of the wires might lead to a considerable decrease in device...... performance over time. In this study the morphological stability of organic nanoclusters and nanowires from the methoxy functionalized quaterphenylene, 4,4'''dimethoxy-1,1':4',1''4'',1'''-quaterphenylene (MOP4), is investigated in detail. Aging experiments conducted by atomic force microscopy under ambient...... conditions already expose substantial changes in sample morphology within hours. Clusters show Ostwald ripening, whereas nanowires reveal strong faceting and even fragmentation. All these aging effects are ascribed to the influence of water vapor. Decay curves (cluster number vs. time) for clusters...

  3. Indium Antimonide Nanowires: Synthesis and Properties

    Science.gov (United States)

    Shafa, Muhammad; Akbar, Sadaf; Gao, Lei; Fakhar-e-Alam, Muhammad; Wang, Zhiming M.

    2016-03-01

    This article summarizes some of the critical features of pure indium antimonide nanowires (InSb NWs) growth and their potential applications in the industry. In the first section, historical studies on the growth of InSb NWs have been presented, while in the second part, a comprehensive overview of the various synthesis techniques is demonstrated briefly. The major emphasis of current review is vapor phase deposition of NWs by manifold techniques. In addition, author review various protocols and methodologies employed to generate NWs from diverse material systems via self-organized fabrication procedures comprising chemical vapor deposition, annealing in reactive atmosphere, evaporation of InSb, molecular/ chemical beam epitaxy, solution-based techniques, and top-down fabrication method. The benefits and ill effects of the gold and self-catalyzed materials for the growth of NWs are explained at length. Afterward, in the next part, four thermodynamic characteristics of NW growth criterion concerning the expansion of NWs, growth velocity, Gibbs-Thomson effect, and growth model were expounded and discussed concisely. Recent progress in device fabrications is explained in the third part, in which the electrical and optical properties of InSb NWs were reviewed by considering the effects of conductivity which are diameter dependent and the applications of NWs in the fabrications of field-effect transistors, quantum devices, thermoelectrics, and detectors.

  4. Single quantum dot nanowire photodetectors

    NARCIS (Netherlands)

    Van Kouwen, M.P.; Van Weert, M.H.M.; Reimer, M.E.; Akopian, N.; Perinetti, U.; Algra, R.E.; Bakkers, E.P.A.M.; Kouwenhoven, L.P.; Zwiller, V.

    2010-01-01

    We report InP nanowire photodetectors with a single InAsP quantum dot as light absorbing element. With excitation above the InP band gap, the nanowire photodetectors are efficient (quantum efficiency of 4%). Under resonant excitation of the quantum dot, the photocurrent amplitude depends on the line

  5. Single quantum dot nanowire photodetectors

    NARCIS (Netherlands)

    Van Kouwen, M.P.; Van Weert, M.H.M.; Reimer, M.E.; Akopian, N.; Perinetti, U.; Algra, R.E.; Bakkers, E.P.A.M.; Kouwenhoven, L.P.; Zwiller, V.

    2010-01-01

    We report InP nanowire photodetectors with a single InAsP quantum dot as light absorbing element. With excitation above the InP band gap, the nanowire photodetectors are efficient (quantum efficiency of 4%). Under resonant excitation of the quantum dot, the photocurrent amplitude depends on the

  6. A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.

    Science.gov (United States)

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  7. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    Directory of Open Access Journals (Sweden)

    Chia-Hua Ho

    2012-03-01

    Full Text Available This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs in the conventional Complementary Metal-Oxide Semiconductor (CMOS-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH and sensitive deoxyribonucleic acid (DNA detection ability (100 pM at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window. The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  8. The four-gate transistor

    Science.gov (United States)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  9. Do Twin Boundaries Always Strengthen Metal Nanowires?

    OpenAIRE

    Zhang Yongfeng; Huang Hanchen

    2008-01-01

    Abstract It has been widely reported that twin boundaries strengthen nanowires regardless of their morphology—that is, the strength of nanowires goes up as twin spacing goes down. This article shows that twin boundaries do not always strengthen nanowires. Using classical molecular dynamics simulations, the authors show that whether twin boundaries strengthen nanowires depends on the necessary stress for dislocation nucleation, which in turn depends on surface morphologies. When nanowire...

  10. Hole-dominated transport in InSb nanowires grown on high-quality InSb films

    Science.gov (United States)

    Algarni, Zaina; George, David; Singh, Abhay; Lin, Yuankun; Philipose, U.

    2016-12-01

    We have developed an effective strategy for synthesizing p-type indium antimonide (InSb) nanowires on a thin film of InSb grown on glass substrate. The InSb films were grown by a chemical reaction between S b 2 S 3 and I n and were characterized by structural, compositional, and optical studies. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) studies reveal that the surface of the substrate is covered with a polycrystalline InSb film comprised of sub-micron sized InSb islands. Energy dispersive X-ray (EDX) results show that the film is stoichiometric InSb. The optical constants of the InSb film, characterized using a variable-angle spectroscopic ellipsometer (VASE) shows a maximum value for refractive index at 3.7 near 1.8 eV, and the extinction coefficient (k) shows a maximum value 3.3 near 4.1 eV. InSb nanowires were subsequently grown on the InSb film with 20 nm sized Au nanoparticles functioning as the metal catalyst initiating nanowire growth. The InSb nanowires with diameters in the range of 40-60 nm exhibit good crystallinity and were found to be rich in Sb. High concentrations of anions in binary semiconductors are known to introduce acceptor levels within the band gap. This un-intentional doping of the InSb nanowire resulting in hole-dominated transport in the nanowires is demonstrated by the fabrication of a p-channel nanowire field effect transistor. The hole concentration and field effect mobility are estimated to be ≈1.3 × 1017 cm-3 and 1000 cm2 V-1 s-1, respectively, at room temperature, values that are particularly attractive for the technological implications of utilizing p-InSb nanowires in CMOS electronics.

  11. A High-Voltage Level Tolerant Transistor Circuit

    NARCIS (Netherlands)

    Annema, Anne Johan; Geelen, Godefridus Johannes Gertrudis Maria

    2001-01-01

    A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) con

  12. Tunable metallic-like conductivity in microbial nanowire networks

    Science.gov (United States)

    Malvankar, Nikhil S.; Vargas, Madeline; Nevin, Kelly P.; Franks, Ashley E.; Leang, Ching; Kim, Byoung-Chan; Inoue, Kengo; Mester, Tünde; Covalla, Sean F.; Johnson, Jessica P.; Rotello, Vincent M.; Tuominen, Mark T.; Lovley, Derek R.

    2011-09-01

    Electronic nanostructures made from natural amino acids are attractive because of their relatively low cost, facile processing and absence of toxicity. However, most materials derived from natural amino acids are electronically insulating. Here, we report metallic-like conductivity in films of the bacterium Geobacter sulfurreducens and also in pilin nanofilaments (known as microbial nanowires) extracted from these bacteria. These materials have electronic conductivities of ~5 mS cm-1, which are comparable to those of synthetic metallic nanostructures. They can also conduct over distances on the centimetre scale, which is thousands of times the size of a bacterium. Moreover, the conductivity of the biofilm can be tuned by regulating gene expression, and also by varying the gate voltage in a transistor configuration. The conductivity of the nanofilaments has a temperature dependence similar to that of a disordered metal, and the conductivity could be increased by processing.

  13. Characterisation of single semiconductor nanowires by non-destructive spectroscopies

    OpenAIRE

    Secco, Eleonora

    2015-01-01

    Los nanohilos semiconductores (NWs, de su nombre inglés, nanowires) tienen una amplia gama de aplicaciones en el campo de la optoelectrónica (emisores de luz y diodos láser), nano-electrónica (circuitos lógicos y transistores de efecto de campo), y detección y producción de energía (células solares). En términos generales, los NWs pueden ser descritos como nanoestructuras de forma alargada con diámetros que van típicamente de decenas a cientos de nanómetros, y con longitudes que oscilan desde...

  14. A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism

    Science.gov (United States)

    Nigam, Kaushal; Kondekar, Pravin; Sharma, Dheeraj; Raad, Bhagwan Ram

    2016-10-01

    For the first time, a distinctive approach based on electrically doped concept is used for the formation of novel double gate tunnel field effect transistor (TFET). For this, the initially heavily doped n+ substrate is converted into n+-i-n+-i (Drain-Channel-Source) by the selection of appropriate work functions of control gate (CG) and polarity gate (PG) as 4.7 eV. Further, the formation of p+ region for source is performed by applying -1.2 V at PG. Hence, the structure behave like a n+-i-n+-p+ gated TFET, whereas, the control gate is used to modulate the effective tunneling barrier width. The physical realization of delta doped n+ layer near to source region is a challenging task for improving the device performance in terms of ON current and subthreshold slope. So, the proposed work will provide a better platform for fabrication of n+-i-n+-p+ TFET with low cost and suppressed random dopant fluctuation (RDF) effects. ATLAS TCAD device simulator is used to carry out the simulation work.

  15. Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

    Directory of Open Access Journals (Sweden)

    D.-L. Kwong

    2012-01-01

    Full Text Available This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1 CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2 a natural platform for tunneling FETs, and (3 a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1 cost reduction in photovoltaic energy conversion through enhanced light trapping and (2 a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

  16. Measurement of the electrostatic edge effect in wurtzite GaN nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Henning, Alex; Rosenwaks, Yossi [Department of Physical Electronics, School of Electrical Engineering, Tel-Aviv University, Ramat-Aviv 69978 (Israel); Klein, Benjamin [School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332 (United States); Bertness, Kris A.; Blanchard, Paul T.; Sanford, Norman A. [NIST, Physical Measurement Laboratory, Division 686, 325 Broadway, Boulder, Colorado 80305 (United States)

    2014-11-24

    The electrostatic effect of the hexagonal corner on the electronic structure in wurtzite GaN nanowires (NWs) was directly measured using Kelvin probe force microscopy (KPFM). By correlating electrostatic simulations with the measured potential difference between the nanowire face and the hexagonal vertices, the surface state concentration and band bending of GaN NWs were estimated. The surface band bending is important for an efficient design of high electron mobility transistors and for opto-electronic devices based on GaN NWs. This methodology provides a way to extract NW parameters without making assumptions concerning the electron affinity. We are taking advantage of electrostatic modeling and the high precision that KPFM offers to circumvent a major source of uncertainty in determining the surface band bending.

  17. Multiple tunnel junctions based nanowire photodetector model for single charge detection

    Science.gov (United States)

    Chatbouri, Samir; Touati, A.; Troudi, M.; Sghaier, N.; Kalboussi, A.

    2013-07-01

    In this paper we propose a new silicon nanowire photodetector model based on a single-electron transistor for single charge detection (photo-NWSET). In the first part of this work we present the two blocks of the device structure (reading and detection blocks). The presented model is consisting of two blocks capacitively coupled. The first SET (SET1) is supposed to read the charge whereas the detection block is represented by the nanowire (NW) system associated to an optical source. We modeled the NW by a series of seven islands separated by eight tunnel junctions (8TJs). In the second part of this work, we investigate the effects of photoexcitation on Id-Vg curves and we present results obtained on the output (photo-NWSET) characteristics after variation of power illumination and response time.

  18. Fluorinated alkyne-derived monolayers on oxide-free silicon nanowires via one-step hydrosilylation

    Science.gov (United States)

    Nguyen Minh, Quyen; Pujari, Sidharam P.; Wang, Bin; Wang, Zhanhua; Haick, Hossam; Zuilhof, Han; van Rijn, Cees J. M.

    2016-11-01

    Passivation of oxide-free silicon nanowires (Si NWs) by the formation of high-quality fluorinated 1-hexadecyne-derived monolayers with varying fluorine content has been investigated. Alkyl chain monolayers (C16H30-xFx) with a varying number of fluorine substituents (x = 0, 1, 3, 9, 17) were attached onto hydrogen-terminated silicon (Sisbnd H) surfaces with an effective one-step hydrosilylation. This surface chemistry gives well-defined monolayers on nanowires that have a cylindrical core-shell structure, as characterized by X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FT-IR) and static contact angle (SCA) analysis. The monolayers were stable under acidic and basic conditions, as well as under extreme conditions (such as UV exposure), and provide excellent surface passivation, which opens up applications in the fields of field effect transistors, optoelectronics and especially for disease diagnosis.

  19. Lattice dislocation in Si nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Omar, M.S., E-mail: dr_m_s_omar@yahoo.co [Department of Physics, College of Science, University of Salahaddin, Arbil, Iraqi Kurdistan (Iraq); Taha, H.T. [Department of Physics, College of Science, University of Salahaddin, Arbil, Iraqi Kurdistan (Iraq)

    2009-12-15

    Modified formulas were used to calculate lattice thermal expansion, specific heat and Bulk modulus for Si nanowires with diameters of 115, 56, 37 and 22 nm. From these values and Gruneisen parameter taken from reference, mean lattice volumes were found to be as 20.03 A{sup 3} for the bulk and 23.63, 29.91, 34.69 and 40.46 A{sup 3} for Si nanowire diameters mentioned above, respectively. Their mean bonding length was calculated to be as 0.235 nm for the bulk and 0.248, 0.269, 0.282 and 0.297 nm for the nanowires diameter mentioned above, respectively. By dividing the nanowires diameter on the mean bonding length, number of layers per each nanowire size was found to be as 230, 104, 65 and 37 for the diameters mentioned above, respectively. Lattice dislocations in 22 nm diameter wire were found to be from 0.00324 nm for the 1st central lattice to 0.2579 nm for the last surface lattice. Such dislocation was smaller for larger wire diameters. Dislocation concentration found to change in Si nanowires according to the proportionalities of surface thickness to nanowire radius ratios.

  20. H2-Assistance One-Step Growth of Si Nanowires and Their Growth Mechanism

    Institute of Scientific and Technical Information of China (English)

    QIU Ming-Xia; RUAN Shuang-Chen; GAO Biao; HUO Kai-Fu; ZHAI Jian-Pang; LI Ling; LIAO Hui; XU Xin-Tong

    2011-01-01

    Large-scale nanowires are grown on Si wafers by the catalyst-free one-step thermal reaction method in Ar/H2 mixture atmosphere at 1000℃. The x-ray diffraction and energy dispersive x-ray spectroscopy results reveal that the final nanowires are of silicon nanostructures. The Held emission scanning electron microscopy shows that these self-organized Si nanowires (SiNWs) possess curly crowns with diameters varying from 10 to 300 nm and lengths of up to several hundreds of micrometers. The transmission electron microscopy indicates that the nanowires are pure Si with amorphous structures. All the measurement results show that no silicon oxide is generated in our products. The growth mechanism is proposed tentatively. Silicon oxide is reduced into Si nanoparticles under the Ar/H2 mixture, which is the main reason for the formation of such SiNWs. Our experiments offer a method of preparing Si nanostructures by simply reducing silicon oxide at high temperature.%Large-scale nanowires are grown on Si wafers by the catalyst-free one-step thermal reaction method in Ar/H2 mixture atmosphere at 1000℃.The x-ray diffraction and energy dispersive x-ray spectroscopy results reveal that the final nanowires are of silicon nanostructures.The field emission scanning electron microscopy shows that these self-organized Si nanowires (SiNWs) possess curly crowns with diameters varying from 10 to 300nm and lengths of up to several hundreds of micrometers.The transmission electron microscopy indicates that the nanowires are pure Si with amorphous structures.All the measurement results show that no silicon oxide is generated in our products.The growth mechanism is proposed tentatively.Silicon oxide is reduced into Si nanoparticles under the Ar/H2 mixture,which is the main reason for the formation of such SiNWs.Our experiments offer a method of preparing Si nanostructures by simply reducing silicon oxide at high temperature.Silicon nanowires (SiNWs) have higher carrier mobility,a larger

  1. Coherently Strained Si-SixGe1-x Core-Shell Nanowire Heterostructures.

    Science.gov (United States)

    Dillen, David C; Wen, Feng; Kim, Kyounghwan; Tutuc, Emanuel

    2016-01-13

    Coherently strained Si-SixGe1-x core-shell nanowire heterostructures are expected to possess a positive shell-to-core conduction band offset, allowing for quantum confinement of electrons in the Si core. We report the growth of epitaxial, coherently strained Si-SixGe1-x core-shell heterostructures through the vapor-liquid-solid mechanism for the Si core, followed in situ by the epitaxial SixGe1-x shell growth using ultrahigh vacuum chemical vapor deposition. The Raman spectra of individual nanowires reveal peaks associated with the Si-Si optical phonon mode in the Si core and the Si-Si, Si-Ge, and Ge-Ge vibrational modes of the SixGe1-x shell. The core Si-Si mode displays a clear red-shift compared to unstrained, bare Si nanowires thanks to the lattice mismatch-induced tensile strain, in agreement with calculated values using a finite-element continuum elasticity model combined with lattice dynamic theory. N-type field-effect transistors using Si-SixGe1-x core-shell nanowires as channel are demonstrated.

  2. CMOS-Compatible Silicon-Nanowire-Based Coulter Counter for Cell Enumeration.

    Science.gov (United States)

    Chen, Yu; Guo, Jinhong; Muhammad, Hamidullah; Kang, Yuejun; Ary, Sunil K

    2016-02-01

    A silicon-nanowire-based Coulter counter has been designed and fabricated for particle/cell enumeration. The silicon nanowire was fabricated in a fully complementary metal-oxide-semiconductor (CMOS)-compatible process and used as a field effect transistor (FET) device. The Coulter counter device worked on the principle of potential change detection introduced by the passing of microparticles/cells through a sensing channel. Device uniformity was confirmed by scanning electron microscopy and transmission electron microscopy. Current-voltage measurement showed the high sensitivity of the nanowire FET device to the surface potential change. The results revealed that the silicon-nanowire-based Coulter counter can differentiate polystyrene beads with diameters of 8 and 15 μm. Michigan Cancer Foundation-7 (MCF-7) cells have been successfully counted to validate the device. A fully CMOS-compatible fabrication process can help the device integration and facilitate the development of sensor arrays for high throughput application. With appropriate sample preparation steps, it is also possible to expand the work to applications such as rare-cells detection.

  3. Superconductivity in nanowires

    CERN Document Server

    Bezryadin, Alexey

    2012-01-01

    The importance and actuality of nanotechnology is unabated and will be for years to come. A main challenge is to understand the various properties of certain nanostructures, and how to generate structures with specific properties for use in actual applications in Electrical Engineering and Medicine.One of the most important structures are nanowires, in particular superconducting ones. They are highly promising for future electronics, transporting current without resistance and at scales of a few nanometers. To fabricate wires to certain defined standards however, is a major challenge, and so i

  4. Fabrication of nanowire electronics on nonconventional substrates by water-assisted transfer printing method

    Science.gov (United States)

    Lee, Chi Hwan; Kim, Dong Rip; Zheng, Xiaolin

    2015-06-01

    We report a simple, versatile, and wafer-scale water-assisted transfer printing method (WTP) that enables the transfer of nanowire devices onto diverse nonconventional substrates that were not easily accessible before, such as paper, plastics, tapes, glass, polydimethylsiloxane (PDMS), aluminum foil, and ultrathin polymer substrates. The WTP method relies on the phenomenon of water penetrating into the interface between Ni and SiO2. The transfer yield is nearly 100%, and the transferred devices, including NW resistors, diodes, and field effect transistors, maintain their original geometries and electronic properties with high fidelity.

  5. Fivefold twinned boron carbide nanowires.

    Science.gov (United States)

    Fu, Xin; Jiang, Jun; Liu, Chao; Yuan, Jun

    2009-09-01

    Chemical composition and crystal structure of fivefold twinned boron carbide nanowires have been determined by electron energy-loss spectroscopy and electron diffraction. The fivefold cyclic twinning relationship is confirmed by systematic axial rotation electron diffraction. Detailed chemical analysis reveals a carbon-rich boron carbide phase. Such boron carbide nanowires are potentially interesting because of their intrinsic hardness and high temperature thermoelectric property. Together with other boron-rich compounds, they may form a set of multiply twinned nanowire systems where the misfit strain could be continuously tuned to influence their mechanical properties.

  6. Single crystalline mesoporous silicon nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Hochbaum, A.I.; Gargas, Daniel; Jeong Hwang, Yun; Yang, Peidong

    2009-08-04

    Herein we demonstrate a novel electroless etching synthesis of monolithic, single-crystalline, mesoporous silicon nanowire arrays with a high surface area and luminescent properties consistent with conventional porous silicon materials. These porous nanowires also retain the crystallographic orientation of the wafer from which they are etched. Electron microscopy and diffraction confirm their single-crystallinity and reveal the silicon surrounding the pores is as thin as several nanometers. Confocal fluorescence microscopy showed that the photoluminescence (PL) of these arrays emanate from the nanowires themselves, and their PL spectrum suggests that these arrays may be useful as photocatalytic substrates or active components of nanoscale optoelectronic devices.

  7. Low Power Band to Band Tunnel Transistors

    Science.gov (United States)

    2010-12-15

    the E-field and tunneling at the source- pocket junction you form a parasitic NPN + transistor and the injection mechanism of carriers into the...hypothesis that the 1000 ° C, 5s anneal split lead to a very wide pocket and the accidental formation of a NPN + transistor , while the 1000 ° C, 1s anneal...Low Power Band to Band Tunnel Transistors Anupama Bowonder Electrical Engineering and Computer Sciences University of California at Berkeley

  8. Single-transistor-clocked flip-flop

    Science.gov (United States)

    Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

    2005-08-30

    The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

  9. Superconducting Josephson vortex flow transistors

    CERN Document Server

    Tavares, P A C

    2002-01-01

    The work reported in this thesis focuses on the development of high-temperature superconducting Josephson vortex-flow transistors (JVFTs). The JVFT is a particular type of superconducting transistor, i.e. an electromagnetic device capable of delivering gain while keeping the control and output circuits electrically isolated. Devices were fabricated from (100) YBa sub 2 Cu sub 3 O sub 7 sub - subdelta thin films grown by Pulsed Laser Deposition on 24 deg magnesium oxide and strontium titanate bicrystals. The design of the JVFTs was guided by numerical simulations and the devices were optimised for current gain. Improvements were made to the fabrication process in order to accurately pattern the small structures required. The devices exhibited current gains higher than 60 in liquid nitrogen. Gains measured at lower temperatures were significantly higher. As part of the work a data acquisition suite was developed for the characterisation of three-terminal devices and, in particular, of JVFTs.

  10. Interactions between semiconductor nanowires and living cells.

    Science.gov (United States)

    Prinz, Christelle N

    2015-06-17

    Semiconductor nanowires are increasingly used for biological applications and their small dimensions make them a promising tool for sensing and manipulating cells with minimal perturbation. In order to interface cells with nanowires in a controlled fashion, it is essential to understand the interactions between nanowires and living cells. The present paper reviews current progress in the understanding of these interactions, with knowledge gathered from studies where living cells were interfaced with vertical nanowire arrays. The effect of nanowires on cells is reported in terms of viability, cell-nanowire interface morphology, cell behavior, changes in gene expression as well as cellular stress markers. Unexplored issues and unanswered questions are discussed.

  11. Strain- and defect-mediated thermal conductivity in silicon nanowires.

    Science.gov (United States)

    Murphy, Kathryn F; Piccione, Brian; Zanjani, Mehdi B; Lukes, Jennifer R; Gianola, Daniel S

    2014-07-09

    The unique thermal transport of insulating nanostructures is attributed to the convergence of material length scales with the mean free paths of quantized lattice vibrations known as phonons, enabling promising next-generation thermal transistors, thermal barriers, and thermoelectrics. Apart from size, strain and defects are also known to drastically affect heat transport when introduced in an otherwise undisturbed crystalline lattice. Here we report the first experimental measurements of the effect of both spatially uniform strain and point defects on thermal conductivity of an individual suspended nanowire using in situ Raman piezothermography. Our results show that whereas phononic transport in undoped Si nanowires with diameters in the range of 170-180 nm is largely unaffected by uniform elastic tensile strain, another means of disturbing a pristine lattice, namely, point defects introduced via ion bombardment, can reduce the thermal conductivity by over 70%. In addition to discerning surface- and core-governed pathways for controlling thermal transport in phonon-dominated insulators and semiconductors, we expect our novel approach to have broad applicability to a wide class of functional one- and two-dimensional nanomaterials.

  12. Gate-Sensing Coherent Charge Oscillations in a Silicon Field-Effect Transistor.

    Science.gov (United States)

    Gonzalez-Zalba, M Fernando; Shevchenko, Sergey N; Barraud, Sylvain; Johansson, J Robert; Ferguson, Andrew J; Nori, Franco; Betz, Andreas C

    2016-03-09

    Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunneling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio frequency resonant circuit coupled via the gate. Differential capacitance changes at the interdot charge transitions allow us to monitor the state of the system in the strong-driving regime where we observe the emergence of Landau-Zener-Stückelberg-Majorana interference on the phase response of the resonator. A theoretical analysis of the dispersive signal demonstrates that quantum and tunneling capacitance changes must be included to describe the qubit-resonator interaction. Furthermore, a Fourier analysis of the interference pattern reveals a charge coherence time, T2 ≈ 100 ps. Our results demonstrate charge coherent control and readout in a simple silicon transistor and open up the possibility to implement charge and spin qubits in existing CMOS technology.

  13. Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

    KAUST Repository

    Zhai, Yujia

    2012-11-26

    We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

  14. Self-Passivation by Fluorine Plasma Treatment and Low-Temperature Annealing in SiGe Nanowires for Biochemical Sensors

    Directory of Open Access Journals (Sweden)

    Kow-Ming Chang

    2014-01-01

    Full Text Available Nanowires are widely used as highly sensitive sensors for electrical detection of biological and chemical species. Modifying the band structure of strained-Si metal-oxide-semiconductor field-effect transistors by applying the in-plane tensile strain reportedly improves electron and hole mobility. The oxidation-induced Ge condensation increases the Ge fraction in a SiGe-on-insulator (SGOI and substantially increases hole mobility. However, oxidation increases the number of surface states, resulting in hole mobility degradation. In this work, 3-aminopropyltrimethoxysilane (APTMS was used as a biochemical reagent. The hydroxyl molecule on the oxide surface was replaced by the methoxy groups of the APTMS molecule. We proposed a surface plasma treatment to improve the electrical properties of SiGe nanowires. Fluorine plasma treatment can result in enhanced rates of thermal oxidation and speed up the formation of a self-passivation oxide layer. Like a capping oxide layer, the self-passivation oxide layer reduces the rate of follow-up oxidation. Preoxidation treatment also improved the sensitivity of SiGe nanowires because the Si-F binding was held at a more stable interface state compared to bare nanowire on the SiGe surface. Additionally, the sensitivity can be further improved by either the N2 plasma posttreatment or the low-temperature postannealing due to the suppression of outdiffusion of Ge and F atoms from the SiGe nanowire surface.

  15. Actuation of polypyrrole nanowires

    Science.gov (United States)

    Lee, Alexander S.; Peteu, Serban F.; Ly, James V.; Requicha, Aristides A. G.; Thompson, Mark E.; Zhou, Chongwu

    2008-04-01

    Nanoscale actuators are essential components of the NEMS (nanoelectromechanical systems) and nanorobots of the future, and are expected to become a major area of development within nanotechnology. This paper demonstrates for the first time that individual polypyrrole (PPy) nanowires with diameters under 100 nm exhibit actuation behavior, and therefore can potentially be used for constructing nanoscale actuators. PPy is an electroactive polymer which can change volume on the basis of its oxidation state. PPy-based macroscale and microscale actuators have been demonstrated, but their nanoscale counterparts have not been realized until now. The research reported here answers positively the fundamental question of whether PPy wires still exhibit useful volume changes at the nanoscale. Nanowires with a 50 nm diameter and a length of approximately 6 µm, are fabricated by chemical polymerization using track-etched polycarbonate membranes as templates. Their actuation response as a function of oxidation state is investigated by electrochemical AFM (atomic force microscopy). An estimate of the minimum actuation force is made, based on the displacement of the AFM cantilever.

  16. Actuation of polypyrrole nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Alexander S; Peteu, Serban F; Ly, James V; Requicha, Aristides A G; Thompson, Mark E; Zhou Chongwu [Laboratory for Molecular Robotics, University of Southern California, Los Angeles, CA 90089 (United States)], E-mail: requicha@usc.edu

    2008-04-23

    Nanoscale actuators are essential components of the NEMS (nanoelectromechanical systems) and nanorobots of the future, and are expected to become a major area of development within nanotechnology. This paper demonstrates for the first time that individual polypyrrole (PPy) nanowires with diameters under 100 nm exhibit actuation behavior, and therefore can potentially be used for constructing nanoscale actuators. PPy is an electroactive polymer which can change volume on the basis of its oxidation state. PPy-based macroscale and microscale actuators have been demonstrated, but their nanoscale counterparts have not been realized until now. The research reported here answers positively the fundamental question of whether PPy wires still exhibit useful volume changes at the nanoscale. Nanowires with a 50 nm diameter and a length of approximately 6 {mu}m, are fabricated by chemical polymerization using track-etched polycarbonate membranes as templates. Their actuation response as a function of oxidation state is investigated by electrochemical AFM (atomic force microscopy). An estimate of the minimum actuation force is made, based on the displacement of the AFM cantilever.

  17. Actuation of polypyrrole nanowires.

    Science.gov (United States)

    Lee, Alexander S; Peteu, Serban F; Ly, James V; Requicha, Aristides A G; Thompson, Mark E; Zhou, Chongwu

    2008-04-23

    Nanoscale actuators are essential components of the NEMS (nanoelectromechanical systems) and nanorobots of the future, and are expected to become a major area of development within nanotechnology. This paper demonstrates for the first time that individual polypyrrole (PPy) nanowires with diameters under 100 nm exhibit actuation behavior, and therefore can potentially be used for constructing nanoscale actuators. PPy is an electroactive polymer which can change volume on the basis of its oxidation state. PPy-based macroscale and microscale actuators have been demonstrated, but their nanoscale counterparts have not been realized until now. The research reported here answers positively the fundamental question of whether PPy wires still exhibit useful volume changes at the nanoscale. Nanowires with a 50 nm diameter and a length of approximately 6 µm, are fabricated by chemical polymerization using track-etched polycarbonate membranes as templates. Their actuation response as a function of oxidation state is investigated by electrochemical AFM (atomic force microscopy). An estimate of the minimum actuation force is made, based on the displacement of the AFM cantilever.

  18. Strong Ionization in carbon Nanowires

    CERN Document Server

    Kaymak, Vural; Shlyaptsev, Vyacheslav N; Rocca, Jorge J

    2015-01-01

    Surfaces covered with nanostructures, such as nanowire arrays, have shown to facilitate a significantly higher absorption of laser energy as compared to flat surfaces. Due to the efficient coupling of the laser energy, highly energetic electrons are produced, which in turn can emit intense ultrafast X-ray pulses. In the present work we use full three dimensional PIC simulations to analyze the behavior of arrays of carbon nanowires $400 nm$ in diameter, irradiated by a $\\lambda_0 = 400 nm$ laser pulse of $60 fs$ duration at FWHM and a vector potential of $a_0 = 18$. We analyze the ionization dynamics of the nanowires. We investigate the difference of the ionization strength and structure between linearly and circularly polarized laser beam. The nanowires are found to be fully ionized after about 30 laser cycles. Circularly polarized light reveals a slightly stronger ionization effect.

  19. Do Twin Boundaries Always Strengthen Metal Nanowires?

    Science.gov (United States)

    Zhang, Yongfeng; Huang, Hanchen

    2009-01-01

    It has been widely reported that twin boundaries strengthen nanowires regardless of their morphology-that is, the strength of nanowires goes up as twin spacing goes down. This article shows that twin boundaries do not always strengthen nanowires. Using classical molecular dynamics simulations, the authors show that whether twin boundaries strengthen nanowires depends on the necessary stress for dislocation nucleation, which in turn depends on surface morphologies. When nanowires are circular cylindrical, the necessary stress of dislocation nucleation is high and the presence of twin boundaries lowers this stress; twin boundaries soften nanowires. In contrast, when nanowires are square cylindrical, the necessary stress of dislocation nucleation is low, and a higher stress is required for dislocations to penetrate twin boundaries; they strengthen nanowires.

  20. Do Twin Boundaries Always Strengthen Metal Nanowires?

    Directory of Open Access Journals (Sweden)

    Zhang Yongfeng

    2008-01-01

    Full Text Available Abstract It has been widely reported that twin boundaries strengthen nanowires regardless of their morphology—that is, the strength of nanowires goes up as twin spacing goes down. This article shows that twin boundaries do not always strengthen nanowires. Using classical molecular dynamics simulations, the authors show that whether twin boundaries strengthen nanowires depends on the necessary stress for dislocation nucleation, which in turn depends on surface morphologies. When nanowires are circular cylindrical, the necessary stress of dislocation nucleation is high and the presence of twin boundaries lowers this stress; twin boundaries soften nanowires. In contrast, when nanowires are square cylindrical, the necessary stress of dislocation nucleation is low, and a higher stress is required for dislocations to penetrate twin boundaries; they strengthen nanowires.

  1. Structural and tunneling properties of Si nanowires

    KAUST Repository

    Montes Muñoz, Enrique

    2013-12-06

    We investigate the electronic structure and electron transport properties of Si nanowires attached to Au electrodes from first principles using density functional theory and the nonequilibrium Green\\'s function method. We systematically study the dependence of the transport properties on the diameter of the nanowires, on the growth direction, and on the length. At the equilibrium Au-nanowire distance we find strong electronic coupling between the electrodes and nanowires, which results in a low contact resistance. With increasing nanowire length we study the transition from metallic to tunneling conductance for small applied bias. For the tunneling regime we investigate the decay of the conductance with the nanowire length and rationalize the results using the complex band structure of the pristine nanowires. The conductance is found to depend strongly on the growth direction, with nanowires grown along the ⟨110⟩ direction showing the smallest decay with length and the largest conductance and current.

  2. Electrochemically grown rough-textured nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Tyagi, Pawan; Postetter, David; Saragnese, Daniel [Johns Hopkins University, Department of Chemical and Biomolecular Engineering (United States); Papadakis, Stergios J. [Johns Hopkins University, Applied Physics Laboratory (United States); Gracias, David H., E-mail: dgracias@jhu.ed [Johns Hopkins University, Department of Chemical and Biomolecular Engineering (United States)

    2010-03-15

    Nanowires with a rough surface texture show unusual electronic, optical, and chemical properties; however, there are only a few existing methods for producing these nanowires. Here, we describe two methods for growing both free standing and lithographically patterned gold (Au) nanowires with a rough surface texture. The first strategy is based on the deposition of nanowires from a silver (Ag)-Au plating solution mixture that precipitates an Ag-Au cyanide complex during electrodeposition at low current densities. This complex disperses in the plating solution, thereby altering the nanowire growth to yield a rough surface texture. These nanowires are mass produced in alumina membranes. The second strategy produces long and rough Au nanowires on lithographically patternable nickel edge templates with corrugations formed by partial etching. These rough nanowires can be easily arrayed and integrated with microscale devices.

  3. Controlling nanowire emission profile using conical taper

    DEFF Research Database (Denmark)

    Gregersen, Niels; Nielsen, Torben Roland; Mørk, Jesper

    2008-01-01

    The influence of a conical taper on nanowire light emission is studied. For nanowires with divergent output beams, the introduction of tapers improves the emission profile and increase the collection efficiency of the detection optics.......The influence of a conical taper on nanowire light emission is studied. For nanowires with divergent output beams, the introduction of tapers improves the emission profile and increase the collection efficiency of the detection optics....

  4. Semiconducting silicon nanowires for biomedical applications

    CERN Document Server

    Coffer, JL

    2014-01-01

    Biomedical applications have benefited greatly from the increasing interest and research into semiconducting silicon nanowires. Semiconducting Silicon Nanowires for Biomedical Applications reviews the fabrication, properties, and applications of this emerging material. The book begins by reviewing the basics, as well as the growth, characterization, biocompatibility, and surface modification, of semiconducting silicon nanowires. It goes on to focus on silicon nanowires for tissue engineering and delivery applications, including cellular binding and internalization, orthopedic tissue scaffol

  5. Operation and modeling of the MOS transistor

    CERN Document Server

    Tsividis, Yannis

    2011-01-01

    Operation and Modeling of the MOS Transistor has become a standard in academia and industry. Extensively revised and updated, the third edition of this highly acclaimed text provides a thorough treatment of the MOS transistor - the key element of modern microelectronic chips.

  6. Ultrasmall transistor-based light sources

    DEFF Research Database (Denmark)

    With Jensen, Per Baunegaard; Tavares, Luciana; Kjelstrup-Hansen, Jakob;

    Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip.......Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip....

  7. Mapping the local structure of nanowires

    DEFF Research Database (Denmark)

    Persson, Johan Mikael; Wagner, Jakob Birkedal

    2013-01-01

    . Nano Beam Electron Diffraction (NBED) is shown to be a powerful technique to reveal strain near the interface of compositional change in heterostructured semiconductor nanowires. Furthermore, the relative orientation of the nanowires is studied by means of NBED revealing the nanowires to be very...

  8. Indium Arsenide Nanowires

    DEFF Research Database (Denmark)

    Madsen, Morten Hannibal

    -ray diffraction is performed with a MBE system attached to a synchrotron beam line. The evolution in crystal structure is monitored for different growth conditions and can be correlated to post growth analysis in TEM. This type of studies gives much more detailed information on formation of the crystal structure......This thesis is about growth of Au-assisted and self-assisted InAs nanowires (NWs). The wires are synthesized using a solid source molecular beam epitaxy (MBE) system and characterized with several techniques including scanning electron microscopy (SEM), transmission electron microscopy (TEM) and x...... by a systematic study to optimize the growth conditions; first the Au deposition, then the growth temperature and finally the beam fluxes. For further control of the growth, Au droplets have been positioned with electron beam lithography and large scale arrays with a > 99 % yield have been made on 2 inch...

  9. Mechanical behaviors of nanowires

    Science.gov (United States)

    Chen, Yujie; An, Xianghai; Liao, Xiaozhou

    2017-09-01

    The mechanical behaviors of nanowires (NWs) are significantly different from those of their bulk materials because of their small dimensions. Determining the mechanical performance of NWs and understanding their deformation behavior are crucial for designing and manufacturing NW-based devices with predictable and reproducible operation. Owing to the difficulties to manipulate these nanoscale materials, nanomechanical testing of NWs is always challenging, and errors can be readily introduced in the measured mechanical data. Here, we survey the techniques that have been developed to quantify the mechanical properties and to understand the deformation mechanisms of NWs. We also provide a general review of the mechanical properties and deformation behaviors of NWs and discuss possible sources responsible for the discrepancy of measured mechanical properties. The effects of planar defects on the mechanical behavior of NWs are also reviewed.

  10. Transistor switching and sequential circuits

    CERN Document Server

    Sparkes, John J

    1969-01-01

    Transistor Switching and Sequential Circuits presents the basic ideas involved in the construction of computers, instrumentation, pulse communication systems, and automation. This book discusses the design procedure for sequential circuits. Organized into two parts encompassing eight chapters, this book begins with an overview of the ways on how to generate the types of waveforms needed in digital circuits, principally ramps, square waves, and delays. This text then considers the behavior of some simple circuits, including the inverter, the emitter follower, and the long-tailed pair. Other cha

  11. Charge transport in polymeric transistors

    Directory of Open Access Journals (Sweden)

    Alberto Salleo

    2007-03-01

    Full Text Available Polymeric semiconductors have attracted much attention because of their possible use as active materials in printed electronics. Thin-film transistors (TFTs are a convenient tool for studying charge-transport physics in conjugated polymers. Two families of materials are reviewed here: fluorene copolymers and polythiophenes. Because charge transport is highly anisotropic in molecular conductors, the electrical properties of conjugated polymers are strongly dependent on microstructure. Molecular weight, polydispersity, and regioregularity all affect morphology and charge-transport in these materials. Charge transport models based on microstructure are instrumental in identifying the electrical bottlenecks in these materials.

  12. Mechanical characterization of a single gold nanowire.

    Science.gov (United States)

    Chang, Ming; Liu, Xiaojun; Chang, Feng-Cheng; Deka, Juti R

    2013-08-01

    Mechanical properties of gold nanowires were individually determined in this investigation using a multifunctional nanomanipulator inside a scanning electron microscope (SEM). Gold nanowires were synthesized by an electrochemical deposition technique. Three different characterization techniques including tensile, buckling and bending tests were adapted to quantitatively determine Young's modulus, yield stress and failure stress of the gold nanowires. The mechanical characterizations show that the nanowires were highly flexible in nature. The excellent resilience and the ability to store elastic energy in these nanowires confirm their potential applications in nano electromechanical devices.

  13. Micromagnetic simulations of cylindrical magnetic nanowires

    KAUST Repository

    Ivanov, Yurii P.

    2015-05-27

    This chapter reviews micromagnetic simulations of cylindrical magnetic nanowires and their ordered arrays. It starts with a description of the theoretical background of micromagnetism. The chapter discusses main magnetization reversal modes, domain wall types, and state diagrams in cylindrical nanowires of different types and sizes. The results of the hysteresis process in individual nanowires and nanowire arrays also are presented. Modeling results are compared with experimental ones. The chapter also discusses future trends in nanowire applications in relation to simulations, such as current-driven dynamics, spintronics, and spincaloritronics. The main micromagnetic programs are presented and discussed, together with the corresponding links.

  14. Graphene field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Reddy, Dharmendar; Register, Leonard F; Banerjee, Sanjay K [Microelectronics Research Center, University of Texas at Austin, Austin, Texas 78758 (United States); Carpenter, Gary D [IBM Austin Research Labs, Austin, Texas 78728 (United States)

    2011-08-10

    Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron-hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm{sup 2} V{sup -1} s{sup -1}. But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications. (topical review)

  15. Graphene field-effect transistors

    Science.gov (United States)

    Reddy, Dharmendar; Register, Leonard F.; Carpenter, Gary D.; Banerjee, Sanjay K.

    2011-08-01

    Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron-hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm2 V-1 s-1. But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications.

  16. Photovoltage field-effect transistors

    Science.gov (United States)

    Adinolfi, Valerio; Sargent, Edward H.

    2017-02-01

    The detection of infrared radiation enables night vision, health monitoring, optical communications and three-dimensional object recognition. Silicon is widely used in modern electronics, but its electronic bandgap prevents the detection of light at wavelengths longer than about 1,100 nanometres. It is therefore of interest to extend the performance of silicon photodetectors into the infrared spectrum, beyond the bandgap of silicon. Here we demonstrate a photovoltage field-effect transistor that uses silicon for charge transport, but is also sensitive to infrared light owing to the use of a quantum dot light absorber. The photovoltage generated at the interface between the silicon and the quantum dot, combined with the high transconductance provided by the silicon device, leads to high gain (more than 104 electrons per photon at 1,500 nanometres), fast time response (less than 10 microseconds) and a widely tunable spectral response. Our photovoltage field-effect transistor has a responsivity that is five orders of magnitude higher at a wavelength of 1,500 nanometres than that of previous infrared-sensitized silicon detectors. The sensitization is achieved using a room-temperature solution process and does not rely on traditional high-temperature epitaxial growth of semiconductors (such as is used for germanium and III–V semiconductors). Our results show that colloidal quantum dots can be used as an efficient platform for silicon-based infrared detection, competitive with state-of-the-art epitaxial semiconductors.

  17. Photoelectrochemistry of Semiconductor Nanowire Arrays

    Energy Technology Data Exchange (ETDEWEB)

    Mallouk, Thomas E; Redwing, Joan M

    2009-11-10

    This project supported research on the growth and photoelectrochemical characterization of semiconductor nanowire arrays, and on the development of catalytic materials for visible light water splitting to produce hydrogen and oxygen. Silicon nanowires were grown in the pores of anodic aluminum oxide films by the vapor-liquid-solid technique and were characterized electrochemically. Because adventitious doping from the membrane led to high dark currents, silicon nanowire arrays were then grown on silicon substrates. The dependence of the dark current and photovoltage on preparation techniques, wire diameter, and defect density was studied for both p-silicon and p-indium phosphide nanowire arrays. The open circuit photovoltage of liquid junction cells increased with increasing wire diameter, reaching 350 mV for micron-diameter silicon wires. Liquid junction and radial p-n junction solar cells were fabricated from silicon nano- and microwire arrays and tested. Iridium oxide cluster catalysts stabilized by bidentate malonate and succinate ligands were also made and studied for the water oxidation reaction. Highlights of this project included the first papers on silicon and indium phosphide nanowire solar cells, and a new procedure for making ligand-stabilized water oxidation catalysts that can be covalently linked to molecular photosensitizers or electrode surfaces.

  18. Ballistic superconductivity in semiconductor nanowires

    Science.gov (United States)

    Zhang, Hao; Gül, Önder; Conesa-Boj, Sonia; Nowak, Michał P.; Wimmer, Michael; Zuo, Kun; Mourik, Vincent; de Vries, Folkert K.; van Veen, Jasper; de Moor, Michiel W. A.; Bommer, Jouri D. S.; van Woerkom, David J.; Car, Diana; Plissard, Sébastien R.; Bakkers, Erik P. A. M.; Quintero-Pérez, Marina; Cassidy, Maja C.; Koelling, Sebastian; Goswami, Srijit; Watanabe, Kenji; Taniguchi, Takashi; Kouwenhoven, Leo P.

    2017-07-01

    Semiconductor nanowires have opened new research avenues in quantum transport owing to their confined geometry and electrostatic tunability. They have offered an exceptional testbed for superconductivity, leading to the realization of hybrid systems combining the macroscopic quantum properties of superconductors with the possibility to control charges down to a single electron. These advances brought semiconductor nanowires to the forefront of efforts to realize topological superconductivity and Majorana modes. A prime challenge to benefit from the topological properties of Majoranas is to reduce the disorder in hybrid nanowire devices. Here we show ballistic superconductivity in InSb semiconductor nanowires. Our structural and chemical analyses demonstrate a high-quality interface between the nanowire and a NbTiN superconductor that enables ballistic transport. This is manifested by a quantized conductance for normal carriers, a strongly enhanced conductance for Andreev-reflecting carriers, and an induced hard gap with a significantly reduced density of states. These results pave the way for disorder-free Majorana devices.

  19. Voltage regulator for battery power source. [using a bipolar transistor

    Science.gov (United States)

    Black, J. M. (Inventor)

    1979-01-01

    A bipolar transistor in series with the battery as the control element also in series with a zener diode and a resistor is used to maintain a predetermined voltage until the battery voltage decays to very nearly the predetermined voltage. A field effect transistor between the base of the bipolar transistor and a junction between the zener diode and resistor regulates base current of the bipolar transistor, thereby regulating the conductivity of the bipolar transistor for control of the output voltage.

  20. Methods for synthesizing metal oxide nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Sunkara, Mahendra Kumar; Kumar, Vivekanand; Kim, Jeong H.; Clark, Ezra Lee

    2016-08-09

    A method of synthesizing a metal oxide nanowire includes the steps of: combining an amount of a transition metal or a transition metal oxide with an amount of an alkali metal compound to produce a mixture; activating a plasma discharge reactor to create a plasma discharge; exposing the mixture to the plasma discharge for a first predetermined time period such that transition metal oxide nanowires are formed; contacting the transition metal oxide nanowires with an acid solution such that an alkali metal ion is exchanged for a hydrogen ion on each of the transition metal oxide nanowires; and exposing the transition metal oxide nanowires to the plasma discharge for a second predetermined time period to thermally anneal the transition metal oxide nanowires. Transition metal oxide nanowires produced using the synthesis methods described herein are also provided.

  1. Electrically Injected UV-Visible Nanowire Lasers

    Energy Technology Data Exchange (ETDEWEB)

    Wang, George T.; Li, Changyi; Li, Qiming; Liu, Sheng; Wright, Jeremy Benjamin; Brener, Igal; Luk, Ting -Shan; Chow, Weng W.; Leung, Benjamin; Figiel, Jeffrey J.; Koleske, Daniel D.; Lu, Tzu-Ming

    2015-09-01

    There is strong interest in minimizing the volume of lasers to enable ultracompact, low-power, coherent light sources. Nanowires represent an ideal candidate for such nanolasers as stand-alone optical cavities and gain media, and optically pumped nanowire lasing has been demonstrated in several semiconductor systems. Electrically injected nanowire lasers are needed to realize actual working devices but have been elusive due to limitations of current methods to address the requirement for nanowire device heterostructures with high material quality, controlled doping and geometry, low optical loss, and efficient carrier injection. In this project we proposed to demonstrate electrically injected single nanowire lasers emitting in the important UV to visible wavelengths. Our approach to simultaneously address these challenges is based on high quality III-nitride nanowire device heterostructures with precisely controlled geometries and strong gain and mode confinement to minimize lasing thresholds, enabled by a unique top-down nanowire fabrication technique.

  2. III-Nitride nanowire optoelectronics

    Science.gov (United States)

    Zhao, Songrui; Nguyen, Hieu P. T.; Kibria, Md. G.; Mi, Zetian

    2015-11-01

    Group-III nitride nanowire structures, including GaN, InN, AlN and their alloys, have been intensively studied in the past decade. Unique to this material system is that its energy bandgap can be tuned from the deep ultraviolet (~6.2 eV for AlN) to the near infrared (~0.65 eV for InN). In this article, we provide an overview on the recent progress made in III-nitride nanowire optoelectronic devices, including light emitting diodes, lasers, photodetectors, single photon sources, intraband devices, solar cells, and artificial photosynthesis. The present challenges and future prospects of III-nitride nanowire optoelectronic devices are also discussed.

  3. Tunneling magnetoresistance in Si nanowires

    Science.gov (United States)

    Montes, E.; Rungger, I.; Sanvito, S.; Schwingenschlögl, U.

    2016-11-01

    We investigate the tunneling magnetoresistance of small diameter semiconducting Si nanowires attached to ferromagnetic Fe electrodes, using first principles density functional theory combined with the non-equilibrium Green’s functions method for quantum transport. Silicon nanowires represent an interesting platform for spin devices. They are compatible with mature silicon technology and their intrinsic electronic properties can be controlled by modifying the diameter and length. Here we systematically study the spin transport properties for neutral nanowires and both n and p doping conditions. We find a substantial low bias magnetoresistance for the neutral case, which halves for an applied voltage of about 0.35 V and persists up to 1 V. Doping in general decreases the magnetoresistance, as soon as the conductance is no longer dominated by tunneling.

  4. Tunneling magnetoresistance in Si nanowires

    KAUST Repository

    Montes Muñoz, Enrique

    2016-11-09

    We investigate the tunneling magnetoresistance of small diameter semiconducting Si nanowires attached to ferromagnetic Fe electrodes, using first principles density functional theory combined with the non-equilibrium Green\\'s functions method for quantum transport. Silicon nanowires represent an interesting platform for spin devices. They are compatible with mature silicon technology and their intrinsic electronic properties can be controlled by modifying the diameter and length. Here we systematically study the spin transport properties for neutral nanowires and both n and p doping conditions. We find a substantial low bias magnetoresistance for the neutral case, which halves for an applied voltage of about 0.35 V and persists up to 1 V. Doping in general decreases the magnetoresistance, as soon as the conductance is no longer dominated by tunneling.

  5. Basic matrix algebra and transistor circuits

    CERN Document Server

    Zelinger, G

    1963-01-01

    Basic Matrix Algebra and Transistor Circuits deals with mastering the techniques of matrix algebra for application in transistors. This book attempts to unify fundamental subjects, such as matrix algebra, four-terminal network theory, transistor equivalent circuits, and pertinent design matters. Part I of this book focuses on basic matrix algebra of four-terminal networks, with descriptions of the different systems of matrices. This part also discusses both simple and complex network configurations and their associated transmission. This discussion is followed by the alternative methods of de

  6. Atomic quantum transistor based on swapping operation

    CERN Document Server

    Moiseev, Sergey A; Moiseev, Eugene S

    2011-01-01

    We propose an atomic quantum transistor based on exchange by virtual photons between two atomic systems through the control gate-atom. The quantum transistor is realized in two QED cavities coupled in nano-optical scheme. We have found novel effect in quantum dynamics of coupled three-node atomic system which provides control-SWAP(\\theta) processes in quantum transistor operation. New possibilities of quantum entanglement in an example of bright and dark qubit states have been demonstrated for quantum transport in the atomic chain. Potentialities of the proposed nano-optical design for quantum computing and fundamental issues of multi-atomic physics are also discussed.

  7. Preliminary thermal analysis of transistor packages

    Science.gov (United States)

    Ross, L. M.; Bennett, G. A.

    1987-04-01

    Efficient thermal design of microwave power transistors is critical for realizing reliable operation of high-power modern electronic circuitry. In an effort to improve thermal performance and enhance reliability, a systematic study is made to quantify transistor package thermal behavior. A series of two-dimensional finite element thermal analyses was completed of a transistor side view. These analyses provide trends for the temperature field and internal thermal resistance components as functions of material properties and geometry. Results from the analyses are shown as isothermal contour plots, plots of temperature drop across the flange and carrier, and plots of temperature versus time.

  8. Organic and polymer transistors for electronics

    Directory of Open Access Journals (Sweden)

    Ananth Dodabalapur

    2006-04-01

    Full Text Available Some of the major application areas for organic and polymeric transistors are reviewed. Organic complementary devices are promising on account of their lower power dissipation and ease of circuit design. The first organic large-scale integrated circuits have been implemented with this circuit approach. Organic transistor backplanes are ideally suited for electronic paper applications and other display schemes. Low-cost and other processing advantages, as well as improving performance, have led to organic-based radio frequency identification tag development. The chemical interaction between various organic and polymer semiconductors can be exploited in chemical and biological sensors based upon organic transistors.

  9. Silicon nanowires as intracellular devices

    Science.gov (United States)

    Zimmerman, John F.

    Semiconductor nanowire devices are an exciting class of materials for biomedical and electrophysiology applications, with current studies primarily delivering substrate bound devices through mechanical abrasion or electroporation. However, the ability to distribute these devices in a drug-like fashion is an important step in developing next-generation active therapeutic devices. In this work, we will discuss the interaction of label free Silicon nanowires (SiNWs) with cellular systems, showing that they can be internalized in multiple cell lines, and undergo an active 'burst-like' transport process. (Abstract shortened by ProQuest.).

  10. Single crystalline mesoporous silicon nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Hochbaum, Allon; Dargas, Daniel; Hwang, Yun Jeong; Yang, Peidong

    2009-08-18

    Herein we demonstrate a novel electroless etching synthesis of monolithic, single-crystalline, mesoporous silicon nanowire arrays with a high surface area and luminescent properties consistent with conventional porous silicon materials. The photoluminescence of these nanowires suggest they are composed of crystalline silicon with small enough dimensions such that these arrays may be useful as photocatalytic substrates or active components of nanoscale optoelectronic devices. A better understanding of this electroless route to mesoporous silicon could lead to facile and general syntheses of different narrow bandgap semiconductor nanostructures for various applications.

  11. Synthesis, microstructural characterization and optical properties of CuO nanorods and nanowires obtained by aerosol assisted CVD

    Energy Technology Data Exchange (ETDEWEB)

    Lugo-Ruelas, M. [Centro de Investigación en Materiales Avanzados S.C., Laboratorio Nacional de Nanotecnología, Miguel de Cervantes No. 120, Chihuahua, Chih. C.P. 31109 (Mexico); Universidad Autónoma de Chihuahua, Facultad de Ingeniería, Circuito No. 1, Nuevo Campus Universitario, Apdo. Postal 1552, Chihuahua, Chih. C.P. 31240 (Mexico); Amézaga-Madrid, P. [Centro de Investigación en Materiales Avanzados S.C., Laboratorio Nacional de Nanotecnología, Miguel de Cervantes No. 120, Chihuahua, Chih. C.P. 31109 (Mexico); Esquivel-Pereyra, O. [Centro de Investigación en Materiales Avanzados S.C., Laboratorio Nacional de Nanotecnología, Miguel de Cervantes No. 120, Chihuahua, Chih. C.P. 31109 (Mexico); Universidad Autónoma de Chihuahua, Facultad de Ingeniería, Circuito No. 1, Nuevo Campus Universitario, Apdo. Postal 1552, Chihuahua, Chih. C.P. 31240 (Mexico); Antúnez-Flores, W.; Pizá-Ruiz, P.; Ornelas-Gutiérrez, C. [Centro de Investigación en Materiales Avanzados S.C., Laboratorio Nacional de Nanotecnología, Miguel de Cervantes No. 120, Chihuahua, Chih. C.P. 31109 (Mexico); Miki-Yoshida, M., E-mail: mario.miki@cimav.edu.mx [Centro de Investigación en Materiales Avanzados S.C., Laboratorio Nacional de Nanotecnología, Miguel de Cervantes No. 120, Chihuahua, Chih. C.P. 31109 (Mexico)

    2015-09-15

    Highlights: • Nanorods and nanowires of CuO were successfully synthesized by AACVD technique. • The carrier gas velocity was a determinant factor for the growth of nanorods or nanowires. • The increase of deposition time generates the reduction in the evenness and distribution density. • The crystalline phase of nanorods and nanowires was monoclinic tenorite. - Abstract: Copper oxide is a particularly interesting material because it presents photovoltaic, electrochemical and catalytic properties. Its unique properties are very important in the area of nanotechnology and may be an advantage because these nanomaterials can be applied in the design and manufacture of nanosensors, photocatalysis area, nanolasers switches and transistors. Nowadays one-dimensional nanostructures as nanorods, nanowires, etc., have generated a great importance and have received considerable attention and study due to their unique physical and chemical properties. In this work we report the synthesis, microstructural characterization and optical properties of CuO nanorods and nanowires grown by aerosol assisted chemical vapor deposition onto a CuO, ZnO and TiO{sub 2} thin film covered and bare borosilicate glass substrate. Concentration of the precursor solution and carrier gas flux were previously optimized and fixed at 0.1 mol dm{sup −3} and 5 L min{sup −1}, respectively. Other deposition parameters such as substrate temperature, as well the carrier gas velocity and deposition time were varied from 623 to 973 K, 0.88 to 1.77 m s{sup −1} and 11 to 16 min, respectively. Their influence on the morphology, microstructure and optical properties of the nanorods and nanowires were analyzed. The crystalline structure of the materials was characterized by grazing incidence X-ray diffraction; results indicate the presence of the tenorite phase. Surface morphology and microstructure were studied by field emission scanning electron microscopy, and high resolution transmission electron

  12. Ultrahigh density array of vertically aligned small-molecular organic nanowires on arbitrary substrates.

    Science.gov (United States)

    Starko-Bowes, Ryan; Pramanik, Sandipan

    2013-06-18

    In recent years π-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication. A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently π-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important π-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors

  13. Selective functionalization and loading of biomolecules in crystalline silicon nanotube field-effect-transistors.

    Science.gov (United States)

    Kwon, Soonshin; Chen, Zack C Y; Noh, Hyunwoo; Lee, Ju Hun; Liu, Hang; Cha, Jennifer N; Xiang, Jie

    2014-07-21

    Crystalline silicon nanotubes (Si NTs) provide distinctive advantages as electrical and biochemical analysis scaffolds through their unique morphology and electrical tunability compared to solid nanowires or amorphous/non-conductive nanotubes. Such potential is investigated in this report. Gate-dependent four-probe current-voltage analysis reveals electrical properties such as resistivity to differ by nearly 3 orders of magnitude between crystalline and amorphous Si NTs. Analysis of transistor transfer characteristics yields a field effect mobility of 40.0 cm(2) V(-1) s(-1) in crystalline Si NTs. The hollow morphology also allows selective inner/outer surface functionalization and loading capability either as a carrier for molecular targets or as a nanofluidic channel for biomolecular assays. We present for the first time a demonstration of internalization of fluorescent dyes (rhodamine) and biomolecules (BSA) in Si NTs as long as 22 μm in length.

  14. High-performance integrated field-effect transistor-based sensors.

    Science.gov (United States)

    Adzhri, R; Md Arshad, M K; Gopinath, Subash C B; Ruslinda, A R; Fathil, M F M; Ayub, R M; Nor, M Nuzaihan Mohd; Voon, C H

    2016-04-21

    Field-effect transistors (FETs) have succeeded in modern electronics in an era of computers and hand-held applications. Currently, considerable attention has been paid to direct electrical measurements, which work by monitoring changes in intrinsic electrical properties. Further, FET-based sensing systems drastically reduce cost, are compatible with CMOS technology, and ease down-stream applications. Current technologies for sensing applications rely on time-consuming strategies and processes and can only be performed under recommended conditions. To overcome these obstacles, an overview is presented here in which we specifically focus on high-performance FET-based sensor integration with nano-sized materials, which requires understanding the interaction of surface materials with the surrounding environment. Therefore, we present strategies, material depositions, device structures and other characteristics involved in FET-based devices. Special attention was given to silicon and polyaniline nanowires and graphene, which have attracted much interest due to their remarkable properties in sensing applications.

  15. In situ electrical characterization of palladium-based single electron transistors made by electromigration technique

    Directory of Open Access Journals (Sweden)

    L. Arzubiaga

    2014-11-01

    Full Text Available We report the fabrication of single electron transistors (SETs by feedback-controlled electromigration of palladium and palladium-nickel alloy nanowires. We have optimized a gradual electromigration process for obtaining devices consisting of three terminals (source, drain and gate electrodes, which are capacitively coupled to a metallic cluster of nanometric dimensions. This metal nanocluster forms into the inter-electrode channel during the electromigration process and constitutes the active element of each device, acting as a quantum dot that rules the electron flow between source and drain electrodes. The charge transport of the as-fabricated devices shows Coulomb blockade characteristics and the source to drain conductance can be modulated by electrostatic gating. We have thus achieved the fabrication and in situ measurement of palladium-based SETs inside a liquid helium cryostat chamber.

  16. Revealing the band structure of InSb nanowires by high-field magnetotransport in the quasiballistic regime

    Science.gov (United States)

    Vigneau, Florian; Gül, Önder; Niquet, Yann-Michel; Car, Diana; Plissard, Sebastien R.; Escoffier, Walter; Bakkers, Erik P. A. M.; Duchemin, Ivan; Raquet, Bertrand; Goiran, Michel

    2016-12-01

    The charge transport properties of individual InSb nanowires based transistors are studied at 4.2 K in the quasiballistic regime. The energy level separations at zero magnetic field are extracted from a bias voltage spectroscopy. The magnetoconductance under a magnetic field applied perpendicularly to the nanowire axis is investigated up to 50 T. Owing to the magnetic reduction of the backscattering, the electronic states of the quasi-one-dimensional electron gas are revealed by Landauer-Büttiker conductance quantization. The results are compared to theoretical predictions revealing the spin and orbital degeneracy lifting. At sufficiently high magnetic field the measurements show the evolution to the quantum Hall effect regime with the formation of Landau orbits and conducting edge states.

  17. Lateral nanowire/nanobelt based nanogenerators, piezotronics and piezo-phototronics

    KAUST Repository

    Wang, Zhong Lin

    2010-11-01

    Relying on the piezopotential created in ZnO under straining, nanogenerators, piezotronics and piezo-phototronics developed based on laterally bonded nanowires on a polymer substrate have been reviewed. The principle of the nanogenerator is a transient flow of electrons in external load as driven by the piezopotential created by dynamic straining. By integrating the contribution made by millions of nanowires, the output voltage has been raised to 1.2 V. Consequently, self-powered nanodevices have been demonstrated. This is an important platform technology for the future sensor network and the internet of things. Alternatively, the piezopotential can act as a gate voltage that can tune/gate the transport process of the charge carriers in the nanowire, which is a gate-electrode free field effect transistor (FET). The device fabricated based on this principle is called the piezotronic device. Piezo-phototronic effect is about the tuning and controlling of electro-optical processes by strain induced piezopotential. The piezotronic, piezophotonic and pieozo-phototronic devices are focused on low frequency applications in areas involving mechanical actions, such as MEMS/NEMS, nanorobotics, sensors, actuators and triggers. © 2010 Elsevier B.V. All rights reserved.

  18. Fluorinated alkyne-derived monolayers on oxide-free silicon nanowires via one-step hydrosilylation

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen Minh, Quyen [Laboratory of Organic Chemistry, Wageningen University, Stippeneng 4, 6708 WE Wageningen (Netherlands); Nanosens, IJsselkade 7, 7201 HB Zutphen (Netherlands); Pujari, Sidharam P. [Laboratory of Organic Chemistry, Wageningen University, Stippeneng 4, 6708 WE Wageningen (Netherlands); Wang, Bin [The Department of Chemical Engineering and Russell Berrie Nanotechnology Institute, Technion – Israel Institute of Technology, Haifa 3200003 (Israel); Wang, Zhanhua [Laboratory of Organic Chemistry, Wageningen University, Stippeneng 4, 6708 WE Wageningen (Netherlands); Haick, Hossam [The Department of Chemical Engineering and Russell Berrie Nanotechnology Institute, Technion – Israel Institute of Technology, Haifa 3200003 (Israel); Zuilhof, Han [Laboratory of Organic Chemistry, Wageningen University, Stippeneng 4, 6708 WE Wageningen (Netherlands); Rijn, Cees J.M. van, E-mail: cees.vanrijn@wur.nl [Laboratory of Organic Chemistry, Wageningen University, Stippeneng 4, 6708 WE Wageningen (Netherlands)

    2016-11-30

    Highlights: • Oxide-free H-terminated silicon nanowires undergo efficient surface modification by reaction with fluorinated 1-alkynes (HC≡C−(CH{sub 2}){sub 6}C{sub 8}H{sub 17−x}F{sub x}; x = 0–17). • These surface-modified Si NWs are chemically stable under range of conditions (including acid, base). • The surface coating yields efficient electrical passivation as demonstrated by a near-zero electrochemical activity of the surface. - Abstract: Passivation of oxide-free silicon nanowires (Si NWs) by the formation of high-quality fluorinated 1-hexadecyne-derived monolayers with varying fluorine content has been investigated. Alkyl chain monolayers (C{sub 16}H{sub 30−x}F{sub x}) with a varying number of fluorine substituents (x = 0, 1, 3, 9, 17) were attached onto hydrogen-terminated silicon (Si−H) surfaces with an effective one-step hydrosilylation. This surface chemistry gives well-defined monolayers on nanowires that have a cylindrical core–shell structure, as characterized by X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FT-IR) and static contact angle (SCA) analysis. The monolayers were stable under acidic and basic conditions, as well as under extreme conditions (such as UV exposure), and provide excellent surface passivation, which opens up applications in the fields of field effect transistors, optoelectronics and especially for disease diagnosis.

  19. Manipulation of Optoelectronic Properties and Band Structure Engineering of Ultrathin Te Nanowires by Chemical Adsorption.

    Science.gov (United States)

    Roy, Ahin; Amin, Kazi Rafsanjani; Tripathi, Shalini; Biswas, Sangram; Singh, Abhishek K; Bid, Aveek; Ravishankar, N

    2017-01-13

    Band structure engineering is a powerful technique both for the design of new semiconductor materials and for imparting new functionalities to existing ones. In this article, we present a novel and versatile technique to achieve this by surface adsorption on low dimensional systems. As a specific example, we demonstrate, through detailed experiments and ab initio simulations, the controlled modification of band structure in ultrathin Te nanowires due to NO2 adsorption. Measurements of the temperature dependence of resistivity of single ultrathin Te nanowire field-effect transistor (FET) devices exposed to increasing amounts of NO2 reveal a gradual transition from a semiconducting to a metallic state. Gradual quenching of vibrational Raman modes of Te with increasing concentration of NO2 supports the appearance of a metallic state in NO2 adsorbed Te. Ab initio simulations attribute these observations to the appearance of midgap states in NO2 adsorbed Te nanowires. Our results provide fundamental insights into the effects of ambient on the electronic structures of low-dimensional materials and can be exploited for designing novel chemical sensors.

  20. Interface engineering in organic transistors

    Directory of Open Access Journals (Sweden)

    Yeong Don Park

    2007-03-01

    Full Text Available Recent technological advances in organic field-effect transistors (OFETs have triggered intensive research into the molecular and mesoscale structures of organic semiconductor films that determine their charge-transport characteristics. Since the molecular structure and morphology of an organic semiconductor are largely determined by the properties of the interface between the organic film and the insulator, a great deal of research has focused on interface engineering. We review recent progress in interface engineering for the fabrication of high-performance OFETs and, in particular, engineering of the interfaces between semiconductors and insulators. The effects of interfacial characteristics on the molecular and mesoscale structures of π-conjugated molecules and the performance of OFET devices are discussed.

  1. Logic Gates with Ion Transistors

    CERN Document Server

    Grebel, Haim

    2016-01-01

    Electronic logic gates are the basic building blocks of every computing and micro controlling system. Logic gates are made of switches, such as diodes and transistors. Ion-selective, ionic switches may emulate electronic switches [1-8]. If we ever want to create artificial bio-chemical circuitry, then we need to move a step further towards ion-logic circuitry. Here we demonstrate ion XOR and OR gates with electrochemical cells, and specifically, with two wet-cell batteries. In parallel to vacuum tubes, the batteries were modified to include a third, permeable and conductive mid electrode (the gate), which was placed between the anode and cathode in order to affect the ion flow through it. The key is to control the cell output with a much smaller biasing power, as demonstrated here. A successful demonstration points to self-powered ion logic gates.

  2. Ionic thermoelectric gating organic transistors

    Science.gov (United States)

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (∼100 μV K−1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (∼10,000 μV K−1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins. PMID:28139738

  3. Ionic thermoelectric gating organic transistors

    Science.gov (United States)

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (~100 μV K-1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (~10,000 μV K-1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins.

  4. Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing

    Science.gov (United States)

    Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

    2015-02-01

    We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 ± 0.14 and 0.10 ± 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

  5. Logic gates based on ion transistors.

    Science.gov (United States)

    Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus

    2012-05-29

    Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.

  6. Water-gel for gating graphene transistors.

    Science.gov (United States)

    Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

    2014-05-14

    Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

  7. Scattering theory of the Johnson spin transistor

    OpenAIRE

    Geux, Linda S.; Brataas, Arne; Bauer, Gerrit E. W.

    1999-01-01

    We discuss a simple, semiclassical scattering theory for spin-dependent transport in a many-terminal formulation, with special attention to the four terminal device of Johnson referred to as spin transistor

  8. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  9. 氧对 IZO 低压无结薄膜晶体管稳定性的影响%Effect of oxygen on stability performance of the IZO junctionless thin film transistors

    Institute of Scientific and Technical Information of China (English)

    2013-01-01

      本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管,并研究了氧分压对其稳定性的影响.氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点,然而氧化物沟道层易受氧、水分子等影响,造成稳定性下降.在室温下,本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极,分析了氧压对于氧化物无结薄膜晶体管稳定性的影响.为使晶体管在低电压( 106), small subthreshold swing( 20 cm2/V·s). The study indicates that the resistivity of IZO thin-film fabricated in increasing oxygen content, leads the threshold voltage to drift in a positive direction, and makes operating mode of TFT change from depletion mode to enhanced mode.

  10. Artificial neural systems using memristive synapses and nano-crystalline silicon thin-film transistors

    Science.gov (United States)

    Cantley, Kurtis D.

    Future computer systems will not rely solely on digital processing of inputs from well-defined data sets. They will also be required to perform various computational tasks using large sets of ill-defined information from the complex environment around them. The most efficient processor of this type of information known today is the human brain. Using a large number of primitive elements (˜1010 neurons in the neocortex) with high parallel connectivity (each neuron has ˜104 synapses), brains have the remarkable ability to recognize and classify patterns, predict outcomes, and learn from and adapt to incredibly diverse sets of problems. A reasonable goal in the push to increase processing power of electronic systems would thus be to implement artificial neural networks in hardware that are compatible with today's digital processors. This work focuses on the feasibility of utilizing non-crystalline silicon devices in neuromorphic electronics. Hydrogenated amorphous silicon (a-Si:H) nanowire transistors with Schottky barrier source/drain junctions, as well as a-Si:H/Ag resistive switches are fabricated and characterized. In the transistors, it is found that the on-current scales linearly with the effective width W eff of the channel nanowire array down to at least 20 nm. The solid-state electrolyte resistive switches (memristors) are shown to exhibit the proper current-voltage hysteresis. SPICE models of similar devices are subsequently developed to investigate their performance in neural circuits. The resulting SPICE simulations demonstrate spiking properties and synaptic learning rules that are incredibly similar to those in biology. Specifically, the neuron circuits can be designed to mimic the firing characteristics of real neurons, and Hebbian learning rules are investigated. Finally, some applications are presented, including associative learning analogous to the classical conditioning experiments originally performed by Pavlov, and frequency and pattern

  11. Germanium nanowires grown using different catalyst metals

    Energy Technology Data Exchange (ETDEWEB)

    Gouveia, R.C., E-mail: riama@ifsp.edu.br [Departamento de Física – NanO Lab, Universidade Federal de São Carlos, Rod. Washington Luís, Km 235 – SP 310, São Carlos, CEP 13565-905 (Brazil); Área de Ciências, Instituto Federal de Educação Ciência e Tecnologia de São Paulo, Rua Américo Ambrósio, 269, Jd. Canaã, Sertãozinho, CEP 14169-263 (Brazil); Kamimura, H.; Munhoz, R.; Rodrigues, A.D. [Departamento de Física – NanO Lab, Universidade Federal de São Carlos, Rod. Washington Luís, Km 235 – SP 310, São Carlos, CEP 13565-905 (Brazil); Leite, E.R. [Departamento de Química – LIEC, Universidade Federal de São Carlos, São Carlos, CEP 13565-905 (Brazil); Chiquito, A.J. [Departamento de Física – NanO Lab, Universidade Federal de São Carlos, Rod. Washington Luís, Km 235 – SP 310, São Carlos, CEP 13565-905 (Brazil)

    2016-11-01

    Germanium nanowires have been synthesized by the well known vapor-liquid-solid growth mechanism using gold, silver, cooper, indium and nickel as catalyst metals. The influence of metal seeds on nanowires structural and electronic transport properties was also investigated. Electron microscopy images demonstrated that, despite differences in diameters, all nanowires obtained presented single crystalline structures. X-ray patterns showed that all nanowires were composed by germanium with a small amount of germanium oxide, and the catalyst metal was restricted at the nanowires' tips. Raman spectroscopy evidenced the long range order in the crystalline structure of each sample. Electrical measurements indicated that variable range hopping was the dominant mechanism in carrier transport for all devices, with similar hopping distance, regardless the material used as catalyst. Then, in spite of the differences in synthesis temperatures and nanowires diameters, the catalyst metals have not affected the composition and crystalline quality of the germanium nanowires nor the carrier transport in the germanium nanowire network devices. - Highlights: • Ge nanowires were grown by VLS method using Au, Ag, Cu, In and Ni as catalysts. • All nanowires presented high single crystalline quality and long range order. • Devices showed semiconducting behavior having VRH as dominant transport mechanism. • The metal catalyst did not influence structural properties or the transport mechanism.

  12. Bipolar Transistor Tester for Physics Lab

    CERN Document Server

    Baddi, Raju

    2012-01-01

    A very simple low cost bipolar transistor tester for physics lab is given. The proposed circuit not only indicates the type of transistor(NPN/PNP) but also indicates the terminals(emitter, base and collector) using simple dual colored(Red/Green) LEDs. Color diagrams of testing procedure have been given for easy following. This article describes the construction of this apparatus in all detail with schematic circuit diagram, circuit layout and constructional illustration.

  13. Hysteresis of Electronic Transport in Graphene Transistors

    OpenAIRE

    Wang, Haomin; Wu, Yihong; Cong, Chunxiao; Shang, Jingzhi; Yu, Ting

    2010-01-01

    Graphene field effect transistors commonly comprise graphene flakes lying on SiO2 surfaces. The gate-voltage dependent conductance shows hysteresis depending on the gate sweeping rate/range. It is shown here that the transistors exhibit two different kinds of hysteresis in their electrical characteristics. Charge transfer causes a positive shift in the gate voltage of the minimum conductance, while capacitive gating can cause the negative shift of conductance with respect to gate voltage. The...

  14. Floating gate transistors as biosensors (Conference Presentation)

    Science.gov (United States)

    Frisbie, C. Daniel

    2016-11-01

    Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

  15. DC operating points of transistor circuits

    Science.gov (United States)

    Trajkovic, Ljiljana

    Finding a circuit's dc operating points is an essential step in its design and involves solving systems of nonlinear algebraic equations. Of particular research and practical interests are dc analysis and simulation of electronic circuits consisting of bipolar junction and field-effect transistors (BJTs and FETs), which are building blocks of modern electronic circuits. In this paper, we survey main theoretical results related to dc operating points of transistor circuits and discuss numerical methods for their calculation.

  16. Organic and polymer transistors for electronics

    OpenAIRE

    Ananth Dodabalapur

    2006-01-01

    Some of the major application areas for organic and polymeric transistors are reviewed. Organic complementary devices are promising on account of their lower power dissipation and ease of circuit design. The first organic large-scale integrated circuits have been implemented with this circuit approach. Organic transistor backplanes are ideally suited for electronic paper applications and other display schemes. Low-cost and other processing advantages, as well as improving performance, have le...

  17. Bipolar transistor in VESTIC technology: prototype

    Science.gov (United States)

    Mierzwiński, Piotr; Kuźmicz, Wiesław; Domański, Krzysztof; Tomaszewski, Daniel; Głuszko, Grzegorz

    2016-12-01

    VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.

  18. Temas de Física para Ingeniería: El transistor de unión

    OpenAIRE

    Beléndez Vázquez, Augusto; Pastor Antón, Carlos; Martín García, Agapito

    1990-01-01

    El transistor de unión bipolar. Tensiones y corrientes en el transistor. El transistor como amplificador. El transistor como conmutador. Transistores unipolares o de efecto de campo. El tiristor. Microelectrónica y circuitos integrados.

  19. Temas de Física para Ingeniería: El transistor de unión

    OpenAIRE

    Beléndez Vázquez, Augusto; Pastor Antón, Carlos; Martín García, Agapito

    1990-01-01

    El transistor de unión bipolar. Tensiones y corrientes en el transistor. El transistor como amplificador. El transistor como conmutador. Transistores unipolares o de efecto de campo. El tiristor. Microelectrónica y circuitos integrados.

  20. Nanowire-based gas sensors

    NARCIS (Netherlands)

    Chen, X.; Wong, C.K.Y.; Yuan, C.A.; Zhang, G.

    2013-01-01

    Gas sensors fabricated with nanowires as the detecting elements are powerful due to their many improved characteristics such as high surface-to-volume ratios, ultrasensitivity, higher selectivity, low power consumption, and fast response. This paper gives an overview on the recent process of the dev

  1. Surface physics of semiconducting nanowires

    Science.gov (United States)

    Amato, Michele; Rurali, Riccardo

    2016-02-01

    Semiconducting nanowires (NWs) are firm candidates for novel nanoelectronic devices and a fruitful playground for fundamental physics. Ultra-thin nanowires, with diameters below 10 nm, present exotic quantum effects due to the confinement of the wave functions, e.g. widening of the electronic band-gap, deepening of the dopant states. However, although several reports of sub-10 nm wires exist to date, the most common NWs have diameters that range from 20 to 200 nm, where these quantum effects are absent or play a very minor role. Yet, the research activity on this field is very intense and these materials still promise to provide an important paradigm shift for the design of emerging electronic devices and different kinds of applications. A legitimate question is then: what makes a nanowire different from bulk systems? The answer is certainly the large surface-to-volume ratio. In this article we discuss the most salient features of surface physics and chemistry in group-IV semiconducting nanowires, focusing mostly on Si NWs. First we review the state-of-the-art of NW growth to achieve a smooth and controlled surface morphology. Next we discuss the importance of a proper surface passivation and its role on the NW electronic properties. Finally, stressing the importance of a large surface-to-volume ratio and emphasizing the fact that in a NW the surface is where most of the action takes place, we discuss molecular sensing and molecular doping.

  2. Nanowire-based Quantum Photonics

    NARCIS (Netherlands)

    Bulgarini, G.

    2014-01-01

    In this thesis work, I studied individual quantum dots embedded in one-dimensional nanostructures called nanowires. Amongst the effects given by the nanometric dimensions, quantum dots enable the generation of single light particles: photons. Single photon emitters and detectors are central building

  3. Optical properties of semiconducting nanowires

    NARCIS (Netherlands)

    Vugt, L.K. van

    2007-01-01

    Semiconductor nanowires of high purity and crystallinity hold promise as building blocks for opto-electronical devices at the nanoscale.. They are commonly grown via a Vapor-Liquid-Solid (VLS) mechanism in which metal (nano) droplets collect the semiconductor precursors to form a solution which, whe

  4. Single gallium nitride nanowire lasers.

    Science.gov (United States)

    Johnson, Justin C; Choi, Heon-Jin; Knutsen, Kelly P; Schaller, Richard D; Yang, Peidong; Saykally, Richard J

    2002-10-01

    There is much current interest in the optical properties of semiconductor nanowires, because the cylindrical geometry and strong two-dimensional confinement of electrons, holes and photons make them particularly attractive as potential building blocks for nanoscale electronics and optoelectronic devices, including lasersand nonlinear optical frequency converters. Gallium nitride (GaN) is a wide-bandgap semiconductor of much practical interest, because it is widely used in electrically pumped ultraviolet-blue light-emitting diodes, lasers and photodetectors. Recent progress in microfabrication techniques has allowed stimulated emission to be observed from a variety of GaN microstructures and films. Here we report the observation of ultraviolet-blue laser action in single monocrystalline GaN nanowires, using both near-field and far-field optical microscopy to characterize the waveguide mode structure and spectral properties of the radiation at room temperature. The optical microscope images reveal radiation patterns that correlate with axial Fabry-Perot modes (Q approximately 10(3)) observed in the laser spectrum, which result from the cylindrical cavity geometry of the monocrystalline nanowires. A redshift that is strongly dependent on pump power (45 meV microJ x cm(-2)) supports the idea that the electron-hole plasma mechanism is primarily responsible for the gain at room temperature. This study is a considerable advance towards the realization of electron-injected, nanowire-based ultraviolet-blue coherent light sources.

  5. GaN Nanowire Devices: Fabrication and Characterization

    Science.gov (United States)

    Scott, Reum

    The development of microelectronics in the last 25 years has been characterized by an exponential increase of the bit density in integrated circuits (ICs) with time. Scaling solid-state devices improves cost, performance, and power; as such, it is of particular interest for companies, who gain a market advantage with the latest technology. As a result, the microelectronics industry has driven transistor feature size scaling from 10 μm to ~30 nm during the past 40 years. This trend has persisted for 40 years due to optimization, new processing techniques, device structures, and materials. But when noting processor speeds from the 1970's to 2009 and then again in 2010, the implication would be that the trend has ceased. To address the challenge of shrinking the integrated circuit (IC), current research is centered on identifying new materials and devices that can supplement and/or potentially supplant it. Bottom-up methods tailor nanoscale building blocks---atoms, molecules, quantum dots, and nanowires (NWs)---to be used to overcome these limitations. The Group IIIA nitrides (InN, AlN, and GaN) possess appealing properties such as a direct band gap spanning the whole solar spectrum, high saturation velocity, and high breakdown electric field. As a result nanostructures and nanodevices made from GaN and related nitrides are suitable candidates for efficient nanoscale UV/ visible light emitters, detectors, and gas sensors. To produce devices with such small structures new fabrication methods must be implemented. Devices composed of GaN nanowires were fabricated using photolithography and electron beam lithography. The IV characteristics of these devices were noted under different illuminations and the current tripled from 4.8*10-7 A to 1.59*10 -6 A under UV light which persisted for at least 5hrs.

  6. Improving Thermoelectric Properties of Nanowires Through Inhomogeneity

    Science.gov (United States)

    González, J. Eduardo; Sánchez, Vicenta; Wang, Chumin

    2017-05-01

    Inhomogeneity in nanowires can be present in the cross-section and/or by breaking the translational symmetry along the nanowire. In particular, the quasiperiodicity introduces an unusual class of electronic and phononic transport with a singular continuous eigenvalue spectrum and critically localized wave functions. In this work, the thermoelectricity in periodic and quasiperiodically segmented nanobelts and nanowires is addressed within the Boltzmann formalism by using a real-space renormalization plus convolution method developed for the Kubo-Greenwood formula, in which tight-binding and Born models are, respectively, used for the calculation of electric and lattice thermal conductivities. For periodic nanowires, we observe a maximum of the thermoelectric figure-of-merit ( ZT) in the temperature space, as occurred in the carrier concentration space. This maximum ZT can be improved by introducing into nanowires periodically arranged segments and an inhomogeneous cross-section. Finally, the quasiperiodically segmented nanowires reveal an even larger ZT in comparison with the periodic ones.

  7. Magnetostatic Interaction in Fe-Co Nanowires

    Directory of Open Access Journals (Sweden)

    Laura Elbaile

    2012-01-01

    Full Text Available Arrays of Fe-Co alloy nanowires with diameter around 35 nm and several micrometers in length have been synthesized by codepositing Fe and Co into porous anodic alumina. The morphology, structure, and magnetic properties of the nanowires (hysteresis loops and remanence curves were characterized by SEM, TEM, X-ray diffraction (XRD, and VSM, respectively. The XRD patterns indicate that the Fe-Co nanowires present a body-centered cubic (bcc structure and a preferred (110 orientation perpendicular to the template surface. From the hysteresis loops obtained with the magnetic field applied in the axis direction of the nanowires, we can observe that the coercive field slightly decreases when the nanowire length increases. This magnetic behaviour is analyzed considering the shape anisotropy and the dipolar interactions among nanowires.

  8. High-performance integrated field-effect transistor-based sensors

    Energy Technology Data Exchange (ETDEWEB)

    Adzhri, R., E-mail: adzhri@gmail.com [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Md Arshad, M.K., E-mail: mohd.khairuddin@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); School of Microelectronic Engineering (SoME), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Gopinath, Subash C.B., E-mail: subash@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); School of Bioprocess Engineering (SBE), Universiti Malaysia Perlis (UniMAP), Arau, Perlis (Malaysia); Ruslinda, A.R., E-mail: ruslinda@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Fathil, M.F.M., E-mail: faris.fathil@gmail.com [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Ayub, R.M., E-mail: ramzan@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Nor, M. Nuzaihan Mohd, E-mail: m.nuzaihan@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Voon, C.H., E-mail: chvoon@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia)

    2016-04-21

    Field-effect transistors (FETs) have succeeded in modern electronics in an era of computers and hand-held applications. Currently, considerable attention has been paid to direct electrical measurements, which work by monitoring changes in intrinsic electrical properties. Further, FET-based sensing systems drastically reduce cost, are compatible with CMOS technology, and ease down-stream applications. Current technologies for sensing applications rely on time-consuming strategies and processes and can only be performed under recommended conditions. To overcome these obstacles, an overview is presented here in which we specifically focus on high-performance FET-based sensor integration with nano-sized materials, which requires understanding the interaction of surface materials with the surrounding environment. Therefore, we present strategies, material depositions, device structures and other characteristics involved in FET-based devices. Special attention was given to silicon and polyaniline nanowires and graphene, which have attracted much interest due to their remarkable properties in sensing applications. - Highlights: • Performance of FET-based biosensors for the detection of biomolecules is presented. • Silicon nanowire, polyaniline and graphene are the highlighted nanoscaled materials as sensing transducers. • The importance of surface material interaction with the surrounding environment is discussed. • Different device structure architectures for ease in fabrication and high sensitivity of sensing are presented.

  9. Transport Phenomena in Nanowires, Nanotubes, and Other Low-Dimensional Systems

    KAUST Repository

    Montes, Enrique

    2017-01-01

    Nanoscale materials are not new in either nature or physics. However, the recent technological improvements have given scientists new tools to understand and quantify phenomena that occur naturally due to quantum confinement effects. In general, these phenomena induce remarkable optical, magnetic, and electronic properties in nanoscale materials in contrast to their bulk counterpart. In addition, scientists have recently developed the necessary tools to control and exploit these properties in electronic devices, in particular field effect transistors, magnetic memories, and gas sensors. In the present thesis we implement theoretical and computational tools for analyzing the ground state and electronic transport properties of nanoscale materials and their performance in electronic devices. The ground state properties are studied within density functional theory using the SIESTA code, whereas the transport properties are investigated using the non-equilibrium Green\\'s functions formalism implemented in the SMEAGOL code. First we study Si-based systems, as Si nanowires are believed to be important building blocks of the next generation of electronic devices. We derive the electron transport properties of Si nanowires connected to Au electrodes and their dependence on the nanowire growth direction, diameter, and length. At equilibrium Au-nanowire distance we find strong electronic coupling between electrodes and nanowire, resulting in low contact resistance. For the tunneling regime, the decay of the conductance with the nanowire length is rationalized using the complex band structure. The nanowires grown along the (110) direction show the smallest decay and the largest conductance and current. Due to the high spin coherence in Si, Si nanowires represent an interesting platform for spin devices. Therefore, we built a magnetic tunneling junction by connecting a (110) Si nanowire to ferromagnetic Fe electrodes. We have find a substantial low bias magnetoresistance of

  10. Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

    KAUST Repository

    Li, Jingqi

    2014-07-01

    A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

  11. Magnetic crossover effect in Nickel nanowire arrays

    Energy Technology Data Exchange (ETDEWEB)

    Ghaddar, A. [Laboratoire de Magnetisme de Bretagne, CNRS-FRE 3117, C.S. 93837, 29238 Brest, Cedex (France); Gloaguen, F. [Laboratoire de Chimie, Electrochimie Moleculaire et Chimie Analytique, CNRS-UMR 6521, C. S. 93837 Brest Cedex 3 (France); Gieraltowski, J. [Laboratoire de Magnetisme de Bretagne, CNRS-FRE 3117, C.S. 93837, 29238 Brest, Cedex (France); Tannous, C., E-mail: tannous@univ-brest.f [Laboratoire de Magnetisme de Bretagne, CNRS-FRE 3117, C.S. 93837, 29238 Brest, Cedex (France)

    2011-05-01

    A crossover effect in the magnetic reversal mechanism within arrays of Nickel nanowires whose diameter varies from 15 to 100 nm is observed around 50 nm. Hysteresis loops and FMR measurements confirm that nanowire diameter controls effectively the nanowire easy axis as well as the magnetization reversal mechanism. This might be very interesting for spintronic devices based on current-induced domain motion such as non-volatile magnetic memory elements (MRAM) and low Ohmic loss devices.

  12. Electrothermal simulation of superconducting nanowire avalanche photodetectors

    Science.gov (United States)

    Marsili, Francesco; Najafi, Faraz; Herder, Charles; Berggren, Karl K.

    2011-02-01

    We developed an electrothermal model of NbN superconducting nanowire avalanche photodetectors (SNAPs) on sapphire substrates. SNAPs are single-photon detectors consisting of the parallel connection of N superconducting nanowires. We extrapolated the physical constants of the model from experimental data and we simulated the time evolution of the device resistance, temperature and current by solving two coupled electrical and thermal differential equations describing the nanowires. The predictions of the model were in good quantitative agreement with the experimental results.

  13. Preparation and characterization of haematite nanowire arrays

    CERN Document Server

    Xue, D S; Liu, Q F; Zhang, L Y

    2003-01-01

    Arrays of alpha-Fe sub 2 O sub 3 nanowires embedded in anodic alumina membranes were obtained after heat-treating beta-FeOOH nanowire arrays fabricated by electrochemical deposition. Haematite polycrystalline nanowires with maximum length of about 7 mu m and average diameter of about 120 nm were characterized by means of x-ray diffraction and transmission electron microscopy. The Morin temperature below 80 K and Neel temperature of about 350 K for the alpha-Fe sub 2 O sub 3 nanowire arrays, far lower than those of bulk material, were measured by Moessbauer spectroscopy and using a Magnetic Property Measurement System.

  14. Rational defect introduction in silicon nanowires.

    Science.gov (United States)

    Shin, Naechul; Chi, Miaofang; Howe, Jane Y; Filler, Michael A

    2013-05-08

    The controlled introduction of planar defects, particularly twin boundaries and stacking faults, in group IV nanowires remains challenging despite the prevalence of these structural features in other nanowire systems (e.g., II-VI and III-V). Here we demonstrate how user-programmable changes to precursor pressure and growth temperature can rationally generate both transverse twin boundaries and angled stacking faults during the growth of oriented Si nanowires. We leverage this new capability to demonstrate prototype defect superstructures. These findings yield important insight into the mechanism of defect generation in semiconductor nanowires and suggest new routes to engineer the properties of this ubiquitous semiconductor.

  15. Electrochemical Preparation of WO_3 Nanowire Arrays

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    1 Results Ordered WO3 nanowires arrays have been fabricated by electrochemical deposition with anodic aluminum oxide (AAO) templates and annealing the W nanowire arrays in air at 400 ℃. The morphology and the chemical composition of WO3 nanowires arrays were characterized by Scanning Electron Microscopy (SEM),Transmission Electron Microscopy (TEM), X-ray Photoelectron Spectroscopy (XPS), and X-ray diffraction (XRD). The results show that the diameters of the WO3 nanowires are about 90 nm, which is in go...

  16. Metal nanowire-graphene composite transparent electrodes

    Science.gov (United States)

    Mankowski, Trent; Zhu, Zhaozhao; Balakrishnan, Kaushik; Shikoh, Ali Sehpar; Touati, Farid; Benammar, Mohieddine; Mansuripur, Masud; Falco, Charlies M.

    2014-10-01

    Silver nanowires with 40 nm diameter and copper nanowires with 150 nm diameter were synthesized using low-temperature routes, and deposited in combination with ultrathin graphene sheets for use as transparent conductors. A systematic and detailed analysis involving nature of capping agent for the metal nanowires, annealing of deposited films, and pre-treatment of substrates revealed critical conditions necessary for preparing high performance transparent conducting electrodes. The best electrodes show ~90% optical transmissivity and sheet resistance of ~10 Ω/□, already comparable to the best available transparent electrodes. The metal nanowire-graphene composite electrodes are therefore well suited for fabrication of opto-electronic and electronic devices.

  17. Optically controllable nanobreaking of metallic nanowires

    Science.gov (United States)

    Zhou, Lina; Lu, Jinsheng; Yang, Hangbo; Luo, Si; Wang, Wei; Lv, Jun; Qiu, Min; Li, Qiang

    2017-02-01

    Nanobreaking of nanowires has shown its necessity for manufacturing integrated nanodevices as nanojoining does. In this letter, we develop a method for breaking gold pentagonal nanowires by taking advantage of the photothermal effect with a 532 nm continuous-wave (CW) laser. The critical power required for nanobreaking is much lower for perpendicular polarization than that for parallel polarization. By controlling the polarization and the power of the irradiation light for nanobreaking, the nanowires can be cut into segments with gap widths ranging from dozens of nanometers to several micrometers. This CW light-induced single point nanobreaking of metallic nanowires provides a highly useful and promising method in constructing nanosystems.

  18. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.

    2011-10-12

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  19. Transistor circuit increases range of logarithmic current amplifier

    Science.gov (United States)

    Gilmour, G.

    1966-01-01

    Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.

  20. Transport properties and nanosensors of oxide nanowires and nanobelts

    Science.gov (United States)

    Lao, Changshi

    ZnO is one of the most important materials for electronics, optoelectronics, piezoelectricity and optics. With a wide band gap of 3.37eV and an exiton binding energy of 60meV, ZnO ID nanostructures exhibit promising properties in a lot of optical device applications. It is also an important piezoelectric material and has applications in a new category of nanodevices, nano-piezotronics. Demonstrated prototype of devices includes nanogenerators, piezoelectric-FET, and a series of evolutive devices based on the concept of nanogenerator. This is based on working principle of a semiconductor and piezoelectric coupled property. This thesis is about the growth, characterization and device fabrication of ZnO nanowires and nanobelts for sensors and UV detectors. First, the fundamental synthesis of ZnO nanostructurs is investigated, particularly polar surface dominated nanostructues, to illustrate the unique growth configurations of ZnO nanobelts, nanorings and nanosprings. Detail study in this part includes nanobelts, nanorings, nanocombs, nanonetworks, and nanodiskettes synthesis. Important factors in driving the nanostructure synthesis mechanism are analyzed, such as the chemical activities of different surface of ZnO, the abundant of available Zn ions in the vapor, and the polar surface dominated effects. These factors contribute to the large abundant available ZnO nanostructures. Then, the devices fabricated methods using individual nanowires/nanobelts and their electrical transport properties were carefully characterized. In this part, dominant factors which are critical for nanobelt device performance are investigated, such as the contact properties, interface effects, and durability testing. Also, a metal doping method is studied to explore the controlling and modification of nanowire electric and optical properties. Research results obtained here provide a basic and thoroughly understanding the control process and fabrication criteria in building a functional

  1. Organic tunnel field effect transistors

    KAUST Repository

    Tietze, Max Lutz

    2017-06-29

    Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer; source (or drain) contact stacks disposed on portions of the first i-layer; a second i-layer of organic semiconductor material disposed on the first i-layer surrounding the source (or drain) contact stacks; an n-doped organic semiconductor layer disposed on the second i-layer; and a drain (or source) contact layer disposed on the n-doped organic semiconductor layer. The source (or drain) contact stacks can include a p-doped injection layer, a source (or drain) contact layer, and a contact insulating layer. In another example, a method includes disposing a first i-layer over a gate insulating layer; forming source or drain contact stacks; and disposing a second i-layer, an n-doped organic semiconductor layer, and a drain or source contact.

  2. Indium Tin Oxide@Carbon Core–Shell Nanowire and Jagged Indium Tin Oxide Nanowire

    Directory of Open Access Journals (Sweden)

    Wang Yong

    2010-01-01

    Full Text Available Abstract This paper reports two new indium tin oxide (ITO-based nanostructures, namely ITO@carbon core–shell nanowire and jagged ITO nanowire. The ITO@carbon core–shell nanowires (~50 nm in diameter, 1–5 μm in length, were prepared by a chemical vapor deposition process from commercial ITO nanoparticles. A carbon overlayer (~5–10 in thickness was observed around ITO nanowire core, which was in situ formed by the catalytic decomposition of acetylene gas. This carbon overlayer could be easily removed after calcination in air at an elevated temperature of 700°C, thus forming jagged ITO nanowires (~40–45 nm in diameter. The growth mechanisms of ITO@carbon core–shell nanowire and jagged ITO nanowire were also suggested.

  3. Radiation-induced edge effects in deep submicron CMOS transistors

    CERN Document Server

    Faccio, F

    2005-01-01

    The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

  4. Polyphosphonium-based ion bipolar junction transistors.

    Science.gov (United States)

    Gabrielsson, Erik O; Tybrandt, Klas; Berggren, Magnus

    2014-11-01

    Advancements in the field of electronics during the past few decades have inspired the use of transistors in a diversity of research fields, including biology and medicine. However, signals in living organisms are not only carried by electrons but also through fluxes of ions and biomolecules. Thus, in order to implement the transistor functionality to control biological signals, devices that can modulate currents of ions and biomolecules, i.e., ionic transistors and diodes, are needed. One successful approach for modulation of ionic currents is to use oppositely charged ion-selective membranes to form so called ion bipolar junction transistors (IBJTs). Unfortunately, overall IBJT device performance has been hindered due to the typical low mobility of ions, large geometries of the ion bipolar junction materials, and the possibility of electric field enhanced (EFE) water dissociation in the junction. Here, we introduce a novel polyphosphonium-based anion-selective material into npn-type IBJTs. The new material does not show EFE water dissociation and therefore allows for a reduction of junction length down to 2 μm, which significantly improves the switching performance of the ion transistor to 2 s. The presented improvement in speed as well the simplified design will be useful for future development of advanced iontronic circuits employing IBJTs, for example, addressable drug-delivery devices.

  5. Hafnium transistor design for neural interfacing.

    Science.gov (United States)

    Parent, David W; Basham, Eric J

    2008-01-01

    A design methodology is presented that uses the EKV model and the g(m)/I(D) biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.

  6. High Accuracy Transistor Compact Model Calibrations

    Energy Technology Data Exchange (ETDEWEB)

    Hembree, Charles E. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Mar, Alan [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Robertson, Perry J. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

    2015-09-01

    Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.

  7. Growth mechanism and quantum confinement effect of silicon nanowires

    Institute of Scientific and Technical Information of China (English)

    冯孙齐; 俞大鹏; 张洪洲; 白志刚; 丁彧; 杭青岭; 邹英华; 王晶晶

    1999-01-01

    The methods for synthesizing one-dimensional Si nanowires with controlled diameter are introduced. The mechanism for the growth of Si nanowires and the growth model for different morphologies of Si nanowires are described, and the quantum confinement effect of the Si nanowires is presented.

  8. Discrete transistor measuring and matching using a solid core oven.

    Science.gov (United States)

    Inkinen, M; Mäkelä, K; Vuorela, T; Palovuori, K

    2013-03-01

    This paper presents transistor measurements done at a constant temperature. The aim in this research was to develop a reliable and repeatable method for measuring and searching transistor pairs with similar parameters, as in certain applications it is advantageous to use transistors from the same production batch due to the significant variability in batches from different manufacturers. Transistor manufacturing methods are well established, but due to the large variability in tolerance, not even transistors from the same manufacturing batch have identical properties. Transistors' electrical properties are also strongly temperature-dependent. Therefore, when measuring transistor properties, the temperature must be kept constant. For the measurement process, a solid-core oven providing stable temperature was implemented. In the oven, the base-to-emitter voltage (VBE) and DC-current gain (β) of 32 transistors could be measured simultaneously. The oven's temperature was controlled with a programmable thermostat, which allowed accurate constant temperature operation. The oven is formed by a large metal block with an individual chamber for each transistor to be measured. Isolation of individual transistors and the highly thermally conductive metal core structure prevent thermal coupling between transistors. The oven enables repeatable measurements, and thus measurements between different batches are comparable. In this research study, the properties of over 5000 transistors were measured and the variance of the aforementioned properties was analyzed.

  9. Fabrication of nanowires and nanostructures

    DEFF Research Database (Denmark)

    Mátéfi-Tempfli, Stefan; Mátéfi-Tempfli, M.; Piraux, L.

    2009-01-01

    We report on different approaches that we have adopted and developed for the fabrication of nanowires and nanostructures. Methods based on template synthesis and on self organization seem to be the most promising for the fabrication of nanomaterials and nanostructures due to their easiness and low...... cost. The development of a supported nanoporous alumina template and the possibility of using this template to combine electrochemical synthesis with lithographic methods open new ways for the fabrication of complex nanostructures. The numerous advantages of the supported template and its compatibility...... with microelectronic processes make it an ideal candidate for further integration into large-scale fabrication of various nanowire-based devices. © 2009 Springer-Verlag....

  10. Nanowire sensors and arrays for chemical/biomolecule detection

    Science.gov (United States)

    Yun, Minhee; Lee, Choonsup; Vasquez, Richard P.; Ramanathan, K.; Bangar, M. A.; Chen, W.; Mulchandan, A.; Myung, N. V.

    2005-01-01

    We report electrochemical growth of single nanowire based sensors using e-beam patterned electrolyte channels, potentially enabling the controlled fabrication of individually addressable high density arrays. The electrodeposition technique results in nanowires with controlled dimensions, positions, alignments, and chemical compositions. Using this technique, we have fabricated single palladium nanowires with diameters ranging between 75 nm and 300 nm and conducting polymer nanowires (polypyrrole and polyaniline) with diameters between 100 nm and 200 nm. Using these single nanowires, we have successfully demonstrated gas sensing with Pd nanowires and pH sensing with polypirrole nanowires.

  11. Diamond Nanowire for UV Detection

    Science.gov (United States)

    2010-02-28

    02/28/2010 6. Program Manager: Dr. Donald Silversmith , yr. 1- yr.3, and Dr. Brian Thomas, yr. 3. 7. Distribution Statement (as on SF-298...if any): None 11. Change in AFOSR program manager, if any: It was in the program managed by Dr. Donald Silversmith . In yr-3 it was transitioned to...NANOWIRE FOR UV DETECTION FA9550-07-1-0140 To Dr. Donald Silversmith and Dr. Brian Thomas AFOSR PI: Jimmy Xu Brown University 184 Hope St

  12. III–V Nanowire Surfaces

    OpenAIRE

    Hjort, Martin

    2014-01-01

    This dissertation deals with the geometric and electronic structure of surfaces on III–V semiconductor nanowires (NWs). NWs made of InAs, GaAs, and InP have been studied using scanning tunneling microscopy/spectroscopy (STM/S), low energy electron microscopy (LEEM), photoemission electron microscopy (PEEM), and x-ray photoelectron spectroscopy (XPS). All of the mentioned techniques have been developed to study 2-dimensional samples and issues related with the adaption to 3-dime...

  13. Transistors using crystalline silicon devices on glass

    Science.gov (United States)

    McCarthy, A.M.

    1995-05-09

    A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

  14. Fundamentals of nanoscaled field effect transistors

    CERN Document Server

    Chaudhry, Amit

    2013-01-01

    Fundamentals of Nanoscaled Field Effect Transistors gives comprehensive coverage of the fundamental physical principles and theory behind nanoscale transistors. The specific issues that arise for nanoscale MOSFETs, such as quantum mechanical tunneling and inversion layer quantization, are fully explored. The solutions to these issues, such as high-κ technology, strained-Si technology, alternate devices structures and graphene technology are also given. Some case studies regarding the above issues and solution are also given in the book. In summary, this book: Covers the fundamental principles behind nanoelectronics/microelectronics Includes chapters devoted to solutions tackling the quantum mechanical effects occurring at nanoscale Provides some case studies to understand the issue mathematically Fundamentals of Nanoscaled Field Effect Transistors is an ideal book for researchers and undergraduate and graduate students in the field of microelectronics, nanoelectronics, and electronics.

  15. TRANSISTOR IMPLEMENTATION OF REVERSIBLE PRT GATES

    Directory of Open Access Journals (Sweden)

    RASHMI S.B,

    2011-03-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for power optimization with its application in low power VLSI design. Reversible or information lossless circuits have applications in nanotechnology, digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computing. In this paper, two newoptimized universal gates are proposed. One of them has an ability to operate as a reversible half adder and half subtractor imultaneously. Another one acts only as half adder with minimum transistor count. The reversible gates are evaluated in terms of number of transistor count, critical path, garbage outputs and one to one mapping. Here transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on the results of the analysis, some of the trade-offs are made in the design to improve the efficiency.

  16. Angular Magnetoresistance of Nanowires with Alternating Cobalt and Nickel Segments

    KAUST Repository

    Mohammed, Hanan

    2017-06-22

    Magnetization reversal in segmented Co/Ni nanowires with varying number of segments was studied using angular Magnetoresistance (MR) measurements on isolated nanowires. The MR measurements offer an insight into the pinning of domain walls within the nanowires. Angular MR measurements were performed on nanowires with two and multiple segments by varying the angle between the applied magnetic field and nanowire (−90° ≤θ≤90°). The angular MR measurements reveal that at lower values of θ the switching fields are nearly identical for the multisegmented and two-segmented nanowires, whereas at higher values of θ, a decrease in the switching field is observed in the case of two segmented nanowires. The two segmented nanowires generally exhibit a single domain wall pinning event, whereas an increased number of pinning events are characteristic of the multisegmented nanowires at higher values of θ. In-situ magnetic force microscopy substantiates reversal by domain wall nucleation and propagation in multisegmented nanowires.

  17. Generation of reactive oxygen species from silicon nanowires.

    Science.gov (United States)

    Leonard, Stephen S; Cohen, Guy M; Kenyon, Allison J; Schwegler-Berry, Diane; Fix, Natalie R; Bangsaruntip, Sarunya; Roberts, Jenny R

    2014-01-01

    Processing and synthesis of purified nanomaterials of diverse composition, size, and properties is an evolving process. Studies have demonstrated that some nanomaterials have potential toxic effects and have led to toxicity research focusing on nanotoxicology. About two million workers will be employed in the field of nanotechnology over the next 10 years. The unknown effects of nanomaterials create a need for research and development of techniques to identify possible toxicity. Through a cooperative effort between National Institute for Occupational Safety and Health and IBM to address possible occupational exposures, silicon-based nanowires (SiNWs) were obtained for our study. These SiNWs are anisotropic filamentary crystals of silicon, synthesized by the vapor-liquid-solid method and used in bio-sensors, gas sensors, and field effect transistors. Reactive oxygen species (ROS) can be generated when organisms are exposed to a material causing cellular responses, such as lipid peroxidation, H2O2 production, and DNA damage. SiNWs were assessed using three different in vitro environments (H2O2, RAW 264.7 cells, and rat alveolar macrophages) for ROS generation and possible toxicity identification. We used electron spin resonance, analysis of lipid peroxidation, measurement of H2O2 production, and the comet assay to assess generation of ROS from SiNW and define possible mechanisms. Our results demonstrate that SiNWs do not appear to be significant generators of free radicals.

  18. DNA hybridization on silicon nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Singh, Shalini, E-mail: shalinsin@gmail.co [Electronic Materials Division, National Physical Laboratory (CSIR), Dr. K. S. Krishnan Marg, New Delhi-110012 (India); Faculty of Life Science, Aligarh Muslim University, Aligarh-202001 (India); Zack, Jyoti [Dr. B.R Ambedkar Center for Biomedical Research, University of Delhi, Delhi-110007 (India); Kumar, Dinesh; Srivastava, S.K.; Govind [Electronic Materials Division, National Physical Laboratory (CSIR), Dr. K. S. Krishnan Marg, New Delhi-110012 (India); Saluja, Daman [Dr. B.R Ambedkar Center for Biomedical Research, University of Delhi, Delhi-110007 (India); Khan, M.A. [Faculty of Life Science, Aligarh Muslim University, Aligarh-202001 (India); Singh, P.K. [Electronic Materials Division, National Physical Laboratory (CSIR), Dr. K. S. Krishnan Marg, New Delhi-110012 (India)

    2010-11-30

    Nanowire-based detection strategies provide promising new routes to bioanalysis and indeed are attractive to conventional systems because of their small size, high surface-to-volume ratios, electronic, and optical properties. A sequence-specific detection of single-stranded oligonucleotides using silicon nanowires (SiNWs) is demonstrated. The surface of the SiNWs is functionalized with densely packed organic monolayer via hydrosilylation for covalent attachment. Subsequently, deoxyribonucleic acid (DNA) is immobilized to recognize the complementary target DNA. The biomolecular recognition properties of the nanowires are tested via hybridization with {sup {gamma}P32} tagged complementary and non-complementary DNA oligonucleotides, showing good selectivity and reversibility. No significant non-specific binding to the incorrect sequences is observed. X-ray photoelectron spectroscopy, fluorescence imaging, and nanodrop techniques are used to characterize the modified SiNWs and covalent attachment with DNA. The results show that SiNWs are excellent substrates for the absorption, stabilization and detection of DNA sequences and could be used for DNA microarrays and micro fabricated SiNWs DNA sensors.

  19. Tunable nanowire nonlinear optical probe

    Energy Technology Data Exchange (ETDEWEB)

    Nakayama, Yuri; Pauzauskie, Peter J.; Radenovic, Aleksandra; Onorato, Robert M.; Saykally, Richard J.; Liphardt, Jan; Yang, Peidong

    2008-02-18

    One crucial challenge for subwavelength optics has been thedevelopment of a tunable source of coherent laser radiation for use inthe physical, information, and biological sciences that is stable at roomtemperature and physiological conditions. Current advanced near-fieldimaging techniques using fiber-optic scattering probes1,2 have alreadyachieved spatial resolution down to the 20-nm range. Recently reportedfar-field approaches for optical microscopy, including stimulatedemission depletion (STED)3, structured illumination4, and photoactivatedlocalization microscopy (PALM)5, have also enabled impressive,theoretically-unlimited spatial resolution of fluorescent biomolecularcomplexes. Previous work with laser tweezers6-8 has suggested the promiseof using optical traps to create novel spatial probes and sensors.Inorganic nanowires have diameters substantially below the wavelength ofvisible light and have unique electronic and optical properties9,10 thatmake them prime candidates for subwavelength laser and imagingtechnology. Here we report the development of an electrode-free,continuously-tunable coherent visible light source compatible withphysiological environments, from individual potassium niobate (KNbO3)nanowires. These wires exhibit efficient second harmonic generation(SHG), and act as frequency converters, allowing the local synthesis of awide range of colors via sum and difference frequency generation (SFG,DFG). We use this tunable nanometric light source to implement a novelform of subwavelength microscopy, in which an infrared (IR) laser is usedto optically trap and scan a nanowire over a sample, suggesting a widerange of potential applications in physics, chemistry, materials science,and biology.

  20. Transparent conducting silver nanowire networks

    CERN Document Server

    van de Groep, Jorik; Polman, Albert; 10.1021/nl301045a

    2013-01-01

    We present a transparent conducting electrode composed of a periodic two-dimensional network of silver nanowires. Networks of Ag nanowires are made with wire diameters of 45-110 nm and pitch of 500, 700 and 1000 nm. Anomalous optical transmission is observed, with an averaged transmission up to 91% for the best transmitting network and sheet resistances as low as 6.5 {\\Omega}/sq for the best conducting network. Our most dilute networks show lower sheet resistance and higher optical transmittance than an 80 nm thick layer of ITO sputtered on glass. By comparing measurements and simulations we identify four distinct physical phenomena that govern the transmission of light through the networks: all related to the excitation of localized surface plasmons and surface plasmon polaritons on the wires. The insights given in this paper provide the key guidelines for designing high-transmittance and low-resistance nanowire electrodes for optoelectronic devices, including thin-film solar cells. For these latter, we disc...

  1. Functionalization of magnetic nanowires by charged biopolymers

    DEFF Research Database (Denmark)

    Magnin, D.; Callegari, V.; Mátéfi-Tempfli, Stefan

    2008-01-01

    We report on a facile method for the preparation of biocompatible and bioactive magnetic nanowires. The method consists of the direct deposition of polysaccharides by layer-by-layer (LbL) assembly onto a brush of metallic nanowires; obtained by electrodeposition of the metal within the nanopores ...

  2. Quantum eigenstates of curved nanowire structures

    Energy Technology Data Exchange (ETDEWEB)

    Gravesen, J. [Department of Mathematics, Technical University of Denmark, Matematiktorvet building 303, DK-2800 Kgs. Lyngby (Denmark); Willatzen, M. [Mads Clausen Institute for Product Innovation, University of Southern Denmark, Grundtvigs Alle 150, DK-6400 Sonderborg (Denmark)]. E-mail: willatzen@mci.sdu.dk

    2006-01-15

    Eigenstates and associated eigenvalues of a quantum-mechanical particle confined to a three-dimensional arbitrarily curved nanowire structure are determined. Special emphasis is given to the influence of nanowire geometry and curvature effects which are expected to play important roles for the physical properties of several nanowire structures recently grown in laboratories. Use of differential-geometry arguments allows separation of the three-dimensional Schroedinger equation into either (i) two partial differential equations plus one ordinary differential equation in the general nanowire cross-section case or [for simple cross-sectional nanowire shapes] (ii) three ordinary differential equations (ODEs) in appropriate curved coordinates for the case where the cross-sectional area is constant along the nanowire axis. Problems corresponding to item, (ii) with three ODEs can be solved either completely analytically or by use of a simple one-dimensional finite-difference scheme. Three case studies are finally analyzed in details: the rectangular cross-sectional-shaped nanowire with a (a) straight-line axis, (b) a circular-shaped axis, and (c) the sinusoidal-shaped nanowire axis including discussion of symmetry properties.

  3. Facile synthesis of vanadium oxide nanowires

    Science.gov (United States)

    Kysar, Jesse; Sekhar, Praveen Kumar

    2016-10-01

    A simple growth process is reported for the synthesis of vanadium (II) oxide nanowires with an average width of 65 nm and up to 5 μm in length for growth at 1000 °C for 3 h. The vanadium (II) oxide nanowires were grown on a gold-coated silicon substrate at ambient pressure using a single heat zone furnace with Ar as the carrier gas. Gold was utilized as a catalyst for the growth of the nanowires. The growth temperature and heating time were varied to observe the nanowire morphology. An increase in nanowire width was observed with an increase in the heating temperature. A ninefold increase in the number density of the nanowires was observed when the heating time was changed from 30 min to 3 h. This is the first time a simple growth process for producing VO nanowires at ambient pressure has been demonstrated. Such a scheme enables wider use of VO nanowires in critical applications such as energy storage, gas sensors, and optical devices.

  4. High-Performance Single Nanowire Tunnel Diodes

    DEFF Research Database (Denmark)

    Wallentin, Jesper; Persson, Johan Mikael; Wagner, Jakob Birkedal

    2010-01-01

    We demonstrate single nanowire tunnel diodes with room temperature peak current densities of up to 329 A/cm(2). Despite the large surface to volume ratio of the type-II InP-GaAs axial heterostructure nanowires, we measure peak to valley current ratios (PVCR) of up to 8.2 at room temperature and 2...

  5. Lateral and Vertical Organic Transistors

    Science.gov (United States)

    Al-Shadeedi, Akram

    An extensive study has been performed to provide a better understanding of the operation principles of doped organic field-effect transistors (OFETs), organic p-i-n diodes, Schottky diodes, and organic permeable base transistors (OPBTs). This has been accomplished by a combination of electrical and structural characterization of these devices. The discussion of doped OFETs focuses on the shift of the threshold voltage due to increased doping concentrations and the generation and transport of minority charge carriers. Doping of pentacene OFETs is achieved by co-evaporation of pentacene with the n-dopant W2(hpp)4. It is found that pentacene thin film are efficiently doped and that a conductivity in the range of 2.6 x 10-6 S cm-1 for 1 wt% to 2.5 x 10-4 S cm-1 for 16 wt% is reached. It is shown that n-doped OFET consisting of an n-doped channel and n-doped contacts are ambipolar. This behavior is surprising, as n-doping the contacts should suppress direct injection of minority charge carriers (holes). It was proposed that minority charge carrier injection and hence the ambipolar characteristic of n-doped OFETs can be explained by Zener tunneling inside the intrinsic pentacene layer underneath the drain electrode. It is shown that the electric field in this layer is indeed in the range of the breakdown field of pentacene based p-i-n Zener homodiodes. Doping the channel has a profound influence on the onset voltage of minority (hole) conduction. The onset voltage can be shifted by lightly n-doping the channel. The shift of onset voltage can be explained by two mechanisms: first, due to a larger voltage that has to be applied to the gate in order to fully deplete the n-doped layer. Second, it can be attributed to an increase in hole trapping by inactive dopants. Moreover, it has been shown that the threshold voltage of majority (electron) conduction is shifted by an increase in the doping concentration, and that the ambipolar OFETs can be turned into unipolar OFETs at

  6. Switching Characteristics of Ferroelectric Transistor Inverters

    Science.gov (United States)

    Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

    2010-01-01

    This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

  7. Electrical Compact Modeling of Graphene Base Transistors

    Directory of Open Access Journals (Sweden)

    Sébastien Frégonèse

    2015-11-01

    Full Text Available Following the recent development of the Graphene Base Transistor (GBT, a new electrical compact model for GBT devices is proposed. The transistor model includes the quantum capacitance model to obtain a self-consistent base potential. It also uses a versatile transfer current equation to be compatible with the different possible GBT configurations and it account for high injection conditions thanks to a transit time based charge model. Finally, the developed large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using advanced numerical simulation.

  8. Fundamentals of RF and microwave transistor amplifiers

    CERN Document Server

    Bahl, Inder J

    2009-01-01

    A Comprehensive and Up-to-Date Treatment of RF and Microwave Transistor Amplifiers This book provides state-of-the-art coverage of RF and microwave transistor amplifiers, including low-noise, narrowband, broadband, linear, high-power, high-efficiency, and high-voltage. Topics covered include modeling, analysis, design, packaging, and thermal and fabrication considerations. Through a unique integration of theory and practice, readers will learn to solve amplifier-related design problems ranging from matching networks to biasing and stability. More than 240 problems are included to help read

  9. Going ballistic: Graphene hot electron transistors

    Science.gov (United States)

    Vaziri, S.; Smith, A. D.; Östling, M.; Lupina, G.; Dabrowski, J.; Lippert, G.; Mehr, W.; Driussi, F.; Venica, S.; Di Lecce, V.; Gnudi, A.; König, M.; Ruhl, G.; Belete, M.; Lemme, M. C.

    2015-12-01

    This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.

  10. VHDL simulation with access to transistor models

    Science.gov (United States)

    Gibson, J.

    1991-01-01

    Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.

  11. Static Characteristics of the Ferroelectric Transistor Inverter

    Science.gov (United States)

    Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

    2010-01-01

    The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

  12. Measurement of light diffusion in ZnO nanowire forests

    CERN Document Server

    Versteegh, Marijn A M; Dijkhuis, Jaap I

    2016-01-01

    Optimum design of efficient nanowire solar cells requires better understanding of light diffusion in a nanowire array. Here we demonstrate that our recently developed ultrafast all-optical shutter can be used to directly measure the dwell time of light in a nanowire array. Our measurements on disordered ZnO nanowire arrays, "nanowire forests," indicate that the photon mean free path and the dwell time of light can be well predicted from SEM images.

  13. Aerotaxy - A Gas-Phase Nanowire Growth Technique

    OpenAIRE

    Heurlin, Magnus

    2014-01-01

    In this thesis an efficient nanowire fabrication technique, called Aerotaxy, is investigated. Traditional nanowire fabrication techniques include the use of a substrate as a point of nanowire nucleation which limits the amount of nanowires that can be produced per unit time. In contrary, Aerotaxy offers a continuous growth process, in the gasphase, which could substantially increase the rate at which nanowires are fabricated and thus lower their fabrication cost. Investig...

  14. Deflections of Nanowires with Consideration of Surface Effects

    Institute of Scientific and Technical Information of China (English)

    LI He; YANG Zhou; ZHANG Yi-Min; WEN Bang-Chun

    2010-01-01

    @@ The elementary beam model is modified to include the surface effects and used to analyze the deflections of nanowires under different boundary conditions.The results show that compared to deflections of nanowires without consideration of surface effects,the surface effects can enlarge or reduce deflections of nanowires,and nanowire buckling occurs under certaJn conditions.This study might be helpful for design of nanowire-based nanoelectromechanical systems.

  15. Nanowire-based All Oxide Solar Cells

    Energy Technology Data Exchange (ETDEWEB)

    Yang*, Benjamin D. Yuhas and Peidong; Yang, Peidong

    2008-12-07

    We present an all-oxide solar cell fabricated from vertically oriented zinc oxide nanowires and cuprous oxide nanoparticles. Our solar cell consists of vertically oriented n-type zinc oxide nanowires, surrounded by a film constructed from p-type cuprous oxide nanoparticles. Our solution-based synthesis of inexpensive and environmentally benign oxide materials in a solar cell would allow for the facile production of large-scale photovoltaic devices. We found that the solar cell performance is enhanced with the addition of an intermediate oxide insulating layer between the nanowires and the nanoparticles. This observation of the important dependence of the shunt resistance on the photovoltaic performance is widely applicable to any nanowire solar cell constructed with the nanowire array in direct contact with one electrode.

  16. Bandgap engineering of GaN nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Ming, Bang-Ming; Yan, Hui [College of Materials Science and Engineering, Beijing University of Technology, Beijing 100124 (China); Wang, Ru-Zhi, E-mail: wrz@bjut.edu.cn, E-mail: yamcy@csrc.ac.cn [College of Materials Science and Engineering, Beijing University of Technology, Beijing 100124 (China); Beijing Computational Science Research Center, Beijing, 100094 (China); Yam, Chi-Yung, E-mail: wrz@bjut.edu.cn, E-mail: yamcy@csrc.ac.cn [Beijing Computational Science Research Center, Beijing, 100094 (China); Xu, Li-Chun [College of Physics and Optoelectronics, Taiyuan University of Technology, Taiyuan 030024 (China); Lau, Woon-Ming [Beijing Computational Science Research Center, Beijing, 100094 (China); Chengdu Green Energy and Green Manufacturing Technology R& D Center, Chengdu, Sichuan, 610207 (China)

    2016-05-15

    Bandgap engineering has been a powerful technique for manipulating the electronic and optical properties of semiconductors. In this work, a systematic investigation of the electronic properties of [0001] GaN nanowires was carried out using the density functional based tight-binding method (DFTB). We studied the effects of geometric structure and uniaxial strain on the electronic properties of GaN nanowires with diameters ranging from 0.8 to 10 nm. Our results show that the band gap of GaN nanowires depends linearly on both the surface to volume ratio (S/V) and tensile strain. The band gap of GaN nanowires increases linearly with S/V, while it decreases linearly with increasing tensile strain. These linear relationships provide an effect way in designing GaN nanowires for their applications in novel nano-devices.

  17. Probing Field Emission from Boron Carbide Nanowires

    Institute of Scientific and Technical Information of China (English)

    TIAN Ji-Fa; GAO Hong-Jun; BAO Li-Hong; WANG Xing-Jun; HUI Chao; LIU Fei; LI Chen; SHEN Cheng-Min; WANG Zong-Li; GU Chang-Zhi

    2008-01-01

    High density boron carbide nanowires are grown by an improved carbon thermal reduction technique. Transmission electron microscopy and electron energy lose spectroscopy of the sample show that the synthesized nanowires are B4 C with good crystallization. The field emission measurement for an individual boron nanowire is performed by using a Pt tip installed in the focused ion beam system. A field emission current with enhancement factor of 106 is observed and the evolution process during emission is also carefully studied. Furthermore, a two-step field emission with stable emission current density is found from the high-density nanowire film. Our results together suggest that boron carbide nanowires are promising candidates for electron emission nanodevices.

  18. Transformation of bulk alloys to oxide nanowires

    Science.gov (United States)

    Lei, Danni; Benson, Jim; Magasinski, Alexandre; Berdichevsky, Gene; Yushin, Gleb

    2017-01-01

    One dimensional (1D) nanostructures offer prospects for enhancing the electrical, thermal, and mechanical properties of a broad range of functional materials and composites, but their synthesis methods are typically elaborate and expensive. We demonstrate a direct transformation of bulk materials into nanowires under ambient conditions without the use of catalysts or any external stimuli. The nanowires form via minimization of strain energy at the boundary of a chemical reaction front. We show the transformation of multimicrometer-sized particles of aluminum or magnesium alloys into alkoxide nanowires of tunable dimensions, which are converted into oxide nanowires upon heating in air. Fabricated separators based on aluminum oxide nanowires enhanced the safety and rate capabilities of lithium-ion batteries. The reported approach allows ultralow-cost scalable synthesis of 1D materials and membranes.

  19. Random access actuation of nanowire grid metamaterial

    Science.gov (United States)

    Cencillo-Abad, Pablo; Ou, Jun-Yu; Plum, Eric; Valente, João; Zheludev, Nikolay I.

    2016-12-01

    While metamaterials offer engineered static optical properties, future artificial media with dynamic random-access control over shape and position of meta-molecules will provide arbitrary control of light propagation. The simplest example of such a reconfigurable metamaterial is a nanowire grid metasurface with subwavelength wire spacing. Recently we demonstrated computationally that such a metadevice with individually controlled wire positions could be used as dynamic diffraction grating, beam steering module and tunable focusing element. Here we report on the nanomembrane realization of such a nanowire grid metasurface constructed from individually addressable plasmonic chevron nanowires with a 230 nm × 100 nm cross-section, which consist of gold and silicon nitride. The active structure of the metadevice consists of 15 nanowires each 18 μm long and is fabricated by a combination of electron beam lithography and ion beam milling. It is packaged as a microchip device where the nanowires can be individually actuated by control currents via differential thermal expansion.

  20. Superconductive silicon nanowires using gallium beam lithography.

    Energy Technology Data Exchange (ETDEWEB)

    Henry, Michael David; Jarecki, Robert Leo,

    2014-01-01

    This work was an early career LDRD investigating the idea of using a focused ion beam (FIB) to implant Ga into silicon to create embedded nanowires and/or fully suspended nanowires. The embedded Ga nanowires demonstrated electrical resistivity of 5 m-cm, conductivity down to 4 K, and acts as an Ohmic silicon contact. The suspended nanowires achieved dimensions down to 20 nm x 30 nm x 10 m with large sensitivity to pressure. These structures then performed well as Pirani gauges. Sputtered niobium was also developed in this research for use as a superconductive coating on the nanowire. Oxidation characteristics of Nb were detailed and a technique to place the Nb under tensile stress resulted in the Nb resisting bulk atmospheric oxidation for up to years.