WorldWideScience

Sample records for intelligent gateway processor

  1. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  2. An Intelligent Cloud Storage Gateway for Medical Imaging.

    Science.gov (United States)

    Viana-Ferreira, Carlos; Guerra, António; Silva, João F; Matos, Sérgio; Costa, Carlos

    2017-09-01

    Historically, medical imaging repositories have been supported by indoor infrastructures. However, the amount of diagnostic imaging procedures has continuously increased over the last decades, imposing several challenges associated with the storage volume, data redundancy and availability. Cloud platforms are focused on delivering hardware and software services over the Internet, becoming an appealing solution for repository outsourcing. Although this option may bring financial and technological benefits, it also presents new challenges. In medical imaging scenarios, communication latency is a critical issue that still hinders the adoption of this paradigm. This paper proposes an intelligent Cloud storage gateway that optimizes data access times. This is achieved through a new cache architecture that combines static rules and pattern recognition for eviction and prefetching. The evaluation results, obtained from experiments over a real-world dataset, show that cache hit ratios can reach around 80%, leading to reductions of image retrieval times by over 60%. The combined use of eviction and prefetching policies proposed can significantly reduce communication latency, even when using a small cache in comparison to the total size of the repository. Apart from the performance gains, the proposed system is capable of adjusting to specific workflows of different institutions.

  3. Intelligent trigger processor for the crystal box

    International Nuclear Information System (INIS)

    Sanders, G.H.; Butler, H.S.; Cooper, M.D.

    1981-01-01

    A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering

  4. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization......In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  5. Enabling South-Africa: development of an intelligent gateway

    CSIR Research Space (South Africa)

    Evans, ED

    1993-08-01

    Full Text Available are catered for on all host protocols. The resulting gateway is operated on a sound business footing for the benefit of end-users and expert searchers in Southern Africa. The development of the system and the business are described in the paper....

  6. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

    2010-01-01

    As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

  7. Optical gateway for intelligent buildings: a new open-up window to the optical fibre sensors market?

    Science.gov (United States)

    Fernandez-Valdivielso, Carlos; Matias, Ignacio R.; Arregui, Francisco J.; Bariain, Candido; Lopez-Amo, Manuel

    2004-06-01

    This paper presents the first optical fiber sensor gateway for integrating these special measurement devices in Home Automation Systems, concretely in those buildings that use the KNX European Intelligent Buildings Standard.

  8. Design on intelligent gateway technique in home network

    Science.gov (United States)

    Hu, Zhonggong; Feng, Xiancheng

    2008-12-01

    Based on digitization, multimedia, mobility, wide band, real-time interaction and so on,family networks, because can provide diverse and personalized synthesis service in information, correspondence work, entertainment, education and health care and so on, are more and more paid attention by the market. The family network product development has become the focus of the related industry. In this paper,the concept of the family network and the overall reference model of the family network are introduced firstly.Then the core techniques and the correspondence standard related with the family network are proposed.The key analysis is made for the function of family gateway, the function module of the software,the key technologies to client side software architecture and the trend of development of the family network entertainment seeing and hearing service and so on. Product present situation of the family gateway and the future trend of development, application solution of the digital family service are introduced. The development of the family network product bringing about the digital family network industry is introduced finally.It causes the development of software industries,such as communication industry,electrical appliances industry, computer and game and so on.It also causes the development of estate industry.

  9. Research and implementation of intelligent gateway driver layer based on Linux bus

    Directory of Open Access Journals (Sweden)

    ZHANG Jian

    2016-10-01

    Full Text Available Currently,in the field of smart home,there is no relevant organization that yet has proposed an unified protocol standard.It increases the complexity and limitations of heterogeneous gateway software framework design that different vendor′s devices have different communication mode and protocol standards.In this paper,a serial of interfaces are provided by Linux kernel,and a virtual bus is registered under Linux.The physical device drivers are able to connect to the virtual bus.The detailed designs of the communication protocol are placed in the underlying adapters,making the integration of heterogeneous networks more natural.At the same time,designing the intelligent gateway system driver layer based on Linux bus can let the application layer be more unified and clear logical.And it also let the hardware access network become more convenient and distinct.

  10. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2010-12-01

    Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

  11. Healthcare Data Gateways: Found Healthcare Intelligence on Blockchain with Novel Privacy Risk Control.

    Science.gov (United States)

    Yue, Xiao; Wang, Huiju; Jin, Dawei; Li, Mingqiang; Jiang, Wei

    2016-10-01

    Healthcare data are a valuable source of healthcare intelligence. Sharing of healthcare data is one essential step to make healthcare system smarter and improve the quality of healthcare service. Healthcare data, one personal asset of patient, should be owned and controlled by patient, instead of being scattered in different healthcare systems, which prevents data sharing and puts patient privacy at risks. Blockchain is demonstrated in the financial field that trusted, auditable computing is possible using a decentralized network of peers accompanied by a public ledger. In this paper, we proposed an App (called Healthcare Data Gateway (HGD)) architecture based on blockchain to enable patient to own, control and share their own data easily and securely without violating privacy, which provides a new potential way to improve the intelligence of healthcare systems while keeping patient data private. Our proposed purpose-centric access model ensures patient own and control their healthcare data; simple unified Indicator-Centric Schema (ICS) makes it possible to organize all kinds of personal healthcare data practically and easily. We also point out that MPC (Secure Multi-Party Computing) is one promising solution to enable untrusted third-party to conduct computation over patient data without violating privacy.

  12. Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications

    Science.gov (United States)

    Xu, Huaiyu; Mita, Yoshio; Shibata, Tadashi

    2002-04-01

    The architecture of a very large scale integration (VLSI) vector-quantization processor (VQP) has been optimized to develop a general-purpose intelligent query-search agent. The agent performs a similarity-based search in a large-volume database. Although similarity-based search processing is computationally very expensive, latency-free searches have become possible due to the highly parallel maximum-likelihood search architecture of the VQP chip. Three architectures of the VQP chip have been studied and their performances are compared. In order to give reasonable searching results according to the different policies, the concept of penalty function has been introduced into the VQP. An E-commerce real-estate agency system has been developed using the VQP chip implemented in a field-programmable gate array (FPGA) and the effectiveness of such an agency system has been demonstrated.

  13. Analysis of image factors of x-ray films : study for the intelligent replenishment system of automatic film processor

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sung Tae; Yoon, Chong Hyun; Park, Kwang BO; Auh, Yong Ho; Lee, Hyoung Jin; In, Kyung Hwan; Kim, Keon Chung [Asan Medical Center, Ulsan Univ. College of Medicine, Ulsan (Korea, Republic of)

    1998-06-01

    We analyzed image factors to determine the characteristic factors that need for intelligent replenishment system of the auto film processor. We processed the serial 300 sheets of radiographic films of chest phantom without replenishment of developing and fixation replenisher. We took the digital data by using film digitizer which scanned the films and automatically summed up the pixel values of the films. We analyzed characteristic curves, average gradients and relative speeds of individual film using densitometer and step densitometry. We also evaluated the pH of developer, fixer, and washer fluid with digital pH meter. Fixer residual rate and washing effect were measured by densitometer using the reagent methods. There was no significant reduction of the digital density numbers of the serial films without replenishment of developer and fixer. The average gradients were gradually decreased by 0.02 and relative speeds were also gradually decreased by 6.96% relative to initial standard step-densitometric measurement. The pHs of developer and fixer were reflected the inactivation of each fluid. The fixer residual rates and washing effects after processing each 25 sheets of films were in the normal range. We suggest that the digital data are not reliable due to limitation of the hardware and software of the film digitizer. We conclude that average gradient and relative speed which mean the film's contrast and sensitivity respectively are reliable factors for determining the need for the replenishment of the auto film processor. We need more study of simpler equations and programming for more intelligent replenishment system of the auto film processor.

  14. 移动支付的智能网关备份策略研究%Research on Intelligent Gateway Backup Strategy for Mobile Payment

    Institute of Scientific and Technical Information of China (English)

    王春

    2016-01-01

    The spread of 4G provided the basis for the development of mobile electronic commerce, and the mobile payment in mobile terminals was with the tide of development and spread. By analyzing mobile payment, this paper found the major risk for disruption in operation to be technical risks, and then proposed the use of technology and business strategy to construct the intelligent gateway backup, to make sure the continued stability of business operation.%4G的普及给移动电子商务的发展提供了基础,移动支付环节也随之在移动终端中进一步发展和普及。主要通过对移动支付的分析,发现移动支付开展中面临的中断风险主要为技术风险,随后通过运用技术和商业策略建设智能网关备份,保障业务的持续稳定开展。

  15. ECH system developments including the design of an intelligent fault processor on the DIII-D tokamak

    International Nuclear Information System (INIS)

    Ponce, D.; Lohr, J.; Tooker, J.F.; O'Neill, R.C.; Moeller, C.P.; Doane, J.L.; Noraky, S.; Dubovenko, K.; Gorelov, Y.A.; Cengher, M.; Penaflor, B.G.; Ellis, R.A.

    2011-01-01

    A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a field programmable gate array device, will analyze signals for aberrant operation and ramp down high voltage to try to avoid hard faults. The processor will then attempt to ramp back up to an attainable operating point. The new generation fault processor will be developed during an expansion of the electron cyclotron heating (ECH) areas that will include the installation of a depressed collector gyrotron and associated equipment. Existing systems will also be upgraded. Testing of real-time control of the ECH launcher poloidal drives by the DIII-D plasma control system will be completed. The ECH control system software will be upgraded for increased scalability and to increase operator productivity. Resources permitting, all systems will receive an extra layer of interlocks for the filament and magnet power supplies, added shielding for the tank electronics, programmable filament boost shape for long pulses, and electronics upgrades for the installation of the advanced fault processor.

  16. Commercial Drivers License Information System - Gateway: (CDLIS - Gateway) -

    Data.gov (United States)

    Department of Transportation — CDLIS - Gateway is the clearinghouse for CDL information collected by all states, and provides a gateway for enforcement users to access CDL data. CDLIS Gateway was...

  17. Pool gateway seal

    International Nuclear Information System (INIS)

    Starr, J.A.; Steinert, L.A.

    1983-01-01

    A device for sealing a gateway between interconnectable pools in a nuclear facility comprising a frame supporting a liquid impermeable sheet positioned in a u-shaped gateway between the pools. An inflatable tube carried in a channel in the periphery of the frame and adjoining the gateway provides a seal therebetween when inflated. A restraining arrangement on the bottom edge of the frame is releasably engagable with an adjacent portion of the gateway to restrict the movement of the frame in the u-shaped gateway upon inflation of the tube, thereby enhancing the seal. The impermeable sheet is formed of an elastomer and thus is conformable to a liquid permeable supportive wall upon application of liquid pressure to the side of the sheet opposite the wall

  18. A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

    Science.gov (United States)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2016-04-01

    A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

  19. Remote Sensing Information Gateway

    Science.gov (United States)

    Remote Sensing Information Gateway, a tool that allows scientists, researchers and decision makers to access a variety of multi-terabyte, environmental datasets and to subset the data and obtain only needed variables, greatly improving the download time.

  20. The BUG BITBUS Universal Gateway

    International Nuclear Information System (INIS)

    Nawrocki, G.

    1996-01-01

    The BITBUS Universal Gateway (BUG) provides a unique, cost effective solution to many different computer interface problems. Each BUG node, utilizing ''on board'' intelligence, has the ability to provide a communication link between BITBUS protocol and other computer-signal interfaces. Among them, IEEE-488, RS232, and raw analog and binary signal 1/0. BITBUS is a multidrop, multinode link with the ability to communicate over great distances. By using this method of signal transfer, along with the communication conversion ability of the BUG, one could accomplish such things as the ability to run IEEE-488 instruments over great distances, extend a multidrop links to RS232 instruments, and provide a convenient interface point for remote analog and binary 1/0 signals, all on one homogeneous network. The BUG not only provides this through the wired ''twisted pair'' standard of BITBUS, but extends the ability to fiber optic communications for signal transfer over extreme distances and through electrically ''noisy'' environments

  1. Expert System Constant False Alarm Rate (CFAR) Processor

    National Research Council Canada - National Science Library

    Wicks, Michael C

    2006-01-01

    An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...

  2. Inferential Processor.

    Science.gov (United States)

    1982-01-01

    dlutilization,o Groupe d’Intelligence Artificielle , Universite d’Aix- Marseille, Luminy, France, September 1975. 4. Clocksint W.F. and C.S. Mellish...for reasoning in higher-order logics such as the first-order predicate calculus; the latter is required for applications in artificial intelligence ...analysis and evaluation of intelligence reports, the preparation and analysis of tactical I methods and principles, the formulation and interpretation of

  3. Design and implementation of scalable IPv4-IPv6 internetworking gateway

    Science.gov (United States)

    Zhu, Guo-sheng; Yu, Shao-hua; Dai, Jin-you

    2008-11-01

    This paper proposed a scalable architecture of IPv4-IPv6 internetworking gateway based on EZchip 10Gbps network processor NP-1c. The Application Layer Gateway(ALG) of control plane can be upgraded without needing to modify the data forwarding plane.A SIP ALG of 3GPP IMS(IP Multimedia Subsystem)was implemented and tested under real China Next Generation Internet(CNGI) network environment.IPv4 SIP UEs can communicate with IPv6 SIP UEs through the gateway.

  4. Intelligence

    Science.gov (United States)

    Sternberg, Robert J.

    2012-01-01

    Intelligence is the ability to learn from experience and to adapt to, shape, and select environments. Intelligence as measured by (raw scores on) conventional standardized tests varies across the lifespan, and also across generations. Intelligence can be understood in part in terms of the biology of the brain—especially with regard to the functioning in the prefrontal cortex—and also correlates with brain size, at least within humans. Studies of the effects of genes and environment suggest that the heritability coefficient (ratio of genetic to phenotypic variation) is between .4 and .8, although heritability varies as a function of socioeconomic status and other factors. Racial differences in measured intelligence have been observed, but race is a socially constructed rather than biological variable, so such differences are difficult to interpret. PMID:22577301

  5. Intelligence.

    Science.gov (United States)

    Sternberg, Robert J

    2012-03-01

    Intelligence is the ability to learn from experience and to adapt to, shape, and select environments. Intelligence as measured by (raw scores on) conventional standardized tests varies across the lifespan, and also across generations. Intelligence can be understood in part in terms of the biology of the brain-especially with regard to the functioning in the prefrontal cortex-and also correlates with brain size, at least within humans. Studies of the effects of genes and environment suggest that the heritability coefficient (ratio of genetic to phenotypic variation) is between .4 and .8, although heritability varies as a function of socioeconomic status and other factors. Racial differences in measured intelligence have been observed, but race is a socially constructed rather than biological variable, so such differences are difficult to interpret.

  6. Region & Gateway Mapping

    OpenAIRE

    Schröter, Derik

    2007-01-01

    State-of-the-art robot mapping approaches are capable of acquiring impressively accurate 2D and 3D models of their environments. To the best of our knowledge, few of them represent structure or acquire models of task-relevant objects. In this work, a new approach to mapping of indoor environments is presented, in which the environment structure in terms of regions and gateways is automatically extracted, while the robot explores. Objects, both in 2D and 3D, are modeled explicitly in those map...

  7. Convergence of Residential Gateway Technology

    NARCIS (Netherlands)

    Hartog, F.T.H. den; Balm, M.; Jong, C.M. de; Kwaaitaal, J.J.B.

    2004-01-01

    A new OSI-based model is described that can be used for the classification of residential gateways. It is applied to analyze current gateway solutions and draw evolutionary paths for the medium to long term. From this it is concluded that particularly set-top boxes and broadband modems, as opposed

  8. Convergence of residential gateway technology

    NARCIS (Netherlands)

    Hartog, den F.T.H.; Balm, M.; Jong, de C.M.; Kwaaitaal, J.J.B.

    2004-01-01

    A new OSI-based model is described that can be used for the classification of residential gateways. It is applied to analyze current gateway solutions and draw evolutionary paths for the medium to long term. From this it is concluded that particularly set-top boxes and broadband modems, as opposed

  9. Volunteer Computing for Science Gateways

    OpenAIRE

    Anderson, David

    2017-01-01

    This poster offers information about volunteer computing for science gateways that offer high-throughput computing services. Volunteer computing can be used to get computing power. This increases the visibility of the gateway to the general public as well as increasing computing capacity at little cost.

  10. VIRTUS: a multi-processor system in FASTBUS

    International Nuclear Information System (INIS)

    Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

    1986-01-01

    VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

  11. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  12. Gateways to clinical trials.

    Science.gov (United States)

    Bayés, M; Rabasseda, X; Prous, J R

    2007-12-01

    Gateways to Clinical Trials are a guide to the most recent clinical trials in current literature and congresses. The data in the following tables has been retrieved from the Clinical Trials Knowledge Area of Prous Science Intergrity, the drug discovery and development portal, http://integrity.prous.com. This issue focuses on the following selection of drugs: 249553, 2-Methoxyestradiol; Abatacept, Adalimumab, Adefovir dipivoxil, Agalsidase beta, Albinterferon alfa-2b, Aliskiren fumarate, Alovudine, Amdoxovir, Amlodipine besylate/atorvastatin calcium, Amrubicin hydrochloride, Anakinra, AQ-13, Aripiprazole, AS-1404, Asoprisnil, Atacicept, Atrasentan; Belimumab, Bevacizumab, Bortezomib, Bosentan, Botulinum toxin type B, Brivaracetam; Catumaxomab, Cediranib, Cetuximab, cG250, Ciclesonide, Cinacalcet hydrochloride, Curcumin, Cypher; Darbepoetin alfa, Denosumab, Dihydrexidine; Eicosapentaenoic acid/docosahexaenoic acid, Entecavir, Erlotinib hydrochloride, Escitalopram oxalate, Etoricoxib, Everolimus, Ezetimibe; Febuxostat, Fenspiride hydrochloride, Fondaparinux sodium; Gefitinib, Ghrelin (human), GSK-1562902A; HSV-tk/GCV; Iclaprim, Imatinib mesylate, Imexon, Indacaterol, Insulinotropin, ISIS-112989; L-Alanosine, Lapatinib ditosylate, Laropiprant; Methoxy polyethylene glycol-epoetin-beta, Mipomersen sodium, Motexafin gadolinium; Natalizumab, Nimotuzumab; OSC, Ozarelix; PACAP-38, Paclitaxel nanoparticles, Parathyroid Hormone-Related Protein-(1-36), Pasireotide, Pegfilgrastim, Peginterferon alfa-2a, Peginterferon alfa-2b, Pemetrexed disodium, Pertuzumab, Picoplatin, Pimecrolimus, Pitavastatin calcium, Plitidepsin; Ranelic acid distrontium salt, Ranolazine, Recombinant human relaxin H2, Regadenoson, RFB4(dsFv)-PE38, RO-3300074, Rosuvastatin calcium; SIR-Spheres, Solifenacin succinate, Sorafenib, Sunitinib malate; Tadalafil, Talabostat, Taribavirin hydrochloride, Taxus, Temsirolimus, Teriparatide, Tiotropium bromide, Tipifarnib, Tirapazamine, Tocilizumab; UCN-01, Ularitide

  13. Gateways to clinical trials.

    Science.gov (United States)

    Bayés, M; Rabasseda, X; Prous, J R

    2005-04-01

    Gateways to Clinical Trials is a guide to the most recent clinical trials in current literature and congresses. The data in the following tables has been retrieved from the Clinical Trials Knowledge Area of Prous Science Integrity, the drug discovery and development portal, http://integrity. prous.com. This issue focuses on the following selection of drugs: ABX-IL-8, Acclaim, adalimumab, AGI-1067, alagebrium chloride, alemtuzumab, Alequel, Androgel, anti-IL-12 MAb, AOD-9604, aripiprazole, atomoxetine hydrochloride; Biphasic insulin aspart, bosentan, botulinum toxin type B, bovine lactoferrin, brivudine; Cantuzumab mertansine, CB-1954, CDB-4124, CEA-TRICOM, choriogonadotropin alfa, cilansetron, CpG-10101, CpG-7909, CTL-102, CTL-102/CB-1954; DAC:GRF, darbepoetin alfa, davanat-1, decitabine, del-1 Genemedicine, dexanabinol, dextofisopam, dnaJP1, dronedarone hydrochloride, dutasteride; Ecogramostim, eletriptan, emtricitabine, EPI-hNE-4, eplerenone, eplivanserin fumarate, erlotinib hydrochloride, ertapenem sodium, escitalopram oxalate, esomeprazole magnesium, etoricoxib, ezetimibe; Falecalcitriol, fingolimod hydrochloride; Gepirone hydrochloride; HBV-ISS, HSV-2 theracine, human insulin; Imatinib mesylate, Indiplon, insulin glargine, ISAtx-247; L612 HuMAb, levodopa/carbidopa/entacapone, lidocaine/prilocaine, LL-2113AD, lucinactant, LY-156735; Meclinertant, metelimumab, morphine hydrochloride, morphine-6-glucuronide; Natalizumab, nimotuzumab, NX-1207, NYVAC-HIV C; Omalizumab, onercept, osanetant; PABA, palosuran sulfate, parathyroid hormone (human recombinant), parecoxib sodium, PBI-1402, PCK-3145, peginterferon alfa-2a, peginterferon alfa-2b, peginterferon alfa-2b/ribavirin, pemetrexed disodium, pimecrolimus, PINC, pregabalin; Ramelteon, rasagiline mesilate, rasburicase, rimonabant hydrochloride, RO-0098557, rofecoxib, rosiglitazone maleate/metformin hydrochloride; Safinamide mesilate, SHL-749, sitaxsentan sodium, sparfosic acid, SprayGel, squalamine, St. John's Wort

  14. Plant simulators using gateway devices

    International Nuclear Information System (INIS)

    Forbes, H.W.

    1988-01-01

    One of the most difficult tasks in building a full-scope power plant simulator is modelling the plant process computer. For reasons of cost, it is usually not feasible to include a duplicate process computer within the simulator, although this would provide the highest degree of realism. The recent introduction of gateway devices by several process control manufacturers changes the cost picture considerably. These gateways are capable of emulating Input/Output multiplexers and controllers at significantly less cost. Simulators which use these devices can provide the absolute realism of a duplicate process computer without the associated cost burden. This paper discusses the use of gateways in simulators, and examines the case of a simulator now being built which uses this design technique

  15. IoT gateway architecture

    OpenAIRE

    Leleika, Paulius

    2017-01-01

    This paper provides an overview of HTTP, CoAP, AMQP, DDS, MQTT, XMPP communication protocols. The main IoT problem is that IoT devices uses many different communication protocols and devices cannot communicate with each other directly. IoT gateway helps to solve that problem. This paper also identifies requirements for IoT gateway software. Provides solution for communication between devices which are using different messaging architectures. Presents security aspects and ways to secure IoT ga...

  16. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  17. Gateways to clinical trials.

    Science.gov (United States)

    Bayés, M; Rabasseda, X; Prous, J R

    2006-10-01

    Gateways to Clinical Trials are a guide to the most recent clinical trials in current literature and congresses. The data the following tables have been retrieved from the Clinical Trials Knowledge Area of Prous Science Integrity, the drug discovery and development portal, http://integrity.prous.com. This issues focuses on the following selection of drugs: (-)-Epigallocatechin gallate, (-)-gossypol, 2-deoxyglucose, 3,4-DAP, 7-monohydroxyethylrutoside; Ad5CMV-p53, adalimumab, adefovir dipivoxil, ADH-1, alemtuzumab, aliskiren fumarate, alvocidib hydrochloride, aminolevulinic acid hydrochloride, aminolevulinic acid methyl ester, amrubicin hydrochloride, AN-152, anakinra, anecortave acetate, antiasthma herbal medicine intervention, AP-12009, AP-23573, apaziquone, aprinocarsen sodium, AR-C126532, AR-H065522, aripiprazole, armodafinil, arzoxifene hydrochloride, atazanavir sulfate, atilmotin, atomoxetine hydrochloride, atorvastatin, avanafil, azimilide hydrochloride; Bevacizumab, biphasic insulin aspart, BMS-214662, BN-83495, bortezomib, bosentan, botulinum toxin type B; Caspofungin acetate, cetuximab, chrysin, ciclesonide, clevudine, clofarabine, clopidogrel, CNF-1010, CNTO-328, CP-751871, CX-717, Cypher; Dapoxetine hydrochloride, darifenacin hydrobromide, dasatinib, deferasirox, dextofisopam, dextromethorphan/quinidine sulfate, diclofenac, dronedarone hydrochloride, drotrecogin alfa (activated), duloxetine hydrochloride, dutasteride; Edaravone, efaproxiral sodium, emtricitabine, entecavir, eplerenone, epratuzumab, erlotinib hydrochloride, escitalopram oxalate, etoricoxib, ezetimibe, ezetimibe/simvastatin; Finrozole, fipamezole hydrochloride, fondaparinux sodium, fulvestrant; Gabapentin enacarbil, gaboxadol, gefitinib, gestodene, ghrelin (human); Human insulin, human papillomavirus vaccine; Imatinib mesylate, immunoglobulin intravenous (human), indiplon, insulin detemir, insulin glargine, insulin glulisine, intranasal insulin, istradefylline, i.v. gamma

  18. Deep Space Gateway "Recycler" Mission

    Science.gov (United States)

    Graham, L.; Fries, M.; Hamilton, J.; Landis, R.; John, K.; O'Hara, W.

    2018-02-01

    Use of the Deep Space Gateway provides a hub for a reusable planetary sample return vehicle for missions to gather star dust as well as samples from various parts of the solar system including main belt asteroids, near-Earth asteroids, and Mars moon.

  19. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  20. Multithreading in vector processors

    Science.gov (United States)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  1. A gateway to the Gulf

    International Nuclear Information System (INIS)

    Crawford, A.P.

    1992-01-01

    One day in February 1991, a man strolling along a bucolic stretch of rural real estate in Alabama heard the call of what he later discovered to be a red-cockaded woodpecker. A rare event, this would ordinarily have been a pleasant surprise. When officials at the Federal Energy Regulatory Commission (FERC) in Washington, D.C., got word of the red's siting, they took notice. And when Dan Mitchell and Jamie Craddock at United Gas Pipe Line Co. in Houston found out, they just shook their heads --- again. The red-cockaded woodpecker is but one of the uniquely named, federally protected species native to South Alabama that Mitchell and Craddock had to constantly concern themselves with as they attempted to ensure the environmental and regulatory compliance of United's recently completed 28-mile Gateway gas pipeline near gas-rich Mobile Bay. Until May 1, when United put Gateway into service, it had taken more than six years to plan and construct the most environmentally correct route for the pipeline. This paper discusses the largest portion of Gateway's route which is piney forest or agricultural land with the wetlands area prevalent in the southern end of the route

  2. Deep Space Gateway Science Opportunities

    Science.gov (United States)

    Quincy, C. D.; Charles, J. B.; Hamill, Doris; Sidney, S. C.

    2018-01-01

    The NASA Life Sciences Research Capabilities Team (LSRCT) has been discussing deep space research needs for the last two years. NASA's programs conducting life sciences studies - the Human Research Program, Space Biology, Astrobiology, and Planetary Protection - see the Deep Space Gateway (DSG) as affording enormous opportunities to investigate biological organisms in a unique environment that cannot be replicated in Earth-based laboratories or on Low Earth Orbit science platforms. These investigations may provide in many cases the definitive answers to risks associated with exploration and living outside Earth's protective magnetic field. Unlike Low Earth Orbit or terrestrial locations, the Gateway location will be subjected to the true deep space spectrum and influence of both galactic cosmic and solar particle radiation and thus presents an opportunity to investigate their long-term exposure effects. The question of how a community of biological organisms change over time within the harsh environment of space flight outside of the magnetic field protection can be investigated. The biological response to the absence of Earth's geomagnetic field can be studied for the first time. Will organisms change in new and unique ways under these new conditions? This may be specifically true on investigations of microbial communities. The Gateway provides a platform for microbiology experiments both inside, to improve understanding of interactions between microbes and human habitats, and outside, to improve understanding of microbe-hardware interactions exposed to the space environment.

  3. Ad Hoc Access Gateway Selection Algorithm

    Science.gov (United States)

    Jie, Liu

    With the continuous development of mobile communication technology, Ad Hoc access network has become a hot research, Ad Hoc access network nodes can be used to expand capacity of multi-hop communication range of mobile communication system, even business adjacent to the community, improve edge data rates. For mobile nodes in Ad Hoc network to internet, internet communications in the peer nodes must be achieved through the gateway. Therefore, the key Ad Hoc Access Networks will focus on the discovery gateway, as well as gateway selection in the case of multi-gateway and handover problems between different gateways. This paper considers the mobile node and the gateway, based on the average number of hops from an average access time and the stability of routes, improved gateway selection algorithm were proposed. An improved gateway selection algorithm, which mainly considers the algorithm can improve the access time of Ad Hoc nodes and the continuity of communication between the gateways, were proposed. This can improve the quality of communication across the network.

  4. Intelligent spatial ecosystem modeling using parallel processors

    International Nuclear Information System (INIS)

    Maxwell, T.; Costanza, R.

    1993-01-01

    Spatial modeling of ecosystems is essential if one's modeling goals include developing a relatively realistic description of past behavior and predictions of the impacts of alternative management policies on future ecosystem behavior. Development of these models has been limited in the past by the large amount of input data required and the difficulty of even large mainframe serial computers in dealing with large spatial arrays. These two limitations have begun to erode with the increasing availability of remote sensing data and GIS systems to manipulate it, and the development of parallel computer systems which allow computation of large, complex, spatial arrays. Although many forms of dynamic spatial modeling are highly amenable to parallel processing, the primary focus in this project is on process-based landscape models. These models simulate spatial structure by first compartmentalizing the landscape into some geometric design and then describing flows within compartments and spatial processes between compartments according to location-specific algorithms. The authors are currently building and running parallel spatial models at the regional scale for the Patuxent River region in Maryland, the Everglades in Florida, and Barataria Basin in Louisiana. The authors are also planning a project to construct a series of spatially explicit linked ecological and economic simulation models aimed at assessing the long-term potential impacts of global climate change

  5. Integrated fuel processor development

    International Nuclear Information System (INIS)

    Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

    2001-01-01

    The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

  6. System Design for Telecommunication Gateways

    CERN Document Server

    Bachmutsky, Alexander

    2010-01-01

    System Design for Telecommunication Gateways provides a thorough review of designing telecommunication network equipment based on the latest hardware designs and software methods available on the market. Focusing on high-end efficient designs that challenge all aspects of the system architecture, this book helps readers to understand a broader view of the system design, analyze all its most critical components, and select the parts that best fit a particular application. In many cases new technology trends, potential future developments, system flexibility and capability extensions are outline

  7. Subject Gateway Sites and Search Engine Ranking.

    Science.gov (United States)

    Thelwall, Mike

    2002-01-01

    Discusses subject gateway sites and commercial search engines for the Web and presents an explanation of Google's PageRank algorithm. The principle question addressed is the conditions under which a gateway site will increase the likelihood that a target page is found in search engines. (LRW)

  8. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  9. 3081/E processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.

    1984-04-01

    The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

  10. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  11. Adaptive signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

  12. Adaptive signal processor

    International Nuclear Information System (INIS)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  13. Automatic Generation of Network Protocol Gateways

    DEFF Research Database (Denmark)

    Bromberg, Yérom-David; Réveillère, Laurent; Lawall, Julia

    2009-01-01

    for describing protocol behaviors, message structures, and the gateway logic.  Z2z includes a compiler that checks essential correctness properties and produces efficient code. We have used z2z to develop a number of gateways, including SIP to RTSP, SLP to UPnP, and SMTP to SMTP via HTTP, involving a range......The emergence of networked devices in the home has made it possible to develop applications that control a variety of household functions. However, current devices communicate via a multitude of incompatible protocols, and thus gateways are needed to translate between them.  Gateway construction......, however, requires an intimate knowledge of the relevant protocols and a substantial understanding of low-level network programming, which can be a challenge for many application programmers. This paper presents a generative approach to gateway construction, z2z, based on a domain-specific language...

  14. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  15. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  16. PreciseMail anti-spam gateway allows users more control over spam definitions; unwanted email is eliminated with no false positives

    CERN Multimedia

    ten Bruggencate, J

    2003-01-01

    "PreciseMail Anti-Spam Gateway uses a combination of proven heuristic (rules-based) and artificial intelligence technologies that eliminates unwanted spam e-mail at an Internet gateway without filtering critical e-mail messages. Its highly effective filtering engine identifies spam and allows multiple levels of tuning and customization to meet each user's personal e-mail spam filtering requirements" (1 page).

  17. GATEWAY - COMMUNICATIONS GATEWAY SOFTWARE FOR NETEX, DECNET, AND TCP/IP

    Science.gov (United States)

    Keith, B.

    1994-01-01

    The Communications Gateway Software, GATEWAY, provides process-to-process communication between remote applications programs in different protocol domains. Communicating peer processes may be resident on any paired combination of NETEX, DECnet, or TCP/IP hosts. The gateway provides the necessary mapping from one protocol to another and will facilitate practical intermachine communications in a cost effective manner by eliminating the need to standardize on a single protocol or the need to implement multiple protocols in the host computers. The purpose of the gateway is to support data transfers between application programs on different host computers using different protocols. The gateway computer must be physically connected to both host computers and must contain the system software needed to use the communication protocols of both host computers. The communication process between application partners can be divided into three phases: session establishment, data transfer, and session termination. The communication protocols supported by GATEWAY (DECnet, NETEX, and TCP/IP) have addressing mechanisms that allow an application to identify itself and distinguish among other applications on the network. The exact form of the address varies depending on whether an application is passively offering (awaiting the receipt of a network connection from another network application) or actively connecting to another network. When the gateway is started, GATEWAY reads a file of address pairs. One of the address pairs is used by GATEWAY for passively offering on one network while the other address in the pair is used for actively connecting on the other network establishing the session. Now the two application partners can send and receive data in a manner appropriate to their home networks. GATEWAY accommodates full duplex transmissions. Thus, if the application partners are sophisticated enough, they can send and receive simultaneously. GATEWAY also keeps track of the number

  18. A Gateway Protocol Based on FIPA-ACL for the New Agent Platform PANGEA

    OpenAIRE

    Sánchez, Alejandro; Villarrubia González, Gabriel; Zato Domínguez, Carolina; Rodríguez González, Sara; Chamoso Santos, Pablo

    2013-01-01

    Communication is one of the cornerstones of the intelligent agents paradigm. There are different forms of communication between agents, just as there are many platforms for creating them. However, one of the problems we encountered when using the agent paradigm is the actual communication between platforms. That is, to have a gateway of communication between different types of agents regardless of the platform has been used to create them. To this end, a new way of communication between PANGE...

  19. 3081//sub E/ processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

    1983-03-01

    Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

  20. A science data gateway for environmental management: A SCIENCE DATA GATEWAY FOR ENVIRONMENTAL MANAGEMENT

    Energy Technology Data Exchange (ETDEWEB)

    Agarwal, Deborah A. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Faybishenko, Boris [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Freedman, Vicky L. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Krishnan, Harinarayan [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Kushner, Gary [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lansing, Carina [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Porter, Ellen [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Romosan, Alexandru [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Shoshani, Arie [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Wainwright, Haruko [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Weidmer, Arthur [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Wu, Kesheng [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

    2015-10-12

    Science data gateways are effective in providing complex science data collections to the world-wide user communities. In this paper we describe a gateway for the Advanced Simulation Capability for Environmental Management (ASCEM) framework. Built on top of established web service technologies, the ASCEM data gateway is specifically designed for environmental modeling applications. Its key distinguishing features include: (1) handling of complex spatiotemporal data, (2) offering a variety of selective data access mechanisms, (3) providing state of the art plotting and visualization of spatiotemporal data records, and (4) integrating seamlessly with a distributed workflow system using a RESTful interface. ASCEM project scientists have been using this data gateway since 2011.

  1. SCORPION II persistent surveillance system with universal gateway

    Science.gov (United States)

    Coster, Michael; Chambers, Jonathan; Brunck, Albert

    2009-05-01

    This paper addresses improvements and benefits derived from the next generation Northrop Grumman SCORPION II family of persistent surveillance and target recognition systems produced by the Xetron campus in Cincinnati, Ohio. SCORPION II reduces the size, weight, and cost of all SCORPION components in a flexible, field programmable system that is easier to conceal, backward compatible, and enables integration of over forty Unattended Ground Sensor (UGS) and camera types from a variety of manufacturers, with a modular approach to supporting multiple Line of Sight (LOS) and Beyond Line of Sight (BLOS) communications interfaces. Since 1998 Northrop Grumman has been integrating best in class sensors with its proven universal modular Gateway to provide encrypted data exfiltration to Common Operational Picture (COP) systems and remote sensor command and control. In addition to being fed to COP systems, SCORPION and SCORPION II data can be directly processed using a common sensor status graphical user interface (GUI) that allows for viewing and analysis of images and sensor data from up to seven hundred SCORPION system Gateways on single or multiple displays. This GUI enables a large amount of sensor data and imagery to be used for actionable intelligence as well as remote sensor command and control by a minimum number of analysts.

  2. Center for Integrated Nanotechnologies (CINT) - Gateway

    Data.gov (United States)

    Federal Laboratory Consortium — The CINT Gateway to Los Alamos Facility, located at Los Alamos National Laboratory in the center of the Materials Science Complex, brings together materials science...

  3. Environmental Dataset Gateway (EDG) REST Interface

    Data.gov (United States)

    U.S. Environmental Protection Agency — Use the Environmental Dataset Gateway (EDG) to find and access EPA's environmental resources. Many options are available for easily reusing EDG content in other...

  4. The EPICS process variable Gateway Version 2

    International Nuclear Information System (INIS)

    Evans, K.

    2005-01-01

    The EPICS Process Variable Gateway is both a Channel Access Server and Channel Access Client that provides a means for many clients, typically on different subnets, to access a process variable while making only one connection to the server that owns the process variable. It also provides additional access security beyond that implemented on the server. It thus protects critical servers while providing suitably restricted access to needed process variables. The original version of the Gateway worked with EPICS Base 3.13 but required a special version, since the changes necessary for its operation were never incorporated into EPICS Base. Version 2 works with any standard EPICS Base 3.14.6 or later and has many improvements in both performance and features over the older version. The Gateway is now used at many institutions and has become a stable, high-performance application. It is capable of handling tens of thousands of process variables with hundreds of thousands of events per second. It has run for over three months in a production environment without having to be restarted. It has many internal process variables that can be used to monitor its state using standard EPICS client tools, such as MEDM and StripTool. Other internal process variables can be used to stop the Gateway, make several kinds of reports, or change the access security without stopping the Gateway. It can even be started on remote workstations from MEDM by using a Secure Shell script. This paper will describe the new Gateway and how it is used. The Gateway is both a server (like an EPICS Input/Output Controller (IOC)) and a client (like the EPICS Motif Editor and Display Manager (MEDM), StripTool, and others). Clients connect to the server side, and the client side connects to IOCs and other servers, possibly other Gateways. See Fig. 1. There are perhaps three principal reasons for using the Gateway: (1) it allows many clients to access a process variable while making only one connection to

  5. Distributed intelligence at CELLO

    International Nuclear Information System (INIS)

    Boer, W. de

    1981-01-01

    This paper describes the use of distributed intelligence at CELLO, a large 4π detector at PETRA. Besides special purpose hardware processors for online calibration and reformatting of data, several microcomputers are used for monitoring and testing the various detector components. (orig.)

  6. MIRATE: MIps RATional dEsign Science Gateway.

    Science.gov (United States)

    Busato, Mirko; Distefano, Rosario; Bates, Ferdia; Karim, Kal; Bossi, Alessandra Maria; López Vilariño, José Manuel; Piletsky, Sergey; Bombieri, Nicola; Giorgetti, Alejandro

    2018-06-13

    Molecularly imprinted polymers (MIPs) are high affinity robust synthetic receptors, which can be optimally synthesized and manufactured more economically than their biological equivalents (i.e. antibody). In MIPs production, rational design based on molecular modeling is a commonly employed technique. This mostly aids in (i) virtual screening of functional monomers (FMs), (ii) optimization of monomer-template ratio, and (iii) selectivity analysis. We present MIRATE, an integrated science gateway for the intelligent design of MIPs. By combining and adapting multiple state-of-the-art bioinformatics tools into automated and innovative pipelines, MIRATE guides the user through the entire process of MIPs' design. The platform allows the user to fully customize each stage involved in the MIPs' design, with the main goal to support the synthesis in the wet-laboratory. MIRATE is freely accessible with no login requirement at http://mirate.di.univr.it/. All major browsers are supported.

  7. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  8. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

  9. The Molen Polymorphic Media Processor

    NARCIS (Netherlands)

    Kuzmanov, G.K.

    2004-01-01

    In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

  10. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  11. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  12. PixonVision real-time video processor

    Science.gov (United States)

    Puetter, R. C.; Hier, R. G.

    2007-09-01

    PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

  13. Video frame processor

    International Nuclear Information System (INIS)

    Joshi, V.M.; Agashe, Alok; Bairi, B.R.

    1993-01-01

    This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

  14. Trigger and decision processors

    International Nuclear Information System (INIS)

    Franke, G.

    1980-11-01

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  15. Optical Finite Element Processor

    Science.gov (United States)

    Casasent, David; Taylor, Bradley K.

    1986-01-01

    A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

  16. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  17. Dust Measurements Onboard the Deep Space Gateway

    Science.gov (United States)

    Horanyi, M.; Kempf, S.; Malaspina, D.; Poppe, A.; Srama, R.; Sternovsky, Z.; Szalay, J.

    2018-02-01

    A dust instrument onboard the Deep Space Gateway will revolutionize our understanding of the dust environment at 1 AU, help our understanding of the evolution of the solar system, and improve dust hazard models for the safety of crewed and robotic missions.

  18. An HDLC communication processor

    International Nuclear Information System (INIS)

    Brehmer, W.; Wawer, W.

    1981-09-01

    Systems for data acquisition and process control may comprise several intelligent stations with local computing power, each of them performing specific tasks in the control system. These stations generally are not independent of each other but are interconnected by the process being monitored or controlled. Therefore they must communicate with each other by transmitting or receiving messages which may contain instructions directed to the control system, status information and data from peripheral devices, variables which synchronize the execution of programs in the autonomous intelligent stations, and data for man-machine communication. This report describes a microprocessor based device which interfaces the I/O port of a host computer (CAMAC Dataway) to an HDLC bus system. The microprocessor (M6800) performs the HDLC protocol for a Multi-Point Unbalanced System. (orig.) [de

  19. SEDAC information gateway plan V(1)

    Science.gov (United States)

    Chen, Robert S. (Compiler)

    1995-01-01

    This annual update of the Information Gateway Plan incorporates changes recommended by the Socioeconomic Data and Applications Center (SEDAC) User Working Group (UWG) and reflects comments and suggestions from users, collaborators, and the Contracting Officer Technical Representative (COTR). The Information Gateway Plan is a concise and specific plan that outlines SEDAC activities and services in support of the earth and social sciences and other user communities. The SEDAC Information Gateway effort is a primary means by which the Earth Observing System Data and Information System (EOSDIS) can link meaningfully with a broad range of social science data sources and users in ways that lead to tangible benefits to the American people. The SEDAC Information Gateway provides interdisciplinary access to socioeconomic and physical science data and information resources held by SEDAC and numerous other institutions and networks around the world. The Plan describes the areas of research of earth scientists and socioeconomic scientists where interchange of data and information is most needed. It sets guidelines for the continued development of SEDAC's directory of social science datasets and establishes priorities for efforts to make data held by SEDAC or accessible through SEDAC available to the user community. The Plan also describes the means by which the SEDAC user community can access information products specified by the SEDAC Data and Applications Development Plan (DADP). Among other major activities, SEDAC will continue to enhance and operate a directory capability, interoperable with the Global Change Master Directory, that provides the socioeconomic community with information about earth science products and the earth science research community with information about socioeconomic data. The Information Gateway also serves as a unique and powerful access pathway for a wide range of users and potential users of socioeconomic and earth science data, including

  20. Intelligence in Artificial Intelligence

    OpenAIRE

    Datta, Shoumen Palit Austin

    2016-01-01

    The elusive quest for intelligence in artificial intelligence prompts us to consider that instituting human-level intelligence in systems may be (still) in the realm of utopia. In about a quarter century, we have witnessed the winter of AI (1990) being transformed and transported to the zenith of tabloid fodder about AI (2015). The discussion at hand is about the elements that constitute the canonical idea of intelligence. The delivery of intelligence as a pay-per-use-service, popping out of ...

  1. Composable processor virtualization for embedded systems

    NARCIS (Netherlands)

    Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

    2010-01-01

    Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

  2. BASSET: Scalable Gateway Finder in Large Graphs

    Energy Technology Data Exchange (ETDEWEB)

    Tong, H; Papadimitriou, S; Faloutsos, C; Yu, P S; Eliassi-Rad, T

    2010-11-03

    Given a social network, who is the best person to introduce you to, say, Chris Ferguson, the poker champion? Or, given a network of people and skills, who is the best person to help you learn about, say, wavelets? The goal is to find a small group of 'gateways': persons who are close enough to us, as well as close enough to the target (person, or skill) or, in other words, are crucial in connecting us to the target. The main contributions are the following: (a) we show how to formulate this problem precisely; (b) we show that it is sub-modular and thus it can be solved near-optimally; (c) we give fast, scalable algorithms to find such gateways. Experiments on real data sets validate the effectiveness and efficiency of the proposed methods, achieving up to 6,000,000x speedup.

  3. Distributed processor systems

    International Nuclear Information System (INIS)

    Zacharov, B.

    1976-01-01

    In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)

  4. Theater gateway closure: a strategic level barricade

    Science.gov (United States)

    logistical planners at the strategic level can anticipate or mitigate the effects of a theater gateway closure on military operations. Through two...that at the strategic level the effects are based on the economic and diplomatic elements of the national power, affecting proportionally sustainment...Finally, logistical planners at the strategic level need to have a vast and ample knowledge and understanding of the operational environment to

  5. Neutron Science TeraGrid Gateway

    International Nuclear Information System (INIS)

    Lynch, Vickie E.; Chen, Meili; Cobb, John W.; Kohl, James Arthur; Miller, Stephen D.; Speirs, David A.; Vazhkudai, Sudharshan S.

    2010-01-01

    The unique contributions of the Neutron Science TeraGrid Gateway (NSTG) are the connection of national user facility instrument data sources to the integrated cyberinfrastructure of the National Science FoundationTeraGrid and the development of a neutron science gateway that allows neutron scientists to use TeraGrid resources to analyze their data, including comparison of experiment with simulation. The NSTG is working in close collaboration with the Spallation Neutron Source (SNS) at Oak Ridge as their principal facility partner. The SNS is a next-generation neutron source. It has completed construction at a cost of $1.4 billion and is ramping up operations. The SNS will provide an order of magnitude greater flux than any previous facility in the world and will be available to all of the nation's scientists, independent of funding source, on a peer-reviewed merit basis. With this new capability, the neutron science community is facing orders of magnitude larger data sets and is at a critical point for data analysis and simulation. There is a recognized need for new ways to manage and analyze data to optimize both beam time and scientific output. The TeraGrid is providing new capabilities in the gateway for simulations using McStas and a fitting service on distributed TeraGrid resources to improved turnaround. NSTG staff are also exploring replicating experimental data in archival storage. As part of the SNS partnership, the NSTG provides access to gateway support, cyberinfrastructure outreach, community development, and user support for the neutron science community. This community includes not only SNS staff and users but extends to all the major worldwide neutron scattering centers.

  6. Green Secure Processors: Towards Power-Efficient Secure Processor Design

    Science.gov (United States)

    Chhabra, Siddhartha; Solihin, Yan

    With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

  7. Processors and systems (picture processing)

    Energy Technology Data Exchange (ETDEWEB)

    Gemmar, P

    1983-01-01

    Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

  8. Seismometer array station processors

    International Nuclear Information System (INIS)

    Key, F.A.; Lea, T.G.; Douglas, A.

    1977-01-01

    A description is given of the design, construction and initial testing of two types of Seismometer Array Station Processor (SASP), one to work with data stored on magnetic tape in analogue form, the other with data in digital form. The purpose of a SASP is to detect the short period P waves recorded by a UK-type array of 20 seismometers and to edit these on to a a digital library tape or disc. The edited data are then processed to obtain a rough location for the source and to produce seismograms (after optimum processing) for analysis by a seismologist. SASPs are an important component in the scheme for monitoring underground explosions advocated by the UK in the Conference of the Committee on Disarmament. With digital input a SASP can operate at 30 times real time using a linear detection process and at 20 times real time using the log detector of Weichert. Although the log detector is slower, it has the advantage over the linear detector that signals with lower signal-to-noise ratio can be detected and spurious large amplitudes are less likely to produce a detection. It is recommended, therefore, that where possible array data should be recorded in digital form for input to a SASP and that the log detector of Weichert be used. Trial runs show that a SASP is capable of detecting signals down to signal-to-noise ratios of about two with very few false detections, and at mid-continental array sites it should be capable of detecting most, if not all, the signals with magnitude above msub(b) 4.5; the UK argues that, given a suitable network, it is realistic to hope that sources of this magnitude and above can be detected and identified by seismological means alone. (author)

  9. A Smart Home Gateway Platform for Data Collection and Awareness

    OpenAIRE

    Wang, Pan; Ye, Feng; Chen, Xuejiao

    2018-01-01

    Smart homes have attracted much attention due to the expanding of Internet-of-Things (IoT) and smart devices. In this paper, we propose a smart gateway platform for data collection and awareness in smart home networks. A smart gateway will replace the traditional network gateway to connect the home network and the Internet. A smart home network supports different types of smart devices, such as in home IoT devices, smart phones, smart electric appliances, etc. A traditional network gateway is...

  10. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  11. Reflections on science gateways sustainability through the business model canvas: case study of a neuroscience gateway

    NARCIS (Netherlands)

    Shahand, S.; van Duffelen, J.; Olabarriaga, S. D.

    2015-01-01

    The sustainability of science gateways has been a topic of active discussion because they have been created and supported in the context of temporary research and infrastructure projects. As successful projects come to an end, it is necessary to find (new) models to secure continuous exploitation of

  12. The Gateway to Cosmic Dawn: A Low Frequency Radio Telescope for the Deep Space Gateway

    Science.gov (United States)

    Tauscher, K.; Burns, J. O.; Monsalve, R.; Rapetti, D.

    2018-02-01

    We suggest that, with a suitable antenna and receiver, the Deep Space Gateway can be used to measure the highly redshifted, global 21-cm signal from neutral hydrogen, a spectral imprint of the history of the universe onto cosmic background radiation.

  13. Improving interoperability through gateways and cots technologies

    CSIR Research Space (South Africa)

    Smith, C

    2013-01-01

    Full Text Available simultaneously, reducing dramatically the time to deploy of the nodes. 4.2 Success History In [7] [8] it’s shown how an out-of-the-box Android smartphone can be used as an information gateway hosting JTRS SCA based public safety waveforms: AM, FM and APCO-P25... and the smartphone. Thus, the entire SCA stack, including the CRC’s Core Framework [8] and the OIS’s CORBA middleware [9] was installed in the Android smartphone. The three SCA compliant waveforms were installed also in the phone. It’s worth to mention...

  14. Evolution of a C2 protocol gateway

    CSIR Research Space (South Africa)

    Duvenhage, A

    2008-06-01

    Full Text Available real-time or slower than real-time, depending on the type of link and the data source: The gateway normally reads logged raw protocol data much faster than real-time; a simulation could also start running slower than real-time if it requires too... inherent support for logging and playback of the raw protocol data. From a software architecture perspective, each link has a corresponding link component that is responsible for opening and closing the connection, as well as reading and writing...

  15. Convergence of Residential Gateway technology: analysis of evolutionary paths

    NARCIS (Netherlands)

    Hartog, den F.T.H.; Balm, M.; Jong, de C.M.; Kwaaitaal, J.J.B.

    2004-01-01

    A new OSI (Open Systems Interconnection)-based model is described that can be used for the classification of residential gateways (RG). It is applied to analyze current gateway solutions and to draw evolutionary paths for the mid-to-long term. It is concluded that set-top boxes and broadband modems

  16. A data-centric neuroscience gateway: design, implementation, and experiences

    NARCIS (Netherlands)

    Shahand, Shayan; Benabdelkader, Ammar; Jaghoori, Mohammad Mahdi; al Mourabit, Mostapha; Huguet, Jordi; Caan, Matthan W. A.; van Kampen, Antoine H. C.; Olabarriaga, Silvia D.

    2015-01-01

    Science gateways provide UIs and high-level services to access and manage applications and data collections on distributed resources. They facilitate users to perform data analysis on distributed computing infrastructures without getting involved into the technical details. The e-BioInfra Gateway is

  17. XL-100S microprogrammable processor

    International Nuclear Information System (INIS)

    Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

    1983-01-01

    The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

  18. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  19. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  20. Optical Array Processor: Laboratory Results

    Science.gov (United States)

    Casasent, David; Jackson, James; Vaerewyck, Gerard

    1987-01-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

  1. Fast processor for dilepton triggers

    International Nuclear Information System (INIS)

    Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

    1983-01-01

    We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

  2. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

  3. VON WISPR Family Processors: Volume 1

    National Research Council Canada - National Science Library

    Wagstaff, Ronald

    1997-01-01

    ...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

  4. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

  5. Performance Evaluation of a Multipurpose Bare PC Gateway

    DEFF Research Database (Denmark)

    Tsetse, Anthony; Appiah-Kubi, Patrick; Loukili, Alae

    2015-01-01

    . Different solutions (6to4 tunneling, IVI translation, NAT64, DNS64 etc.), have being proposed but these are all standalone systems. In this paper we discuss the design,implementation and performance evaluation of a multipurpose Bare PC Gateway which incorporates Network Address translation (NAT), 6to4...... results indicate a relatively better performance (18%-45%) of the Bare PC gateway compared to a Linux gateway (running the functionalities as standalone systems). We believe the proposed solution could easily scale to wide area networks and also provide a cost efficient solution...

  6. Deterministic chaos in the processor load

    International Nuclear Information System (INIS)

    Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

    2007-01-01

    In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

  7. Gateways: Expanding knowledge through broader participation

    Directory of Open Access Journals (Sweden)

    Phil Nyden

    2008-09-01

    Full Text Available This new journal, Gateways: International Journal of Community Research and Engagement, responds to a growing global movement of university-collaborative research initiatives. It also strives to fill a gap created by the sparse number of journals which publish outcomes of community-engaged research and work concerning community engagement. We seek articles based on research that is the result of actively engaged research-practitioner collaborative projects, has the potential of informing community-based activities or develops understanding of community engagement. Combining different knowledge bases that have traditionally been separated into academic and non-academic worlds can dramatically increase information flowing to scholars, community leaders and activists seeking to improve the quality of life in local communities around the world. We also wish to encourage work that contributes to the scholarship of engagement.

  8. Accessibility: global gateway to health literacy.

    Science.gov (United States)

    Perlow, Ellen

    2010-01-01

    Health literacy, cited as essential to achieving Healthy People 2010's goals to "increase quality and years of healthy life" and to "eliminate health disparities," is defined by Healthy People as "the degree to which individuals have the capacity to obtain, process, and understand basic health information and services needed to make appropriate health decisions." Accessibility, by definition, the aforementioned "capacity to obtain," thus is health literacy's primary prerequisite. Accessibility's designation as the global gateway to health literacy is predicated also on life's realities: global aging and climate change, war and terrorism, and life-extending medical and technological advances. People with diverse access needs are health professionals' raison d'être. However, accessibility, consummately cross-cultural and universal, is virtually absent as a topic of health promotion and practice research and scholarly discussion of health literacy and equity. A call to action to place accessibility in its rightful premier position on the profession's agenda is issued.

  9. Service interoperability through advanced media gateways

    CERN Document Server

    van der Meer, S

    2000-01-01

    The convergence of telecommunications systems and the Internet causes a variety of concepts for service integration. The focus of the recent research studies and the work of several standardization bodies lies mostly on the interworking of services and the universal service access from end-user systems including both fixed and wireless terminals. All approaches are driven by the concept of providing several technologies to users by keeping the peculiarity of each service alive. But, developments should not only concentrate on media adaptation between VoIP and PSTN, but also consider the adaptation among completely different types of applications as for example E- mail, facsimile, or voice. Unified messaging, which is an already accepted service on the market, provides solutions for conversions of different application protocols into each other. The functionality of converting one medium into another is implemented here in so-called media gateways. This paper provides an overview of the current developments in...

  10. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  11. Online Fastbus processor for LEP

    International Nuclear Information System (INIS)

    Mueller, H.

    1986-01-01

    The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

  12. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  13. Starshade Assembly Enabled by the Deep Space Gateway Architecture

    Science.gov (United States)

    Grunsfeld, J. M.; Siegler, N.; Mukherjee, R.

    2018-02-01

    A starshade is a large external coronagraph which will allow the direct imaging and analysis of planets around nearby stars. We present how the Deep Space Gateway would enable the robotic/astronaut construction of a starshade.

  14. Software Defined Radio (SDR) Overlay Node Gateway, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal details a novel mobile data transceiver solution that supports standalone wireless sensors and concurrently acts as a gateway between multiple sensor...

  15. Mumbai harbour, India: Gateway for introduction of marine organisms

    Digital Repository Service at National Institute of Oceanography (India)

    Gaonkar, C.; Sawant, S.S.; Anil, A; Venkat, K.; Harkantra, S.N.

    Ships have been identified as one of the important vectors in the translocation of organisms from one bioregion to another leading to bioinvasion. In this context, harbours serve as a gateway for the introduction of alien species. Surveys were...

  16. Environmental Dataset Gateway (EDG) CS-W Interface

    Data.gov (United States)

    U.S. Environmental Protection Agency — Use the Environmental Dataset Gateway (EDG) to find and access EPA's environmental resources. Many options are available for easily reusing EDG content in other...

  17. Intelligible Artificial Intelligence

    OpenAIRE

    Weld, Daniel S.; Bansal, Gagan

    2018-01-01

    Since Artificial Intelligence (AI) software uses techniques like deep lookahead search and stochastic optimization of huge neural networks to fit mammoth datasets, it often results in complex behavior that is difficult for people to understand. Yet organizations are deploying AI algorithms in many mission-critical settings. In order to trust their behavior, we must make it intelligible --- either by using inherently interpretable models or by developing methods for explaining otherwise overwh...

  18. An Authentication Gateway for Integrated Grid and Cloud Access

    International Nuclear Information System (INIS)

    Ciaschini, V; Salomoni, D

    2011-01-01

    The WNoDeS architecture, providing distributed, integrated access to both Cloud and Grid resources through virtualization technologies, makes use of an Authentication Gateway to support diverse authentication mechanisms. Three main use cases are foreseen, covering access via X.509 digital certificates, federated services like Shibboleth or Kerberos, and credit-based access. In this paper, we describe the structure of the WNoDeS authentication gateway.

  19. Mentoring the Next Generation of Science Gateway Developers and Users

    Science.gov (United States)

    Hayden, L. B.; Jackson-Ward, F.

    2016-12-01

    The Science Gateway Institute (SGW-I) for the Democratization and Acceleration of Science was a SI2-SSE Collaborative Research conceptualization award funded by NSF in 2012. From 2012 through 2015, we engaged interested members of the science and engineering community in a planning process for a Science Gateway Community Institute (SGCI). Science Gateways provide Web interfaces to some of the most sophisticated cyberinfrastructure resources. They interact with remotely executing science applications on supercomputers, they connect to remote scientific data collections, instruments and sensor streams, and support large collaborations. Gateways allow scientists to concentrate on the most challenging science problems while underlying components such as computing architectures and interfaces to data collection changes. The goal of our institute was to provide coordinating activities across the National Science Foundation, eventually providing services more broadly to projects funded by other agencies. SGW-I has succeeded in identifying two underrepresented communities of future gateway designers and users. The Association of Computer and Information Science/Engineering Departments at Minority Institutions (ADMI) was identified as a source of future gateway designers. The National Organization for the Professional Advancement of Black Chemists and Chemical Engineers (NOBCChE) was identified as a community of future science gateway users. SGW-I efforts to engage NOBCChE and ADMI faculty and students in SGW-I are now woven into the workforce development component of SGCI. SGCI (ScienceGateways.org ) is a collaboration of six universities, led by San Diego Supercomputer Center. The workforce development component is led by Elizabeth City State University (ECSU). ECSU efforts focus is on: Produce a model of engagement; Integration of research into education; and Mentoring of students while aggressively addressing diversity. This paper documents the outcome of the SGW

  20. High-performance parallel interface to synchronous optical network gateway

    Science.gov (United States)

    St. John, Wallace B.; DuBois, David H.

    1998-08-11

    A digital system provides sending and receiving gateways for HIPPI interfaces. Electronic logic circuitry formats data signals and overhead signals in a data frame that is suitable for transmission over a connecting fiber optic link. Multiplexers route the data and overhead signals to a framer module. The framer module allocates the data and overhead signals to a plurality of 9-byte words that are arranged in a selected protocol. The formatted words are stored in a storage register for output through the gateway.

  1. Access control mechanism of wireless gateway based on open flow

    Science.gov (United States)

    Peng, Rong; Ding, Lei

    2017-08-01

    In order to realize the access control of wireless gateway and improve the access control of wireless gateway devices, an access control mechanism of SDN architecture which is based on Open vSwitch is proposed. The mechanism utilizes the features of the controller--centralized control and programmable. Controller send access control flow table based on the business logic. Open vSwitch helps achieve a specific access control strategy based on the flow table.

  2. A Gateway MultiSite recombination cloning toolkit.

    Directory of Open Access Journals (Sweden)

    Lena K Petersen

    Full Text Available The generation of DNA constructs is often a rate-limiting step in conducting biological experiments. Recombination cloning of single DNA fragments using the Gateway system provided an advance over traditional restriction enzyme cloning due to increases in efficiency and reliability. Here we introduce a series of entry clones and a destination vector for use in two, three, and four fragment Gateway MultiSite recombination cloning whose advantages include increased flexibility and versatility. In contrast to Gateway single-fragment cloning approaches where variations are typically incorporated into model system-specific destination vectors, our Gateway MultiSite cloning strategy incorporates variations in easily generated entry clones that are model system-independent. In particular, we present entry clones containing insertions of GAL4, QF, UAS, QUAS, eGFP, and mCherry, among others, and demonstrate their in vivo functionality in Drosophila by using them to generate expression clones including GAL4 and QF drivers for various trp ion channel family members, UAS and QUAS excitatory and inhibitory light-gated ion channels, and QUAS red and green fluorescent synaptic vesicle markers. We thus establish a starter toolkit of modular Gateway MultiSite entry clones potentially adaptable to any model system. An inventory of entry clones and destination vectors for Gateway MultiSite cloning has also been established (www.gatewaymultisite.org.

  3. Framework Programmable Platform for the advanced software development workstation: Framework processor design document

    Science.gov (United States)

    Mayer, Richard J.; Blinn, Thomas M.; Mayer, Paula S. D.; Ackley, Keith A.; Crump, Wes; Sanders, Les

    1991-01-01

    The design of the Framework Processor (FP) component of the Framework Programmable Software Development Platform (FFP) is described. The FFP is a project aimed at combining effective tool and data integration mechanisms with a model of the software development process in an intelligent integrated software development environment. Guided by the model, this Framework Processor will take advantage of an integrated operating environment to provide automated support for the management and control of the software development process so that costly mistakes during the development phase can be eliminated.

  4. Teaching Synaesthesia as a Gateway to Creativity

    Directory of Open Access Journals (Sweden)

    Monica D. Murgia

    2015-04-01

    Full Text Available This article encapsulates my experience of teaching creativity within a higher education curriculum. Creativity often eludes common understanding because it involves using different conceptual streams of thought, often times developing unconsciously and manifesting in the prized “eureka” moment. In 2009, I began explaining the neurological condition of synaesthesia and later introduced this phenomenology in a course designed to cultivate creativity to first year fashion design students. There are many challenges in teaching creativity. Through teaching this course, I discovered that the first challenge is making the students conscious of their own qualitative beliefs on creativity and art. The second is creating exercises to challenge and alter these beliefs, thus forming a new way of thinking and experiencing the world. The most resistance from my students arose when experimenting with non-representational art. They did not have a conscious framework for making and evaluating abstract art. Introducing synaesthesia, a neurologically-based condition that “merges” two or more sensory pathways in the brain, gave my students a framework for discovery. Understanding sensory modalities and ways in which these modalities can blended together in synaesthesia proved to be a gateway to creativity in many of my students. The scope of this article chronicles how I developed my teaching methodology, the results it created in my classroom, as well as its effects on my own artistic practice.

  5. An Innovative Gateway for Indoor Positioning

    Directory of Open Access Journals (Sweden)

    Marias Giannis F

    2006-01-01

    Full Text Available Enabling the pervasive paradigm requires the incorporation of location information. Retrieving location data has been a field of ongoing research for both the outdoor and indoor wireless systems. The results in the cellular scenario are already mature and location architectures have been standardized. Recent research is ongoing for indoor-positioning mechanisms, resulting in implementations that vary. A platform that enables the deployment of location-based services in heterogeneous indoor and WLAN-based communication systems will address difficulties in cooperating with different positioning systems. For that purpose, we have designed a novel entity, called Gateway WLAN Location Center (GWLC, which hides the heterogeneous functions of the indoor positioning architectures, incorporating a unified framework for retrieving location data of users and objects. The GWLC platform has been designed to meet objectives such as modularity, scalability, as well as portability, and to facilitate open interfaces. In this contribution, we elaborate on the design principles and the functionality of GWLC. We also provide performance results, obtained through real experiments.

  6. Artificial intelligence

    CERN Document Server

    Hunt, Earl B

    1975-01-01

    Artificial Intelligence provides information pertinent to the fundamental aspects of artificial intelligence. This book presents the basic mathematical and computational approaches to problems in the artificial intelligence field.Organized into four parts encompassing 16 chapters, this book begins with an overview of the various fields of artificial intelligence. This text then attempts to connect artificial intelligence problems to some of the notions of computability and abstract computing devices. Other chapters consider the general notion of computability, with focus on the interaction bet

  7. Intelligent mechatronics; Intelligent mechatronics

    Energy Technology Data Exchange (ETDEWEB)

    Hashimoto, H. [The University of Tokyo, Tokyo (Japan). Institute of Industrial Science

    1995-10-01

    Intelligent mechatronics (IM) was explained as follows: a study of IM essentially targets realization of a robot namely, but in the present stage the target is a creation of new values by intellectualization of machine, that is, a combination of the information infrastructure and the intelligent machine system. IM is also thought to be constituted of computers positively used and micromechatronics. The paper next introduces examples of IM study, mainly those the author is concerned with as shown below: sensor gloves, robot hands, robot eyes, tele operation, three-dimensional object recognition, mobile robot, magnetic bearing, construction of remote controlled unmanned dam, robot network, sensitivity communication using neuro baby, etc. 27 figs.

  8. A Methodolgy, Based on Analytical Modeling, for the Design of Parallel and Distributed Architectures for Relational Database Query Processors.

    Science.gov (United States)

    1987-12-01

    Application Programs Intelligent Disk Database Controller Manangement System Operating System Host .1’ I% Figure 2. Intelligent Disk Controller Application...8217. /- - • Database Control -% Manangement System Disk Data Controller Application Programs Operating Host I"" Figure 5. Processor-Per- Head data. Therefore, the...However. these ad- ditional properties have been proven in classical set and relation theory [75]. These additional properties are described here

  9. Accuracies Of Optical Processors For Adaptive Optics

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1992-01-01

    Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

  10. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  11. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  12. The UA1 trigger processor

    International Nuclear Information System (INIS)

    Grayer, G.H.

    1981-01-01

    Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

  13. Artificial Intelligence and Moral intelligence

    OpenAIRE

    Laura Pana

    2008-01-01

    We discuss the thesis that the implementation of a moral code in the behaviour of artificial intelligent systems needs a specific form of human and artificial intelligence, not just an abstract intelligence. We present intelligence as a system with an internal structure and the structural levels of the moral system, as well as certain characteristics of artificial intelligent agents which can/must be treated as 1- individual entities (with a complex, specialized, autonomous or selfdetermined,...

  14. Data register and processor for multiwire chambers

    International Nuclear Information System (INIS)

    Karpukhin, V.V.

    1985-01-01

    A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

  15. Many - body simulations using an array processor

    International Nuclear Information System (INIS)

    Rapaport, D.C.

    1985-01-01

    Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

  16. Sensitometric control of roentgen film processors

    International Nuclear Information System (INIS)

    Forsberg, H.; Karolinska Sjukhuset, Stockholm

    1987-01-01

    Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

  17. The Einstein Genome Gateway using WASP - a high throughput multi-layered life sciences portal for XSEDE.

    Science.gov (United States)

    Golden, Aaron; McLellan, Andrew S; Dubin, Robert A; Jing, Qiang; O Broin, Pilib; Moskowitz, David; Zhang, Zhengdong; Suzuki, Masako; Hargitai, Joseph; Calder, R Brent; Greally, John M

    2012-01-01

    Massively-parallel sequencing (MPS) technologies and their diverse applications in genomics and epigenomics research have yielded enormous new insights into the physiology and pathophysiology of the human genome. The biggest hurdle remains the magnitude and diversity of the datasets generated, compromising our ability to manage, organize, process and ultimately analyse data. The Wiki-based Automated Sequence Processor (WASP), developed at the Albert Einstein College of Medicine (hereafter Einstein), uniquely manages to tightly couple the sequencing platform, the sequencing assay, sample metadata and the automated workflows deployed on a heterogeneous high performance computing cluster infrastructure that yield sequenced, quality-controlled and 'mapped' sequence data, all within the one operating environment accessible by a web-based GUI interface. WASP at Einstein processes 4-6 TB of data per week and since its production cycle commenced it has processed ~ 1 PB of data overall and has revolutionized user interactivity with these new genomic technologies, who remain blissfully unaware of the data storage, management and most importantly processing services they request. The abstraction of such computational complexity for the user in effect makes WASP an ideal middleware solution, and an appropriate basis for the development of a grid-enabled resource - the Einstein Genome Gateway - as part of the Extreme Science and Engineering Discovery Environment (XSEDE) program. In this paper we discuss the existing WASP system, its proposed middleware role, and its planned interaction with XSEDE to form the Einstein Genome Gateway.

  18. GATEWAY Report Brief: SSL Demonstration: Long-Term Evaluation of Indoor Field Performance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2017-02-28

    Report brief summarizing a GATEWAY program evaluation of the long-term performance characteristics (chromaticity change, maintained illuminance, and operations and maintenance) of LED lighting systems in four field installations previously documented in separate DOE GATEWAY reports.

  19. GATEWAY Demonstrations: Long-Term Evaluation of SSL Field Performance in Select Interior Projects

    Energy Technology Data Exchange (ETDEWEB)

    Davis, Tess E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Davis, Robert G. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Wilkerson, Andrea M. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2017-02-28

    The GATEWAY program evaluated the long-term performance characteristics (chromaticity change, maintained illuminance, and operations and maintenance) of LED lighting systems in four field installations previously documented in separate DOE GATEWAY reports.

  20. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    Kaerhae, K.; Jouhiaho, A.

    2009-01-01

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  1. Data-intensive science gateway for rock physicists and volcanologists.

    Science.gov (United States)

    Filgueira, Rosa; Atkinson, Malcom; Bell, Andrew; Main, Ian; Boon, Steve; Meredith, Philp; Kilburn, Christopher

    2014-05-01

    Scientists have always shared data and mathematical models of the phenomena they study. Rock physics and Volcanology, as well as other solid-Earth sciences, have increasingly used Internet communications and computational renditions of their models for this purpose over the last two decades. Here we consider how to organise rock physics and volcanology data to open up opportunities for sharing and comparing both experiment data from experiments, observations and model runs and analytic interpretations of these data. Our hypothesis is that if we facilitate productive information sharing across those communities by using a new science gateway, it will benefit the science. The proposed science gateway should make the first steps for making existing research practices easier and facilitate new research. It will achieve this by supporting three major functions: 1) sharing data from laboratories and observatories, experimental facilities and models; 2) sharing models of rock fracture and methods for analysing experimental data; and 3) supporting recurrent operational tasks, such as data collection and model application in real time. We report initial work in two projects (NERC EFFORT and NERC CREEP-2) and experience with an early web-accessible protytpe called EFFORT gateway, where we are implementing such information sharing services for those projects. 1. Sharing data: In EFFORT gateway, we are working on several facilities for sharing data: *Upload data: We have designed and developed a new adaptive data transfer java tool called FAST (Flexible Automated Streaming Transfer) to upload experimental data and metadata periodically from laboratories to our repository. *Visualisation: As data are deposited in the repository, a visualisation of the accumulated data is made available for display in the Web portal. *Metadata and catalogues: The gateway uses a repository to hold all the data and a catalogue to hold all the corresponding metadata. 2. Sharing models and methods

  2. Pengembangan SMS Gateway Layanan Informasi Akademik di STMIK GI MDP

    Directory of Open Access Journals (Sweden)

    Fransiska Prihatini Sihotang

    2017-08-01

    Full Text Available Information technology can be utilized in education such as e-Learning and Academic Information System. STMIK GI MDP has applied information technology that provides ease for the dissemination of academic information to students. However, the parents of the students have not obtained the academic information of their children due to the lack of internet-related knowledge. Therefore, this study aims to create a service that is able to convey information to parents directly with SMS Gateway service. This research begins with the collection of user needs through observation techniques and interviews to academic staff and parents. Then performed the required feature analysis. Then the design of SMS Gateway application that will be embedded in existing academic applications and coding system. Gammu is used as a link between applications with mobile phones. The result of this research is the application of SMS Gateway service that can give the student academic information to the parents.

  3. Artificial intelligence and the future.

    Science.gov (United States)

    Clocksin, William F

    2003-08-15

    We consider some of the ideas influencing current artificial-intelligence research and outline an alternative conceptual framework that gives priority to social relationships as a key component and constructor of intelligent behaviour. The framework starts from Weizenbaum's observation that intelligence manifests itself only relative to specific social and cultural contexts. This is in contrast to a prevailing view, which sees intelligence as an abstract capability of the individual mind based on a mechanism for rational thought. The new approach is not based on the conventional idea that the mind is a rational processor of symbolic information, nor does it require the idea that thought is a kind of abstract problem solving with a semantics that is independent of its embodiment. Instead, priority is given to affective and social responses that serve to engage the whole agent in the life of the communities in which it participates. Intelligence is seen not as the deployment of capabilities for problem solving, but as constructed by the continual, ever-changing and unfinished engagement with the social group within the environment. The construction of the identity of the intelligent agent involves the appropriation or 'taking up' of positions within the conversations and narratives in which it participates. Thus, the new approach argues that the intelligent agent is shaped by the meaning ascribed to experience, by its situation in the social matrix, and by practices of self and of relationship into which intelligent life is recruited. This has implications for the technology of the future, as, for example, classic artificial intelligence models such as goal-directed problem solving are seen as special cases of narrative practices instead of as ontological foundations.

  4. Micro processors for plant protection

    International Nuclear Information System (INIS)

    McAffer, N.T.C.

    1976-01-01

    Micro computers can be used satisfactorily in general protection duties with economic advantages over hardwired systems. The reliability of such protection functions can be enhanced by keeping the task performed by each protection micro processor simple and by avoiding such a task being dependent on others in any substantial way. This implies that vital work done for any task is kept within it and that any communications from it to outside or to it from outside are restricted to those for controlling data transfer. Also that the amount of this data should be the minimum consistent with satisfactory task execution. Technology is changing rapidly and devices may become obsolete and be supplanted by new ones before their theoretical reliability can be confirmed or otherwise by field service. This emphasises the need for users to pool device performance data so that effective reliability judgements can be made within the lifetime of the devices. (orig.) [de

  5. Alcohol as a Gateway Drug: A Study of US 12th Graders

    Science.gov (United States)

    Kirby, Tristan; Barry, Adam E.

    2012-01-01

    Background: The Gateway Drug Theory suggests that licit drugs, such as tobacco and alcohol, serve as a "gateway" toward the use of other, illicit drugs. However, there remains some discrepancy regarding which drug--alcohol, tobacco, or even marijuana--serves as the initial "gateway" drug subsequently leading to the use of…

  6. Global Document Delivery, User Studies, and Service Evaluation: The Gateway Experience

    Science.gov (United States)

    Miller, Rush; Xu, Hong; Zou, Xiuying

    2008-01-01

    This study examines user and service data from 2002-2006 at the East Asian Gateway Service for Chinese and Korean Academic Journal Publications (Gateway Service), the University of Pittsburgh. Descriptive statistical analysis reveals that the Gateway Service has been consistently playing the leading role in global document delivery service as well…

  7. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  8. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

  9. The communication processor of TUMULT-64

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Jansen, P.G.

    1988-01-01

    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

  10. An interactive parallel processor for data analysis

    International Nuclear Information System (INIS)

    Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

    1984-01-01

    A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

  11. Design and implementation of Skype USB user gateway software

    Science.gov (United States)

    Qi, Yang

    2017-08-01

    With the widespread application of VoIP, the client with private protocol becomes more and more popular. Skype is one of the representatives. How to connect Skype with PSTN just by Skype client has gradually become hot. This paper design and implement the software based on a kind of USB User Gateway. With the software Skype user can freely communicate with PSTN phone. FSM is designed as the core of the software, and Skype control is separated by the USB Gateway control. In this way, the communication becomes more flexible and efficient. In the actual user testing, the software obtains good results.

  12. Advanced distributed simulation technology: Digital Voice Gateway Reference Guide

    Science.gov (United States)

    Vanhook, Dan; Stadler, Ed

    1994-01-01

    The Digital Voice Gateway (referred to as the 'DVG' in this document) transmits and receives four full duplex encoded speech channels over the Ethernet. The information in this document applies only to DVG's running firmware of the version listed on the title page. This document, previously named Digital Voice Gateway Reference Guide, BBN Systems and Technologies Corporation, Cambridge, MA 02138, was revised for revision 2.00. This new revision changes the network protocol used by the DVG, to comply with the SINCGARS radio simulation (For SIMNET 6.6.1). Because of the extensive changes to revision 2.00 a separate document was created rather than supplying change pages.

  13. Design and Realization of a Condition Management System for the Gateway Electrical Energy Metering Device

    Directory of Open Access Journals (Sweden)

    Chao Tang

    2013-12-01

    Full Text Available With the construction of firm and intelligent power grid in China, it is difficult for the traditional management method of electrical energy metering device to meet the prospecting requirements. Using the computer and internet techniques to realize the information and intelligentization of the electrical energy metering management has become a necessary guarantee of improving power supply ability, marketing control, and customer service. This paper introduced a kind of large and intelligent condition management system of the gateway electrical energy metering device. The key technologies and realize process were analyzed. Moreover, a detailed description of the application modules such as the GIS smart display of metering point, the condition management of metering devices and the visual monitoring of metering point was presented. The trial operation in the selected transformer substations and the power stations of Chongqing Power Electrical Corp. indicated that, the condition management system is very open, safety and efficient. According to the data exchange with the production and scheduling platform, the system improved the efficient operation of the electrical energy metering devices. Meanwhile, combined with the real-time visual monitoring, the condition management system improved the prevention ability of electricity filching, realized the unified automatic large-scale management of electrical energy metering devices.

  14. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  15. Development of a highly reliable CRT processor

    International Nuclear Information System (INIS)

    Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

    1996-01-01

    Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

  16. Online track processor for the CDF upgrade

    International Nuclear Information System (INIS)

    Thomson, E. J.

    2002-01-01

    A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

  17. Computer Generated Inputs for NMIS Processor Verification

    International Nuclear Information System (INIS)

    J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

    2001-01-01

    Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

  18. Artificial Intelligence.

    Science.gov (United States)

    Information Technology Quarterly, 1985

    1985-01-01

    This issue of "Information Technology Quarterly" is devoted to the theme of "Artificial Intelligence." It contains two major articles: (1) Artificial Intelligence and Law" (D. Peter O'Neill and George D. Wood); (2) "Artificial Intelligence: A Long and Winding Road" (John J. Simon, Jr.). In addition, it contains two sidebars: (1) "Calculating and…

  19. Competitive Intelligence.

    Science.gov (United States)

    Bergeron, Pierrette; Hiller, Christine A.

    2002-01-01

    Reviews the evolution of competitive intelligence since 1994, including terminology and definitions and analytical techniques. Addresses the issue of ethics; explores how information technology supports the competitive intelligence process; and discusses education and training opportunities for competitive intelligence, including core competencies…

  20. GPU: the biggest key processor for AI and parallel processing

    Science.gov (United States)

    Baji, Toru

    2017-07-01

    Two types of processors exist in the market. One is the conventional CPU and the other is Graphic Processor Unit (GPU). Typical CPU is composed of 1 to 8 cores while GPU has thousands of cores. CPU is good for sequential processing, while GPU is good to accelerate software with heavy parallel executions. GPU was initially dedicated for 3D graphics. However from 2006, when GPU started to apply general-purpose cores, it was noticed that this architecture can be used as a general purpose massive-parallel processor. NVIDIA developed a software framework Compute Unified Device Architecture (CUDA) that make it possible to easily program the GPU for these application. With CUDA, GPU started to be used in workstations and supercomputers widely. Recently two key technologies are highlighted in the industry. The Artificial Intelligence (AI) and Autonomous Driving Cars. AI requires a massive parallel operation to train many-layers of neural networks. With CPU alone, it was impossible to finish the training in a practical time. The latest multi-GPU system with P100 makes it possible to finish the training in a few hours. For the autonomous driving cars, TOPS class of performance is required to implement perception, localization, path planning processing and again SoC with integrated GPU will play a key role there. In this paper, the evolution of the GPU which is one of the biggest commercial devices requiring state-of-the-art fabrication technology will be introduced. Also overview of the GPU demanding key application like the ones described above will be introduced.

  1. Analytical Bounds on the Threads in IXP1200 Network Processor

    OpenAIRE

    Ramakrishna, STGS; Jamadagni, HS

    2003-01-01

    Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

  2. Intelligence Ethics:

    DEFF Research Database (Denmark)

    Rønn, Kira Vrist

    2016-01-01

    Questions concerning what constitutes a morally justified conduct of intelligence activities have received increased attention in recent decades. However, intelligence ethics is not yet homogeneous or embedded as a solid research field. The aim of this article is to sketch the state of the art...... of intelligence ethics and point out subjects for further scrutiny in future research. The review clusters the literature on intelligence ethics into two groups: respectively, contributions on external topics (i.e., the accountability of and the public trust in intelligence agencies) and internal topics (i.......e., the search for an ideal ethical framework for intelligence actions). The article concludes that there are many holes to fill for future studies on intelligence ethics both in external and internal discussions. Thus, the article is an invitation – especially, to moral philosophers and political theorists...

  3. WorldWideScience.org: the global science gateway.

    Science.gov (United States)

    Fitzpatrick, Roberta Bronson

    2009-10-01

    WorldWideScience.org is a Web-based global gateway connecting users to both national and international scientific databases and portals. This column will provide background information on the resource as well as introduce basic searching practices for users.

  4. Advances in Planetary Protection at the Deep Space Gateway

    Science.gov (United States)

    Spry, J. A.; Siegel, B.; Race, M.; Rummel, J. D.; Pugel, D. E.; Groen, F. J.; Kminek, G.; Conley, C. A.; Carosso, N. J.

    2018-02-01

    Planetary protection knowledge gaps that can be addressed by science performed at the Deep Space Gateway in the areas of human health and performance, space biology, and planetary sciences that enable future exploration in deep space, at Mars, and other targets.

  5. Tobacco, the Common Enemy and a Gateway Drug: Policy Implications

    Science.gov (United States)

    Torabi, Mohammad R.; Jun, Mi Kyung; Nowicke, Carole; Seitz de Martinez, Barbara; Gassman, Ruth

    2010-01-01

    For the four leading causes of death in the United States (heart disease, cancer, stroke and chronic respiratory disease), tobacco use is a common risk factor. Tobacco use is responsible for almost 450,000 deaths per year and impacts the health of every member of our society. Tobacco is a gateway drug for substance abuse. That role is critical to…

  6. Gateway to Careers. Postsecondary VSO Hones Workplace Skills.

    Science.gov (United States)

    Vernezze, Michael; Henkel, Marjorie

    1993-01-01

    The Gateway Marketing and Management Association is a local chapter of Delta Epsilon Chi, the postsecondary affiliate of Distributive Education Clubs of America. This vocational student organization provides leadership training and marketing skill development to prepare students for competition at state and national levels. (JOW)

  7. Network Gateway Technology: The Issue of Redundancy towards ...

    African Journals Online (AJOL)

    The Internet has provided advancement in the areas of network and networking facilities. Everyone connected to the Internet is concerned about two basic things: the availability of network services and the speed of the network. Network gateway redundancy technology falls within these categories and happens to be one of ...

  8. A Life-Course Perspective on the "Gateway Hypothesis"

    Science.gov (United States)

    Van Gundy, Karen; Rebellon, Cesar J.

    2010-01-01

    Drawing on stress and life-course perspectives and using panel data from 1,286 south Florida young adults, we assess three critical questions regarding the role of marijuana in the "gateway hypothesis." First, does teen marijuana use independently (causally) affect subsequent use of more dangerous substances? Second, if so, does that…

  9. Coal comprehensive utilization is the gateway for Shanxi Province

    International Nuclear Information System (INIS)

    Ma, L.; Gui, G.

    1997-01-01

    Shanxi Province is abundant in coal reserve. Taiyuan Coal Gasification Corporation is a large sized union enterprise engaged in comprehensive use of coal in Shanxi province, and significant economic, social, environmental benefits have been brought forth with it. This leads people to believe that coal comprehensive utilization is the gateway for Shanxi Province in the fields of improvement of environment and development of economy

  10. Network Gateway Technology: The Issue of Redundancy towards ...

    African Journals Online (AJOL)

    Everyone connected to the Internet is concerned about two basic things: the availability of network services and the speed of the network. Network gateway redundancy technology falls within these categories and happens to be one of the newest technologies which only few companies, such as mobile companies and ...

  11. Effect of processor temperature on film dosimetry

    International Nuclear Information System (INIS)

    Srivastava, Shiv P.; Das, Indra J.

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

  12. Optical Associative Processors For Visual Perception"

    Science.gov (United States)

    Casasent, David; Telfer, Brian

    1988-05-01

    We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

  13. Design of intelligent house system based on Yeelink

    Directory of Open Access Journals (Sweden)

    Lin Zhi-Huang

    2016-01-01

    Full Text Available In order to monitor the security situation of house in real time, an intelligent house remote monitoring system is designed based on Yeelink cloud services and ZigBee wireless communication technology. This system includes three parts, ZigBee wireless sensor networks, intelligent house gateway and Yeelink Cloud Services. Users can access Yeelink website or APP to get real time information in the house, receiving information including gas concentration, temperature. Also, remote commands can be sent from mobile devices to control the household appliances. The user who can monitor and control the house effectively through a simple and convenient user interface, will feel much more safe and comfortable.

  14. Development of Innovative Design Processor

    International Nuclear Information System (INIS)

    Park, Y.S.; Park, C.O.

    2004-01-01

    The nuclear design analysis requires time-consuming and erroneous model-input preparation, code run, output analysis and quality assurance process. To reduce human effort and improve design quality and productivity, Innovative Design Processor (IDP) is being developed. Two basic principles of IDP are the document-oriented design and the web-based design. The document-oriented design is that, if the designer writes a design document called active document and feeds it to a special program, the final document with complete analysis, table and plots is made automatically. The active documents can be written with ordinary HTML editors or created automatically on the web, which is another framework of IDP. Using the proper mix-up of server side and client side programming under the LAMP (Linux/Apache/MySQL/PHP) environment, the design process on the web is modeled as a design wizard style so that even a novice designer makes the design document easily. This automation using the IDP is now being implemented for all the reload design of Korea Standard Nuclear Power Plant (KSNP) type PWRs. The introduction of this process will allow large reduction in all reload design efforts of KSNP and provide a platform for design and R and D tasks of KNFC. (authors)

  15. Onboard spectral imager data processor

    Science.gov (United States)

    Otten, Leonard J.; Meigs, Andrew D.; Franklin, Abraham J.; Sears, Robert D.; Robison, Mark W.; Rafert, J. Bruce; Fronterhouse, Donald C.; Grotbeck, Ronald L.

    1999-10-01

    Previous papers have described the concept behind the MightySat II.1 program, the satellite's Fourier Transform imaging spectrometer's optical design, the design for the spectral imaging payload, and its initial qualification testing. This paper discusses the on board data processing designed to reduce the amount of downloaded data by an order of magnitude and provide a demonstration of a smart spaceborne spectral imaging sensor. Two custom components, a spectral imager interface 6U VME card that moves data at over 30 MByte/sec, and four TI C-40 processors mounted to a second 6U VME and daughter card, are used to adapt the sensor to the spacecraft and provide the necessary high speed processing. A system architecture that offers both on board real time image processing and high-speed post data collection analysis of the spectral data has been developed. In addition to the on board processing of the raw data into a usable spectral data volume, one feature extraction technique has been incorporated. This algorithm operates on the basic interferometric data. The algorithm is integrated within the data compression process to search for uploadable feature descriptions.

  16. Intelligent robotic tracker

    Science.gov (United States)

    Otaguro, W. S.; Kesler, L. O.; Land, K. C.; Rhoades, D. E.

    1987-01-01

    An intelligent tracker capable of robotic applications requiring guidance and control of platforms, robotic arms, and end effectors has been developed. This packaged system capable of supervised autonomous robotic functions is partitioned into a multiple processor/parallel processing configuration. The system currently interfaces to cameras but has the capability to also use three-dimensional inputs from scanning laser rangers. The inputs are fed into an image processing and tracking section where the camera inputs are conditioned for the multiple tracker algorithms. An executive section monitors the image processing and tracker outputs and performs all the control and decision processes. The present architecture of the system is presented with discussion of its evolutionary growth for space applications. An autonomous rendezvous demonstration of this system was performed last year. More realistic demonstrations in planning are discussed.

  17. A data base processor semantics specification package

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

  18. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  19. Intelligence Naturelle et Intelligence Artificielle

    OpenAIRE

    Dubois, Daniel

    2011-01-01

    Cet article présente une approche systémique du concept d’intelligence naturelle en ayant pour objectif de créer une intelligence artificielle. Ainsi, l’intelligence naturelle, humaine et animale non-humaine, est une fonction composée de facultés permettant de connaître et de comprendre. De plus, l'intelligence naturelle reste indissociable de la structure, à savoir les organes du cerveau et du corps. La tentation est grande de doter les systèmes informatiques d’une intelligence artificielle ...

  20. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  1. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  2. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

    1995-01-01

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  3. Highway traffic simulation on multi-processor computers

    Energy Technology Data Exchange (ETDEWEB)

    Hanebutte, U.R.; Doss, E.; Tentner, A.M.

    1997-04-01

    A computer model has been developed to simulate highway traffic for various degrees of automation with a high level of fidelity in regard to driver control and vehicle characteristics. The model simulates vehicle maneuvering in a multi-lane highway traffic system and allows for the use of Intelligent Transportation System (ITS) technologies such as an Automated Intelligent Cruise Control (AICC). The structure of the computer model facilitates the use of parallel computers for the highway traffic simulation, since domain decomposition techniques can be applied in a straight forward fashion. In this model, the highway system (i.e. a network of road links) is divided into multiple regions; each region is controlled by a separate link manager residing on an individual processor. A graphical user interface augments the computer model kv allowing for real-time interactive simulation control and interaction with each individual vehicle and road side infrastructure element on each link. Average speed and traffic volume data is collected at user-specified loop detector locations. Further, as a measure of safety the so- called Time To Collision (TTC) parameter is being recorded.

  4. Accuracy Limitations in Optical Linear Algebra Processors

    Science.gov (United States)

    Batsell, Stephen Gordon

    1990-01-01

    One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

  5. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

  6. ZD-I intelligent scaler

    International Nuclear Information System (INIS)

    Zhen Zhihao; Zhou Weimin

    1999-01-01

    The ZD-I Intelligent Scaler is a new kind of high-powered scaler using high-speed CMOS96 series single chip processor. Besides the normal timing and counting functions, it can also supply 0-2000 V high voltage, store or print measuring data, communicate with PC by RS232 interface, and transfer measuring data. There is essential improvements on the panel. Keyboard without dialing switches and rheostats can perform all the operations, and the setting parameters would not lose when the scaler is switched off. So the ZD-I Intelligent Scaler is a perfect up-to-date production of the NIM-style scaler and the HV-generator

  7. Intelligent Buildings and pervasive computing

    DEFF Research Database (Denmark)

    Grønbæk, Kaj; Kyng, Morten; Krogh, Peter Gall

    2001-01-01

    computers are everywhere, for everyone, at all times. Where IT becomes a still more integrated part of our environments with processors, sensors, and actuators connected via high-speed networks and combined with new visualiza-tion devices ranging from projections directly in the eye to large panorama......Intelligent Buildings have been the subject of research and commercial interest for more than two decades. The different perspectives range from monitoring and controlling energy consumption over interactive rooms supporting work in offices and leisure in the home, to buildings providing...... information to by-passers in plazas and urban environments. This paper puts forward the hypothesis that the coming decade will witness a dramatic increase in both quality and quantity of intelligent buildings due to the emerging field of pervasive computing: the next generation computing environments where...

  8. ZD-I intelligent scaler

    International Nuclear Information System (INIS)

    Chen Zhihao

    2001-01-01

    The ZD-I Intelligent Scaler is a new kind of high-powered scaler using high-speed CMOS96 series single chip processor. It not only has the normal timing, counting functions, but also can supply 0-2000 V high voltage, storage or print measuring data, communicate with PC by RS232 interface, transfer measuring data. And there is essentially improvement on the panel. Keyboard without dialing switches and rheostats can perform all the operations, and the setting parameters wouldn't lose when you shut down the scaler. So the ZE-I Intelligent Scaler is a perfect updating production of the NIM-style scaler and the HV-generator

  9. ATLAS TDAQ application gateway upgrade during LS1

    CERN Document Server

    KOROL, A; The ATLAS collaboration; BOGDANCHIKOV, A; BRASOLIN, F; CONTESCU, A C; DUBROV, S; HAFEEZ, M; LEE, C J; SCANNICCHIO, D A; TWOMEY, M; VORONKOV, A; ZAYTSEV, A

    2014-01-01

    The ATLAS Gateway service is implemented with a set of dedicated computer nodes to provide a fine-grained access control between CERN General Public Network (GPN) and ATLAS Technical Control Network (ATCN). ATCN connects the ATLAS online farm used for ATLAS Operations and data taking, including the ATLAS TDAQ (Trigger and Data Aquisition) and DCS (Detector Control System) nodes. In particular, it provides restricted access to the web services (proxy), general login sessions (via SSH and RDP protocols), NAT and mail relay from ATCN. At the Operating System level the implementation is based on virtualization technologies. Here we report on the Gateway upgrade during Long Shutdown 1 (LS1) period: it includes the transition to the last production release of the CERN Linux distribution (SLC6), the migration to the centralized configuration management system (based on Puppet) and the redesign of the internal system architecture.

  10. Efficient preparation of shuffled DNA libraries through recombination (Gateway) cloning.

    Science.gov (United States)

    Lehtonen, Soili I; Taskinen, Barbara; Ojala, Elina; Kukkurainen, Sampo; Rahikainen, Rolle; Riihimäki, Tiina A; Laitinen, Olli H; Kulomaa, Markku S; Hytönen, Vesa P

    2015-01-01

    Efficient and robust subcloning is essential for the construction of high-diversity DNA libraries in the field of directed evolution. We have developed a more efficient method for the subcloning of DNA-shuffled libraries by employing recombination cloning (Gateway). The Gateway cloning procedure was performed directly after the gene reassembly reaction, without additional purification and amplification steps, thus simplifying the conventional DNA shuffling protocols. Recombination-based cloning, directly from the heterologous reassembly reaction, conserved the high quality of the library and reduced the time required for the library construction. The described method is generally compatible for the construction of DNA-shuffled gene libraries. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

  11. Artificial Intelligence.

    Science.gov (United States)

    Wash, Darrel Patrick

    1989-01-01

    Making a machine seem intelligent is not easy. As a consequence, demand has been rising for computer professionals skilled in artificial intelligence and is likely to continue to go up. These workers develop expert systems and solve the mysteries of machine vision, natural language processing, and neural networks. (Editor)

  12. Intelligent Design

    DEFF Research Database (Denmark)

    Hjorth, Poul G.

    2005-01-01

    Forestillingen om at naturen er designet af en guddommelig 'intelligens' er et smukt filosofisk princip. Teorier om Intelligent Design som en naturvidenskabeligt baseret teori er derimod helt forfærdelig.......Forestillingen om at naturen er designet af en guddommelig 'intelligens' er et smukt filosofisk princip. Teorier om Intelligent Design som en naturvidenskabeligt baseret teori er derimod helt forfærdelig....

  13. Architectural design and analysis of a programmable image processor

    International Nuclear Information System (INIS)

    Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

    2003-01-01

    In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

  14. Virtual Experiments on the Neutron Science TeraGrid Gateway

    International Nuclear Information System (INIS)

    Lynch, Vickie E; Cobb, John W; Farhi, Emmanuel N; Miller, Stephen D; Taylor, M

    2008-01-01

    The TeraGrid's outreach effort to the neutron science community is creating an environment that is encouraging the exploration of advanced cyberinfrastructure being incorporated into facility operations in a way that leverages facility operations to multiply the scientific output of its users, including many NSF supported scientists in many disciplines. The Neutron Science TeraGrid Gateway serves as an exploratory incubator for several TeraGrid projects. Virtual neutron scattering experiments from one exploratory project will be highlighted

  15. Europe in global maritime flows: Gateways, forelands, and subnetworks

    OpenAIRE

    Ducruet , César; Joly , Olivier; Le Cam , Marine

    2014-01-01

    The position of Europe in maritime flows is demonstrated by the connections of its port gateways with the rest of the world. Such connections vary from one port to another in terms of traffic concentration and geographic coverage, dependent on multiple factors including origin-destination time and cost factors, shipper and ocean carrier decisions, and the size, quality, and specialization of local port infrastructures. A key research challenge is therefore to unravel the relationships between...

  16. Eocene cooling linked to early flow across the Tasmanian Gateway.

    Science.gov (United States)

    Bijl, Peter K; Bendle, James A P; Bohaty, Steven M; Pross, Jörg; Schouten, Stefan; Tauxe, Lisa; Stickley, Catherine E; McKay, Robert M; Röhl, Ursula; Olney, Matthew; Sluijs, Appy; Escutia, Carlota; Brinkhuis, Henk

    2013-06-11

    The warmest global temperatures of the past 85 million years occurred during a prolonged greenhouse episode known as the Early Eocene Climatic Optimum (52-50 Ma). The Early Eocene Climatic Optimum terminated with a long-term cooling trend that culminated in continental-scale glaciation of Antarctica from 34 Ma onward. Whereas early studies attributed the Eocene transition from greenhouse to icehouse climates to the tectonic opening of Southern Ocean gateways, more recent investigations invoked a dominant role of declining atmospheric greenhouse gas concentrations (e.g., CO2). However, the scarcity of field data has prevented empirical evaluation of these hypotheses. We present marine microfossil and organic geochemical records spanning the early-to-middle Eocene transition from the Wilkes Land Margin, East Antarctica. Dinoflagellate biogeography and sea surface temperature paleothermometry reveal that the earliest throughflow of a westbound Antarctic Counter Current began ~49-50 Ma through a southern opening of the Tasmanian Gateway. This early opening occurs in conjunction with the simultaneous onset of regional surface water and continental cooling (2-4 °C), evidenced by biomarker- and pollen-based paleothermometry. We interpret that the westbound flowing current flow across the Tasmanian Gateway resulted in cooling of Antarctic surface waters and coasts, which was conveyed to global intermediate waters through invigorated deep convection in southern high latitudes. Although atmospheric CO2 forcing alone would provide a more uniform middle Eocene cooling, the opening of the Tasmanian Gateway better explains Southern Ocean surface water and global deep ocean cooling in the apparent absence of (sub-) equatorial cooling.

  17. Expansion of the gateway multisite recombination cloning toolkit.

    Science.gov (United States)

    Shearin, Harold K; Dvarishkis, Alisa R; Kozeluh, Craig D; Stowers, R Steven

    2013-01-01

    Precise manipulation of transgene expression in genetic model organisms has led to advances in understanding fundamental mechanisms of development, physiology, and genetic disease. Transgene construction is, however, a precondition of transgene expression, and often limits the rate of experimental progress. Here we report an expansion of the modular Gateway MultiSite recombination-cloning platform for high efficiency transgene assembly. The expansion includes two additional destination vectors and entry clones for the LexA binary transcription system, among others. These new tools enhance the expression levels possible with Gateway MultiSite generated transgenes and make possible the generation of LexA drivers and reporters with Gateway MultiSite cloning. In vivo data from transgenic Drosophila functionally validating each novel component are presented and include neuronal LexA drivers, LexAop2 red and green fluorescent synaptic vesicle reporters, TDC2 and TRH LexA, GAL4, and QF drivers, and LexAop2, UAS, and QUAS channelrhodopsin2 T159C reporters.

  18. Design of a multimedia gateway for mobile devices

    Science.gov (United States)

    Hens, Raf; Goeminne, Nico; Van Hoecke, Sofie; Verdickt, Tom; Bouve, Thomas; Gielen, Frank; Demeester, Piet

    2005-03-01

    Although mobile users are currently offered a lot more capabilities on their mobile devices, they still experience some limitations. They can surf the Internet, read their e-mail and receive MMS messages, but they have limited processing power, storage capacity and bandwidth and are limited in their access to peripherals (e.g. printers). We have designed and implemented a multimedia gateway for mobile devices that reduces these limitations. It gives the mobile devices transparent access to high capacity devices connected to the gateway, which is built around a central, modularly extensible server that can run on any PC or home gateway. It manages two sets of modules: one set offering the actual services and another set handling the IP-based wireless interaction with the client applications on the mobile devices. These modules can be added and removed dynamically, offering new services on the fly. Currently services for storage, printing, domotics and playing music are provided. Others can easily be added later on. This paper discusses the architecture and development, the management of modules, the actual services and their benefits. Besides a proprietary implementation, it also looks into OSGi and how both platforms compare to each other, concerning design, architecture, ease of development, functionality, ...

  19. Syllabic compression and speech intelligibility in hearing impaired listeners

    NARCIS (Netherlands)

    Verschuure, J.; Dreschler, W. A.; de Haan, E. H.; van Cappellen, M.; Hammerschlag, R.; Maré, M. J.; Maas, A. J.; Hijmans, A. C.

    1993-01-01

    Syllabic compression has not been shown unequivocally to improve speech intelligibility in hearing-impaired listeners. This paper attempts to explain the poor results by introducing the concept of minimum overshoots. The concept was tested with a digital signal processor on hearing-impaired

  20. The use and effectiveness of the eLib subject gateways: a preliminary investigation

    OpenAIRE

    Mackie, M.; Burton, P.F.

    1999-01-01

    Internet subject gateways were set up under the Electronic Libraries Programme (eLib) in order to address some of the problems of searching the Internet which have been identified by information professionals, i.e. locating relevant, good quality information. This preliminary study examines the extent to which academics in two universities use three eLib subject gateways (EEVL, OMNI and SOSIG). The results are generally encouraging for the eLib programme, but it is necessary for the gateways ...

  1. A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

    OpenAIRE

    Guan, Kai; Shao, Minggang; Wu, Shuicai

    2017-01-01

    This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) ...

  2. An I/O subnet for the APS control system - The BITBUS Universal Gateway

    International Nuclear Information System (INIS)

    Nawrocki, G.J.; Arnold, N.D.; Hoffberg, M.G.; Winans, J.R.; Benes, S.J.

    1993-01-01

    The Advanced Photon Source (APS) control system is based on a distributed topology of microprocessor-based Input/Output Controllers (IOCs). Since the cost effectiveness of placing an IOC near every point where an interface to the control system is required may be prohibitive, I/O subnets implemented via message passing network protocols are utilized. For greatest flexibility, such a subnet must support connections to equipment via discrete I/O points, connections to standard interfaces such as GPIB and RS232, and be a practical network for custom-designed interfaces to intelligent equipment. This paper describes the BITBUS Universal Gateway (BUG), a device which supports the different interfaces mentioned above with a connection to a single BITBUS distributed subnet. The BUG utilizes an interchangeable set of circuit boards, which allow for a commonality among interface points, and the ability to use commercially-available modules for I/O. This approach also circumvents several limitations of GPIB and RS232, which restrict their use in industrial, electrically harsh environments, via an implementation of the BITBUS protocol over optical fibers

  3. The Neutron Science TeraGrid Gateway, a TeraGrid Science Gateway to Support the Spallation Neutron Source

    International Nuclear Information System (INIS)

    Cobb, John W.; Geist, Al; Kohl, James Arthur; Miller, Stephen D; Peterson, Peter F.; Pike, Gregory; Reuter, Michael A; Swain, William; Vazhkudai, Sudharshan S.; Vijayakumar, Nithya N.

    2006-01-01

    The National Science Foundation's (NSF's) Extensible Terascale Facility (ETF), or TeraGrid (1) is entering its operational phase. An ETF science gateway effort is the Neutron Science TeraGrid Gateway (NSTG.) The Oak Ridge National Laboratory (ORNL) resource provider effort (ORNL-RP) during construction and now in operations is bridging a large scale experimental community and the TeraGrid as a large-scale national cyberinfrastructure. Of particular emphasis is collaboration with the Spallation Neutron Source (SNS) at ORNL. The U.S. Department of Energy's (DOE's) SNS (2) at ORNL will be commissioned in spring of 2006 as the world's brightest source of neutrons. Neutron science users can run experiments, generate datasets, perform data reduction, analysis, visualize results; collaborate with remotes users; and archive long term data in repositories with curation services. The ORNL-RP and the SNS data analysis group have spent 18 months developing and exploring user requirements, including the creation of prototypical services such as facility portal, data, and application execution services. We describe results from these efforts and discuss implications for science gateway creation. Finally, we show incorporation into implementation planning for the NSTG and SNS architectures. The plan is for a primarily portal-based user interaction supported by a service oriented architecture for functional implementation

  4. Multi-Gateway-Based Energy Holes Avoidance Routing Protocol for WSN

    Directory of Open Access Journals (Sweden)

    Rohini Sharma

    2016-04-01

    Full Text Available In wireless sensor networks (WSNs, efficient energy conservation is required to prolong the lifetime of the network. In this work, we have given emphasis on balanced energy consumption and energy holes avoidance. This paper proposes a multi-gateway-based approach to reduce the transmission distance between the sender and the sink node. The area to be monitored is divided into regions and gateway nodes are deployed at optimal positions. We have designed a transmission scheme, in which sensors in the sink region communicate directly to the sink, sensors in the gateway region communicate directly to the gateway, and sensors in the cluster region transmit their data directly to their respective cluster head which transmits data to the gateway in its region. If the distance between a cluster head and the sink is less than the distance between the cluster head and the gateway node, the cluster head transmits data to the sink instead of the gateway node. We have compared the proposed protocol with Low-Energy Adaptive Clustering Hierarchy (LEACH, Gateway Based Energy Aware Multi-Hop Routing (M-GEAR, and Gateway Based Stable Election Protocol (GSEP protocols. The protocol performs better than other protocols in terms of throughput, stability period, lifetime, residual energy, and the packet transmitted to the sink.

  5. A Planetary Defense Gateway for Smart Discovery of relevant Information for Decision Support

    Science.gov (United States)

    Bambacus, Myra; Yang, Chaowei Phil; Leung, Ronald Y.; Barbee, Brent; Nuth, Joseph A.; Seery, Bernard; Jiang, Yongyao; Qin, Han; Li, Yun; Yu, Manzhu; hide

    2017-01-01

    A Planetary Defense Gateway for Smart Discovery of relevant Information for Decision Support presentation discussing background, framework architecture, current results, ongoing research, conclusions.

  6. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  7. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-02-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  8. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

  9. Embedded processor extensions for image processing

    Science.gov (United States)

    Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

    2008-04-01

    The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

  10. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Baird, S.A.; Biddulph, P.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  11. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  12. Intelligent playgrounds

    DEFF Research Database (Denmark)

    Larsen, Lasse Juel

    2009-01-01

    This paper examines play, gaming and learning in regard to intelligent playware developed for outdoor use. The key questions are how does these novel artefacts influence the concept of play, gaming and learning. Up until now play and game have been understood as different activities. This paper...... examines if the sharp differentiation between the two can be uphold in regard to intelligent playware for outdoor use. Play and game activities will be analysed and viewed in conjunction with learning contexts. This paper will stipulate that intelligent playware facilitates rapid shifts in contexts...

  13. Artificial intelligence

    CERN Document Server

    Ennals, J R

    1987-01-01

    Artificial Intelligence: State of the Art Report is a two-part report consisting of the invited papers and the analysis. The editor first gives an introduction to the invited papers before presenting each paper and the analysis, and then concludes with the list of references related to the study. The invited papers explore the various aspects of artificial intelligence. The analysis part assesses the major advances in artificial intelligence and provides a balanced analysis of the state of the art in this field. The Bibliography compiles the most important published material on the subject of

  14. Artificial Intelligence

    CERN Document Server

    Warwick, Kevin

    2011-01-01

    if AI is outside your field, or you know something of the subject and would like to know more then Artificial Intelligence: The Basics is a brilliant primer.' - Nick Smith, Engineering and Technology Magazine November 2011 Artificial Intelligence: The Basics is a concise and cutting-edge introduction to the fast moving world of AI. The author Kevin Warwick, a pioneer in the field, examines issues of what it means to be man or machine and looks at advances in robotics which have blurred the boundaries. Topics covered include: how intelligence can be defined whether machines can 'think' sensory

  15. Commodity multi-processor systems in the ATLAS level-2 trigger

    International Nuclear Information System (INIS)

    Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

    2000-01-01

    Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

  16. Commodity multi-processor systems in the ATLAS level-2 trigger

    CERN Document Server

    Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

    2000-01-01

    Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

  17. Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

    Science.gov (United States)

    Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

    2007-04-01

    In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

  18. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  19. Parallel processor for fast event analysis

    International Nuclear Information System (INIS)

    Hensley, D.C.

    1983-01-01

    Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

  20. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  1. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  2. Simulation of a parallel processor on a serial processor: The neutron diffusion equation

    International Nuclear Information System (INIS)

    Honeck, H.C.

    1981-01-01

    Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

  3. Intelligent Advertising

    OpenAIRE

    Díaz Pinedo, Edilfredo Eliot

    2012-01-01

    Intelligent Advertisement diseña e implementa un sistema de publicidad para dispositivos móviles en un centro comercial, donde los clientes reciben publicidad de forma pasiva en sus dispositivos mientras están dentro.

  4. Special purpose processors for high energy physics applications

    International Nuclear Information System (INIS)

    Verkerk, C.

    1978-01-01

    The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

  5. BUSINESS INTELLIGENCE

    OpenAIRE

    Bogdan Mohor Dumitrita

    2011-01-01

    The purpose of this work is to present business intelligence systems. These systems can be extremely complex and important in modern market competition. Its effectiveness also reflects in price, so we have to exlore their financial potential before investment. The systems have 20 years long history and during that time many of such tools have been developed, but they are rarely still in use. Business intelligence system consists of three main areas: Data Warehouse, ETL tools and tools f...

  6. Intelligent indexing

    International Nuclear Information System (INIS)

    Farkas, J.

    1992-01-01

    In this paper we discuss the relevance of artificial intelligence to the automatic indexing of natural language text. We describe the use of domain-specific semantically-based thesauruses and address the problem of creating adequate knowledge bases for intelligent indexing systems. We also discuss the relevance of the Hilbert space ι 2 to the compact representation of documents and to the definition of the similarity of natural language texts. (author). 17 refs., 2 figs

  7. Intelligent indexing

    Energy Technology Data Exchange (ETDEWEB)

    Farkas, J

    1993-12-31

    In this paper we discuss the relevance of artificial intelligence to the automatic indexing of natural language text. We describe the use of domain-specific semantically-based thesauruses and address the problem of creating adequate knowledge bases for intelligent indexing systems. We also discuss the relevance of the Hilbert space {iota}{sup 2} to the compact representation of documents and to the definition of the similarity of natural language texts. (author). 17 refs., 2 figs.

  8. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  9. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

  10. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

  11. Beeldverwerking met de Micron Automatic Processor

    OpenAIRE

    Goyens, Frank

    2017-01-01

    Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

  12. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

  13. Simplifying cochlear implant speech processor fitting

    NARCIS (Netherlands)

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

  14. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    This book presents the papers given at a conference which reviewed the new developments in parallel and vector processing. Topics considered at the conference included hardware (array processors, supercomputers), programming languages, software aids, numerical methods (e.g., Monte Carlo algorithms, iterative methods, finite elements, optimization), and applications (e.g., neutron transport theory, meteorology, image processing)

  15. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  16. Interleaved Subtask Scheduling on Multi Processor SOC

    NARCIS (Netherlands)

    Zhe, M.

    2006-01-01

    The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

  17. User manual Dieka PreProcessor

    NARCIS (Netherlands)

    Valkering, Kasper

    2000-01-01

    This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

  18. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  19. Event analysis using a massively parallel processor

    International Nuclear Information System (INIS)

    Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.

    1990-01-01

    This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable

  20. Gateway to the Syriac Saints: A Database Project

    Directory of Open Access Journals (Sweden)

    Jeanne-Nicole Mellon Saint-Laurent

    2016-04-01

    Full Text Available This article describes The Gateway to the Syriac Saints, a database project developed by the Syriac Reference Portal (www.syriaca.org. It is a research tool for the study of Syriac saints and hagiographic texts. The Gateway to the Syriac Saints is a two-volume database: 1 Qadishe and 2 Bibliotheca Hagiographica Syriaca Electronica (BHSE. Hagiography, the lives of the saints, is a multiform genre. It contains elements of myth, history, biblical exegesis, romance, and theology. The production of saints’ lives blossomed in late antiquity alongside the growth of the cult of the saints. Scholars have attended to hagiographic traditions in Greek and Latin, but many scholars have yet to discover the richness of Syriac hagiographic literature: the stories, homilies, and hymns on the saints that Christians of the Middle East told and preserved. It is our hope that our database will give scholars and students increased access to these traditions to generate new scholarship. The first volume, Qadishe or “saints” in Syriac, is a digital catalogue of saints or holy persons venerated in the Syriac tradition. Some saints are native to the Syriac-speaking milieu, whereas others come from other linguistic or cultural traditions. Through the translation of their hagiographies and the diffusion of saints’ cults in the late antique world, saints were adopted, “imported,” and appropriated into Syriac religious memory. The second volume, the BHSE, focuses on Syriac hagiographic texts. The BHSE contains the titles of over 1000 Syriac stories, hymns, and homilies on saints. It also includes authors’ or hagiographers’ names, the first and last lines of the texts (in Syriac, English, and French, bibliographic information, and the names of the manuscripts containing these hagiographic works. We have also listed modern and ancient translations of these works. All of the data in the Gateway to the Syriac Saints has been encoded in TEI, and it is fully

  1. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  2. Lyceum: A Multi-Protocol Digital Library Gateway

    Science.gov (United States)

    Maa, Ming-Hokng; Nelson, Michael L.; Esler, Sandra L.

    1997-01-01

    Lyceum is a prototype scalable query gateway that provides a logically central interface to multi-protocol and physically distributed, digital libraries of scientific and technical information. Lyceum processes queries to multiple syntactically distinct search engines used by various distributed information servers from a single logically central interface without modification of the remote search engines. A working prototype (http://www.larc.nasa.gov/lyceum/) demonstrates the capabilities, potentials, and advantages of this type of meta-search engine by providing access to over 50 servers covering over 20 disciplines.

  3. Time Dependent Hartree Fock Equation: Gateway to Nonequilibrium Plasmas

    International Nuclear Information System (INIS)

    Dufty, James W.

    2007-01-01

    This is the Final Technical Report for DE-FG02-2ER54677 award 'Time Dependent Hartree Fock Equation - Gateway to Nonequilibrium Plasmas'. Research has focused on the nonequilibrium dynamics of electrons in the presence of ions, both via basic quantum theory and via semi-classical molecular dynamics (MD) simulation. In addition, fundamental notions of dissipative dynamics have been explored for models of grains and dust, and for scalar fields (temperature) in turbulent edge plasmas. The specific topics addressed were Quantum Kinetic Theory for Metallic Clusters, Semi-classical MD Simulation of Plasmas , and Effects of Dissipative Dynamics.

  4. The MIM web gateway to IP multicast e-meetings

    Science.gov (United States)

    Parviainen, Roland; Parnes, Peter

    2003-12-01

    As video conferencing and e-meeting systems are used more and more on the Internet and in businesses it becomes increasingly important to be able to participate from any computer at any location. Often this is impossible, since these systems requires often special software that are not available everywhere or impossible to install for administrative reasons. Many locations also lack the necessary network infrastructure such as IP multicast. This paper presents a WWW gateway system that enables users to participate using only a standard web browser. The design and architecture of the system are described and performance tests that show the scalability of the system are also presented.

  5. European Film Gateway projekt EFG1914 / Ivi Tomingas

    Index Scriptorium Estoniae

    Tomingas, Ivi

    2015-01-01

    Saja aasta möödumise puhul Esimesest maailmasõjast kutsus Euroopa Komisjon ellu European Film Gateway projekti EFG 1914. Avalikkusele on nüüd kättesaadav 660 tundi digiteeritud filme ja 5500 plakatit, fotot ja dokumenti. Nendega saab tutvuda aadressidel http://project.efg1914.eu ja http://www.europeanfilmgateway.eu/content/efg1914-project. Rahvusarhiivist on portaali lisatud kaks tundi Johannes Pääsukese ülesvõetud etnograafilist materjali, Pathé ringvaade nr. 17 (sõjategevus 1917) ja Theodor Lutsu film "Noored kotkad" (1927) ning Karl Akeli ja Johann Ostrati fotosid

  6. RANCANGAN PROTOTYPE ALAT PEMANTAU JUMLAH PENGUNJUNG MINIMARKET BERBASIS SMS GATEWAY

    Directory of Open Access Journals (Sweden)

    Suleman Suleman

    2016-03-01

    Full Text Available Abstract - Has designed and implemented the monitoring system, the number of visitors to the minimart based sms gateway using microcontroller ATMega8. If the first minimarket (glass was opened, then automatically limit switch 1 on the first door is depressed, so that would indicate to the microcontroller to give orders to the wavecom modem convert to the owner. The second condition, namely if the minimarket is closed then automatically limit switch 2 is depressed, it will then indicate to the microcontroller to give orders to the wavecom modem for sending sms to the owner. The design of this system using the method of architecture that consists of several stages, namely, (1 analysis of needs, (2, (3 design, Implementation arrangements, Testing tools (4, (5 test procedure and (6 Making Tools. The hardware consists of a limit switch, infrared, ATMega8 microcontroller as a minimum system controller circuit controller inputs and outputs, the output display circuit using IC MAX 232 wavecom modem that is linked to. The software is written with BASCOM-AVR Keyword : Design Of Prototype Tools Monitor The Number Of Visitors To The Minimarket, SMS Gateway Abstrak - Telah dirancang dan implementasikan sistem pemantau jumlah pengunjung minimarket berbasis sms gateway menggunakan mikrokontroler ATMega8. Jika pintu minimarket pertama (kaca dibuka, maka secara otomatis limit switch 1 yang terdapat pada pintu pertama tertekan, sehingga akan mengindikasikan kepada mikrokontroler untuk memberikan perintah kepada modem wavecom untuk menggirimkan sms kepada owner. Keadaan kedua yaitu jika pintu minimarket ditutup maka secara otomatis limit switch 2 tertekan, kemudian akan mengindikasikan kepada mikrokontroler untuk memberikan perintah kepada modem wavecom untuk mengirimkan sms kepada owner. Perancangan sistem ini menggunakan metode rancang bangun yang terdiri beberapa tahap yaitu, (1 Analisis kebutuhan, (2 Perancangan, (3 Implementasi rangkaian, (4 Pengujian alat

  7. Construction of gateway-compatible yeast two-hybrid vectors for ...

    African Journals Online (AJOL)

    Yeast two-hybrid system combined with the gateway technology will greatly facilitate the cloning of interested DNA fragment into yeast two-hybrid vectors and therefore increase the efficiency of yeast two-hybrid analysis. In this study, we constructed a pair of Gateway-compatible yeast two-hybrid vectors pBTM116GW and ...

  8. Construction of gateway-compatible yeast two-hybrid vectors for ...

    African Journals Online (AJOL)

    USER

    2010-03-01

    Mar 1, 2010 ... vectors pBTM116GW and pVP16GW by introducing the gateway cassette ... Key words: Yeast two-hybrid, gateway cloning technology, protein interaction. .... cycling parameters were as follows: an initial denaturation step at.

  9. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

    1983-01-01

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  10. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  11. The Gateway Reflex, a Novel Neuro-Immune Interaction for the Regulation of Regional Vessels

    Directory of Open Access Journals (Sweden)

    Yuki Tanaka

    2017-10-01

    Full Text Available The gateway reflex is a new phenomenon that explains how immune cells bypass the blood–brain barrier to infiltrate the central nervous system (CNS and trigger neuroinflammation. To date, four examples of gateway reflexes have been discovered, each described by the stimulus that evokes the reflex. Gravity, electricity, pain, and stress have all been found to create gateways at specific regions of the CNS. The gateway reflex, the most recently discovered of the four, has also been shown to upset the homeostasis of organs in the periphery through its action on the CNS. These reflexes provide novel therapeutic targets for the control of local neuroinflammation and organ function. Each gateway reflex is activated by different neural activations and induces inflmammation at different regions in the CNS. Therefore, it is theoretically possible to manipulate each independently, providing a novel therapeutic strategy to control local neuroinflammation and peripheral organ homeostasis.

  12. Design of intelligent gateway control system based on AllJoyn and FC-3180

    Directory of Open Access Journals (Sweden)

    Chen Yanzhong

    2017-02-01

    Full Text Available To simplify interconnection of distributed household equipment,this design creates a spontaneous,movable,safe and configurable equipment management system and smart home layout with the open-source software framework AllJoyn,the embedded microprocessor FC-3180,the low power wireless transmission network ZigBee and mobile application platform Android.

  13. The ’TIS’ Intelligent Gateway Computer: An Alternative to the ’Doomsday Scenario’,

    Science.gov (United States)

    1983-02-01

    century. The traditional intermediary, the librarian, or information specialist, will have joined the fate of dinosaurs by that time, Lewis said, unless...others in similar work environments, (Refs. 2-5) also by Lewis who offers it as a partial alternative to the extinction of the traditional information...1979 1960 1981 1982 Year The underlying reasons probably are that major end users at LLNL: 1) Don’t have the time to bother with routine searching- 2

  14. Lipsi: Probably the Smallest Processor in the World

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

  15. A Wireless and Batteryless Intelligent Carbon Monoxide Sensor.

    Science.gov (United States)

    Chen, Chen-Chia; Sung, Gang-Neng; Chen, Wen-Ching; Kuo, Chih-Ting; Chue, Jin-Ju; Wu, Chieh-Ming; Huang, Chun-Ming

    2016-09-23

    Carbon monoxide (CO) poisoning from natural gas water heaters is a common household accident in Taiwan. We propose a wireless and batteryless intelligent CO sensor for improving the safety of operating natural gas water heaters. A micro-hydropower generator supplies power to a CO sensor without battery (COSWOB) (2.5 W at a flow rate of 4.2 L/min), and the power consumption of the COSWOB is only ~13 mW. The COSWOB monitors the CO concentration in ambient conditions around natural gas water heaters and transmits it to an intelligent gateway. When the CO level reaches a dangerous level, the COSWOB alarm sounds loudly. Meanwhile, the intelligent gateway also sends a trigger to activate Wi-Fi alarms and sends notifications to the mobile device through the Internet. Our strategy can warn people indoors and outdoors, thereby reducing CO poisoning accidents. We also believe that our technique not only can be used for home security but also can be used in industrial applications (for example, to monitor leak occurrence in a pipeline).

  16. Intelligent systems

    CERN Document Server

    Irwin, J David

    2011-01-01

    Technology has now progressed to the point that intelligent systems are replacing humans in the decision making processes as well as aiding in the solution of very complex problems. In many cases intelligent systems are already outperforming human activities. Artificial neural networks are not only capable of learning how to classify patterns, such images or sequence of events, but they can also effectively model complex nonlinear systems. Their ability to classify sequences of events is probably more popular in industrial applications where there is an inherent need to model nonlinear system

  17. Intelligent Universe

    Energy Technology Data Exchange (ETDEWEB)

    Hoyle, F

    1983-01-01

    The subject is covered in chapters, entitled: chance and the universe (synthesis of proteins; the primordial soup); the gospel according to Darwin (discussion of Darwin theory of evolution); life did not originate on earth (fossils from space; life in space); the interstellar connection (living dust between the stars; bacteria in space falling to the earth; interplanetary dust); evolution by cosmic control (microorganisms; genetics); why aren't the others here (a cosmic origin of life); after the big bang (big bang and steady state); the information rich universe; what is intelligence up to; the intelligent universe.

  18. Artificial intelligence

    International Nuclear Information System (INIS)

    Perret-Galix, D.

    1992-01-01

    A vivid example of the growing need for frontier physics experiments to make use of frontier technology is in the field of artificial intelligence and related themes. This was reflected in the second international workshop on 'Software Engineering, Artificial Intelligence and Expert Systems in High Energy and Nuclear Physics' which took place from 13-18 January at France Telecom's Agelonde site at La Londe des Maures, Provence. It was the second in a series, the first having been held at Lyon in 1990

  19. Artificial Intelligence and Moral intelligence

    Directory of Open Access Journals (Sweden)

    Laura Pana

    2008-07-01

    Full Text Available We discuss the thesis that the implementation of a moral code in the behaviour of artificial intelligent systems needs a specific form of human and artificial intelligence, not just an abstract intelligence. We present intelligence as a system with an internal structure and the structural levels of the moral system, as well as certain characteristics of artificial intelligent agents which can/must be treated as 1- individual entities (with a complex, specialized, autonomous or selfdetermined, even unpredictable conduct, 2- entities endowed with diverse or even multiple intelligence forms, like moral intelligence, 3- open and, even, free-conduct performing systems (with specific, flexible and heuristic mechanisms and procedures of decision, 4 – systems which are open to education, not just to instruction, 5- entities with “lifegraphy”, not just “stategraphy”, 6- equipped not just with automatisms but with beliefs (cognitive and affective complexes, 7- capable even of reflection (“moral life” is a form of spiritual, not just of conscious activity, 8 – elements/members of some real (corporal or virtual community, 9 – cultural beings: free conduct gives cultural value to the action of a ”natural” or artificial being. Implementation of such characteristics does not necessarily suppose efforts to design, construct and educate machines like human beings. The human moral code is irremediably imperfect: it is a morality of preference, of accountability (not of responsibility and a morality of non-liberty, which cannot be remedied by the invention of ethical systems, by the circulation of ideal values and by ethical (even computing education. But such an imperfect morality needs perfect instruments for its implementation: applications of special logic fields; efficient psychological (theoretical and technical attainments to endow the machine not just with intelligence, but with conscience and even spirit; comprehensive technical

  20. Bulk-memory processor for data acquisition

    International Nuclear Information System (INIS)

    Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

    1981-01-01

    To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

  1. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  2. Real time processor for array speckle interferometry

    International Nuclear Information System (INIS)

    Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

    1989-01-01

    With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

  3. Parallel processor programs in the Federal Government

    Science.gov (United States)

    Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.

    1985-01-01

    In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

  4. RISC Processors and High Performance Computing

    Science.gov (United States)

    Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

    1995-01-01

    This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

  5. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  6. Low-Latency Embedded Vision Processor (LLEVS)

    Science.gov (United States)

    2016-03-01

    algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system

  7. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  8. Silicon Processors Using Organically Reconfigurable Techniques (SPORT)

    Science.gov (United States)

    2014-05-19

    AFRL-OSR-VA-TR-2014-0132 SILICON PROCESSORS USING ORGANICALLY RECONFIGURABLE TECHNIQUES ( SPORT ) Dennis Prather UNIVERSITY OF DELAWARE Final Report 05...5a. CONTRACT NUMBER Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) 5b. GRANT NUMBER FA9550-10-1-0363 5c...Contract: Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) Contract #: FA9550-10-1-0363 Reporting Period: 1 July 2010 – 31 December

  9. Quantum chemistry on a superconducting quantum processor

    Energy Technology Data Exchange (ETDEWEB)

    Kaicher, Michael P.; Wilhelm, Frank K. [Theoretical Physics, Saarland University, 66123 Saarbruecken (Germany); Love, Peter J. [Department of Physics and Astronomy, Tufts University, Medford, MA 02155 (United States)

    2016-07-01

    Quantum chemistry is the most promising civilian application for quantum processors to date. We study its adaptation to superconducting (sc) quantum systems, computing the ground state energy of LiH through a variational hybrid quantum classical algorithm. We demonstrate how interactions native to sc qubits further reduce the amount of quantum resources needed, pushing sc architectures as a near-term candidate for simulations of more complex atoms/molecules.

  10. Debugging in a multi-processor environment

    International Nuclear Information System (INIS)

    Spann, J.M.

    1981-01-01

    The Supervisory Control and Diagnostic System (SCDS) for the Mirror Fusion Test Facility (MFTF) consists of nine 32-bit minicomputers arranged in a tightly coupled distributed computer system utilizing a share memory as the data exchange medium. Debugging of more than one program in the multi-processor environment is a difficult process. This paper describes what new tools were developed and how the testing of software is performed in the SCDS for the MFTF project

  11. Multibus-based parallel processor for simulation

    Science.gov (United States)

    Ogrady, E. P.; Wang, C.-H.

    1983-01-01

    A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

  12. Code compression for VLIW embedded processors

    Science.gov (United States)

    Piccinelli, Emiliano; Sannino, Roberto

    2004-04-01

    The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

  13. Techniques for optimizing inerting in electron processors

    International Nuclear Information System (INIS)

    Rangwalla, I.J.; Korn, D.J.; Nablo, S.V.

    1993-01-01

    The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NO x which can be transported from the process zone by the product into the work area. Since the tolerable levels for O 3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O 2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O 2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O 2 ). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O 2 ) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O 2 ) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

  14. Treecode with a Special-Purpose Processor

    Science.gov (United States)

    Makino, Junichiro

    1991-08-01

    We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

  15. Plant intelligence

    Science.gov (United States)

    Lipavská, Helena; Žárský, Viktor

    2009-01-01

    The concept of plant intelligence, as proposed by Anthony Trewavas, has raised considerable discussion. However, plant intelligence remains loosely defined; often it is either perceived as practically synonymous to Darwinian fitness, or reduced to a mere decorative metaphor. A more strict view can be taken, emphasizing necessary prerequisites such as memory and learning, which requires clarifying the definition of memory itself. To qualify as memories, traces of past events have to be not only stored, but also actively accessed. We propose a criterion for eliminating false candidates of possible plant intelligence phenomena in this stricter sense: an “intelligent” behavior must involve a component that can be approximated by a plausible algorithmic model involving recourse to stored information about past states of the individual or its environment. Re-evaluation of previously presented examples of plant intelligence shows that only some of them pass our test. “You were hurt?” Kumiko said, looking at the scar. Sally looked down. “Yeah.” “Why didn't you have it removed?” “Sometimes it's good to remember.” “Being hurt?” “Being stupid.”—(W. Gibson: Mona Lisa Overdrive) PMID:19816094

  16. Speech Intelligibility

    Science.gov (United States)

    Brand, Thomas

    Speech intelligibility (SI) is important for different fields of research, engineering and diagnostics in order to quantify very different phenomena like the quality of recordings, communication and playback devices, the reverberation of auditoria, characteristics of hearing impairment, benefit using hearing aids or combinations of these things.

  17. Multi-processor network implementations in Multibus II and VME

    International Nuclear Information System (INIS)

    Briegel, C.

    1992-01-01

    ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

  18. Design of smart home gateway based on Wi-Fi and ZigBee

    Science.gov (United States)

    Li, Yang

    2018-04-01

    With the increasing demand for home lifestyle, the traditional smart home products have been unable to meet the needs of users. Aim at the complex wiring, high cost and difficult operation problems of traditional smart home system, this paper designs a home gateway for smart home system based on Wi-Fi and ZigBee. This paper first gives a smart home system architecture base on cloud server, Wi-Fi and ZigBee. This architecture enables users to access the smart home system remotely from Internet through the cloud server or through Wi-Fi at home. It also offers the flexibility and low cost of ZigBee wireless networking for home equipment. This paper analyzes the functional requirements of the home gateway, and designs a modular hardware architecture based on the RT5350 wireless gateway module and the CC2530 ZigBee coordinator module. Also designs the software of the home gateway, including the gateway master program and the ZigBee coordinator program. Finally, the smart home system and home gateway are tested in two kinds of network environments, internal network and external network. The test results show that the designed home gateway can meet the requirements, support remote and local access, support multi-user, support information security technology, and can timely report equipment status information.

  19. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  20. E-DECIDER Decision Support Gateway For Earthquake Disaster Response

    Science.gov (United States)

    Glasscoe, M. T.; Stough, T. M.; Parker, J. W.; Burl, M. C.; Donnellan, A.; Blom, R. G.; Pierce, M. E.; Wang, J.; Ma, Y.; Rundle, J. B.; Yoder, M. R.

    2013-12-01

    Earthquake Data Enhanced Cyber-Infrastructure for Disaster Evaluation and Response (E-DECIDER) is a NASA-funded project developing capabilities for decision-making utilizing remote sensing data and modeling software in order to provide decision support for earthquake disaster management and response. E-DECIDER incorporates earthquake forecasting methodology and geophysical modeling tools developed through NASA's QuakeSim project in order to produce standards-compliant map data products to aid in decision-making following an earthquake. Remote sensing and geodetic data, in conjunction with modeling and forecasting tools, help provide both long-term planning information for disaster management decision makers as well as short-term information following earthquake events (i.e. identifying areas where the greatest deformation and damage has occurred and emergency services may need to be focused). E-DECIDER utilizes a service-based GIS model for its cyber-infrastructure in order to produce standards-compliant products for different user types with multiple service protocols (such as KML, WMS, WFS, and WCS). The goal is to make complex GIS processing and domain-specific analysis tools more accessible to general users through software services as well as provide system sustainability through infrastructure services. The system comprises several components, which include: a GeoServer for thematic mapping and data distribution, a geospatial database for storage and spatial analysis, web service APIs, including simple-to-use REST APIs for complex GIS functionalities, and geoprocessing tools including python scripts to produce standards-compliant data products. These are then served to the E-DECIDER decision support gateway (http://e-decider.org), the E-DECIDER mobile interface, and to the Department of Homeland Security decision support middleware UICDS (Unified Incident Command and Decision Support). The E-DECIDER decision support gateway features a web interface that

  1. Multi-Modal Traveler Information System - Gateway Functional Requirements

    Science.gov (United States)

    1997-11-17

    The Multi-Modal Traveler Information System (MMTIS) project involves a large number of Intelligent Transportation System (ITS) related tasks. It involves research of all ITS initiatives in the Gary-Chicago-Milwaukee (GCM) Corridor which are currently...

  2. Formal Semantics and Implementation of BPMN 2.0 Inclusive Gateways

    Science.gov (United States)

    Christiansen, David Raymond; Carbone, Marco; Hildebrandt, Thomas

    We present the first direct formalization of the semantics of inclusive gateways as described in the Business Process Modeling Notation (BPMN) 2.0 Beta 1 specification. The formal semantics is given for a minimal subset of BPMN 2.0 containing just the inclusive and exclusive gateways and the start and stop events. By focusing on this subset we achieve a simple graph model that highlights the particular non-local features of the inclusive gateway semantics. We sketch two ways of implementing the semantics using algorithms based on incrementally updated data structures and also discuss distributed communication-based implementations of the two algorithms.

  3. Recombinational Cloning Using Gateway and In-Fusion Cloning Schemes

    Science.gov (United States)

    Throop, Andrea L.; LaBaer, Joshua

    2015-01-01

    The comprehensive study of protein structure and function, or proteomics, depends on the obtainability of full-length cDNAs in species-specific expression vectors and subsequent functional analysis of the expressed protein. Recombinational cloning is a universal cloning technique based on site-specific recombination that is independent of the insert DNA sequence of interest, which differentiates this method from the classical restriction enzyme-based cloning methods. Recombinational cloning enables rapid and efficient parallel transfer of DNA inserts into multiple expression systems. This unit summarizes strategies for generating expression-ready clones using the most popular recombinational cloning technologies, including the commercially available Gateway® (Life Technologies) and In-Fusion® (Clontech) cloning technologies. PMID:25827088

  4. Design of Mobile Gateway for Implementation of Smart Work System

    Directory of Open Access Journals (Sweden)

    Sang-Young Oh

    2015-01-01

    Full Text Available In the development of new technologies based on mobile system, there is a growing interest as a fundamental technology. In particular, in order to realize a mobile office and mobile phones, conferencing remote document is a technique that can realize smart network services solutions with enhanced real-time communication, real-time information sharing, and collaboration. Therefore, in this paper, the design meets the diverse needs of customers and the smart work platform mobile-based fast and conveniently it is trying to develop. For this reason, I have developed a mobile gateway that is based on the communication server construction OPEN API development, management of mobile ID, protocol design, and design of SSL/TLS security tunnel. Also, we developed a smart work platform that you apply this, you are trying to provide information systems environment of mobile company.

  5. Artificial Intelligence.

    Science.gov (United States)

    Lawrence, David R; Palacios-González, César; Harris, John

    2016-04-01

    It seems natural to think that the same prudential and ethical reasons for mutual respect and tolerance that one has vis-à-vis other human persons would hold toward newly encountered paradigmatic but nonhuman biological persons. One also tends to think that they would have similar reasons for treating we humans as creatures that count morally in our own right. This line of thought transcends biological boundaries-namely, with regard to artificially (super)intelligent persons-but is this a safe assumption? The issue concerns ultimate moral significance: the significance possessed by human persons, persons from other planets, and hypothetical nonorganic persons in the form of artificial intelligence (AI). This article investigates why our possible relations to AI persons could be more complicated than they first might appear, given that they might possess a radically different nature to us, to the point that civilized or peaceful coexistence in a determinate geographical space could be impossible to achieve.

  6. Intelligent Tutor

    Science.gov (United States)

    1990-01-01

    NASA also seeks to advance American education by employing the technology utilization process to develop a computerized, artificial intelligence-based Intelligent Tutoring System (ITS) to help high school and college physics students. The tutoring system is designed for use with the lecture and laboratory portions of a typical physics instructional program. Its importance lies in its ability to observe continually as a student develops problem solutions and to intervene when appropriate with assistance specifically directed at the student's difficulty and tailored to his skill level and learning style. ITS originated as a project of the Johnson Space Center (JSC). It is being developed by JSC's Software Technology Branch in cooperation with Dr. R. Bowen Loftin at the University of Houston-Downtown. Program is jointly sponsored by NASA and ACOT (Apple Classrooms of Tomorrow). Other organizations providing support include Texas Higher Education Coordinating Board, the National Research Council, Pennzoil Products Company and the George R. Brown Foundation. The Physics I class of Clear Creek High School, League City, Texas are providing the classroom environment for test and evaluation of the system. The ITS is a spinoff product developed earlier to integrate artificial intelligence into training/tutoring systems for NASA astronauts flight controllers and engineers.

  7. Modcomp MAX IV System Processors reference guide

    Energy Technology Data Exchange (ETDEWEB)

    Cummings, J.

    1990-10-01

    A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

  8. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  9. The design of a graphics processor

    International Nuclear Information System (INIS)

    Holmes, M.; Thorne, A.R.

    1975-12-01

    The design of a graphics processor is described which takes into account known and anticipated user requirements, the availability of cheap minicomputers, the state of integrated circuit technology, and the overall need to minimise cost for a given performance. The main user needs are the ability to display large high resolution pictures, and to dynamically change the user's view in real time by means of fast coordinate processing hardware. The transformations that can be applied to 2D or 3D coordinates either singly or in combination are: translation, scaling, mirror imaging, rotation, and the ability to map the transformation origin on to any point on the screen. (author)

  10. Dual-scale topology optoelectronic processor.

    Science.gov (United States)

    Marsden, G C; Krishnamoorthy, A V; Esener, S C; Lee, S H

    1991-12-15

    The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.

  11. Nuclear interactive evaluations on distributed processors

    International Nuclear Information System (INIS)

    Dix, G.E.; Congdon, S.P.

    1988-01-01

    BWR [boiling water reactor] nuclear design is a complicated process, involving trade-offs among a variety of conflicting objectives. Complex computer calculations and usually required for each design iteration. GE Nuclear Energy has implemented a system where the evaluations are performed interactively on a large number of small microcomputers. This approach minimizes the time it takes to carry out design iterations even through the processor speeds are low compared with modern super computers. All of the desktop microcomputers are linked to a common data base via an ethernet communications system so that design data can be shared and data quality can be maintained

  12. Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    Levinskas, D.

    1993-01-01

    This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves

  13. Lattice gauge theory using parallel processors

    International Nuclear Information System (INIS)

    Lee, T.D.; Chou, K.C.; Zichichi, A.

    1987-01-01

    The book's contents include: Lattice Gauge Theory Lectures: Introduction and Current Fermion Simulations; Monte Carlo Algorithms for Lattice Gauge Theory; Specialized Computers for Lattice Gauge Theory; Lattice Gauge Theory at Finite Temperature: A Monte Carlo Study; Computational Method - An Elementary Introduction to the Langevin Equation, Present Status of Numerical Quantum Chromodynamics; Random Lattice Field Theory; The GF11 Processor and Compiler; and The APE Computer and First Physics Results; Columbia Supercomputer Project: Parallel Supercomputer for Lattice QCD; Statistical and Systematic Errors in Numerical Simulations; Monte Carlo Simulation for LGT and Programming Techniques on the Columbia Supercomputer; Food for Thought: Five Lectures on Lattice Gauge Theory

  14. Introduction to programming multiple-processor computers

    International Nuclear Information System (INIS)

    Hicks, H.R.; Lynch, V.E.

    1985-04-01

    FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult

  15. Design of an MSAT-X mobile transceiver and related base and gateway stations

    Science.gov (United States)

    Fang, Russell J. F.; Bhaskar, Udaya; Hemmati, Farhad; Mackenthun, Kenneth M.; Shenoy, Ajit

    This paper summarizes the results of a design study of the mobile transceiver, base station, and gateway station for NASA's proposed Mobile Satellite Experiment (MSAT-X). Major ground segment system design issues such as frequency stability control, modulation method, linear predictive coding vocoder algorithm, and error control technique are addressed. The modular and flexible transceiver design is described in detail, including the core, RF/IF, modem, vocoder, forward error correction codec, amplitude-companded single sideband, and input/output modules, as well as the flexible interface. Designs for a three-carrier base station and a 10-carrier gateway station are also discussed, including the interface with the controllers and with the public-switched telephone networks at the gateway station. Functional specifications are given for the transceiver, the base station, and the gateway station.

  16. Enabling Global Lunar Sample Return and Life-Detection Studies Using a Deep-Space Gateway

    Science.gov (United States)

    Cohen, B. A.; Eigenbrode, J. A.; Young, K. E.; Bleacher, J. E.; Trainer, M. E.

    2018-02-01

    The Deep Space Gateway could uniquely enable a lunar robotic sampling campaign that would provide incredible science return as well as feed forward to Mars and Europa by testing instrument sterility and ability to distinguish biogenic signals.

  17. Communications Relay and Human-Assisted Sample Return from the Deep Space Gateway

    Science.gov (United States)

    Cichan, T.; Hopkins, J. B.; Bierhaus, B.; Murrow, D. W.

    2018-02-01

    The Deep Space Gateway can enable or enhance exploration of the lunar surface through two capabilities: 1. communications relay, opening up access to the lunar farside, and 2. sample return, enhancing the ability to return large sample masses.

  18. Characterization of Outer Space Radiation Induced Changes in Extremophiles Utilizing Deep Space Gateway Opportunities

    Science.gov (United States)

    Venkateswaran, K.; Wang, C.; Smith, D.; Mason, C.; Landry, K.; Rettberg, P.

    2018-02-01

    Extremophilic microbial survival, adaptation, biological functions, and molecular mechanisms associated with outer space radiation can be tested by exposing them onto Deep Space Gateway hardware (inside/outside) using microbiology and molecular biology techniques.

  19. Wetlands & Deepwater Habitats - MO 2012 East West Gateway Wetland Restoration Rank (GDB)

    Data.gov (United States)

    NSGIC State | GIS Inventory — Over the past five years, the East-West Gateway Council of Governments has facilitated creation of data layers to enhance conservation and transportation planning in...

  20. Design of an MSAT-X mobile transceiver and related base and gateway stations

    Science.gov (United States)

    Fang, Russell J. F.; Bhaskar, Udaya; Hemmati, Farhad; Mackenthun, Kenneth M.; Shenoy, Ajit

    1987-01-01

    This paper summarizes the results of a design study of the mobile transceiver, base station, and gateway station for NASA's proposed Mobile Satellite Experiment (MSAT-X). Major ground segment system design issues such as frequency stability control, modulation method, linear predictive coding vocoder algorithm, and error control technique are addressed. The modular and flexible transceiver design is described in detail, including the core, RF/IF, modem, vocoder, forward error correction codec, amplitude-companded single sideband, and input/output modules, as well as the flexible interface. Designs for a three-carrier base station and a 10-carrier gateway station are also discussed, including the interface with the controllers and with the public-switched telephone networks at the gateway station. Functional specifications are given for the transceiver, the base station, and the gateway station.

  1. Lunar Heat Flux Measurements Enabled by a Microwave Radiometer Aboard the Deep Space Gateway

    Science.gov (United States)

    Siegler, M.; Ruf, C.; Putzig, N.; Morgan, G.; Hayne, P.; Paige, D.; Nagihara, S.; Weber, R.

    2018-02-01

    We would like to present a concept to use the Deep Space Gateway as a platform for constraining the geothermal heat production, surface, and near-surface rocks, and dielectric properties of the Moon from orbit with passive microwave radiometery.

  2. Basic and Applied Algal Life Support System Research on Board the Deep Space Gateway

    Science.gov (United States)

    Niederwieser, T.; Zea, L.; Anthony, J.; Stodieck, L.

    2018-02-01

    We study the effect of long-term preservation methods on DNA damage of algal cultures for BLSS applications. In a secondary step, the Deep Space Gateway serves as a technology demonstration platform for algal photobioreactors in intermittently occupied habitats.

  3. Recommending the heterogeneous cluster type multi-processor system computing

    International Nuclear Information System (INIS)

    Iijima, Nobukazu

    2010-01-01

    Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

  4. SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

    Science.gov (United States)

    Moyer, Ruth A.

    Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

  5. Intelligent Design and Intelligent Failure

    Science.gov (United States)

    Jerman, Gregory

    2015-01-01

    Good Evening, my name is Greg Jerman and for nearly a quarter century I have been performing failure analysis on NASA's aerospace hardware. During that time I had the distinct privilege of keeping the Space Shuttle flying for two thirds of its history. I have analyzed a wide variety of failed hardware from simple electrical cables to cryogenic fuel tanks to high temperature turbine blades. During this time I have found that for all the time we spend intelligently designing things, we need to be equally intelligent about understanding why things fail. The NASA Flight Director for Apollo 13, Gene Kranz, is best known for the expression "Failure is not an option." However, NASA history is filled with failures both large and small, so it might be more accurate to say failure is inevitable. It is how we react and learn from our failures that makes the difference.

  6. A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

    OpenAIRE

    Ding, Fei; Song, Aiguo; Tong, En; Li, Jianqing

    2016-01-01

    A smart home gateway plays an important role in the Internet of Things (IoT) system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN) layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integr...

  7. Communication-Gateway Software For NETEX, DECnet, And TCP/IP

    Science.gov (United States)

    Keith, B.; Ferry, D.; Fendler, E.

    1990-01-01

    Communications gateway software, GATEWAY, provides process-to-process communication between remote applications programs in different protocol domains. Communicating peer processes may be resident on any paired combination of NETEX, DECnet, or TCP/IP hosts. Provides necessary mapping from one protocol to another and facilitates practical intermachine communications in cost-effective manner by eliminating need to standardize on single protocol or to implement multiple protocols in host computers. Written in Ada.

  8. GATEWAY Report Brief: OLED Lighting in the Offices of Aurora Lighting Design, Inc.

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2016-05-31

    Summary of a GATEWAY report evaluation at the offices of Aurora Lighting Design, Inc., in Grayslake, IL, where the GATEWAY program conducted its first investigation involving OLED lighting. The project experienced several challenges, but also highlighted a number of promising attributes – which indicate that with continued improvements in efficacy, longevity, size, and flexibility, OLEDs could provide a new tool for creative and effective lighting.

  9. Design of intelligent power consumption optimization and visualization management platform for large buildings based on internet of things

    Directory of Open Access Journals (Sweden)

    Gong Shulan

    2017-01-01

    Full Text Available The buildings provide a significant contribution to total energy consumption and CO2 emission. It has been estimated that the development of an intelligent power consumption monitor and control system will result in about 30% savings in energy consumption. This design innovatively integrates the advanced technologies such as the internet of things, the internet, intelligent buildings and intelligent electricity which can offer open, efficient, convenient energy consumption detection platform in demand side and visual management demonstration application platform in power enterprises side. The system was created to maximize the effective and efficient the use of energy resource. It was development around sensor networks and intelligent gateway and the monitoring center software. This will realize the highly integration and comprehensive application in energy and information to meet the needs with intelligent buildings

  10. Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

    OpenAIRE

    Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

    2016-01-01

    International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

  11. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  12. Intelligent networks recent approaches and applications in medical systems

    CERN Document Server

    Ahamed, Syed V

    2013-01-01

    This textbook offers an insightful study of the intelligent Internet-driven revolutionary and fundamental forces at work in society. Readers will have access to tools and techniques to mentor and monitor these forces rather than be driven by changes in Internet technology and flow of money. These submerged social and human forces form a powerful synergistic foursome web of (a) processor technology, (b) evolving wireless networks of the next generation, (c) the intelligent Internet, and (d) the motivation that drives individuals and corporations. In unison, the technological forces can tear

  13. Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway di Petshop "PetZone"

    Directory of Open Access Journals (Sweden)

    Siska Fadhilah Wati

    2013-09-01

    Full Text Available Dewasa ini teknologi informasi sangat membantu dalam dunia bisnis. Kemudahan yang ditawarkan akan menjaring lebih banyak konsumen. Namun, perusahan tingkat menengah seperti PetZone saat ini masih jarang yang menawarkan kemudahan berbelanja atau pemesanan layanan secara online. Oleh karena itu diperlukan sebuah sistem berbasis web di perusahaan PetZone yang dapat memudahkan pemilik dan karyawan dalam apenjualan, pelayanan, dan pemasaran, serta memudahkan pelanggan dalam jual-beli barang dan jasa. Atas dasar masalah tersebut dibangun Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway untuk menunjang proses bisnis yang ada. Sistem informasi dibangun menggunakan bahasa pemrograman PHP framework Codeigniter, javascript untuk tampilan yang dinamis, dan database MySQL. Proses pembuatan dan pengembangan Sistem Informasi Penjualan ini menggunakan metode air terjun. Metode air terjun meliputi kebutuhan pengguna, analisis, rancangan, implementasi dan pengujian. Pemodelan Sistem Informasi yang dibangun menggunakan metode berorientasi objek UML (Unified Modeling Language yang terdiri dari Use case  diagram, Class diagram dan Sequence diagram. Hasil pengujian Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway menunjukkan bahwa semua fitur yang terdapat baik dalam sistem informasi maupun SMS gateway dapat bekerja dengan baikdengan ratusan sample data, dan server SMS gateway dapat memproses lebih dari satu SMS secara bersamaan. Dalam perkembangan ke depannya nanti, Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway masih dapat dikembangkan lagi dengan menambah fitur-fitur pada SMS gateway sehingga lebih memudahkan konsumen.

  14. XDS-I Gateway Development for HIE Connectivity with Legacy PACS at Gil Hospital.

    Science.gov (United States)

    Simalango, Mikael Fernandus; Kim, Youngchul; Seo, Young Tae; Choi, Young Hwan; Cho, Yong Kyun

    2013-12-01

    The ability to support healthcare document sharing is imperative in a health information exchange (HIE). Sharing imaging documents or images, however, can be challenging, especially when they are stored in a picture archiving and communication system (PACS) archive that does not support document sharing via standard HIE protocols. This research proposes a standard-compliant imaging gateway that enables connectivity between a legacy PACS and the entire HIE. Investigation of the PACS solutions used at Gil Hospital was conducted. An imaging gateway application was then developed using a Java technology stack. Imaging document sharing capability enabled by the gateway was tested by integrating it into Gil Hospital's order communication system and its HIE infrastructure. The gateway can acquire radiology images from a PACS storage system, provide and register the images to Gil Hospital's HIE for document sharing purposes, and make the images retrievable by a cross-enterprise document sharing document viewer. Development of an imaging gateway that mediates communication between a PACS and an HIE can be considered a viable option when the PACS does not support the standard protocol for cross-enterprise document sharing for imaging. Furthermore, the availability of common HIE standards expedites the development and integration of the imaging gateway with an HIE.

  15. Fast track trigger processor for the OPAL detector at LEP

    Energy Technology Data Exchange (ETDEWEB)

    Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

    1986-09-20

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

  16. Special processor for in-core control systems

    International Nuclear Information System (INIS)

    Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

    1978-01-01

    The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

  17. Development of level 2 processor for the readout of TMC

    International Nuclear Information System (INIS)

    Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

    1995-01-01

    We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

  18. Smart Meter (Gateways). Attacks and implementation of a cost effective security solution; Smart Meter (Gateways). Angriffe und Umsetzung einer kostenguenstigen Sicherheitsloesung

    Energy Technology Data Exchange (ETDEWEB)

    Krauss, Christoph [Fraunhofer Research Institution AISEC, Garching (Germany); Sigl, Georg [Technische Univ. Muenchen (Germany); Stumpf, Frederic

    2012-07-01

    Smart Meter (Gateways) are a central component of future Smart Grids and their secure operation must be ensured. In this paper, we first present several attacks on actual smart meter and gateway systems. Next, we describe a possible security solution which meets the requirements of the protection profile specified by the German Federal Office for Information Security (BIS) as far as possible with current available technology and includes additional security mechanisms. To realize a cost-efficient solution, we use off-the-shelf hardware for the mandatory Hardware Security Module (HSM) in form of a Trusted Platform Module (TPM). Finally, we give a brief overview on alternative approaches. (orig.)

  19. Flood risk and insurance loss potential in the Thames Gateway

    Science.gov (United States)

    Eldridge, J.; Horn, D.

    2009-04-01

    The Thames Gateway, currently Europe's largest regeneration project, is an area of redevelopment located in the South East of England, with Government plans to create up to 160,000 new homes and 180,000 new jobs by 2016. Although the new development is intended to contribute £12bn annually to the economy, the potential flood risk is high, with much of the area situated on Thames tidal floodplain and vulnerable to both storm surges and peak river flows. This poses significant hazard to those inhabiting the area and has raised concern amongst the UK insurance industry, who would be liable for significant financial claims if a large flood event were to occur, particularly with respect to the number of new homes and businesses being built in flood risk areas. Flood risk and the potential damage to both lives and assets in vulnerable areas have gained substantial recognition, in light of recent flooding events, from both governmental agencies and in the public's awareness of flood hazard. This has resulted in a change in UK policy with planning policy for flood risk (PPS25, Planning Policy Statement 25) adopting a more strategic approach to development, as well as a new Flooding and Water Bill which is due for consultation in 2009. The Government and the Association of British Insurers, who represent the UK insurance industry, have also recently changed their Statement of Principles which guides provision of flood insurance in the future. This PhD research project aims to quantify flood risk in the Thames Gateway area with a view to evaluating the insurance loss potential under different insurance and planning scenarios. Using current sources of inundation extent, and incorporating varying insurance penetration rates and degrees of adoption of planning policy and guidance, it focuses on estimating flood risk under these different scenarios. This presentation introduces the development of the project and the theory and methodology which will be used to address the

  20. Smart and Intelligent Sensors

    Science.gov (United States)

    Lansaw, John; Schmalzel, John; Figueroa, Jorge

    2009-01-01

    John C. Stennis Space Center (SSC) provides rocket engine propulsion testing for NASA's space programs. Since the development of the Space Shuttle, every Space Shuttle Main Engine (SSME) has undergone acceptance testing at SSC before going to Kennedy Space Center (KSC) for integration into the Space Shuttle. The SSME is a large cryogenic rocket engine that uses Liquid Hydrogen (LH2) as the fuel. As NASA moves to the new ARES V launch system, the main engines on the new vehicle, as well as the upper stage engine, are currently base lined to be cryogenic rocket engines that will also use LH2. The main rocket engines for the ARES V will be larger than the SSME, while the upper stage engine will be approximately half that size. As a result, significant quantities of hydrogen will be required during the development, testing, and operation of these rocket engines.Better approaches are needed to simplify sensor integration and help reduce life-cycle costs. 1.Smarter sensors. Sensor integration should be a matter of "plug-and-play" making sensors easier to add to a system. Sensors that implement new standards can help address this problem; for example, IEEE STD 1451.4 defines transducer electronic data sheet (TEDS) templates for commonly used sensors such as bridge elements and thermocouples. When a 1451.4 compliant smart sensor is connected to a system that can read the TEDS memory, all information needed to configure the data acquisition system can be uploaded. This reduces the amount of labor required and helps minimize configuration errors. 2.Intelligent sensors. Data received from a sensor be scaled, linearized; and converted to engineering units. Methods to reduce sensor processing overhead at the application node are needed. Smart sensors using low-cost microprocessors with integral data acquisition and communication support offer the means to add these capabilities. Once a processor is embedded, other features can be added; for example, intelligent sensors can make

  1. Business Intelligence

    OpenAIRE

    Petersen, Anders

    2001-01-01

    Cílem této bakalářské práce je seznámení s Business Intelligence a zpracování vývojového trendu, který ovlivňuje podobu řešení Business Intelligence v podniku ? Business Activity Monitoring. Pro zpracování tohoto tématu byla použita metoda studia odborných pramenů, a to jak v českém, tak v anglickém jazyce. Hlavním přínosem práce je ucelený, v českém jazyce zpracovaný materiál pojednávající o Business Activity Monitoring. Práce je rozdělena do šesti hlavních kapitol. Prvních pět je věnováno p...

  2. Web Intelligence and Artificial Intelligence in Education

    Science.gov (United States)

    Devedzic, Vladan

    2004-01-01

    This paper surveys important aspects of Web Intelligence (WI) in the context of Artificial Intelligence in Education (AIED) research. WI explores the fundamental roles as well as practical impacts of Artificial Intelligence (AI) and advanced Information Technology (IT) on the next generation of Web-related products, systems, services, and…

  3. Aspects of computation on asynchronous parallel processors

    International Nuclear Information System (INIS)

    Wright, M.

    1989-01-01

    The increasing availability of asynchronous parallel processors has provided opportunities for original and useful work in scientific computing. However, the field of parallel computing is still in a highly volatile state, and researchers display a wide range of opinion about many fundamental questions such as models of parallelism, approaches for detecting and analyzing parallelism of algorithms, and tools that allow software developers and users to make effective use of diverse forms of complex hardware. This volume collects the work of researchers specializing in different aspects of parallel computing, who met to discuss the framework and the mechanics of numerical computing. The far-reaching impact of high-performance asynchronous systems is reflected in the wide variety of topics, which include scientific applications (e.g. linear algebra, lattice gauge simulation, ordinary and partial differential equations), models of parallelism, parallel language features, task scheduling, automatic parallelization techniques, tools for algorithm development in parallel environments, and system design issues

  4. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  5. The ALICE Central Trigger Processor (CTP) upgrade

    International Nuclear Information System (INIS)

    Krivda, M.; Alexandre, D.; Barnby, L.S.; Evans, D.; Jones, P.G.; Jusko, A.; Lietava, R.; Baillie, O. Villalobos; Pospíšil, J.

    2016-01-01

    The ALICE Central Trigger Processor (CTP) at the CERN LHC has been upgraded for LHC Run 2, to improve the Transition Radiation Detector (TRD) data-taking efficiency and to improve the physics performance of ALICE. There is a new additional CTP interaction record sent using a new second Detector Data Link (DDL), a 2 GB DDR3 memory and an extension of functionality for classes. The CTP switch has been incorporated directly onto the new LM0 board. A design proposal for an ALICE CTP upgrade for LHC Run 3 is also presented. Part of the development is a low latency high bandwidth interface whose purpose is to minimize an overall trigger latency

  6. Processor-in-memory-and-storage architecture

    Science.gov (United States)

    DeBenedictis, Erik

    2018-01-02

    A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

  7. Ethics as a Gateway to Computer Science in Primary Education

    Directory of Open Access Journals (Sweden)

    Juan Vicente OLTRA GUTIÉRREZ

    2017-07-01

    Full Text Available This paper presents a proposal to bring ethics and ICT closer to students of the first courses of the primary education, supporting one in each other, following the Law “Real Decreto 126/2014, 28th of February”, which establishes the basic curriculum for Primary Education. Within this Law, two of seven skills in the curriculum are established: digital skill (the third and also social and civic skills (the fifth. Given the digital natives population who are receiving education, it would be a slightly more ambitious goal to be able to glimpse them to support one in another. In this area, for example, we find a specific subject such as “Social and Civic values” with evaluation criteria such as “Employ new technologies by developing social and civic values in safe environments”. Thanks to this gateway, we can introduce small door to the vision of computer science, through ethics, which may be transversal with all subjects of the curriculum. The suggestion of the present article is to confront teachers with a vision of technology from an outside perspective, from an ethical prism, once the technology is turned it off and the mobiles or tablets screens are converted into a mere black mirror.

  8. Data Leakage Prevention: E-Mail Protection via Gateway

    Science.gov (United States)

    Kaur, Kamaljeet; Gupta, Ishu; Singh, Ashutosh Kumar

    2018-01-01

    Protection of digital assets and intellectual property is becoming a challenge for most of the companies. Due to increasing availability of database services on internet, data may be insecure after passing through precarious networks. To protect intellectual property (IP) is a major concern for today's organizations, because a leakage that compromises IP means, sensitive information of a company is in the hands of biggest competitors. Electronic information processing and communication is replacing paper in many applications increasingly. Instead of paper, an email is being used for communication at workplace and from social media logins to bank accounts. Nowadays an email is becoming a mainstream business tool. An email can be misused to leave company’s sensitive data open to compromise. So, it may be of little surprise that attacks on emails are common. So, here we need an email protection system (EPS) that will protect information to leave organization via mail. In this paper, we developed an algorithm that will offer email protection via gateway during data transfer. This algorithm matches the patterns with the keywords stored in the database and then takes the actions accordingly to protect the data. This paper describes why email protection is important? How companies can protect their confidential information from being leaked by insiders.

  9. Optimal processor for malfunction detection in operating nuclear reactor

    International Nuclear Information System (INIS)

    Ciftcioglu, O.

    1990-01-01

    An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

  10. Sojourn time tails in processor-sharing systems

    NARCIS (Netherlands)

    Egorova, R.R.

    2009-01-01

    The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

  11. ACP/R3000 processors in data acquisition systems

    International Nuclear Information System (INIS)

    Deppe, J.; Areti, H.; Atac, R.

    1989-02-01

    We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

  12. On the effective parallel programming of multi-core processors

    NARCIS (Netherlands)

    Varbanescu, A.L.

    2010-01-01

    Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

  13. Bank switched memory interface for an image processor

    International Nuclear Information System (INIS)

    Barron, M.; Downward, J.

    1980-09-01

    A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

  14. Digital image processing software system using an array processor

    International Nuclear Information System (INIS)

    Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.

    1981-01-01

    A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

  15. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  16. Biomass is beginning to threaten the wood-processors

    International Nuclear Information System (INIS)

    Beer, G.; Sobinkovic, B.

    2004-01-01

    In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

  17. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  18. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  19. Recursive Matrix Inverse Update On An Optical Processor

    Science.gov (United States)

    Casasent, David P.; Baranoski, Edward J.

    1988-02-01

    A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

  20. The crustal dynamics intelligent user interface anthology

    Science.gov (United States)

    Short, Nicholas M., Jr.; Campbell, William J.; Roelofs, Larry H.; Wattawa, Scott L.

    1987-01-01

    The National Space Science Data Center (NSSDC) has initiated an Intelligent Data Management (IDM) research effort which has, as one of its components, the development of an Intelligent User Interface (IUI). The intent of the IUI is to develop a friendly and intelligent user interface service based on expert systems and natural language processing technologies. The purpose of such a service is to support the large number of potential scientific and engineering users that have need of space and land-related research and technical data, but have little or no experience in query languages or understanding of the information content or architecture of the databases of interest. This document presents the design concepts, development approach and evaluation of the performance of a prototype IUI system for the Crustal Dynamics Project Database, which was developed using a microcomputer-based expert system tool (M. 1), the natural language query processor THEMIS, and the graphics software system GSS. The IUI design is based on a multiple view representation of a database from both the user and database perspective, with intelligent processes to translate between the views.

  1. Middle Miocene paleoenvironmental crises in Central Eurasia caused by changes in marine gateway configuration

    Science.gov (United States)

    Palcu, D. V.; Golovina, L. A.; Vernyhorova, Y. V.; Popov, S. V.; Krijgsman, W.

    2017-11-01

    Marine gateways prove to be important factors for changes in the ecology and biochemistry of marginal seas. Changes in gateway configuration played a dominant role in the Middle Miocene paleogeographic evolution of the Paratethys Sea that covered Central Eurasia. Here, we focus on the connection between the Central (CP) and Eastern Paratethys (EP) to understand the paleoenvironmental changes caused by the evolution of this marine gateway. We first construct an integrated magneto-biostratigraphic framework for the late Langhian-Serravallian (Chokrakian-Karaganian-Konkian-Volhynian) sedimentary record of the eastern domain, which allows a correlation to the well-dated successions west of the gateway. The magneto-biostratigraphic results from the Zelensky-Panagia section on the Black Sea coast of Russia show that the Chokrakian/Karaganian boundary has an age of 13.8 Ma, the Karaganian/Konkian boundary is dated at 13.4 Ma, and the Konkian/Volhynian boundary at 12.65 Ma. We identify three major phases on gateway functioning that are reflected in specific environmental changes. During the Karaganian, the EP turned into a lake-sea that supplied a unidirectional flow of low-salinity waters to the west, where the CP sea experienced its Badenian Salinity Crisis. This configuration is remarkably similar to the Mediterranean during its Messinian Salinity Crisis. The second phase is marked by a marine transgression from the west, reinstalling open-marine conditions in the CP and causing marine incursions in the EP during the Konkian. The Volhynian is characterized by a new gateway configuration that allows exchange between CP and EP, creating unified conditions all over the Paratethys. We hypothesize that a density driven pumping mechanism is triggered by the increase in connectivity at the Konkian/Volhynian boundary, which simultaneously caused major paleoenvironmental changes at both sides of the gateway and led to the Badenian-Sarmatian extinction event in the CP.

  2. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  3. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  4. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  5. Experimental testing of the noise-canceling processor.

    Science.gov (United States)

    Collins, Michael D; Baer, Ralph N; Simpson, Harry J

    2011-09-01

    Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

  6. Simulation of a processor switching circuit with APLSV

    International Nuclear Information System (INIS)

    Dilcher, H.

    1979-01-01

    The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

  7. New development for low energy electron beam processor

    International Nuclear Information System (INIS)

    Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

    2003-01-01

    Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

  8. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

  9. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  10. Intelligence and negotiating

    International Nuclear Information System (INIS)

    George, D.G.

    1990-01-01

    This paper discusses the role of US intelligence during arms control negotiations between 1982 and 1987. It also covers : the orchestration of intelligence projects; an evaluation of the performance of intelligence activities; the effect intelligence work had on actual arms negotiations; and suggestions for improvements in the future

  11. Intelligent products : A survey

    NARCIS (Netherlands)

    Meyer, G.G.; Främling, K.; Holmström, J.

    This paper presents an overview of the field of Intelligent Products. As Intelligent Products have many facets, this paper is mainly focused on the concept behind Intelligent Products, the technical foundations, and the achievable practical goals of Intelligent Products. A novel classification of

  12. Intelligence Issues for Congress

    Science.gov (United States)

    2013-04-23

    open source information— osint (newspapers...by user agencies. Section 1052 of the Intelligence Reform Act expressed the sense of Congress that there should be an open source intelligence ...center to coordinate the collection, analysis, production, and dissemination of open source intelligence to other intelligence agencies. An Open Source

  13. Intelligent Governmentality

    Directory of Open Access Journals (Sweden)

    Willem de Lint

    2008-10-01

    Full Text Available Recently, within liberal democracies, the post-Westphalian consolidation of security and intelligence has ushered in the normalization not only of security in ‘securitization’ but also of intelligence in what is proposed here as ‘intelligencification.’ In outlining the features of intelligencified governance, my aim is to interrogate the view that effects or traces, and productivity rather than negation is as persuasive as commonly thought by the constructivists. After all, counter-intelligence is both about purging and reconstructing the archive for undisclosed values. In practice, what is being normalized is the authorized and legalized use of release and retention protocols of politically actionable information. The intelligencification of governmentality affords a sovereignty shell-game or the instrumentalization of sovereign power by interests that are dependent on, yet often inimical to, the power of state, national, and popular sovereignty. On voit le politique et le social comme dépendant de contingences exclusives. Récemment, au sein des démocraties libérales, la consolidation de la sécurité et des services de renseignements de sécurité qui a suivi les traités de la Westphalie a donné lieu à la normalisation non seulement de la sécurité en «sécurisation» mais aussi des services de renseignements de sécurité en ce qui est proposé ici comme «intelligencification» [terme anglais créé par l’auteur, dérivé du mot anglais «intelligence» dans le sens de renseignements des écurité]. En particulier, ce que l’on normalise dans le but de contourner des contingences exclusives est l’utilisation autorisée et légalisée de protocoles de communication et de rétention d’information qui, politiquement, pourrait mener à des poursuites. En esquissant les traits de la gouvernance «intelligencifiée», mon but est d’interroger le point de vue que les effets ou les traces, et la productivité plutôt que la

  14. Pathogen intelligence

    Directory of Open Access Journals (Sweden)

    Michael eSteinert

    2014-01-01

    Full Text Available Different species inhabit different sensory worlds and thus have evolved diverse means of processing information, learning and memory. In the escalated arms race with host defense, each pathogenic bacterium not only has evolved its individual cellular sensing and behaviour, but also collective sensing, interbacterial communication, distributed information processing, joint decision making, dissociative behaviour, and the phenotypic and genotypic heterogeneity necessary for epidemiologic success. Moreover, pathogenic populations take advantage of dormancy strategies and rapid evolutionary speed, which allow them to save co-generated intelligent traits in a collective genomic memory. This review discusses how these mechanisms add further levels of complexity to bacterial pathogenicity and transmission, and how mining for these mechanisms could help to develop new anti-infective strategies.

  15. Intelligent Routines

    CERN Document Server

    Anastassiou, George A

    Intelligent Routines II: Solving Linear Algebra and Differential Geometry with Sage” contains numerous of examples and problems as well as many unsolved problems. This book extensively applies the successful software Sage, which can be found free online http://www.sagemath.org/. Sage is a recent and popular software for mathematical computation, available freely and simple to use. This book is useful to all applied scientists in mathematics, statistics and engineering, as well for late undergraduate and graduate students of above subjects. It is the first such book in solving symbolically with Sage problems in Linear Algebra and Differential Geometry. Plenty of SAGE applications are given at each step of the exposition.

  16. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  17. Intelligence: Real or artificial?

    OpenAIRE

    Schlinger, Henry D.

    1992-01-01

    Throughout the history of the artificial intelligence movement, researchers have strived to create computers that could simulate general human intelligence. This paper argues that workers in artificial intelligence have failed to achieve this goal because they adopted the wrong model of human behavior and intelligence, namely a cognitive essentialist model with origins in the traditional philosophies of natural intelligence. An analysis of the word “intelligence” suggests that it originally r...

  18. A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

    Directory of Open Access Journals (Sweden)

    Fei Ding

    2016-01-01

    Full Text Available A smart home gateway plays an important role in the Internet of Things (IoT system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integrated access gateway (IAGW is proposed in this paper which upward connects with the operator machine-to-machine platform (M2M P/F. In this home network scheme, the gateway provides standard interfaces for supporting various applications in home environments, ranging from on-site configuration to node and service access. In addition, communication management ability is also provided by M2M P/F. A testbed of a simple home network application system that includes the IAGW prototype is created to test its user interaction capabilities. Experimental results show that the proposed gateway provides significant flexibility for users to configure and deploy a home automation network; it can be applied to other monitoring areas and simultaneously supports a multi-ubiquitous sensor network.

  19. A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

    Science.gov (United States)

    Shao, Minggang

    2017-01-01

    This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly. PMID:29204258

  20. A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

    Directory of Open Access Journals (Sweden)

    Kai Guan

    2017-01-01

    Full Text Available This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly’s electrocardiogram (ECG and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly.

  1. A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway.

    Science.gov (United States)

    Guan, Kai; Shao, Minggang; Wu, Shuicai

    2017-01-01

    This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly.

  2. Development of a software tool using deterministic logic for the optimization of cochlear implant processor programming.

    Science.gov (United States)

    Govaerts, Paul J; Vaerenberg, Bart; De Ceulaer, Geert; Daemers, Kristin; De Beukelaer, Carina; Schauwers, Karen

    2010-08-01

    An intelligent agent, Fitting to Outcomes eXpert, was developed to optimize and automate Cochlear implant (CI) programming. The current article describes the rationale, development, and features of this tool. Cochlear implant fitting is a time-consuming procedure to define the value of a subset of the available electric parameters based primarily on behavioral responses. It is comfort-driven with high intraindividual and interindividual variability both with respect to the patient and to the clinician. Its validity in terms of process control can be questioned. Good clinical practice would require an outcome-driven approach. An intelligent agent may help solve the complexity of addressing more electric parameters based on a range of outcome measures. A software application was developed that consists of deterministic rules that analyze the map settings in the processor together with psychoacoustic test results (audiogram, A(section sign)E phoneme discrimination, A(section sign)E loudness scaling, speech audiogram) obtained with that map. The rules were based on the daily clinical practice and the expertise of the CI programmers. The data transfer to and from this agent is either manual or through seamless digital communication with the CI fitting database and the psychoacoustic test suite. It recommends and executes modifications to the map settings to improve the outcome. Fitting to Outcomes eXpert is an operational intelligent agent, the principles of which are described. Its development and modes of operation are outlined, and a case example is given. Fitting to Outcomes eXpert is in use for more than a year now and seems to be capable to improve the measured outcome. It is argued that this novel tool allows a systematic approach focusing on outcome, reducing the fitting time, and improving the quality of fitting. It introduces principles of artificial intelligence in the process of CI fitting.

  3. Fundamental physics issues of multilevel logic in developing a parallel processor.

    Science.gov (United States)

    Bandyopadhyay, Anirban; Miki, Kazushi

    2007-06-01

    In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.

  4. First level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

  5. A dedicated line-processor as used at the SHF

    International Nuclear Information System (INIS)

    Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

    1985-01-01

    A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

  6. First-level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

  7. Smart metering gateway works as Smart Home Energy Manager; Smart Metering Gateway als Smart Home Energy Manager

    Energy Technology Data Exchange (ETDEWEB)

    Walter, Klaus-Dieter [SSV Software Systems GmbH, Hannover (Germany)

    2011-07-01

    The installation of smart meters together with real time consumption data visualization doesn't help to save energy CO2 emissions. With regards to refinancing options, the situation in Germany has been quite different since the middle of last year for buildings equipped with a photovoltaic system. If a heat pump system is also present, intelligent energy use in conjunction with smart meters can save considerable amounts of money. A Smart Home Energy Manager (SHEM) automates the energy saving. (orig.)

  8. Novel memory architecture for video signal processor

    Science.gov (United States)

    Hung, Jen-Sheng; Lin, Chia-Hsing; Jen, Chein-Wei

    1993-11-01

    An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.

  9. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  10. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  11. Preventing Precipitation in the ISS Urine Processor

    Science.gov (United States)

    Muirhead, Dean; Carter, Layne; Williamson, Jill; Chambers, Antja

    2017-01-01

    The ISS Urine Processor Assembly (UPA) was initially designed to achieve 85% recovery of water from pretreated urine on ISS. Pretreated urine is comprised of crew urine treated with flush water, an oxidant (chromium trioxide), and an inorganic acid (sulfuric acid) to control microbial growth and inhibit precipitation. Unfortunately, initial operation of the UPA on ISS resulted in the precipitation of calcium sulfate at 85% recovery. This occurred because the calcium concentration in the crew urine was elevated in microgravity due to bone loss. The higher calcium concentration precipitated with sulfate from the pretreatment acid, resulting in a failure of the UPA due to the accumulation of solids in the Distillation Assembly. Since this failure, the UPA has been limited to a reduced recovery of water from urine to prevent calcium sulfate from reaching the solubility limit. NASA personnel have worked to identify a solution that would allow the UPA to return to a nominal recovery rate of 85%. This effort has culminated with the development of a pretreatment based on phosphoric acid instead of sulfuric acid. By eliminating the sulfate associated with the pretreatment, the brine can be concentrated to a much higher concentration before calcium sulfate reach the solubility limit. This paper summarizes the development of this pretreatment and the testing performed to verify its implementation on ISS.

  12. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  13. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  14. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  15. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    Science.gov (United States)

    Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

    2018-02-01

    We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

  16. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    Directory of Open Access Journals (Sweden)

    Hristov Ivan

    2018-01-01

    Full Text Available We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP” in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL. The results show 2 times better performance on KNL processor.

  17. Adolescents and Young Adults' Perceptions of Electronic Cigarettes as a Gateway to Smoking: A Qualitative Study in Switzerland

    Science.gov (United States)

    Akre, Christina; Suris, Joan-Carles

    2017-01-01

    Electronic cigarettes (ECs) acting as a gateway to smoking traditional cigarettes (TCs) is a growing public health concern of EC use among youths. To gather the opinions and perceptions of adolescents and young adults (AYAs) on whether and how EC can act as a gateway to smoking TC among youths. A qualitative method included 42 AYAs. Participants…

  18. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Kazimierz Wiatr

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  19. Science gateways for distributed computing infrastructures development framework and exploitation by scientific user communities

    CERN Document Server

    Kacsuk, Péter

    2014-01-01

    The book describes the science gateway building technology developed in the SCI-BUS European project and its adoption and customization method, by which user communities, such as biologists, chemists, and astrophysicists, can build customized, domain-specific science gateways. Many aspects of the core technology are explained in detail, including its workflow capability, job submission mechanism to various grids and clouds, and its data transfer mechanisms among several distributed infrastructures. The book will be useful for scientific researchers and IT professionals engaged in the develop

  20. The home gateway used in FTTH which can implement triple play

    Science.gov (United States)

    Ji, Wei; Yang, Hongliang; Liu, Yang; Liu, Yonghui; Cui, Wei

    2008-11-01

    The paper proposes the design of Home Gateway used in FTTH. On the customer's side, the Home Gateway finishes the optical signal receiving, provides three kinds of interfaces for the video, voice data, and attains the integration of the three services. PAS6301 chip achieves the control of voice, video and data services. Especially on the aspect of the video services, the HG system combines the advantages of IPTV and the DVB to offer a platform for receiving two signals. Users can use ordinary TV to receive both digital TV programs encoded by MPEG-2 and IPTV programs encoded by H.264.

  1. Access for Internet of Things using Smartphone as a Gateway utilizing LTE and WiFi

    DEFF Research Database (Denmark)

    Mathur, Prateek; Nielsen, Rasmus Hjorth; Prasad, Neeli R.

    2016-01-01

    Communicating the Internet of Things (IoT) data relying on Long-Term Evolution (LTE) and WiFi has been been presented in the relevant literature. However, this necessitates devices to have LTE/WiFi capability of their own, that has limitations in the form of power consumption, and radio access...... the data to the Internet. In this paper we present a system model wherein the smartphone functions as a gateway for the IoT devices operating on NFC, ZigBee and Bluetooth. The smartphone functioning as a gateway for transferring IoT data. The system modelled in the form of a Markov Chain based...

  2. Educational Programs for Intelligence Professionals.

    Science.gov (United States)

    Miller, Jerry P.

    1994-01-01

    Discusses the need for education programs for competitive intelligence professionals. Highlights include definitions of intelligence functions, focusing on business intelligence; information utilization by decision makers; information sources; competencies for intelligence professionals; and the development of formal education programs. (38…

  3. A New Dimension of Business Intelligence: Location-based Intelligence

    OpenAIRE

    Zeljko Panian

    2012-01-01

    Through the course of this paper we define Locationbased Intelligence (LBI) which is outgrowing from process of amalgamation of geolocation and Business Intelligence. Amalgamating geolocation with traditional Business Intelligence (BI) results in a new dimension of BI named Location-based Intelligence. LBI is defined as leveraging unified location information for business intelligence. Collectively, enterprises can transform location data into business intelligence applic...

  4. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Directory of Open Access Journals (Sweden)

    Seung-Ho Ok

    2017-02-01

    Full Text Available Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV, three-dimensional (3D stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  5. Molecular processors: from qubits to fuzzy logic.

    Science.gov (United States)

    Gentili, Pier Luigi

    2011-03-14

    Single molecules or their assemblies are information processing devices. Herein it is demonstrated how it is possible to process different types of logic through molecules. As long as decoherent effects are maintained far away from a pure quantum mechanical system, quantum logic can be processed. If the collapse of superimposed or entangled wavefunctions is unavoidable, molecules can still be used to process either crisp (binary or multi-valued) or fuzzy logic. The way for implementing fuzzy inference engines is declared and it is supported by the examples of molecular fuzzy logic systems devised so far. Fuzzy logic is drawing attention in the field of artificial intelligence, because it models human reasoning quite well. This ability may be due to some structural analogies between a fuzzy logic system and the human nervous system. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Reconfigurable VLIW Processor for Software Defined Radio, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  7. Detailed algorithmic description of a processor: a recipe for ...

    African Journals Online (AJOL)

    International Journal of Natural and Applied Sciences ... a simple developed compiler could generate the code of a simple programming language. ... It should be noted that such code generation must be done on a particular processor- for ...

  8. Analysis of Intel IA-64 Processor Support for Secure Systems

    National Research Council Canada - National Science Library

    Unalmis, Bugra

    2001-01-01

    .... Systems could be constructed for which serious security threats would be eliminated. This thesis explores the Intel IA-64 processor's hardware support and its relationship to software for building a secure system...

  9. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  10. Optical backplane interconnect switch for data processors and computers

    Science.gov (United States)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  11. High-speed packet filtering utilizing stream processors

    Science.gov (United States)

    Hummel, Richard J.; Fulp, Errin W.

    2009-04-01

    Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

  12. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  13. Huffman-based code compression techniques for embedded processors

    KAUST Repository

    Bonny, Mohamed Talal; Henkel, Jö rg

    2010-01-01

    % for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.

  14. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  15. Particle simulation on a distributed memory highly parallel processor

    International Nuclear Information System (INIS)

    Sato, Hiroyuki; Ikesaka, Morio

    1990-01-01

    This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

  16. Radiation Tolerant Software Defined Video Processor, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  17. Assembly processor program converts symbolic programming language to machine language

    Science.gov (United States)

    Pelto, E. V.

    1967-01-01

    Assembly processor program converts symbolic programming language to machine language. This program translates symbolic codes into computer understandable instructions, assigns locations in storage for successive instructions, and computer locations from symbolic addresses.

  18. Intelligent Extruder

    Energy Technology Data Exchange (ETDEWEB)

    AlperEker; Mark Giammattia; Paul Houpt; Aditya Kumar; Oscar Montero; Minesh Shah; Norberto Silvi; Timothy Cribbs

    2003-04-24

    ''Intelligent Extruder'' described in this report is a software system and associated support services for monitoring and control of compounding extruders to improve material quality, reduce waste and energy use, with minimal addition of new sensors or changes to the factory floor system components. Emphasis is on process improvements to the mixing, melting and de-volatilization of base resins, fillers, pigments, fire retardants and other additives in the :finishing'' stage of high value added engineering polymer materials. While GE Plastics materials were used for experimental studies throughout the program, the concepts and principles are broadly applicable to other manufacturers materials. The project involved a joint collaboration among GE Global Research, GE Industrial Systems and Coperion Werner & Pleiderer, USA, a major manufacturer of compounding equipment. Scope of the program included development of a algorithms for monitoring process material viscosity without rheological sensors or generating waste streams, a novel detection scheme for rapid detection of process upsets and an adaptive feedback control system to compensate for process upsets where at line adjustments are feasible. Software algorithms were implemented and tested on a laboratory scale extruder (50 lb/hr) at GE Global Research and data from a production scale system (2000 lb/hr) at GE Plastics was used to validate the monitoring and detection software. Although not evaluated experimentally, a new concept for extruder process monitoring through estimation of high frequency drive torque without strain gauges is developed and demonstrated in simulation. A plan to commercialize the software system is outlined, but commercialization has not been completed.

  19. Klimanavigator - Climate Navigator - Gateway to climate knowledge in Germany

    Science.gov (United States)

    Schuck-Zöller, Susanne

    2013-04-01

    Objective More than 50 German research institutions and networks are represented on www.klimanavigator.de, a common platform, where information about their work, and the latest findings from climate research and adaptation can be found. Thus Klimanavigator as a gateway to climate knowledge provides a information portal for those who have to respond to climate change. The internet portal gives an overview of the present state of research and is estimated as a decision support tool for appropriate mitigation and adaptation measures. Target Groups The portal collects the German climate research institutions to publish their scientific knowledge in a non-scientific language. Economists, policymakers, administration and the media are bound to find the names of scientific experts and institutions by an elaborated research tool. Methodology The chapter "Dossiers" is edited by the Klimanavigator-Coordinator CSC. It gathers information to a special issue looked upon from various points of view. Publications of outstanding German scientists are presented side by side, current knowledge is being synthesized, scientifically reviewed and disseminated. The latest news from climate and adaptation research is presented in an own chapter, dedicated to the press releases of the portal members. Via RSS-feed the press releases are collected from the different partner institutions. Thirdly, portraits of the member institutions, that are individually edited by themselves, draw a map of science in Germany and help to find appropriate cooperation partners. For the future further development is being planned. Common Management Klimanavigator is being managed by the partners in common. The main decisions concerning the concept and shape of the portal are made by the partners' assembly. An elected editorial committee decides about the content between the assemblies. The Climate Service Center (part of the Helmholtz-Zentrum Geesthacht) concentrates on facilitating the cooperation, and

  20. NERIES: Seismic Data Gateways and User Composed Datasets Metadata Management

    Science.gov (United States)

    Spinuso, Alessandro; Trani, Luca; Kamb, Linus; Frobert, Laurent

    2010-05-01

    One of the NERIES EC project main objectives is to establish and improve the networking of seismic waveform data exchange and access among four main data centers in Europe: INGV, GFZ, ORFEUS and IPGP. Besides the implementation of the data backbone, several investigations and developments have been conducted in order to offer to the users the data available from this network, either programmatically or interactively. One of the challenges is to understand how to enable users` activities such as discovering, aggregating, describing and sharing datasets to obtain a decrease in the replication of similar data queries towards the network, exempting the data centers to guess and create useful pre-packed products. We`ve started to transfer this task more and more towards the users community, where the users` composed data products could be extensively re-used. The main link to the data is represented by a centralized webservice (SeismoLink) acting like a single access point to the whole data network. Users can download either waveform data or seismic station inventories directly from their own software routines by connecting to this webservice, which routes the request to the data centers. The provenance of the data is maintained and transferred to the users in the form of URIs, that identify the dataset and implicitly refer to the data provider. SeismoLink, combined with other webservices (eg EMSC-QuakeML earthquakes catalog service), is used from a community gateway such as the NERIES web portal (http://www.seismicportal.eu). Here the user interacts with a map based portlet which allows the dynamic composition of a data product, binding seismic event`s parameters with a set of seismic stations. The requested data is collected by the back-end processes of the portal, preserved and offered to the user in a personal data cart, where metadata can be generated interactively on-demand. The metadata, expressed in RDF, can also be remotely ingested. They offer rating

  1. Intelligent Home Control System Based on ARM10

    Science.gov (United States)

    Chen, G. X.; Jiang, J.; Zhong, L. H.

    2017-10-01

    Intelligent home is becoming the hot spot of social attention in the 21st century. When it is in China, it is a really new industry. However, there is no doubt that Intelligent home will become a new economic growth point of social development; it will change the life-style of human being. To develop the intelligent home, we should keep up with the development trend of technology. This is the reason why I talk about the intelligent home control system here. In this paper, intelligent home control system is designed for alarm and remote control on gas- leaking, fire disaster, earthquake prediction, etc., by examining environmental changes around house. When the Intelligent home control system has detected an accident occurs, the processor will communicate with the GSM module, informing the house keeper the occurrence of accident. User can receive and send the message to the system to cut the power by mobile phone. The system can get access to DCCthrough ARM10 JTAG interface, using DCC to send and receive messages. At the same time, the debugger on the host is mainly used to receive the user’s command and send it to the debug component in the target system. The data that returned from the target system is received and displayed to the user in a certain format.

  2. Suboptimal processor for anomaly detection for system surveillance and diagnosis

    Energy Technology Data Exchange (ETDEWEB)

    Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van

    1989-06-01

    Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.

  3. Reducing Competitive Cache Misses in Modern Processor Architectures

    OpenAIRE

    Prisagjanec, Milcho; Mitrevski, Pece

    2017-01-01

    The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This tec...

  4. UA1 upgrade first-level calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

    1989-01-01

    A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

  5. GA103: A microprogrammable processor for online filtering

    International Nuclear Information System (INIS)

    Calzas, A.; Danon, G.; Bouquet, B.

    1981-01-01

    GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)

  6. 16-Bit RISC Processor Design for Convolution Application

    OpenAIRE

    Anand Nandakumar Shardul

    2013-01-01

    In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

  7. IKT-Gateway as a bridge between dual-purpose power plant and smart grid; IKT-Gateway als Bruecke zwischen BHKW und Smart Grid

    Energy Technology Data Exchange (ETDEWEB)

    Neumann, Joerg [SSV Software Systems GmbH, Hannover (Germany). Bereich Vertrieb und Marketing

    2012-07-15

    The way to a smart grid leads via the interconnection of distributed energy producers and consumers. Within the total network, energy producers and consumers have to communicate meaningfully with each other. This is a great performance for a reliable and performant long-distance service. In the case of 2G Energietechnik AG (Heek, Federal Republic of Germany), SSV Software Systems GmbH (Hannover, Federal Republic of Germany) has met this challenge with an ICT-based gateway solution mastered.

  8. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  9. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  10. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  11. Intelligent Mission Controller Node

    National Research Council Canada - National Science Library

    Perme, David

    2002-01-01

    The goal of the Intelligent Mission Controller Node (IMCN) project was to improve the process of translating mission taskings between real-world Command, Control, Communications, Computers, and Intelligence (C41...

  12. Algorithms in ambient intelligence

    NARCIS (Netherlands)

    Aarts, E.H.L.; Korst, J.H.M.; Verhaegh, W.F.J.; Verhaegh, W.F.J.; Aarts, E.H.L.; Korst, J.H.M.

    2004-01-01

    In this chapter, we discuss the new paradigm for user-centered computing known as ambient intelligence and its relation with methods and techniques from the field of computational intelligence, including problem solving, machine learning, and expert systems.

  13. Advanced intelligent systems

    CERN Document Server

    Ryoo, Young; Jang, Moon-soo; Bae, Young-Chul

    2014-01-01

    Intelligent systems have been initiated with the attempt to imitate the human brain. People wish to let machines perform intelligent works. Many techniques of intelligent systems are based on artificial intelligence. According to changing and novel requirements, the advanced intelligent systems cover a wide spectrum: big data processing, intelligent control, advanced robotics, artificial intelligence and machine learning. This book focuses on coordinating intelligent systems with highly integrated and foundationally functional components. The book consists of 19 contributions that features social network-based recommender systems, application of fuzzy enforcement, energy visualization, ultrasonic muscular thickness measurement, regional analysis and predictive modeling, analysis of 3D polygon data, blood pressure estimation system, fuzzy human model, fuzzy ultrasonic imaging method, ultrasonic mobile smart technology, pseudo-normal image synthesis, subspace classifier, mobile object tracking, standing-up moti...

  14. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  15. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  16. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  17. A UNIX-based prototype biomedical virtual image processor

    International Nuclear Information System (INIS)

    Fahy, J.B.; Kim, Y.

    1987-01-01

    The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

  18. A digital retina-like low-level vision processor.

    Science.gov (United States)

    Mertoguno, S; Bourbakis, N G

    2003-01-01

    This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

  19. Air-Lubricated Thermal Processor For Dry Silver Film

    Science.gov (United States)

    Siryj, B. W.

    1980-09-01

    Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

  20. Artificial Intelligence Project

    Science.gov (United States)

    1990-01-01

    Symposium on Aritificial Intelligence and Software Engineering Working Notes, March 1989. Blumenthal, Brad, "An Architecture for Automating...Artificial Intelligence Project Final Technical Report ARO Contract: DAAG29-84-K-OGO Artificial Intelligence LaboratO"ry The University of Texas at...Austin N>.. ~ ~ JA 1/I 1991 n~~~ Austin, Texas 78712 ________k A,.tificial Intelligence Project i Final Technical Report ARO Contract: DAAG29-84-K-0060

  1. Intelligent computational systems for space applications

    Science.gov (United States)

    Lum, Henry; Lau, Sonie

    Intelligent computational systems can be described as an adaptive computational system integrating both traditional computational approaches and artificial intelligence (AI) methodologies to meet the science and engineering data processing requirements imposed by specific mission objectives. These systems will be capable of integrating, interpreting, and understanding sensor input information; correlating that information to the "world model" stored within its data base and understanding the differences, if any; defining, verifying, and validating a command sequence to merge the "external world" with the "internal world model"; and, controlling the vehicle and/or platform to meet the scientific and engineering mission objectives. Performance and simulation data obtained to date indicate that the current flight processors baselined for many missions such as Space Station Freedom do not have the computational power to meet the challenges of advanced automation and robotics systems envisioned for the year 2000 era. Research issues which must be addressed to achieve greater than giga-flop performance for on-board intelligent computational systems have been identified, and a technology development program has been initiated to achieve the desired long-term system performance objectives.

  2. Orchestrating Multiple Intelligences

    Science.gov (United States)

    Moran, Seana; Kornhaber, Mindy; Gardner, Howard

    2006-01-01

    Education policymakers often go astray when they attempt to integrate multiple intelligences theory into schools, according to the originator of the theory, Howard Gardner, and his colleagues. The greatest potential of a multiple intelligences approach to education grows from the concept of a profile of intelligences. Each learner's intelligence…

  3. Algorithms in ambient intelligence

    NARCIS (Netherlands)

    Aarts, E.H.L.; Korst, J.H.M.; Verhaegh, W.F.J.; Weber, W.; Rabaey, J.M.; Aarts, E.

    2005-01-01

    We briefly review the concept of ambient intelligence and discuss its relation with the domain of intelligent algorithms. By means of four examples of ambient intelligent systems, we argue that new computing methods and quantification measures are needed to bridge the gap between the class of

  4. Designing with computational intelligence

    CERN Document Server

    Lopes, Heitor; Mourelle, Luiza

    2017-01-01

    This book discusses a number of real-world applications of computational intelligence approaches. Using various examples, it demonstrates that computational intelligence has become a consolidated methodology for automatically creating new competitive solutions to complex real-world problems. It also presents a concise and efficient synthesis of different systems using computationally intelligent techniques.

  5. Reflection on robotic intelligence

    NARCIS (Netherlands)

    Bartneck, C.

    2006-01-01

    This paper reflects on the development or robots, both their physical shape as well as their intelligence. The later strongly depends on the progress made in the artificial intelligence (AI) community which does not yet provide the models and tools necessary to create intelligent robots. It is time

  6. High-speed special-purpose processor for event selection by number of direct tracks

    International Nuclear Information System (INIS)

    Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.

    1986-01-01

    A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits

  7. Linking Gateway Technical College with Workforce Development: The SC Johnson-A Family Company Story.

    Science.gov (United States)

    Knudson, Edward

    2004-01-01

    Seven years ago, SC Johnson--A Family Company approached Gateway Technical College with a need to further strengthen their incumbent workforce's technical training and education. Retirements, brain drain, and competition for technical expertise were the forces driving SC Johnson to develop a comprehensive, flexible, and timely workplace education…

  8. A Gateway((R)) -compatible bacterial adenylate cyclase-based two-hybrid system

    Czech Academy of Sciences Publication Activity Database

    Ouellette, S. P.; Gauliard, E.; Antošová, Zuzana; Ladant, D.

    2014-01-01

    Roč. 6, č. 3 (2014), s. 259-267 ISSN 1758-2229 Institutional support: RVO:67985823 Keywords : bacterial two-hybrid system * protein–protein interactions * cell division * Gateway((R))(GW) cloning system Subject RIV: EE - Microbiology, Virology Impact factor: 3.293, year: 2014

  9. RESTful M2M Gateway for Remote Wireless Monitoring for District Central Heating Networks

    Directory of Open Access Journals (Sweden)

    Bo Cheng

    2014-11-01

    Full Text Available In recent years, the increased interest in energy conservation and environmental protection, combined with the development of modern communication and computer technology, has resulted in the replacement of distributed heating by central heating in urban areas. This paper proposes a Representational State Transfer (REST Machine-to-Machine (M2M gateway for wireless remote monitoring for a district central heating network. In particular, we focus on the resource-oriented RESTful M2M gateway architecture, and present an uniform devices abstraction approach based on Open Service Gateway Initiative (OSGi technology, and implement the resource mapping mechanism between resource address mapping mechanism between RESTful resources and the physical sensor devices, and present the buffer queue combined with polling method to implement the data scheduling and Quality of Service (QoS guarantee, and also give the RESTful M2M gateway open service Application Programming Interface (API set. The performance has been measured and analyzed. Finally, the conclusions and future work are presented.

  10. Prioritizing Active Learning: An Exploration of Gateway Courses in Political Science

    Science.gov (United States)

    Archer, Candace C.; Miller, Melissa K.

    2011-01-01

    Prior research in political science and other disciplines demonstrates the pedagogical and practical benefits of active learning. Less is known, however, about the extent to which active learning is used in political science classrooms. This study assesses the prioritization of active learning in "gateway" political science courses, paying…

  11. Tackling the complexity of residential gateways in an unbundling value chain

    NARCIS (Netherlands)

    Hartog, F.T.H. den; Baken, N.H.G.; Keyson, D.V.; Kwaaitaal, J.J.B.; Snijders, W.A.M.

    2004-01-01

    Various crucial multi-disciplinary issues have been investigated concerning residential gateway (RG) technology applicable in an unbundled telecommunications value chain. We find that the Calculating-with-Concepts method can be used to construct an unambiguous frame of reference for digital rights

  12. Response of Mediterranean circulation to Miocene shoaling and closure of the Indian Gateway : A model study

    NARCIS (Netherlands)

    De La Vara, Alba; Meijer, Paul

    2016-01-01

    In this regional ocean model study, we explore the effect of the Early to Middle Miocene shoaling and closure of the Indian Gateway on Mediterranean circulation and its exchange with the adjacent oceans. For this we use the regional ocean circulation model "sbPOM" and a collection of bathymetries

  13. From the Adam Smith Institute to the Zapatistas: An Internet Gateway to all Development Knowledge.

    Science.gov (United States)

    Wilks, Alex

    2002-01-01

    Examines the World Bank Internet initiative, the Development Gateway. Describes the importance of the Bank as a knowledge bank and the threats posed by the Internet to its near monopoly of development thinking. Argues that the initiative reveals biases and misunderstandings in the World Bank's approach to knowledge for development. (CAJ)

  14. Factors Affecting Student Academic Success in Gateway Courses at Northern Arizona University

    Science.gov (United States)

    Benford, Russell; Gess-Newsome, Julie

    2006-01-01

    Students in gateway business, math, and science courses at Northern Arizona University receive non-passing grades (grades of D, F, and W) at high rates. To identify possible trends in demographic groups that receive DFWs and to investigate why students receive DFWs in these courses, a student survey was administered to 719 students in 7 gateway…

  15. Remote Agriculture Automation using Wireless Link and IoT Gateway Infrastructure

    DEFF Research Database (Denmark)

    Nakutis, Z.; Deksnys, V.; Jaurusevicius, I.

    2015-01-01

    processing and control algorithms that produce control stimulus are executed in the gateway. This approach features the advantage of convenient possibilities to change control rules from Cloud services (installing or configuring process controller) without updating firmware of remote sensors...... benefit from the proposed architecture are identified....

  16. A Squandered Resource: The Divestment of Mexican Parental Involvement in a New Gateway State

    Science.gov (United States)

    Petrone, Eleanor

    2016-01-01

    Parental involvement plays an important role in the academic success of children. Schools in new gateway states where there has not been a longstanding tradition of immigration often lack the cultural knowledge and linguistic resources necessary to serve immigrant youth and their families effectively. By examining the experiences of Mexican…

  17. Direct Characterization of Comets and Asteroids via Cosmic Dust Analysis from the Deep Space Gateway

    Science.gov (United States)

    Fries, M.; Fisher, K.

    2018-02-01

    The Deep Space Gateway can allow direct analysis of dust from over a dozen comets, using an instrument similar to the successful Cassini Dust Analyzer (CDA). Long-term measurements are preferred. Compositions of over a dozen asteroids and comets can be obtained.

  18. The NC3Rs gateway: Accelerating scientific discoveries with new 3Rs models and technologies.

    Science.gov (United States)

    Percie du Sert, Nathalie; Robinson, Vicky

    2018-01-01

    This editorial introduces the NC3Rs gateway, which publishes articles and reviews on new models and technologies emerging from NC3Rs-funded research. The aim is to raise awareness about these approaches, increase confidence in their capability, and provide sufficient information to facilitate their uptake by others.

  19. A Standard-Based and Context-Aware Architecture for Personal Healthcare Smart Gateways.

    Science.gov (United States)

    Santos, Danilo F S; Gorgônio, Kyller C; Perkusich, Angelo; Almeida, Hyggo O

    2016-10-01

    The rising availability of Personal Health Devices (PHDs) capable of Personal Network Area (PAN) communication and the desire of keeping a high quality of life are the ingredients of the Connected Health vision. In parallel, a growing number of personal and portable devices, like smartphones and tablet computers, are becoming capable of taking the role of health gateway, that is, a data collector for the sensor PHDs. However, as the number of PHDs increase, the number of other peripherals connected in PAN also increases. Therefore, PHDs are now competing for medium access with other devices, decreasing the Quality of Service (QoS) of health applications in the PAN. In this article we present a reference architecture to prioritize PHD connections based on their state and requirements, creating a healthcare Smart Gateway. Healthcare context information is extracted by observing the traffic through the gateway. A standard-based approach was used to identify health traffic based on ISO/IEEE 11073 family of standards. A reference implementation was developed showing the relevance of the problem and how the proposed architecture can assist in the prioritization. The reference Smart Gateway solution was integrated with a Connected Health System for the Internet of Things, validating its use in a real case scenario.

  20. GATEWAY Demonstrations: OLED Lighting in the Offices of Aurora Lighting Design, Inc.

    Energy Technology Data Exchange (ETDEWEB)

    Miller, Naomi J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-03-31

    At the offices of Aurora Lighting Design, Inc., in Grayslake, IL, the GATEWAY program conducted its first investigation involving OLED lighting. The project experienced several challenges, but also highlighted a number of promising attributes – which indicate that with continued improvements in efficacy, longevity, size, and flexibility, OLEDs could provide a new tool for creative and effective lighting.

  1. All gates lead to smoking: the 'gateway theory', e-cigarettes and the remaking of nicotine.

    Science.gov (United States)

    Bell, Kirsten; Keane, Helen

    2014-10-01

    The idea that drug use in 'softer' forms leads to 'harder' drug use lies at the heart of the gateway theory, one of the most influential models of drug use of the twentieth century. Although hotly contested, the notion of the 'gateway drug' continues to rear its head in discussions of drug use--most recently in the context of electronic cigarettes. Based on a critical reading of a range of texts, including scholarly literature and media reports, we explore the history and gestation of the gateway theory, highlighting the ways in which intersections between academic, media and popular accounts actively produced the concept. Arguing that the theory has been critical in maintaining the distinction between 'soft' and 'hard' drugs, we turn to its distinctive iteration in the context of debates about e-cigarettes. We show that the notion of the 'gateway' has been transformed from a descriptive to a predictive model, one in which nicotine is constituted as simultaneously 'soft' and 'hard'--as both relatively innocuous and incontrovertibly harmful. Copyright © 2014 Elsevier Ltd. All rights reserved.

  2. Perceived Connections between Anti-Social Gateway Behaviors and School Bullying and Culture

    Science.gov (United States)

    Grell, Brett Stanley; Meyer, Richard C.

    2016-01-01

    The purpose of this study was to examine and compare opinions of 8th and 9th grade teachers and students regarding the prevalence of anti-social/gateway behaviors in their classrooms, the perceived connection between these behaviors and more traditional forms of bullying, and the potential impact of school-wide anti-bullying programs specifically…

  3. Global Lunar Topography from the Deep Space Gateway for Science and Exploration

    Science.gov (United States)

    Archinal, B.; Gaddis, L.; Kirk, R.; Edmundson, K.; Stone, T.; Portree, D.; Keszthelyi, L.

    2018-02-01

    The Deep Space Gateway, in low lunar orbit, could be used to achieve a long standing goal of lunar science, collecting stereo images in two months to make a complete, uniform, high resolution, known accuracy, global topographic model of the Moon.

  4. GATEWAY Demonstrations: Trial Demonstration of Area Lighting Retrofit, Yuma Border Patrol, Yuma, Arizona

    Energy Technology Data Exchange (ETDEWEB)

    Wilkerson, A. M. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); McCullough, J. J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2014-12-31

    Along the Yuma Sector Border Patrol Area in Yuma, Arizona, the GATEWAY program conducted a trial demonstration in which the incumbent quartz metal halide area lighting was replaced with LED at three pole locations at the Yuma Sector Border Patrol Area in Yuma, Arizona. The retrofit was documented to better understand LED technology performance in high-temperature environments.

  5. The Usage of Informational Gateways for Data Exchange between Personal Data Systems of Different Classes

    Directory of Open Access Journals (Sweden)

    E. I. Goncharov

    2010-03-01

    Full Text Available When personal data exchange between informational systems takes place, one must guarantee the systems are not integrating but just interacting. This task can not be accomplished by using traditional tools such as firewalls, cryptography and so on. To solve the problem we suggest deploying of informational gateway in personal data exchange process.

  6. Effective connectivity gateways to the Theory of Mind network in processing communicative intention.

    Science.gov (United States)

    Tettamanti, Marco; Vaghi, Matilde M; Bara, Bruno G; Cappa, Stefano F; Enrici, Ivan; Adenzato, Mauro

    2017-07-15

    An Intention Processing Network (IPN), involving the medial prefrontal cortex, precuneus, bilateral posterior superior temporal sulcus, and temporoparietal junctions, plays a fundamental role in comprehending intentions underlying action goals. In a previous fMRI study, we showed that, depending on the linguistic or extralinguistic (gestural) modality used to convey the intention, the IPN is complemented by activation of additional brain areas, reflecting distinct modality-specific input gateways to the IPN. These areas involve, for the linguistic modality, the left inferior frontal gyrus (LIFG), and for the extralinguistic modality, the right inferior frontal gyrus (RIFG). Here, we tested the modality-specific gateway hypothesis, by using DCM to measure inter-regional functional integration dynamics between the IPN and LIFG/RIFG gateways. We found strong evidence of a well-defined effective connectivity architecture mediating the functional integration between the IPN and the inferior frontal cortices. The connectivity dynamics indicate a modality-specific propagation of stimulus information from LIFG to IPN for the linguistic modality, and from RIFG to IPN for the extralinguistic modality. Thus, we suggest a functional model in which the modality-specific gateways mediate the structural and semantic decoding of the stimuli, and allow for the modality-specific communicative information to be integrated in Theory of Mind inferences elaborated through the IPN. Copyright © 2017 Elsevier Inc. All rights reserved.

  7. Exploration of Near-Earth Objects from the Deep Space Gateway

    Science.gov (United States)

    Dunham, D. W.; Stakkestad, K.; Vedder, P.; McAdams, J.; Horsewood, J.; Genova, A. L.

    2018-02-01

    The paper will show how clever use of orbital dynamics can lower delta-V costs to enable scientifically interesting missions. The high-energy Deep Space Gateway orbits can be used to reach NEOs, a trans node for crews, or to deploy small sats. Examples are given.

  8. The Divine Dreams of a Sample of South African Children: The Gateway to Their Spirituality

    Science.gov (United States)

    Potgieter, Ferdinand J.; van der Walt, Johannes L.; Wolhuter, Charl C.

    2009-01-01

    As part of a research project on religion, spirituality and education, the authors attended to the role that children's divine dreams could play in religious education (RE). They contend that such dreams can indeed be used by RE teachers as the gateway to understanding the spirituality of their learners. They defend their claim by firstly…

  9. Pre-Assessment and Peer Tutoring as Measures to Improve Performance in Gateway General Chemistry Classes

    Science.gov (United States)

    Allenbaugh, R. J.; Herrera, K. M.

    2014-01-01

    Determining student readiness for gateway chemistry courses and providing underprepared students effective remediation are important as student bodies are growing increasingly diverse in their precollege preparation. The effectiveness of the ACT Mathematics Test and the Whimbey Analytical Skills Inventory (WASI) in predicting student success in…

  10. “Puerto Rico: gateway to landscape” from an ecological perspective

    Science.gov (United States)

    Grizelle Gonzalez

    2015-01-01

    The exhibit Puerto Rico: Gateway to Landscape proposes to explore various ways in which citizens approach the landscape, or construct it – inside and outside the city – and considers city planning, the creation of parks and natural reserves, and their interpretation. From a perspective of citizen involvement, this thematic scaffolding related to landscape and the...

  11. GATEWAY Demonstrations: OLED Lighting in the Offices of DeJoy, Knauf & Blood, LLP

    Energy Technology Data Exchange (ETDEWEB)

    Miller, Naomi J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2017-07-24

    At the offices of the accounting firm of DeJoy, Knauf & Blood, LLP in Rochester, NY, the GATEWAY program evaluated a new lighting system that incorporates a number of different OLED luminaires. Evaluation of the OLED products included efficacy performance, field measurements of panel color, flicker measurements, and staff feedback.

  12. 78 FR 79707 - Notice of Public Meeting, Gateway West Project Subcommittee of the Boise District Resource...

    Science.gov (United States)

    2013-12-31

    ... Resource Advisory Council on matters of planning and management of the Gateway West Project (sections 8 and... Interior, through the BLM, on a variety of planning and management issues associated with public land... a telecommunications device for the deaf (TDD) may call the Federal Information Relay Service (FIRS...

  13. Marine gateway vs. fluvial stream within the Balkans from 6 to 5Ma

    NARCIS (Netherlands)

    Suc, Jean Pierre; Popescu, Speranta Maria; Do Couto, Damien; Clauzon, Georges; Rubino, Jean Loup; Melinte-Dobrinescu, Mihaela Carmen; Quillévéré, Frédéric; Brun, Jean Pierre; Dumurdžanov, Nikola; Zagorchev, Ivan; Lesić, Vesna; Tomić, Dragana; Sokoutis, Dimitrios; Meyer, Bertrand; Macaleţ, Rodica; Rifelj, Helena

    Since the discovery of calcareous nannofossils, dinoflagellate cysts and planktonic foraminifers in deposits from the Dacic Basin, intensive research has been performed in order to evidence which gateway this microplankton used to connect Paratethys and the Mediterranean prior and after the

  14. Flexible gateway constructs for functional analyses of genes in plant pathogenic fungi

    NARCIS (Netherlands)

    Mehrabi, Rahim; Mirzadi Gohari, Amir; Silva, da Gilvan Ferreira; Steinberg, Gero; Kema, Gert H.J.; Wit, de Pierre J.G.M.

    2015-01-01

    Genetic manipulation of fungi requires quick, low-cost, efficient, high-throughput and molecular tools. In this paper, we report 22 entry constructs as new molecular tools based on the Gateway technology facilitating rapid construction of binary vectors that can be used for functional analysis of

  15. Event detection intelligent camera development

    International Nuclear Information System (INIS)

    Szappanos, A.; Kocsis, G.; Molnar, A.; Sarkozi, J.; Zoletnik, S.

    2008-01-01

    A new camera system 'event detection intelligent camera' (EDICAM) is being developed for the video diagnostics of W-7X stellarator, which consists of 10 distinct and standalone measurement channels each holding a camera. Different operation modes will be implemented for continuous and for triggered readout as well. Hardware level trigger signals will be generated from real time image processing algorithms optimized for digital signal processor (DSP) and field programmable gate array (FPGA) architectures. At full resolution a camera sends 12 bit sampled 1280 x 1024 pixels with 444 fps which means 1.43 Terabyte over half an hour. To analyse such a huge amount of data is time consuming and has a high computational complexity. We plan to overcome this problem by EDICAM's preprocessing concepts. EDICAM camera system integrates all the advantages of CMOS sensor chip technology and fast network connections. EDICAM is built up from three different modules with two interfaces. A sensor module (SM) with reduced hardware and functional elements to reach a small and compact size and robust action in harmful environment as well. An image processing and control unit (IPCU) module handles the entire user predefined events and runs image processing algorithms to generate trigger signals. Finally a 10 Gigabit Ethernet compatible image readout card functions as the network interface for the PC. In this contribution all the concepts of EDICAM and the functions of the distinct modules are described

  16. THOR Fields and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Ahlen, Lennart; Balikhin, Michael; Carr, Christopher; Dekkali, Moustapha; Khotyaintsev, Yuri; Lan, Radek; Magnes, Werner; Morawski, Marek; Nakamura, Rumi; Uhlir, Ludek; Yearby, Keith; Winkler, Marek; Zaslavsky, Arnaud

    2017-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first spacecraft mission dedicated to the study of plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all THOR fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer, and search-coil magnetometer (SCM), and perform signal digitization and on-board data processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The scientific value of highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation will further improve on this heritage. Large dynamic range of the instruments will be complemented by a thorough electromagnetic cleanliness program, which will prevent perturbation of field measurements by interference from payload and platform subsystems. Taking advantage of the capabilities of modern electronics and the large telemetry bandwidth of THOR, FWP will provide multi-component electromagnetic field waveforms and spectral data products at a high time resolution. Fully synchronized sampling of many signals will allow to resolve wave phase information and estimate wavelength via interferometric correlations between EFI probes. FWP will also implement a plasma resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will rapidly transmit information about magnetic field vector and spacecraft potential to the

  17. Intelligent trigger by massively parallel processors for high energy physics experiments

    International Nuclear Information System (INIS)

    Rohrbach, F.; Vesztergombi, G.

    1992-01-01

    The CERN-MPPC collaboration concentrates its effort on the development of machines based on massive parallelism with thousands of integrated processing elements, arranged in a string. Seven applications are under detailed studies within the collaboration: three for LHC, one for SSC, two for fixed target high energy physics at CERN and one for HDTV. Preliminary results are presented. They show that the objectives should be reached with the use of the ASP architecture. (author)

  18. Evaluation of Arm Processor-based Bionic Intelligent Controller for a Buck-boost Converte

    OpenAIRE

    M.V. Mini; L. Padma Suresh

    2015-01-01

    This study focuses on performance-comparison of different tuning methods for a PI controller applied to a buck-boost converter. Comparison between the controllers is made by analysis of design methodology implementation issues and empirically measured performance. Design of PI controller is based on frequency response of the converter. The optimization of PI controller is based on ant colony algorithm. Experimental results show that, tuning the PI controller using ACO algorithm gave better pe...

  19. Metal Ion Sensor with Catalytic DNA in a Nanofluidic Intelligent Processor

    Science.gov (United States)

    2011-12-01

    the SU8 epoxy group of polymers , but two common problems resulted from its use. First, SU8 shrinks during curing leaving cracks along channels...expands and contracts at the same CTE as the coverglass, which leads to layer misalignment. .................... 32 Figure 20. Modification of the SU8 ...tradeoff between forming a flat layer, although highly stressed on glass, or an unstressed layer but highly non-uniform on a polymer substrate. Because

  20. Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

  1. Social intelligence, human intelligence and niche construction.

    Science.gov (United States)

    Sterelny, Kim

    2007-04-29

    This paper is about the evolution of hominin intelligence. I agree with defenders of the social intelligence hypothesis in thinking that externalist models of hominin intelligence are not plausible: such models cannot explain the unique cognition and cooperation explosion in our lineage, for changes in the external environment (e.g. increasing environmental unpredictability) affect many lineages. Both the social intelligence hypothesis and the social intelligence-ecological complexity hybrid I outline here are niche construction models. Hominin evolution is hominin response to selective environments that earlier hominins have made. In contrast to social intelligence models, I argue that hominins have both created and responded to a unique foraging mode; a mode that is both social in itself and which has further effects on hominin social environments. In contrast to some social intelligence models, on this view, hominin encounters with their ecological environments continue to have profound selective effects. However, though the ecological environment selects, it does not select on its own. Accidents and their consequences, differential success and failure, result from the combination of the ecological environment an agent faces and the social features that enhance some opportunities and suppress others and that exacerbate some dangers and lessen others. Individuals do not face the ecological filters on their environment alone, but with others, and with the technology, information and misinformation that their social world provides.

  2. Road Nail: Experimental Solar Powered Intelligent Road Marking System

    Science.gov (United States)

    Samardžija, Dragan; Teslić, Nikola; Todorović, Branislav M.; Kovač, Erne; Isailović, Đorđe; Miladinović, Bojan

    2012-03-01

    Driving in low visibility conditions (night time, fog or heavy precipitation) is particularly challenging task with an increased probability of traffic accidents and possible injuries. Road Nail is a solar powered intelligent road marking system of wirelessly networked signaling devices that improve driver safety in low visibility conditions along hazardous roadways. Nails or signaling devices are autonomous nodes with capability to accumulate energy, exchange wireless messages, detect approaching vehicles and emit signalization light. We have built an experimental test-bed that consists of 20 nodes and a cellular gateway. Implementation details of the above system, including extensive measurements and performance evaluations in realistic field deployments are presented. A novel distributed network topology discovery scheme is proposed which integrates both sensor and wireless communication aspects, where nodes act autonomously. Finally, integration of the Road Nail system with the cellular network and the Internet is described.

  3. Secure data exchange between intelligent devices and computing centers

    Science.gov (United States)

    Naqvi, Syed; Riguidel, Michel

    2005-03-01

    The advent of reliable spontaneous networking technologies (commonly known as wireless ad-hoc networks) has ostensibly raised stakes for the conception of computing intensive environments using intelligent devices as their interface with the external world. These smart devices are used as data gateways for the computing units. These devices are employed in highly volatile environments where the secure exchange of data between these devices and their computing centers is of paramount importance. Moreover, their mission critical applications require dependable measures against the attacks like denial of service (DoS), eavesdropping, masquerading, etc. In this paper, we propose a mechanism to assure reliable data exchange between an intelligent environment composed of smart devices and distributed computing units collectively called 'computational grid'. The notion of infosphere is used to define a digital space made up of a persistent and a volatile asset in an often indefinite geographical space. We study different infospheres and present general evolutions and issues in the security of such technology-rich and intelligent environments. It is beyond any doubt that these environments will likely face a proliferation of users, applications, networked devices, and their interactions on a scale never experienced before. It would be better to build in the ability to uniformly deal with these systems. As a solution, we propose a concept of virtualization of security services. We try to solve the difficult problems of implementation and maintenance of trust on the one hand, and those of security management in heterogeneous infrastructure on the other hand.

  4. Quality control of intelligence research

    International Nuclear Information System (INIS)

    Lu Yan; Xin Pingping; Wu Jian

    2014-01-01

    Quality control of intelligence research is the core issue of intelligence management, is a problem in study of information science This paper focuses on the performance of intelligence to explain the significance of intelligence research quality control. In summing up the results of the study on the basis of the analysis, discusses quality control methods in intelligence research, introduces the experience of foreign intelligence research quality control, proposes some recommendations to improve quality control in intelligence research. (authors)

  5. A programmable systolic trigger processor for FERA bus data

    International Nuclear Information System (INIS)

    Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

    1992-09-01

    A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

  6. Low voltage 80 KV to 125 KV electron processors

    International Nuclear Information System (INIS)

    Lauppi, U.V.

    1999-01-01

    The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

  7. Design of RISC Processor Using VHDL and Cadence

    Science.gov (United States)

    Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

    The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

  8. Work in Amsterdam on local intelligence

    International Nuclear Information System (INIS)

    Dorenbosch, J.; Gosman, D.; Holthuizen, D.J.; Vermeulen, J.C.; Hertzberger, L.O.; Tuynman, F.

    1984-07-01

    Work on local intelligence at NIKHEF-H was started in 1979 with a proposal to design a multi microprocessor system for real-time event selection in high-energy physics experiments. The outcome of this is the Fast Amsterdam Multi Processor (FAMP) system which has the following properties: a high degree of modularity, facilitating easy system expansion; the possibility to realize hierarchical structures of processing elements; use of commercially available microprocessors. The system consists of modules that mechanically fit into a CAMAC crate. From the CAMAC standard only the CAMAC power supply lines are used. The FAMP system is described as it is used in the NA11/NA32 and UA1 experiments at CERN SPS (inclusive phi-meson production; proton-antiproton collisions.) Moreover, the FAMP distributed operating system (FADOS) is discussed in its present-day and future developments. (Auth.)

  9. Accelerating artificial intelligence with reconfigurable computing

    Science.gov (United States)

    Cieszewski, Radoslaw

    Reconfigurable computing is emerging as an important area of research in computer architectures and software systems. Many algorithms can be greatly accelerated by placing the computationally intense portions of an algorithm into reconfigurable hardware. Reconfigurable computing combines many benefits of both software and ASIC implementations. Like software, the mapped circuit is flexible, and can be changed over the lifetime of the system. Similar to an ASIC, reconfigurable systems provide a method to map circuits into hardware. Reconfigurable systems therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Such a field, where there is many different algorithms which can be accelerated, is an artificial intelligence. This paper presents example hardware implementations of Artificial Neural Networks, Genetic Algorithms and Expert Systems.

  10. An intercomparison of Canadian external dosimetry processors for radiation protection

    International Nuclear Information System (INIS)

    1989-10-01

    The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations

  11. First Results of an “Artificial Retina” Processor Prototype

    International Nuclear Information System (INIS)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-01-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

  12. Modal Processor Effects Inspired by Hammond Tonewheel Organs

    Directory of Open Access Journals (Sweden)

    Kurt James Werner

    2016-06-01

    Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

  13. Safety-critical Java on a time-predictable processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  14. Token-Aware Completion Functions for Elastic Processor Verification

    Directory of Open Access Journals (Sweden)

    Sudarshan K. Srinivasan

    2009-01-01

    Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

  15. A Bayesian sequential processor approach to spectroscopic portal system decisions

    Energy Technology Data Exchange (ETDEWEB)

    Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

    2007-07-31

    The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

  16. Processor farming in two-level analysis of historical bridge

    Science.gov (United States)

    Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

    2017-11-01

    This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

  17. A single chip pulse processor for nuclear spectroscopy

    International Nuclear Information System (INIS)

    Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

    1985-01-01

    A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

  18. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  19. Stepping motor control processor reference manual. Volume I

    International Nuclear Information System (INIS)

    Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.

    1980-01-01

    This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained

  20. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  1. A Processor-Sharing Scheduling Strategy for NFV Nodes

    Directory of Open Access Journals (Sweden)

    Giuseppe Faraci

    2016-01-01

    Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.

  2. Brain Intelligence: Go Beyond Artificial Intelligence

    OpenAIRE

    Lu, Huimin; Li, Yujie; Chen, Min; Kim, Hyoungseop; Serikawa, Seiichi

    2017-01-01

    Artificial intelligence (AI) is an important technology that supports daily social life and economic activities. It contributes greatly to the sustainable growth of Japan's economy and solves various social problems. In recent years, AI has attracted attention as a key for growth in developed countries such as Europe and the United States and developing countries such as China and India. The attention has been focused mainly on developing new artificial intelligence information communication ...

  3. Satellite on-board real-time SAR processor prototype

    Science.gov (United States)

    Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

    2017-11-01

    A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

  4. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  5. On the Behavior of ECN/RED Gateways Under a Large Number of TCP Flows: Limit Theorems

    National Research Council Canada - National Science Library

    Tinnakornsrisuphap, Peerapol; Makowski, Armand M

    2005-01-01

    .... As the number of competing flows becomes large, the asymptotic queue behavior at the gateway can be described by a simple recursion and the throughput behavior of individual TCP flows becomes asymptotically independent...

  6. Space Biology Model Organism Research on the Deep Space Gateway to Pioneer Discovery and Advance Human Space Exploration

    Science.gov (United States)

    Sato, K. Y.; Tomko, D. L.; Levine, H. G.; Quincy, C. D.; Rayl, N. A.; Sowa, M. B.; Taylor, E. M.; Sun, S. C.; Kundrot, C. E.

    2018-02-01

    Model organisms are foundational for conducting physiological and systems biology research to define how life responds to the deep space environment. The organisms, areas of research, and Deep Space Gateway capabilities needed will be presented.

  7. Los Angeles-Gateway Freight Advanced Traveler Information System : final system design and architecture for FRATIS prototype.

    Science.gov (United States)

    2013-05-01

    This Final Architecture and Design report has been prepared to describe the structure and design of all the system : components for the LA-Gateway FRATIS Demonstration Project. More specifically, this document provides: : Detailed descriptions of...

  8. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    OpenAIRE

    Hristov Ivan; Goranov Goran; Hristova Radoslava

    2018-01-01

    We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP”) in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL). The results show 2 times better per...

  9. The Danish real-time SAR processor: first results

    DEFF Research Database (Denmark)

    Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders

    1993-01-01

    A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

  10. Matrix preconditioning: a robust operation for optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A; Paparao, P

    1987-07-15

    Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

  11. UNIBUS processor interface for a FASTBUS data acquisition system

    International Nuclear Information System (INIS)

    Larwill, M.; Lagerlund, T.D.; Barsotti, E.; Taff, L.M.; Franzen, J.

    1981-01-01

    Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS ''event builder'' (i.e., data acquisition processor). Primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. Some possible FASTBUS data acquisition system architectures employing the UPI are discussed along with some detailed specifications of the UPI itself

  12. Ring-array processor distribution topology for optical interconnects

    Science.gov (United States)

    Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

    1992-01-01

    The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

  13. Global synchronization of parallel processors using clock pulse width modulation

    Science.gov (United States)

    Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

    2013-04-02

    A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

  14. Post-silicon and runtime verification for modern processors

    CERN Document Server

    Wagner, Ilya

    2010-01-01

    The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

  15. A VAX-FPS Loosely-Coupled Array of Processors

    International Nuclear Information System (INIS)

    Grosdidier, G.

    1987-03-01

    The main features of a VAX-FPS Loosely-Coupled Array of Processors (LCAP) set-up and the implementation of a High Energy Physics tracking program for off-line purposes will be described. This LCAP consists of a VAX 11/750 host and two FPS 64 bit attached processors. Before analyzing the performances of this LCAP, its characteristics will be outlined, especially from a user's point of vue, and will be briefly compared to those of the IBM-FPS LCAP

  16. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  17. FASTBUS Standard Routines implementation for Fermilab embedded processor boards

    International Nuclear Information System (INIS)

    Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

    1992-10-01

    In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

  18. The associative memory system for the FTK processor at ATLAS

    CERN Document Server

    Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

    2014-01-01

    In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

  19. Graphics processor efficiency for realization of rapid tabular computations

    International Nuclear Information System (INIS)

    Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.

    2016-01-01

    Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions

  20. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.