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Sample records for intel 80170nx chip

  1. 29 CFR 801.70 - Implementation by the Secretary.

    Science.gov (United States)

    2010-07-01

    ... 29 Labor 3 2010-07-01 2010-07-01 false Implementation by the Secretary. 801.70 Section 801.70 Labor Regulations Relating to Labor (Continued) WAGE AND HOUR DIVISION, DEPARTMENT OF LABOR OTHER LAWS... Vacation of Decision and Order of Administrative Law Judge § 801.70 Implementation by the Secretary. (a...

  2. 33 CFR 80.170 - Sandy Hook, NJ to Tom's River, NJ.

    Science.gov (United States)

    2010-07-01

    ... 33 Navigation and Navigable Waters 1 2010-07-01 2010-07-01 false Sandy Hook, NJ to Tom's River, NJ. 80.170 Section 80.170 Navigation and Navigable Waters COAST GUARD, DEPARTMENT OF HOMELAND SECURITY INTERNATIONAL NAVIGATION RULES COLREGS DEMARCATION LINES Atlantic Coast § 80.170 Sandy Hook, NJ to Tom's River...

  3. Newsgroups, Activist Publics, and Corporate Apologia: The Case of Intel and Its Pentium Chip.

    Science.gov (United States)

    Hearit, Keith Michael

    1999-01-01

    Applies J. Grunig's theory of publics to the phenomenon of Internet newsgroups using the case of the flawed Intel Pentium chip. Argues that technology facilitates the rapid movement of publics from the theoretical construct stage to the active stage. Illustrates some of the difficulties companies face in establishing their identity in cyberspace.…

  4. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  5. [Intel random number generator-based true random number generator].

    Science.gov (United States)

    Huang, Feng; Shen, Hong

    2004-09-01

    To establish a true random number generator on the basis of certain Intel chips. The random numbers were acquired by programming using Microsoft Visual C++ 6.0 via register reading from the random number generator (RNG) unit of an Intel 815 chipset-based computer with Intel Security Driver (ISD). We tested the generator with 500 random numbers in NIST FIPS 140-1 and X(2) R-Squared test, and the result showed that the random number it generated satisfied the demand of independence and uniform distribution. We also compared the random numbers generated by Intel RNG-based true random number generator and those from the random number table statistically, by using the same amount of 7500 random numbers in the same value domain, which showed that the SD, SE and CV of Intel RNG-based random number generator were less than those of the random number table. The result of u test of two CVs revealed no significant difference between the two methods. Intel RNG-based random number generator can produce high-quality random numbers with good independence and uniform distribution, and solves some problems with random number table in acquisition of the random numbers.

  6. 40 CFR 80.170 - Volumetric additive reconciliation (VAR), equipment calibration, and recordkeeping requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 16 2010-07-01 2010-07-01 false Volumetric additive reconciliation... ADDITIVES Detergent Gasoline § 80.170 Volumetric additive reconciliation (VAR), equipment calibration, and...) For a facility which uses a gauge to measure the inventory of the detergent storage tank, the total...

  7. New compilers speed up applications for Intel-based systems; Intel Compilers pave the way for Intel's Hyper-threading technology

    CERN Multimedia

    2002-01-01

    "Intel Corporation today introduced updated tools to help software developers optimize applications for Intel's expanding family of architectures with key innovations such as Intel's Hyper Threading Technology (1 page).

  8. Autonomous BBOBS-NX (NX-2G) for New Era of Ocean Bottom Broadband Seismology

    Science.gov (United States)

    Shiobara, H.; Ito, A.; Sugioka, H.; Shinohara, M.

    2017-12-01

    The broadband ocean bottom seismometer (BBOBS) and its new generation system (BBOBS-NX) have been developed in Japan, and we performed several test and practical observations to create and establish a new category of the ocean floor broadband seismology, since 1999. Now, the data obtained by our BBOBS and BBOBS-NX is proved to be adequate for broadband seismic analyses. Especially, the BBOBS-NX can obtain the horizontal data comparable to land sites in longer periods (10 s -). Moreover, the BBOBST-NX is in practical evaluation for the mobile tilt observation that enables dense geodetic monitoring. The BBOBS-NX system is a powerful tool, although, it has intrinsic limitation of the ROV operation. If this system can be used without the ROV, like as the BBOBS, it should lead us a true breakthrough of ocean bottom seismology. Hereafter, the new autonomous BBOBS-NX is noted as NX-2G in short. The main problem to realize the NX-2G is a tilt of the sensor unit on landing, which exceed the acceptable limit (±8°) in about 50%. As we had no evidence at which moment and how this tilt occurred, we tried to observe it during the BBOBST-NX landing in 2015 by attaching a video camera and an acceleration logger. The result shows that the tilt on landing was determined by the final posture of the system at the penetration into the sediment, and the large oscillating tilt more than ±10° was observed in descending. The function of the NX-2G system is based on 3 stage operations as shown in the image. The glass float is aimed not only to obtain enough buoyancy to extract the sensor unit, but also to suppress the oscillating tilt of the system in descending. In Oct. 2016, we made the first in-situ test of the NX-2G system with a ROV. It was dropped from the sea surface with the video camera and the acceleration logger. The ROV was used to watch the operation of the system at the seafloor. The landing looked well and it was examined from the acceleration data. As the maximum tilt in

  9. Intel: High Throughput Computing Collaboration: A CERN openlab / Intel collaboration

    CERN Multimedia

    CERN. Geneva

    2015-01-01

    The Intel/CERN High Throughput Computing Collaboration studies the application of upcoming Intel technologies to the very challenging environment of the LHC trigger and data-acquisition systems. These systems will need to transport and process many terabits of data every second, in some cases with tight latency constraints. Parallelisation and tight integration of accelerators and classical CPU via Intel's OmniPath fabric are the key elements in this project.

  10. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  11. Investigating the Use of the Intel Xeon Phi for Event Reconstruction

    Science.gov (United States)

    Sherman, Keegan; Gilfoyle, Gerard

    2014-09-01

    The physics goal of Jefferson Lab is to understand how quarks and gluons form nuclei and it is being upgraded to a higher, 12-GeV beam energy. The new CLAS12 detector in Hall B will collect 5-10 terabytes of data per day and will require considerable computing resources. We are investigating tools, such as the Intel Xeon Phi, to speed up the event reconstruction. The Kalman Filter is one of the methods being studied. It is a linear algebra algorithm that estimates the state of a system by combining existing data and predictions of those measurements. The tools required to apply this technique (i.e. matrix multiplication, matrix inversion) are being written using C++ intrinsics for Intel's Xeon Phi Coprocessor, which uses the Many Integrated Cores (MIC) architecture. The Intel MIC is a new high-performance chip that connects to a host machine through the PCIe bus and is built to run highly vectorized and parallelized code making it a well-suited device for applications such as the Kalman Filter. Our tests of the MIC optimized algorithms needed for the filter show significant increases in speed. For example, matrix multiplication of 5x5 matrices on the MIC was able to run up to 69 times faster than the host core. The physics goal of Jefferson Lab is to understand how quarks and gluons form nuclei and it is being upgraded to a higher, 12-GeV beam energy. The new CLAS12 detector in Hall B will collect 5-10 terabytes of data per day and will require considerable computing resources. We are investigating tools, such as the Intel Xeon Phi, to speed up the event reconstruction. The Kalman Filter is one of the methods being studied. It is a linear algebra algorithm that estimates the state of a system by combining existing data and predictions of those measurements. The tools required to apply this technique (i.e. matrix multiplication, matrix inversion) are being written using C++ intrinsics for Intel's Xeon Phi Coprocessor, which uses the Many Integrated Cores (MIC

  12. Intel Galileo essentials

    CERN Document Server

    Grimmett, Richard

    2015-01-01

    This book is for anyone who has ever been curious about using the Intel Galileo to create electronics projects. Some programming background is useful, but if you know how to use a personal computer, with the aid of the step-by-step instructions in this book, you can construct complex electronics projects that use the Intel Galileo.

  13. Accessing Intel FPGAs for Acceleration

    CERN Multimedia

    CERN. Geneva

    2018-01-01

    In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on the Intel Programmable Acceleration Card in a Data Center. We will then talk about the OpenCL flow which allows parallel software developers to create FPGA systems and deploy them using the OpenCL standard. Next, we will talk about the Intel High-Level Synthesis compiler which can convert C++ code into custom RTL code optimized for Intel FPGAs. Lastly, we will focus on the task of running Machine Learning inference on the FPGA leveraging some of the tools we discussed. About the speaker Karl Qi is Sr. Staff Applications Engineer, Technical Training. He has been with the Customer Training department at Altera/Intel for 8 years. Most recently, he is responsible for all training content relating to High-Level Design tools, including the OpenCL...

  14. Intel Xeon Phi coprocessor high performance programming

    CERN Document Server

    Jeffers, James

    2013-01-01

    Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products. This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture. It off...

  15. Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

    International Nuclear Information System (INIS)

    Gozzo, F.; Cossy-Favre, A.; Padmore, H.

    1997-01-01

    Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by the Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here

  16. Lattice QCD with Domain Decomposition on Intel Xeon Phi Co-Processors

    Energy Technology Data Exchange (ETDEWEB)

    Heybrock, Simon; Joo, Balint; Kalamkar, Dhiraj D; Smelyanskiy, Mikhail; Vaidyanathan, Karthikeyan; Wettig, Tilo; Dubey, Pradeep

    2014-12-01

    The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromodynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel Xeon Phi co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

  17. InP MMIC Chip Set for Power Sources Covering 80-170 GHz

    Science.gov (United States)

    Ngo, Catherine

    2001-01-01

    We will present a Monolithic Millimeter-wave Integrated Circuit (MMIC) chip set which provides high output-power sources for driving diode frequency multipliers into the terahertz range. The chip set was fabricated at HRL Laboratories using a 0.1-micrometer gate-length InAlAs/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with an f(sub max) above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range. In this paper, these high frequency HEMTs form the basis for power sources up to 170 GHz. A number of state-of-the-art InP HEMT MMICs will be presented. These include voltage-controlled and fixed-tuned oscillators, power amplifiers, and an active doubler. We will first discuss an 80 GHz voltage-controlled oscillator with 5 GHz of tunability and at least 17 mW of output power, as well as a 120 GHz oscillator providing 7 mW of output power. In addition, we will present results of a power amplifier which covers the full WRIO waveguide band (75-110 GHz), and provides 40-50 mW of output power. Furthermore, we will present an active doubler at 164 GHz providing 8% bandwidth, 3 mW of output power, and an unprecedented 2 dB of conversion loss for an InP HEMT MMIC at this frequency. Finally, we will demonstrate a power amplifier to cover 140-170 GHz with 15-25 mW of output power and 8 dB gain. These components can form a power source in the 155-165 GHz range by cascading the 80 GHz oscillator, W-band power amplifier, 164 GHz active doubler and final 140-170 GHz power amplifier for a stable, compact local oscillator subsystem, which could be used for atmospheric science or astrophysics radiometers.

  18. Home automation with Intel Galileo

    CERN Document Server

    Dundar, Onur

    2015-01-01

    This book is for anyone who wants to learn Intel Galileo for home automation and cross-platform software development. No knowledge of programming with Intel Galileo is assumed, but knowledge of the C programming language is essential.

  19. Unlock performance secrets of next-gen Intel hardware

    CERN Multimedia

    CERN. Geneva

    2015-01-01

    Intel® Xeon Phi Product. About the speaker Zakhar is a software architect in Intel SSG group. His current role is Parallel Studio architect with focus on SIMD vector parallelism assistance tools. Before it he was working as Intel Advisor XE software architect and software development team-lead. Before joining Intel he was...

  20. Effective SIMD Vectorization for Intel Xeon Phi Coprocessors

    OpenAIRE

    Tian, Xinmin; Saito, Hideki; Preis, Serguei V.; Garcia, Eric N.; Kozhukhov, Sergey S.; Masten, Matt; Cherkasov, Aleksei G.; Panchenko, Nikolay

    2015-01-01

    Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the Intel C/C++ and Fortran production compilers for Intel Xeon Phi coprocessors. A ...

  1. INTEL: Intel based systems move up in supercomputing ranks

    CERN Multimedia

    2002-01-01

    "The TOP500 supercomputer rankings released today at the Supercomputing 2002 conference show a dramatic increase in the number of Intel-based systems being deployed in high-performance computing (HPC) or supercomputing areas" (1/2 page).

  2. The development of the time-keeping clock with TS-1 single chip microcomputer.

    Science.gov (United States)

    Zhou, Jiguang; Li, Yongan

    The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

  3. Effective SIMD Vectorization for Intel Xeon Phi Coprocessors

    Directory of Open Access Journals (Sweden)

    Xinmin Tian

    2015-01-01

    Full Text Available Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the Intel C/C++ and Fortran production compilers for Intel Xeon Phi coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel Xeon Phi coprocessor. We also demonstrate a 2000x performance speedup from the seamless integration of SIMD vectorization and parallelization.

  4. Roofline Analysis in the Intel® Advisor to Deliver Optimized Performance for applications on Intel® Xeon Phi™ Processor

    OpenAIRE

    Koskela, TS; Lobet, M

    2017-01-01

    In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science appl...

  5. Scientific Computing and Apple's Intel Transition

    CERN Document Server

    CERN. Geneva

    2006-01-01

    Intel's published processor roadmap and how it may affect the future of personal and scientific computing About the speaker: Eric Albert is Senior Software Engineer in Apple's Core Technologies group. During Mac OS X's transition to Intel processors he has worked on almost every part of the operating system, from the OS kernel and compiler tools to appli...

  6. Exploring performance and power properties of modern multicore chips via simple machine models

    OpenAIRE

    Hager, Georg; Treibig, Jan; Habich, Johannes; Wellein, Gerhard

    2012-01-01

    Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the wel...

  7. Using the Intel Math Kernel Library on Peregrine | High-Performance

    Science.gov (United States)

    Computing | NREL the Intel Math Kernel Library on Peregrine Using the Intel Math Kernel Library on Peregrine Learn how to use the Intel Math Kernel Library (MKL) with Peregrine system software. MKL architectures. Core math functions in MKL include BLAS, LAPACK, ScaLAPACK, sparse solvers, fast Fourier

  8. Comparative VME Performance Tests for MEN A20 Intel-L865 and RIO-3 PPC-LynxOS platforms

    CERN Document Server

    Andersen, M; CERN. Geneva. BE Department

    2009-01-01

    This benchmark note presents test results from reading values over VME using different methods and different sizes of data registers, running on two different platforms Intel-L865 and PPC-LynxOS. We find that the PowerPC is a factor 3 faster in accessing an array of contiguous VME memory locations. Block transfer and DMA read accesses are also tested and compared with conventional single access reads.

  9. CERN welcomes Intel Science Fair winners

    CERN Multimedia

    Katarina Anthony

    2012-01-01

    This June, CERN welcomed twelve gifted young scientists aged 15-18 for a week-long visit of the Laboratory. These talented students were the winners of a special award co-funded by CERN and Intel, given yearly at the Intel International Science and Engineering Fair (ISEF).   The CERN award winners at the Intel ISEF 2012 Special Awards Ceremony. © Society for Science & the Public (SSP). The CERN award was set up back in 2009 as an opportunity to bring some of the best and brightest young minds to the Laboratory. The award winners are selected from among 1,500 talented students participating in ISEF – the world's largest pre-university science competition, in which students compete for more than €3 million in awards. “CERN gave an award – which was obviously this trip – to students studying physics, maths, electrical engineering and computer science,” says Benjamin Craig Bartlett, 17, from South Carolina, USA, wh...

  10. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    Science.gov (United States)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

  11. What can we learn from the decay of $ N_X(1625)$ in molecule picture?

    OpenAIRE

    Liu, Xiang; Zhang, Bo

    2007-01-01

    Considering two molecular state assumptions, i.e. S-wave $\\bar{\\Lambda}-K^-$ and S-wave $\\bar{\\Sigma}^0-K^-$ molecular states, we study the possible decays of $\\bar N_X(1625)$ that include $\\bar N_X(1625)\\to K^{-}\\bar{\\Lambda}, \\pi^{0}\\bar{p}, \\eta\\bar{p}, \\pi^{-}\\bar{n}$. Our results indicate: (1) if $\\bar N_{X}(1625)$ is $\\bar{\\Lambda}-K^-$ molecular state, $K^{-}\\bar{\\Lambda}$ is the main decay modes of $\\bar N_{X}(1625)$, and the branching ratios of the rest decay modes are tiny; (2) if $...

  12. Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors

    Directory of Open Access Journals (Sweden)

    Enrico Calore

    2018-06-01

    Full Text Available Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short. We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS technique.

  13. Experience with Intel's Many Integrated Core Architecture in ATLAS Software

    CERN Document Server

    Fleischmann, S; The ATLAS collaboration; Lavrijsen, W; Neumann, M; Vitillo, R

    2014-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks. This should make it possible to develop for both throughput and latency devices using a single code base.\

  14. Experience with Intel's Many Integrated Core Architecture in ATLAS Software

    CERN Document Server

    Fleischmann, S; The ATLAS collaboration; Lavrijsen, W; Neumann, M; Vitillo, R

    2013-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks. This should make it possible to develop for both throughput and latency devices using a single code base.\

  15. NiCrNx interlayer thickness dependence of spectral performance and environmental durability of protected-silver mirrors

    Science.gov (United States)

    Xu, Xu; Li, Bincheng; He, Wenyan; Wang, Changjun; Wei, Ming

    2018-04-01

    Gemini-style protected-silver mirror (Sub / NiCrNx / Ag / NiCrNx / SiNx / Air) is a suitable choice for optical instruments requiring both long-term environmental durability and high broadband reflectance. Three Gemini-style protected-silver mirrors with NiCrNx interlayer thicknesses between 0.1 and 0.6 nm were prepared by magnetron sputtering, and the dependences of spectral properties and environmental durability of these protected-silver mirrors on the thickness of NiCrNx interlayer between the silver layer and SiNx layer were investigated in-depth. The reflectance, transmittance and total scattering loss measurements, optical microscope, and scanning electron microscope imaging were employed to characterize the spectral properties and surface morphology, and accelerated environmental tests, including humidity test and salt fog test, were applied to investigate the environmental durability. The experimental results showed that both optical and corrosion-resistant properties of protected-silver mirrors were NiCrNx interlayer thickness dependent, and an optimum NiCrNx interlayer thickness should be ˜0.3 nm for Gemini-style protected-silver mirrors to have reasonably both high reflectance in a broadband spectral range from visible to far infrared and good corrosion resistance for long-lifetime applications in harsh environments.

  16. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    CERN Document Server

    Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Knight, Robert; Muzaffar, Shahzad

    2014-01-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).

  17. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    Science.gov (United States)

    Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; Eulisse, Giulio; Knight, Robert; Muzaffar, Shahzad

    2015-05-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).

  18. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    International Nuclear Information System (INIS)

    Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad; Knight, Robert

    2015-01-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG). (paper)

  19. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

    2010-01-01

    As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

  20. Non Isolated and Non-Inverting Cockcroft Walton Multiplier Based Hybrid 2Nx Interleaved Boost Converter For Renewable Energy Applications

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Padamanaban, Sanjeevi Kumar; Blaabjerg, Frede

    2016-01-01

    In this paper hybrid non isolated and non-invertingCockcroft-Walton multiplier based 2Nx InterleavedBoost converter (2Nx IBC) for renewable energy applications is presented. The presented hybrid boost converter topology is derived from non-inverting Nx Multilevel Boost Converter (Nx MBC......) and inverting Nx Multilevel Boost Converter (Nx MBC). In renewable energy applications, generated voltage needs to be stepped up with high conversion ratio using a DC-DC converter at voltage levels as per the application requirement. The advantages of the presentedtopology of interleaved converter are high...

  1. NxStage dialysis system-associated thrombocytopenia: a report of two cases.

    Science.gov (United States)

    Sekkarie, Mohamed; Waldron, Michelle; Reynolds, Texas

    2016-01-01

    Thrombocytopenia in hemodialysis patients has recently been reported to be commonly caused by electron-beam sterilization of dialysis filters. We report the occurrence of thrombocytopenia in the first two patients of a newly established home hemodialysis program. The 2 patients switched from conventional hemodialysis using polysulfone electron-beam sterilized dialyzers to a NxStage system, which uses gamma sterilized polyehersulfone dialyzers incorporated into a drop-in cartridge. The thrombocytopenia resolved after return to conventional dialysis in both patients and recurred upon rechallenge in the patient who opted to retry NxStage. This is the first report of thrombocytopenia with the NxStage system according to the authors’ knowledge. Dialysis-associated thrombocytopenia pathophysiology and clinical significance are not well understood and warrant additional investigations.

  2. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  3. Adaptation of MPDATA Heterogeneous Stencil Computation to Intel Xeon Phi Coprocessor

    Directory of Open Access Journals (Sweden)

    Lukasz Szustak

    2015-01-01

    Full Text Available The multidimensional positive definite advection transport algorithm (MPDATA belongs to the group of nonoscillatory forward-in-time algorithms and performs a sequence of stencil computations. MPDATA is one of the major parts of the dynamic core of the EULAG geophysical model. In this work, we outline an approach to adaptation of the 3D MPDATA algorithm to the Intel MIC architecture. In order to utilize available computing resources, we propose the (3 + 1D decomposition of MPDATA heterogeneous stencil computations. This approach is based on combination of the loop tiling and fusion techniques. It allows us to ease memory/communication bounds and better exploit the theoretical floating point efficiency of target computing platforms. An important method of improving the efficiency of the (3 + 1D decomposition is partitioning of available cores/threads into work teams. It permits for reducing inter-cache communication overheads. This method also increases opportunities for the efficient distribution of MPDATA computation onto available resources of the Intel MIC architecture, as well as Intel CPUs. We discuss preliminary performance results obtained on two hybrid platforms, containing two CPUs and Intel Xeon Phi. The top-of-the-line Intel Xeon Phi 7120P gives the best performance results, and executes MPDATA almost 2 times faster than two Intel Xeon E5-2697v2 CPUs.

  4. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  5. MILC staggered conjugate gradient performance on Intel KNL

    OpenAIRE

    DeTar, Carleton; Doerfler, Douglas; Gottlieb, Steven; Jha, Ashish; Kalamkar, Dhiraj; Li, Ruizi; Toussaint, Doug

    2016-01-01

    We review our work done to optimize the staggered conjugate gradient (CG) algorithm in the MILC code for use with the Intel Knights Landing (KNL) architecture. KNL is the second gener- ation Intel Xeon Phi processor. It is capable of massive thread parallelism, data parallelism, and high on-board memory bandwidth and is being adopted in supercomputing centers for scientific research. The CG solver consumes the majority of time in production running, so we have spent most of our effort on it. ...

  6. Influence of in-situ deposited SiNx interlayer on crystal quality of GaN epitaxial films

    Science.gov (United States)

    Fan, Teng; Jia, Wei; Tong, Guangyun; Zhai, Guangmei; Li, Tianbao; Dong, Hailiang; Xu, Bingshe

    2018-05-01

    GaN epitaxial films with SiNx interlayers were prepared by metal organic chemical vapor deposition (MOCVD) on c-plane sapphire substrates. The influences of deposition times and locations of SiNx interlayers on crystal quality of GaN epitaxial films were studied. Under the optimal growth time of 120 s for the SiNx interlayer, the dislocation density of GaN film is reduced to 4.05 × 108 cm-2 proved by high resolution X-ray diffraction results. It is found that when the SiNx interlayer deposits on the GaN nucleation islands, the subsequent GaN film has the lowest dislocation density of only 2.89 × 108 cm-2. Moreover, a model is proposed to illustrate the morphological evolution and associated propagation processes of TDs in GaN epi-layers with SiNx interlayers for different deposition times and locations.

  7. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2010-12-01

    Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

  8. Realization of Colored Multicrystalline Silicon Solar Cells with SiO2/SiNx:H Double Layer Antireflection Coatings

    Directory of Open Access Journals (Sweden)

    Minghua Li

    2013-01-01

    Full Text Available We presented a method to use SiO2/SiNx:H double layer antireflection coatings (DARC on acid textures to fabricate colored multicrystalline silicon (mc-Si solar cells. Firstly, we modeled the perceived colors and short-circuit current density (Jsc as a function of SiNx:H thickness for single layer SiNx:H, and as a function of SiO2 thickness for the case of SiO2/SiNx:H (DARC with fixed SiNx:H (refractive index n=2.1 at 633 nm, and thickness = 80 nm. The simulation results show that it is possible to achieve various colors by adjusting the thickness of SiO2 to avoid significant optical losses. Therefore, we carried out the experiments by using electron beam (e-beam evaporation to deposit a layer of SiO2 over the standard SiNx:H for 156×156 mm2 mc-Si solar cells which were fabricated by a conventional process. Semisphere reflectivity over 300 nm to 1100 nm and I-V measurements were performed for grey yellow, purple, deep blue, and green cells. The efficiency of colored SiO2/SiNx:H DARC cells is comparable to that of standard SiNx:H light blue cells, which shows the potential of colored cells in industrial applications.

  9. Parallelization of particle transport using Intel® TBB

    International Nuclear Information System (INIS)

    Apostolakis, J; Brun, R; Carminati, F; Gheata, A; Wenzel, S; Belogurov, S; Ovcharenko, E

    2014-01-01

    One of the current challenges in HEP computing is the development of particle propagation algorithms capable of efficiently use all performance aspects of modern computing devices. The Geant-Vector project at CERN has recently introduced an approach in this direction. This paper describes the implementation of a similar workflow using the Intel(r) Threading Building Blocks (Intel(r) TBB) library. This approach is intended to overcome the potential bottleneck of having a single dispatcher on many-core architectures and to result in better scalability compared to the initial pthreads-based version.

  10. NxRepair: error correction in de novo sequence assembly using Nextera mate pairs

    Directory of Open Access Journals (Sweden)

    Rebecca R. Murphy

    2015-06-01

    Full Text Available Scaffolding errors and incorrect repeat disambiguation during de novo assembly can result in large scale misassemblies in draft genomes. Nextera mate pair sequencing data provide additional information to resolve assembly ambiguities during scaffolding. Here, we introduce NxRepair, an open source toolkit for error correction in de novo assemblies that uses Nextera mate pair libraries to identify and correct large-scale errors. We show that NxRepair can identify and correct large scaffolding errors, without use of a reference sequence, resulting in quantitative improvements in the assembly quality. NxRepair can be downloaded from GitHub or PyPI, the Python Package Index; a tutorial and user documentation are also available.

  11. Performance of a plasma fluid code on the Intel parallel computers

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Leboeuf, J.N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel σ machine gives an improvement factor close to 64 over the single-processor CRAY-2

  12. Performance of a plasma fluid code on the Intel parallel computers

    Science.gov (United States)

    Lynch, V. E.; Carreras, B. A.; Drake, J. B.; Leboeuf, J. N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel (sigma) machine gives an improvement factor close to 64 over the single-processor CRAY-2.

  13. Multi-Kepler GPU vs. multi-Intel MIC for spin systems simulations

    Science.gov (United States)

    Bernaschi, M.; Bisson, M.; Salvadore, F.

    2014-10-01

    We present and compare the performances of two many-core architectures: the Nvidia Kepler and the Intel MIC both in a single system and in cluster configuration for the simulation of spin systems. As a benchmark we consider the time required to update a single spin of the 3D Heisenberg spin glass model by using the Over-relaxation algorithm. We present data also for a traditional high-end multi-core architecture: the Intel Sandy Bridge. The results show that although on the two Intel architectures it is possible to use basically the same code, the performances of a Intel MIC change dramatically depending on (apparently) minor details. Another issue is that to obtain a reasonable scalability with the Intel Phi coprocessor (Phi is the coprocessor that implements the MIC architecture) in a cluster configuration it is necessary to use the so-called offload mode which reduces the performances of the single system. As to the GPU, the Kepler architecture offers a clear advantage with respect to the previous Fermi architecture maintaining exactly the same source code. Scalability of the multi-GPU implementation remains very good by using the CPU as a communication co-processor of the GPU. All source codes are provided for inspection and for double-checking the results.

  14. High-Performance Epoxy-Resin-Bonded Magnets Produced from the Sm2Fe17Nx Powders Coated by Copper and Zinc Metals

    Science.gov (United States)

    Noguchi, Kenji; Machida, Ken-ichi; Adachi, Gin-ya

    2001-04-01

    Fine powders of Sm2Fe17Nx coated with copper metal reduced from CuCl2 and/or zinc metal subsequently derived by photo-decomposition of diethylzinc [Zn(C2H5)2] were prepared, and their magnetic properties were characterized in addition to those of epoxy-resin-bonded magnets produced from the coated powders (Cu/Sm2Fe17Nx, Zn/Sm2Fe17Nx and Zn/Cu/Sm2Fe17Nx). The remanence (Br) and maximum energy product [(\\mathit{BH})max] of double metal-coated Zn/Cu/Sm2Fe17Nx powders were maintained at higher levels than those of single Zn metal-coated Sm2Fe17Nx ones (Zn/Sm2Fe17Nx) even after heat treatment at 673 K since the oxidation resistance and thermal stability were effectively improved by formation of the thick and uniform protection layer on the surface of Sm2Fe17Nx particles. Moreover, the epoxy-resin-bonded magnets produced from the Zn/Cu/Sm2Fe17Nx powders possessed good corrosion resistance in air at 393 K which it resulted in the smaller thermal irreversible flux loss than that of uncoated and single Zn metal-coated Sm2Fe17Nx powders in the temperature range of above 393 K.

  15. Performance of a plasma fluid code on the Intel parallel computers

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Leboeuf, J.N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel (sigma) machine gives an improvement factor close to 64 over the single-processor CRAY-2. 12 refs

  16. Analysis OpenMP performance of AMD and Intel architecture for breaking waves simulation using MPS

    Science.gov (United States)

    Alamsyah, M. N. A.; Utomo, A.; Gunawan, P. H.

    2018-03-01

    Simulation of breaking waves by using Navier-Stokes equation via moving particle semi-implicit method (MPS) over close domain is given. The results show the parallel computing on multicore architecture using OpenMP platform can reduce the computational time almost half of the serial time. Here, the comparison using two computer architectures (AMD and Intel) are performed. The results using Intel architecture is shown better than AMD architecture in CPU time. However, in efficiency, the computer with AMD architecture gives slightly higher than the Intel. For the simulation by 1512 number of particles, the CPU time using Intel and AMD are 12662.47 and 28282.30 respectively. Moreover, the efficiency using similar number of particles, AMD obtains 50.09 % and Intel up to 49.42 %.

  17. Efficient Implementation of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Apra, Edoardo; Klemm, Michael; Kowalski, Karol

    2014-12-01

    This paper presents the implementation and performance of the highly accurate CCSD(T) quantum chemistry method on the Intel Xeon Phi coprocessor within the context of the NWChem computational chemistry package. The widespread use of highly correlated methods in electronic structure calculations is contingent upon the interplay between advances in theory and the possibility of utilizing the ever-growing computer power of emerging heterogeneous architectures. We discuss the design decisions of our implementation as well as the optimizations applied to the compute kernels and data transfers between host and coprocessor. We show the feasibility of adopting the Intel Many Integrated Core Architecture and the Intel Xeon Phi coprocessor for developing efficient computational chemistry modeling tools. Remarkable scalability is demonstrated by benchmarks. Our solution scales up to a total of 62560 cores with the concurrent utilization of Intel Xeon processors and Intel Xeon Phi coprocessors.

  18. Rear-Sided Passivation by SiNx:H Dielectric Layer for Improved Si/PEDOT:PSS Hybrid Heterojunction Solar Cells.

    Science.gov (United States)

    Sun, Yiling; Gao, Pingqi; He, Jian; Zhou, Suqiong; Ying, Zhiqin; Yang, Xi; Xiang, Yong; Ye, Jichun

    2016-12-01

    Silicon/organic hybrid solar cells have recently attracted great attention because they combine the advantages of silicon (Si) and the organic cells. In this study, we added a patterned passivation layer of silicon nitride (SiNx:H) onto the rear surface of the Si substrate in a Si/poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) ( PSS) hybrid solar cell, enabling an improvement of 0.6 % in the power conversion efficiency (PCE). The addition of the SiNx:H layer boosted the open circuit voltage (V oc) from 0.523 to 0.557 V, suggesting the well-passivation property of the patterned SiNx:H thin layer that was created by plasma-enhanced chemical vapor deposition and lithography processes. The passivation properties that stemmed from front PSS, rear-SiNx:H, front PSS/rear-SiNx:H, etc. are thoroughly investigated, in consideration of the process-related variations.

  19. The effect of CO2 on the plasma remediation of NxOy

    Science.gov (United States)

    Gentile, Ann C.; Kushner, Mark J.

    1996-04-01

    Plasma remediation is being investigated for the removal of oxides of nitrogen (NxOy) from atmospheric pressure gas streams. In previous works we have investigated the plasma remediation of NxOy from N2/O2/H2O mixtures using repetitively pulsed dielectric barrier discharges. As combustion effluents contain large percentages of CO2, in this paper we discuss the consequences of CO2 in the gas mixture on the efficiency of remediation and on the end products. We find that there is a small increase in the efficiency of total NxOy remediation (molecules/eV) with increasing CO2 fraction, however the efficiency of NO remediation alone generally decreases with increasing CO2. This differential is more pronounced at low energy deposition per pulse. More remediation occurs through the reduction channel with increasing CO2 while less NO2 and HNOx are produced through the oxidation channel. CO is produced by electron impact of CO2 though negligible amounts of cyanides are generated.

  20. Intel Corporation osaleb Eesti koolitusprogrammis / Raivo Juurak

    Index Scriptorium Estoniae

    Juurak, Raivo, 1949-

    2001-01-01

    Haridusministeeriumis tutvustati infotehnoloogiaalast koolitusprogrammi, milles osaleb maailma suuremaid arvutifirmasid Intel Corporation. Koolituskursuse käigus õpetatakse aineõpetajaid oma ainetundides interneti võimalusi kasutama. 50-tunnised kursused viiakse läbi kõigis maakondades

  1. 4Nx Non-Isolated and Non-Inverting Hybrid Interleaved Multilevel Boost Converter Based on VLCIm Cell and Cockroft Walton Voltage Multiplier for Renewable Energy Applications

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Padmanaban, Sanjeevikumar; Blaabjerg, Frede

    2016-01-01

    In this treatise, 4Nx hybrid Non Inverting & Non Isolated (NI-NI) DC-DC interleaved multi-level boost converter (4Nx IMBC) for renewable energy applications is proposed. The proposed 4Nx IMBC is derived by coalescing the feature of 2Nx DC-DC Interleaved Multi-level Boost Converter (2Nx IMBC), vol...... or transformers. Simulations results of proposed circuitry are presented which verify the analysis, function, working modes & feasibility of proposed circuitry converter.......In this treatise, 4Nx hybrid Non Inverting & Non Isolated (NI-NI) DC-DC interleaved multi-level boost converter (4Nx IMBC) for renewable energy applications is proposed. The proposed 4Nx IMBC is derived by coalescing the feature of 2Nx DC-DC Interleaved Multi-level Boost Converter (2Nx IMBC...... applicable at user end its DC voltage magnitude needs to be incremented with high conversion. Existing and recently proposed DC-DC converter are not sufficiently expert to employ practically, because of stability issues, high duty cycle and high ripple in the output. To overcome the conversion ratio problem...

  2. Performance Evaluation of Computation and Communication Kernels of the Fast Multipole Method on Intel Manycore Architecture

    KAUST Repository

    AbdulJabbar, Mustafa Abdulmajeed; Al Farhan, Mohammed; Yokota, Rio; Keyes, David E.

    2017-01-01

    Manycore optimizations are essential for achieving performance worthy of anticipated exascale systems. Utilization of manycore chips is inevitable to attain the desired floating point performance of these energy-austere systems. In this work, we revisit ExaFMM, the open source Fast Multiple Method (FMM) library, in light of highly tuned shared-memory parallelization and detailed performance analysis on the new highly parallel Intel manycore architecture, Knights Landing (KNL). We assess scalability and performance gain using task-based parallelism of the FMM tree traversal. We also provide an in-depth analysis of the most computationally intensive part of the traversal kernel (i.e., the particle-to-particle (P2P) kernel), by comparing its performance across KNL and Broadwell architectures. We quantify different configurations that exploit the on-chip 512-bit vector units within different task-based threading paradigms. MPI communication-reducing and NUMA-aware approaches for the FMM’s global tree data exchange are examined with different cluster modes of KNL. By applying several algorithm- and architecture-aware optimizations for FMM, we show that the N-Body kernel on 256 threads of KNL achieves on average 2.8× speedup compared to the non-vectorized version, whereas on 56 threads of Broadwell, it achieves on average 2.9× speedup. In addition, the tree traversal kernel on KNL scales monotonically up to 256 threads with task-based programming models. The MPI-based communication-reducing algorithms show expected improvements of the data locality across the KNL on-chip network.

  3. Performance Evaluation of Computation and Communication Kernels of the Fast Multipole Method on Intel Manycore Architecture

    KAUST Repository

    AbdulJabbar, Mustafa Abdulmajeed

    2017-07-31

    Manycore optimizations are essential for achieving performance worthy of anticipated exascale systems. Utilization of manycore chips is inevitable to attain the desired floating point performance of these energy-austere systems. In this work, we revisit ExaFMM, the open source Fast Multiple Method (FMM) library, in light of highly tuned shared-memory parallelization and detailed performance analysis on the new highly parallel Intel manycore architecture, Knights Landing (KNL). We assess scalability and performance gain using task-based parallelism of the FMM tree traversal. We also provide an in-depth analysis of the most computationally intensive part of the traversal kernel (i.e., the particle-to-particle (P2P) kernel), by comparing its performance across KNL and Broadwell architectures. We quantify different configurations that exploit the on-chip 512-bit vector units within different task-based threading paradigms. MPI communication-reducing and NUMA-aware approaches for the FMM’s global tree data exchange are examined with different cluster modes of KNL. By applying several algorithm- and architecture-aware optimizations for FMM, we show that the N-Body kernel on 256 threads of KNL achieves on average 2.8× speedup compared to the non-vectorized version, whereas on 56 threads of Broadwell, it achieves on average 2.9× speedup. In addition, the tree traversal kernel on KNL scales monotonically up to 256 threads with task-based programming models. The MPI-based communication-reducing algorithms show expected improvements of the data locality across the KNL on-chip network.

  4. 75 FR 21353 - Intel Corporation, Fab 20 Division, Including On-Site Leased Workers From Volt Technical...

    Science.gov (United States)

    2010-04-23

    ... DEPARTMENT OF LABOR Employment and Training Administration [TA-W-73,642] Intel Corporation, Fab 20... of Intel Corporation, Fab 20 Division, including on-site leased workers of Volt Technical Resources... Precision, Inc. were employed on-site at the Hillsboro, Oregon location of Intel Corporation, Fab 20...

  5. Thread-level parallelization and optimization of NWChem for the Intel MIC architecture

    Energy Technology Data Exchange (ETDEWEB)

    Shan, Hongzhang [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Williams, Samuel [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); de Jong, Wibe [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Oliker, Leonid [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

    2015-01-01

    In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant e ort was required to safely and efeciently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI+OpenMP hybrid implementations attain up to 65× better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6× better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.

  6. Thread-Level Parallelization and Optimization of NWChem for the Intel MIC Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Shan, Hongzhang; Williams, Samuel; Jong, Wibe de; Oliker, Leonid

    2014-10-10

    In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in tt native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant effort was required to safely and efficiently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI OpenMP hybrid implementations attain up to 65x better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6x better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.

  7. MILC staggered conjugate gradient performance on Intel KNL

    Energy Technology Data Exchange (ETDEWEB)

    Li, Ruiz [Indiana Univ., Bloomington, IN (United States). Dept. of Physics; Detar, Carleton [Univ. of Utah, Salt Lake City, UT (United States). Dept. of Physics and Astronomy; Doerfler, Douglas W. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). National Energy Research Scientific Computing Center (NERSC); Gottlieb, Steven [Indiana Univ., Bloomington, IN (United States). Dept. of Physics; Jha, Asish [Intel Corp., Hillsboro, OR (United States). Sofware and Services Group; Kalamkar, Dhiraj [Intel Labs., Bangalore (India). Parallel Computing Lab.; Toussaint, Doug [Univ. of Arizona, Tucson, AZ (United States). Physics Dept.

    2016-11-03

    We review our work done to optimize the staggered conjugate gradient (CG) algorithm in the MILC code for use with the Intel Knights Landing (KNL) architecture. KNL is the second gener- ation Intel Xeon Phi processor. It is capable of massive thread parallelism, data parallelism, and high on-board memory bandwidth and is being adopted in supercomputing centers for scientific research. The CG solver consumes the majority of time in production running, so we have spent most of our effort on it. We compare performance of an MPI+OpenMP baseline version of the MILC code with a version incorporating the QPhiX staggered CG solver, for both one-node and multi-node runs.

  8. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  9. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  10. Nanocrystalline Si pathway induced unipolar resistive switching behavior from annealed Si-rich SiNx/SiNy multilayers

    Science.gov (United States)

    Jiang, Xiaofan; Ma, Zhongyuan; Yang, Huafeng; Yu, Jie; Wang, Wen; Zhang, Wenping; Li, Wei; Xu, Jun; Xu, Ling; Chen, Kunji; Huang, Xinfan; Feng, Duan

    2014-09-01

    Adding a resistive switching functionality to a silicon microelectronic chip is a new challenge in materials research. Here, we demonstrate that unipolar and electrode-independent resistive switching effects can be realized in the annealed Si-rich SiNx/SiNy multilayers with high on/off ratio of 109. High resolution transmission electron microscopy reveals that for the high resistance state broken pathways composed of discrete nanocrystalline silicon (nc-Si) exist in the Si nitride multilayers. While for the low resistance state the discrete nc-Si regions is connected, forming continuous nc-Si pathways. Based on the analysis of the temperature dependent I-V characteristics and HRTEM photos, we found that the break-and-bridge evolution of nc-Si pathway is the origin of resistive switching memory behavior. Our findings provide insights into the mechanism of the resistive switching behavior in nc-Si films, opening a way for it to be utilized as a material in Si-based memories.

  11. An INTEL 8080 microprocessor development system

    International Nuclear Information System (INIS)

    Horne, P.J.

    1977-01-01

    The INTEL 8080 has become one of the two most widely used microprocessors at CERN, the other being the MOTOROLA 6800. Even thouth this is the case, there have been, to date, only rudimentary facilities available for aiding the development of application programs for this microprocessor. An ideal development system is one which has a sophisticated editing and filing system, an assembler/compiler, and access to the microprocessor application. In many instances access to a PROM programmer is also required, as the application may utilize only PROMs for program storage. With these thoughts in mind, an INTEL 8080 microprocessor development system was implemented in the Proton Synchrotron (PS) Division. This system utilizes a PDP 11/45 as the editing and file-handling machine, and an MSC 8/MOD 80 microcomputer for assembling, PROM programming and debugging user programs at run time. The two machines are linked by an existing CAMAC crate system which will also provide the means of access to microprocessor applications in CAMAC and the interface of the development system to any other application. (Auth.)

  12. Effect of oxygen on tuning the TiNx metal gate work function on LaLuO3

    International Nuclear Information System (INIS)

    Mitrovic, I.Z.; Przewlocki, H.M.; Piskorski, K.; Simutis, G.; Dhanak, V.R.; Sedghi, N.; Hall, S.

    2012-01-01

    This paper presents experimental evidence on effective work function tuning due to the presence of oxygen at the TiNx/LaLuO 3 interface. Two complementary techniques, internal photoemission and X-ray photoelectron spectroscopy, show good agreement on the position of the metal gate Fermi level to conduction (2.79 ± 0.25 eV) and valence (2.65 ± 0.08 eV) band edge for TiNx/bulk LaLuO 3 gate stacks. The chemical shifts of Ti2p and N1s core levels and different degree in ionicity of TiNx metal gates correlate with the observed valence band offset shifts. The results have significance for setting the band edge work function and resulting low threshold voltage for ultimately scaled LaLuO 3 -based p-metal oxide semiconductor field effect transistor devices. - Highlights: ► The conduction band offset measured by internal photoemission. ► The valence band offset (VBO) measured by X-ray photoelectron spectroscopy. ► Different degree in ionicity of TiNx correlates with the VBO shifts. ► The effective work function of the gate stacks varies from 4.6 to 5.2 eV. ► Oxygen at the TiNx/LaLuO 3 interface increases effective work function.

  13. Intel Xeon Phi accelerated Weather Research and Forecasting (WRF) Goddard microphysics scheme

    Science.gov (United States)

    Mielikainen, J.; Huang, B.; Huang, A. H.-L.

    2014-12-01

    The Weather Research and Forecasting (WRF) model is a numerical weather prediction system designed to serve both atmospheric research and operational forecasting needs. The WRF development is a done in collaboration around the globe. Furthermore, the WRF is used by academic atmospheric scientists, weather forecasters at the operational centers and so on. The WRF contains several physics components. The most time consuming one is the microphysics. One microphysics scheme is the Goddard cloud microphysics scheme. It is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The Goddard microphysics scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Goddard scheme incorporates a large number of improvements. Thus, we have optimized the Goddard scheme code. In this paper, we present our results of optimizing the Goddard microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The Intel MIC is capable of executing a full operating system and entire programs rather than just kernels as the GPU does. The MIC coprocessor supports all important Intel development tools. Thus, the development environment is one familiar to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discussed in this paper. The results show that the optimizations improved performance of Goddard microphysics scheme on Xeon Phi 7120P by a factor of 4.7×. In addition, the optimizations reduced the Goddard microphysics scheme's share of the total WRF processing time from 20.0 to 7.5%. Furthermore, the same optimizations

  14. Vectorization for Molecular Dynamics on Intel Xeon Phi Corpocessors

    Science.gov (United States)

    Yi, Hongsuk

    2014-03-01

    Many modern processors are capable of exploiting data-level parallelism through the use of single instruction multiple data (SIMD) execution. The new Intel Xeon Phi coprocessor supports 512 bit vector registers for the high performance computing. In this paper, we have developed a hierarchical parallelization scheme for accelerated molecular dynamics simulations with the Terfoff potentials for covalent bond solid crystals on Intel Xeon Phi coprocessor systems. The scheme exploits multi-level parallelism computing. We combine thread-level parallelism using a tightly coupled thread-level and task-level parallelism with 512-bit vector register. The simulation results show that the parallel performance of SIMD implementations on Xeon Phi is apparently superior to their x86 CPU architecture.

  15. 75 FR 48338 - Intel Corporation; Analysis of Proposed Consent Order to Aid Public Comment

    Science.gov (United States)

    2010-08-10

    ... product road maps, its compilers, and product benchmarking (Sections VI, VII, and VIII). The Proposed... alleges that Intel's failure to fully disclose the changes it made to its compilers and libraries... benchmarking organizations the effects of its compiler redesign on non-Intel CPUs. Several benchmarking...

  16. Windows for Intel Macs

    CERN Document Server

    Ogasawara, Todd

    2008-01-01

    Even the most devoted Mac OS X user may need to use Windows XP, or may just be curious about XP and its applications. This Short Cut is a concise guide for OS X users who need to quickly get comfortable and become productive with Windows XP basics on their Macs. It covers: Security Networking ApplicationsMac users can easily install and use Windows thanks to Boot Camp and Parallels Desktop for Mac. Boot Camp lets an Intel-based Mac install and boot Windows XP on its own hard drive partition. Parallels Desktop for Mac uses virtualization technology to run Windows XP (or other operating systems

  17. Optimizing Performance of Combustion Chemistry Solvers on Intel's Many Integrated Core (MIC) Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Sitaraman, Hariswaran [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Grout, Ray W [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

    2017-06-09

    This work investigates novel algorithm designs and optimization techniques for restructuring chemistry integrators in zero and multidimensional combustion solvers, which can then be effectively used on the emerging generation of Intel's Many Integrated Core/Xeon Phi processors. These processors offer increased computing performance via large number of lightweight cores at relatively lower clock speeds compared to traditional processors (e.g. Intel Sandybridge/Ivybridge) used in current supercomputers. This style of processor can be productively used for chemistry integrators that form a costly part of computational combustion codes, in spite of their relatively lower clock speeds. Performance commensurate with traditional processors is achieved here through the combination of careful memory layout, exposing multiple levels of fine grain parallelism and through extensive use of vendor supported libraries (Cilk Plus and Math Kernel Libraries). Important optimization techniques for efficient memory usage and vectorization have been identified and quantified. These optimizations resulted in a factor of ~ 3 speed-up using Intel 2013 compiler and ~ 1.5 using Intel 2017 compiler for large chemical mechanisms compared to the unoptimized version on the Intel Xeon Phi. The strategies, especially with respect to memory usage and vectorization, should also be beneficial for general purpose computational fluid dynamics codes.

  18. Permanent magnetic properties of NdFe12Nx sputtered films epitaxially grown on V buffer layer

    Science.gov (United States)

    Sato, T.; Ohsuna, T.; Yano, M.; Kato, A.; Kaneko, Y.

    2017-08-01

    To clarify the magnetic properties of the NdFe12Nx compound, which shows promise as a high-performance permanent magnet material, NdFe12Nx epitaxial films fabricated by using a V underlayer on MgO (100) single-crystalline substrates were investigated. Nd-Fe films deposited on a V underlayer consist of NdFe12 grains, which have a c-axis orientation perpendicular to the film plane, as well as α-Fe and Nd2Fe17 phases. In the Nd-Fe-N film obtained by subsequent nitridation of the Nd-Fe film, NdFe12Nx grains grew as the dominant phase, and the volume fractions of α-Fe phases dropped below 5%. A Nd-Fe-N film with a thickness of 50 nm exhibits a saturation magnetization (Ms) of 1.7 T, an anisotropy field (HA) of ˜60 kOe, a magnetocrystalline anisotropy energy (K1) of ˜4.1 MJ/m3, and a coercivity (Hc) of 1.7 kOe. The Hc of a Nd-Fe-N film with a thickness of 25 nm is 4.3 kOe. These results indicate that NdFe12Nx compounds have a superior Ms compared to Nd-Fe-B magnets, while the enhancement in Hc is indispensable.

  19. Towards Porting a Real-World Seismological Application to the Intel MIC Architecture

    OpenAIRE

    V. Weinberg

    2014-01-01

    This whitepaper aims to discuss first experiences with porting an MPI-based real-world geophysical application to the new Intel Many Integrated Core (MIC) architecture. The selected code SeisSol is an application written in Fortran that can be used to simulate earthquake rupture and radiating seismic wave propagation in complex 3-D heterogeneous materials. The PRACE prototype cluster EURORA at CINECA, Italy, was accessed to analyse the MPI-performance of SeisSol on Intel Xeon Phi on both sing...

  20. Connecting Effective Instruction and Technology. Intel-elebration: Safari.

    Science.gov (United States)

    Burton, Larry D.; Prest, Sharon

    Intel-ebration is an attempt to integrate the following research-based instructional frameworks and strategies: (1) dimensions of learning; (2) multiple intelligences; (3) thematic instruction; (4) cooperative learning; (5) project-based learning; and (6) instructional technology. This paper presents a thematic unit on safari, using the…

  1. CAMSHIFT Tracker Design Experiments With Intel OpenCV and SAI

    National Research Council Canada - National Science Library

    Francois, Alexandre R

    2004-01-01

    ... (including multi-modal) systems, must be specifically addressed. This report describes design and implementation experiments for CAMSHIFT-based tracking systems using Intel's Open Computer Vision library and SAI...

  2. Full cycle trigonometric function on Intel Quartus II Verilog

    Science.gov (United States)

    Mustapha, Muhazam; Zulkarnain, Nur Antasha

    2018-02-01

    This paper discusses about an improvement of a previous research on hardware based trigonometric calculations. Tangent function will also be implemented to get a complete set. The functions have been simulated using Quartus II where the result will be compared to the previous work. The number of bits has also been extended for each trigonometric function. The design is based on RTL due to its resource efficient nature. At earlier stage, a technology independent test bench simulation was conducted on ModelSim due to its convenience in capturing simulation data so that accuracy information can be obtained. On second stage, Intel/Altera Quartus II will be used to simulate on technology dependent platform, particularly on the one belonging to Intel/Altera itself. Real data on no. logic elements used and propagation delay have also been obtained.

  3. Accelerating the Pace of Protein Functional Annotation With Intel Xeon Phi Coprocessors.

    Science.gov (United States)

    Feinstein, Wei P; Moreno, Juana; Jarrell, Mark; Brylinski, Michal

    2015-06-01

    Intel Xeon Phi is a new addition to the family of powerful parallel accelerators. The range of its potential applications in computationally driven research is broad; however, at present, the repository of scientific codes is still relatively limited. In this study, we describe the development and benchmarking of a parallel version of eFindSite, a structural bioinformatics algorithm for the prediction of ligand-binding sites in proteins. Implemented for the Intel Xeon Phi platform, the parallelization of the structure alignment portion of eFindSite using pragma-based OpenMP brings about the desired performance improvements, which scale well with the number of computing cores. Compared to a serial version, the parallel code runs 11.8 and 10.1 times faster on the CPU and the coprocessor, respectively; when both resources are utilized simultaneously, the speedup is 17.6. For example, ligand-binding predictions for 501 benchmarking proteins are completed in 2.1 hours on a single Stampede node equipped with the Intel Xeon Phi card compared to 3.1 hours without the accelerator and 36.8 hours required by a serial version. In addition to the satisfactory parallel performance, porting existing scientific codes to the Intel Xeon Phi architecture is relatively straightforward with a short development time due to the support of common parallel programming models by the coprocessor. The parallel version of eFindSite is freely available to the academic community at www.brylinski.org/efindsite.

  4. Extension of the AMBER molecular dynamics software to Intel's Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Needham, Perri J.; Bhuiyan, Ashraf; Walker, Ross C.

    2016-04-01

    We present an implementation of explicit solvent particle mesh Ewald (PME) classical molecular dynamics (MD) within the PMEMD molecular dynamics engine, that forms part of the AMBER v14 MD software package, that makes use of Intel Xeon Phi coprocessors by offloading portions of the PME direct summation and neighbor list build to the coprocessor. We refer to this implementation as pmemd MIC offload and in this paper present the technical details of the algorithm, including basic models for MPI and OpenMP configuration, and analyze the resultant performance. The algorithm provides the best performance improvement for large systems (>400,000 atoms), achieving a ∼35% performance improvement for satellite tobacco mosaic virus (1,067,095 atoms) when 2 Intel E5-2697 v2 processors (2 ×12 cores, 30M cache, 2.7 GHz) are coupled to an Intel Xeon Phi coprocessor (Model 7120P-1.238/1.333 GHz, 61 cores). The implementation utilizes a two-fold decomposition strategy: spatial decomposition using an MPI library and thread-based decomposition using OpenMP. We also present compiler optimization settings that improve the performance on Intel Xeon processors, while retaining simulation accuracy.

  5. Application of NX Siemens PLM software in educational process in preparing students of engineering branch

    Science.gov (United States)

    Sadchikova, G. M.

    2017-01-01

    This article discusses the results of the introduction of computer-aided design NX by Siemens Plm Software to the classes of a higher education institution. The necessity of application of modern information technologies in teaching students of engineering profile and selection of a software product is substantiated. The author describes stages of the software module study in relation to some specific courses, considers the features of NX software, which require the creation of standard and unified product databases. The article also gives examples of research carried out by the students with the various software modules.

  6. Trusted Computing Technologies, Intel Trusted Execution Technology.

    Energy Technology Data Exchange (ETDEWEB)

    Guise, Max Joseph; Wendt, Jeremy Daniel

    2011-01-01

    We describe the current state-of-the-art in Trusted Computing Technologies - focusing mainly on Intel's Trusted Execution Technology (TXT). This document is based on existing documentation and tests of two existing TXT-based systems: Intel's Trusted Boot and Invisible Things Lab's Qubes OS. We describe what features are lacking in current implementations, describe what a mature system could provide, and present a list of developments to watch. Critical systems perform operation-critical computations on high importance data. In such systems, the inputs, computation steps, and outputs may be highly sensitive. Sensitive components must be protected from both unauthorized release, and unauthorized alteration: Unauthorized users should not access the sensitive input and sensitive output data, nor be able to alter them; the computation contains intermediate data with the same requirements, and executes algorithms that the unauthorized should not be able to know or alter. Due to various system requirements, such critical systems are frequently built from commercial hardware, employ commercial software, and require network access. These hardware, software, and network system components increase the risk that sensitive input data, computation, and output data may be compromised.

  7. Radiation Failures in Intel 14nm Microprocessors

    Science.gov (United States)

    Bossev, Dobrin P.; Duncan, Adam R.; Gadlage, Matthew J.; Roach, Austin H.; Kay, Matthew J.; Szabo, Carl; Berger, Tammy J.; York, Darin A.; Williams, Aaron; LaBel, K.; hide

    2016-01-01

    In this study the 14 nm Intel Broadwell 5th generation core series 5005U-i3 and 5200U-i5 was mounted on Dell Inspiron laptops, MSI Cubi and Gigabyte Brix barebones and tested with Windows 8 and CentOS7 at idle. Heavy-ion-induced hard- and catastrophic failures do not appear to be related to the Intel 14nm Tri-Gate FinFET process. They originate from a small (9 m 140 m) area on the 32nm planar PCH die (not the CPU) as initially speculated. The hard failures seem to be due to a SEE but the exact physical mechanism has yet to be identified. Some possibilities include latch-ups, charge ion trapping or implantation, ion channels, or a combination of those (in biased conditions). The mechanism of the catastrophic failures seems related to the presence of electric power (1.05V core voltage). The 1064 nm laser mimics ionization radiation and induces soft- and hard failures as a direct result of electron-hole pair production, not heat. The 14nm FinFET processes continue to look promising for space radiation environments.

  8. Real-time data acquisition and feedback control using Linux Intel computers

    International Nuclear Information System (INIS)

    Penaflor, B.G.; Ferron, J.R.; Piglowski, D.A.; Johnson, R.D.; Walker, M.L.

    2006-01-01

    This paper describes the experiences of the DIII-D programming staff in adapting Linux based Intel computing hardware for use in real-time data acquisition and feedback control systems. Due to the highly dynamic and unstable nature of magnetically confined plasmas in tokamak fusion experiments, real-time data acquisition and feedback control systems are in routine use with all major tokamaks. At DIII-D, plasmas are created and sustained using a real-time application known as the digital plasma control system (PCS). During each experiment, the PCS periodically samples data from hundreds of diagnostic signals and provides these data to control algorithms implemented in software. These algorithms compute the necessary commands to send to various actuators that affect plasma performance. The PCS consists of a group of rack mounted Intel Xeon computer systems running an in-house customized version of the Linux operating system tailored specifically to meet the real-time performance needs of the plasma experiments. This paper provides a more detailed description of the real-time computing hardware and custom developed software, including recent work to utilize dual Intel Xeon equipped computers within the PCS

  9. Analysis of Intel IA-64 Processor Support for Secure Systems

    National Research Council Canada - National Science Library

    Unalmis, Bugra

    2001-01-01

    .... Systems could be constructed for which serious security threats would be eliminated. This thesis explores the Intel IA-64 processor's hardware support and its relationship to software for building a secure system...

  10. I-deas TMG to NX Space Systems Thermal Model Conversion and Computational Performance Comparison

    Science.gov (United States)

    Somawardhana, Ruwan

    2011-01-01

    CAD/CAE packages change on a continuous basis as the power of the tools increase to meet demands. End -users must adapt to new products as they come to market and replace legacy packages. CAE modeling has continued to evolve and is constantly becoming more detailed and complex. Though this comes at the cost of increased computing requirements Parallel processing coupled with appropriate hardware can minimize computation time. Users of Maya Thermal Model Generator (TMG) are faced with transitioning from NX I -deas to NX Space Systems Thermal (SST). It is important to understand what differences there are when changing software packages We are looking for consistency in results.

  11. Lawrence Livermore National Laboratory selects Intel Itanium 2 processors for world's most powerful Linux cluster

    CERN Multimedia

    2003-01-01

    "Intel Corporation, system manufacturer California Digital and the University of California at Lawrence Livermore National Laboratory (LLNL) today announced they are building one of the world's most powerful supercomputers. The supercomputer project, codenamed "Thunder," uses nearly 4,000 Intel® Itanium® 2 processors... is expected to be complete in January 2004" (1 page).

  12. Experience with Intel's many integrated core architecture in ATLAS software

    International Nuclear Information System (INIS)

    Fleischmann, S; Neumann, M; Kama, S; Lavrijsen, W; Vitillo, R

    2014-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks (TBB). This should make it possible to develop for both throughput and latency devices using a single code base. In ATLAS Software, track reconstruction has been shown to be a good candidate for throughput computing on GPGPU devices. In addition, the newly proposed offline parallel event-processing framework, GaudiHive, uses TBB for task scheduling. The MIC is thus, in principle, a good fit for this domain. In this paper, we report our experiences of porting to and optimizing ATLAS tracking algorithms for the MIC, comparing the programmability and relative cost/performance of the MIC against those of current GPGPUs and latency-optimized CPUs.

  13. Scaling Deep Learning Workloads: NVIDIA DGX-1/Pascal and Intel Knights Landing

    Energy Technology Data Exchange (ETDEWEB)

    Gawande, Nitin A.; Landwehr, Joshua B.; Daily, Jeffrey A.; Tallent, Nathan R.; Vishnu, Abhinav; Kerbyson, Darren J.

    2017-07-03

    Deep Learning (DL) algorithms have become ubiquitous in data analytics. As a result, major computing vendors --- including NVIDIA, Intel, AMD and IBM --- have architectural road-maps influenced by DL workloads. Furthermore, several vendors have recently advertised new computing products as accelerating DL workloads. Unfortunately, it is difficult for data scientists to quantify the potential of these different products. This paper provides a performance and power analysis of important DL workloads on two major parallel architectures: NVIDIA DGX-1 (eight Pascal P100 GPUs interconnected with NVLink) and Intel Knights Landing (KNL) CPUs interconnected with Intel Omni-Path. Our evaluation consists of a cross section of convolutional neural net workloads: CifarNet, CaffeNet, AlexNet and GoogleNet topologies using the Cifar10 and ImageNet datasets. The workloads are vendor optimized for each architecture. GPUs provide the highest overall raw performance. Our analysis indicates that although GPUs provide the highest overall performance, the gap can close for some convolutional networks; and KNL can be competitive when considering performance/watt. Furthermore, NVLink is critical to GPU scaling.

  14. Evaluation of the Intel Westmere-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2011-01-01

    One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

  15. Optimizing the updated Goddard shortwave radiation Weather Research and Forecasting (WRF) scheme for Intel Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.-L.

    2015-05-01

    Intel Many Integrated Core (MIC) ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our results of optimizing the updated Goddard shortwave radiation Weather Research and Forecasting (WRF) scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The co-processor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of Xeon Phi will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The results show that the optimizations improved performance of the original code on Xeon Phi 7120P by a factor of 1.3x.

  16. Revisiting Intel Xeon Phi optimization of Thompson cloud microphysics scheme in Weather Research and Forecasting (WRF) model

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen

    2015-10-01

    The Thompson cloud microphysics scheme is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Thompson scheme incorporates a large number of improvements. Thus, we have optimized the speed of this important part of WRF. Intel Many Integrated Core (MIC) ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our results of optimizing the Thompson microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. New optimizations for an updated Thompson scheme are discusses in this paper. The optimizations improved the performance of the original Thompson code on Xeon Phi 7120P by a factor of 1.8x. Furthermore, the same optimizations improved the performance of the Thompson on a dual socket configuration of eight core Intel Xeon E5-2670 CPUs by a factor of 1.8x compared to the original Thompson code.

  17. Investigation of roughing machining simulation by using visual basic programming in NX CAM system

    Science.gov (United States)

    Hafiz Mohamad, Mohamad; Nafis Osman Zahid, Muhammed

    2018-03-01

    This paper outlines a simulation study to investigate the characteristic of roughing machining simulation in 4th axis milling processes by utilizing visual basic programming in NX CAM systems. The selection and optimization of cutting orientation in rough milling operation is critical in 4th axis machining. The main purpose of roughing operation is to approximately shape the machined parts into finished form by removing the bulk of material from workpieces. In this paper, the simulations are executed by manipulating a set of different cutting orientation to generate estimated volume removed from the machine parts. The cutting orientation with high volume removal is denoted as an optimum value and chosen to execute a roughing operation. In order to run the simulation, customized software is developed to assist the routines. Operations build-up instructions in NX CAM interface are translated into programming codes via advanced tool available in the Visual Basic Studio. The codes is customized and equipped with decision making tools to run and control the simulations. It permits the integration with any independent program files to execute specific operations. This paper aims to discuss about the simulation program and identifies optimum cutting orientations for roughing processes. The output of this study will broaden up the simulation routines performed in NX CAM systems.

  18. Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture

    OpenAIRE

    Liu, Xu; Chen, Langshi; Firoz, Jesun S.; Qiu, Judy; Jiang, Lei

    2017-01-01

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging per...

  19. Intel Legend and CERN would build up high speed Internet

    CERN Multimedia

    2002-01-01

    Intel, Legend and China Education and Research Network jointly announced on the 25th of April that they will be cooperating with each other to build up the new generation high speed internet, over the next three years (1/2 page).

  20. Effect of Atomic Hydrogen on Preparation of Highly Moisture-Resistive SiNx Films at Low Substrate Temperatures

    Science.gov (United States)

    Heya, Akira; Niki, Toshikazu; Takano, Masahiro; Yonezawa, Yasuto; Minamikawa, Toshiharu; Muroi, Susumu; Minami, Shigehira; Izumi, Akira; Masuda, Atsushi; Umemoto, Hironobu; Matsumura, Hideki

    2004-12-01

    Highly moisture-resistive SiNx films on a Si substrate are obtained at substrate temperatures of 80°C by catalytic chemical vapor deposition (Cat-CVD) using a source gas with H2. Atomic hydrogen effected the selective etching of a weak-bond regions and an increase in atomic density induced by the energy of the surface reaction. It is concluded that Cat-CVD using H2 is a promising candidate for the fabrication of highly moisture-resistive SiNx films at low temperatures.

  1. Staggered Dslash Performance on Intel Xeon Phi Architecture

    OpenAIRE

    Li, Ruizi; Gottlieb, Steven

    2014-01-01

    The conjugate gradient (CG) algorithm is among the most essential and time consuming parts of lattice calculations with staggered quarks. We test the performance of CG and dslash, the key step in the CG algorithm, on the Intel Xeon Phi, also known as the Many Integrated Core (MIC) architecture. We try different parallelization strategies using MPI, OpenMP, and the vector processing units (VPUs).

  2. Easy fabrication of high quality nickel mold for deep polymer microfluidic channels

    International Nuclear Information System (INIS)

    Wong, Ten It; Tan, Christina Yuan Ling; Zhou, Xiaodong; Limantoro, Julian; Fong, Kin Phang; Quan, Chenggen; Sun, Ling Ling

    2016-01-01

    Mass fabrication of disposable microfluidic chips with hot embossing is a key technology for microfluidic chip based biosensors. In this work, we develop a new method of fabricating high quality and highly durable nickel molds for hot embossing polymer chips. The process involves the addition of a thick, patterned layer of negative photoresist AZ-125nxT to a 4″ silicon wafer, followed by nickel electroplating and delamination of the nickel mold. Our investigations found that compared to a pillar mask, a hole mask can minimize the diffraction effect in photolithography of a thick photoresist, reduce the adhesion of the AZ-125nxT to the photomask in photolithography, and facilitate clean development of the photoresist patterns. By optimizing the hot embossing and chip bonding parameters, microfluidic chips with deep channels are achieved. (paper)

  3. Enhancement of optical and structural quality of semipolar (11-22) GaN by introducing nanoporous SiNx interlayers

    Science.gov (United States)

    Monavarian, Morteza; Metzner, Sebastian; Izyumskaya, Natalia; Müller, Marcus; Okur, Serdal; Zhang, Fan; Can, Nuri; Das, Saikat; Avrutin, Vitaliy; Özgür, Ümit; Bertram, Frank; Christen, Juergen; Morkoç, Hadis

    2015-03-01

    Enhancement of optical and structural quality of semipolar (11‾22) GaN grown by metal-organic chemical vapor deposition on planar m-sapphire substrates was achieved by using an in-situ epitaxial lateral overgrowth (ELO) technique with nanoporous SiNx layers employed as masks. In order to optimize the procedure, the effect of SiNx deposition time was studied by steady-state photoluminescence (PL), and X-ray diffraction. The intensity of room temperature PL for the (11‾22) GaN layers grown under optimized conditions was about three times higher compared to those for the reference samples having the same thickness but no SiNx interlayers. This finding is attributed to the blockage of extended defect propagation toward the surface by the SiNx interlayers as evidenced from the suppression of emissions associated with basal-plane and prismatic stacking faults with regard to the intensity of donor bound excitons (D0X) in lowtemperature PL spectra. In agreement with the optical data, full width at half maximum values of (11‾22) X-ray rocking curves measured for two different in-plane rotational orientations of [1‾100] and [11‾23] reduced from 0.33º and 0.26º for the reference samples to 0.2º and 0.16º for the nano-ELO structures grown under optimized conditions, respectively.

  4. Hybrid Non-Isolated and Non Inverting Nx Interleaved DC-DC Multilevel Boost Converter for Renewable Energy Applications

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Kulkarni, Rishi M.; Padmanaban, Sanjeevi Kumar

    2016-01-01

    In this paper hybrid non isolated/ non inverting Nx interleaved DC-DC multilevel Boost Converter for renewable energy applications is presented. The presented hybrid topology is derived from the conventional interleaved converter and the Nx Multilevel boost converter. In renewable energy...... applications, generated energy cannot be directly used at application end. In most of the cases it needs to be stepped up with DC-DC converter at operating voltage levels as per the requirement of the application. Though conventional boost converter can theoretically be used for this purpose, but obtaining...

  5. [Home Daily Hemodialysis with NxStage System One: monocentric italian casistic results].

    Science.gov (United States)

    Brunati, Chiara; Cassaro, Franca; Cretti, Laura; Izzo, Michela; Pegoraro, Marisa; Negri, Daniela; Gervasi, Francesca; Colussi, Giacomo

    2017-09-28

    NxStage System One is a new dialytic technology based on easy setup, simplicity of use and reduced dimensions, which is increasingly in use worldwide for home hemodialysis treatments. The system utilizes a low amount of dialysate, usually 15-30 liters according to anthropometric patients' values. The dialysate is supplied at very low flux, generally about 1/3 of blood flow, in order to obtain an elevated saturation of dialysate for solutes. In these conditions the clearance of urea will be almost equal to dialysate flow rate. In order to achieve an obptimal weekly clearance evaluated by Std Kt/V the dialysis sessions are repeated six times a week. In this way a good control of blood voleme can be reached. In this paper we report our experience of treatment with NxStage System One in 12 patients from May 2011 to Dicember 2016. Copyright by Società Italiana di Nefrologia SIN, Rome, Italy.

  6. Role of SiNx Barrier Layer on the Performances of Polyimide Ga2O3-doped ZnO p-i-n Hydrogenated Amorphous Silicon Thin Film Solar Cells

    Science.gov (United States)

    Wang, Fang-Hsing; Kuo, Hsin-Hui; Yang, Cheng-Fu; Liu, Min-Chu

    2014-01-01

    In this study, silicon nitride (SiNx) thin films were deposited on polyimide (PI) substrates as barrier layers by a plasma enhanced chemical vapor deposition (PECVD) system. The gallium-doped zinc oxide (GZO) thin films were deposited on PI and SiNx/PI substrates at room temperature (RT), 100 and 200 °C by radio frequency (RF) magnetron sputtering. The thicknesses of the GZO and SiNx thin films were controlled at around 160 ± 12 nm and 150 ± 10 nm, respectively. The optimal deposition parameters for the SiNx thin films were a working pressure of 800 × 10−3 Torr, a deposition power of 20 W, a deposition temperature of 200 °C, and gas flowing rates of SiH4 = 20 sccm and NH3 = 210 sccm, respectively. For the GZO/PI and GZO-SiNx/PI structures we had found that the GZO thin films deposited at 100 and 200 °C had higher crystallinity, higher electron mobility, larger carrier concentration, smaller resistivity, and higher optical transmittance ratio. For that, the GZO thin films deposited at 100 and 200 °C on PI and SiNx/PI substrates with thickness of ~000 nm were used to fabricate p-i-n hydrogenated amorphous silicon (α-Si) thin film solar cells. 0.5% HCl solution was used to etch the surfaces of the GZO/PI and GZO-SiNx/PI substrates. Finally, PECVD system was used to deposit α-Si thin film onto the etched surfaces of the GZO/PI and GZO-SiNx/PI substrates to fabricate α-Si thin film solar cells, and the solar cells’ properties were also investigated. We had found that substrates to get the optimally solar cells’ efficiency were 200 °C-deposited GZO-SiNx/PI. PMID:28788494

  7. Role of SiNx Barrier Layer on the Performances of Polyimide Ga2O3-doped ZnO p-i-n Hydrogenated Amorphous Silicon Thin Film Solar Cells

    Directory of Open Access Journals (Sweden)

    Fang-Hsing Wang

    2014-02-01

    Full Text Available In this study, silicon nitride (SiNx thin films were deposited on polyimide (PI substrates as barrier layers by a plasma enhanced chemical vapor deposition (PECVD system. The gallium-doped zinc oxide (GZO thin films were deposited on PI and SiNx/PI substrates at room temperature (RT, 100 and 200 °C by radio frequency (RF magnetron sputtering. The thicknesses of the GZO and SiNx thin films were controlled at around 160 ± 12 nm and 150 ± 10 nm, respectively. The optimal deposition parameters for the SiNx thin films were a working pressure of 800 × 10−3 Torr, a deposition power of 20 W, a deposition temperature of 200 °C, and gas flowing rates of SiH4 = 20 sccm and NH3 = 210 sccm, respectively. For the GZO/PI and GZO-SiNx/PI structures we had found that the GZO thin films deposited at 100 and 200 °C had higher crystallinity, higher electron mobility, larger carrier concentration, smaller resistivity, and higher optical transmittance ratio. For that, the GZO thin films deposited at 100 and 200 °C on PI and SiNx/PI substrates with thickness of ~1000 nm were used to fabricate p-i-n hydrogenated amorphous silicon (α-Si thin film solar cells. 0.5% HCl solution was used to etch the surfaces of the GZO/PI and GZO-SiNx/PI substrates. Finally, PECVD system was used to deposit α-Si thin film onto the etched surfaces of the GZO/PI and GZO-SiNx/PI substrates to fabricate α-Si thin film solar cells, and the solar cells’ properties were also investigated. We had found that substrates to get the optimally solar cells’ efficiency were 200 °C-deposited GZO-SiNx/PI.

  8. Global synchronization algorithms for the Intel iPSC/860

    Science.gov (United States)

    Seidel, Steven R.; Davis, Mark A.

    1992-01-01

    In a distributed memory multicomputer that has no global clock, global processor synchronization can only be achieved through software. Global synchronization algorithms are used in tridiagonal systems solvers, CFD codes, sequence comparison algorithms, and sorting algorithms. They are also useful for event simulation, debugging, and for solving mutual exclusion problems. For the Intel iPSC/860 in particular, global synchronization can be used to ensure the most effective use of the communication network for operations such as the shift, where each processor in a one-dimensional array or ring concurrently sends a message to its right (or left) neighbor. Three global synchronization algorithms are considered for the iPSC/860: the gysnc() primitive provided by Intel, the PICL primitive sync0(), and a new recursive doubling synchronization (RDS) algorithm. The performance of these algorithms is compared to the performance predicted by communication models of both the long and forced message protocols. Measurements of the cost of shift operations preceded by global synchronization show that the RDS algorithm always synchronizes the nodes more precisely and costs only slightly more than the other two algorithms.

  9. H irradiation effects on the GaAs-like Raman modes in GaAs1-xNx/GaAs1-xNx:H planar heterostructures

    Science.gov (United States)

    Giulotto, E.; Geddo, M.; Patrini, M.; Guizzetti, G.; Felici, M.; Capizzi, M.; Polimeni, A.; Martelli, F.; Rubini, S.

    2014-12-01

    The GaAs-like longitudinal optical phonon frequency in two hydrogenated GaAs1-xNx/GaAs1-xNx:H microwire heterostructures—with similar N concentration, but different H dose and implantation conditions—has been investigated by micro-Raman mapping. In the case of GaAs0.991N0.009 wires embedded in barriers where GaAs-like properties are recovered through H irradiation, the phonon frequency in the barriers undergoes a blue shift with respect to the wires. In GaAs0.992N0.008 wires embedded in less hydrogenated barriers, the phonon frequency exhibits an opposite behavior (red shift). Strain, disorder, phonon localization effects induced by H-irradiation on the GaAs-like phonon frequency are discussed and related to different types of N-H complexes formed in the hydrogenated barriers. It is shown that the red (blue) character of the frequency shift is related to the dominant N-2H (N-3H) type of complexes. Moreover, for specific experimental conditions, an all-optical determination of the uniaxial strain field is obtained. This may improve the design of recently presented devices that exploit the correlation between uniaxial stress and the degree of polarization of photoluminescence.

  10. Scaling deep learning workloads: NVIDIA DGX-1/Pascal and Intel Knights Landing

    Energy Technology Data Exchange (ETDEWEB)

    Gawande, Nitin A.; Landwehr, Joshua B.; Daily, Jeffrey A.; Tallent, Nathan R.; Vishnu, Abhinav; Kerbyson, Darren J.

    2017-08-24

    Deep Learning (DL) algorithms have become ubiquitous in data analytics. As a result, major computing vendors --- including NVIDIA, Intel, AMD, and IBM --- have architectural road-maps influenced by DL workloads. Furthermore, several vendors have recently advertised new computing products as accelerating large DL workloads. Unfortunately, it is difficult for data scientists to quantify the potential of these different products. This paper provides a performance and power analysis of important DL workloads on two major parallel architectures: NVIDIA DGX-1 (eight Pascal P100 GPUs interconnected with NVLink) and Intel Knights Landing (KNL) CPUs interconnected with Intel Omni-Path or Cray Aries. Our evaluation consists of a cross section of convolutional neural net workloads: CifarNet, AlexNet, GoogLeNet, and ResNet50 topologies using the Cifar10 and ImageNet datasets. The workloads are vendor-optimized for each architecture. Our analysis indicates that although GPUs provide the highest overall performance, the gap can close for some convolutional networks; and the KNL can be competitive in performance/watt. We find that NVLink facilitates scaling efficiency on GPUs. However, its importance is heavily dependent on neural network architecture. Furthermore, for weak-scaling --- sometimes encouraged by restricted GPU memory --- NVLink is less important.

  11. Investigation of microstructure and properties of ultrathin graded ZrNx self-assembled diffusion barrier in deep nano-vias prepared by plasma ion immersion implantation

    Science.gov (United States)

    Zou, Jianxiong; Liu, Bo; Lin, Liwei; Lu, Yuanfu; Dong, Yuming; Jiao, Guohua; Ma, Fei; Li, Qiran

    2018-01-01

    Ultrathin graded ZrNx self-assembled diffusion barriers with controllable stoichiometry was prepared in Cu/p-SiOC:H interfaces by plasma immersion ion implantation (PIII) with dynamic regulation of implantation fluence. The fundamental relationship between the implantation fluence of N+ and the stoichiometry and thereby the electrical properties of the ZrNx barrier was established. The optimized fluence of a graded ZrN thin film with gradually decreased Zr valence was obtained with the best electrical performance as well. The Cu/p-SiOC:H integration is thermally stable up to 500 °C due to the synergistic effect of Cu3Ge and ZrNx layers. Accordingly, the PIII process was verified in a 100-nm-thick Cu dual-damascene interconnect, in which the ZrNx diffusion barrier of 1 nm thick was successfully self-assembled on the sidewall without barrier layer on the via bottom. In this case, the via resistance was reduced by approximately 50% in comparison with Ta/TaN barrier. Considering the results in this study, ultrathin ZrNx conformal diffusion barrier can be adopted in the sub-14 nm technology node.

  12. High-performance computing on the Intel Xeon Phi how to fully exploit MIC architectures

    CERN Document Server

    Wang, Endong; Shen, Bo; Zhang, Guangyong; Lu, Xiaowei; Wu, Qing; Wang, Yajuan

    2014-01-01

    The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors' first-hand optimization experience.The material is organized in three sections. The first section, "Basics of MIC", introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment

  13. Application of rapid thermal processing on SiNx thin film to solar cells

    Institute of Scientific and Technical Information of China (English)

    Youjie LI; Peiqing LUO; Zhibin ZHOU; Rongqiang CUI; Jianhua HUANG; Jingxiao WANG

    2008-01-01

    Rapid thermal processing (RTP) of SiNx thin films from PECVD with low temperature was investigated. A special processing condition of this technique which could greatly increase the minority lifetime was found in the experiments. The processing mechanism and the application of the technique to silicon solar cells fabrication were dis-cussed. A main achievement is an increase of the minority lifetime in silicon wafer with SiNx thin film by about 200% after the RTP was reached. PC-1D simulation results exhibit an enhancement of the efficiency of the solar cell by 0.42% coming from the minority lifetime improvement. The same experiment was also conducted with P-diffusion silicon wafers, but the increment of minority lifetime is just about 55%. It could be expected to improve the solar cell efficiency if it would be used in silicon solar cells fabrication with the combination of laser firing contact technique.

  14. Implementation of an Agent-Based Parallel Tissue Modelling Framework for the Intel MIC Architecture

    Directory of Open Access Journals (Sweden)

    Maciej Cytowski

    2017-01-01

    Full Text Available Timothy is a novel large scale modelling framework that allows simulating of biological processes involving different cellular colonies growing and interacting with variable environment. Timothy was designed for execution on massively parallel High Performance Computing (HPC systems. The high parallel scalability of the implementation allows for simulations of up to 109 individual cells (i.e., simulations at tissue spatial scales of up to 1 cm3 in size. With the recent advancements of the Timothy model, it has become critical to ensure appropriate performance level on emerging HPC architectures. For instance, the introduction of blood vessels supplying nutrients to the tissue is a very important step towards realistic simulations of complex biological processes, but it greatly increased the computational complexity of the model. In this paper, we describe the process of modernization of the application in order to achieve high computational performance on HPC hybrid systems based on modern Intel® MIC architecture. Experimental results on the Intel Xeon Phi™ coprocessor x100 and the Intel Xeon Phi processor x200 are presented.

  15. Protein Alignment on the Intel Xeon Phi Coprocessor

    OpenAIRE

    Ramstad, Jorun

    2015-01-01

    There is an increasing need for sensitive, high perfomance sequence alignemnet tools. With the growing databases of scientificly analyzed protein sequences, more compute power is necessary. Specialized architectures arise, and a transition from serial to specialized implementationsis is required. This thesis is a study of whether Intel 60's cores Xeon Phi coprocessor is a suitable architecture for implementation of a sequence alignment tool. The performance relative to existing tools are eval...

  16. Intel·ligència emocional a maternal

    OpenAIRE

    Missé Cortina, Jordi

    2015-01-01

    Inclusió d'activitats d'intel·ligència emocional a maternal A i B per al treball de l'adquisició de valors com l'autoestima, el respecte, la tolerància, etc. Inclusión de actividades de inteligencia emocional en maternal A y B para el trabajo de la adquisición de valores como la autoestima, el respeto, la tolerancia, etc. Practicum for the Psychology program on Educational Psychology.

  17. Communication overhead on the Intel iPSC-860 hypercube

    Science.gov (United States)

    Bokhari, Shahid H.

    1990-01-01

    Experiments were conducted on the Intel iPSC-860 hypercube in order to evaluate the overhead of interprocessor communication. It is demonstrated that: (1) contrary to popular belief, the distance between two communicating processors has a significant impact on communication time, (2) edge contention can increase communication time by a factor of more than 7, and (3) node contention has no measurable impact.

  18. Roofline Analysis in the Intel® Advisor to Deliver Optimized Performance for applications on Intel® Xeon Phi™ Processor

    Energy Technology Data Exchange (ETDEWEB)

    Koskela, Tuomas S.; Lobet, Mathieu; Deslippe, Jack; Matveev, Zakhar

    2017-05-23

    In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science applications to achieve up to 4.6 times speed-up and prepare for future exascale architectures. # Goal/Relevance of Session The roofline model [1,2] is a powerful tool for analyzing the performance of applications with respect to the theoretical peak achievable on a given computer architecture. It allows one to graphically represent the performance of an application in terms of operational intensity, i.e. the ratio of flops performed and bytes moved from memory in order to guide optimization efforts. Given the scale and complexity of modern science applications, it can often be a tedious task for the user to perform the analysis on the level of functions or loops to identify where performance gains can be made. With new Intel tools, it is now possible to automate this task, as well as base the estimates of peak performance on measurements rather than vendor specifications. The goal of this session is to demonstrate how the roofline feature of Intel Advisor can be used to balance memory vs. computation related optimization efforts and effectively identify performance bottlenecks. A series of typical optimization techniques: cache blocking, structure refactoring, data alignment, and vectorization illustrated by the kernel cases will be addressed. # Description of the codes ## XGC1 The XGC1 code [3] is a magnetic fusion Particle-In-Cell code that uses an unstructured mesh for its Poisson solver that allows it to accurately resolve the edge plasma of a magnetic fusion device. After

  19. Molecular Characterizations of Surface Proteins Hemagglutinin and Neuraminidase from Recent H5Nx Avian Influenza Viruses

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Hua; Carney, Paul J.; Mishin, Vasiliy P.; Guo, Zhu; Chang, Jessie C.; Wentworth, David E.; Gubareva, Larisa V.; Stevens, James; Schultz-Cherry, S.

    2016-04-06

    ABSTRACT

    During 2014, a subclade 2.3.4.4 highly pathogenic avian influenza (HPAI) A(H5N8) virus caused poultry outbreaks around the world. In late 2014/early 2015, the virus was detected in wild birds in Canada and the United States, and these viruses also gave rise to reassortant progeny, composed of viral RNA segments (vRNAs) from both Eurasian and North American lineages. In particular, viruses were found with N1, N2, and N8 neuraminidase vRNAs, and these are collectively referred to as H5Nx viruses. In the United States, more than 48 million domestic birds have been affected. Here we present a detailed structural and biochemical analysis of the surface antigens of H5N1, H5N2, and H5N8 viruses in addition to those of a recent human H5N6 virus. Our results with recombinant hemagglutinin reveal that these viruses have a strict avian receptor binding preference, while recombinantly expressed neuraminidases are sensitive to FDA-approved and investigational antivirals. Although H5Nx viruses currently pose a low risk to humans, it is important to maintain surveillance of these circulating viruses and to continually assess future changes that may increase their pandemic potential.

    IMPORTANCEThe H5Nx viruses emerging in North America, Europe, and Asia pose a great public health concern. Here we report a molecular and structural study of the major surface proteins of several H5Nx influenza viruses. Our results improve the understanding of these new viruses and provide important information on their receptor preferences and susceptibilities to antivirals, which are central to pandemic risk assessment.

  20. Parallel Programming with Intel Parallel Studio XE

    CERN Document Server

    Blair-Chappell , Stephen

    2012-01-01

    Optimize code for multi-core processors with Intel's Parallel Studio Parallel programming is rapidly becoming a "must-know" skill for developers. Yet, where to start? This teach-yourself tutorial is an ideal starting point for developers who already know Windows C and C++ and are eager to add parallelism to their code. With a focus on applying tools, techniques, and language extensions to implement parallelism, this essential resource teaches you how to write programs for multicore and leverage the power of multicore in your programs. Sharing hands-on case studies and real-world examples, the

  1. Evaluating the transport layer of the ALFA framework for the Intel® Xeon Phi™ Coprocessor

    Science.gov (United States)

    Santogidis, Aram; Hirstius, Andreas; Lalis, Spyros

    2015-12-01

    The ALFA framework supports the software development of major High Energy Physics experiments. As part of our research effort to optimize the transport layer of ALFA, we focus on profiling its data transfer performance for inter-node communication on the Intel Xeon Phi Coprocessor. In this article we present the collected performance measurements with the related analysis of the results. The optimization opportunities that are discovered, help us to formulate the future plans of enabling high performance data transfer for ALFA on the Intel Xeon Phi architecture.

  2. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  3. Performance tuning Weather Research and Forecasting (WRF) Goddard longwave radiative transfer scheme on Intel Xeon Phi

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2015-10-01

    Next-generation mesoscale numerical weather prediction system, the Weather Research and Forecasting (WRF) model, is a designed for dual use for forecasting and research. WRF offers multiple physics options that can be combined in any way. One of the physics options is radiance computation. The major source for energy for the earth's climate is solar radiation. Thus, it is imperative to accurately model horizontal and vertical distribution of the heating. Goddard solar radiative transfer model includes the absorption duo to water vapor,ozone, ozygen, carbon dioxide, clouds and aerosols. The model computes the interactions among the absorption and scattering by clouds, aerosols, molecules and surface. Finally, fluxes are integrated over the entire longwave spectrum.In this paper, we present our results of optimizing the Goddard longwave radiative transfer scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The optimizations improved the performance of the original Goddard longwave radiative transfer scheme on Xeon Phi 7120P by a factor of 2.2x. Furthermore, the same optimizations improved the performance of the Goddard longwave radiative transfer scheme on a dual socket configuration of eight core Intel Xeon E5-2670 CPUs by a factor of 2.1x compared to the original Goddard longwave radiative transfer scheme code.

  4. Intel Many Integrated Core (MIC) architecture optimization strategies for a memory-bound Weather Research and Forecasting (WRF) Goddard microphysics scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Goddard cloud microphysics scheme is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The WRF is a widely used weather prediction system in the world. It development is a done in collaborative around the globe. The Goddard microphysics scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Goddard scheme incorporates a large number of improvements. Thus, we have optimized the code of this important part of WRF. In this paper, we present our results of optimizing the Goddard microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The Intel MIC is capable of executing a full operating system and entire programs rather than just kernels as the GPU do. The MIC coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The results show that the optimizations improved performance of the original code on Xeon Phi 7120P by a factor of 4.7x. Furthermore, the same optimizations improved performance on a dual socket Intel Xeon E5-2670 system by a factor of 2.8x compared to the original code.

  5. Implementation of High-Order Multireference Coupled-Cluster Methods on Intel Many Integrated Core Architecture.

    Science.gov (United States)

    Aprà, E; Kowalski, K

    2016-03-08

    In this paper we discuss the implementation of multireference coupled-cluster formalism with singles, doubles, and noniterative triples (MRCCSD(T)), which is capable of taking advantage of the processing power of the Intel Xeon Phi coprocessor. We discuss the integration of two levels of parallelism underlying the MRCCSD(T) implementation with computational kernels designed to offload the computationally intensive parts of the MRCCSD(T) formalism to Intel Xeon Phi coprocessors. Special attention is given to the enhancement of the parallel performance by task reordering that has improved load balancing in the noniterative part of the MRCCSD(T) calculations. We also discuss aspects regarding efficient optimization and vectorization strategies.

  6. The NxStage System One.

    Science.gov (United States)

    Clark, William R; Turk, Joseph E

    2004-01-01

    Given the results of recent randomized controlled trials as well as staffing and budget challenges that today face many institutions across North America, a novel therapeutic approach is likely necessary to enable improvements in clinical outcomes for renal failure patients. The NxStage System One was developed to address these challenges. The system is an innovative, flexible device that delivers hemodialysis, hemofiltration, and/or ultrafiltration therapies to patients with renal failure or fluid overload. The unique characteristics of this system include a highly automated system design with a drop-in cartridge to facilitate training and simple operation; portable size and independence from dedicated infrastructure to minimize practical barriers to where therapy may be administered; use of high-quality premixed treatment fluids to enable capture of the potential clinical benefits of fluid purity without the hassles of local water treatment; and wide operating ranges to allow clinician flexibility in patient therapy prescriptions. In both the chronic and acute care environments, the System One presents clinicians with a new platform for delivering patient therapy improvements within real-world constraints.

  7. Crosstalk: The Journal of Defense Software Engineering. Volume 22, Number 2, February 2009

    Science.gov (United States)

    2009-02-01

    possible system attacks. by Ron Greenfield and Dr. Charley Tichenor Enforcing Static Program Properties to Enable Safety-Critical Use of Java Software...Assurance by Ron Greenfield and Dr. Charley Tichenor, and Dr. Kelvin Nilsen’s Enforcing Static Program Properties in Safety-Critical Java Software Components...01&lang=en>. 5. Shakespeare, William. The Tempest. 6. Intel. “How Chips are Made.” 2008 <www.intel.com/ education /making chips/preparation.htm>. 7

  8. Frequent hemodialysis with NxStage system in pediatric patients receiving maintenance hemodialysis.

    Science.gov (United States)

    Goldstein, Stuart L; Silverstein, Douglas M; Leung, Jocelyn C; Feig, Daniel I; Soletsky, Beth; Knight, Cathy; Warady, Bradley A

    2008-01-01

    Recent evidence from adult hemodialysis (HD) patient studies reveal improved biochemical control and reported health-related quality of life after transition from conventional thrice weekly to daily home maintenance HD treatment. Published pediatric frequent dialysis experiences demonstrate similar improvement but all used conventional HD machines, which employ a treated municipal water supply, thereby frequently exposing patients to proinflammatory components. We report our pediatric experience with six-times-weekly HD using the NxStage system, which uses sterile dialysis fluid to provide dialysis in the home or center setting. Four patients (weight range 38-61.4 kg) completed the 16-week study. Patients exhibited progressive reductions in casual pretreatment systolic and diastolic blood pressures, discontinuation of antihypertensive medications, and decreased blood pressure load by ambulatory blood pressure monitoring. Mean serum phosphorus improved without change in phosphorus binder medication, and all three patients with a normalized protein catabolic rate 1.1 g/kg per day. Patients reported no adverse effects. Variable changes in proinflammatory cytokine levels were observed. We suggest that frequent HD with the NxStage system be considered for children who would benefit from home-based maintenance dialysis.

  9. Porting FEASTFLOW to the Intel Xeon Phi: Lessons Learned

    OpenAIRE

    Georgios Goumas

    2014-01-01

    In this paper we report our experiences in porting the FEASTFLOW software infrastructure to the Intel Xeon Phi coprocessor. Our efforts involved both the evaluation of programming models including OpenCL, POSIX threads and OpenMP and typical optimization strategies like parallelization and vectorization. Since the straightforward porting process of the already existing OpenCL version of the code encountered performance problems that require further analysis, we focused our efforts on the impl...

  10. Single event effect testing of the Intel 80386 family and the 80486 microprocessor

    International Nuclear Information System (INIS)

    Moran, A.; LaBel, K.; Gates, M.; Seidleck, C.; McGraw, R.; Broida, M.; Firer, J.; Sprehn, S.

    1996-01-01

    The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored

  11. Prototype design based on NX subdivision modeling application

    Science.gov (United States)

    Zhan, Xianghui; Li, Xiaoda

    2018-04-01

    Prototype design is an important part of the product design, through a quick and easy way to draw a three-dimensional product prototype. Combined with the actual production, the prototype could be modified several times, resulting in a highly efficient and reasonable design before the formal design. Subdivision modeling is a common method of modeling product prototypes. Through Subdivision modeling, people can in a short time with a simple operation to get the product prototype of the three-dimensional model. This paper discusses the operation method of Subdivision modeling for geometry. Take a vacuum cleaner as an example, the NX Subdivision modeling functions are applied. Finally, the development of Subdivision modeling is forecasted.

  12. Crystal and Electronic Structures, Photoluminescence Properties of Eu2+-Doped Novel Oxynitride Ba4Si6O16-3x/2Nx

    Directory of Open Access Journals (Sweden)

    Takashi Takeda

    2010-03-01

    Full Text Available The crystal structure and the photoluminescence properties of novel green Ba4-yEuySi6O16-3x/2Nx phosphors were investigated. The electronic structures of the Ba4Si6O16 host were calculated by first principles pseudopotential method based on density functional theory. The results reveal that the top of the valence bands are dominated by O-2p states hybridized with Ba-6s and Si-3p states, while the conduction bands are mainly determined by Ba-6s states for the host, which is an insulator with a direct energy gap of 4.6 eV at Γ. A small amount of nitrogen can be incorporated into the host to replace oxygen and forms Ba4-yEuySi6O16-3x/2Nx solid solutions crystallized in a monoclinic (space group P21/c, Z = 2 having the lattice parameters a = 12.4663(5 Å, b = 4.6829(2 Å, c = 13.9236(6 Å, and β = 93.61(1°, with a maximum solubility of nitrogen at about x = 0.1. Ba4Si6O16-3x/2Nx:Eu2+ exhibits efficient green emission centered at 515–525 nm varying with the Eu2+ concentration when excited under UV to 400 nm. Furthermore, the incorporation of nitrogen can slightly enhance the photoluminescence intensity. Excitation in the UV-blue spectral range (λexc = 375 nm, the absorption and quantum efficiency of Ba4-yEuySi6O16-3x/2Nx (x = 0.1, y = 0.2 reach about 80% and 46%, respectively. Through further improvement of the thermal stability, novel green phosphor of Ba4-yEuySi6O16-3x/2Nx is promising for application in white UV-LEDs.

  13. CFD Analysis of Thermal Control System Using NX Thermal and Flow

    Science.gov (United States)

    Fortier, C. R.; Harris, M. F. (Editor); McConnell, S. (Editor)

    2014-01-01

    The Thermal Control Subsystem (TCS) is a key part of the Advanced Plant Habitat (APH) for the International Space Station (ISS). The purpose of this subsystem is to provide thermal control, mainly cooling, to the other APH subsystems. One of these subsystems, the Environmental Control Subsystem (ECS), controls the temperature and humidity of the growth chamber (GC) air to optimize the growth of plants in the habitat. The TCS provides thermal control to the ECS with three cold plates, which use Thermoelectric Coolers (TECs) to heat or cool water as needed to control the air temperature in the ECS system. In order to optimize the TCS design, pressure drop and heat transfer analyses were needed. The analysis for this system was performed in Siemens NX Thermal/Flow software (Version 8.5). NX Thermal/Flow has the ability to perform 1D or 3D flow solutions. The 1D flow solver can be used to represent simple geometries, such as pipes and tubes. The 1D flow method also has the ability to simulate either fluid only or fluid and wall regions. The 3D flow solver is similar to other Computational Fluid Dynamic (CFD) software. TCS performance was analyzed using both the 1D and 3D solvers. Each method produced different results, which will be evaluated and discussed.

  14. Neutron induced reactions II: (n,x) reactions on medium and heavy nuclei

    International Nuclear Information System (INIS)

    Cindro, N.

    1976-01-01

    Recent interest in (n,x) reactions in the MeV and above range of energies is concentrated on two main subjects: the mechanism of nucleon emission (precompound in particular) and the possible role of clustering in the emission of complex particles. Hence the first two sections of this paper will be devoted to these two subjects. In the last section some other subjects that have recently emerged in the field are discussed

  15. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™

    OpenAIRE

    Gomes, Jeremias M.; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H.

    2015-01-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel® Xeon Phi™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP’s irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high perfo...

  16. Space modeling with SolidWorks and NX

    CERN Document Server

    Duhovnik, Jože; Drešar, Primož

    2015-01-01

    Through a series of step-by-step tutorials and numerous hands-on exercises, this book aims to equip the reader with both a good understanding of the importance of space in the abstract world of engineers and the ability to create a model of a product in virtual space – a skill essential for any designer or engineer who needs to present ideas concerning a particular product within a professional environment. The exercises progress logically from the simple to the more complex; while SolidWorks or NX is the software used, the underlying philosophy is applicable to all modeling software. In each case, the explanation covers the entire procedure from the basic idea and production capabilities through to the real model; the conversion from 3D model to 2D manufacturing drawing is also clearly explained. Topics covered include modeling of prism, axisymmetric, symmetric, and sophisticated shapes; digitization of physical models using modeling software; creation of a CAD model starting from a physical model; free fo...

  17. The ML1Nx2 Phosphatidylinositol 3,5-Bisphosphate Probe Shows Poor Selectivity in Cells.

    Science.gov (United States)

    Hammond, Gerald R V; Takasuga, Shunsuke; Sasaki, Takehiko; Balla, Tamas

    2015-01-01

    Phosphatidylinositol (3,5)-bisphosphate (PtdIns(3,5)P2) is a quantitatively minor phospholipid in eukaryotic cells that plays a fundamental role in regulating endocytic membrane traffic. Despite its clear importance for cellular function and organism physiology, mechanistic details of its biology have so far not been fully elucidated. In part, this is due to a lack of experimental tools that specifically probe for PtdIns(3,5)P2 in cells to unambiguously identify its dynamics and site(s) of action. In this study, we have evaluated a recently reported PtdIns(3,5)P2 biosensor, GFP-ML1Nx2, for its veracity as such a probe. We report that, in live cells, the localization of this biosensor to sub-cellular compartments is largely independent of PtdIns(3,5)P2, as assessed after pharmacological, chemical genetic or genomic interventions that block the lipid's synthesis. We therefore conclude that it is unwise to interpret the localization of ML1Nx2 as a true and unbiased biosensor for PtdIns(3,5)P2.

  18. Optimizing the MapReduce Framework on Intel Xeon Phi Coprocessor

    OpenAIRE

    Lu, Mian; Zhang, Lei; Huynh, Huynh Phung; Ong, Zhongliang; Liang, Yun; He, Bingsheng; Goh, Rick Siow Mong; Huynh, Richard

    2013-01-01

    With the ease-of-programming, flexibility and yet efficiency, MapReduce has become one of the most popular frameworks for building big-data applications. MapReduce was originally designed for distributed-computing, and has been extended to various architectures, e,g, multi-core CPUs, GPUs and FPGAs. In this work, we focus on optimizing the MapReduce framework on Xeon Phi, which is the latest product released by Intel based on the Many Integrated Core Architecture. To the best of our knowledge...

  19. Does the Intel Xeon Phi processor fit HEP workloads?

    Science.gov (United States)

    Nowak, A.; Bitzes, G.; Dotti, A.; Lazzaro, A.; Jarp, S.; Szostek, P.; Valsan, L.; Botezatu, M.; Leduc, J.

    2014-06-01

    This paper summarizes the five years of CERN openlab's efforts focused on the Intel Xeon Phi co-processor, from the time of its inception to public release. We consider the architecture of the device vis a vis the characteristics of HEP software and identify key opportunities for HEP processing, as well as scaling limitations. We report on improvements and speedups linked to parallelization and vectorization on benchmarks involving software frameworks such as Geant4 and ROOT. Finally, we extrapolate current software and hardware trends and project them onto accelerators of the future, with the specifics of offline and online HEP processing in mind.

  20. Profiling CPU-bound workloads on Intel Haswell-EP platforms

    CERN Document Server

    Guerri, Marco; Cristovao, Cordeiro; CERN. Geneva. IT Department

    2017-01-01

    With the increasing adoption of public and private cloud resources to support the demands in terms of computing capacity of the WLCG, the HEP community has begun studying several benchmarking applications aimed at continuously assessing the performance of virtual machines procured from commercial providers. In order to characterise the behaviour of these benchmarks, in-depth profiling activities have been carried out. In this document we outline our experience in profiling one specific application, the ATLAS Kit Validation, in an attempt to explain an unexpected distribution in the performance samples obtained on systems based on Intel Haswell-EP processors.

  1. Evaluation of the Intel Xeon Phi 7120 and NVIDIA K80 as accelerators for two-dimensional panel codes.

    Science.gov (United States)

    Einkemmer, Lukas

    2017-01-01

    To optimize the geometry of airfoils for a specific application is an important engineering problem. In this context genetic algorithms have enjoyed some success as they are able to explore the search space without getting stuck in local optima. However, these algorithms require the computation of aerodynamic properties for a significant number of airfoil geometries. Consequently, for low-speed aerodynamics, panel methods are most often used as the inner solver. In this paper we evaluate the performance of such an optimization algorithm on modern accelerators (more specifically, the Intel Xeon Phi 7120 and the NVIDIA K80). For that purpose, we have implemented an optimized version of the algorithm on the CPU and Xeon Phi (based on OpenMP, vectorization, and the Intel MKL library) and on the GPU (based on CUDA and the MAGMA library). We present timing results for all codes and discuss the similarities and differences between the three implementations. Overall, we observe a speedup of approximately 2.5 for adding an Intel Xeon Phi 7120 to a dual socket workstation and a speedup between 3.4 and 3.8 for adding a NVIDIA K80 to a dual socket workstation.

  2. Why K-12 IT Managers and Administrators Are Embracing the Intel-Based Mac

    Science.gov (United States)

    Technology & Learning, 2007

    2007-01-01

    Over the past year, Apple has dramatically increased its share of the school computer marketplace--especially in the category of notebook computers. A recent study conducted by Grunwald Associates and Rockman et al. reports that one of the major reasons for this growth is Apple's introduction of the Intel processor to the entire line of Mac…

  3. Autonomous controller (JCAM 10) for CAMAC crate with 8080 (INTEL) microprocessor

    International Nuclear Information System (INIS)

    Gallice, P.; Mathis, M.

    1975-01-01

    The CAMAC crate autonomous controller JCAM-10 is designed around an INTEL 8080 microprocessor in association with a 5K RAM and 4K REPROM memory. The concept of the module is described, in which data transfers between CAMAC modules and the memory are optimised from software point of view as well as from execution time. In fact, the JCAM-10 is a microcomputer with a set of 1000 peripheral units represented by the CAMAC modules commercially available

  4. Mashup d'aplicacions basat en un buscador intel·ligent

    OpenAIRE

    Sancho Piqueras, Javier

    2010-01-01

    Mashup de funcionalitats, basat en un cercador intel·ligent, en aquest cas pensat per a cursos, carreres màsters, etc. La finalitat és adjuntar diverses aplicacions amb l'únic propòsit que en aquest cas és un buscador però que també ens permet utilitzar eines per a la connectivitat mitjançant web Services, o xarxes socials. Mashup de funcionalidades, basado en un buscador inteligente, en este caso pensado para cursos, carreras másters, etc. La finalidad es juntar diversas aplicaciones con ...

  5. Performance Evaluation of an Intel Haswell- and Ivy Bridge-Based Supercomputer Using Scientific and Engineering Applications

    Science.gov (United States)

    Saini, Subhash; Hood, Robert T.; Chang, Johnny; Baron, John

    2016-01-01

    We present a performance evaluation conducted on a production supercomputer of the Intel Xeon Processor E5- 2680v3, a twelve-core implementation of the fourth-generation Haswell architecture, and compare it with Intel Xeon Processor E5-2680v2, an Ivy Bridge implementation of the third-generation Sandy Bridge architecture. Several new architectural features have been incorporated in Haswell including improvements in all levels of the memory hierarchy as well as improvements to vector instructions and power management. We critically evaluate these new features of Haswell and compare with Ivy Bridge using several low-level benchmarks including subset of HPCC, HPCG and four full-scale scientific and engineering applications. We also present a model to predict the performance of HPCG and Cart3D within 5%, and Overflow within 10% accuracy.

  6. Xeon Phi - A comparison between the newly introduced MIC architecture and a standard CPU through three types of problems.

    OpenAIRE

    Kristiansen, Joakim

    2016-01-01

    As Moore s law continues, processors keep getting more cores packed together on the chip. This thesis is an empirical study of the rather newly introduced Intel Many Integrated Core (IMIC) architecture found in the Intel Xeon Phi. With roughly 60 cores connected by a high performance on-die interconnect, the Intel Xeon Phi makes an interesting candidate for High Performance Computing. By digging into parallel algorithms solving three well known problems, our goal is to optimize, test and comp...

  7. Does the Intel Xeon Phi processor fit HEP workloads?

    International Nuclear Information System (INIS)

    Nowak, A; Bitzes, G; Dotti, A; Lazzaro, A; Jarp, S; Szostek, P; Valsan, L; Botezatu, M; Leduc, J

    2014-01-01

    This paper summarizes the five years of CERN openlab's efforts focused on the Intel Xeon Phi co-processor, from the time of its inception to public release. We consider the architecture of the device vis a vis the characteristics of HEP software and identify key opportunities for HEP processing, as well as scaling limitations. We report on improvements and speedups linked to parallelization and vectorization on benchmarks involving software frameworks such as Geant4 and ROOT. Finally, we extrapolate current software and hardware trends and project them onto accelerators of the future, with the specifics of offline and online HEP processing in mind.

  8. OpenMP GNU and Intel Fortran programs for solving the time-dependent Gross-Pitaevskii equation

    Science.gov (United States)

    Young-S., Luis E.; Muruganandam, Paulsamy; Adhikari, Sadhan K.; Lončar, Vladimir; Vudragović, Dušan; Balaž, Antun

    2017-11-01

    speedups of the supplied 2d and 3d programs are larger than those of 1d programs. Also, for a single program the speedup increases with the size of the spatial grid, i.e., with the number of spatial discretization points, since this increases the amount of calculations performed by the program. To demonstrate this, we tested the supplied real2d-th program and varied the number of spatial discretization points NX=NY from 20 to 1000. The measured speedup obtained when running this program on 19 CPU cores as a function of the number of discretization points is shown in Fig. 2. The speedup first increases rapidly with the number of discretization points and eventually saturates. Additional comments: Example inputs provided with the programs take less than 30 minutes to run on a workstation with two Intel Xeon E5-2650 v3 processors (2 QPI links, 10 CPU cores, 25 MB cache, 2.3 GHz).

  9. Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

    OpenAIRE

    Stanic, Milan; Palomar, Oscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman; Cristal, Adrian; Valero, Mateo

    2014-01-01

    Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if Graph500 is suitable for vectorization mostly due a lack of vector memory instructions for irregular memory accesses. The Xeon Phi is a massively parallel processor recently released by Intel with new features such as a wide 512-bit vector unit and vector scatter/gather instru...

  10. 3-D electromagnetic plasma particle simulations on the Intel Delta parallel computer

    International Nuclear Information System (INIS)

    Wang, J.; Liewer, P.C.

    1994-01-01

    A three-dimensional electromagnetic PIC code has been developed on the 512 node Intel Touchstone Delta MIMD parallel computer. This code is based on the General Concurrent PIC algorithm which uses a domain decomposition to divide the computation among the processors. The 3D simulation domain can be partitioned into 1-, 2-, or 3-dimensional sub-domains. Particles must be exchanged between processors as they move among the subdomains. The Intel Delta allows one to use this code for very-large-scale simulations (i.e. over 10 8 particles and 10 6 grid cells). The parallel efficiency of this code is measured, and the overall code performance on the Delta is compared with that on Cray supercomputers. It is shown that their code runs with a high parallel efficiency of ≥ 95% for large size problems. The particle push time achieved is 115 nsecs/particle/time step for 162 million particles on 512 nodes. Comparing with the performance on a single processor Cray C90, this represents a factor of 58 speedup. The code uses a finite-difference leap frog method for field solve which is significantly more efficient than fast fourier transforms on parallel computers. The performance of this code on the 128 node Cray T3D will also be discussed

  11. Practical Implementation of Lattice QCD Simulation on Intel Xeon Phi Knights Landing

    OpenAIRE

    Kanamori, Issaku; Matsufuru, Hideo

    2017-01-01

    We investigate implementation of lattice Quantum Chromodynamics (QCD) code on the Intel Xeon Phi Knights Landing (KNL). The most time consuming part of the numerical simulations of lattice QCD is a solver of linear equation for a large sparse matrix that represents the strong interaction among quarks. To establish widely applicable prescriptions, we examine rather general methods for the SIMD architecture of KNL, such as using intrinsics and manual prefetching, to the matrix multiplication an...

  12. Optimizing zonal advection of the Advanced Research WRF (ARW) dynamics for Intel MIC

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Weather Research and Forecast (WRF) model is the most widely used community weather forecast and research model in the world. There are two distinct varieties of WRF. The Advanced Research WRF (ARW) is an experimental, advanced research version featuring very high resolution. The WRF Nonhydrostatic Mesoscale Model (WRF-NMM) has been designed for forecasting operations. WRF consists of dynamics code and several physics modules. The WRF-ARW core is based on an Eulerian solver for the fully compressible nonhydrostatic equations. In the paper, we will use Intel Intel Many Integrated Core (MIC) architecture to substantially increase the performance of a zonal advection subroutine for optimization. It is of the most time consuming routines in the ARW dynamics core. Advection advances the explicit perturbation horizontal momentum equations by adding in the large-timestep tendency along with the small timestep pressure gradient tendency. We will describe the challenges we met during the development of a high-speed dynamics code subroutine for MIC architecture. Furthermore, lessons learned from the code optimization process will be discussed. The results show that the optimizations improved performance of the original code on Xeon Phi 5110P by a factor of 2.4x.

  13. Results from a MA16-based neural trigger in an experiment looking for beauty

    Energy Technology Data Exchange (ETDEWEB)

    Baldanza, C. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Beichter, J. [Siemens AG, ZFE T ME2, 81730 Munich (Germany); Bisi, F. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Bruels, N. [Siemens AG, ZFE T ME2, 81730 Munich (Germany); Bruschini, C. [INFN/Genoa, Via Dodecaneso 33, 16146 Genoa (Italy); Cotta-Ramusino, A. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); D`Antone, I. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Malferrari, L. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Mazzanti, P. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Musico, P. [INFN/Genoa, Via Dodecaneso 33, 16146 Genoa (Italy); Novelli, P. [INFN/Genoa, Via Dodecaneso 33, 16146 Genoa (Italy); Odorici, F. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Odorico, R. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy); Passaseo, M. [CERN, 1211 Geneva 23 (Switzerland); Zuffa, M. [Istituto Nazionale di Fisica Nucleare, Bologna (Italy)

    1996-07-11

    Results from a neural-network trigger based on the digital MA16 chip of Siemens are reported. The neural trigger has been applied to data from the WA92 experiment, looking for beauty particles, which have been collected during a run in which a neural trigger module based on Intel`s analog neural chip ETANN operated, as already reported. The MA16 board hosting the chip has a 16-bit I/O precision and a 53-bit precision for internal calculations. It operated at 50 MHz, yielding a response time for a 16 input-variable net of 3 {mu}s for a Fisher discriminant (1-layer net) and of 6 {mu}s for a 2-layer net. Results are compared with those previously obtained with the ETANN trigger. (orig.).

  14. Reflective memory recorder upgrade: an opportunity to benchmark PowerPC and Intel architectures for real time

    Science.gov (United States)

    Abuter, Roberto; Tischer, Helmut; Frahm, Robert

    2014-07-01

    Several high frequency loops are required to run the VLTI (Very Large Telescope Interferometer) 2, e.g. for fringe tracking11, 5, angle tracking, vibration cancellation, data capture. All these loops rely on low latency real time computers based on the VME bus, Motorola PowerPC14 hardware architecture. In this context, one highly demanding application in terms of cycle time, latency and data transfer volume is the VLTI centralized recording facility, so called, RMN recorder1 (Reflective Memory Recorder). This application captures and transfers data flowing through the distributed memory of the system in real time. Some of the VLTI data producers are running with frequencies up to 8 KHz. With the evolution from first generation instruments like MIDI3, PRIMA5, and AMBER4 which use one or two baselines, to second generation instruments like MATISSE10 and GRAVITY9 which will use all six baselines simultaneously, the quantity of signals has increased by, at least, a factor of six. This has led to a significant overload of the RMN recorder1 which has reached the natural limits imposed by the underlying hardware. At the same time, new, more powerful computers, based on the Intel multicore families of CPUs and PCI buses have become available. With the purpose of improving the performance of the RMN recorder1 application and in order to make it capable of coping with the demands of the new generation instruments, a slightly modified implementation has been developed and integrated into an Intel based multicore computer15 running the VxWorks17 real time operating system. The core of the application is based on the standard VLT software framework for instruments13. The real time task reads from the reflective memory using the onboard DMA access12 and captured data is transferred to the outside world via a TCP socket on a dedicated Ethernet connection. The diversity of the software and hardware that are involved makes this application suitable as a benchmarking platform. A

  15. Modeling and simulation of five-axis virtual machine based on NX

    Science.gov (United States)

    Li, Xiaoda; Zhan, Xianghui

    2018-04-01

    Virtual technology in the machinery manufacturing industry has shown the role of growing. In this paper, the Siemens NX software is used to model the virtual CNC machine tool, and the parameters of the virtual machine are defined according to the actual parameters of the machine tool so that the virtual simulation can be carried out without loss of the accuracy of the simulation. How to use the machine builder of the CAM module to define the kinematic chain and machine components of the machine is described. The simulation of virtual machine can provide alarm information of tool collision and over cutting during the process to users, and can evaluate and forecast the rationality of the technological process.

  16. Digital development of products with NX9 for academical areas

    Science.gov (United States)

    Goanta, A. M.

    2015-11-01

    International competitiveness forced the manufacturing enterprises to look for new ways to accelerate the development of digital products through innovation, global alliances and strategic partnerships. In an environment of global research and development of distributed geographically, all members of the joint teams made up of companies and universities need to access updated and accurate information about products created by any of the type employed, student, teacher. Current design processes involve more complex products consisting of elements of design created by multiple teams, disciplines and suppliers using independent CAD systems. Even when using a 3D CAD mature technology, many companies fail to significantly reduce losses in the process, improve product quality or product type to ensure successful innovations to market arouse interest. These challenges require a radical rethinking of the business model, which belongs to the field of design, which must be based on digital development of products based on integrated files. Through this work, the author has proposed to provide both synthesis and transformations brought news of the integrated NX [1, 2, 3] from Siemens PLM Software 9, following a news results detailed documentary study, and personal results obtained by applying the same version, the digital and integrated development of a product type device test beams. Based on educational license received for NX 9 was made a detailed study of the innovations made by this release, and the application of some of them went to graphical modelling and getting all the documentation of a test device bearing beams. Also, were synthesized in terms of methodology, the steps to take to obtain graphical documentation. The results consist of: 3D models of all parts and assembly 3D model of the three-dimensional constraints of all component parts and not least respectively all drawings and assembly drawing. The most important consequence of the paper is the obtaining of

  17. DBPQL: A view-oriented query language for the Intel Data Base Processor

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    An interactive query language (BDPQL) for the Intel Data Base Processor (DBP) is defined. DBPQL includes a parser generator package which permits the analyst to easily create and manipulate the query statement syntax and semantics. The prototype language, DBPQL, includes trace and performance commands to aid the analyst when implementing new commands and analyzing the execution characteristics of the DBP. The DBPQL grammar file and associated key procedures are included as an appendix to this report.

  18. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  19. Game-Based Experiential Learning in Online Management Information Systems Classes Using Intel's IT Manager 3

    Science.gov (United States)

    Bliemel, Michael; Ali-Hassan, Hossam

    2014-01-01

    For several years, we used Intel's flash-based game "IT Manager 3: Unseen Forces" as an experiential learning tool, where students had to act as a manager making real-time prioritization decisions about repairing computer problems, training and upgrading systems with better technologies as well as managing increasing numbers of technical…

  20. Acceleration of Blender Cycles Path-Tracing Engine Using Intel Many Integrated Core Architecture

    OpenAIRE

    Jaroš , Milan; Říha , Lubomír; Strakoš , Petr; Karásek , Tomáš; Vašatová , Alena; Jarošová , Marta; Kozubek , Tomáš

    2015-01-01

    Part 2: Algorithms; International audience; This paper describes the acceleration of the most computationally intensive kernels of the Blender rendering engine, Blender Cycles, using Intel Many Integrated Core architecture (MIC). The proposed parallelization, which uses OpenMP technology, also improves the performance of the rendering engine when running on multi-core CPUs and multi-socket servers. Although the GPU acceleration is already implemented in Cycles, its functionality is limited. O...

  1. Optimizing the Betts-Miller-Janjic cumulus parameterization with Intel Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.-L.

    2015-10-01

    The schemes of cumulus parameterization are responsible for the sub-grid-scale effects of convective and/or shallow clouds, and intended to represent vertical fluxes due to unresolved updrafts and downdrafts and compensating motion outside the clouds. Some schemes additionally provide cloud and precipitation field tendencies in the convective column, and momentum tendencies due to convective transport of momentum. The schemes all provide the convective component of surface rainfall. Betts-Miller-Janjic (BMJ) is one scheme to fulfill such purposes in the weather research and forecast (WRF) model. National Centers for Environmental Prediction (NCEP) has tried to optimize the BMJ scheme for operational application. As there are no interactions among horizontal grid points, this scheme is very suitable for parallel computation. With the advantage of Intel Xeon Phi Many Integrated Core (MIC) architecture, efficient parallelization and vectorization essentials, it allows us to optimize the BMJ scheme. If compared to the original code respectively running on one CPU socket (eight cores) and on one CPU core with Intel Xeon E5-2670, the MIC-based optimization of this scheme running on Xeon Phi coprocessor 7120P improves the performance by 2.4x and 17.0x, respectively.

  2. Application of Intel Many Integrated Core (MIC) accelerators to the Pleim-Xiu land surface scheme

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2015-10-01

    The land-surface model (LSM) is one physics process in the weather research and forecast (WRF) model. The LSM includes atmospheric information from the surface layer scheme, radiative forcing from the radiation scheme, and precipitation forcing from the microphysics and convective schemes, together with internal information on the land's state variables and land-surface properties. The LSM is to provide heat and moisture fluxes over land points and sea-ice points. The Pleim-Xiu (PX) scheme is one LSM. The PX LSM features three pathways for moisture fluxes: evapotranspiration, soil evaporation, and evaporation from wet canopies. To accelerate the computation process of this scheme, we employ Intel Xeon Phi Many Integrated Core (MIC) Architecture as it is a multiprocessor computer structure with merits of efficient parallelization and vectorization essentials. Our results show that the MIC-based optimization of this scheme running on Xeon Phi coprocessor 7120P improves the performance by 2.3x and 11.7x as compared to the original code respectively running on one CPU socket (eight cores) and on one CPU core with Intel Xeon E5-2670.

  3. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  4. Acceleration of Cherenkov angle reconstruction with the new Intel Xeon/FPGA compute platform for the particle identification in the LHCb Upgrade

    Science.gov (United States)

    Faerber, Christian

    2017-10-01

    The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40 MHz. This increases the data bandwidth from the detector down to the Event Filter farm to 40 TBit/s, which also has to be processed to select the interesting proton-proton collision for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new Event Filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade the usage of an experimental FPGA accelerated computing platform in the Event Building or in the Event Filter farm is being considered and therefore tested. This platform from Intel hosts a general CPU and a high performance FPGA linked via a high speed link which is for this platform a QPI link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. As a first step, a computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported in Verilog to the Intel Xeon/FPGA platform and accelerated by a factor of 35. The same algorithm was ported to the Intel Xeon/FPGA platform with OpenCL. The implementation work and the performance will be compared. Also another FPGA accelerator the Nallatech 385 PCIe accelerator with the same Stratix V FPGA were tested for performance. The results show that the Intel

  5. CALTRANS: A parallel, deterministic, 3D neutronics code

    Energy Technology Data Exchange (ETDEWEB)

    Carson, L.; Ferguson, J.; Rogers, J.

    1994-04-01

    Our efforts to parallelize the deterministic solution of the neutron transport equation has culminated in a new neutronics code CALTRANS, which has full 3D capability. In this article, we describe the layout and algorithms of CALTRANS and present performance measurements of the code on a variety of platforms. Explicit implementation of the parallel algorithms of CALTRANS using both the function calls of the Parallel Virtual Machine software package (PVM 3.2) and the Meiko CS-2 tagged message passing library (based on the Intel NX/2 interface) are provided in appendices.

  6. Implementation of 5-layer thermal diffusion scheme in weather research and forecasting model with Intel Many Integrated Cores

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2014-10-01

    For weather forecasting and research, the Weather Research and Forecasting (WRF) model has been developed, consisting of several components such as dynamic solvers and physical simulation modules. WRF includes several Land- Surface Models (LSMs). The LSMs use atmospheric information, the radiative and precipitation forcing from the surface layer scheme, the radiation scheme, and the microphysics/convective scheme all together with the land's state variables and land-surface properties, to provide heat and moisture fluxes over land and sea-ice points. The WRF 5-layer thermal diffusion simulation is an LSM based on the MM5 5-layer soil temperature model with an energy budget that includes radiation, sensible, and latent heat flux. The WRF LSMs are very suitable for massively parallel computation as there are no interactions among horizontal grid points. The features, efficient parallelization and vectorization essentials, of Intel Many Integrated Core (MIC) architecture allow us to optimize this WRF 5-layer thermal diffusion scheme. In this work, we present the results of the computing performance on this scheme with Intel MIC architecture. Our results show that the MIC-based optimization improved the performance of the first version of multi-threaded code on Xeon Phi 5110P by a factor of 2.1x. Accordingly, the same CPU-based optimizations improved the performance on Intel Xeon E5- 2603 by a factor of 1.6x as compared to the first version of multi-threaded code.

  7. Estimation of the Binding Free Energy of AC1NX476 to HIV-1 Protease Wild Type and Mutations Using Free Energy Perturbation Method.

    Science.gov (United States)

    Ngo, Son Tung; Mai, Binh Khanh; Hiep, Dinh Minh; Li, Mai Suan

    2015-10-01

    The binding mechanism of AC1NX476 to HIV-1 protease wild type and mutations was studied by the docking and molecular dynamics simulations. The binding free energy was calculated using the double-annihilation binding free energy method. It is shown that the binding affinity of AC1NX476 to wild type is higher than not only ritonavir but also darunavir, making AC1NX476 become attractive candidate for HIV treatment. Our theoretical results are in excellent agreement with the experimental data as the correlation coefficient between calculated and experimentally measured binding free energies R = 0.993. Residues Asp25-A, Asp29-A, Asp30-A, Ile47-A, Gly48-A, and Val50-A from chain A, and Asp25-B from chain B play a crucial role in the ligand binding. The mutations were found to reduce the receptor-ligand interaction by widening the binding cavity, and the binding propensity is mainly driven by the van der Waals interaction. Our finding may be useful for designing potential drugs to combat with HIV. © 2015 John Wiley & Sons A/S.

  8. Applying the roofline performance model to the intel xeon phi knights landing processor

    OpenAIRE

    Doerfler, D; Deslippe, J; Williams, S; Oliker, L; Cook, B; Kurth, T; Lobet, M; Malas, T; Vay, JL; Vincenti, H

    2016-01-01

    � Springer International Publishing AG 2016. The Roofline Performance Model is a visually intuitive method used to bound the sustained peak floating-point performance of any given arithmetic kernel on any given processor architecture. In the Roofline, performance is nominally measured in floating-point operations per second as a function of arithmetic intensity (operations per byte of data). In this study we determine the Roofline for the Intel Knights Landing (KNL) processor, determining t...

  9. Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator

    OpenAIRE

    Hofmann, Johannes; Treibig, Jan; Hager, Georg; Wellein, Gerhard

    2013-01-01

    We examine the Xeon Phi, which is based on Intel's Many Integrated Cores architecture, for its suitability to run the FDK algorithm--the most commonly used algorithm to perform the 3D image reconstruction in cone-beam computed tomography. We study the challenges of efficiently parallelizing the application and means to enable sensible data sharing between threads despite the lack of a shared last level cache. Apart from parallelization, SIMD vectorization is critical for good performance on t...

  10. Acceleration of Monte Carlo simulation of photon migration in complex heterogeneous media using Intel many-integrated core architecture.

    Science.gov (United States)

    Gorshkov, Anton V; Kirillin, Mikhail Yu

    2015-08-01

    Over two decades, the Monte Carlo technique has become a gold standard in simulation of light propagation in turbid media, including biotissues. Technological solutions provide further advances of this technique. The Intel Xeon Phi coprocessor is a new type of accelerator for highly parallel general purpose computing, which allows execution of a wide range of applications without substantial code modification. We present a technical approach of porting our previously developed Monte Carlo (MC) code for simulation of light transport in tissues to the Intel Xeon Phi coprocessor. We show that employing the accelerator allows reducing computational time of MC simulation and obtaining simulation speed-up comparable to GPU. We demonstrate the performance of the developed code for simulation of light transport in the human head and determination of the measurement volume in near-infrared spectroscopy brain sensing.

  11. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  12. The growth of the metallic ZrNx thin films on P-GaN substrate by pulsed laser deposition

    Science.gov (United States)

    Gu, Chengyan; Sui, Zhanpeng; Li, Yuxiong; Chu, Haoyu; Ding, Sunan; Zhao, Yanfei; Jiang, Chunping

    2018-03-01

    Although metal nitride thin films have attractive prospects in plasmonic applications due to its stable properties in harsh environments containing high temperatures, shock, and contaminants, the effect of deposition parameters on the properties of the metallic ZrN grown on III-N semiconductors by pulse laser deposition still lacks of detailed exploration. Here we have successfully prepared metallic ZrNx films on p-GaN substrate by pulsed laser deposition in N2 ambient of various pressures at a fixed substrate temperature (475 °C). It is found that the films exhibit quite smooth surfaces and (111) preferred orientation. The X-ray photoelectron spectroscopy measurements indicate that carbon contamination can be completely removed and oxygen contamination is significantly reduced on the film surfaces after cleaning using Ar+ sputtering. The N/Zr ratio increases from 0.64 to 0.75 when the N2 pressure increases from 0.5 Pa to 3 Pa. The optical reflectivity spectra measured by the UV-vis-NIR spectrophotometer show that the ZrNx is a typical and good metallic-like material and its metallic properties can be tuned with changing the film compositions.

  13. Performance Analysis of an Astrophysical Simulation Code on the Intel Xeon Phi Architecture

    OpenAIRE

    Noormofidi, Vahid; Atlas, Susan R.; Duan, Huaiyu

    2015-01-01

    We have developed the astrophysical simulation code XFLAT to study neutrino oscillations in supernovae. XFLAT is designed to utilize multiple levels of parallelism through MPI, OpenMP, and SIMD instructions (vectorization). It can run on both CPU and Xeon Phi co-processors based on the Intel Many Integrated Core Architecture (MIC). We analyze the performance of XFLAT on configurations with CPU only, Xeon Phi only and both CPU and Xeon Phi. We also investigate the impact of I/O and the multi-n...

  14. Efficient sparse matrix-matrix multiplication for computing periodic responses by shooting method on Intel Xeon Phi

    Science.gov (United States)

    Stoykov, S.; Atanassov, E.; Margenov, S.

    2016-10-01

    Many of the scientific applications involve sparse or dense matrix operations, such as solving linear systems, matrix-matrix products, eigensolvers, etc. In what concerns structural nonlinear dynamics, the computations of periodic responses and the determination of stability of the solution are of primary interest. Shooting method iswidely used for obtaining periodic responses of nonlinear systems. The method involves simultaneously operations with sparse and dense matrices. One of the computationally expensive operations in the method is multiplication of sparse by dense matrices. In the current work, a new algorithm for sparse matrix by dense matrix products is presented. The algorithm takes into account the structure of the sparse matrix, which is obtained by space discretization of the nonlinear Mindlin's plate equation of motion by the finite element method. The algorithm is developed to use the vector engine of Intel Xeon Phi coprocessors. It is compared with the standard sparse matrix by dense matrix algorithm and the one developed by Intel MKL and it is shown that by considering the properties of the sparse matrix better algorithms can be developed.

  15. Simulation on Vehicle Vibration Offset of NX70 Flatcar

    Directory of Open Access Journals (Sweden)

    Han Yanhui

    2014-11-01

    Full Text Available The current rolling stock gauge for standard gauge railway is a static gauge to check the vehicle frame. The contradiction of large construction gauge and small rolling stock gauge has always existed. It is important to set down the clearance requirements in respect of physical size for the safe passage of rail vehicles. Reasonably determining the maximum vibration offset can improve the efficiency of clearance. As an example, analyze the complex vibration of NX70 flat car by simulation test on the running track. Comprehensive considering the track model, loading plan, line conditions and running speed, then SIMPACK is used to present the vehicle system dynamics simulation model. After researching simulation result, respectively determine the maximum vehicle vibration offset for railroads of Class I, Class II and Class III on the height of the center of gravity 2000 mm and 2400 mm. According to the clearance between the structure gauge and the position of maximum vibration offset, analyze the safety of vehicle operation since the center of gravity is higher than before.

  16. Electronics Industry Study Report: Semiconductors and Defense Electronics

    Science.gov (United States)

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  17. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  18. Transitioning to Intel-based Linux Servers in the Payload Operations Integration Center

    Science.gov (United States)

    Guillebeau, P. L.

    2004-01-01

    The MSFC Payload Operations Integration Center (POIC) is the focal point for International Space Station (ISS) payload operations. The POIC contains the facilities, hardware, software and communication interface necessary to support payload operations. ISS ground system support for processing and display of real-time spacecraft and telemetry and command data has been operational for several years. The hardware components were reaching end of life and vendor costs were increasing while ISS budgets were becoming severely constrained. Therefore it has been necessary to migrate the Unix portions of our ground systems to commodity priced Intel-based Linux servers. hardware architecture including networks, data storage, and highly available resources. This paper will concentrate on the Linux migration implementation for the software portion of our ground system. The migration began with 3.5 million lines of code running on Unix platforms with separate servers for telemetry, command, Payload information management systems, web, system control, remote server interface and databases. The Intel-based system is scheduled to be available for initial operational use by August 2004 The overall migration to Intel-based Linux servers in the control center involves changes to the This paper will address the Linux migration study approach including the proof of concept, criticality of customer buy-in and importance of beginning with POSlX compliant code. It will focus on the development approach explaining the software lifecycle. Other aspects of development will be covered including phased implementation, interim milestones and metrics measurements and reporting mechanisms. This paper will also address the testing approach covering all levels of testing including development, development integration, IV&V, user beta testing and acceptance testing. Test results including performance numbers compared with Unix servers will be included. need for a smooth transition while maintaining

  19. Benchmarking Data Analysis and Machine Learning Applications on the Intel KNL Many-Core Processor

    OpenAIRE

    Byun, Chansup; Kepner, Jeremy; Arcand, William; Bestor, David; Bergeron, Bill; Gadepally, Vijay; Houle, Michael; Hubbell, Matthew; Jones, Michael; Klein, Anna; Michaleas, Peter; Milechin, Lauren; Mullen, Julie; Prout, Andrew; Rosa, Antonio

    2017-01-01

    Knights Landing (KNL) is the code name for the second-generation Intel Xeon Phi product family. KNL has generated significant interest in the data analysis and machine learning communities because its new many-core architecture targets both of these workloads. The KNL many-core vector processor design enables it to exploit much higher levels of parallelism. At the Lincoln Laboratory Supercomputing Center (LLSC), the majority of users are running data analysis applications such as MATLAB and O...

  20. On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

    International Nuclear Information System (INIS)

    Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

    2010-01-01

    We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

  1. Adaption of wild-bird origin H5Nx highly pathogenic avian influenza virus Clade 2.3.4.4 in vaccinated poultry

    Science.gov (United States)

    The 2014-2015 incursion of H5Nx clade 2.3.4.4 high pathogenicity avian influenza (HPAI) virus caused the largest animal health emergency in U.S. history and renewed interest in developing vaccines against these newly emergent viruses. Our previous research demonstrated several H5 vaccines with varyi...

  2. High-throughput sockets over RDMA for the Intel Xeon Phi coprocessor

    CERN Document Server

    Santogidis, Aram

    2017-01-01

    In this paper we describe the design, implementation and performance of Trans4SCIF, a user-level socket-like transport library for the Intel Xeon Phi coprocessor. Trans4SCIF library is primarily intended for high-throughput applications. It uses RDMA transfers over the native SCIF support, in a way that is transparent for the application, which has the illusion of using conventional stream sockets. We also discuss the integration of Trans4SCIF with the ZeroMQ messaging library, used extensively by several applications running at CERN. We show that this can lead to a substantial, up to 3x, increase of application throughput compared to the default TCP/IP transport option.

  3. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    Science.gov (United States)

    Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junmin; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

    2017-08-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC), KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1) updating the pure Message Passing Interface (MPI) parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2) fully employing the 512 bit wide vector processing units (VPUs) on the KNL platform; (3) reducing unnecessary memory access to improve cache efficiency; (4) reducing the thread local storage (TLS) in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5) changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined performance and energy

  4. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  5. Structural, electronic, mechanical, thermal and optical properties of B(P,As)1-xNx; (x = 0, 0.25, 0.5, 0.75, 1) alloys and hardness of B(P,As) under compression using DFT calculations

    Science.gov (United States)

    Viswanathan, E.; Sundareswari, M.; Jayalakshmi, D. S.; Manjula, M.; Krishnaveni, S.

    2017-09-01

    First principles calculations are carried out in order to analyze the structural, electronic, mechanical, thermal and optical properties of BP and BAs compounds by ternary alloying with nitrogen namely B(P,As)1-xNx (x = 0.25, 0.5, 0.75) alloys at ambient condition. Thereby we report the mechanical and thermal properties of B(P,As)1-xNx (x = 0.25, 0.5, 0.75) alloys namely bulk modulus, shear modulus, Young's modulus, hardness, ductile-brittle nature, elastic wave velocity, Debye temperature, melting point, etc.; optical properties of B(P)1-xNx (x = 0.25, 0.5, 0.75) and B(As)1-xNx (x = 0.25, 0.75) alloys namely the dielectric function of real and imaginary part, refractive index, extinction coefficient and reflectivity and the hardness profile of the parent compounds BP and BAs under compression. The charge density plot, density of states histograms and band structures are plotted and discussed for all the ternary alloys of the present study. The calculated results agree very well with the available literature. Analysis of the present study reveals that the ternary alloy combinations namely BP.25N.75 and BAs.25N.75 could be superhard materials; hardness of BP and BAs increases with compression.

  6. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  7. Design of real-time monitoring and control system of 222Rn/220Rn sampling for radon chamber

    International Nuclear Information System (INIS)

    Wu Rongyan; Zhao Xiuliang; Zhang Meiqin; Yu Hong

    2008-01-01

    This paper describes the design of 222 Rn/ 220 Rn sampling monitoring and control system based on single-chip microcomputer of series Intel51. The hardware design involves the choosing and usage of sensors-chips, A/D conversion-chip, USB interface-chip, keyboard-chip, digital display-chip, photoelectric coupling isolation-chips and drive circuit-chips of the direct current pump. Software design is composed by software of Personal Computer (PC) and software of Single Chip Microcomputer (SCM). The data acquisition and conversion and the flux control of direct current pump are realized by using soft of Visual Basic and assemble language. The program flow charts are given. Furthermore, we improved the stability of the direct current pump by means of PID Control Algorithms. (authors)

  8. Method of spectra parametrization of (n, x) and (n, nx) reactions induced by DT-neutrons

    International Nuclear Information System (INIS)

    Aleksandrov, D.V.; Kovrigin, B.S.

    1980-01-01

    A method for parmetrization of experimental spectra has been developed for more convenient carrying out a process of separating competing mechanisms contributions in spectra of the (n, x) and (n, nx) reactions induced with DT neutrons. Differential cross sections of competing partial processes are used. as expanding coefficients. Model spectra may be represented in the form of tabulated-given functions calculated separately from formulae of any complexity degree. Fit of model expressions is performed by the least square method (lsm). Step-by-step algorithm of nonlinear optimization is used for search for lsm- evaluations of theoretical models parameters [ru

  9. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  10. Initial results on computational performance of Intel Many Integrated Core (MIC) architecture: implementation of the Weather and Research Forecasting (WRF) Purdue-Lin microphysics scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    Purdue-Lin scheme is a relatively sophisticated microphysics scheme in the Weather Research and Forecasting (WRF) model. The scheme includes six classes of hydro meteors: water vapor, cloud water, raid, cloud ice, snow and graupel. The scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. In this paper, we accelerate the Purdue Lin scheme using Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi is a high performance coprocessor consists of up to 61 cores. The Xeon Phi is connected to a CPU via the PCI Express (PICe) bus. In this paper, we will discuss in detail the code optimization issues encountered while tuning the Purdue-Lin microphysics Fortran code for Xeon Phi. In particularly, getting a good performance required utilizing multiple cores, the wide vector operations and make efficient use of memory. The results show that the optimizations improved performance of the original code on Xeon Phi 5110P by a factor of 4.2x. Furthermore, the same optimizations improved performance on Intel Xeon E5-2603 CPU by a factor of 1.2x compared to the original code.

  11. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  12. Implementation of a 3-D nonlinear MHD [magnetohydrodynamics] calculation on the Intel hypercube

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Hicks, H.R.; Lawkins, W.F.

    1987-01-01

    The optimization of numerical schemes and increasing computer capabilities in the last ten years have improved the efficiency of 3-D nonlinear resistive MHD calculations by about two to three orders of magnitude. However, we are still very limited in performing these types of calculations. Hypercubes have a large number of processors with only local memory and bidirectional links among neighbors. The Intel Hypercube at Oak Ridge has 64 processors with 0.5 megabytes of memory per processor. The multiplicity of processors opens new possibilities for the treatment of such computations. The constraint on time and resources favored the approach of using the existing RSF code which solves as an initial value problem the reduced set of MHD equations for a periodic cylindrical geometry. This code includes minimal physics and geometry, but contains the basic three dimensionality and nonlinear structure of the equations. The code solves the reduced set of MHD equations by Fourier expansion in two angular coordinates and finite differences in the radial one. Due to the continuing interest in these calculations and the likelihood that future supercomputers will take greater advantage of parallelism, the present study was initiated by the ORNL Exploratory Studies Committee and funded entirely by Laboratory Discretionary Funds. The objectives of the study were: to ascertain the suitability of MHD calculation for parallel computation, to design and implement a parallel algorithm to perform the computations, and to evaluate the hypercube, and in particular, ORNL's Intel iPSC, for use in MHD computations

  13. Drift chamber tracking with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

  14. STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

    Directory of Open Access Journals (Sweden)

    Ireneusz Zagórski

    2016-12-01

    Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

  15. GW Calculations of Materials on the Intel Xeon-Phi Architecture

    Science.gov (United States)

    Deslippe, Jack; da Jornada, Felipe H.; Vigil-Fowler, Derek; Biller, Ariel; Chelikowsky, James R.; Louie, Steven G.

    Intel Xeon-Phi processors are expected to power a large number of High-Performance Computing (HPC) systems around the United States and the world in the near future. We evaluate the ability of GW and pre-requisite Density Functional Theory (DFT) calculations for materials on utilizing the Xeon-Phi architecture. We describe the optimization process and performance improvements achieved. We find that the GW method, like other higher level Many-Body methods beyond standard local/semilocal approximations to Kohn-Sham DFT, is particularly well suited for many-core architectures due to the ability to exploit a large amount of parallelism over plane-waves, band-pairs and frequencies. Support provided by the SCIDAC program, Department of Energy, Office of Science, Advanced Scientic Computing Research and Basic Energy Sciences. Grant Numbers DE-SC0008877 (Austin) and DE-AC02-05CH11231 (LBNL).

  16. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  17. Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study

    OpenAIRE

    Rucci, Enzo; De Giusti, Armando Eduardo; Naiouf, Marcelo

    2017-01-01

    Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm ...

  18. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    International Nuclear Information System (INIS)

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  19. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  20. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS on Intel Xeon Phi processors

    Directory of Open Access Journals (Sweden)

    H. Wang

    2017-08-01

    Full Text Available The Global Nested Air Quality Prediction Modeling System (GNAQPMS is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS, which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL. Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC, KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1 updating the pure Message Passing Interface (MPI parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2 fully employing the 512 bit wide vector processing units (VPUs on the KNL platform; (3 reducing unnecessary memory access to improve cache efficiency; (4 reducing the thread local storage (TLS in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5 changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined

  1. Time-efficient simulations of tight-binding electronic structures with Intel Xeon PhiTM many-core processors

    Science.gov (United States)

    Ryu, Hoon; Jeong, Yosang; Kang, Ji-Hoon; Cho, Kyu Nam

    2016-12-01

    Modelling of multi-million atomic semiconductor structures is important as it not only predicts properties of physically realizable novel materials, but can accelerate advanced device designs. This work elaborates a new Technology-Computer-Aided-Design (TCAD) tool for nanoelectronics modelling, which uses a sp3d5s∗ tight-binding approach to describe multi-million atomic structures, and simulate electronic structures with high performance computing (HPC), including atomic effects such as alloy and dopant disorders. Being named as Quantum simulation tool for Advanced Nanoscale Devices (Q-AND), the tool shows nice scalability on traditional multi-core HPC clusters implying the strong capability of large-scale electronic structure simulations, particularly with remarkable performance enhancement on latest clusters of Intel Xeon PhiTM coprocessors. A review of the recent modelling study conducted to understand an experimental work of highly phosphorus-doped silicon nanowires, is presented to demonstrate the utility of Q-AND. Having been developed via Intel Parallel Computing Center project, Q-AND will be open to public to establish a sound framework of nanoelectronics modelling with advanced HPC clusters of a many-core base. With details of the development methodology and exemplary study of dopant electronics, this work will present a practical guideline for TCAD development to researchers in the field of computational nanoelectronics.

  2. A parallel implementation of particle tracking with space charge effects on an INTEL iPSC/860

    International Nuclear Information System (INIS)

    Chang, L.; Bourianoff, G.; Cole, B.; Machida, S.

    1993-05-01

    Particle-tracking simulation is one of the scientific applications that is well-suited to parallel computations. At the Superconducting Super Collider, it has been theoretically and empirically demonstrated that particle tracking on a designed lattice can achieve very high parallel efficiency on a MIMD Intel iPSC/860 machine. The key to such success is the realization that the particles can be tracked independently without considering their interaction. The perfectly parallel nature of particle tracking is broken if the interaction effects between particles are included. The space charge introduces an electromagnetic force that will affect the motion of tracked particles in 3-D space. For accurate modeling of the beam dynamics with space charge effects, one needs to solve three-dimensional Maxwell field equations, usually by a particle-in-cell (PIC) algorithm. This will require each particle to communicate with its neighbor grids to compute the momentum changes at each time step. It is expected that the 3-D PIC method will degrade parallel efficiency of particle-tracking implementation on any parallel computer. In this paper, we describe an efficient scheme for implementing particle tracking with space charge effects on an INTEL iPSC/860 machine. Experimental results show that a parallel efficiency of 75% can be obtained

  3. Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    Science.gov (United States)

    Hashida, Takushi; Nagata, Makoto

    Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

  4. Hot Chips and Hot Interconnects for High End Computing Systems

    Science.gov (United States)

    Saini, Subhash

    2005-01-01

    I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

  5. Student Intern Ben Freed Competes as Finalist in Intel STS Competition, Three Other Interns Named Semifinalists | Poster

    Science.gov (United States)

    By Ashley DeVine, Staff Writer Werner H. Kirstin (WHK) student intern Ben Freed was one of 40 finalists to compete in the Intel Science Talent Search (STS) in Washington, DC, in March. “It was seven intense days of interacting with amazing judges and incredibly smart and interesting students. We met President Obama, and then the MIT astronomy lab named minor planets after each

  6. Development of Jerusalem artichoke resource for efficient one-step fermentation of poly-(γ-glutamic acid) using a novel strain Bacillus amyloliquefaciens NX-2S.

    Science.gov (United States)

    Qiu, Yibin; Sha, Yuanyuan; Zhang, Yatao; Xu, Zongqi; Li, Sha; Lei, Peng; Xu, Zheng; Feng, Xiaohai; Xu, Hong

    2017-09-01

    This study aimed to develop non-food fermentation for the cost-effective production of poly-(γ-glutamic acid) (γ-PGA) using a novel strain of Bacillus amyloliquefaciens NX-2S. The new isolate assimilated inulin more efficiently than other carbohydrates from Jerusalem artichoke, without hydrolytic treatment. To investigate the effect of inulin on γ-PGA production, the transcript levels of γ-PGA synthetase genes (pgsB, pgsC, pgsA), regulatory genes (comA, degQ, degS), and the glutamic acid biosynthesis gene (glnA) were analyzed; inulin addition upregulated these key genes. Without exogenous glutamate, strain NX-2S could produce 6.85±0.22g/L of γ-PGA during fermentation. Exogenous glutamate greatly enhances the γ-PGA yield (39.4±0.38g/L) and productivity (0.43±0.05g/L/h) in batch fermentation. Our study revealed a potential method of non-food fermentation to produce high-value products. Copyright © 2017. Published by Elsevier Ltd.

  7. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  8. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  9. Research on Rigid Body Motion Tracing in Space based on NX MCD

    Science.gov (United States)

    Wang, Junjie; Dai, Chunxiang; Shi, Karen; Qin, Rongkang

    2018-03-01

    In the use of MCD (Mechatronics Concept Designer) which is a module belong to SIEMENS Ltd industrial design software UG (Unigraphics NX), user can define rigid body and kinematic joint to make objects move according to the existing plan in simulation. At this stage, user may have the desire to see the path of some points in the moving object intuitively. In response to this requirement, this paper will compute the pose through the transformation matrix which can be available from the solver engine, and then fit these sampling points through B-spline curve. Meanwhile, combined with the actual constraints of rigid bodies, the traditional equal interval sampling strategy was optimized. The result shown that this method could satisfy the demand and make up for the deficiency in traditional sampling method. User can still edit and model on this 3D curve. Expected result has been achieved.

  10. tavgU_2d_flx_Nx: MERRA 2D IAU Diagnostic, Surface Fluxes, Diurnal 0.667 x 0.5 degree V5.2.0 (MATUNXFLX) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATUNXFLX or tavgU_2d_flx_Nx data product is the MERRA Data Assimilation System 2-Dimensional surface turbulence flux diagnostic that is time averaged...

  11. Les multituds intel·ligents com a generadores de dades massives : la intel·ligència col·lectiva al servei de la innovació social

    Directory of Open Access Journals (Sweden)

    Sanz, Sandra

    2015-06-01

    Full Text Available Les últimes dècades es registra un increment de mobilitzacions socials organitzades, intervingudes, narrades i coordinades a través de les TIC. Són mostra de multituds intel·ligents (smart mobs que s'aprofiten dels nous mitjans de comunicació per organitzar-se. Tant pel nombre de missatges intercanviats i generats com per les pròpies interaccions generades, aquestes multituds intel·ligents es converteixen en objecte de les dades massives. La seva anàlisi a partir de les possibilitats que brinda l'enginyeria de dades pot contribuir a detectar idees construïdes com també sabers compartits fruit de la intel·ligència col·lectiva. Aquest fet afavoriria la reutilització d'aquesta informació per incrementar el coneixement del col·lectiu i contribuir al desenvolupament de la innovació social. És per això que en aquest article s'assenyalen els interrogants i les limitacions que encara presenten aquestes anàlisis i es posa en relleu la necessitat d'aprofundir en el desenvolupament de nous mètodes i tècniques d'anàlisi.En las últimas décadas se registra un incremento de movilizaciones sociales organizadas, mediadas, narradas y coordinadas a través de TICs. Son muestra de smart mobs o multitudes inteligentes que se aprovechan de los nuevos medios de comunicación para organizarse. Tanto por el número de mensajes intercambiados y generados como por las propias interacciones generadas, estas multitudes inteligentes se convierten en objeto del big data. Su análisis a partir de las posibilidades que brinda la ingeniería de datos puede contribuir a detectar ideas construidas así como saberes compartidos fruto de la inteligencia colectiva. Ello favorecería la reutilización de esta información para incrementar el conocimiento del colectivo y contribuir al desarrollo de la innovación social. Es por ello que en este artículo se señalan los interrogantes y limitaciones que todavía presentan estos análisis y se pone de relieve la

  12. Hydrogen Permeation, and Mechanical and Tribological Behavior, of CrNx Coatings Deposited at Various Bias Voltages on IN718 by Direct Current Reactive Sputtering

    Directory of Open Access Journals (Sweden)

    Egor B. Kashkarov

    2018-02-01

    Full Text Available In the current work, the microstructure, hydrogen permeability, and properties of chromium nitride (CrNx thin films deposited on the Inconel 718 superalloy using direct current reactive sputtering are investigated. The influence of the substrate bias voltage on the crystal structure, mechanical, and tribological properties before and after hydrogen exposure was studied. It was found that increasing the substrate bias voltage leads to densification of the coating. X-ray diffraction (XRD results reveal a change from mixed fcc-CrN + hcp-Cr2N to the approximately stoichiometric hcp-Cr2N phase with increasing substrate bias confirmed by wavelength-dispersive X-ray spectroscopy (WDS. The texture coefficients of (113, (110, and (111 planes vary significantly with increasing substrate bias voltage. The hydrogen permeability was measured by gas-phase hydrogenation. The CrN coating deposited at 60 V with mixed c-CrN and (113 textured hcp-Cr2N phases exhibits the lowest hydrogen absorption at 873 K. It is suggested that the crystal orientation is only one parameter influencing the permeation resistance of the CrNx coating together with the film structure, the presence of mixing phases, and the packing density of the structure. After hydrogenation, the hardness increased for all coatings, which could be related to the formation of a Cr2O3 oxide film on the surface, as well as the defect formation after hydrogen loading. Tribological tests reveal that hydrogenation leads to a decrease of the friction coefficient by up to 40%. The lowest value of 0.25 ± 0.02 was reached for the CrNx coating deposited at 60 V after hydrogenation.

  13. Hydrogen loss and its improved retention in hydrogen plasma treated a-SiNx:H films: ERDA study with 100 MeV Ag7+ ions

    Science.gov (United States)

    Bommali, R. K.; Ghosh, S.; Khan, S. A.; Srivastava, P.

    2018-05-01

    Hydrogen loss from a-SiNx:H films under irradiation with 100 MeV Ag7+ ions using elastic recoil detection analysis (ERDA) experiment is reported. The results are explained under the basic assumptions of the molecular recombination model. The ERDA hydrogen concentration profiles are composed of two distinct hydrogen desorption processes, limited by rapid molecular diffusion in the initial stages of irradiation, and as the fluence progresses a slow process limited by diffusion of atomic hydrogen takes over. Which of the aforesaid processes dominates, is determined by the continuously evolving Hydrogen concentration within the films. The first process dominates when the H content is high, and as the H concentration falls below a certain threshold (Hcritical) the irradiation generated H radicals have to diffuse through larger distances before recombining to form H2, thereby significantly bringing down the hydrogen evolution rate. The ERDA measurements were also carried out for films treated with low temperature (300 °C) hydrogen plasma annealing (HPA). The HPA treated films show a clear increase in Hcritical value, thus indicating an improved diffusion of atomic hydrogen, resulting from healing of weak bonds and passivation of dangling bonds. Further, upon HPA films show a significantly higher H concentration relative to the as-deposited films, at advanced fluences. These results indicate the potential of HPA towards improved H retention in a-SiNx:H films. The study distinguishes clearly the presence of two diffusion processes in a-SiNx:H whose diffusion rates differ by an order of magnitude, with atomic hydrogen not being able to diffuse further beyond ∼ 1 nm from the point of its creation.

  14. Chip compacting press; Jido kirikuzu asshukuki

    Energy Technology Data Exchange (ETDEWEB)

    Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

    1998-08-15

    The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

  15. Evaluating the transport layer of the ALFA framework for the Intel(®) Xeon Phi(™) Coprocessor

    OpenAIRE

    Santogidis, Aram; Hirstius, Andreas; Lalis, Spyros

    2015-01-01

    The ALFA framework supports the software development of major High Energy Physics experiments. As part of our research effort to optimize the transport layer of ALFA, we focus on profiling its data transfer performance for inter-node communication on the Intel Xeon Phi Coprocessor. In this article we present the collected performance measurements with the related analysis of the results. The optimization opportunities that are discovered, help us to formulate the future plans of enabling high...

  16. Accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) model on Intel Xeon Phi processors

    OpenAIRE

    Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junming; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

    2017-01-01

    The GNAQPMS model is the global version of the Nested Air Quality Prediction Modelling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present our work of porting and optimizing the GNAQPMS model on the second generation Intel Xeon Phi processor codename “Knights Landing” (KNL). Compared with the first generation Xeon Phi coprocessor, KNL introduced many new hardware features such as a boo...

  17. tavgM_2d_ocn_Nx: MERRA 2D IAU Ocean Surface Diagnostic, Diurnal 0.667 x 0.5 degree V5.2.0 (MATUNXOCN) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATUNXOCN or tavgU_2d_ocn_Nx data product is the MERRA Data Assimilation System 2-Dimensional ocean surface single-level diagnostics that is monthly mean...

  18. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00014247; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea

    2017-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with detai...

  19. Multi-threaded ATLAS Simulation on Intel Knights Landing Processors

    CERN Document Server

    Farrell, Steven; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles

    2016-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), will be delivered to its users in two phases with the first phase online now and the second phase expected in mid-2016. Cori Phase 2 will be based on the KNL architecture and will contain over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a great use-case for the KNL architecture and supercomputers like Cori. Simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this presentation we will give an overview of the ATLAS simulation application with details on its multi-thr...

  20. A new shared-memory programming paradigm for molecular dynamics simulations on the Intel Paragon

    International Nuclear Information System (INIS)

    D'Azevedo, E.F.; Romine, C.H.

    1994-12-01

    This report describes the use of shared memory emulation with DOLIB (Distributed Object Library) to simplify parallel programming on the Intel Paragon. A molecular dynamics application is used as an example to illustrate the use of the DOLIB shared memory library. SOTON-PAR, a parallel molecular dynamics code with explicit message-passing using a Lennard-Jones 6-12 potential, is rewritten using DOLIB primitives. The resulting code has no explicit message primitives and resembles a serial code. The new code can perform dynamic load balancing and achieves better performance than the original parallel code with explicit message-passing

  1. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  2. Surface passivation by Al2O3 and a-SiNx: H films deposited on wet-chemically conditioned Si surfaces

    NARCIS (Netherlands)

    Bordihn, S.; Mertens, V.; Engelhart, P.; Kersten, K.; Mandoc, M.M.; Müller, J.W.; Kessels, W.M.M.

    2012-01-01

    The surface passivation of p- and n-type silicon by different chemically grown SiO2 films (prepared by HNO3, H2SO4/H2O2 and HCl/H2O2 treatments) was investigated after PECVD of a-SiNx:H and ALD of Al2O3 capping films. The wet chemically grown SiO2 films were compared to thermally grown SiO2 and the

  3. Plasma turbulence calculations on the Intel iPSC/860 (rx) hypercube

    International Nuclear Information System (INIS)

    Lynch, V.E.; Ruiter, J.R.

    1990-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A serial algorithm used for plasma turbulence calculations was modified to allocate a radial region in each node. In this way, convolutions at a fixed radius are performed in parallel, and communication is limited to boundary values for each radial region. For a semi-implicity numerical scheme (tridiagonal matrix solver), there is a factor of 3 improvement in efficiency with the Intel iPSC/860 machine using 64 processors over a single-processor Cray-II. For block-tridiagonal matrix cases (fully implicit code), a second parallelization takes place. The Fourier components are distributed in nodes. In each node, the block-tridiagonal matrix is inverted for each of allocated Fourier components. The algorithm for this second case has not yet been optimized. 10 refs., 4 figs

  4. Emmarcar el debat: Lliure expressió contra propietat intel·lectual, els propers cinquanta anys

    Directory of Open Access Journals (Sweden)

    Eben Moglen

    2007-02-01

    Full Text Available

    El Prof. Moglen explica i analitza, des d'una perspectiva històrica, la profunda revolució social i legal que resulta de la tecnologia digital quan aquesta s'aplica a tots els camps: programari, música i tot tipus de creacions. En concret, explica la manera en què la tecnologia digital està forçant una modificació substancial (desaparició dels sistemes de propietat intel·lectual i fa prediccions per al futur pròxim dels mercats de la PI.

  5. tavgM_2d_flx_Nx: MERRA 2D IAU Diagnostic, Surface Fluxes, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXFLX) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXFLX or tavgM_2d_flx_Nx data product is the MERRA Data Assimilation System 2-Dimensional surface turbulence flux diagnostic that is time averaged...

  6. Using Intel Xeon Phi to accelerate the WRF TEMF planetary boundary layer scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen

    2014-05-01

    The Weather Research and Forecasting (WRF) model is designed for numerical weather prediction and atmospheric research. The WRF software infrastructure consists of several components such as dynamic solvers and physics schemes. Numerical models are used to resolve the large-scale flow. However, subgrid-scale parameterizations are for an estimation of small-scale properties (e.g., boundary layer turbulence and convection, clouds, radiation). Those have a significant influence on the resolved scale due to the complex nonlinear nature of the atmosphere. For the cloudy planetary boundary layer (PBL), it is fundamental to parameterize vertical turbulent fluxes and subgrid-scale condensation in a realistic manner. A parameterization based on the Total Energy - Mass Flux (TEMF) that unifies turbulence and moist convection components produces a better result that the other PBL schemes. For that reason, the TEMF scheme is chosen as the PBL scheme we optimized for Intel Many Integrated Core (MIC), which ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our optimization results for TEMF planetary boundary layer scheme. The optimizations that were performed were quite generic in nature. Those optimizations included vectorization of the code to utilize vector units inside each CPU. Furthermore, memory access was improved by scalarizing some of the intermediate arrays. The results show that the optimization improved MIC performance by 14.8x. Furthermore, the optimizations increased CPU performance by 2.6x compared to the original multi-threaded code on quad core Intel Xeon E5-2603 running at 1.8 GHz. Compared to the optimized code running on a single CPU socket the optimized MIC code is 6.2x faster.

  7. A (Nd, Zr(Fe, Co11.5Ti0.5Nx compound as a permanent magnet material

    Directory of Open Access Journals (Sweden)

    S. Suzuki

    2014-11-01

    Full Text Available We studied NdFe11TiNx compounds as permanent magnet materials. The (Nd0.7,Zr0.3(Fe0.75Co0.2511.5Ti0.5N0.52 powder that contained a limited amount of the α-(Fe, Co phase shows fairly good magnetic properties, such as a saturation polarization (Js of 1.68 T and an anisotropic field (Ha of 2.88 (Law of approach to saturation – 4.0 MA/m (Intersection of magnetization curves. Both properties are comparable to those of the Nd2Fe14B phase.

  8. Applications Performance on NAS Intel Paragon XP/S - 15#

    Science.gov (United States)

    Saini, Subhash; Simon, Horst D.; Copper, D. M. (Technical Monitor)

    1994-01-01

    The Numerical Aerodynamic Simulation (NAS) Systems Division received an Intel Touchstone Sigma prototype model Paragon XP/S- 15 in February, 1993. The i860 XP microprocessor with an integrated floating point unit and operating in dual -instruction mode gives peak performance of 75 million floating point operations (NIFLOPS) per second for 64 bit floating point arithmetic. It is used in the Paragon XP/S-15 which has been installed at NAS, NASA Ames Research Center. The NAS Paragon has 208 nodes and its peak performance is 15.6 GFLOPS. Here, we will report on early experience using the Paragon XP/S- 15. We have tested its performance using both kernels and applications of interest to NAS. We have measured the performance of BLAS 1, 2 and 3 both assembly-coded and Fortran coded on NAS Paragon XP/S- 15. Furthermore, we have investigated the performance of a single node one-dimensional FFT, a distributed two-dimensional FFT and a distributed three-dimensional FFT Finally, we measured the performance of NAS Parallel Benchmarks (NPB) on the Paragon and compare it with the performance obtained on other highly parallel machines, such as CM-5, CRAY T3D, IBM SP I, etc. In particular, we investigated the following issues, which can strongly affect the performance of the Paragon: a. Impact of the operating system: Intel currently uses as a default an operating system OSF/1 AD from the Open Software Foundation. The paging of Open Software Foundation (OSF) server at 22 MB to make more memory available for the application degrades the performance. We found that when the limit of 26 NIB per node out of 32 MB available is reached, the application is paged out of main memory using virtual memory. When the application starts paging, the performance is considerably reduced. We found that dynamic memory allocation can help applications performance under certain circumstances. b. Impact of data cache on the i860/XP: We measured the performance of the BLAS both assembly coded and Fortran

  9. Electronic structure and magnetic anisotropy of Sm2Fe17Nx

    Science.gov (United States)

    Akai, Hisazumi; Ogura, Masako

    2014-03-01

    Electronic structure and magnetic properties of Sm2Fe17Nx are studies on the basis of the first-principles electronic structure calculation in the framework of the density functional theory within the local density and coherent potential approximations. The magnetic anisotropy of the system as a function of nitrogen concentration x is discussed by taking account not only of the crystal field effects but also of the effects of the f-electron transfer from Sm to the neighboring sites. Also discussed is the magnetic transition temperature that is estimated by mapping the system into a Heisenberg model. The results show the crystalline magnetic anisotropy changes its direction from in-plane to uniaxial ones as x increases. It takes the maximum value near x ~ 2 . 8 and then decreases slightly towards x = 3 . The mechanism for these behaviors is discussed in the light of the results of detailed calculations on the bonding properties between Sm and its neighboring N. This work was partly supported by Elements Strategy Initiative Center for Magnetic Materials Project, the Ministry of Education, Culture, Sports, Science and Technology, Japan.

  10. tavgM_2d_ocn_Nx: MERRA 2D IAU Ocean Surface Diagnostic, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXOCN) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXOCN or tavgM_2d_ocn_Nx data product is the MERRA Data Assimilation System 2-Dimensional ocean surface single-level diagnostics that is monthly mean...

  11. Could Changes in the Agricultural Landscape of Northeastern China Have Influenced the Long-Distance Transmission of Highly Pathogenic Avian Influenza H5Nx Viruses?

    Directory of Open Access Journals (Sweden)

    Marius Gilbert

    2017-12-01

    Full Text Available In the last few years, several reassortant subtypes of highly pathogenic avian influenza viruses (HPAI H5Nx have emerged in East Asia. These new viruses, mostly of subtype H5N1, H5N2, H5N6, and H5N8 belonging to clade 2.3.4.4, have been found in several Asian countries and have caused outbreaks in poultry in China, South Korea, and Vietnam. HPAI H5Nx also have spread over considerable distances with the introduction of viruses belonging to the same 2.3.4.4 clade in the U.S. (2014–2015 and in Europe (2014–2015 and 2016–2017. In this paper, we examine the emergence and spread of these new viruses in Asia in relation to published datasets on HPAI H5Nx distribution, movement of migratory waterfowl, avian influenza risk models, and land-use change analyses. More specifically, we show that between 2000 and 2015, vast areas of northeast China have been newly planted with rice paddy fields (3.21 million ha in Heilongjiang, Jilin, and Liaoning in areas connected to other parts of Asia through migratory pathways of wild waterfowl. We hypothesize that recent land use changes in northeast China have affected the spatial distribution of wild waterfowl, their stopover areas, and the wild-domestic interface, thereby altering transmission dynamics of avian influenza viruses across flyways. Detailed studies of the habitat use by wild migratory birds, of the extent of the wild–domestic interface, and of the circulation of avian influenza viruses in those new planted areas may help to shed more light on this hypothesis, and on the possible impact of those changes on the long-distance patterns of avian influenza transmission.

  12. "Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

    Directory of Open Access Journals (Sweden)

    Krohn Knut

    2008-08-01

    Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

  13. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  14. Experience with low-power x86 processors (Atom) for HEP usage. An initial analysis of the Intel® dual core Atom™ N330 processor

    CERN Document Server

    Balazs, G; Nowak, A; CERN. Geneva. IT Department

    2009-01-01

    In this paper we compare a system based on an Intel Atom N330 low-power processor to a modern Intel Xeon® dual-socket server using CERN IT’s standard criteria for comparing price-performance and performance per watt. The Xeon server corresponds to what is typically acquired as servers in the LHC Computing Grid. The comparisons used public pricing information from November 2008. After the introduction in section 1, section 2 describes the hardware and software setup. In section 3 we describe the power measurements we did and in section 4 we discuss the throughput performance results. In section 5 we summarize our initial conclusions. We then go on to describe our long term vision and possible future scenarios for using such low-power processors, and finally we list interesting development directions.

  15. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  16. A performance study of sparse Cholesky factorization on INTEL iPSC/860

    Science.gov (United States)

    Zubair, M.; Ghose, M.

    1992-01-01

    The problem of Cholesky factorization of a sparse matrix has been very well investigated on sequential machines. A number of efficient codes exist for factorizing large unstructured sparse matrices. However, there is a lack of such efficient codes on parallel machines in general, and distributed machines in particular. Some of the issues that are critical to the implementation of sparse Cholesky factorization on a distributed memory parallel machine are ordering, partitioning and mapping, load balancing, and ordering of various tasks within a processor. Here, we focus on the effect of various partitioning schemes on the performance of sparse Cholesky factorization on the Intel iPSC/860. Also, a new partitioning heuristic for structured as well as unstructured sparse matrices is proposed, and its performance is compared with other schemes.

  17. tavgM_2d_slv_Nx: MERRA 2D IAU Diagnostic, Single Level Meteorology, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXSLV) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXSLV or tavgM_2d_slv_Nx data product is the MERRA Data Assimilation System 2-Dimensional atmospheric single-level diagnostics that is time averaged...

  18. An automation of design and modelling tasks in NX Siemens environment with original software - generator module

    Science.gov (United States)

    Zbiciak, M.; Grabowik, C.; Janik, W.

    2015-11-01

    Nowadays the design constructional process is almost exclusively aided with CAD/CAE/CAM systems. It is evaluated that nearly 80% of design activities have a routine nature. These design routine tasks are highly susceptible to automation. Design automation is usually made with API tools which allow building original software responsible for adding different engineering activities. In this paper the original software worked out in order to automate engineering tasks at the stage of a product geometrical shape design is presented. The elaborated software works exclusively in NX Siemens CAD/CAM/CAE environment and was prepared in Microsoft Visual Studio with application of the .NET technology and NX SNAP library. The software functionality allows designing and modelling of spur and helicoidal involute gears. Moreover, it is possible to estimate relative manufacturing costs. With the Generator module it is possible to design and model both standard and non-standard gear wheels. The main advantage of the model generated in such a way is its better representation of an involute curve in comparison to those which are drawn in specialized standard CAD systems tools. It comes from fact that usually in CAD systems an involute curve is drawn by 3 points that respond to points located on the addendum circle, the reference diameter of a gear and the base circle respectively. In the Generator module the involute curve is drawn by 11 involute points which are located on and upper the base and the addendum circles therefore 3D gear wheels models are highly accurate. Application of the Generator module makes the modelling process very rapid so that the gear wheel modelling time is reduced to several seconds. During the conducted research the analysis of differences between standard 3 points and 11 points involutes was made. The results and conclusions drawn upon analysis are shown in details.

  19. The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

    Science.gov (United States)

    Nikolova, Silviya; Stearns, Sally

    2014-03-03

    Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

  20. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  1. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  2. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  3. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  4. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  5. Experiment list: SRX122465 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

  6. Old PCs: Upgrade or Abandon?

    Science.gov (United States)

    Perez, Ernest

    1997-01-01

    Examines the practical realities of upgrading Intel personal computers in libraries, considering budgets and technical personnel availability. Highlights include adding RAM; putting in faster processor chips, including clock multipliers; new hard disks; CD-ROM speed; motherboards and interface cards; cost limits and economic factors; and…

  7. Experiment list: SRX122555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip anti...body catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-7

  8. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  9. Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors

    OpenAIRE

    Hirano, Akihiro; Nakayama, Kenji

    2008-01-01

    This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup ...

  10. Parallelizing ATLAS Reconstruction and Simulation: Issues and Optimization Solutions for Scaling on Multi- and Many-CPU Platforms

    International Nuclear Information System (INIS)

    Leggett, C; Jackson, K; Tatarkhanov, M; Yao, Y; Binet, S; Levinthal, D

    2011-01-01

    Thermal limitations have forced CPU manufacturers to shift from simply increasing clock speeds to improve processor performance, to producing chip designs with multi- and many-core architectures. Further the cores themselves can run multiple threads as a zero overhead context switch allowing low level resource sharing (Intel Hyperthreading). To maximize bandwidth and minimize memory latency, memory access has become non uniform (NUMA). As manufacturers add more cores to each chip, a careful understanding of the underlying architecture is required in order to fully utilize the available resources. We present AthenaMP and the Atlas event loop manager, the driver of the simulation and reconstruction engines, which have been rewritten to make use of multiple cores, by means of event based parallelism, and final stage I/O synchronization. However, initial studies on 8 andl6 core Intel architectures have shown marked non-linearities as parallel process counts increase, with as much as 30% reductions in event throughput in some scenarios. Since the Intel Nehalem architecture (both Gainestown and Westmere) will be the most common choice for the next round of hardware procurements, an understanding of these scaling issues is essential. Using hardware based event counters and Intel's Performance Tuning Utility, we have studied the performance bottlenecks at the hardware level, and discovered optimization schemes to maximize processor throughput. We have also produced optimization mechanisms, common to all large experiments, that address the extreme nature of today's HEP code, which due to it's size, places huge burdens on the memory infrastructure of today's processors.

  11. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-15

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

  12. Supply systems of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-01

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

  13. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

    2009-07-01

    The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

  14. A comparison of SuperLU solvers on the intel MIC architecture

    Science.gov (United States)

    Tuncel, Mehmet; Duran, Ahmet; Celebi, M. Serdar; Akaydin, Bora; Topkaya, Figen O.

    2016-10-01

    In many science and engineering applications, problems may result in solving a sparse linear system AX=B. For example, SuperLU_MCDT, a linear solver, was used for the large penta-diagonal matrices for 2D problems and hepta-diagonal matrices for 3D problems, coming from the incompressible blood flow simulation (see [1]). It is important to test the status and potential improvements of state-of-the-art solvers on new technologies. In this work, sequential, multithreaded and distributed versions of SuperLU solvers (see [2]) are examined on the Intel Xeon Phi coprocessors using offload programming model at the EURORA cluster of CINECA in Italy. We consider a portfolio of test matrices containing patterned matrices from UFMM ([3]) and randomly located matrices. This architecture can benefit from high parallelism and large vectors. We find that the sequential SuperLU benefited up to 45 % performance improvement from the offload programming depending on the sparse matrix type and the size of transferred and processed data.

  15. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    OpenAIRE

    H. Wang; H. Wang; H. Wang; H. Wang; H. Chen; H. Chen; Q. Wu; Q. Wu; J. Lin; X. Chen; X. Xie; R. Wang; R. Wang; X. Tang; Z. Wang

    2017-01-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (code...

  16. Single chip camera active pixel sensor

    Science.gov (United States)

    Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

    2003-01-01

    A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

  17. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  18. An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

    Science.gov (United States)

    Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

    2001-11-01

    The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

  19. An efficient MPI/OpenMP parallelization of the Hartree–Fock–Roothaan method for the first generation of Intel® Xeon Phi™ processor architecture

    International Nuclear Information System (INIS)

    Mironov, Vladimir; Moskovsky, Alexander; D’Mello, Michael; Alexeev, Yuri

    2017-01-01

    The Hartree-Fock (HF) method in the quantum chemistry package GAMESS represents one of the most irregular algorithms in computation today. Major steps in the calculation are the irregular computation of electron repulsion integrals (ERIs) and the building of the Fock matrix. These are the central components of the main Self Consistent Field (SCF) loop, the key hotspot in Electronic Structure (ES) codes. By threading the MPI ranks in the official release of the GAMESS code, we not only speed up the main SCF loop (4x to 6x for large systems), but also achieve a significant (>2x) reduction in the overall memory footprint. These improvements are a direct consequence of memory access optimizations within the MPI ranks. We benchmark our implementation against the official release of the GAMESS code on the Intel R Xeon PhiTM supercomputer. Here, scaling numbers are reported on up to 7,680 cores on Intel Xeon Phi coprocessors.

  20. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  1. Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

    DEFF Research Database (Denmark)

    2000-01-01

    towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

  2. tavgM_2d_rad_Nx: MERRA 2D IAU Diagnostic, Radiation Surface and TOA, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXRAD) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXRAD or tavgM_2d_rad_Nx data product is the MERRA Data Assimilation System 2-Dimensional surface and TOA radiation flux that is time averaged single-level...

  3. Experiment list: SRX214086 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

  4. Optical lattice on an atom chip

    DEFF Research Database (Denmark)

    Gallego, D.; Hofferberth, S.; Schumm, Thorsten

    2009-01-01

    Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

  5. A method of computer aided design with self-generative models in NX Siemens environment

    Science.gov (United States)

    Grabowik, C.; Kalinowski, K.; Kempa, W.; Paprocka, I.

    2015-11-01

    Currently in CAD/CAE/CAM systems it is possible to create 3D design virtual models which are able to capture certain amount of knowledge. These models are especially useful in an automation of routine design tasks. These models are known as self-generative or auto generative and they can behave in an intelligent way. The main difference between the auto generative and fully parametric models consists in the auto generative models ability to self-organizing. In this case design model self-organizing means that aside from the possibility of making of automatic changes of model quantitative features these models possess knowledge how these changes should be made. Moreover they are able to change quality features according to specific knowledge. In spite of undoubted good points of self-generative models they are not so often used in design constructional process which is mainly caused by usually great complexity of these models. This complexity makes the process of self-generative time and labour consuming. It also needs a quite great investment outlays. The creation process of self-generative model consists of the three stages it is knowledge and information acquisition, model type selection and model implementation. In this paper methods of the computer aided design with self-generative models in NX Siemens CAD/CAE/CAM software are presented. There are the five methods of self-generative models preparation in NX with: parametric relations model, part families, GRIP language application, knowledge fusion and OPEN API mechanism. In the paper examples of each type of the self-generative model are presented. These methods make the constructional design process much faster. It is suggested to prepare this kind of self-generative models when there is a need of design variants creation. The conducted research on assessing the usefulness of elaborated models showed that they are highly recommended in case of routine tasks automation. But it is still difficult to distinguish

  6. Experiment list: SRX214071 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2=

  7. Luminescence properties of Eu2+-doped MAl2-xSixO4-xNx (M = Ca, Sr, Ba) conversion phosphor for white LED applications

    NARCIS (Netherlands)

    Li, Y.Q.; With, de G.; Hintzen, H.T.J.M.

    2006-01-01

    Undoped and Eu-doped MAl2-xSixO4-2Nx (M = Ca, Sr, Ba) were synthesized by a solid-state reaction method at 1300 - 1400 ¿C under nitrogen-hydrogen atmosphere. The solubility of (SiN)+, in MAl2O4 was determined. Nitrogen can be incorporated into MAl2O4 by replacement of (AlO)+ by (SiN)+, whose amount

  8. Experiment list: SRX214075 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  9. Experiment list: SRX214074 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ge=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  10. Experiment list: SRX214072 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  11. Experiment list: SRX214067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available fferentiated || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacture...r 1=Santa Cruz || chip antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.bioscien

  12. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing; Yi, Xin; Xiao, Kang; Li, Shunbo; Kodzius, Rimantas; Qin, Jianhua; Wen, Weijia

    2013-01-01

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  13. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing

    2013-10-10

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  14. Drift chamber tracking with neural networks

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.

    1992-10-01

    We discuss drift chamber tracking with a commercial log VLSI neural network chip. Voltages proportional to the drift times in a 4-layer drift chamber were presented to the Intel ETANN chip. The network was trained to provide the intercept and slope of straight tracks traversing the chamber. The outputs were recorded and later compared off line to conventional track fits. Two types of network architectures were studied. Applications of neural network tracking to high energy physics detector triggers is discussed

  15. A Portable Parallel Implementation of the U.S. Navy Layered Ocean Model

    Science.gov (United States)

    1995-01-01

    Wallcraft, PhD (I.C. 1981) Planning Systems Inc. & P. R. Moore, PhD (Camb. 1971) IC Dept. Math. DR Moore 1° Encontro de Metodos Numericos...Kendall Square, Hypercube, D R Moore 1 ° Encontro de Metodos Numericos para Equacöes de Derivadas Parciais A. J. Wallcraft IC Mathematics...chips: Chips Machine DEC Alpha CrayT3D/E SUN Sparc Fujitsu AP1000 Intel 860 Paragon D R Moore 1° Encontro de Metodos Numericos para Equacöes

  16. Experiment list: SRX122523 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  17. Experiment list: SRX122414 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  18. Experiment list: SRX214077 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available erentiated || treatment=Overexpress Sox17_V5 tagged || cell line=KH2 || chip antibody 1=Sox17 || chip antibody manufacture...r 1=R&D || chip antibody 2=V5 || chip antibody manufacturer 2=Invit

  19. Experiment list: SRX122485 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100

  20. Experiment list: SRX122521 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  1. Experiment list: SRX122417 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  2. Experiment list: SRX122520 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  3. Experiment list: SRX122413 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  4. Experiment list: SRX122412 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  5. Experiment list: SRX122406 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http:/

  6. Experiment list: SRX122415 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  7. Experiment list: SRX122416 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  8. Experiment list: SRX122565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

  9. Experiment list: SRX122510 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Egr1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110 ht

  10. Experiment list: SRX122519 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  11. Experiment list: SRX122472 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Runx1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564 http

  12. Experiment list: SRX122473 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Runx1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564

  13. Experiment list: SRX122497 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  14. Experiment list: SRX122410 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  15. Experiment list: SRX186172 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 1=YY1 || chip antibody manufacturer 1=Abcam || chip antibody 2=YY1 || chip antibody manufacturer 2=Santa Cru...ip-Seq; Mus musculus; ChIP-Seq source_name=Rag1 -/- pro-B cells || chip antibody

  16. Experiment list: SRX122493 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-200

  17. Experiment list: SRX122571 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http

  18. Experiment list: SRX122411 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  19. Experiment list: SRX122498 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  20. Experiment list: SRX122516 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  1. Experiment list: SRX122495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Rel || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody catal...og number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http://

  2. Experiment list: SRX122563 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  3. Experiment list: SRX122564 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  4. Experiment list: SRX122488 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  5. Experiment list: SRX122491 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  6. Experiment list: SRX122548 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  7. Experiment list: SRX122468 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rela || treatment=LPS || time=0 min || chip antibody manufacturer 1=Bethyl || chip antibody catalo...g number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372 htt

  8. Experiment list: SRX122561 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  9. Experiment list: SRX122409 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Irf1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody cata...log number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 htt

  10. Experiment list: SRX122487 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  11. Experiment list: SRX122552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  12. Experiment list: SRX122408 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Irf1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http

  13. Experiment list: SRX122513 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Egr1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110

  14. Experiment list: SRX122567 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  15. Experiment list: SRX122490 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  16. Experiment list: SRX122558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  17. Experiment list: SRX122494 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-2

  18. Experiment list: SRX122557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  19. Experiment list: SRX122492 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  20. Experiment list: SRX122549 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  1. Experiment list: SRX122484 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cata...log number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 http

  2. Experiment list: SRX122514 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available tibody=Irf2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog nu...mber 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://db

  3. Experiment list: SRX122570 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  4. Experiment list: SRX122569 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 h

  5. Experiment list: SRX122511 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Egr1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-11

  6. Experiment list: SRX122471 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Rela || treatment=LPS || time=60 min || chip antibody manufacturer 1=Bethyl || chip antibody cat...alog number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372

  7. Experiment list: SRX122554 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  8. Evaluation of the Intel iWarp parallel processor for space flight applications

    Science.gov (United States)

    Hine, Butler P., III; Fong, Terrence W.

    1993-01-01

    The potential of a DARPA-sponsored advanced processor, the Intel iWarp, for use in future SSF Data Management Systems (DMS) upgrades is evaluated through integration into the Ames DMS testbed and applications testing. The iWarp is a distributed, parallel computing system well suited for high performance computing applications such as matrix operations and image processing. The system architecture is modular, supports systolic and message-based computation, and is capable of providing massive computational power in a low-cost, low-power package. As a consequence, the iWarp offers significant potential for advanced space-based computing. This research seeks to determine the iWarp's suitability as a processing device for space missions. In particular, the project focuses on evaluating the ease of integrating the iWarp into the SSF DMS baseline architecture and the iWarp's ability to support computationally stressing applications representative of SSF tasks.

  9. Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

    DEFF Research Database (Denmark)

    Liu, Weifeng; Vinter, Brian

    2015-01-01

    of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over...

  10. Experiment list: SRX122551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ca...talog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A htt

  11. Experiment list: SRX122546 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  12. Experiment list: SRX122547 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  13. Experiment list: SRX214084 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available turer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox17-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufac

  14. Experiment list: SRX122544 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  15. Experiment list: SRX214082 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available facturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manu

  16. Experiment list: SRX122466 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Relb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Bethyl || chip antibody cata...log number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-226 h

  17. Experiment list: SRX122545 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  18. Experiment list: SRX214080 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  19. Experiment list: SRX214081 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  20. Experiment list: SRX214068 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available inoic acid || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacturer 1=Santa Cruz || chip... antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDat

  1. tavgM_2d_int_Nx: MERRA 2D IAU Diagnostic, Vertical Integrals and Budget Terms, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXINT) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXINT or tavgM_2d_int_Nx data product is the MERRA Data Assimilation System 2-Dimensional vertical integral that is time averaged single-level at the native...

  2. tavgM_2d_lnd_Nx: MERRA 2D IAU Diagnostic, Land Only States and Diagnostics, Monthly Mean 0.667 x 0.5 degree V5.2.0 (MATMNXLND) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MATMNXLND or tavgM_2d_lnd_Nx data product is the MERRA Data Assimilation System 2-Dimensional land surface diagnostic that is time averaged single-level at the...

  3. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  4. A new material platform of Si photonics for implementing architecture of dense wavelength division multiplexing on Si bulk wafer

    Science.gov (United States)

    Zhang, Ziyi; Yako, Motoki; Ju, Kan; Kawai, Naoyuki; Chaisakul, Papichaya; Tsuchizawa, Tai; Hikita, Makoto; Yamada, Koji; Ishikawa, Yasuhiko; Wada, Kazumi

    2017-12-01

    A new materials group to implement dense wavelength division multiplexing (DWDM) in Si photonics is proposed. A large thermo-optic (TO) coefficient of Si malfunctions multiplexer/demultiplexer (MUX/DEMUX) on a chip under thermal fluctuation, and thus DWDM implementation, has been one of the most challenging targets in Si photonics. The present study specifies an optical materials group for DWDM by a systematic survey of their TO coefficients and refractive indices. The group is classified as mid-index contrast optics (MiDex) materials, and non-stoichiometric silicon nitride (SiNx) is chosen to demonstrate its significant thermal stability. The TO coefficient of non-stoichiometric SiNx is precisely measured in the temperature range 24-76 °C using the SiNx rings prepared by two methods: chemical vapor deposition (CVD) and physical vapor deposition (PVD). The CVD-SiNx ring reveals nearly the same TO coefficient reported for stoichiometric CVD-Si3N4, while the value for the PVD-SiNx ring is slightly higher. Both SiNx rings lock their resonance frequencies within 100 GHz in this temperature range. Since CVD-SiNx needs a high temperature annealing to reduce N-H bond absorption, it is concluded that PVD-SiNx is suited as a MiDex material introduced in the CMOS back-end-of-line. Further stabilization is required, considering the crosstalk between two channels; a 'silicone' polymer is employed to compensate for the temperature fluctuation using its negative TO coefficient, called athermalization. This demonstrates that the resonance of these SiNx rings is locked within 50 GHz at the same temperature range in the wavelength range 1460-1620 nm (the so-called S, C, and L bands in optical fiber communication networks). A further survey on the MiDex materials strongly suggests that Al2O3, Ga2O3 Ta2O5, HfO2 and their alloys should provide even more stable platforms for DWDM implementation in MiDex photonics. It is discussed that the MiDex photonics will find various applications

  5. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™

    Science.gov (United States)

    Gomes, Jeremias M.; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H.

    2016-01-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel® Xeon Phi™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP’s irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high performance. However, SIMD atomic instructions are not supported. Therefore, we propose a new IWPP algorithm that can take advantage of the supported SIMD instruction set. We also evaluate an alternate storage container (priority queue) to track active elements in the wavefront in an effort to improve the parallel algorithm efficiency. The new IWPP algorithm is evaluated with Morphological Reconstruction and Imfill operations as use cases. Our results show performance improvements of up to 5.63× on top of the original IWPP due to vectorization. Moreover, the new IWPP achieves speedups of 45.7× and 1.62×, respectively, as compared to efficient CPU and GPU implementations. PMID:27298591

  6. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™.

    Science.gov (United States)

    Gomes, Jeremias M; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H

    2015-10-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel ® Xeon Phi ™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP's irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high performance. However, SIMD atomic instructions are not supported. Therefore, we propose a new IWPP algorithm that can take advantage of the supported SIMD instruction set. We also evaluate an alternate storage container (priority queue) to track active elements in the wavefront in an effort to improve the parallel algorithm efficiency. The new IWPP algorithm is evaluated with Morphological Reconstruction and Imfill operations as use cases. Our results show performance improvements of up to 5.63 × on top of the original IWPP due to vectorization. Moreover, the new IWPP achieves speedups of 45.7 × and 1.62 × , respectively, as compared to efficient CPU and GPU implementations.

  7. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  8. tavg1_2d_flx_Nx: MERRA 2D IAU Diagnostic, Surface Fluxes, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXFLX) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXFLX or tavg1_2d_flx_Nx data product is the MERRA Data Assimilation System 2-Dimensional surface turbulence flux diagnostic that is time averaged...

  9. Plasma Science and Applications at the Intel Science Fair: A Retrospective

    Science.gov (United States)

    Berry, Lee

    2009-11-01

    For the past five years, the Coalition for Plasma Science (CPS) has presented an award for a plasma project at the Intel International Science and Engineering Fair (ISEF). Eligible projects have ranged from grape-based plasma production in a microwave oven to observation of the effects of viscosity in a fluid model of quark-gluon plasma. Most projects have been aimed at applications, including fusion, thrusters, lighting, materials processing, and GPS improvements. However diagnostics (spectroscopy), technology (magnets), and theory (quark-gluon plasmas) have also been represented. All of the CPS award-winning projects so far have been based on experiments, with two awards going to women students and three to men. Since the award was initiated, both the number and quality of plasma projects has increased. The CPS expects this trend to continue, and looks forward to continuing its work with students who are excited about the possibilities of plasma. You too can share this excitement by judging at the 2010 fair in San Jose on May 11-12.

  10. tavg1_2d_ocn_Nx: MERRA 2D IAU Ocean Surface Diagnostic, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXOCN) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXOCN or tavg1_2d_ocn_Nx data product is the MERRA Data Assimilation System 2-Dimensional ocean surface single-level diagnostics that is time averaged...

  11. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  12. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  13. Effect of hydrogen on the device performance and stability characteristics of amorphous InGaZnO thin-film transistors with a SiO2/SiNx/SiO2 buffer

    Science.gov (United States)

    Han, Ki-Lim; Ok, Kyung-Chul; Cho, Hyeon-Su; Oh, Saeroonter; Park, Jin-Seong

    2017-08-01

    We investigate the influence of the multi-layered buffer consisting of SiO2/SiNx/SiO2 on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The multi-layered buffer inhibits permeation of water from flexible plastic substrates and prevents degradation of overlying organic layers. The a-IGZO TFTs with a multi-layered buffer suffer less positive bias temperature stress instability compared to the device with a single SiO2 buffer layer after annealing at 250 °C. Hydrogen from the SiNx layer diffuses into the active layer and reduces electron trapping at loosely bound oxygen defects near the SiO2/a-IGZO interface. Quantitative analysis shows that a hydrogen density of 1.85 × 1021 cm-3 is beneficial to reliability. However, the multi-layered buffer device annealed at 350 °C resulted in conductive characteristics due to the excess carrier concentration from the higher hydrogen density of 2.12 × 1021 cm-3.

  14. Lab-on a-Chip

    Science.gov (United States)

    1999-01-01

    Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

  15. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    Science.gov (United States)

    Farrell, Steven; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea; ATLAS Collaboration

    2017-10-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with details on its multi-threaded design. Then, we will present a performance analysis of the application on KNL devices and compare it to a traditional x86 platform to demonstrate the capabilities of the architecture and evaluate the benefits of utilizing KNL platforms like Cori for ATLAS production.

  16. tavg1_2d_slv_Nx: MERRA 2D IAU Diagnostic, Single Level Meteorology, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXSLV) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXSLV or tavg1_2d_slv_Nx data product is the MERRA Data Assimilation System 2-Dimensional atmospheric single-level diagnostics that is time averaged...

  17. La responsabilitat davant la intel·ligència artificial en el comerç electrònic

    OpenAIRE

    Martín i Palomas, Elisabet

    2015-01-01

    Es planteja en aquesta tesi l'efecte produït sobre la responsabilitat derivada de les accions realitzades autònomament per sistemes dotats d'intel·ligència artificial, sense la participació directa de cap ésser humà, en els temes més directament relacionats amb el comerç electrònic. Per a això s'analitzen les activitats realitzades per algunes de les principals empreses internacionals de comerç electrònic, com el grup nord-americà eBay o el grup xinès Alibaba. Després de desenvolupar els prin...

  18. Enhanced poly(γ-glutamic acid) production by H2 O2 -induced reactive oxygen species in the fermentation of Bacillus subtilis NX-2.

    Science.gov (United States)

    Tang, Bao; Zhang, Dan; Li, Sha; Xu, Zongqi; Feng, Xiaohai; Xu, Hong

    2016-09-01

    Effects of reactive oxygen species (ROS) on cell growth and poly(γ-glutamic acid) (γ-PGA) synthesis were studied by adding hydrogen peroxide to a medium of Bacillus subtilis NX-2. After optimizing the addition concentration and time of H 2 O 2 , a maximum concentration of 33.9 g/L γ-PGA was obtained by adding 100 µM H 2 O 2 to the medium after 24 H. This concentration was 20.6% higher than that of the control. The addition of diphenyleneiodonium chloride (ROS inhibitor) can interdict the effect of H 2 O 2 -induced ROS. Transcriptional levels of the cofactors and relevant genes were also determined under ROS stress to illustrate the possible metabolic mechanism contributing to the improve γ-PGA production. The transcriptional levels of genes belonging to the tricarboxylic acid cycle and electron transfer chain system were significantly increased by ROS, which decreased the NADH/NAD + ratio and increased the ATP levels, thereby providing more reducing power and energy for γ-PGA biosynthesis. The enhanced γ-PGA synthetic genes also directly promoted the formation of γ-PGA. This study was the first to use the ROS control strategy for γ-PGA fermentation and provided valuable information on the possible mechanism by which ROS regulated γ-PGA biosynthesis in B. subtilis NX-2. © 2015 International Union of Biochemistry and Molecular Biology, Inc.

  19. Future home hemodialysis - advantages of the NxStage System One.

    Science.gov (United States)

    Takahashi, Susumu

    2012-01-01

    To improve the quality of life (QOL) of patients with renal failure who are on dialysis, we have been working to promote home hemodialysis (HHD), but it has not come into widespread use at present because of various problems, including limitations of the equipment, the large proportion of elderly patients, and difficulty performing self-care. With regard to problems with the equipment, dialysis equipment for home use has not yet been approved in Japan, so equipment designed for medical facilities has to be used for home dialysis. Such equipment is bulky and occupies living space, as well as involving the cost of home renovation and the need for a caregiver. The NxStage System One (NSO) artificial kidney has served advantages for HHD compared with conventional equipment, since it is compact, portable, and easy to operate (especially for preparation and cleaning), does not require a water supply, occupies less living space, and reduces the need for renovation of the home. Other advantages of the NSO include improvement of QOL by saving time travelling to hospitals and helping patients to participate in social activities. In addition, HHD with the NSO can improve sleep disorders, the restless legs syndrome, and depressive symptoms, resulting in a good outcome. Moreover, HHD with the NSO reduces the need for drugs, such as antihypertensive medications and erythropoietin, possibly leading to saving of healthcare costs. Copyright © 2012 S. Karger AG, Basel.

  20. Communication overhead on the Intel Paragon, IBM SP2 and Meiko CS-2

    Science.gov (United States)

    Bokhari, Shahid H.

    1995-01-01

    Interprocessor communication overhead is a crucial measure of the power of parallel computing systems-its impact can severely limit the performance of parallel programs. This report presents measurements of communication overhead on three contemporary commercial multicomputer systems: the Intel Paragon, the IBM SP2 and the Meiko CS-2. In each case the time to communicate between processors is presented as a function of message length. The time for global synchronization and memory access is discussed. The performance of these machines in emulating hypercubes and executing random pairwise exchanges is also investigated. It is shown that the interprocessor communication time depends heavily on the specific communication pattern required. These observations contradict the commonly held belief that communication overhead on contemporary machines is independent of the placement of tasks on processors. The information presented in this report permits the evaluation of the efficiency of parallel algorithm implementations against standard baselines.

  1. Performance Evaluation of Multithreaded Geant4 Simulations Using an Intel Xeon Phi Cluster

    Directory of Open Access Journals (Sweden)

    P. Schweitzer

    2015-01-01

    Full Text Available The objective of this study is to evaluate the performances of Intel Xeon Phi hardware accelerators for Geant4 simulations, especially for multithreaded applications. We present the complete methodology to guide users for the compilation of their Geant4 applications on Phi processors. Then, we propose series of benchmarks to compare the performance of Xeon CPUs and Phi processors for a Geant4 example dedicated to the simulation of electron dose point kernels, the TestEm12 example. First, we compare a distributed execution of a sequential version of the Geant4 example on both architectures before evaluating the multithreaded version of the Geant4 example. If Phi processors demonstrated their ability to accelerate computing time (till a factor 3.83 when distributing sequential Geant4 simulations, we do not reach the same level of speedup when considering the multithreaded version of the Geant4 example.

  2. Optimal selection of TLD chips

    International Nuclear Information System (INIS)

    Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

    1996-01-01

    Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

  3. Computer Architecture A Quantitative Approach

    CERN Document Server

    Hennessy, John L

    2007-01-01

    The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelis

  4. Power and performance software analysis and optimization

    CERN Document Server

    Kukunas, Jim

    2015-01-01

    Power and Performance: Software Analysis and Optimization is a guide to solving performance problems in modern Linux systems. Power-efficient chips are no help if the software those chips run on is inefficient. Starting with the necessary architectural background as a foundation, the book demonstrates the proper usage of performance analysis tools in order to pinpoint the cause of performance problems, and includes best practices for handling common performance issues those tools identify. Provides expert perspective from a key member of Intel's optimization team on how processors and memory

  5. Broadband enhancement of single photon emission and polarization dependent coupling in silicon nitride waveguides.

    Science.gov (United States)

    Bisschop, Suzanne; Guille, Antoine; Van Thourhout, Dries; Hens, Zeger; Brainis, Edouard

    2015-06-01

    Single-photon (SP) sources are important for a number of optical quantum information processing applications. We study the possibility to integrate triggered solid-state SP emitters directly on a photonic chip. A major challenge consists in efficiently extracting their emission into a single guided mode. Using 3D finite-difference time-domain simulations, we investigate the SP emission from dipole-like nanometer-sized inclusions embedded into different silicon nitride (SiNx) photonic nanowire waveguide designs. We elucidate the effect of the geometry on the emission lifetime and the polarization of the emitted SP. The results show that highly efficient and polarized SP sources can be realized using suspended SiNx slot-waveguides. Combining this with the well-established CMOS-compatible processing technology, fully integrated and complex optical circuits for quantum optics experiments can be developed.

  6. Experiment list: SRX110782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e3 (ab6002, abcam), Pol II (CTD4H8, Millipore) || chip antibody 1 manufacturer=ab...cam || chip antibody 2=Pol II (CTD4H8, Millipore) || chip antibody 2 manufacturer=Millipore http://dbarchive

  7. Avaliação da aceitação de "chips" de mandioca Acceptance evaluation of cassava chips

    Directory of Open Access Journals (Sweden)

    Regina Kitagawa Grizotto

    2003-12-01

    Full Text Available Pré-tratamentos como o cozimento, a fermentação natural e a secagem parcial foram aplicados em raízes de mandioca, visando a obtenção de "chips" comestíveis. A avaliação sensorial foi feita com base na aceitação e aparência dos "chips" das variedades IAC Mantiqueira e IAC 576.70. Trinta consumidores potenciais do produto foram selecionados em função da disponibilidade e interesse em participar dos testes. Foi utilizada escala hedônica de 7 pontos, onde os provadores avaliaram as amostras delineadas em blocos casualizados. Os resultados obtidos mostraram que os "chips" controle e pré-cozidos foram aceitos sensorialmente, apresentado médias de 5,1 (gostei ligeiramente para IAC Mantiqueira e 6,0 (gostei moderadamente para IAC 576.70. Os "chips" pré-fermentados de ambas variedades foram rejeitados. Os termos de agrado mais comentados pelos provadores foram "sabor de mandioca", "crocância" e "textura". Os termos de desagrado mais citados incluem "textura dura", "falta sabor de mandioca" e "gosto de óleo". Os provadores consideraram adequada a aparência dos "chips" de ambas variedades, sendo ligeiramente preferida a aparência dos "chips" da IAC 576.70, com exceção dos "chips" cozidos por 8 minutos e os fermentados, rejeitados pelos consumidores. A cor amarela da polpa pode ter influenciado a aceitação da variedade IAC 576.70. A composição centesimal e o teor de fibras na mandioca in natura e, o teor de lipídeos em "chips" de mandioca, também foram apresentados.Pre-treatments such as cooking, natural fermentation and partial drying were applied to cassava roots, aimed at obtaining edible cassava chips. The sensory evaluation was based on the acceptance and appearance of the chips, using the varieties IAC Mantiqueira and IAC 576.70. Thirty potential consumers of the product were selected based on their availability and interest. A 7-point hedonic scale was used, all the judges evaluating all the samples using a randomised

  8. Fully Automated On-Chip Imaging Flow Cytometry System with Disposable Contamination-Free Plastic Re-Cultivation Chip

    Directory of Open Access Journals (Sweden)

    Tomoyuki Kaneko

    2011-06-01

    Full Text Available We have developed a novel imaging cytometry system using a poly(methyl methacrylate (PMMA based microfluidic chip. The system was contamination-free, because sample suspensions contacted only with a flammable PMMA chip and no other component of the system. The transparency and low-fluorescence of PMMA was suitable for microscopic imaging of cells flowing through microchannels on the chip. Sample particles flowing through microchannels on the chip were discriminated by an image-recognition unit with a high-speed camera in real time at the rate of 200 event/s, e.g., microparticles 2.5 μm and 3.0 μm in diameter were differentiated with an error rate of less than 2%. Desired cells were separated automatically from other cells by electrophoretic or dielectrophoretic force one by one with a separation efficiency of 90%. Cells in suspension with fluorescent dye were separated using the same kind of microfluidic chip. Sample of 5 μL with 1 × 106 particle/mL was processed within 40 min. Separated cells could be cultured on the microfluidic chip without contamination. The whole operation of sample handling was automated using 3D micropipetting system. These results showed that the novel imaging flow cytometry system is practically applicable for biological research and clinical diagnostics.

  9. Real time track finding in a drift chamber with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-01-01

    In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

  10. Network structure and functional properties of transparent hydrogel sanxan produced by Sphingomonas sanxanigenens NX02.

    Science.gov (United States)

    Wu, Mengmeng; Shi, Zhong; Huang, Haidong; Qu, Jianmei; Dai, Xiaohui; Tian, Xuefeng; Wei, Weiying; Li, Guoqiang; Ma, Ting

    2017-11-15

    The micro-network structure and functional properties of sanxan, a novel polysaccharide produced by Sphingomonas sanxanigenens NX02, were investigated. Transparent hydrogel sanxan was a high acyl polymer containing 8.96% acetyl and 4.75% glyceroyl. The micro-network structure of sanxan was mainly cyclic configurations composed of side-by-side intermolecular associations, with many rounded nodes found. Sanxan exhibited predominant gelation behavior at concentrations above 0.1%, which was enhanced by adding cations, especially Ca 2+ . The gel strength of sanxan was much higher than that of low acyl gellan, but slightly lower than that of high acyl gellan. Furthermore, the conformation transition temperature was increased in the presence of added cations. Moreover, sanxan showed excellent emulsifying and emulsion stabilizing properties. Consequently, such excellent functional properties make sanxan a good candidate as a gelling, stabilizing, emulsifying, or suspending agent in food and cosmetics industries, and in medical and pharmaceutical usage. Copyright © 2017 Elsevier Ltd. All rights reserved.

  11. Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

    Science.gov (United States)

    Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

    2012-06-01

    The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

  12. ChIP on SNP-chip for genome-wide analysis of human histone H4 hyperacetylation

    Directory of Open Access Journals (Sweden)

    Porter Christopher J

    2007-09-01

    Full Text Available Abstract Background SNP microarrays are designed to genotype Single Nucleotide Polymorphisms (SNPs. These microarrays report hybridization of DNA fragments and therefore can be used for the purpose of detecting genomic fragments. Results Here, we demonstrate that a SNP microarray can be effectively used in this way to perform chromatin immunoprecipitation (ChIP on chip as an alternative to tiling microarrays. We illustrate this novel application by mapping whole genome histone H4 hyperacetylation in human myoblasts and myotubes. We detect clusters of hyperacetylated histone H4, often spanning across up to 300 kilobases of genomic sequence. Using complementary genome-wide analyses of gene expression by DNA microarray we demonstrate that these clusters of hyperacetylated histone H4 tend to be associated with expressed genes. Conclusion The use of a SNP array for a ChIP-on-chip application (ChIP on SNP-chip will be of great value to laboratories whose interest is the determination of general rules regarding the relationship of specific chromatin modifications to transcriptional status throughout the genome and to examine the asymmetric modification of chromatin at heterozygous loci.

  13. Simulating the Effect of Modulated Tool-Path Chip Breaking On Surface Texture and Chip Length

    Energy Technology Data Exchange (ETDEWEB)

    Smith, K.S.; McFarland, J.T.; Tursky, D. A.; Assaid, T. S.; Barkman, W. E.; Babelay, Jr., E. F.

    2010-04-30

    One method for creating broken chips in turning processes involves oscillating the cutting tool in the feed direction utilizing the CNC machine axes. The University of North Carolina at Charlotte and the Y-12 National Security Complex have developed and are refining a method to reliably control surface finish and chip length based on a particular machine's dynamic performance. Using computer simulations it is possible to combine the motion of the machine axes with the geometry of the cutting tool to predict the surface characteristics and map the surface texture for a wide range of oscillation parameters. These data allow the selection of oscillation parameters to simultaneously ensure broken chips and acceptable surface characteristics. This paper describes the machine dynamic testing and characterization activities as well as the computational method used for evaluating and predicting chip length and surface texture.

  14. tavg1_2d_rad_Nx: MERRA 2D IAU Diagnostic, Radiation Surface and TOA, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXRAD) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXRAD or tavg1_2d_rad_Nx data product is the MERRA Data Assimilation System 2-Dimensional surface and TOA radiation flux that is time averaged single-level...

  15. Deployment of the OSIRIS EM-PIC code on the Intel Knights Landing architecture

    Science.gov (United States)

    Fonseca, Ricardo

    2017-10-01

    Electromagnetic particle-in-cell (EM-PIC) codes such as OSIRIS have found widespread use in modelling the highly nonlinear and kinetic processes that occur in several relevant plasma physics scenarios, ranging from astrophysical settings to high-intensity laser plasma interaction. Being computationally intensive, these codes require large scale HPC systems, and a continuous effort in adapting the algorithm to new hardware and computing paradigms. In this work, we report on our efforts on deploying the OSIRIS code on the new Intel Knights Landing (KNL) architecture. Unlike the previous generation (Knights Corner), these boards are standalone systems, and introduce several new features, include the new AVX-512 instructions and on-package MCDRAM. We will focus on the parallelization and vectorization strategies followed, as well as memory management, and present a detailed performance evaluation of code performance in comparison with the CPU code. This work was partially supported by Fundaçã para a Ciência e Tecnologia (FCT), Portugal, through Grant No. PTDC/FIS-PLA/2940/2014.

  16. Modeling high-temperature superconductors and metallic alloys on the Intel IPSC/860

    Science.gov (United States)

    Geist, G. A.; Peyton, B. W.; Shelton, W. A.; Stocks, G. M.

    Oak Ridge National Laboratory has embarked on several computational Grand Challenges, which require the close cooperation of physicists, mathematicians, and computer scientists. One of these projects is the determination of the material properties of alloys from first principles and, in particular, the electronic structure of high-temperature superconductors. While the present focus of the project is on superconductivity, the approach is general enough to permit study of other properties of metallic alloys such as strength and magnetic properties. This paper describes the progress to date on this project. We include a description of a self-consistent KKR-CPA method, parallelization of the model, and the incorporation of a dynamic load balancing scheme into the algorithm. We also describe the development and performance of a consolidated KKR-CPA code capable of running on CRAYs, workstations, and several parallel computers without source code modification. Performance of this code on the Intel iPSC/860 is also compared to a CRAY 2, CRAY YMP, and several workstations. Finally, some density of state calculations of two perovskite superconductors are given.

  17. Balancing Contention and Synchronization on the Intel Paragon

    Science.gov (United States)

    Bokhari, Shahid H.; Nicol, David M.

    1996-01-01

    The Intel Paragon is a mesh-connected distributed memory parallel computer. It uses an oblivious and deterministic message routing algorithm: this permits us to develop highly optimized schedules for frequently needed communication patterns. The complete exchange is one such pattern. Several approaches are available for carrying it out on the mesh. We study an algorithm developed by Scott. This algorithm assumes that a communication link can carry one message at a time and that a node can only transmit one message at a time. It requires global synchronization to enforce a schedule of transmissions. Unfortunately global synchronization has substantial overhead on the Paragon. At the same time the powerful interconnection mechanism of this machine permits 2 or 3 messages to share a communication link with minor overhead. It can also overlap multiple message transmission from the same node to some extent. We develop a generalization of Scott's algorithm that executes complete exchange with a prescribed contention. Schedules that incur greater contention require fewer synchronization steps. This permits us to tradeoff contention against synchronization overhead. We describe the performance of this algorithm and compare it with Scott's original algorithm as well as with a naive algorithm that does not take interconnection structure into account. The Bounded contention algorithm is always better than Scott's algorithm and outperforms the naive algorithm for all but the smallest message sizes. The naive algorithm fails to work on meshes larger than 12 x 12. These results show that due consideration of processor interconnect and machine performance parameters is necessary to obtain peak performance from the Paragon and its successor mesh machines.

  18. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  19. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  20. Experiment list: SRX485203 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346544: Rhino ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  1. Experiment list: SRX485202 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346543: Rhino ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  2. Experiment list: SRX485210 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6551: Deadlock ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name...=Deadlock ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made

  3. Experiment list: SRX485211 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346552: Cutoff ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=...Cutoff ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=control || chip antibody=custom-made rabb

  4. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  5. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  6. Influence of passivation process on chip performance

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; Schmitz, Jurriaan

    2009-01-01

    In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition

  7. Experiment list: SRX485205 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 46546: Rhino ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=R...hino ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made rabb

  8. Experiment list: SRX485212 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346553: Cutoff ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=C...utoff ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female |...| tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit

  9. Experiment list: SRX485206 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346547: Rhino ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rh...ino ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ...tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit po

  10. Experiment list: SRX485209 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346550: Deadlock ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_nam...e=Deadlock ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=custom-made

  11. The use of forest chips in Finland

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    International commitments require the industrial world to restrict their greenhouse gas emissions. In Finland, where the annual timber cut per capita is more than ten times the average cut in the other EU countries, the primary means to reduce CO 2 emissions is to replace fossil fuels with forest biomass. The annual consumption of wood-based energy corresponds to 6 million tonnes of oil equivalent (toe) or almost 20% of the total primary energy consumption. The goal is to rise the annual production of wood-based energy to 7.8 million toe by 2010. Substantial part of the targeted increase could be obtained by forest chips produced of unmerchantable small-diameter trees and logging residues. The goal for 2010 is to use 5 million solid m 3 of forest chips, which equals to 0.9 million toe. The use of forest chips is increasing. About 474 000 solid m 3 of forest chips were used as fuel in 1999. At the moment, the growth is rapid especially in cogeneration plants producing both heat and electricity. The growth is based primarily on chips obtained from logging residues. The price of forest chips decreased considerably during the 1990s but the price range remained wide. Chips made of logging residues are cheaper than those made of small trees. The average price of forest chips at the plant, VAT excluded, is about 53 FIM per MWh. In Sweden, the average price is more than 40% higher

  12. Application of Intel Many Integrated Core (MIC) architecture to the Yonsei University planetary boundary layer scheme in Weather Research and Forecasting model

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Weather Research and Forecasting (WRF) model provided operational services worldwide in many areas and has linked to our daily activity, in particular during severe weather events. The scheme of Yonsei University (YSU) is one of planetary boundary layer (PBL) models in WRF. The PBL is responsible for vertical sub-grid-scale fluxes due to eddy transports in the whole atmospheric column, determines the flux profiles within the well-mixed boundary layer and the stable layer, and thus provide atmospheric tendencies of temperature, moisture (including clouds), and horizontal momentum in the entire atmospheric column. The YSU scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. To accelerate the computation process of the YSU scheme, we employ Intel Many Integrated Core (MIC) Architecture as it is a multiprocessor computer structure with merits of efficient parallelization and vectorization essentials. Our results show that the MIC-based optimization improved the performance of the first version of multi-threaded code on Xeon Phi 5110P by a factor of 2.4x. Furthermore, the same CPU-based optimizations improved the performance on Intel Xeon E5-2603 by a factor of 1.6x as compared to the first version of multi-threaded code.

  13. Experiment list: SRX485220 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 53 GSM1346561: RNA Polymerase II ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-...Seq source_name=RNA Polymerase II ChIP from rhino germline knock-down ovaries || developmental stage=4-6 day...s old adult || Sex=female || tissue=ovary || germline knock-down=rhino || chip an

  14. Experiment list: SRX485204 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346545: Rhino ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rhi...no ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ti...ssue=ovary || germline knock-down=rhino || chip antibody=custom-made rabbit polyc

  15. Experiment list: SRX485208 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346549: Rhino ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq sou...rce_name=Rhino ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=piwi || chip antibody=custom-made ra

  16. METAL CHIP HEATING PROCESS INVESTIGATION (Part I

    Directory of Open Access Journals (Sweden)

    O. M. Dyakonov

    2007-01-01

    Full Text Available The main calculation methods for heat- and mass transfer in porous heterogeneous medium have been considered. The paper gives an evaluation of the possibility to apply them for calculation of metal chip heating process. It has been shown that a description of transfer processes in a chip has its own specific character that is attributed to difference between thermal and physical properties of chip material and lubricant-coolant components on chip surfaces. It has been determined that the known expressions for effective heat transfer coefficients can be used as basic ones while approaching mutually penetrating continuums. A mathematical description of heat- and mass transfer in chip medium can be considered as a basis of mathematical modeling, numerical solution and parameter optimization of the mentioned processes.

  17. tavg1_2d_int_Nx: MERRA 2D IAU Diagnostic, Vertical Integrals and Budget Terms, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXINT) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXINT or tavg1_2d_int_Nx data product is the MERRA Data Assimilation System 2-Dimensional vertical integral that is time averaged single-level at the native...

  18. tavg1_2d_lnd_Nx: MERRA 2D IAU Diagnostic, Land Only States and Diagnostics, Time Average 1-hourly 0.667 x 0.5 degree V5.2.0 (MAT1NXLND) at GES DISC

    Data.gov (United States)

    National Aeronautics and Space Administration — The MAT1NXLND or tavg1_2d_lnd_Nx data product is the MERRA Data Assimilation System 2-Dimensional land surface diagnostic that is time averaged single-level at the...

  19. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  20. Wood chip delivery and research project at Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1995-01-01

    In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m 3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m 3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m 3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m 3 /a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

  1. Performance optimization of Qbox and WEST on Intel Knights Landing

    Science.gov (United States)

    Zheng, Huihuo; Knight, Christopher; Galli, Giulia; Govoni, Marco; Gygi, Francois

    We present the optimization of electronic structure codes Qbox and WEST targeting the Intel®Xeon Phi™processor, codenamed Knights Landing (KNL). Qbox is an ab-initio molecular dynamics code based on plane wave density functional theory (DFT) and WEST is a post-DFT code for excited state calculations within many-body perturbation theory. Both Qbox and WEST employ highly scalable algorithms which enable accurate large-scale electronic structure calculations on leadership class supercomputer platforms beyond 100,000 cores, such as Mira and Theta at the Argonne Leadership Computing Facility. In this work, features of the KNL architecture (e.g. hierarchical memory) are explored to achieve higher performance in key algorithms of the Qbox and WEST codes and to develop a road-map for further development targeting next-generation computing architectures. In particular, the optimizations of the Qbox and WEST codes on the KNL platform will target efficient large-scale electronic structure calculations of nanostructured materials exhibiting complex structures and prediction of their electronic and thermal properties for use in solar and thermal energy conversion device. This work was supported by MICCoM, as part of Comp. Mats. Sci. Program funded by the U.S. DOE, Office of Sci., BES, MSE Division. This research used resources of the ALCF, which is a DOE Office of Sci. User Facility under Contract DE-AC02-06CH11357.

  2. Experiment list: SRX485222 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 4me2 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimethy

  3. Experiment list: SRX485221 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K4me2 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimeth

  4. Rework of flip chip bonded radiation pixel detectors

    International Nuclear Information System (INIS)

    Vaehaenen, S.; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S.

    2008-01-01

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process

  5. Rework of flip chip bonded radiation pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Vaehaenen, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)], E-mail: sami.vahanen@vtt.fi; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)

    2008-06-11

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process.

  6. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  7. Experiment list: SRX485218 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_name...=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 anti

  8. Experiment list: SRX485213 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  9. Experiment list: SRX485214 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  10. 75 FR 16149 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-April 26, 2010

    Science.gov (United States)

    2010-03-31

    ... DEPARTMENT OF HEALTH AND HUMAN SERVICES Centers for Medicare & Medicaid Services [CMS-2312-N] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP Working Group-- April 26, 2010 AGENCIES: Centers for Medicare & Medicaid Services (CMS), Department of...

  11. Electromagnetic modeling and optimization of packaged photodetector modules for 100 Gbit/s applications

    DEFF Research Database (Denmark)

    Jiang, Chenhui; Krozer, Viktor; Bach, H-G

    2008-01-01

    In this paper, we propose an accurate full 3D EM behavioral model of PD chips for the first time. The model, which is meshed at 130 GHz, runs for about 17 minutes on an Intel Core2 Duo CPU@3 GHz PC with 3.5 GB of RAM. The impact of various parameters in wire- bonding transitions for transmission...

  12. Modelling, Synthesis, and Configuration of Networks-on-Chips

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo

    This thesis presents three contributions in two different areas of network-on-chip and system-on-chip research: Application modelling and identifying and solving different optimization problems related to two specific network-on-chip architectures. The contribution related to application modelling...... is an analytical method for deriving the worst-case traffic pattern caused by an application and the cache-coherence protocol in a cache-coherent shared-memory system. The contributions related to network-on-chip optimization problems consist of two parts: The development and evaluation of six heuristics...... for solving the network synthesis problem in the MANGO network-on-chip, and the identification and formalization of the ReNoC configuration problem together with three heuristics for solving it....

  13. Research of Dielectric Breakdown Micro fluidic Sampling Chip

    International Nuclear Information System (INIS)

    Jiang, F.; Lei, Y.; Yu, J.

    2013-01-01

    Micro fluidic chip is mainly driven electrically by external electrode and array electrode, but there are certain disadvantages in both of ways, which affect the promotion and application of micro fluidic technology. This paper discusses a scheme that uses the conductive solution in a microchannel made by PDMS, replacing electrodes and the way of dielectric breakdown to achieve microfluidic chip driver. It could reduce the driving voltage and simplify the chip production process. To prove the feasibility of this method, we produced a micro fluidic chip used in PDMS material with the lithography technology and experimented it. The results showed that using the dielectric breakdown to achieve microfluidic chip driver is feasible, and it has certain application prospect.

  14. Experiment list: SRX485216 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from rhino germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fema...le || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3

  15. Experiment list: SRX485215 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from rhino germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=femal...e || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3 a

  16. Experiment list: SRX485217 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from piwi germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 ant

  17. ReseqChip: Automated integration of multiple local context probe data from the MitoChip array in mitochondrial DNA sequence assembly

    Directory of Open Access Journals (Sweden)

    Spang Rainer

    2009-12-01

    Full Text Available Abstract Background The Affymetrix MitoChip v2.0 is an oligonucleotide tiling array for the resequencing of the human mitochondrial (mt genome. For each of 16,569 nucleotide positions of the mt genome it holds two sets of four 25-mer probes each that match the heavy and the light strand of a reference mt genome and vary only at their central position to interrogate all four possible alleles. In addition, the MitoChip v2.0 carries alternative local context probes to account for known mtDNA variants. These probes have been neglected in most studies due to the lack of software for their automated analysis. Results We provide ReseqChip, a free software that automates the process of resequencing mtDNA using multiple local context probes on the MitoChip v2.0. ReseqChip significantly improves base call rate and sequence accuracy. ReseqChip is available at http://code.open-bio.org/svnweb/index.cgi/bioperl/browse/bioperl-live/trunk/Bio/Microarray/Tools/. Conclusions ReseqChip allows for the automated consolidation of base calls from alternative local mt genome context probes. It thereby improves the accuracy of resequencing, while reducing the number of non-called bases.

  18. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  19. Thermal-Aware Scheduling for Future Chip Multiprocessors

    Directory of Open Access Journals (Sweden)

    Pedro Trancoso

    2007-04-01

    Full Text Available The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.

  20. 75 FR 30046 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-June 14, 2010

    Science.gov (United States)

    2010-05-28

    ..., Employee Benefits Security Administration, DOL at (202) 693-8335. News media representatives must contact... eligible for benefits under titles XIX or XXI of the Social Security Act (the Act) to enable them to enroll...] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP...

  1. 'Micro-8' micro-computer system

    International Nuclear Information System (INIS)

    Yagi, Hideyuki; Nakahara, Yoshinori; Yamada, Takayuki; Takeuchi, Norio; Koyama, Kinji

    1978-08-01

    The micro-computer Micro-8 system has been developed to organize a data exchange network between various instruments and a computer group including a large computer system. Used for packet exchangers and terminal controllers, the system consists of ten kinds of standard boards including a CPU board with INTEL-8080 one-chip-processor. CPU architecture, BUS architecture, interrupt control, and standard-boards function are explained in circuit block diagrams. Operations of the basic I/O device, digital I/O board and communication adapter are described with definitions of the interrupt ramp status, I/O command, I/O mask, data register, etc. In the appendixes are circuit drawings, INTEL-8080 micro-processor specifications, BUS connections, I/O address mappings, jumper connections of address selection, and interface connections. (author)

  2. Instrument for measuring moisture in wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Werme, L

    1980-06-01

    A method to determine the moisture content in wood chips, in batch and on-line, has been investigated. The method can be used for frozen and non frozen chips. Samples of wood chips are thawn and dryed with microwaves. During the drying the sample is weighed continously and the rate of drying is measured. The sample is dried t 10 percent moisture content. The result is extrapolated to the drying rate zero. The acccuracy at the method is 1.6 to 1.7 percent for both frozen and non frozen chips. The accuracy of the method is considered acceptable, but sofisticated sampling equipment is necessary. This makes the method too complex to make the instrument marketable.

  3. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  4. Characterizing Rat PNS Electrophysiological Response to Electrical Stimulation Using in vitro Chip-Based Human Investigational Platform (iCHIP)

    Energy Technology Data Exchange (ETDEWEB)

    Khani, Joshua [Georgetown Univ., Washington, DC (United States); Prescod, Lindsay [Georgetown Univ., Washington, DC (United States); Enright, Heather [Georgetown Univ., Washington, DC (United States); Felix, Sarah [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Osburn, Joanne [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Wheeler, Elizabeth [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Kulp, Kris [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2015-08-18

    Ex vivo systems and organ-on-a-chip technology offer an unprecedented approach to modeling the inner workings of the human body. The ultimate goal of LLNL’s in vitro Chip-based Human Investigational Platform (iCHIP) is to integrate multiple organ tissue cultures using microfluidic channels, multi-electrode arrays (MEA), and other biosensors in order to effectively simulate and study the responses and interactions of the major organs to chemical and physical stimulation. In this study, we focused on the peripheral nervous system (PNS) component of the iCHIP system. Specifically we sought to expound on prior research investigating the electrophysiological response of rat dorsal root ganglion cells (rDRGs) to chemical exposures, such as capsaicin. Our aim was to establish a protocol for electrical stimulation using the iCHIP device that would reliably elicit a characteristic response in rDRGs. By varying the parameters for both the stimulation properties – amplitude, phase width, phase shape, and stimulation/ return configuration – and the culture conditions – day in vitro and neural cell types - we were able to make several key observations and uncover a potential convention with a minimal number of devices tested. Future work will seek to establish a standard protocol for human DRGs in the iCHIP which will afford a portable, rapid method for determining the effects of toxins and novel therapeutics on the PNS.

  5. Modified precision-husky progrind H-3045 for chipping biomass

    Science.gov (United States)

    Dana Mitchell; Fernando Seixas; John. Klepac

    2008-01-01

    A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

  6. Formation of SiNx:H by PECVD: optimization of the optical, bulk passivation and structural properties for photovoltaic applications

    International Nuclear Information System (INIS)

    Lelievre, J.F.

    2007-04-01

    The hydrogenated silicon nitride SiNx:H is widely used as antireflection coating and passivation layer in the manufacture of silicon photovoltaic cells. The aim of this work was to implement a low frequency (440 kHz) PECVD reactor and to characterize the obtained SiN layers. After having determined the parameters of the optimal deposition, the physico-chemical structure of the layers has been studied. The optical properties have been studied with the aim to improve the antireflection coating of the photovoltaic cells. The surface and bulk passivation properties, induced by the SiN layer in terms of its stoichiometry, have been analyzed and have revealed the excellent passivating efficiency of this material. At last, have been studied the formation conditions of the silicon nano-crystals in the SiN matrix. (O.M.)

  7. GPU accelerated simulations of 3D deterministic particle transport using discrete ordinates method

    International Nuclear Information System (INIS)

    Gong Chunye; Liu Jie; Chi Lihua; Huang Haowei; Fang Jingyue; Gong Zhenghu

    2011-01-01

    Graphics Processing Unit (GPU), originally developed for real-time, high-definition 3D graphics in computer games, now provides great faculty in solving scientific applications. The basis of particle transport simulation is the time-dependent, multi-group, inhomogeneous Boltzmann transport equation. The numerical solution to the Boltzmann equation involves the discrete ordinates (S n ) method and the procedure of source iteration. In this paper, we present a GPU accelerated simulation of one energy group time-independent deterministic discrete ordinates particle transport in 3D Cartesian geometry (Sweep3D). The performance of the GPU simulations are reported with the simulations of vacuum boundary condition. The discussion of the relative advantages and disadvantages of the GPU implementation, the simulation on multi GPUs, the programming effort and code portability are also reported. The results show that the overall performance speedup of one NVIDIA Tesla M2050 GPU ranges from 2.56 compared with one Intel Xeon X5670 chip to 8.14 compared with one Intel Core Q6600 chip for no flux fixup. The simulation with flux fixup on one M2050 is 1.23 times faster than on one X5670.

  8. GPU accelerated simulations of 3D deterministic particle transport using discrete ordinates method

    Science.gov (United States)

    Gong, Chunye; Liu, Jie; Chi, Lihua; Huang, Haowei; Fang, Jingyue; Gong, Zhenghu

    2011-07-01

    Graphics Processing Unit (GPU), originally developed for real-time, high-definition 3D graphics in computer games, now provides great faculty in solving scientific applications. The basis of particle transport simulation is the time-dependent, multi-group, inhomogeneous Boltzmann transport equation. The numerical solution to the Boltzmann equation involves the discrete ordinates ( Sn) method and the procedure of source iteration. In this paper, we present a GPU accelerated simulation of one energy group time-independent deterministic discrete ordinates particle transport in 3D Cartesian geometry (Sweep3D). The performance of the GPU simulations are reported with the simulations of vacuum boundary condition. The discussion of the relative advantages and disadvantages of the GPU implementation, the simulation on multi GPUs, the programming effort and code portability are also reported. The results show that the overall performance speedup of one NVIDIA Tesla M2050 GPU ranges from 2.56 compared with one Intel Xeon X5670 chip to 8.14 compared with one Intel Core Q6600 chip for no flux fixup. The simulation with flux fixup on one M2050 is 1.23 times faster than on one X5670.

  9. Perspective: Fabrication of integrated organ-on-a-chip via bioprinting.

    Science.gov (United States)

    Yang, Qingzhen; Lian, Qin; Xu, Feng

    2017-05-01

    Organ-on-a-chip has emerged as a powerful platform with widespread applications in biomedical engineering, such as pathology studies and drug screening. However, the fabrication of organ-on-a-chip is still a challenging task due to its complexity. For an integrated organ-on-a-chip, it may contain four key elements, i.e., a microfluidic chip, live cells/microtissues that are cultured in this chip, components for stimulus loading to mature the microtissues, and sensors for results readout. Recently, bioprinting has been used for fabricating organ-on-a-chip as it enables the printing of multiple materials, including biocompatible materials and even live cells in a programmable manner with a high spatial resolution. Besides, all four elements for organ-on-a-chip could be printed in a single continuous procedure on one printer; in other words, the fabrication process is assembly free. In this paper, we discuss the recent advances of organ-on-a-chip fabrication by bioprinting. Light is shed on the printing strategies, materials, and biocompatibility. In addition, some specific bioprinted organs-on-chips are analyzed in detail. Because the bioprinted organ-on-a-chip is still in its early stage, significant efforts are still needed. Thus, the challenges presented together with possible solutions and future trends are also discussed.

  10. Experiment list: SRX319558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available | cell type=mouse embryonic stem cells || genotype/variation=expressing control BirA || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  11. Experiment list: SRX319557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Nanog || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  12. Parallel computation for biological sequence comparison: comparing a portable model to the native model for the Intel Hypercube.

    Science.gov (United States)

    Nadkarni, P M; Miller, P L

    1991-01-01

    A parallel program for inter-database sequence comparison was developed on the Intel Hypercube using two models of parallel programming. One version was built using machine-specific Hypercube parallel programming commands. The other version was built using Linda, a machine-independent parallel programming language. The two versions of the program provide a case study comparing these two approaches to parallelization in an important biological application area. Benchmark tests with both programs gave comparable results with a small number of processors. As the number of processors was increased, the Linda version was somewhat less efficient. The Linda version was also run without change on Network Linda, a virtual parallel machine running on a network of desktop workstations.

  13. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally...

  14. Experiment list: SRX319556 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  15. Experiment list: SRX319553 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Tip60 || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  16. Experiment list: SRX319555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  17. Experiment list: SRX319551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available use embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dmap1 || chip beads=Dynabeads MyOn...e Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.

  18. Space division multiplexing chip-to-chip quantum key distribution

    DEFF Research Database (Denmark)

    Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum...

  19. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H; Seppaenen, V

    1997-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  20. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H.; Seppaenen, V.

    1996-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  1. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    Directory of Open Access Journals (Sweden)

    Xin Wang

    2007-01-01

    Full Text Available Two network-on-chip (NoC designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

  2. Experiment list: SRX319550 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e embryonic stem cells || genotype/variation=expressing Flag-bio tagged Myc || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  3. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  4. Experiment list: SRX180159 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available sd || cell type=hemogenic endothelium || chip antibody=CEBPb || chip antibody vendor=santa cruz biotechnol...ogy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachData/bw/SRX180159.bw http://

  5. Experiment list: SRX112178 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=8WG16 (MMS-126R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm

  6. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2016-01-01

    On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range.......On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range....

  7. Experiment list: SRX185907 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Homo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-...7 || cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_

  8. Experiment list: SRX319552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available embryonic stem cells || genotype/variation=expressing Flag-bio tagged E2F4 || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  9. Experiment list: SRX112184 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Sepharose beads http://dbarchive.biosciencedbc.jp/kyushu-u/m

  10. Experiment list: SRX367328 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siCTL http://dbarchive.bio...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  11. Experiment list: SRX543048 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea...CID.adh murine thymic lymphoma || development stage=DN3 || chip antibody=rabbit anti-Miz-1 || chip antibody vendor=Santa Cruz Biotech

  12. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  13. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  14. Structural, mechanical, electrical and wetting properties of ZrNx films deposited by Ar/N2 vacuum arc discharge: Effect of nitrogen partial pressure

    Science.gov (United States)

    Abdallah, B.; Naddaf, M.; A-Kharroub, M.

    2013-03-01

    Non-stiochiometric zirconium nitride (ZrNx) thin films have been deposited on silicon substrates by vacuum arc discharge of (N2 + Ar) gas mixtures at different N2 partial pressure ratio. The microstructure, mechanical, electrical and wetting properties of these films are studied by means of X-ray diffraction (XRD), micro-Raman spectroscopy, Rutherford back scattering (RBS) technique, conventional micro-hardness testing, electrical resistivity, atomic force microscopy (AFM) and contact angle (CA) measurements. RBS results and analysis show that the (N/Zr) ratio in the film increases with increasing the N2 partial pressure. A ZrNx film with (Zr/N) ratio in the vicinity of stoichiometric ZrN is obtained at N2 partial pressure of 10%. XRD and Raman results indicate that all deposited films have strained cubic crystal phase of ZrN, regardless of the N2 partial pressure. On increasing the N2 partial pressure, the relative intensity of (1 1 1) orientation with respect to (2 0 0) orientation is seen to decrease. The effect of N2 partial pressure on micro-hardness and the resistivity of the deposited film is revealed and correlated to the alteration of grain size, crystallographic texture, stoichiometry and residual stress developed in the film. In particular, it is found that residual stress and nitrogen incorporation in the film play crucial role in the alteration of micro-hardness and resistivity respectively. In addition, CA and AFM results demonstrate that as N2 partial pressure increases, both the surface hydrophobicity and roughness of the deposited film increase, leading to a significant decrease in the film surface free energy (SFE).

  15. Experiment list: SRX185915 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available mo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 |...| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_tar

  16. Experiment list: SRX185909 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  17. Experiment list: SRX185917 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  18. Experiment list: SRX112179 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =OS25 ES cells || chip antibody=H5 (MMS-129R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads=Magnetic bea...ds http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  19. Experiment list: SRX367330 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siBrd4 http://dbarchive.bi...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  20. Wood chips procurement and research project at the Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1996-01-01

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m 3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m 3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m 3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m 3 /ha

  1. A primary battery-on-a-chip using monolayer graphene

    Science.gov (United States)

    Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

    2016-07-01

    We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

  2. Results from a MA16-based neural trigger in an experiment looking for beauty

    International Nuclear Information System (INIS)

    Baldanza, C.; Beichter, J.; Bisi, F.; Bruels, N.; Bruschini, C.; Cotta-Ramusino, A.; D'Antone, I.; Malferrari, L.; Mazzanti, P.; Musico, P.; Novelli, P.; Odorici, F.; Odorico, R.; Passaseo, M.; Zuffa, M.

    1996-01-01

    Results from a neural-network trigger based on the digital MA16 chip of Siemens are reported. The neural trigger has been applied to data from the WA92 experiment, looking for beauty particles, which have been collected during a run in which a neural trigger module based on Intel's analog neural chip ETANN operated, as already reported. The MA16 board hosting the chip has a 16-bit I/O precision and a 53-bit precision for internal calculations. It operated at 50 MHz, yielding a response time for a 16 input-variable net of 3 μs for a Fisher discriminant (1-layer net) and of 6 μs for a 2-layer net. Results are compared with those previously obtained with the ETANN trigger. (orig.)

  3. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  4. Microfluidic Organ-on-a-Chip Models of Human IntestineSummary

    Directory of Open Access Journals (Sweden)

    Amir Bein

    Full Text Available Microfluidic organ-on-a-chip models of human intestine have been developed and used to study intestinal physiology and pathophysiology. In this article, we review this field and describe how microfluidic Intestine Chips offer new capabilities not possible with conventional culture systems or organoid cultures, including the ability to analyze contributions of individual cellular, chemical, and physical control parameters one-at-a-time; to coculture human intestinal cells with commensal microbiome for extended times; and to create human-relevant disease models. We also discuss potential future applications of human Intestine Chips, including how they might be used for drug development and personalized medicine. Keywords: Organs-on-Chips, Gut-on-a-Chip, Intestine-on-a-Chip, Microfluidic

  5. Experiment list: SRX112176 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  6. Chipping operations and efficiency in different operational environments

    Energy Technology Data Exchange (ETDEWEB)

    Roeser, D.; Mola-Yudego, B.; Prinz, R.; Emer, B.; Sikanen, L., e-mail: dominik.roser@metla.fi

    2012-11-01

    This research analyses the productivity of energy wood chipping operations at several sites in Austria and Finland. The aim of the work is to examine the differences in productivity and the effects of the operational environment for the chipping of bioenergy at the roadside. Furthermore, the study quantifies the effects of different variables such as forest energy assortments, tree species, sieve size and machines on the overall productivity of chipping. The results revealed that there are significant differences in the chipping productivity in Austria and Finland which are largely based on the use of different sieve sizes. Furthermore, the different operational environments in both countries, as well as the characteristics of the raw material also seem to have an effect on productivity. In order to improve the chipping productivity, particularly in Central European conditions, all relevant stakeholders need to work jointly to find solutions that will allow a greater variation of chip size. Furthermore, in the future more consideration has to be given to the close interlinkage between the chipper, crane and grapple. As a result, investments costs can be optimized and operational costs and stress on the machines reduced. (orig.)

  7. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  8. Influence of a-Si:H deposition power on surface passivation property and thermal stability of a-Si:H/SiNx:H stacks

    Directory of Open Access Journals (Sweden)

    Hua Li

    2012-06-01

    Full Text Available The effectiveness of hydrogenated amorphous silicon (a-Si:H layers for passivating crystalline silicon surfaces has been well documented in the literature for well over a decade. One limitation of such layers however has arisen from their inability to withstand temperatures much above their deposition temperature without significant degradation. This limitation is of importance particularly with multicrystalline silicon materials where temperatures of at least 400°C are needed for effective hydrogenation of the crystallographic defects such as grain boundaries. To address this limitation, in this work the surface passivation quality and thermal stability of a stack passivating system, combining a layer of intrinsic a-Si:H and a capping layer of silicon nitride (SiNx:H, on p-type crystalline silicon wafers is studied and optimized. In particular the sensitivity of different microwave (MW power levels for underlying a-Si:H layer deposition are examined. Both effective minority carrier lifetime (ζeff measurement and Fourier transform infrared (FTIR spectrometry were employed to study the bonding configurations, passivating quality and thermal stability of the a-Si:H/SiNx:H stacks. It is established that the higher MW power could result in increased as-deposited ζeff and implied Voc (iVoc values, indicating likely improved surface passivation quality, but that this combination degrades more quickly when exposed to prolonged thermal treatments. The more dihydride-rich film composition corresponding to the higher MW power appears to be beneficial for bond restructuring by hydrogen interchanges when exposed to short term annealing, however it also appears more susceptible to providing channels for hydrogen out-effusion which is the likely cause of the poorer thermal stability for prolonged high temperature exposure compared with stacks with underlying a-Si:H deposited with lower MW power.

  9. Analysis of the prognostic factors for low rectal cancer with the pT1-2NxM0 stage after abdominoperineal resection.

    Science.gov (United States)

    Zhang, Xing-mao; Ma, Chao; Sun, Da-yong; Wang, Zheng; Zhou, Zhi-xiang

    2015-01-01

    This study was designed to explore the factors influencing local recurrence and survival for low rectal cancer with pT1-2NxM0 stage after an abdominoperineal resection (APR). Data of 429 patients confirmed to have pT1-2NxM0 after APR were reviewed. The recurrence rate in patients with intraoperative perforation, less than 12 lymph nodes (LNs) harvested, T2 staging, and positive circumferential resection margin (CRM) was 25.1, 19.9, 9.5, and 26.1% compared with 6.9, 7.0, 0, and 5.8% in patients with no perforation, 12 or more LNs harvested, T1, and negative CRM. The 5-year survival rate in patients with age of at least 70, perforation, less than 12 LNs harvested, T2, and positive CRM was 71.1, 60.8, 58.8, 69.9, and 46.0%, but 73.4, 73.5, 73.8, 89.4, and 75.0% in patients with age less than 70, no perforation, 12 or more LNs harvested, T1, and negative CRM. Meanwhile, patients with N0, N1, and N2 had a survival rate of 90.7, 69.9, and 63.9%. Multivariate analysis showed that perforation (PCRM status (P=0.002) were associated with local recurrence, whereas age of the patients (P=0.023), N staging (PCRM status (P=0.004) were associated with survival. APR was affected by patients' age, operation performer, perforation, number of LNs harvested, T staging, N staging, differentiation, and CRM status. Perforation, number of LNs harvested, T staging, differentiation, and CRM status were independent factors for recurrence; meanwhile, age of the patients, N staging, differentiation, and CRM status were independent factors influencing survival.

  10. Opto-electronic DNA chip-based integrated card for clinical diagnostics.

    Science.gov (United States)

    Marchand, Gilles; Broyer, Patrick; Lanet, Véronique; Delattre, Cyril; Foucault, Frédéric; Menou, Lionel; Calvas, Bernard; Roller, Denis; Ginot, Frédéric; Campagnolo, Raymond; Mallard, Frédéric

    2008-02-01

    Clinical diagnostics is one of the most promising applications for microfluidic lab-on-a-chip or lab-on-card systems. DNA chips, which provide multiparametric data, are privileged tools for genomic analysis. However, automation of molecular biology protocol and use of these DNA chips in fully integrated systems remains a great challenge. Simplicity of chip and/or card/instrument interfaces is amongst the most critical issues to be addressed. Indeed, current detection systems for DNA chip reading are often complex, expensive, bulky and even limited in terms of sensitivity or accuracy. Furthermore, for liquid handling in the lab-on-cards, many devices use complex and bulky systems, either to directly manipulate fluids, or to ensure pneumatic or mechanical control of integrated valves. All these drawbacks prevent or limit the use of DNA-chip-based integrated systems, for point-of-care testing or as a routine diagnostics tool. We present here a DNA-chip-based protocol integration on a plastic card for clinical diagnostics applications including: (1) an opto-electronic DNA-chip, (2) fluid handling using electrically activated embedded pyrotechnic microvalves with closing/opening functions. We demonstrate both fluidic and electric packaging of the optoelectronic DNA chip without major alteration of its electronical and biological functionalities, and fluid control using novel electrically activable pyrotechnic microvalves. Finally, we suggest a complete design of a card dedicated to automation of a complex biological protocol with a fully electrical fluid handling and DNA chip reading.

  11. Integrated lasers for polymer Lab-on-a-Chip systems

    DEFF Research Database (Denmark)

    Mappes, Timo; Vannahme, Christoph; Grosmann, Tobias

    2012-01-01

    We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers.......We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers....

  12. Biostability of an implantable glucose sensor chip

    Science.gov (United States)

    Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

    2012-12-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  13. Biostability of an implantable glucose sensor chip

    International Nuclear Information System (INIS)

    Fröhlich, M; Ehwald, K E; Kulse, P; Fursenko, O; Katzer, J; Birkholz, M

    2012-01-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO 2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and R a roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  14. Experiment list: SRX262781 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available _name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biotec...hnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  15. Experiment list: SRX262786 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_MRTFA_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  16. Experiment list: SRX262791 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFB_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-B || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  17. Experiment list: SRX262782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available echnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9...ce_name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biot

  18. Experiment list: SRX262788 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_UO || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechn...ology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eac

  19. Experiment list: SRX262787 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  20. Experiment list: SRX262780 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/...e_name=NIH3T3_SRF_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biote

  1. 3D Printing of Organs-On-Chips.

    Science.gov (United States)

    Yi, Hee-Gyeong; Lee, Hyungseok; Cho, Dong-Woo

    2017-01-25

    Organ-on-a-chip engineering aims to create artificial living organs that mimic the complex and physiological responses of real organs, in order to test drugs by precisely manipulating the cells and their microenvironments. To achieve this, the artificial organs should to be microfabricated with an extracellular matrix (ECM) and various types of cells, and should recapitulate morphogenesis, cell differentiation, and functions according to the native organ. A promising strategy is 3D printing, which precisely controls the spatial distribution and layer-by-layer assembly of cells, ECMs, and other biomaterials. Owing to this unique advantage, integration of 3D printing into organ-on-a-chip engineering can facilitate the creation of micro-organs with heterogeneity, a desired 3D cellular arrangement, tissue-specific functions, or even cyclic movement within a microfluidic device. Moreover, fully 3D-printed organs-on-chips more easily incorporate other mechanical and electrical components with the chips, and can be commercialized via automated massive production. Herein, we discuss the recent advances and the potential of 3D cell-printing technology in engineering organs-on-chips, and provides the future perspectives of this technology to establish the highly reliable and useful drug-screening platforms.

  2. Chip-based microtrap arrays for cold polar molecules

    Science.gov (United States)

    Hou, Shunyong; Wei, Bin; Deng, Lianzhong; Yin, Jianping

    2017-12-01

    Compared to the atomic chip, which has been a powerful platform to perform an astonishing range of applications from rapid Bose-Einstein condensate (BEC) production to the atomic clock, the molecular chip is only in its infant stages. Recently a one-dimensional electric lattice was demonstrated to trap polar molecules on a chip. This excellent work opens up the way to building a molecular chip laboratory. Here we propose a two-dimensional (2D) electric lattice on a chip with concise and robust structure, which is formed by arrays of squared gold wires. Arrays of microtraps that originate in the microsize electrodes offer a steep gradient and thus allow for confining both light and heavy polar molecules. Theoretical analysis and numerical calculations are performed using two types of sample molecules, N D3 and SrF, to justify the possibility of our proposal. The height of the minima of the potential wells is about 10 μm above the surface of the chip and can be easily adjusted in a wide range by changing the voltages applied on the electrodes. These microtraps offer intriguing perspectives for investigating cold molecules in periodic potentials, such as quantum computing science, low-dimensional physics, and some other possible applications amenable to magnetic or optical lattice. The 2D adjustable electric lattice is expected to act as a building block for a future gas-phase molecular chip laboratory.

  3. An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Rauwerda, G.K.; Smit, L.T.

    Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as

  4. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  5. Reagent-loaded plastic microfluidic chips for detecting homocysteine

    International Nuclear Information System (INIS)

    Suk, Ji Won; Jang, Jae-Young; Cho, Jun-Hyeong

    2008-01-01

    This report describes the preliminary study on plastic microfluidic chips with pre-loaded reagents for detecting homocysteine (Hcy). All reagents needed in an Hcy immunoassay were included in a microfluidic chip to remove tedious assay steps. A simple and cost-effective bonding method was developed to realize reagent-loaded microfluidic chips. This technique uses an intermediate layer between two plastic substrates by selectively patterning polydimethylsiloxane (PDMS) on the embossed surface of microchannels and fixing the substrates under pressure. Using this bonding method, the competitive immunoassay for SAH, a converted form of Hcy, was performed without any damage to reagents in chips, and the results showed that the fluorescent signal from antibody antigen binding decreased as the SAH concentration increased. Based on the SAH immunoassay, whole immunoassay steps for Hcy detection were carried out in plastic microfluidic chips with all necessary reagents. These experiments demonstrated the feasibility of the Hcy immunoassay in microfluidic devices

  6. Experiment list: SRX262797 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3T3_SAP1_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechnolo...gy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  7. Experiment list: SRX262799 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_SAP1_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  8. Experiment list: SRX352046 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available SM1232564: CSB M CHIP; Homo sapiens; ChIP-Seq source_name=fibroblast_menadione_CSB-ChIP || cell type=fibroblast || treated with=menad...ione || chip antibody=Mouse monoclonal anti-CSB N Terminus (1B1) http://dbarchive.b

  9. Microneedle Array Interface to CE on Chip

    NARCIS (Netherlands)

    Lüttge, Regina; Gardeniers, Johannes G.E.; Vrouwe, E.X.; van den Berg, Albert; Northrup, M.A.; Jensen, K.F; Harrison, D.J.

    2003-01-01

    This paper presents a microneedle array sampler interfaced to a capillary electrophoresis (CE) glass chip with integrated conductivity detection electrodes. A solution of alkali ions was electrokinetically loaded through the microneedles onto the chip and separation was demonstrated compared to a

  10. Experiment list: SRX144526 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available stein-Barr Virus transformed 11803840,92.5,91.6,38 GSM922971: NRF2 ChIP vehicle treated rep2; Homo sapiens; ...ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_provider=Coriell; h

  11. Experiment list: SRX151245 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 0: CTCF ChIPSeq; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, CTCF ChIP || cell line=...BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=rabbit anti-CTCF || antibo

  12. OpenMP-accelerated SWAT simulation using Intel C and FORTRAN compilers: Development and benchmark

    Science.gov (United States)

    Ki, Seo Jin; Sugimura, Tak; Kim, Albert S.

    2015-02-01

    We developed a practical method to accelerate execution of Soil and Water Assessment Tool (SWAT) using open (free) computational resources. The SWAT source code (rev 622) was recompiled using a non-commercial Intel FORTRAN compiler in Ubuntu 12.04 LTS Linux platform, and newly named iOMP-SWAT in this study. GNU utilities of make, gprof, and diff were used to develop the iOMP-SWAT package, profile memory usage, and check identicalness of parallel and serial simulations. Among 302 SWAT subroutines, the slowest routines were identified using GNU gprof, and later modified using Open Multiple Processing (OpenMP) library in an 8-core shared memory system. In addition, a C wrapping function was used to rapidly set large arrays to zero by cross compiling with the original SWAT FORTRAN package. A universal speedup ratio of 2.3 was achieved using input data sets of a large number of hydrological response units. As we specifically focus on acceleration of a single SWAT run, the use of iOMP-SWAT for parameter calibrations will significantly improve the performance of SWAT optimization.

  13. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  14. Experiment list: SRX150568 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59265240,72.4,16.4,4779 GSM935489: Harvard ChipSeq HeLa-S3 RPC155 std source_name=HeLa-S3 ...|| biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipS

  15. Experiment list: SRX150661 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59396606,71.7,11.1,1200 GSM935582: Harvard ChipSeq HeLa-S3 BRF1 std source_name=HeLa-S3 ||... biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  16. Experiment list: SRX150495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 62508352,67.6,8.4,1556 GSM935416: Harvard ChipSeq HeLa-S3 ZZZ3 std source_name=HeLa-S3 || ...biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  17. Experiment list: SRX150565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Adenocarcinoma 54953593,74.3,12.2,1703 GSM935486: Harvard ChipSeq HeLa-S3 BDP1 std source_name=HeLa-S3 || b...iomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq |

  18. Performance evaluation of chip seals in Idaho.

    Science.gov (United States)

    2010-08-01

    The intent of this research project is to identify a wide variety of parameters that influence the performance of pavements treated via chip seals within the State of Idaho. Chip sealing is currently one of the most popular methods of maintenance for...

  19. Experiment list: SRX507380 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=anti-HP1 || chip antibody vend...1770: WT anti-HP1- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_anti-HP1 || strain=piwi/

  20. Experiment list: SRX176054 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nosis=Carcinoma 13338805,91.2,4.9,792 GSM984386: LNCAP AR vehicle; Homo sapiens; ChIP-Seq source_name=prosta...te cancer cells || cell line=LNCaP || chip antibody=AR || chip antibody manufacturer=Abcam || treatment=EtOH vehicle

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