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  1. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  2. Newsgroups, Activist Publics, and Corporate Apologia: The Case of Intel and Its Pentium Chip.

    Science.gov (United States)

    Hearit, Keith Michael

    1999-01-01

    Applies J. Grunig's theory of publics to the phenomenon of Internet newsgroups using the case of the flawed Intel Pentium chip. Argues that technology facilitates the rapid movement of publics from the theoretical construct stage to the active stage. Illustrates some of the difficulties companies face in establishing their identity in cyberspace.…

  3. Intel Galileo essentials

    CERN Document Server

    Grimmett, Richard

    2015-01-01

    This book is for anyone who has ever been curious about using the Intel Galileo to create electronics projects. Some programming background is useful, but if you know how to use a personal computer, with the aid of the step-by-step instructions in this book, you can construct complex electronics projects that use the Intel Galileo.

  4. Home automation with Intel Galileo

    CERN Document Server

    Dundar, Onur

    2015-01-01

    This book is for anyone who wants to learn Intel Galileo for home automation and cross-platform software development. No knowledge of programming with Intel Galileo is assumed, but knowledge of the C programming language is essential.

  5. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  6. Intel: High Throughput Computing Collaboration: A CERN openlab / Intel collaboration

    CERN Multimedia

    CERN. Geneva

    2015-01-01

    The Intel/CERN High Throughput Computing Collaboration studies the application of upcoming Intel technologies to the very challenging environment of the LHC trigger and data-acquisition systems. These systems will need to transport and process many terabits of data every second, in some cases with tight latency constraints. Parallelisation and tight integration of accelerators and classical CPU via Intel's OmniPath fabric are the key elements in this project.

  7. Windows for Intel Macs

    CERN Document Server

    Ogasawara, Todd

    2008-01-01

    Even the most devoted Mac OS X user may need to use Windows XP, or may just be curious about XP and its applications. This Short Cut is a concise guide for OS X users who need to quickly get comfortable and become productive with Windows XP basics on their Macs. It covers: Security Networking ApplicationsMac users can easily install and use Windows thanks to Boot Camp and Parallels Desktop for Mac. Boot Camp lets an Intel-based Mac install and boot Windows XP on its own hard drive partition. Parallels Desktop for Mac uses virtualization technology to run Windows XP (or other operating systems

  8. [Intel random number generator-based true random number generator].

    Science.gov (United States)

    Huang, Feng; Shen, Hong

    2004-09-01

    To establish a true random number generator on the basis of certain Intel chips. The random numbers were acquired by programming using Microsoft Visual C++ 6.0 via register reading from the random number generator (RNG) unit of an Intel 815 chipset-based computer with Intel Security Driver (ISD). We tested the generator with 500 random numbers in NIST FIPS 140-1 and X(2) R-Squared test, and the result showed that the random number it generated satisfied the demand of independence and uniform distribution. We also compared the random numbers generated by Intel RNG-based true random number generator and those from the random number table statistically, by using the same amount of 7500 random numbers in the same value domain, which showed that the SD, SE and CV of Intel RNG-based random number generator were less than those of the random number table. The result of u test of two CVs revealed no significant difference between the two methods. Intel RNG-based random number generator can produce high-quality random numbers with good independence and uniform distribution, and solves some problems with random number table in acquisition of the random numbers.

  9. INTEL: Intel based systems move up in supercomputing ranks

    CERN Multimedia

    2002-01-01

    "The TOP500 supercomputer rankings released today at the Supercomputing 2002 conference show a dramatic increase in the number of Intel-based systems being deployed in high-performance computing (HPC) or supercomputing areas" (1/2 page).

  10. Accessing Intel FPGAs for Acceleration

    CERN Multimedia

    CERN. Geneva

    2018-01-01

    In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on the Intel Programmable Acceleration Card in a Data Center. We will then talk about the OpenCL flow which allows parallel software developers to create FPGA systems and deploy them using the OpenCL standard. Next, we will talk about the Intel High-Level Synthesis compiler which can convert C++ code into custom RTL code optimized for Intel FPGAs. Lastly, we will focus on the task of running Machine Learning inference on the FPGA leveraging some of the tools we discussed. About the speaker Karl Qi is Sr. Staff Applications Engineer, Technical Training. He has been with the Customer Training department at Altera/Intel for 8 years. Most recently, he is responsible for all training content relating to High-Level Design tools, including the OpenCL...

  11. Intel Xeon Phi coprocessor high performance programming

    CERN Document Server

    Jeffers, James

    2013-01-01

    Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products. This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture. It off...

  12. New compilers speed up applications for Intel-based systems; Intel Compilers pave the way for Intel's Hyper-threading technology

    CERN Multimedia

    2002-01-01

    "Intel Corporation today introduced updated tools to help software developers optimize applications for Intel's expanding family of architectures with key innovations such as Intel's Hyper Threading Technology (1 page).

  13. Scientific Computing and Apple's Intel Transition

    CERN Document Server

    CERN. Geneva

    2006-01-01

    Intel's published processor roadmap and how it may affect the future of personal and scientific computing About the speaker: Eric Albert is Senior Software Engineer in Apple's Core Technologies group. During Mac OS X's transition to Intel processors he has worked on almost every part of the operating system, from the OS kernel and compiler tools to appli...

  14. Unlock performance secrets of next-gen Intel hardware

    CERN Multimedia

    CERN. Geneva

    2015-01-01

    Intel® Xeon Phi Product. About the speaker Zakhar is a software architect in Intel SSG group. His current role is Parallel Studio architect with focus on SIMD vector parallelism assistance tools. Before it he was working as Intel Advisor XE software architect and software development team-lead. Before joining Intel he was...

  15. Intel Corporation osaleb Eesti koolitusprogrammis / Raivo Juurak

    Index Scriptorium Estoniae

    Juurak, Raivo, 1949-

    2001-01-01

    Haridusministeeriumis tutvustati infotehnoloogiaalast koolitusprogrammi, milles osaleb maailma suuremaid arvutifirmasid Intel Corporation. Koolituskursuse käigus õpetatakse aineõpetajaid oma ainetundides interneti võimalusi kasutama. 50-tunnised kursused viiakse läbi kõigis maakondades

  16. Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

    International Nuclear Information System (INIS)

    Gozzo, F.; Cossy-Favre, A.; Padmore, H.

    1997-01-01

    Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by the Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here

  17. Effective SIMD Vectorization for Intel Xeon Phi Coprocessors

    OpenAIRE

    Tian, Xinmin; Saito, Hideki; Preis, Serguei V.; Garcia, Eric N.; Kozhukhov, Sergey S.; Masten, Matt; Cherkasov, Aleksei G.; Panchenko, Nikolay

    2015-01-01

    Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the Intel C/C++ and Fortran production compilers for Intel Xeon Phi coprocessors. A ...

  18. Investigating the Use of the Intel Xeon Phi for Event Reconstruction

    Science.gov (United States)

    Sherman, Keegan; Gilfoyle, Gerard

    2014-09-01

    The physics goal of Jefferson Lab is to understand how quarks and gluons form nuclei and it is being upgraded to a higher, 12-GeV beam energy. The new CLAS12 detector in Hall B will collect 5-10 terabytes of data per day and will require considerable computing resources. We are investigating tools, such as the Intel Xeon Phi, to speed up the event reconstruction. The Kalman Filter is one of the methods being studied. It is a linear algebra algorithm that estimates the state of a system by combining existing data and predictions of those measurements. The tools required to apply this technique (i.e. matrix multiplication, matrix inversion) are being written using C++ intrinsics for Intel's Xeon Phi Coprocessor, which uses the Many Integrated Cores (MIC) architecture. The Intel MIC is a new high-performance chip that connects to a host machine through the PCIe bus and is built to run highly vectorized and parallelized code making it a well-suited device for applications such as the Kalman Filter. Our tests of the MIC optimized algorithms needed for the filter show significant increases in speed. For example, matrix multiplication of 5x5 matrices on the MIC was able to run up to 69 times faster than the host core. The physics goal of Jefferson Lab is to understand how quarks and gluons form nuclei and it is being upgraded to a higher, 12-GeV beam energy. The new CLAS12 detector in Hall B will collect 5-10 terabytes of data per day and will require considerable computing resources. We are investigating tools, such as the Intel Xeon Phi, to speed up the event reconstruction. The Kalman Filter is one of the methods being studied. It is a linear algebra algorithm that estimates the state of a system by combining existing data and predictions of those measurements. The tools required to apply this technique (i.e. matrix multiplication, matrix inversion) are being written using C++ intrinsics for Intel's Xeon Phi Coprocessor, which uses the Many Integrated Cores (MIC

  19. CERN welcomes Intel Science Fair winners

    CERN Multimedia

    Katarina Anthony

    2012-01-01

    This June, CERN welcomed twelve gifted young scientists aged 15-18 for a week-long visit of the Laboratory. These talented students were the winners of a special award co-funded by CERN and Intel, given yearly at the Intel International Science and Engineering Fair (ISEF).   The CERN award winners at the Intel ISEF 2012 Special Awards Ceremony. © Society for Science & the Public (SSP). The CERN award was set up back in 2009 as an opportunity to bring some of the best and brightest young minds to the Laboratory. The award winners are selected from among 1,500 talented students participating in ISEF – the world's largest pre-university science competition, in which students compete for more than €3 million in awards. “CERN gave an award – which was obviously this trip – to students studying physics, maths, electrical engineering and computer science,” says Benjamin Craig Bartlett, 17, from South Carolina, USA, wh...

  20. The development of the time-keeping clock with TS-1 single chip microcomputer.

    Science.gov (United States)

    Zhou, Jiguang; Li, Yongan

    The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

  1. Experience with Intel's Many Integrated Core Architecture in ATLAS Software

    CERN Document Server

    Fleischmann, S; The ATLAS collaboration; Lavrijsen, W; Neumann, M; Vitillo, R

    2014-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks. This should make it possible to develop for both throughput and latency devices using a single code base.\

  2. Experience with Intel's Many Integrated Core Architecture in ATLAS Software

    CERN Document Server

    Fleischmann, S; The ATLAS collaboration; Lavrijsen, W; Neumann, M; Vitillo, R

    2013-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks. This should make it possible to develop for both throughput and latency devices using a single code base.\

  3. Parallel Programming with Intel Parallel Studio XE

    CERN Document Server

    Blair-Chappell , Stephen

    2012-01-01

    Optimize code for multi-core processors with Intel's Parallel Studio Parallel programming is rapidly becoming a "must-know" skill for developers. Yet, where to start? This teach-yourself tutorial is an ideal starting point for developers who already know Windows C and C++ and are eager to add parallelism to their code. With a focus on applying tools, techniques, and language extensions to implement parallelism, this essential resource teaches you how to write programs for multicore and leverage the power of multicore in your programs. Sharing hands-on case studies and real-world examples, the

  4. Trusted Computing Technologies, Intel Trusted Execution Technology.

    Energy Technology Data Exchange (ETDEWEB)

    Guise, Max Joseph; Wendt, Jeremy Daniel

    2011-01-01

    We describe the current state-of-the-art in Trusted Computing Technologies - focusing mainly on Intel's Trusted Execution Technology (TXT). This document is based on existing documentation and tests of two existing TXT-based systems: Intel's Trusted Boot and Invisible Things Lab's Qubes OS. We describe what features are lacking in current implementations, describe what a mature system could provide, and present a list of developments to watch. Critical systems perform operation-critical computations on high importance data. In such systems, the inputs, computation steps, and outputs may be highly sensitive. Sensitive components must be protected from both unauthorized release, and unauthorized alteration: Unauthorized users should not access the sensitive input and sensitive output data, nor be able to alter them; the computation contains intermediate data with the same requirements, and executes algorithms that the unauthorized should not be able to know or alter. Due to various system requirements, such critical systems are frequently built from commercial hardware, employ commercial software, and require network access. These hardware, software, and network system components increase the risk that sensitive input data, computation, and output data may be compromised.

  5. Radiation Failures in Intel 14nm Microprocessors

    Science.gov (United States)

    Bossev, Dobrin P.; Duncan, Adam R.; Gadlage, Matthew J.; Roach, Austin H.; Kay, Matthew J.; Szabo, Carl; Berger, Tammy J.; York, Darin A.; Williams, Aaron; LaBel, K.; hide

    2016-01-01

    In this study the 14 nm Intel Broadwell 5th generation core series 5005U-i3 and 5200U-i5 was mounted on Dell Inspiron laptops, MSI Cubi and Gigabyte Brix barebones and tested with Windows 8 and CentOS7 at idle. Heavy-ion-induced hard- and catastrophic failures do not appear to be related to the Intel 14nm Tri-Gate FinFET process. They originate from a small (9 m 140 m) area on the 32nm planar PCH die (not the CPU) as initially speculated. The hard failures seem to be due to a SEE but the exact physical mechanism has yet to be identified. Some possibilities include latch-ups, charge ion trapping or implantation, ion channels, or a combination of those (in biased conditions). The mechanism of the catastrophic failures seems related to the presence of electric power (1.05V core voltage). The 1064 nm laser mimics ionization radiation and induces soft- and hard failures as a direct result of electron-hole pair production, not heat. The 14nm FinFET processes continue to look promising for space radiation environments.

  6. An INTEL 8080 microprocessor development system

    International Nuclear Information System (INIS)

    Horne, P.J.

    1977-01-01

    The INTEL 8080 has become one of the two most widely used microprocessors at CERN, the other being the MOTOROLA 6800. Even thouth this is the case, there have been, to date, only rudimentary facilities available for aiding the development of application programs for this microprocessor. An ideal development system is one which has a sophisticated editing and filing system, an assembler/compiler, and access to the microprocessor application. In many instances access to a PROM programmer is also required, as the application may utilize only PROMs for program storage. With these thoughts in mind, an INTEL 8080 microprocessor development system was implemented in the Proton Synchrotron (PS) Division. This system utilizes a PDP 11/45 as the editing and file-handling machine, and an MSC 8/MOD 80 microcomputer for assembling, PROM programming and debugging user programs at run time. The two machines are linked by an existing CAMAC crate system which will also provide the means of access to microprocessor applications in CAMAC and the interface of the development system to any other application. (Auth.)

  7. Lattice QCD with Domain Decomposition on Intel Xeon Phi Co-Processors

    Energy Technology Data Exchange (ETDEWEB)

    Heybrock, Simon; Joo, Balint; Kalamkar, Dhiraj D; Smelyanskiy, Mikhail; Vaidyanathan, Karthikeyan; Wettig, Tilo; Dubey, Pradeep

    2014-12-01

    The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromodynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel Xeon Phi co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

  8. Effective SIMD Vectorization for Intel Xeon Phi Coprocessors

    Directory of Open Access Journals (Sweden)

    Xinmin Tian

    2015-01-01

    Full Text Available Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the Intel C/C++ and Fortran production compilers for Intel Xeon Phi coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel Xeon Phi coprocessor. We also demonstrate a 2000x performance speedup from the seamless integration of SIMD vectorization and parallelization.

  9. Analysis of Intel IA-64 Processor Support for Secure Systems

    National Research Council Canada - National Science Library

    Unalmis, Bugra

    2001-01-01

    .... Systems could be constructed for which serious security threats would be eliminated. This thesis explores the Intel IA-64 processor's hardware support and its relationship to software for building a secure system...

  10. MILC staggered conjugate gradient performance on Intel KNL

    OpenAIRE

    DeTar, Carleton; Doerfler, Douglas; Gottlieb, Steven; Jha, Ashish; Kalamkar, Dhiraj; Li, Ruizi; Toussaint, Doug

    2016-01-01

    We review our work done to optimize the staggered conjugate gradient (CG) algorithm in the MILC code for use with the Intel Knights Landing (KNL) architecture. KNL is the second gener- ation Intel Xeon Phi processor. It is capable of massive thread parallelism, data parallelism, and high on-board memory bandwidth and is being adopted in supercomputing centers for scientific research. The CG solver consumes the majority of time in production running, so we have spent most of our effort on it. ...

  11. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

    2010-01-01

    As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

  12. Comparative VME Performance Tests for MEN A20 Intel-L865 and RIO-3 PPC-LynxOS platforms

    CERN Document Server

    Andersen, M; CERN. Geneva. BE Department

    2009-01-01

    This benchmark note presents test results from reading values over VME using different methods and different sizes of data registers, running on two different platforms Intel-L865 and PPC-LynxOS. We find that the PowerPC is a factor 3 faster in accessing an array of contiguous VME memory locations. Block transfer and DMA read accesses are also tested and compared with conventional single access reads.

  13. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    CERN Document Server

    Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Knight, Robert; Muzaffar, Shahzad

    2014-01-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).

  14. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    Science.gov (United States)

    Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; Eulisse, Giulio; Knight, Robert; Muzaffar, Shahzad

    2015-05-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).

  15. Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

    International Nuclear Information System (INIS)

    Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad; Knight, Robert

    2015-01-01

    Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG). (paper)

  16. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    Science.gov (United States)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

  17. Parallelization of particle transport using Intel® TBB

    International Nuclear Information System (INIS)

    Apostolakis, J; Brun, R; Carminati, F; Gheata, A; Wenzel, S; Belogurov, S; Ovcharenko, E

    2014-01-01

    One of the current challenges in HEP computing is the development of particle propagation algorithms capable of efficiently use all performance aspects of modern computing devices. The Geant-Vector project at CERN has recently introduced an approach in this direction. This paper describes the implementation of a similar workflow using the Intel(r) Threading Building Blocks (Intel(r) TBB) library. This approach is intended to overcome the potential bottleneck of having a single dispatcher on many-core architectures and to result in better scalability compared to the initial pthreads-based version.

  18. Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors

    Directory of Open Access Journals (Sweden)

    Enrico Calore

    2018-06-01

    Full Text Available Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short. We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS technique.

  19. Intel Legend and CERN would build up high speed Internet

    CERN Multimedia

    2002-01-01

    Intel, Legend and China Education and Research Network jointly announced on the 25th of April that they will be cooperating with each other to build up the new generation high speed internet, over the next three years (1/2 page).

  20. Communication overhead on the Intel iPSC-860 hypercube

    Science.gov (United States)

    Bokhari, Shahid H.

    1990-01-01

    Experiments were conducted on the Intel iPSC-860 hypercube in order to evaluate the overhead of interprocessor communication. It is demonstrated that: (1) contrary to popular belief, the distance between two communicating processors has a significant impact on communication time, (2) edge contention can increase communication time by a factor of more than 7, and (3) node contention has no measurable impact.

  1. Connecting Effective Instruction and Technology. Intel-elebration: Safari.

    Science.gov (United States)

    Burton, Larry D.; Prest, Sharon

    Intel-ebration is an attempt to integrate the following research-based instructional frameworks and strategies: (1) dimensions of learning; (2) multiple intelligences; (3) thematic instruction; (4) cooperative learning; (5) project-based learning; and (6) instructional technology. This paper presents a thematic unit on safari, using the…

  2. Using the Intel Math Kernel Library on Peregrine | High-Performance

    Science.gov (United States)

    Computing | NREL the Intel Math Kernel Library on Peregrine Using the Intel Math Kernel Library on Peregrine Learn how to use the Intel Math Kernel Library (MKL) with Peregrine system software. MKL architectures. Core math functions in MKL include BLAS, LAPACK, ScaLAPACK, sparse solvers, fast Fourier

  3. Roofline Analysis in the Intel® Advisor to Deliver Optimized Performance for applications on Intel® Xeon Phi™ Processor

    OpenAIRE

    Koskela, TS; Lobet, M

    2017-01-01

    In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science appl...

  4. Performance Evaluation of Computation and Communication Kernels of the Fast Multipole Method on Intel Manycore Architecture

    KAUST Repository

    AbdulJabbar, Mustafa Abdulmajeed

    2017-07-31

    Manycore optimizations are essential for achieving performance worthy of anticipated exascale systems. Utilization of manycore chips is inevitable to attain the desired floating point performance of these energy-austere systems. In this work, we revisit ExaFMM, the open source Fast Multiple Method (FMM) library, in light of highly tuned shared-memory parallelization and detailed performance analysis on the new highly parallel Intel manycore architecture, Knights Landing (KNL). We assess scalability and performance gain using task-based parallelism of the FMM tree traversal. We also provide an in-depth analysis of the most computationally intensive part of the traversal kernel (i.e., the particle-to-particle (P2P) kernel), by comparing its performance across KNL and Broadwell architectures. We quantify different configurations that exploit the on-chip 512-bit vector units within different task-based threading paradigms. MPI communication-reducing and NUMA-aware approaches for the FMM’s global tree data exchange are examined with different cluster modes of KNL. By applying several algorithm- and architecture-aware optimizations for FMM, we show that the N-Body kernel on 256 threads of KNL achieves on average 2.8× speedup compared to the non-vectorized version, whereas on 56 threads of Broadwell, it achieves on average 2.9× speedup. In addition, the tree traversal kernel on KNL scales monotonically up to 256 threads with task-based programming models. The MPI-based communication-reducing algorithms show expected improvements of the data locality across the KNL on-chip network.

  5. Performance Evaluation of Computation and Communication Kernels of the Fast Multipole Method on Intel Manycore Architecture

    KAUST Repository

    AbdulJabbar, Mustafa Abdulmajeed; Al Farhan, Mohammed; Yokota, Rio; Keyes, David E.

    2017-01-01

    Manycore optimizations are essential for achieving performance worthy of anticipated exascale systems. Utilization of manycore chips is inevitable to attain the desired floating point performance of these energy-austere systems. In this work, we revisit ExaFMM, the open source Fast Multiple Method (FMM) library, in light of highly tuned shared-memory parallelization and detailed performance analysis on the new highly parallel Intel manycore architecture, Knights Landing (KNL). We assess scalability and performance gain using task-based parallelism of the FMM tree traversal. We also provide an in-depth analysis of the most computationally intensive part of the traversal kernel (i.e., the particle-to-particle (P2P) kernel), by comparing its performance across KNL and Broadwell architectures. We quantify different configurations that exploit the on-chip 512-bit vector units within different task-based threading paradigms. MPI communication-reducing and NUMA-aware approaches for the FMM’s global tree data exchange are examined with different cluster modes of KNL. By applying several algorithm- and architecture-aware optimizations for FMM, we show that the N-Body kernel on 256 threads of KNL achieves on average 2.8× speedup compared to the non-vectorized version, whereas on 56 threads of Broadwell, it achieves on average 2.9× speedup. In addition, the tree traversal kernel on KNL scales monotonically up to 256 threads with task-based programming models. The MPI-based communication-reducing algorithms show expected improvements of the data locality across the KNL on-chip network.

  6. MILC staggered conjugate gradient performance on Intel KNL

    Energy Technology Data Exchange (ETDEWEB)

    Li, Ruiz [Indiana Univ., Bloomington, IN (United States). Dept. of Physics; Detar, Carleton [Univ. of Utah, Salt Lake City, UT (United States). Dept. of Physics and Astronomy; Doerfler, Douglas W. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). National Energy Research Scientific Computing Center (NERSC); Gottlieb, Steven [Indiana Univ., Bloomington, IN (United States). Dept. of Physics; Jha, Asish [Intel Corp., Hillsboro, OR (United States). Sofware and Services Group; Kalamkar, Dhiraj [Intel Labs., Bangalore (India). Parallel Computing Lab.; Toussaint, Doug [Univ. of Arizona, Tucson, AZ (United States). Physics Dept.

    2016-11-03

    We review our work done to optimize the staggered conjugate gradient (CG) algorithm in the MILC code for use with the Intel Knights Landing (KNL) architecture. KNL is the second gener- ation Intel Xeon Phi processor. It is capable of massive thread parallelism, data parallelism, and high on-board memory bandwidth and is being adopted in supercomputing centers for scientific research. The CG solver consumes the majority of time in production running, so we have spent most of our effort on it. We compare performance of an MPI+OpenMP baseline version of the MILC code with a version incorporating the QPhiX staggered CG solver, for both one-node and multi-node runs.

  7. Vectorization for Molecular Dynamics on Intel Xeon Phi Corpocessors

    Science.gov (United States)

    Yi, Hongsuk

    2014-03-01

    Many modern processors are capable of exploiting data-level parallelism through the use of single instruction multiple data (SIMD) execution. The new Intel Xeon Phi coprocessor supports 512 bit vector registers for the high performance computing. In this paper, we have developed a hierarchical parallelization scheme for accelerated molecular dynamics simulations with the Terfoff potentials for covalent bond solid crystals on Intel Xeon Phi coprocessor systems. The scheme exploits multi-level parallelism computing. We combine thread-level parallelism using a tightly coupled thread-level and task-level parallelism with 512-bit vector register. The simulation results show that the parallel performance of SIMD implementations on Xeon Phi is apparently superior to their x86 CPU architecture.

  8. Full cycle trigonometric function on Intel Quartus II Verilog

    Science.gov (United States)

    Mustapha, Muhazam; Zulkarnain, Nur Antasha

    2018-02-01

    This paper discusses about an improvement of a previous research on hardware based trigonometric calculations. Tangent function will also be implemented to get a complete set. The functions have been simulated using Quartus II where the result will be compared to the previous work. The number of bits has also been extended for each trigonometric function. The design is based on RTL due to its resource efficient nature. At earlier stage, a technology independent test bench simulation was conducted on ModelSim due to its convenience in capturing simulation data so that accuracy information can be obtained. On second stage, Intel/Altera Quartus II will be used to simulate on technology dependent platform, particularly on the one belonging to Intel/Altera itself. Real data on no. logic elements used and propagation delay have also been obtained.

  9. Porting FEASTFLOW to the Intel Xeon Phi: Lessons Learned

    OpenAIRE

    Georgios Goumas

    2014-01-01

    In this paper we report our experiences in porting the FEASTFLOW software infrastructure to the Intel Xeon Phi coprocessor. Our efforts involved both the evaluation of programming models including OpenCL, POSIX threads and OpenMP and typical optimization strategies like parallelization and vectorization. Since the straightforward porting process of the already existing OpenCL version of the code encountered performance problems that require further analysis, we focused our efforts on the impl...

  10. Protein Alignment on the Intel Xeon Phi Coprocessor

    OpenAIRE

    Ramstad, Jorun

    2015-01-01

    There is an increasing need for sensitive, high perfomance sequence alignemnet tools. With the growing databases of scientificly analyzed protein sequences, more compute power is necessary. Specialized architectures arise, and a transition from serial to specialized implementationsis is required. This thesis is a study of whether Intel 60's cores Xeon Phi coprocessor is a suitable architecture for implementation of a sequence alignment tool. The performance relative to existing tools are eval...

  11. Staggered Dslash Performance on Intel Xeon Phi Architecture

    OpenAIRE

    Li, Ruizi; Gottlieb, Steven

    2014-01-01

    The conjugate gradient (CG) algorithm is among the most essential and time consuming parts of lattice calculations with staggered quarks. We test the performance of CG and dslash, the key step in the CG algorithm, on the Intel Xeon Phi, also known as the Many Integrated Core (MIC) architecture. We try different parallelization strategies using MPI, OpenMP, and the vector processing units (VPUs).

  12. Intel·ligència emocional a maternal

    OpenAIRE

    Missé Cortina, Jordi

    2015-01-01

    Inclusió d'activitats d'intel·ligència emocional a maternal A i B per al treball de l'adquisició de valors com l'autoestima, el respecte, la tolerància, etc. Inclusión de actividades de inteligencia emocional en maternal A y B para el trabajo de la adquisición de valores como la autoestima, el respeto, la tolerancia, etc. Practicum for the Psychology program on Educational Psychology.

  13. Exploring performance and power properties of modern multicore chips via simple machine models

    OpenAIRE

    Hager, Georg; Treibig, Jan; Habich, Johannes; Wellein, Gerhard

    2012-01-01

    Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the wel...

  14. Thread-level parallelization and optimization of NWChem for the Intel MIC architecture

    Energy Technology Data Exchange (ETDEWEB)

    Shan, Hongzhang [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Williams, Samuel [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); de Jong, Wibe [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Oliker, Leonid [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

    2015-01-01

    In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant e ort was required to safely and efeciently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI+OpenMP hybrid implementations attain up to 65× better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6× better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.

  15. Thread-Level Parallelization and Optimization of NWChem for the Intel MIC Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Shan, Hongzhang; Williams, Samuel; Jong, Wibe de; Oliker, Leonid

    2014-10-10

    In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in tt native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant effort was required to safely and efficiently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI OpenMP hybrid implementations attain up to 65x better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6x better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.

  16. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2010-12-01

    Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

  17. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  18. Does the Intel Xeon Phi processor fit HEP workloads?

    Science.gov (United States)

    Nowak, A.; Bitzes, G.; Dotti, A.; Lazzaro, A.; Jarp, S.; Szostek, P.; Valsan, L.; Botezatu, M.; Leduc, J.

    2014-06-01

    This paper summarizes the five years of CERN openlab's efforts focused on the Intel Xeon Phi co-processor, from the time of its inception to public release. We consider the architecture of the device vis a vis the characteristics of HEP software and identify key opportunities for HEP processing, as well as scaling limitations. We report on improvements and speedups linked to parallelization and vectorization on benchmarks involving software frameworks such as Geant4 and ROOT. Finally, we extrapolate current software and hardware trends and project them onto accelerators of the future, with the specifics of offline and online HEP processing in mind.

  19. Does the Intel Xeon Phi processor fit HEP workloads?

    International Nuclear Information System (INIS)

    Nowak, A; Bitzes, G; Dotti, A; Lazzaro, A; Jarp, S; Szostek, P; Valsan, L; Botezatu, M; Leduc, J

    2014-01-01

    This paper summarizes the five years of CERN openlab's efforts focused on the Intel Xeon Phi co-processor, from the time of its inception to public release. We consider the architecture of the device vis a vis the characteristics of HEP software and identify key opportunities for HEP processing, as well as scaling limitations. We report on improvements and speedups linked to parallelization and vectorization on benchmarks involving software frameworks such as Geant4 and ROOT. Finally, we extrapolate current software and hardware trends and project them onto accelerators of the future, with the specifics of offline and online HEP processing in mind.

  20. Evaluation of the Intel Westmere-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2011-01-01

    One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

  1. Global synchronization algorithms for the Intel iPSC/860

    Science.gov (United States)

    Seidel, Steven R.; Davis, Mark A.

    1992-01-01

    In a distributed memory multicomputer that has no global clock, global processor synchronization can only be achieved through software. Global synchronization algorithms are used in tridiagonal systems solvers, CFD codes, sequence comparison algorithms, and sorting algorithms. They are also useful for event simulation, debugging, and for solving mutual exclusion problems. For the Intel iPSC/860 in particular, global synchronization can be used to ensure the most effective use of the communication network for operations such as the shift, where each processor in a one-dimensional array or ring concurrently sends a message to its right (or left) neighbor. Three global synchronization algorithms are considered for the iPSC/860: the gysnc() primitive provided by Intel, the PICL primitive sync0(), and a new recursive doubling synchronization (RDS) algorithm. The performance of these algorithms is compared to the performance predicted by communication models of both the long and forced message protocols. Measurements of the cost of shift operations preceded by global synchronization show that the RDS algorithm always synchronizes the nodes more precisely and costs only slightly more than the other two algorithms.

  2. Lawrence Livermore National Laboratory selects Intel Itanium 2 processors for world's most powerful Linux cluster

    CERN Multimedia

    2003-01-01

    "Intel Corporation, system manufacturer California Digital and the University of California at Lawrence Livermore National Laboratory (LLNL) today announced they are building one of the world's most powerful supercomputers. The supercomputer project, codenamed "Thunder," uses nearly 4,000 Intel® Itanium® 2 processors... is expected to be complete in January 2004" (1 page).

  3. 75 FR 48338 - Intel Corporation; Analysis of Proposed Consent Order to Aid Public Comment

    Science.gov (United States)

    2010-08-10

    ... product road maps, its compilers, and product benchmarking (Sections VI, VII, and VIII). The Proposed... alleges that Intel's failure to fully disclose the changes it made to its compilers and libraries... benchmarking organizations the effects of its compiler redesign on non-Intel CPUs. Several benchmarking...

  4. Efficient Implementation of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Apra, Edoardo; Klemm, Michael; Kowalski, Karol

    2014-12-01

    This paper presents the implementation and performance of the highly accurate CCSD(T) quantum chemistry method on the Intel Xeon Phi coprocessor within the context of the NWChem computational chemistry package. The widespread use of highly correlated methods in electronic structure calculations is contingent upon the interplay between advances in theory and the possibility of utilizing the ever-growing computer power of emerging heterogeneous architectures. We discuss the design decisions of our implementation as well as the optimizations applied to the compute kernels and data transfers between host and coprocessor. We show the feasibility of adopting the Intel Many Integrated Core Architecture and the Intel Xeon Phi coprocessor for developing efficient computational chemistry modeling tools. Remarkable scalability is demonstrated by benchmarks. Our solution scales up to a total of 62560 cores with the concurrent utilization of Intel Xeon processors and Intel Xeon Phi coprocessors.

  5. Analysis OpenMP performance of AMD and Intel architecture for breaking waves simulation using MPS

    Science.gov (United States)

    Alamsyah, M. N. A.; Utomo, A.; Gunawan, P. H.

    2018-03-01

    Simulation of breaking waves by using Navier-Stokes equation via moving particle semi-implicit method (MPS) over close domain is given. The results show the parallel computing on multicore architecture using OpenMP platform can reduce the computational time almost half of the serial time. Here, the comparison using two computer architectures (AMD and Intel) are performed. The results using Intel architecture is shown better than AMD architecture in CPU time. However, in efficiency, the computer with AMD architecture gives slightly higher than the Intel. For the simulation by 1512 number of particles, the CPU time using Intel and AMD are 12662.47 and 28282.30 respectively. Moreover, the efficiency using similar number of particles, AMD obtains 50.09 % and Intel up to 49.42 %.

  6. 75 FR 21353 - Intel Corporation, Fab 20 Division, Including On-Site Leased Workers From Volt Technical...

    Science.gov (United States)

    2010-04-23

    ... DEPARTMENT OF LABOR Employment and Training Administration [TA-W-73,642] Intel Corporation, Fab 20... of Intel Corporation, Fab 20 Division, including on-site leased workers of Volt Technical Resources... Precision, Inc. were employed on-site at the Hillsboro, Oregon location of Intel Corporation, Fab 20...

  7. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  8. Performance of a plasma fluid code on the Intel parallel computers

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Leboeuf, J.N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel σ machine gives an improvement factor close to 64 over the single-processor CRAY-2

  9. Performance of a plasma fluid code on the Intel parallel computers

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Leboeuf, J.N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel (sigma) machine gives an improvement factor close to 64 over the single-processor CRAY-2. 12 refs

  10. Performance of a plasma fluid code on the Intel parallel computers

    Science.gov (United States)

    Lynch, V. E.; Carreras, B. A.; Drake, J. B.; Leboeuf, J. N.; Liewer, P.

    1992-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A parallel algorithm for plasma turbulence calculations was tested on the Intel iPSC/860 hypercube and the Touchtone Delta machine. Using the 128 processors of the Intel iPSC/860 hypercube, a factor of 5 improvement over a single-processor CRAY-2 is obtained. For the Touchtone Delta machine, the corresponding improvement factor is 16. For plasma edge turbulence calculations, an extrapolation of the present results to the Intel (sigma) machine gives an improvement factor close to 64 over the single-processor CRAY-2.

  11. Applications Performance on NAS Intel Paragon XP/S - 15#

    Science.gov (United States)

    Saini, Subhash; Simon, Horst D.; Copper, D. M. (Technical Monitor)

    1994-01-01

    The Numerical Aerodynamic Simulation (NAS) Systems Division received an Intel Touchstone Sigma prototype model Paragon XP/S- 15 in February, 1993. The i860 XP microprocessor with an integrated floating point unit and operating in dual -instruction mode gives peak performance of 75 million floating point operations (NIFLOPS) per second for 64 bit floating point arithmetic. It is used in the Paragon XP/S-15 which has been installed at NAS, NASA Ames Research Center. The NAS Paragon has 208 nodes and its peak performance is 15.6 GFLOPS. Here, we will report on early experience using the Paragon XP/S- 15. We have tested its performance using both kernels and applications of interest to NAS. We have measured the performance of BLAS 1, 2 and 3 both assembly-coded and Fortran coded on NAS Paragon XP/S- 15. Furthermore, we have investigated the performance of a single node one-dimensional FFT, a distributed two-dimensional FFT and a distributed three-dimensional FFT Finally, we measured the performance of NAS Parallel Benchmarks (NPB) on the Paragon and compare it with the performance obtained on other highly parallel machines, such as CM-5, CRAY T3D, IBM SP I, etc. In particular, we investigated the following issues, which can strongly affect the performance of the Paragon: a. Impact of the operating system: Intel currently uses as a default an operating system OSF/1 AD from the Open Software Foundation. The paging of Open Software Foundation (OSF) server at 22 MB to make more memory available for the application degrades the performance. We found that when the limit of 26 NIB per node out of 32 MB available is reached, the application is paged out of main memory using virtual memory. When the application starts paging, the performance is considerably reduced. We found that dynamic memory allocation can help applications performance under certain circumstances. b. Impact of data cache on the i860/XP: We measured the performance of the BLAS both assembly coded and Fortran

  12. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  13. Single event effect testing of the Intel 80386 family and the 80486 microprocessor

    International Nuclear Information System (INIS)

    Moran, A.; LaBel, K.; Gates, M.; Seidleck, C.; McGraw, R.; Broida, M.; Firer, J.; Sprehn, S.

    1996-01-01

    The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored

  14. CAMSHIFT Tracker Design Experiments With Intel OpenCV and SAI

    National Research Council Canada - National Science Library

    Francois, Alexandre R

    2004-01-01

    ... (including multi-modal) systems, must be specifically addressed. This report describes design and implementation experiments for CAMSHIFT-based tracking systems using Intel's Open Computer Vision library and SAI...

  15. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    Science.gov (United States)

    Farrell, Steven; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea; ATLAS Collaboration

    2017-10-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with details on its multi-threaded design. Then, we will present a performance analysis of the application on KNL devices and compare it to a traditional x86 platform to demonstrate the capabilities of the architecture and evaluate the benefits of utilizing KNL platforms like Cori for ATLAS production.

  16. Performance optimization of Qbox and WEST on Intel Knights Landing

    Science.gov (United States)

    Zheng, Huihuo; Knight, Christopher; Galli, Giulia; Govoni, Marco; Gygi, Francois

    We present the optimization of electronic structure codes Qbox and WEST targeting the Intel®Xeon Phi™processor, codenamed Knights Landing (KNL). Qbox is an ab-initio molecular dynamics code based on plane wave density functional theory (DFT) and WEST is a post-DFT code for excited state calculations within many-body perturbation theory. Both Qbox and WEST employ highly scalable algorithms which enable accurate large-scale electronic structure calculations on leadership class supercomputer platforms beyond 100,000 cores, such as Mira and Theta at the Argonne Leadership Computing Facility. In this work, features of the KNL architecture (e.g. hierarchical memory) are explored to achieve higher performance in key algorithms of the Qbox and WEST codes and to develop a road-map for further development targeting next-generation computing architectures. In particular, the optimizations of the Qbox and WEST codes on the KNL platform will target efficient large-scale electronic structure calculations of nanostructured materials exhibiting complex structures and prediction of their electronic and thermal properties for use in solar and thermal energy conversion device. This work was supported by MICCoM, as part of Comp. Mats. Sci. Program funded by the U.S. DOE, Office of Sci., BES, MSE Division. This research used resources of the ALCF, which is a DOE Office of Sci. User Facility under Contract DE-AC02-06CH11357.

  17. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00014247; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea

    2017-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with detai...

  18. Multi-threaded ATLAS Simulation on Intel Knights Landing Processors

    CERN Document Server

    Farrell, Steven; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles

    2016-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), will be delivered to its users in two phases with the first phase online now and the second phase expected in mid-2016. Cori Phase 2 will be based on the KNL architecture and will contain over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a great use-case for the KNL architecture and supercomputers like Cori. Simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this presentation we will give an overview of the ATLAS simulation application with details on its multi-thr...

  19. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  20. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  1. Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture

    OpenAIRE

    Liu, Xu; Chen, Langshi; Firoz, Jesun S.; Qiu, Judy; Jiang, Lei

    2017-01-01

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging per...

  2. Adaptation of MPDATA Heterogeneous Stencil Computation to Intel Xeon Phi Coprocessor

    Directory of Open Access Journals (Sweden)

    Lukasz Szustak

    2015-01-01

    Full Text Available The multidimensional positive definite advection transport algorithm (MPDATA belongs to the group of nonoscillatory forward-in-time algorithms and performs a sequence of stencil computations. MPDATA is one of the major parts of the dynamic core of the EULAG geophysical model. In this work, we outline an approach to adaptation of the 3D MPDATA algorithm to the Intel MIC architecture. In order to utilize available computing resources, we propose the (3 + 1D decomposition of MPDATA heterogeneous stencil computations. This approach is based on combination of the loop tiling and fusion techniques. It allows us to ease memory/communication bounds and better exploit the theoretical floating point efficiency of target computing platforms. An important method of improving the efficiency of the (3 + 1D decomposition is partitioning of available cores/threads into work teams. It permits for reducing inter-cache communication overheads. This method also increases opportunities for the efficient distribution of MPDATA computation onto available resources of the Intel MIC architecture, as well as Intel CPUs. We discuss preliminary performance results obtained on two hybrid platforms, containing two CPUs and Intel Xeon Phi. The top-of-the-line Intel Xeon Phi 7120P gives the best performance results, and executes MPDATA almost 2 times faster than two Intel Xeon E5-2697v2 CPUs.

  3. Balancing Contention and Synchronization on the Intel Paragon

    Science.gov (United States)

    Bokhari, Shahid H.; Nicol, David M.

    1996-01-01

    The Intel Paragon is a mesh-connected distributed memory parallel computer. It uses an oblivious and deterministic message routing algorithm: this permits us to develop highly optimized schedules for frequently needed communication patterns. The complete exchange is one such pattern. Several approaches are available for carrying it out on the mesh. We study an algorithm developed by Scott. This algorithm assumes that a communication link can carry one message at a time and that a node can only transmit one message at a time. It requires global synchronization to enforce a schedule of transmissions. Unfortunately global synchronization has substantial overhead on the Paragon. At the same time the powerful interconnection mechanism of this machine permits 2 or 3 messages to share a communication link with minor overhead. It can also overlap multiple message transmission from the same node to some extent. We develop a generalization of Scott's algorithm that executes complete exchange with a prescribed contention. Schedules that incur greater contention require fewer synchronization steps. This permits us to tradeoff contention against synchronization overhead. We describe the performance of this algorithm and compare it with Scott's original algorithm as well as with a naive algorithm that does not take interconnection structure into account. The Bounded contention algorithm is always better than Scott's algorithm and outperforms the naive algorithm for all but the smallest message sizes. The naive algorithm fails to work on meshes larger than 12 x 12. These results show that due consideration of processor interconnect and machine performance parameters is necessary to obtain peak performance from the Paragon and its successor mesh machines.

  4. Multi-Kepler GPU vs. multi-Intel MIC for spin systems simulations

    Science.gov (United States)

    Bernaschi, M.; Bisson, M.; Salvadore, F.

    2014-10-01

    We present and compare the performances of two many-core architectures: the Nvidia Kepler and the Intel MIC both in a single system and in cluster configuration for the simulation of spin systems. As a benchmark we consider the time required to update a single spin of the 3D Heisenberg spin glass model by using the Over-relaxation algorithm. We present data also for a traditional high-end multi-core architecture: the Intel Sandy Bridge. The results show that although on the two Intel architectures it is possible to use basically the same code, the performances of a Intel MIC change dramatically depending on (apparently) minor details. Another issue is that to obtain a reasonable scalability with the Intel Phi coprocessor (Phi is the coprocessor that implements the MIC architecture) in a cluster configuration it is necessary to use the so-called offload mode which reduces the performances of the single system. As to the GPU, the Kepler architecture offers a clear advantage with respect to the previous Fermi architecture maintaining exactly the same source code. Scalability of the multi-GPU implementation remains very good by using the CPU as a communication co-processor of the GPU. All source codes are provided for inspection and for double-checking the results.

  5. Optimizing Performance of Combustion Chemistry Solvers on Intel's Many Integrated Core (MIC) Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Sitaraman, Hariswaran [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Grout, Ray W [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

    2017-06-09

    This work investigates novel algorithm designs and optimization techniques for restructuring chemistry integrators in zero and multidimensional combustion solvers, which can then be effectively used on the emerging generation of Intel's Many Integrated Core/Xeon Phi processors. These processors offer increased computing performance via large number of lightweight cores at relatively lower clock speeds compared to traditional processors (e.g. Intel Sandybridge/Ivybridge) used in current supercomputers. This style of processor can be productively used for chemistry integrators that form a costly part of computational combustion codes, in spite of their relatively lower clock speeds. Performance commensurate with traditional processors is achieved here through the combination of careful memory layout, exposing multiple levels of fine grain parallelism and through extensive use of vendor supported libraries (Cilk Plus and Math Kernel Libraries). Important optimization techniques for efficient memory usage and vectorization have been identified and quantified. These optimizations resulted in a factor of ~ 3 speed-up using Intel 2013 compiler and ~ 1.5 using Intel 2017 compiler for large chemical mechanisms compared to the unoptimized version on the Intel Xeon Phi. The strategies, especially with respect to memory usage and vectorization, should also be beneficial for general purpose computational fluid dynamics codes.

  6. Intel Xeon Phi accelerated Weather Research and Forecasting (WRF) Goddard microphysics scheme

    Science.gov (United States)

    Mielikainen, J.; Huang, B.; Huang, A. H.-L.

    2014-12-01

    The Weather Research and Forecasting (WRF) model is a numerical weather prediction system designed to serve both atmospheric research and operational forecasting needs. The WRF development is a done in collaboration around the globe. Furthermore, the WRF is used by academic atmospheric scientists, weather forecasters at the operational centers and so on. The WRF contains several physics components. The most time consuming one is the microphysics. One microphysics scheme is the Goddard cloud microphysics scheme. It is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The Goddard microphysics scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Goddard scheme incorporates a large number of improvements. Thus, we have optimized the Goddard scheme code. In this paper, we present our results of optimizing the Goddard microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The Intel MIC is capable of executing a full operating system and entire programs rather than just kernels as the GPU does. The MIC coprocessor supports all important Intel development tools. Thus, the development environment is one familiar to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discussed in this paper. The results show that the optimizations improved performance of Goddard microphysics scheme on Xeon Phi 7120P by a factor of 4.7×. In addition, the optimizations reduced the Goddard microphysics scheme's share of the total WRF processing time from 20.0 to 7.5%. Furthermore, the same optimizations

  7. High-performance computing on the Intel Xeon Phi how to fully exploit MIC architectures

    CERN Document Server

    Wang, Endong; Shen, Bo; Zhang, Guangyong; Lu, Xiaowei; Wu, Qing; Wang, Yajuan

    2014-01-01

    The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors' first-hand optimization experience.The material is organized in three sections. The first section, "Basics of MIC", introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment

  8. Evaluating the transport layer of the ALFA framework for the Intel® Xeon Phi™ Coprocessor

    Science.gov (United States)

    Santogidis, Aram; Hirstius, Andreas; Lalis, Spyros

    2015-12-01

    The ALFA framework supports the software development of major High Energy Physics experiments. As part of our research effort to optimize the transport layer of ALFA, we focus on profiling its data transfer performance for inter-node communication on the Intel Xeon Phi Coprocessor. In this article we present the collected performance measurements with the related analysis of the results. The optimization opportunities that are discovered, help us to formulate the future plans of enabling high performance data transfer for ALFA on the Intel Xeon Phi architecture.

  9. Implementation of High-Order Multireference Coupled-Cluster Methods on Intel Many Integrated Core Architecture.

    Science.gov (United States)

    Aprà, E; Kowalski, K

    2016-03-08

    In this paper we discuss the implementation of multireference coupled-cluster formalism with singles, doubles, and noniterative triples (MRCCSD(T)), which is capable of taking advantage of the processing power of the Intel Xeon Phi coprocessor. We discuss the integration of two levels of parallelism underlying the MRCCSD(T) implementation with computational kernels designed to offload the computationally intensive parts of the MRCCSD(T) formalism to Intel Xeon Phi coprocessors. Special attention is given to the enhancement of the parallel performance by task reordering that has improved load balancing in the noniterative part of the MRCCSD(T) calculations. We also discuss aspects regarding efficient optimization and vectorization strategies.

  10. Towards Porting a Real-World Seismological Application to the Intel MIC Architecture

    OpenAIRE

    V. Weinberg

    2014-01-01

    This whitepaper aims to discuss first experiences with porting an MPI-based real-world geophysical application to the new Intel Many Integrated Core (MIC) architecture. The selected code SeisSol is an application written in Fortran that can be used to simulate earthquake rupture and radiating seismic wave propagation in complex 3-D heterogeneous materials. The PRACE prototype cluster EURORA at CINECA, Italy, was accessed to analyse the MPI-performance of SeisSol on Intel Xeon Phi on both sing...

  11. Accelerating the Pace of Protein Functional Annotation With Intel Xeon Phi Coprocessors.

    Science.gov (United States)

    Feinstein, Wei P; Moreno, Juana; Jarrell, Mark; Brylinski, Michal

    2015-06-01

    Intel Xeon Phi is a new addition to the family of powerful parallel accelerators. The range of its potential applications in computationally driven research is broad; however, at present, the repository of scientific codes is still relatively limited. In this study, we describe the development and benchmarking of a parallel version of eFindSite, a structural bioinformatics algorithm for the prediction of ligand-binding sites in proteins. Implemented for the Intel Xeon Phi platform, the parallelization of the structure alignment portion of eFindSite using pragma-based OpenMP brings about the desired performance improvements, which scale well with the number of computing cores. Compared to a serial version, the parallel code runs 11.8 and 10.1 times faster on the CPU and the coprocessor, respectively; when both resources are utilized simultaneously, the speedup is 17.6. For example, ligand-binding predictions for 501 benchmarking proteins are completed in 2.1 hours on a single Stampede node equipped with the Intel Xeon Phi card compared to 3.1 hours without the accelerator and 36.8 hours required by a serial version. In addition to the satisfactory parallel performance, porting existing scientific codes to the Intel Xeon Phi architecture is relatively straightforward with a short development time due to the support of common parallel programming models by the coprocessor. The parallel version of eFindSite is freely available to the academic community at www.brylinski.org/efindsite.

  12. Extension of the AMBER molecular dynamics software to Intel's Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Needham, Perri J.; Bhuiyan, Ashraf; Walker, Ross C.

    2016-04-01

    We present an implementation of explicit solvent particle mesh Ewald (PME) classical molecular dynamics (MD) within the PMEMD molecular dynamics engine, that forms part of the AMBER v14 MD software package, that makes use of Intel Xeon Phi coprocessors by offloading portions of the PME direct summation and neighbor list build to the coprocessor. We refer to this implementation as pmemd MIC offload and in this paper present the technical details of the algorithm, including basic models for MPI and OpenMP configuration, and analyze the resultant performance. The algorithm provides the best performance improvement for large systems (>400,000 atoms), achieving a ∼35% performance improvement for satellite tobacco mosaic virus (1,067,095 atoms) when 2 Intel E5-2697 v2 processors (2 ×12 cores, 30M cache, 2.7 GHz) are coupled to an Intel Xeon Phi coprocessor (Model 7120P-1.238/1.333 GHz, 61 cores). The implementation utilizes a two-fold decomposition strategy: spatial decomposition using an MPI library and thread-based decomposition using OpenMP. We also present compiler optimization settings that improve the performance on Intel Xeon processors, while retaining simulation accuracy.

  13. Game-Based Experiential Learning in Online Management Information Systems Classes Using Intel's IT Manager 3

    Science.gov (United States)

    Bliemel, Michael; Ali-Hassan, Hossam

    2014-01-01

    For several years, we used Intel's flash-based game "IT Manager 3: Unseen Forces" as an experiential learning tool, where students had to act as a manager making real-time prioritization decisions about repairing computer problems, training and upgrading systems with better technologies as well as managing increasing numbers of technical…

  14. Why K-12 IT Managers and Administrators Are Embracing the Intel-Based Mac

    Science.gov (United States)

    Technology & Learning, 2007

    2007-01-01

    Over the past year, Apple has dramatically increased its share of the school computer marketplace--especially in the category of notebook computers. A recent study conducted by Grunwald Associates and Rockman et al. reports that one of the major reasons for this growth is Apple's introduction of the Intel processor to the entire line of Mac…

  15. Performance tuning Weather Research and Forecasting (WRF) Goddard longwave radiative transfer scheme on Intel Xeon Phi

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2015-10-01

    Next-generation mesoscale numerical weather prediction system, the Weather Research and Forecasting (WRF) model, is a designed for dual use for forecasting and research. WRF offers multiple physics options that can be combined in any way. One of the physics options is radiance computation. The major source for energy for the earth's climate is solar radiation. Thus, it is imperative to accurately model horizontal and vertical distribution of the heating. Goddard solar radiative transfer model includes the absorption duo to water vapor,ozone, ozygen, carbon dioxide, clouds and aerosols. The model computes the interactions among the absorption and scattering by clouds, aerosols, molecules and surface. Finally, fluxes are integrated over the entire longwave spectrum.In this paper, we present our results of optimizing the Goddard longwave radiative transfer scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The optimizations improved the performance of the original Goddard longwave radiative transfer scheme on Xeon Phi 7120P by a factor of 2.2x. Furthermore, the same optimizations improved the performance of the Goddard longwave radiative transfer scheme on a dual socket configuration of eight core Intel Xeon E5-2670 CPUs by a factor of 2.1x compared to the original Goddard longwave radiative transfer scheme code.

  16. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  17. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  18. Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study

    OpenAIRE

    Rucci, Enzo; De Giusti, Armando Eduardo; Naiouf, Marcelo

    2017-01-01

    Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm ...

  19. Benchmarking Data Analysis and Machine Learning Applications on the Intel KNL Many-Core Processor

    OpenAIRE

    Byun, Chansup; Kepner, Jeremy; Arcand, William; Bestor, David; Bergeron, Bill; Gadepally, Vijay; Houle, Michael; Hubbell, Matthew; Jones, Michael; Klein, Anna; Michaleas, Peter; Milechin, Lauren; Mullen, Julie; Prout, Andrew; Rosa, Antonio

    2017-01-01

    Knights Landing (KNL) is the code name for the second-generation Intel Xeon Phi product family. KNL has generated significant interest in the data analysis and machine learning communities because its new many-core architecture targets both of these workloads. The KNL many-core vector processor design enables it to exploit much higher levels of parallelism. At the Lincoln Laboratory Supercomputing Center (LLSC), the majority of users are running data analysis applications such as MATLAB and O...

  20. Accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) model on Intel Xeon Phi processors

    OpenAIRE

    Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junming; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

    2017-01-01

    The GNAQPMS model is the global version of the Nested Air Quality Prediction Modelling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present our work of porting and optimizing the GNAQPMS model on the second generation Intel Xeon Phi processor codename “Knights Landing” (KNL). Compared with the first generation Xeon Phi coprocessor, KNL introduced many new hardware features such as a boo...

  1. Applying the roofline performance model to the intel xeon phi knights landing processor

    OpenAIRE

    Doerfler, D; Deslippe, J; Williams, S; Oliker, L; Cook, B; Kurth, T; Lobet, M; Malas, T; Vay, JL; Vincenti, H

    2016-01-01

    � Springer International Publishing AG 2016. The Roofline Performance Model is a visually intuitive method used to bound the sustained peak floating-point performance of any given arithmetic kernel on any given processor architecture. In the Roofline, performance is nominally measured in floating-point operations per second as a function of arithmetic intensity (operations per byte of data). In this study we determine the Roofline for the Intel Knights Landing (KNL) processor, determining t...

  2. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™

    OpenAIRE

    Gomes, Jeremias M.; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H.

    2015-01-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel® Xeon Phi™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP’s irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high perfo...

  3. Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator

    OpenAIRE

    Hofmann, Johannes; Treibig, Jan; Hager, Georg; Wellein, Gerhard

    2013-01-01

    We examine the Xeon Phi, which is based on Intel's Many Integrated Cores architecture, for its suitability to run the FDK algorithm--the most commonly used algorithm to perform the 3D image reconstruction in cone-beam computed tomography. We study the challenges of efficiently parallelizing the application and means to enable sensible data sharing between threads despite the lack of a shared last level cache. Apart from parallelization, SIMD vectorization is critical for good performance on t...

  4. DBPQL: A view-oriented query language for the Intel Data Base Processor

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    An interactive query language (BDPQL) for the Intel Data Base Processor (DBP) is defined. DBPQL includes a parser generator package which permits the analyst to easily create and manipulate the query statement syntax and semantics. The prototype language, DBPQL, includes trace and performance commands to aid the analyst when implementing new commands and analyzing the execution characteristics of the DBP. The DBPQL grammar file and associated key procedures are included as an appendix to this report.

  5. Autonomous controller (JCAM 10) for CAMAC crate with 8080 (INTEL) microprocessor

    International Nuclear Information System (INIS)

    Gallice, P.; Mathis, M.

    1975-01-01

    The CAMAC crate autonomous controller JCAM-10 is designed around an INTEL 8080 microprocessor in association with a 5K RAM and 4K REPROM memory. The concept of the module is described, in which data transfers between CAMAC modules and the memory are optimised from software point of view as well as from execution time. In fact, the JCAM-10 is a microcomputer with a set of 1000 peripheral units represented by the CAMAC modules commercially available

  6. Practical Implementation of Lattice QCD Simulation on Intel Xeon Phi Knights Landing

    OpenAIRE

    Kanamori, Issaku; Matsufuru, Hideo

    2017-01-01

    We investigate implementation of lattice Quantum Chromodynamics (QCD) code on the Intel Xeon Phi Knights Landing (KNL). The most time consuming part of the numerical simulations of lattice QCD is a solver of linear equation for a large sparse matrix that represents the strong interaction among quarks. To establish widely applicable prescriptions, we examine rather general methods for the SIMD architecture of KNL, such as using intrinsics and manual prefetching, to the matrix multiplication an...

  7. Acceleration of Blender Cycles Path-Tracing Engine Using Intel Many Integrated Core Architecture

    OpenAIRE

    Jaroš , Milan; Říha , Lubomír; Strakoš , Petr; Karásek , Tomáš; Vašatová , Alena; Jarošová , Marta; Kozubek , Tomáš

    2015-01-01

    Part 2: Algorithms; International audience; This paper describes the acceleration of the most computationally intensive kernels of the Blender rendering engine, Blender Cycles, using Intel Many Integrated Core architecture (MIC). The proposed parallelization, which uses OpenMP technology, also improves the performance of the rendering engine when running on multi-core CPUs and multi-socket servers. Although the GPU acceleration is already implemented in Cycles, its functionality is limited. O...

  8. Real-time data acquisition and feedback control using Linux Intel computers

    International Nuclear Information System (INIS)

    Penaflor, B.G.; Ferron, J.R.; Piglowski, D.A.; Johnson, R.D.; Walker, M.L.

    2006-01-01

    This paper describes the experiences of the DIII-D programming staff in adapting Linux based Intel computing hardware for use in real-time data acquisition and feedback control systems. Due to the highly dynamic and unstable nature of magnetically confined plasmas in tokamak fusion experiments, real-time data acquisition and feedback control systems are in routine use with all major tokamaks. At DIII-D, plasmas are created and sustained using a real-time application known as the digital plasma control system (PCS). During each experiment, the PCS periodically samples data from hundreds of diagnostic signals and provides these data to control algorithms implemented in software. These algorithms compute the necessary commands to send to various actuators that affect plasma performance. The PCS consists of a group of rack mounted Intel Xeon computer systems running an in-house customized version of the Linux operating system tailored specifically to meet the real-time performance needs of the plasma experiments. This paper provides a more detailed description of the real-time computing hardware and custom developed software, including recent work to utilize dual Intel Xeon equipped computers within the PCS

  9. Implementation of an Agent-Based Parallel Tissue Modelling Framework for the Intel MIC Architecture

    Directory of Open Access Journals (Sweden)

    Maciej Cytowski

    2017-01-01

    Full Text Available Timothy is a novel large scale modelling framework that allows simulating of biological processes involving different cellular colonies growing and interacting with variable environment. Timothy was designed for execution on massively parallel High Performance Computing (HPC systems. The high parallel scalability of the implementation allows for simulations of up to 109 individual cells (i.e., simulations at tissue spatial scales of up to 1 cm3 in size. With the recent advancements of the Timothy model, it has become critical to ensure appropriate performance level on emerging HPC architectures. For instance, the introduction of blood vessels supplying nutrients to the tissue is a very important step towards realistic simulations of complex biological processes, but it greatly increased the computational complexity of the model. In this paper, we describe the process of modernization of the application in order to achieve high computational performance on HPC hybrid systems based on modern Intel® MIC architecture. Experimental results on the Intel Xeon Phi™ coprocessor x100 and the Intel Xeon Phi processor x200 are presented.

  10. Experience with Intel's many integrated core architecture in ATLAS software

    International Nuclear Information System (INIS)

    Fleischmann, S; Neumann, M; Kama, S; Lavrijsen, W; Vitillo, R

    2014-01-01

    Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks (TBB). This should make it possible to develop for both throughput and latency devices using a single code base. In ATLAS Software, track reconstruction has been shown to be a good candidate for throughput computing on GPGPU devices. In addition, the newly proposed offline parallel event-processing framework, GaudiHive, uses TBB for task scheduling. The MIC is thus, in principle, a good fit for this domain. In this paper, we report our experiences of porting to and optimizing ATLAS tracking algorithms for the MIC, comparing the programmability and relative cost/performance of the MIC against those of current GPGPUs and latency-optimized CPUs.

  11. Scaling deep learning workloads: NVIDIA DGX-1/Pascal and Intel Knights Landing

    Energy Technology Data Exchange (ETDEWEB)

    Gawande, Nitin A.; Landwehr, Joshua B.; Daily, Jeffrey A.; Tallent, Nathan R.; Vishnu, Abhinav; Kerbyson, Darren J.

    2017-08-24

    Deep Learning (DL) algorithms have become ubiquitous in data analytics. As a result, major computing vendors --- including NVIDIA, Intel, AMD, and IBM --- have architectural road-maps influenced by DL workloads. Furthermore, several vendors have recently advertised new computing products as accelerating large DL workloads. Unfortunately, it is difficult for data scientists to quantify the potential of these different products. This paper provides a performance and power analysis of important DL workloads on two major parallel architectures: NVIDIA DGX-1 (eight Pascal P100 GPUs interconnected with NVLink) and Intel Knights Landing (KNL) CPUs interconnected with Intel Omni-Path or Cray Aries. Our evaluation consists of a cross section of convolutional neural net workloads: CifarNet, AlexNet, GoogLeNet, and ResNet50 topologies using the Cifar10 and ImageNet datasets. The workloads are vendor-optimized for each architecture. Our analysis indicates that although GPUs provide the highest overall performance, the gap can close for some convolutional networks; and the KNL can be competitive in performance/watt. We find that NVLink facilitates scaling efficiency on GPUs. However, its importance is heavily dependent on neural network architecture. Furthermore, for weak-scaling --- sometimes encouraged by restricted GPU memory --- NVLink is less important.

  12. Scaling Deep Learning Workloads: NVIDIA DGX-1/Pascal and Intel Knights Landing

    Energy Technology Data Exchange (ETDEWEB)

    Gawande, Nitin A.; Landwehr, Joshua B.; Daily, Jeffrey A.; Tallent, Nathan R.; Vishnu, Abhinav; Kerbyson, Darren J.

    2017-07-03

    Deep Learning (DL) algorithms have become ubiquitous in data analytics. As a result, major computing vendors --- including NVIDIA, Intel, AMD and IBM --- have architectural road-maps influenced by DL workloads. Furthermore, several vendors have recently advertised new computing products as accelerating DL workloads. Unfortunately, it is difficult for data scientists to quantify the potential of these different products. This paper provides a performance and power analysis of important DL workloads on two major parallel architectures: NVIDIA DGX-1 (eight Pascal P100 GPUs interconnected with NVLink) and Intel Knights Landing (KNL) CPUs interconnected with Intel Omni-Path. Our evaluation consists of a cross section of convolutional neural net workloads: CifarNet, CaffeNet, AlexNet and GoogleNet topologies using the Cifar10 and ImageNet datasets. The workloads are vendor optimized for each architecture. GPUs provide the highest overall raw performance. Our analysis indicates that although GPUs provide the highest overall performance, the gap can close for some convolutional networks; and KNL can be competitive when considering performance/watt. Furthermore, NVLink is critical to GPU scaling.

  13. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  14. Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

    OpenAIRE

    Stanic, Milan; Palomar, Oscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman; Cristal, Adrian; Valero, Mateo

    2014-01-01

    Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if Graph500 is suitable for vectorization mostly due a lack of vector memory instructions for irregular memory accesses. The Xeon Phi is a massively parallel processor recently released by Intel with new features such as a wide 512-bit vector unit and vector scatter/gather instru...

  15. Performance Analysis of an Astrophysical Simulation Code on the Intel Xeon Phi Architecture

    OpenAIRE

    Noormofidi, Vahid; Atlas, Susan R.; Duan, Huaiyu

    2015-01-01

    We have developed the astrophysical simulation code XFLAT to study neutrino oscillations in supernovae. XFLAT is designed to utilize multiple levels of parallelism through MPI, OpenMP, and SIMD instructions (vectorization). It can run on both CPU and Xeon Phi co-processors based on the Intel Many Integrated Core Architecture (MIC). We analyze the performance of XFLAT on configurations with CPU only, Xeon Phi only and both CPU and Xeon Phi. We also investigate the impact of I/O and the multi-n...

  16. Optimizing the MapReduce Framework on Intel Xeon Phi Coprocessor

    OpenAIRE

    Lu, Mian; Zhang, Lei; Huynh, Huynh Phung; Ong, Zhongliang; Liang, Yun; He, Bingsheng; Goh, Rick Siow Mong; Huynh, Richard

    2013-01-01

    With the ease-of-programming, flexibility and yet efficiency, MapReduce has become one of the most popular frameworks for building big-data applications. MapReduce was originally designed for distributed-computing, and has been extended to various architectures, e,g, multi-core CPUs, GPUs and FPGAs. In this work, we focus on optimizing the MapReduce framework on Xeon Phi, which is the latest product released by Intel based on the Many Integrated Core Architecture. To the best of our knowledge...

  17. Mashup d'aplicacions basat en un buscador intel·ligent

    OpenAIRE

    Sancho Piqueras, Javier

    2010-01-01

    Mashup de funcionalitats, basat en un cercador intel·ligent, en aquest cas pensat per a cursos, carreres màsters, etc. La finalitat és adjuntar diverses aplicacions amb l'únic propòsit que en aquest cas és un buscador però que també ens permet utilitzar eines per a la connectivitat mitjançant web Services, o xarxes socials. Mashup de funcionalidades, basado en un buscador inteligente, en este caso pensado para cursos, carreras másters, etc. La finalidad es juntar diversas aplicaciones con ...

  18. Profiling CPU-bound workloads on Intel Haswell-EP platforms

    CERN Document Server

    Guerri, Marco; Cristovao, Cordeiro; CERN. Geneva. IT Department

    2017-01-01

    With the increasing adoption of public and private cloud resources to support the demands in terms of computing capacity of the WLCG, the HEP community has begun studying several benchmarking applications aimed at continuously assessing the performance of virtual machines procured from commercial providers. In order to characterise the behaviour of these benchmarks, in-depth profiling activities have been carried out. In this document we outline our experience in profiling one specific application, the ATLAS Kit Validation, in an attempt to explain an unexpected distribution in the performance samples obtained on systems based on Intel Haswell-EP processors.

  19. A new shared-memory programming paradigm for molecular dynamics simulations on the Intel Paragon

    International Nuclear Information System (INIS)

    D'Azevedo, E.F.; Romine, C.H.

    1994-12-01

    This report describes the use of shared memory emulation with DOLIB (Distributed Object Library) to simplify parallel programming on the Intel Paragon. A molecular dynamics application is used as an example to illustrate the use of the DOLIB shared memory library. SOTON-PAR, a parallel molecular dynamics code with explicit message-passing using a Lennard-Jones 6-12 potential, is rewritten using DOLIB primitives. The resulting code has no explicit message primitives and resembles a serial code. The new code can perform dynamic load balancing and achieves better performance than the original parallel code with explicit message-passing

  20. Optimizing the updated Goddard shortwave radiation Weather Research and Forecasting (WRF) scheme for Intel Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.-L.

    2015-05-01

    Intel Many Integrated Core (MIC) ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our results of optimizing the updated Goddard shortwave radiation Weather Research and Forecasting (WRF) scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The co-processor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of Xeon Phi will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The results show that the optimizations improved performance of the original code on Xeon Phi 7120P by a factor of 1.3x.

  1. Roofline Analysis in the Intel® Advisor to Deliver Optimized Performance for applications on Intel® Xeon Phi™ Processor

    Energy Technology Data Exchange (ETDEWEB)

    Koskela, Tuomas S.; Lobet, Mathieu; Deslippe, Jack; Matveev, Zakhar

    2017-05-23

    In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science applications to achieve up to 4.6 times speed-up and prepare for future exascale architectures. # Goal/Relevance of Session The roofline model [1,2] is a powerful tool for analyzing the performance of applications with respect to the theoretical peak achievable on a given computer architecture. It allows one to graphically represent the performance of an application in terms of operational intensity, i.e. the ratio of flops performed and bytes moved from memory in order to guide optimization efforts. Given the scale and complexity of modern science applications, it can often be a tedious task for the user to perform the analysis on the level of functions or loops to identify where performance gains can be made. With new Intel tools, it is now possible to automate this task, as well as base the estimates of peak performance on measurements rather than vendor specifications. The goal of this session is to demonstrate how the roofline feature of Intel Advisor can be used to balance memory vs. computation related optimization efforts and effectively identify performance bottlenecks. A series of typical optimization techniques: cache blocking, structure refactoring, data alignment, and vectorization illustrated by the kernel cases will be addressed. # Description of the codes ## XGC1 The XGC1 code [3] is a magnetic fusion Particle-In-Cell code that uses an unstructured mesh for its Poisson solver that allows it to accurately resolve the edge plasma of a magnetic fusion device. After

  2. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  3. Application of Intel Many Integrated Core (MIC) accelerators to the Pleim-Xiu land surface scheme

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2015-10-01

    The land-surface model (LSM) is one physics process in the weather research and forecast (WRF) model. The LSM includes atmospheric information from the surface layer scheme, radiative forcing from the radiation scheme, and precipitation forcing from the microphysics and convective schemes, together with internal information on the land's state variables and land-surface properties. The LSM is to provide heat and moisture fluxes over land points and sea-ice points. The Pleim-Xiu (PX) scheme is one LSM. The PX LSM features three pathways for moisture fluxes: evapotranspiration, soil evaporation, and evaporation from wet canopies. To accelerate the computation process of this scheme, we employ Intel Xeon Phi Many Integrated Core (MIC) Architecture as it is a multiprocessor computer structure with merits of efficient parallelization and vectorization essentials. Our results show that the MIC-based optimization of this scheme running on Xeon Phi coprocessor 7120P improves the performance by 2.3x and 11.7x as compared to the original code respectively running on one CPU socket (eight cores) and on one CPU core with Intel Xeon E5-2670.

  4. Optimizing the Betts-Miller-Janjic cumulus parameterization with Intel Many Integrated Core (MIC) architecture

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.-L.

    2015-10-01

    The schemes of cumulus parameterization are responsible for the sub-grid-scale effects of convective and/or shallow clouds, and intended to represent vertical fluxes due to unresolved updrafts and downdrafts and compensating motion outside the clouds. Some schemes additionally provide cloud and precipitation field tendencies in the convective column, and momentum tendencies due to convective transport of momentum. The schemes all provide the convective component of surface rainfall. Betts-Miller-Janjic (BMJ) is one scheme to fulfill such purposes in the weather research and forecast (WRF) model. National Centers for Environmental Prediction (NCEP) has tried to optimize the BMJ scheme for operational application. As there are no interactions among horizontal grid points, this scheme is very suitable for parallel computation. With the advantage of Intel Xeon Phi Many Integrated Core (MIC) architecture, efficient parallelization and vectorization essentials, it allows us to optimize the BMJ scheme. If compared to the original code respectively running on one CPU socket (eight cores) and on one CPU core with Intel Xeon E5-2670, the MIC-based optimization of this scheme running on Xeon Phi coprocessor 7120P improves the performance by 2.4x and 17.0x, respectively.

  5. Optimizing zonal advection of the Advanced Research WRF (ARW) dynamics for Intel MIC

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Weather Research and Forecast (WRF) model is the most widely used community weather forecast and research model in the world. There are two distinct varieties of WRF. The Advanced Research WRF (ARW) is an experimental, advanced research version featuring very high resolution. The WRF Nonhydrostatic Mesoscale Model (WRF-NMM) has been designed for forecasting operations. WRF consists of dynamics code and several physics modules. The WRF-ARW core is based on an Eulerian solver for the fully compressible nonhydrostatic equations. In the paper, we will use Intel Intel Many Integrated Core (MIC) architecture to substantially increase the performance of a zonal advection subroutine for optimization. It is of the most time consuming routines in the ARW dynamics core. Advection advances the explicit perturbation horizontal momentum equations by adding in the large-timestep tendency along with the small timestep pressure gradient tendency. We will describe the challenges we met during the development of a high-speed dynamics code subroutine for MIC architecture. Furthermore, lessons learned from the code optimization process will be discussed. The results show that the optimizations improved performance of the original code on Xeon Phi 5110P by a factor of 2.4x.

  6. Implementation of a 3-D nonlinear MHD [magnetohydrodynamics] calculation on the Intel hypercube

    International Nuclear Information System (INIS)

    Lynch, V.E.; Carreras, B.A.; Drake, J.B.; Hicks, H.R.; Lawkins, W.F.

    1987-01-01

    The optimization of numerical schemes and increasing computer capabilities in the last ten years have improved the efficiency of 3-D nonlinear resistive MHD calculations by about two to three orders of magnitude. However, we are still very limited in performing these types of calculations. Hypercubes have a large number of processors with only local memory and bidirectional links among neighbors. The Intel Hypercube at Oak Ridge has 64 processors with 0.5 megabytes of memory per processor. The multiplicity of processors opens new possibilities for the treatment of such computations. The constraint on time and resources favored the approach of using the existing RSF code which solves as an initial value problem the reduced set of MHD equations for a periodic cylindrical geometry. This code includes minimal physics and geometry, but contains the basic three dimensionality and nonlinear structure of the equations. The code solves the reduced set of MHD equations by Fourier expansion in two angular coordinates and finite differences in the radial one. Due to the continuing interest in these calculations and the likelihood that future supercomputers will take greater advantage of parallelism, the present study was initiated by the ORNL Exploratory Studies Committee and funded entirely by Laboratory Discretionary Funds. The objectives of the study were: to ascertain the suitability of MHD calculation for parallel computation, to design and implement a parallel algorithm to perform the computations, and to evaluate the hypercube, and in particular, ORNL's Intel iPSC, for use in MHD computations

  7. 3-D electromagnetic plasma particle simulations on the Intel Delta parallel computer

    International Nuclear Information System (INIS)

    Wang, J.; Liewer, P.C.

    1994-01-01

    A three-dimensional electromagnetic PIC code has been developed on the 512 node Intel Touchstone Delta MIMD parallel computer. This code is based on the General Concurrent PIC algorithm which uses a domain decomposition to divide the computation among the processors. The 3D simulation domain can be partitioned into 1-, 2-, or 3-dimensional sub-domains. Particles must be exchanged between processors as they move among the subdomains. The Intel Delta allows one to use this code for very-large-scale simulations (i.e. over 10 8 particles and 10 6 grid cells). The parallel efficiency of this code is measured, and the overall code performance on the Delta is compared with that on Cray supercomputers. It is shown that their code runs with a high parallel efficiency of ≥ 95% for large size problems. The particle push time achieved is 115 nsecs/particle/time step for 162 million particles on 512 nodes. Comparing with the performance on a single processor Cray C90, this represents a factor of 58 speedup. The code uses a finite-difference leap frog method for field solve which is significantly more efficient than fast fourier transforms on parallel computers. The performance of this code on the 128 node Cray T3D will also be discussed

  8. Revisiting Intel Xeon Phi optimization of Thompson cloud microphysics scheme in Weather Research and Forecasting (WRF) model

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen

    2015-10-01

    The Thompson cloud microphysics scheme is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Thompson scheme incorporates a large number of improvements. Thus, we have optimized the speed of this important part of WRF. Intel Many Integrated Core (MIC) ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our results of optimizing the Thompson microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. New optimizations for an updated Thompson scheme are discusses in this paper. The optimizations improved the performance of the original Thompson code on Xeon Phi 7120P by a factor of 1.8x. Furthermore, the same optimizations improved the performance of the Thompson on a dual socket configuration of eight core Intel Xeon E5-2670 CPUs by a factor of 1.8x compared to the original Thompson code.

  9. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  10. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  11. Transitioning to Intel-based Linux Servers in the Payload Operations Integration Center

    Science.gov (United States)

    Guillebeau, P. L.

    2004-01-01

    The MSFC Payload Operations Integration Center (POIC) is the focal point for International Space Station (ISS) payload operations. The POIC contains the facilities, hardware, software and communication interface necessary to support payload operations. ISS ground system support for processing and display of real-time spacecraft and telemetry and command data has been operational for several years. The hardware components were reaching end of life and vendor costs were increasing while ISS budgets were becoming severely constrained. Therefore it has been necessary to migrate the Unix portions of our ground systems to commodity priced Intel-based Linux servers. hardware architecture including networks, data storage, and highly available resources. This paper will concentrate on the Linux migration implementation for the software portion of our ground system. The migration began with 3.5 million lines of code running on Unix platforms with separate servers for telemetry, command, Payload information management systems, web, system control, remote server interface and databases. The Intel-based system is scheduled to be available for initial operational use by August 2004 The overall migration to Intel-based Linux servers in the control center involves changes to the This paper will address the Linux migration study approach including the proof of concept, criticality of customer buy-in and importance of beginning with POSlX compliant code. It will focus on the development approach explaining the software lifecycle. Other aspects of development will be covered including phased implementation, interim milestones and metrics measurements and reporting mechanisms. This paper will also address the testing approach covering all levels of testing including development, development integration, IV&V, user beta testing and acceptance testing. Test results including performance numbers compared with Unix servers will be included. need for a smooth transition while maintaining

  12. High-throughput sockets over RDMA for the Intel Xeon Phi coprocessor

    CERN Document Server

    Santogidis, Aram

    2017-01-01

    In this paper we describe the design, implementation and performance of Trans4SCIF, a user-level socket-like transport library for the Intel Xeon Phi coprocessor. Trans4SCIF library is primarily intended for high-throughput applications. It uses RDMA transfers over the native SCIF support, in a way that is transparent for the application, which has the illusion of using conventional stream sockets. We also discuss the integration of Trans4SCIF with the ZeroMQ messaging library, used extensively by several applications running at CERN. We show that this can lead to a substantial, up to 3x, increase of application throughput compared to the default TCP/IP transport option.

  13. GW Calculations of Materials on the Intel Xeon-Phi Architecture

    Science.gov (United States)

    Deslippe, Jack; da Jornada, Felipe H.; Vigil-Fowler, Derek; Biller, Ariel; Chelikowsky, James R.; Louie, Steven G.

    Intel Xeon-Phi processors are expected to power a large number of High-Performance Computing (HPC) systems around the United States and the world in the near future. We evaluate the ability of GW and pre-requisite Density Functional Theory (DFT) calculations for materials on utilizing the Xeon-Phi architecture. We describe the optimization process and performance improvements achieved. We find that the GW method, like other higher level Many-Body methods beyond standard local/semilocal approximations to Kohn-Sham DFT, is particularly well suited for many-core architectures due to the ability to exploit a large amount of parallelism over plane-waves, band-pairs and frequencies. Support provided by the SCIDAC program, Department of Energy, Office of Science, Advanced Scientic Computing Research and Basic Energy Sciences. Grant Numbers DE-SC0008877 (Austin) and DE-AC02-05CH11231 (LBNL).

  14. Communication overhead on the Intel Paragon, IBM SP2 and Meiko CS-2

    Science.gov (United States)

    Bokhari, Shahid H.

    1995-01-01

    Interprocessor communication overhead is a crucial measure of the power of parallel computing systems-its impact can severely limit the performance of parallel programs. This report presents measurements of communication overhead on three contemporary commercial multicomputer systems: the Intel Paragon, the IBM SP2 and the Meiko CS-2. In each case the time to communicate between processors is presented as a function of message length. The time for global synchronization and memory access is discussed. The performance of these machines in emulating hypercubes and executing random pairwise exchanges is also investigated. It is shown that the interprocessor communication time depends heavily on the specific communication pattern required. These observations contradict the commonly held belief that communication overhead on contemporary machines is independent of the placement of tasks on processors. The information presented in this report permits the evaluation of the efficiency of parallel algorithm implementations against standard baselines.

  15. A performance study of sparse Cholesky factorization on INTEL iPSC/860

    Science.gov (United States)

    Zubair, M.; Ghose, M.

    1992-01-01

    The problem of Cholesky factorization of a sparse matrix has been very well investigated on sequential machines. A number of efficient codes exist for factorizing large unstructured sparse matrices. However, there is a lack of such efficient codes on parallel machines in general, and distributed machines in particular. Some of the issues that are critical to the implementation of sparse Cholesky factorization on a distributed memory parallel machine are ordering, partitioning and mapping, load balancing, and ordering of various tasks within a processor. Here, we focus on the effect of various partitioning schemes on the performance of sparse Cholesky factorization on the Intel iPSC/860. Also, a new partitioning heuristic for structured as well as unstructured sparse matrices is proposed, and its performance is compared with other schemes.

  16. Plasma turbulence calculations on the Intel iPSC/860 (rx) hypercube

    International Nuclear Information System (INIS)

    Lynch, V.E.; Ruiter, J.R.

    1990-01-01

    One approach to improving the real-time efficiency of plasma turbulence calculations is to use a parallel algorithm. A serial algorithm used for plasma turbulence calculations was modified to allocate a radial region in each node. In this way, convolutions at a fixed radius are performed in parallel, and communication is limited to boundary values for each radial region. For a semi-implicity numerical scheme (tridiagonal matrix solver), there is a factor of 3 improvement in efficiency with the Intel iPSC/860 machine using 64 processors over a single-processor Cray-II. For block-tridiagonal matrix cases (fully implicit code), a second parallelization takes place. The Fourier components are distributed in nodes. In each node, the block-tridiagonal matrix is inverted for each of allocated Fourier components. The algorithm for this second case has not yet been optimized. 10 refs., 4 figs

  17. Performance Evaluation of Multithreaded Geant4 Simulations Using an Intel Xeon Phi Cluster

    Directory of Open Access Journals (Sweden)

    P. Schweitzer

    2015-01-01

    Full Text Available The objective of this study is to evaluate the performances of Intel Xeon Phi hardware accelerators for Geant4 simulations, especially for multithreaded applications. We present the complete methodology to guide users for the compilation of their Geant4 applications on Phi processors. Then, we propose series of benchmarks to compare the performance of Xeon CPUs and Phi processors for a Geant4 example dedicated to the simulation of electron dose point kernels, the TestEm12 example. First, we compare a distributed execution of a sequential version of the Geant4 example on both architectures before evaluating the multithreaded version of the Geant4 example. If Phi processors demonstrated their ability to accelerate computing time (till a factor 3.83 when distributing sequential Geant4 simulations, we do not reach the same level of speedup when considering the multithreaded version of the Geant4 example.

  18. Evaluation of the Intel iWarp parallel processor for space flight applications

    Science.gov (United States)

    Hine, Butler P., III; Fong, Terrence W.

    1993-01-01

    The potential of a DARPA-sponsored advanced processor, the Intel iWarp, for use in future SSF Data Management Systems (DMS) upgrades is evaluated through integration into the Ames DMS testbed and applications testing. The iWarp is a distributed, parallel computing system well suited for high performance computing applications such as matrix operations and image processing. The system architecture is modular, supports systolic and message-based computation, and is capable of providing massive computational power in a low-cost, low-power package. As a consequence, the iWarp offers significant potential for advanced space-based computing. This research seeks to determine the iWarp's suitability as a processing device for space missions. In particular, the project focuses on evaluating the ease of integrating the iWarp into the SSF DMS baseline architecture and the iWarp's ability to support computationally stressing applications representative of SSF tasks.

  19. Using Intel Xeon Phi to accelerate the WRF TEMF planetary boundary layer scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen

    2014-05-01

    The Weather Research and Forecasting (WRF) model is designed for numerical weather prediction and atmospheric research. The WRF software infrastructure consists of several components such as dynamic solvers and physics schemes. Numerical models are used to resolve the large-scale flow. However, subgrid-scale parameterizations are for an estimation of small-scale properties (e.g., boundary layer turbulence and convection, clouds, radiation). Those have a significant influence on the resolved scale due to the complex nonlinear nature of the atmosphere. For the cloudy planetary boundary layer (PBL), it is fundamental to parameterize vertical turbulent fluxes and subgrid-scale condensation in a realistic manner. A parameterization based on the Total Energy - Mass Flux (TEMF) that unifies turbulence and moist convection components produces a better result that the other PBL schemes. For that reason, the TEMF scheme is chosen as the PBL scheme we optimized for Intel Many Integrated Core (MIC), which ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our optimization results for TEMF planetary boundary layer scheme. The optimizations that were performed were quite generic in nature. Those optimizations included vectorization of the code to utilize vector units inside each CPU. Furthermore, memory access was improved by scalarizing some of the intermediate arrays. The results show that the optimization improved MIC performance by 14.8x. Furthermore, the optimizations increased CPU performance by 2.6x compared to the original multi-threaded code on quad core Intel Xeon E5-2603 running at 1.8 GHz. Compared to the optimized code running on a single CPU socket the optimized MIC code is 6.2x faster.

  20. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  1. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  2. Optimal selection of TLD chips

    International Nuclear Information System (INIS)

    Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

    1996-01-01

    Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

  3. Acceleration of Monte Carlo simulation of photon migration in complex heterogeneous media using Intel many-integrated core architecture.

    Science.gov (United States)

    Gorshkov, Anton V; Kirillin, Mikhail Yu

    2015-08-01

    Over two decades, the Monte Carlo technique has become a gold standard in simulation of light propagation in turbid media, including biotissues. Technological solutions provide further advances of this technique. The Intel Xeon Phi coprocessor is a new type of accelerator for highly parallel general purpose computing, which allows execution of a wide range of applications without substantial code modification. We present a technical approach of porting our previously developed Monte Carlo (MC) code for simulation of light transport in tissues to the Intel Xeon Phi coprocessor. We show that employing the accelerator allows reducing computational time of MC simulation and obtaining simulation speed-up comparable to GPU. We demonstrate the performance of the developed code for simulation of light transport in the human head and determination of the measurement volume in near-infrared spectroscopy brain sensing.

  4. Performance Evaluation of an Intel Haswell- and Ivy Bridge-Based Supercomputer Using Scientific and Engineering Applications

    Science.gov (United States)

    Saini, Subhash; Hood, Robert T.; Chang, Johnny; Baron, John

    2016-01-01

    We present a performance evaluation conducted on a production supercomputer of the Intel Xeon Processor E5- 2680v3, a twelve-core implementation of the fourth-generation Haswell architecture, and compare it with Intel Xeon Processor E5-2680v2, an Ivy Bridge implementation of the third-generation Sandy Bridge architecture. Several new architectural features have been incorporated in Haswell including improvements in all levels of the memory hierarchy as well as improvements to vector instructions and power management. We critically evaluate these new features of Haswell and compare with Ivy Bridge using several low-level benchmarks including subset of HPCC, HPCG and four full-scale scientific and engineering applications. We also present a model to predict the performance of HPCG and Cart3D within 5%, and Overflow within 10% accuracy.

  5. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    OpenAIRE

    H. Wang; H. Wang; H. Wang; H. Wang; H. Chen; H. Chen; Q. Wu; Q. Wu; J. Lin; X. Chen; X. Xie; R. Wang; R. Wang; X. Tang; Z. Wang

    2017-01-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (code...

  6. Student Intern Ben Freed Competes as Finalist in Intel STS Competition, Three Other Interns Named Semifinalists | Poster

    Science.gov (United States)

    By Ashley DeVine, Staff Writer Werner H. Kirstin (WHK) student intern Ben Freed was one of 40 finalists to compete in the Intel Science Talent Search (STS) in Washington, DC, in March. “It was seven intense days of interacting with amazing judges and incredibly smart and interesting students. We met President Obama, and then the MIT astronomy lab named minor planets after each

  7. Evaluating the transport layer of the ALFA framework for the Intel(®) Xeon Phi(™) Coprocessor

    OpenAIRE

    Santogidis, Aram; Hirstius, Andreas; Lalis, Spyros

    2015-01-01

    The ALFA framework supports the software development of major High Energy Physics experiments. As part of our research effort to optimize the transport layer of ALFA, we focus on profiling its data transfer performance for inter-node communication on the Intel Xeon Phi Coprocessor. In this article we present the collected performance measurements with the related analysis of the results. The optimization opportunities that are discovered, help us to formulate the future plans of enabling high...

  8. Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors

    OpenAIRE

    Hirano, Akihiro; Nakayama, Kenji

    2008-01-01

    This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup ...

  9. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™.

    Science.gov (United States)

    Gomes, Jeremias M; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H

    2015-10-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel ® Xeon Phi ™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP's irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high performance. However, SIMD atomic instructions are not supported. Therefore, we propose a new IWPP algorithm that can take advantage of the supported SIMD instruction set. We also evaluate an alternate storage container (priority queue) to track active elements in the wavefront in an effort to improve the parallel algorithm efficiency. The new IWPP algorithm is evaluated with Morphological Reconstruction and Imfill operations as use cases. Our results show performance improvements of up to 5.63 × on top of the original IWPP due to vectorization. Moreover, the new IWPP achieves speedups of 45.7 × and 1.62 × , respectively, as compared to efficient CPU and GPU implementations.

  10. OpenMP-accelerated SWAT simulation using Intel C and FORTRAN compilers: Development and benchmark

    Science.gov (United States)

    Ki, Seo Jin; Sugimura, Tak; Kim, Albert S.

    2015-02-01

    We developed a practical method to accelerate execution of Soil and Water Assessment Tool (SWAT) using open (free) computational resources. The SWAT source code (rev 622) was recompiled using a non-commercial Intel FORTRAN compiler in Ubuntu 12.04 LTS Linux platform, and newly named iOMP-SWAT in this study. GNU utilities of make, gprof, and diff were used to develop the iOMP-SWAT package, profile memory usage, and check identicalness of parallel and serial simulations. Among 302 SWAT subroutines, the slowest routines were identified using GNU gprof, and later modified using Open Multiple Processing (OpenMP) library in an 8-core shared memory system. In addition, a C wrapping function was used to rapidly set large arrays to zero by cross compiling with the original SWAT FORTRAN package. A universal speedup ratio of 2.3 was achieved using input data sets of a large number of hydrological response units. As we specifically focus on acceleration of a single SWAT run, the use of iOMP-SWAT for parameter calibrations will significantly improve the performance of SWAT optimization.

  11. Optimizing meridional advection of the Advanced Research WRF (ARW) dynamics for Intel Xeon Phi coprocessor

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.-L.

    2015-05-01

    The most widely used community weather forecast and research model in the world is the Weather Research and Forecast (WRF) model. Two distinct varieties of WRF exist. The one we are interested is the Advanced Research WRF (ARW) is an experimental, advanced research version featuring very high resolution. The WRF Nonhydrostatic Mesoscale Model (WRF-NMM) has been designed for forecasting operations. WRF consists of dynamics code and several physics modules. The WRF-ARW core is based on an Eulerian solver for the fully compressible nonhydrostatic equations. In the paper, we optimize a meridional (north-south direction) advection subroutine for Intel Xeon Phi coprocessor. Advection is of the most time consuming routines in the ARW dynamics core. It advances the explicit perturbation horizontal momentum equations by adding in the large-timestep tendency along with the small timestep pressure gradient tendency. We will describe the challenges we met during the development of a high-speed dynamics code subroutine for MIC architecture. Furthermore, lessons learned from the code optimization process will be discussed. The results show that the optimizations improved performance of the original code on Xeon Phi 7120P by a factor of 1.2x.

  12. A comparison of SuperLU solvers on the intel MIC architecture

    Science.gov (United States)

    Tuncel, Mehmet; Duran, Ahmet; Celebi, M. Serdar; Akaydin, Bora; Topkaya, Figen O.

    2016-10-01

    In many science and engineering applications, problems may result in solving a sparse linear system AX=B. For example, SuperLU_MCDT, a linear solver, was used for the large penta-diagonal matrices for 2D problems and hepta-diagonal matrices for 3D problems, coming from the incompressible blood flow simulation (see [1]). It is important to test the status and potential improvements of state-of-the-art solvers on new technologies. In this work, sequential, multithreaded and distributed versions of SuperLU solvers (see [2]) are examined on the Intel Xeon Phi coprocessors using offload programming model at the EURORA cluster of CINECA in Italy. We consider a portfolio of test matrices containing patterned matrices from UFMM ([3]) and randomly located matrices. This architecture can benefit from high parallelism and large vectors. We find that the sequential SuperLU benefited up to 45 % performance improvement from the offload programming depending on the sparse matrix type and the size of transferred and processed data.

  13. Modeling high-temperature superconductors and metallic alloys on the Intel IPSC/860

    Science.gov (United States)

    Geist, G. A.; Peyton, B. W.; Shelton, W. A.; Stocks, G. M.

    Oak Ridge National Laboratory has embarked on several computational Grand Challenges, which require the close cooperation of physicists, mathematicians, and computer scientists. One of these projects is the determination of the material properties of alloys from first principles and, in particular, the electronic structure of high-temperature superconductors. While the present focus of the project is on superconductivity, the approach is general enough to permit study of other properties of metallic alloys such as strength and magnetic properties. This paper describes the progress to date on this project. We include a description of a self-consistent KKR-CPA method, parallelization of the model, and the incorporation of a dynamic load balancing scheme into the algorithm. We also describe the development and performance of a consolidated KKR-CPA code capable of running on CRAYs, workstations, and several parallel computers without source code modification. Performance of this code on the Intel iPSC/860 is also compared to a CRAY 2, CRAY YMP, and several workstations. Finally, some density of state calculations of two perovskite superconductors are given.

  14. Parallel spatial direct numerical simulations on the Intel iPSC/860 hypercube

    Science.gov (United States)

    Joslin, Ronald D.; Zubair, Mohammad

    1993-01-01

    The implementation and performance of a parallel spatial direct numerical simulation (PSDNS) approach on the Intel iPSC/860 hypercube is documented. The direct numerical simulation approach is used to compute spatially evolving disturbances associated with the laminar-to-turbulent transition in boundary-layer flows. The feasibility of using the PSDNS on the hypercube to perform transition studies is examined. The results indicate that the direct numerical simulation approach can effectively be parallelized on a distributed-memory parallel machine. By increasing the number of processors nearly ideal linear speedups are achieved with nonoptimized routines; slower than linear speedups are achieved with optimized (machine dependent library) routines. This slower than linear speedup results because the Fast Fourier Transform (FFT) routine dominates the computational cost and because the routine indicates less than ideal speedups. However with the machine-dependent routines the total computational cost decreases by a factor of 4 to 5 compared with standard FORTRAN routines. The computational cost increases linearly with spanwise wall-normal and streamwise grid refinements. The hypercube with 32 processors was estimated to require approximately twice the amount of Cray supercomputer single processor time to complete a comparable simulation; however it is estimated that a subgrid-scale model which reduces the required number of grid points and becomes a large-eddy simulation (PSLES) would reduce the computational cost and memory requirements by a factor of 10 over the PSDNS. This PSLES implementation would enable transition simulations on the hypercube at a reasonable computational cost.

  15. Efficient irregular wavefront propagation algorithms on Intel® Xeon Phi™

    Science.gov (United States)

    Gomes, Jeremias M.; Teodoro, George; de Melo, Alba; Kong, Jun; Kurc, Tahsin; Saltz, Joel H.

    2016-01-01

    We investigate the execution of the Irregular Wavefront Propagation Pattern (IWPP), a fundamental computing structure used in several image analysis operations, on the Intel® Xeon Phi™ co-processor. An efficient implementation of IWPP on the Xeon Phi is a challenging problem because of IWPP’s irregularity and the use of atomic instructions in the original IWPP algorithm to resolve race conditions. On the Xeon Phi, the use of SIMD and vectorization instructions is critical to attain high performance. However, SIMD atomic instructions are not supported. Therefore, we propose a new IWPP algorithm that can take advantage of the supported SIMD instruction set. We also evaluate an alternate storage container (priority queue) to track active elements in the wavefront in an effort to improve the parallel algorithm efficiency. The new IWPP algorithm is evaluated with Morphological Reconstruction and Imfill operations as use cases. Our results show performance improvements of up to 5.63× on top of the original IWPP due to vectorization. Moreover, the new IWPP achieves speedups of 45.7× and 1.62×, respectively, as compared to efficient CPU and GPU implementations. PMID:27298591

  16. Deployment of the OSIRIS EM-PIC code on the Intel Knights Landing architecture

    Science.gov (United States)

    Fonseca, Ricardo

    2017-10-01

    Electromagnetic particle-in-cell (EM-PIC) codes such as OSIRIS have found widespread use in modelling the highly nonlinear and kinetic processes that occur in several relevant plasma physics scenarios, ranging from astrophysical settings to high-intensity laser plasma interaction. Being computationally intensive, these codes require large scale HPC systems, and a continuous effort in adapting the algorithm to new hardware and computing paradigms. In this work, we report on our efforts on deploying the OSIRIS code on the new Intel Knights Landing (KNL) architecture. Unlike the previous generation (Knights Corner), these boards are standalone systems, and introduce several new features, include the new AVX-512 instructions and on-package MCDRAM. We will focus on the parallelization and vectorization strategies followed, as well as memory management, and present a detailed performance evaluation of code performance in comparison with the CPU code. This work was partially supported by Fundaçã para a Ciência e Tecnologia (FCT), Portugal, through Grant No. PTDC/FIS-PLA/2940/2014.

  17. Plasma Science and Applications at the Intel Science Fair: A Retrospective

    Science.gov (United States)

    Berry, Lee

    2009-11-01

    For the past five years, the Coalition for Plasma Science (CPS) has presented an award for a plasma project at the Intel International Science and Engineering Fair (ISEF). Eligible projects have ranged from grape-based plasma production in a microwave oven to observation of the effects of viscosity in a fluid model of quark-gluon plasma. Most projects have been aimed at applications, including fusion, thrusters, lighting, materials processing, and GPS improvements. However diagnostics (spectroscopy), technology (magnets), and theory (quark-gluon plasmas) have also been represented. All of the CPS award-winning projects so far have been based on experiments, with two awards going to women students and three to men. Since the award was initiated, both the number and quality of plasma projects has increased. The CPS expects this trend to continue, and looks forward to continuing its work with students who are excited about the possibilities of plasma. You too can share this excitement by judging at the 2010 fair in San Jose on May 11-12.

  18. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  19. Implementation of 5-layer thermal diffusion scheme in weather research and forecasting model with Intel Many Integrated Cores

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2014-10-01

    For weather forecasting and research, the Weather Research and Forecasting (WRF) model has been developed, consisting of several components such as dynamic solvers and physical simulation modules. WRF includes several Land- Surface Models (LSMs). The LSMs use atmospheric information, the radiative and precipitation forcing from the surface layer scheme, the radiation scheme, and the microphysics/convective scheme all together with the land's state variables and land-surface properties, to provide heat and moisture fluxes over land and sea-ice points. The WRF 5-layer thermal diffusion simulation is an LSM based on the MM5 5-layer soil temperature model with an energy budget that includes radiation, sensible, and latent heat flux. The WRF LSMs are very suitable for massively parallel computation as there are no interactions among horizontal grid points. The features, efficient parallelization and vectorization essentials, of Intel Many Integrated Core (MIC) architecture allow us to optimize this WRF 5-layer thermal diffusion scheme. In this work, we present the results of the computing performance on this scheme with Intel MIC architecture. Our results show that the MIC-based optimization improved the performance of the first version of multi-threaded code on Xeon Phi 5110P by a factor of 2.1x. Accordingly, the same CPU-based optimizations improved the performance on Intel Xeon E5- 2603 by a factor of 1.6x as compared to the first version of multi-threaded code.

  20. Evaluation of the Intel Xeon Phi 7120 and NVIDIA K80 as accelerators for two-dimensional panel codes.

    Science.gov (United States)

    Einkemmer, Lukas

    2017-01-01

    To optimize the geometry of airfoils for a specific application is an important engineering problem. In this context genetic algorithms have enjoyed some success as they are able to explore the search space without getting stuck in local optima. However, these algorithms require the computation of aerodynamic properties for a significant number of airfoil geometries. Consequently, for low-speed aerodynamics, panel methods are most often used as the inner solver. In this paper we evaluate the performance of such an optimization algorithm on modern accelerators (more specifically, the Intel Xeon Phi 7120 and the NVIDIA K80). For that purpose, we have implemented an optimized version of the algorithm on the CPU and Xeon Phi (based on OpenMP, vectorization, and the Intel MKL library) and on the GPU (based on CUDA and the MAGMA library). We present timing results for all codes and discuss the similarities and differences between the three implementations. Overall, we observe a speedup of approximately 2.5 for adding an Intel Xeon Phi 7120 to a dual socket workstation and a speedup between 3.4 and 3.8 for adding a NVIDIA K80 to a dual socket workstation.

  1. Using Intel's Knight Landing Processor to Accelerate Global Nested Air Quality Prediction Modeling System (GNAQPMS) Model

    Science.gov (United States)

    Wang, H.; Chen, H.; Chen, X.; Wu, Q.; Wang, Z.

    2016-12-01

    The Global Nested Air Quality Prediction Modeling System for Hg (GNAQPMS-Hg) is a global chemical transport model coupled Hg transport module to investigate the mercury pollution. In this study, we present our work of transplanting the GNAQPMS model on Intel Xeon Phi processor, Knights Landing (KNL) to accelerate the model. KNL is the second-generation product adopting Many Integrated Core Architecture (MIC) architecture. Compared with the first generation Knight Corner (KNC), KNL has more new hardware features, that it can be used as unique processor as well as coprocessor with other CPU. According to the Vtune tool, the high overhead modules in GNAQPMS model have been addressed, including CBMZ gas chemistry, advection and convection module, and wet deposition module. These high overhead modules were accelerated by optimizing code and using new techniques of KNL. The following optimized measures was done: 1) Changing the pure MPI parallel mode to hybrid parallel mode with MPI and OpenMP; 2.Vectorizing the code to using the 512-bit wide vector computation unit. 3. Reducing unnecessary memory access and calculation. 4. Reducing Thread Local Storage (TLS) for common variables with each OpenMP thread in CBMZ. 5. Changing the way of global communication from files writing and reading to MPI functions. After optimization, the performance of GNAQPMS is greatly increased both on CPU and KNL platform, the single-node test showed that optimized version has 2.6x speedup on two sockets CPU platform and 3.3x speedup on one socket KNL platform compared with the baseline version code, which means the KNL has 1.29x speedup when compared with 2 sockets CPU platform.

  2. Navier-Stokes Aerodynamic Simulation of the V-22 Osprey on the Intel Paragon MPP

    Science.gov (United States)

    Vadyak, Joseph; Shrewsbury, George E.; Narramore, Jim C.; Montry, Gary; Holst, Terry; Kwak, Dochan (Technical Monitor)

    1995-01-01

    The paper will describe the Development of a general three-dimensional multiple grid zone Navier-Stokes flowfield simulation program (ENS3D-MPP) designed for efficient execution on the Intel Paragon Massively Parallel Processor (MPP) supercomputer, and the subsequent application of this method to the prediction of the viscous flowfield about the V-22 Osprey tiltrotor vehicle. The flowfield simulation code solves the thin Layer or full Navier-Stoke's equation - for viscous flow modeling, or the Euler equations for inviscid flow modeling on a structured multi-zone mesh. In the present paper only viscous simulations will be shown. The governing difference equations are solved using a time marching implicit approximate factorization method with either TVD upwind or central differencing used for the convective terms and central differencing used for the viscous diffusion terms. Steady state or Lime accurate solutions can be calculated. The present paper will focus on steady state applications, although time accurate solution analysis is the ultimate goal of this effort. Laminar viscosity is calculated using Sutherland's law and the Baldwin-Lomax two layer algebraic turbulence model is used to compute the eddy viscosity. The Simulation method uses an arbitrary block, curvilinear grid topology. An automatic grid adaption scheme is incorporated which concentrates grid points in high density gradient regions. A variety of user-specified boundary conditions are available. This paper will present the application of the scalable and superscalable versions to the steady state viscous flow analysis of the V-22 Osprey using a multiple zone global mesh. The mesh consists of a series of sheared cartesian grid blocks with polar grids embedded within to better simulate the wing tip mounted nacelle. MPP solutions will be shown in comparison to equivalent Cray C-90 results and also in comparison to experimental data. Discussions on meshing considerations, wall clock execution time

  3. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  4. Amdahl 470 Chip Package

    CERN Multimedia

    1975-01-01

    In the late 70s the larger IBM computers were water cooled. Amdahl, an IBM competitor, invented an air cooling technology for it's computers. His company worked hard, developing a computer that was faster and less expensive than the IBM System/360 mainframe computer systems. This object contains an actual Amdahl series 470 computer logic chip with an air cooling device mounted on top. The package leads and cooling tower are gold-plated.

  5. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  6. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    Science.gov (United States)

    Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junmin; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

    2017-08-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC), KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1) updating the pure Message Passing Interface (MPI) parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2) fully employing the 512 bit wide vector processing units (VPUs) on the KNL platform; (3) reducing unnecessary memory access to improve cache efficiency; (4) reducing the thread local storage (TLS) in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5) changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined performance and energy

  7. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS on Intel Xeon Phi processors

    Directory of Open Access Journals (Sweden)

    H. Wang

    2017-08-01

    Full Text Available The Global Nested Air Quality Prediction Modeling System (GNAQPMS is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS, which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL. Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC, KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1 updating the pure Message Passing Interface (MPI parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2 fully employing the 512 bit wide vector processing units (VPUs on the KNL platform; (3 reducing unnecessary memory access to improve cache efficiency; (4 reducing the thread local storage (TLS in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5 changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined

  8. Emmarcar el debat: Lliure expressió contra propietat intel·lectual, els propers cinquanta anys

    Directory of Open Access Journals (Sweden)

    Eben Moglen

    2007-02-01

    Full Text Available

    El Prof. Moglen explica i analitza, des d'una perspectiva històrica, la profunda revolució social i legal que resulta de la tecnologia digital quan aquesta s'aplica a tots els camps: programari, música i tot tipus de creacions. En concret, explica la manera en què la tecnologia digital està forçant una modificació substancial (desaparició dels sistemes de propietat intel·lectual i fa prediccions per al futur pròxim dels mercats de la PI.

  9. Hot Chips and Hot Interconnects for High End Computing Systems

    Science.gov (United States)

    Saini, Subhash

    2005-01-01

    I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

  10. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  11. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  12. Efficient sparse matrix-matrix multiplication for computing periodic responses by shooting method on Intel Xeon Phi

    Science.gov (United States)

    Stoykov, S.; Atanassov, E.; Margenov, S.

    2016-10-01

    Many of the scientific applications involve sparse or dense matrix operations, such as solving linear systems, matrix-matrix products, eigensolvers, etc. In what concerns structural nonlinear dynamics, the computations of periodic responses and the determination of stability of the solution are of primary interest. Shooting method iswidely used for obtaining periodic responses of nonlinear systems. The method involves simultaneously operations with sparse and dense matrices. One of the computationally expensive operations in the method is multiplication of sparse by dense matrices. In the current work, a new algorithm for sparse matrix by dense matrix products is presented. The algorithm takes into account the structure of the sparse matrix, which is obtained by space discretization of the nonlinear Mindlin's plate equation of motion by the finite element method. The algorithm is developed to use the vector engine of Intel Xeon Phi coprocessors. It is compared with the standard sparse matrix by dense matrix algorithm and the one developed by Intel MKL and it is shown that by considering the properties of the sparse matrix better algorithms can be developed.

  13. Time-efficient simulations of tight-binding electronic structures with Intel Xeon PhiTM many-core processors

    Science.gov (United States)

    Ryu, Hoon; Jeong, Yosang; Kang, Ji-Hoon; Cho, Kyu Nam

    2016-12-01

    Modelling of multi-million atomic semiconductor structures is important as it not only predicts properties of physically realizable novel materials, but can accelerate advanced device designs. This work elaborates a new Technology-Computer-Aided-Design (TCAD) tool for nanoelectronics modelling, which uses a sp3d5s∗ tight-binding approach to describe multi-million atomic structures, and simulate electronic structures with high performance computing (HPC), including atomic effects such as alloy and dopant disorders. Being named as Quantum simulation tool for Advanced Nanoscale Devices (Q-AND), the tool shows nice scalability on traditional multi-core HPC clusters implying the strong capability of large-scale electronic structure simulations, particularly with remarkable performance enhancement on latest clusters of Intel Xeon PhiTM coprocessors. A review of the recent modelling study conducted to understand an experimental work of highly phosphorus-doped silicon nanowires, is presented to demonstrate the utility of Q-AND. Having been developed via Intel Parallel Computing Center project, Q-AND will be open to public to establish a sound framework of nanoelectronics modelling with advanced HPC clusters of a many-core base. With details of the development methodology and exemplary study of dopant electronics, this work will present a practical guideline for TCAD development to researchers in the field of computational nanoelectronics.

  14. A parallel implementation of particle tracking with space charge effects on an INTEL iPSC/860

    International Nuclear Information System (INIS)

    Chang, L.; Bourianoff, G.; Cole, B.; Machida, S.

    1993-05-01

    Particle-tracking simulation is one of the scientific applications that is well-suited to parallel computations. At the Superconducting Super Collider, it has been theoretically and empirically demonstrated that particle tracking on a designed lattice can achieve very high parallel efficiency on a MIMD Intel iPSC/860 machine. The key to such success is the realization that the particles can be tracked independently without considering their interaction. The perfectly parallel nature of particle tracking is broken if the interaction effects between particles are included. The space charge introduces an electromagnetic force that will affect the motion of tracked particles in 3-D space. For accurate modeling of the beam dynamics with space charge effects, one needs to solve three-dimensional Maxwell field equations, usually by a particle-in-cell (PIC) algorithm. This will require each particle to communicate with its neighbor grids to compute the momentum changes at each time step. It is expected that the 3-D PIC method will degrade parallel efficiency of particle-tracking implementation on any parallel computer. In this paper, we describe an efficient scheme for implementing particle tracking with space charge effects on an INTEL iPSC/860 machine. Experimental results show that a parallel efficiency of 75% can be obtained

  15. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  16. Reflective memory recorder upgrade: an opportunity to benchmark PowerPC and Intel architectures for real time

    Science.gov (United States)

    Abuter, Roberto; Tischer, Helmut; Frahm, Robert

    2014-07-01

    Several high frequency loops are required to run the VLTI (Very Large Telescope Interferometer) 2, e.g. for fringe tracking11, 5, angle tracking, vibration cancellation, data capture. All these loops rely on low latency real time computers based on the VME bus, Motorola PowerPC14 hardware architecture. In this context, one highly demanding application in terms of cycle time, latency and data transfer volume is the VLTI centralized recording facility, so called, RMN recorder1 (Reflective Memory Recorder). This application captures and transfers data flowing through the distributed memory of the system in real time. Some of the VLTI data producers are running with frequencies up to 8 KHz. With the evolution from first generation instruments like MIDI3, PRIMA5, and AMBER4 which use one or two baselines, to second generation instruments like MATISSE10 and GRAVITY9 which will use all six baselines simultaneously, the quantity of signals has increased by, at least, a factor of six. This has led to a significant overload of the RMN recorder1 which has reached the natural limits imposed by the underlying hardware. At the same time, new, more powerful computers, based on the Intel multicore families of CPUs and PCI buses have become available. With the purpose of improving the performance of the RMN recorder1 application and in order to make it capable of coping with the demands of the new generation instruments, a slightly modified implementation has been developed and integrated into an Intel based multicore computer15 running the VxWorks17 real time operating system. The core of the application is based on the standard VLT software framework for instruments13. The real time task reads from the reflective memory using the onboard DMA access12 and captured data is transferred to the outside world via a TCP socket on a dedicated Ethernet connection. The diversity of the software and hardware that are involved makes this application suitable as a benchmarking platform. A

  17. Intel Many Integrated Core (MIC) architecture optimization strategies for a memory-bound Weather Research and Forecasting (WRF) Goddard microphysics scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Goddard cloud microphysics scheme is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The WRF is a widely used weather prediction system in the world. It development is a done in collaborative around the globe. The Goddard microphysics scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Goddard scheme incorporates a large number of improvements. Thus, we have optimized the code of this important part of WRF. In this paper, we present our results of optimizing the Goddard microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The Intel MIC is capable of executing a full operating system and entire programs rather than just kernels as the GPU do. The MIC coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The results show that the optimizations improved performance of the original code on Xeon Phi 7120P by a factor of 4.7x. Furthermore, the same optimizations improved performance on a dual socket Intel Xeon E5-2670 system by a factor of 2.8x compared to the original code.

  18. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  19. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  20. Single chip camera active pixel sensor

    Science.gov (United States)

    Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

    2003-01-01

    A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

  1. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  2. Parallel computation for biological sequence comparison: comparing a portable model to the native model for the Intel Hypercube.

    Science.gov (United States)

    Nadkarni, P M; Miller, P L

    1991-01-01

    A parallel program for inter-database sequence comparison was developed on the Intel Hypercube using two models of parallel programming. One version was built using machine-specific Hypercube parallel programming commands. The other version was built using Linda, a machine-independent parallel programming language. The two versions of the program provide a case study comparing these two approaches to parallelization in an important biological application area. Benchmark tests with both programs gave comparable results with a small number of processors. As the number of processors was increased, the Linda version was somewhat less efficient. The Linda version was also run without change on Network Linda, a virtual parallel machine running on a network of desktop workstations.

  3. La responsabilitat davant la intel·ligència artificial en el comerç electrònic

    OpenAIRE

    Martín i Palomas, Elisabet

    2015-01-01

    Es planteja en aquesta tesi l'efecte produït sobre la responsabilitat derivada de les accions realitzades autònomament per sistemes dotats d'intel·ligència artificial, sense la participació directa de cap ésser humà, en els temes més directament relacionats amb el comerç electrònic. Per a això s'analitzen les activitats realitzades per algunes de les principals empreses internacionals de comerç electrònic, com el grup nord-americà eBay o el grup xinès Alibaba. Després de desenvolupar els prin...

  4. Evaluating the networking characteristics of the Cray XC-40 Intel Knights Landing-based Cori supercomputer at NERSC

    Energy Technology Data Exchange (ETDEWEB)

    Doerfler, Douglas [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Austin, Brian [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Cook, Brandon [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Deslippe, Jack [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Kandalla, Krishna [Cray Inc, Bloomington, MN (United States); Mendygral, Peter [Cray Inc, Bloomington, MN (United States)

    2017-09-12

    There are many potential issues associated with deploying the Intel Xeon Phi™ (code named Knights Landing [KNL]) manycore processor in a large-scale supercomputer. One in particular is the ability to fully utilize the high-speed communications network, given that the serial performance of a Xeon Phi TM core is a fraction of a Xeon®core. In this paper, we take a look at the trade-offs associated with allocating enough cores to fully utilize the Aries high-speed network versus cores dedicated to computation, e.g., the trade-off between MPI and OpenMP. In addition, we evaluate new features of Cray MPI in support of KNL, such as internode optimizations. We also evaluate one-sided programming models such as Unified Parallel C. We quantify the impact of the above trade-offs and features using a suite of National Energy Research Scientific Computing Center applications.

  5. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2016-01-01

    On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range.......On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range....

  6. Les multituds intel·ligents com a generadores de dades massives : la intel·ligència col·lectiva al servei de la innovació social

    Directory of Open Access Journals (Sweden)

    Sanz, Sandra

    2015-06-01

    Full Text Available Les últimes dècades es registra un increment de mobilitzacions socials organitzades, intervingudes, narrades i coordinades a través de les TIC. Són mostra de multituds intel·ligents (smart mobs que s'aprofiten dels nous mitjans de comunicació per organitzar-se. Tant pel nombre de missatges intercanviats i generats com per les pròpies interaccions generades, aquestes multituds intel·ligents es converteixen en objecte de les dades massives. La seva anàlisi a partir de les possibilitats que brinda l'enginyeria de dades pot contribuir a detectar idees construïdes com també sabers compartits fruit de la intel·ligència col·lectiva. Aquest fet afavoriria la reutilització d'aquesta informació per incrementar el coneixement del col·lectiu i contribuir al desenvolupament de la innovació social. És per això que en aquest article s'assenyalen els interrogants i les limitacions que encara presenten aquestes anàlisis i es posa en relleu la necessitat d'aprofundir en el desenvolupament de nous mètodes i tècniques d'anàlisi.En las últimas décadas se registra un incremento de movilizaciones sociales organizadas, mediadas, narradas y coordinadas a través de TICs. Son muestra de smart mobs o multitudes inteligentes que se aprovechan de los nuevos medios de comunicación para organizarse. Tanto por el número de mensajes intercambiados y generados como por las propias interacciones generadas, estas multitudes inteligentes se convierten en objeto del big data. Su análisis a partir de las posibilidades que brinda la ingeniería de datos puede contribuir a detectar ideas construidas así como saberes compartidos fruto de la inteligencia colectiva. Ello favorecería la reutilización de esta información para incrementar el conocimiento del colectivo y contribuir al desarrollo de la innovación social. Es por ello que en este artículo se señalan los interrogantes y limitaciones que todavía presentan estos análisis y se pone de relieve la

  7. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  8. Atom chip gravimeter

    Science.gov (United States)

    Schubert, Christian; Abend, Sven; Gebbe, Martina; Gersemann, Matthias; Ahlers, Holger; Müntinga, Hauke; Matthias, Jonas; Sahelgozin, Maral; Herr, Waldemar; Lämmerzahl, Claus; Ertmer, Wolfgang; Rasel, Ernst

    2016-04-01

    Atom interferometry has developed into a tool for measuring rotations [1], accelerations [2], and testing fundamental physics [3]. Gravimeters based on laser cooled atoms demonstrated residual uncertainties of few microgal [2,4] and were simplified for field applications [5]. Atomic gravimeters rely on the interference of matter waves which are coherently manipulated by laser light fields. The latter can be interpreted as rulers to which the position of the atoms is compared. At three points in time separated by a free evolution, the light fields are pulsed onto the atoms. First, a coherent superposition of two momentum states is produced, then the momentum is inverted, and finally the two trajectories are recombined. Depending on the acceleration the atoms experienced, the number of atoms detected in the output ports will change. Consequently, the acceleration can be determined from the output signal. The laser cooled atoms with microkelvin temperatures used in state-of-the-art gravimeters impose limits on the accuracy [4]. Therefore, ultra-cold atoms generated by Bose-Einstein condensation and delta-kick collimation [6,7] are expected to be the key for further improvements. These sources suffered from a low flux implying an incompatible noise floor, but a competitive performance was demonstrated recently with atom chips [8]. In the compact and robust setup constructed for operation in the drop tower [6] we demonstrated all steps necessary for an atom chip gravimeter with Bose-Einstein condensates in a ground based operation. We will discuss the principle of operation, the current performance, and the perspectives to supersede the state of the art. The authors thank the QUANTUS cooperation for contributions to the drop tower project in the earlier stages. This work is supported by the German Space Agency (DLR) with funds provided by the Federal Ministry for Economic Affairs and Energy (BMWi) due to an enactment of the German Bundestag under grant numbers DLR 50WM

  9. Experiment list: SRX214075 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  10. Experiment list: SRX122523 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  11. Experiment list: SRX122414 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  12. Experiment list: SRX214071 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2=

  13. Experiment list: SRX214086 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

  14. Experiment list: SRX122485 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100

  15. Experiment list: SRX122521 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  16. Experiment list: SRX122417 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  17. Experiment list: SRX122520 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  18. Experiment list: SRX122413 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  19. Experiment list: SRX122412 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  20. Experiment list: SRX122406 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http:/

  1. Experiment list: SRX122415 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  2. Experiment list: SRX214074 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ge=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  3. Experiment list: SRX214072 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  4. Experiment list: SRX214067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available fferentiated || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacture...r 1=Santa Cruz || chip antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.bioscien

  5. Experiment list: SRX122416 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  6. Experiment list: SRX122565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

  7. OpenMP GNU and Intel Fortran programs for solving the time-dependent Gross-Pitaevskii equation

    Science.gov (United States)

    Young-S., Luis E.; Muruganandam, Paulsamy; Adhikari, Sadhan K.; Lončar, Vladimir; Vudragović, Dušan; Balaž, Antun

    2017-11-01

    We present Open Multi-Processing (OpenMP) version of Fortran 90 programs for solving the Gross-Pitaevskii (GP) equation for a Bose-Einstein condensate in one, two, and three spatial dimensions, optimized for use with GNU and Intel compilers. We use the split-step Crank-Nicolson algorithm for imaginary- and real-time propagation, which enables efficient calculation of stationary and non-stationary solutions, respectively. The present OpenMP programs are designed for computers with multi-core processors and optimized for compiling with both commercially-licensed Intel Fortran and popular free open-source GNU Fortran compiler. The programs are easy to use and are elaborated with helpful comments for the users. All input parameters are listed at the beginning of each program. Different output files provide physical quantities such as energy, chemical potential, root-mean-square sizes, densities, etc. We also present speedup test results for new versions of the programs. Program files doi:http://dx.doi.org/10.17632/y8zk3jgn84.2 Licensing provisions: Apache License 2.0 Programming language: OpenMP GNU and Intel Fortran 90. Computer: Any multi-core personal computer or workstation with the appropriate OpenMP-capable Fortran compiler installed. Number of processors used: All available CPU cores on the executing computer. Journal reference of previous version: Comput. Phys. Commun. 180 (2009) 1888; ibid.204 (2016) 209. Does the new version supersede the previous version?: Not completely. It does supersede previous Fortran programs from both references above, but not OpenMP C programs from Comput. Phys. Commun. 204 (2016) 209. Nature of problem: The present Open Multi-Processing (OpenMP) Fortran programs, optimized for use with commercially-licensed Intel Fortran and free open-source GNU Fortran compilers, solve the time-dependent nonlinear partial differential (GP) equation for a trapped Bose-Einstein condensate in one (1d), two (2d), and three (3d) spatial dimensions for

  8. Chip compacting press; Jido kirikuzu asshukuki

    Energy Technology Data Exchange (ETDEWEB)

    Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

    1998-08-15

    The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

  9. Evaluation of the Intel Xeon Phi Co-processor to accelerate the sensitivity map calculation for PET imaging

    Science.gov (United States)

    Dey, T.; Rodrigue, P.

    2015-07-01

    We aim to evaluate the Intel Xeon Phi coprocessor for acceleration of 3D Positron Emission Tomography (PET) image reconstruction. We focus on the sensitivity map calculation as one computational intensive part of PET image reconstruction, since it is a promising candidate for acceleration with the Many Integrated Core (MIC) architecture of the Xeon Phi. The computation of the voxels in the field of view (FoV) can be done in parallel and the 103 to 104 samples needed to calculate the detection probability of each voxel can take advantage of vectorization. We use the ray tracing kernels of the Embree project to calculate the hit points of the sample rays with the detector and in a second step the sum of the radiological path taking into account attenuation is determined. The core components are implemented using the Intel single instruction multiple data compiler (ISPC) to enable a portable implementation showing efficient vectorization either on the Xeon Phi and the Host platform. On the Xeon Phi, the calculation of the radiological path is also implemented in hardware specific intrinsic instructions (so-called `intrinsics') to allow manually-optimized vectorization. For parallelization either OpenMP and ISPC tasking (based on pthreads) are evaluated.Our implementation achieved a scalability factor of 0.90 on the Xeon Phi coprocessor (model 5110P) with 60 cores at 1 GHz. Only minor differences were found between parallelization with OpenMP and the ISPC tasking feature. The implementation using intrinsics was found to be about 12% faster than the portable ISPC version. With this version, a speedup of 1.43 was achieved on the Xeon Phi coprocessor compared to the host system (HP SL250s Gen8) equipped with two Xeon (E5-2670) CPUs, with 8 cores at 2.6 to 3.3 GHz each. Using a second Xeon Phi card the speedup could be further increased to 2.77. No significant differences were found between the results of the different Xeon Phi and the Host implementations. The examination

  10. Evaluation of the Intel Xeon Phi Co-processor to accelerate the sensitivity map calculation for PET imaging

    International Nuclear Information System (INIS)

    Dey, T.; Rodrigue, P.

    2015-01-01

    We aim to evaluate the Intel Xeon Phi coprocessor for acceleration of 3D Positron Emission Tomography (PET) image reconstruction. We focus on the sensitivity map calculation as one computational intensive part of PET image reconstruction, since it is a promising candidate for acceleration with the Many Integrated Core (MIC) architecture of the Xeon Phi. The computation of the voxels in the field of view (FoV) can be done in parallel and the 10 3 to 10 4 samples needed to calculate the detection probability of each voxel can take advantage of vectorization. We use the ray tracing kernels of the Embree project to calculate the hit points of the sample rays with the detector and in a second step the sum of the radiological path taking into account attenuation is determined. The core components are implemented using the Intel single instruction multiple data compiler (ISPC) to enable a portable implementation showing efficient vectorization either on the Xeon Phi and the Host platform. On the Xeon Phi, the calculation of the radiological path is also implemented in hardware specific intrinsic instructions (so-called 'intrinsics') to allow manually-optimized vectorization. For parallelization either OpenMP and ISPC tasking (based on pthreads) are evaluated.Our implementation achieved a scalability factor of 0.90 on the Xeon Phi coprocessor (model 5110P) with 60 cores at 1 GHz. Only minor differences were found between parallelization with OpenMP and the ISPC tasking feature. The implementation using intrinsics was found to be about 12% faster than the portable ISPC version. With this version, a speedup of 1.43 was achieved on the Xeon Phi coprocessor compared to the host system (HP SL250s Gen8) equipped with two Xeon (E5-2670) CPUs, with 8 cores at 2.6 to 3.3 GHz each. Using a second Xeon Phi card the speedup could be further increased to 2.77. No significant differences were found between the results of the different Xeon Phi and the Host implementations. The

  11. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  12. STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

    Directory of Open Access Journals (Sweden)

    Ireneusz Zagórski

    2016-12-01

    Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

  13. CMOS foveal image sensor chip

    Science.gov (United States)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  14. An efficient MPI/OpenMP parallelization of the Hartree–Fock–Roothaan method for the first generation of Intel® Xeon Phi™ processor architecture

    International Nuclear Information System (INIS)

    Mironov, Vladimir; Moskovsky, Alexander; D’Mello, Michael; Alexeev, Yuri

    2017-01-01

    The Hartree-Fock (HF) method in the quantum chemistry package GAMESS represents one of the most irregular algorithms in computation today. Major steps in the calculation are the irregular computation of electron repulsion integrals (ERIs) and the building of the Fock matrix. These are the central components of the main Self Consistent Field (SCF) loop, the key hotspot in Electronic Structure (ES) codes. By threading the MPI ranks in the official release of the GAMESS code, we not only speed up the main SCF loop (4x to 6x for large systems), but also achieve a significant (>2x) reduction in the overall memory footprint. These improvements are a direct consequence of memory access optimizations within the MPI ranks. We benchmark our implementation against the official release of the GAMESS code on the Intel R Xeon PhiTM supercomputer. Here, scaling numbers are reported on up to 7,680 cores on Intel Xeon Phi coprocessors.

  15. Experience with low-power x86 processors (Atom) for HEP usage. An initial analysis of the Intel® dual core Atom™ N330 processor

    CERN Document Server

    Balazs, G; Nowak, A; CERN. Geneva. IT Department

    2009-01-01

    In this paper we compare a system based on an Intel Atom N330 low-power processor to a modern Intel Xeon® dual-socket server using CERN IT’s standard criteria for comparing price-performance and performance per watt. The Xeon server corresponds to what is typically acquired as servers in the LHC Computing Grid. The comparisons used public pricing information from November 2008. After the introduction in section 1, section 2 describes the hardware and software setup. In section 3 we describe the power measurements we did and in section 4 we discuss the throughput performance results. In section 5 we summarize our initial conclusions. We then go on to describe our long term vision and possible future scenarios for using such low-power processors, and finally we list interesting development directions.

  16. Space division multiplexing chip-to-chip quantum key distribution

    DEFF Research Database (Denmark)

    Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum...

  17. Influence of passivation process on chip performance

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; Schmitz, Jurriaan

    2009-01-01

    In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition

  18. ELT-scale Adaptive Optics real-time control with thes Intel Xeon Phi Many Integrated Core Architecture

    Science.gov (United States)

    Jenkins, David R.; Basden, Alastair; Myers, Richard M.

    2018-05-01

    We propose a solution to the increased computational demands of Extremely Large Telescope (ELT) scale adaptive optics (AO) real-time control with the Intel Xeon Phi Knights Landing (KNL) Many Integrated Core (MIC) Architecture. The computational demands of an AO real-time controller (RTC) scale with the fourth power of telescope diameter and so the next generation ELTs require orders of magnitude more processing power for the RTC pipeline than existing systems. The Xeon Phi contains a large number (≥64) of low power x86 CPU cores and high bandwidth memory integrated into a single socketed server CPU package. The increased parallelism and memory bandwidth are crucial to providing the performance for reconstructing wavefronts with the required precision for ELT scale AO. Here, we demonstrate that the Xeon Phi KNL is capable of performing ELT scale single conjugate AO real-time control computation at over 1.0kHz with less than 20μs RMS jitter. We have also shown that with a wavefront sensor camera attached the KNL can process the real-time control loop at up to 966Hz, the maximum frame-rate of the camera, with jitter remaining below 20μs RMS. Future studies will involve exploring the use of a cluster of Xeon Phis for the real-time control of the MCAO and MOAO regimes of AO. We find that the Xeon Phi is highly suitable for ELT AO real time control.

  19. Heat dissipation for the Intel Core i5 processor using multiwalled carbon-nanotube-based ethylene glycol

    International Nuclear Information System (INIS)

    Thang, Bui Hung; Trinh, Pham Van; Quang, Le Dinh; Khoi, Phan Hong; Minh, Phan Ngoc; Huong, Nguyen Thi

    2014-01-01

    Carbon nanotubes (CNTs) are some of the most valuable materials with high thermal conductivity. The thermal conductivity of individual multiwalled carbon nanotubes (MWCNTs) grown by using chemical vapor deposition is 600 ± 100 Wm -1 K -1 compared with the thermal conductivity 419 Wm -1 K -1 of Ag. Carbon-nanotube-based liquids - a new class of nanomaterials, have shown many interesting properties and distinctive features offering potential in heat dissipation applications for electronic devices, such as computer microprocessor, high power LED, etc. In this work, a multiwalled carbon-nanotube-based liquid was made of well-dispersed hydroxyl-functional multiwalled carbon nanotubes (MWCNT-OH) in ethylene glycol (EG)/distilled water (DW) solutions by using Tween-80 surfactant and an ultrasonication method. The concentration of MWCNT-OH in EG/DW solutions ranged from 0.1 to 1.2 gram/liter. The dispersion of the MWCNT-OH-based EG/DW solutions was evaluated by using a Zeta-Sizer analyzer. The MWCNT-OH-based EG/DW solutions were used as coolants in the liquid cooling system for the Intel Core i5 processor. The thermal dissipation efficiency and the thermal response of the system were evaluated by directly measuring the temperature of the micro-processor using the Core Temp software and the temperature sensors built inside the micro-processor. The results confirmed the advantages of CNTs in thermal dissipation systems for computer processors and other high-power electronic devices.

  20. Quantum Chemical Calculations Using Accelerators: Migrating Matrix Operations to the NVIDIA Kepler GPU and the Intel Xeon Phi.

    Science.gov (United States)

    Leang, Sarom S; Rendell, Alistair P; Gordon, Mark S

    2014-03-11

    Increasingly, modern computer systems comprise a multicore general-purpose processor augmented with a number of special purpose devices or accelerators connected via an external interface such as a PCI bus. The NVIDIA Kepler Graphical Processing Unit (GPU) and the Intel Phi are two examples of such accelerators. Accelerators offer peak performances that can be well above those of the host processor. How to exploit this heterogeneous environment for legacy application codes is not, however, straightforward. This paper considers how matrix operations in typical quantum chemical calculations can be migrated to the GPU and Phi systems. Double precision general matrix multiply operations are endemic in electronic structure calculations, especially methods that include electron correlation, such as density functional theory, second order perturbation theory, and coupled cluster theory. The use of approaches that automatically determine whether to use the host or an accelerator, based on problem size, is explored, with computations that are occurring on the accelerator and/or the host. For data-transfers over PCI-e, the GPU provides the best overall performance for data sizes up to 4096 MB with consistent upload and download rates between 5-5.6 GB/s and 5.4-6.3 GB/s, respectively. The GPU outperforms the Phi for both square and nonsquare matrix multiplications.

  1. Stereoscopic-3D display design: a new paradigm with Intel Adaptive Stable Image Technology [IA-SIT

    Science.gov (United States)

    Jain, Sunil

    2012-03-01

    Stereoscopic-3D (S3D) proliferation on personal computers (PC) is mired by several technical and business challenges: a) viewing discomfort due to cross-talk amongst stereo images; b) high system cost; and c) restricted content availability. Users expect S3D visual quality to be better than, or at least equal to, what they are used to enjoying on 2D in terms of resolution, pixel density, color, and interactivity. Intel Adaptive Stable Image Technology (IA-SIT) is a foundational technology, successfully developed to resolve S3D system design challenges and deliver high quality 3D visualization at PC price points. Optimizations in display driver, panel timing firmware, backlight hardware, eyewear optical stack, and synch mechanism combined can help accomplish this goal. Agnostic to refresh rate, IA-SIT will scale with shrinking of display transistors and improvements in liquid crystal and LED materials. Industry could profusely benefit from the following calls to action:- 1) Adopt 'IA-SIT S3D Mode' in panel specs (via VESA) to help panel makers monetize S3D; 2) Adopt 'IA-SIT Eyewear Universal Optical Stack' and algorithm (via CEA) to help PC peripheral makers develop stylish glasses; 3) Adopt 'IA-SIT Real Time Profile' for sub-100uS latency control (via BT Sig) to extend BT into S3D; and 4) Adopt 'IA-SIT Architecture' for Monitors and TVs to monetize via PC attach.

  2. Initial results on computational performance of Intel Many Integrated Core (MIC) architecture: implementation of the Weather and Research Forecasting (WRF) Purdue-Lin microphysics scheme

    Science.gov (United States)

    Mielikainen, Jarno; Huang, Bormin; Huang, Allen H.

    2014-10-01

    Purdue-Lin scheme is a relatively sophisticated microphysics scheme in the Weather Research and Forecasting (WRF) model. The scheme includes six classes of hydro meteors: water vapor, cloud water, raid, cloud ice, snow and graupel. The scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. In this paper, we accelerate the Purdue Lin scheme using Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi is a high performance coprocessor consists of up to 61 cores. The Xeon Phi is connected to a CPU via the PCI Express (PICe) bus. In this paper, we will discuss in detail the code optimization issues encountered while tuning the Purdue-Lin microphysics Fortran code for Xeon Phi. In particularly, getting a good performance required utilizing multiple cores, the wide vector operations and make efficient use of memory. The results show that the optimizations improved performance of the original code on Xeon Phi 5110P by a factor of 4.2x. Furthermore, the same optimizations improved performance on Intel Xeon E5-2603 CPU by a factor of 1.2x compared to the original code.

  3. Ultracold atoms on atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Hofferberth, S.; Haller, E.

    2005-01-01

    Miniaturized potentials near the surface of atom chips can be used as flexible and versatile tools for the manipulation of ultracold atoms on a microscale. The full scope of possibilities is only accessible if atom-surface distances can be reduced to microns. We discuss experiments in this regime...

  4. FERMI multi-chip module

    CERN Multimedia

    This FERMI multi-chip module contains five million transistors. 25 000 of these modules will handle the flood of information through parts of the ATLAS and CMS detectors at the LHC. To select interesting events for recording, crucial decisions are taken before the data leaves the detector. FERMI modules are being developed at CERN in partnership with European industry.

  5. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2015-01-01

    A chip scale tunable laser in the visible spectral band is realized by generating a periodic droplet array inside a microfluidic channel. Combined with a gain medium within the droplets, the periodic structure provides the optical feedback of the laser. By controlling the pressure applied to two...

  6. Chip & Cut Tests an Elastomeren

    OpenAIRE

    Euchler, Eric; Heinrich, Gert; Michael, Hannes; Gehde, Michael; Stocek, Radek; Kratina, Ondrej; Kipscholl, Reinhold

    2016-01-01

    Dieser Vortrag stellt einen neuartigen Prüfstand vor, mit welchem das Chip & Cut Verhalten von Elastomeren charakterisiert werden kann. Sowohl theoretischer Hintergrund als auch praktische Erkenntnisse werden diskutiert. Die Vorstellung der Praxisrelevanz dieser Untersuchungen steht im Fokus des Vortrags.

  7. Optical lattice on an atom chip

    DEFF Research Database (Denmark)

    Gallego, D.; Hofferberth, S.; Schumm, Thorsten

    2009-01-01

    Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

  8. Acceleration of Cherenkov angle reconstruction with the new Intel Xeon/FPGA compute platform for the particle identification in the LHCb Upgrade

    Science.gov (United States)

    Faerber, Christian

    2017-10-01

    The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40 MHz. This increases the data bandwidth from the detector down to the Event Filter farm to 40 TBit/s, which also has to be processed to select the interesting proton-proton collision for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new Event Filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade the usage of an experimental FPGA accelerated computing platform in the Event Building or in the Event Filter farm is being considered and therefore tested. This platform from Intel hosts a general CPU and a high performance FPGA linked via a high speed link which is for this platform a QPI link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. As a first step, a computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported in Verilog to the Intel Xeon/FPGA platform and accelerated by a factor of 35. The same algorithm was ported to the Intel Xeon/FPGA platform with OpenCL. The implementation work and the performance will be compared. Also another FPGA accelerator the Nallatech 385 PCIe accelerator with the same Stratix V FPGA were tested for performance. The results show that the Intel

  9. Heat dissipation for the Intel Core i5 processor using multiwalled carbon-nanotube-based ethylene glycol

    Energy Technology Data Exchange (ETDEWEB)

    Thang, Bui Hung; Trinh, Pham Van; Quang, Le Dinh; Khoi, Phan Hong; Minh, Phan Ngoc [Vietnam Academy of Science and Technology, Ho Chi Minh CIty (Viet Nam); Huong, Nguyen Thi [Hanoi University of Science, Hanoi (Viet Nam); Vietnam National University, Hanoi (Viet Nam)

    2014-08-15

    Carbon nanotubes (CNTs) are some of the most valuable materials with high thermal conductivity. The thermal conductivity of individual multiwalled carbon nanotubes (MWCNTs) grown by using chemical vapor deposition is 600 ± 100 Wm{sup -1}K{sup -1} compared with the thermal conductivity 419 Wm{sup -1}K{sup -1} of Ag. Carbon-nanotube-based liquids - a new class of nanomaterials, have shown many interesting properties and distinctive features offering potential in heat dissipation applications for electronic devices, such as computer microprocessor, high power LED, etc. In this work, a multiwalled carbon-nanotube-based liquid was made of well-dispersed hydroxyl-functional multiwalled carbon nanotubes (MWCNT-OH) in ethylene glycol (EG)/distilled water (DW) solutions by using Tween-80 surfactant and an ultrasonication method. The concentration of MWCNT-OH in EG/DW solutions ranged from 0.1 to 1.2 gram/liter. The dispersion of the MWCNT-OH-based EG/DW solutions was evaluated by using a Zeta-Sizer analyzer. The MWCNT-OH-based EG/DW solutions were used as coolants in the liquid cooling system for the Intel Core i5 processor. The thermal dissipation efficiency and the thermal response of the system were evaluated by directly measuring the temperature of the micro-processor using the Core Temp software and the temperature sensors built inside the micro-processor. The results confirmed the advantages of CNTs in thermal dissipation systems for computer processors and other high-power electronic devices.

  10. Scalability of Parallel Spatial Direct Numerical Simulations on Intel Hypercube and IBM SP1 and SP2

    Science.gov (United States)

    Joslin, Ronald D.; Hanebutte, Ulf R.; Zubair, Mohammad

    1995-01-01

    The implementation and performance of a parallel spatial direct numerical simulation (PSDNS) approach on the Intel iPSC/860 hypercube and IBM SP1 and SP2 parallel computers is documented. Spatially evolving disturbances associated with the laminar-to-turbulent transition in boundary-layer flows are computed with the PSDNS code. The feasibility of using the PSDNS to perform transition studies on these computers is examined. The results indicate that PSDNS approach can effectively be parallelized on a distributed-memory parallel machine by remapping the distributed data structure during the course of the calculation. Scalability information is provided to estimate computational costs to match the actual costs relative to changes in the number of grid points. By increasing the number of processors, slower than linear speedups are achieved with optimized (machine-dependent library) routines. This slower than linear speedup results because the computational cost is dominated by FFT routine, which yields less than ideal speedups. By using appropriate compile options and optimized library routines on the SP1, the serial code achieves 52-56 M ops on a single node of the SP1 (45 percent of theoretical peak performance). The actual performance of the PSDNS code on the SP1 is evaluated with a "real world" simulation that consists of 1.7 million grid points. One time step of this simulation is calculated on eight nodes of the SP1 in the same time as required by a Cray Y/MP supercomputer. For the same simulation, 32-nodes of the SP1 and SP2 are required to reach the performance of a Cray C-90. A 32 node SP1 (SP2) configuration is 2.9 (4.6) times faster than a Cray Y/MP for this simulation, while the hypercube is roughly 2 times slower than the Y/MP for this application. KEY WORDS: Spatial direct numerical simulations; incompressible viscous flows; spectral methods; finite differences; parallel computing.

  11. Experiment list: SRX122465 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

  12. Experiment list: SRX122555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip anti...body catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-7

  13. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  14. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  15. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing; Yi, Xin; Xiao, Kang; Li, Shunbo; Kodzius, Rimantas; Qin, Jianhua; Wen, Weijia

    2013-01-01

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  16. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing

    2013-10-10

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  17. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  18. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  19. Self-powered integrated systems-on-chip (energy chip)

    Science.gov (United States)

    Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

    2010-04-01

    In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  20. Application of Intel Many Integrated Core (MIC) architecture to the Yonsei University planetary boundary layer scheme in Weather Research and Forecasting model

    Science.gov (United States)

    Huang, Melin; Huang, Bormin; Huang, Allen H.

    2014-10-01

    The Weather Research and Forecasting (WRF) model provided operational services worldwide in many areas and has linked to our daily activity, in particular during severe weather events. The scheme of Yonsei University (YSU) is one of planetary boundary layer (PBL) models in WRF. The PBL is responsible for vertical sub-grid-scale fluxes due to eddy transports in the whole atmospheric column, determines the flux profiles within the well-mixed boundary layer and the stable layer, and thus provide atmospheric tendencies of temperature, moisture (including clouds), and horizontal momentum in the entire atmospheric column. The YSU scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. To accelerate the computation process of the YSU scheme, we employ Intel Many Integrated Core (MIC) Architecture as it is a multiprocessor computer structure with merits of efficient parallelization and vectorization essentials. Our results show that the MIC-based optimization improved the performance of the first version of multi-threaded code on Xeon Phi 5110P by a factor of 2.4x. Furthermore, the same CPU-based optimizations improved the performance on Intel Xeon E5-2603 by a factor of 1.6x as compared to the first version of multi-threaded code.

  1. The use of forest chips in Finland

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    International commitments require the industrial world to restrict their greenhouse gas emissions. In Finland, where the annual timber cut per capita is more than ten times the average cut in the other EU countries, the primary means to reduce CO 2 emissions is to replace fossil fuels with forest biomass. The annual consumption of wood-based energy corresponds to 6 million tonnes of oil equivalent (toe) or almost 20% of the total primary energy consumption. The goal is to rise the annual production of wood-based energy to 7.8 million toe by 2010. Substantial part of the targeted increase could be obtained by forest chips produced of unmerchantable small-diameter trees and logging residues. The goal for 2010 is to use 5 million solid m 3 of forest chips, which equals to 0.9 million toe. The use of forest chips is increasing. About 474 000 solid m 3 of forest chips were used as fuel in 1999. At the moment, the growth is rapid especially in cogeneration plants producing both heat and electricity. The growth is based primarily on chips obtained from logging residues. The price of forest chips decreased considerably during the 1990s but the price range remained wide. Chips made of logging residues are cheaper than those made of small trees. The average price of forest chips at the plant, VAT excluded, is about 53 FIM per MWh. In Sweden, the average price is more than 40% higher

  2. Least cost supply strategies for wood chips

    DEFF Research Database (Denmark)

    Möller, Bernd

    The abstract presents a study based on a geographical information system, which produce  cost-supply curves by location for forest woods chips in Denmark.......The abstract presents a study based on a geographical information system, which produce  cost-supply curves by location for forest woods chips in Denmark....

  3. Teaching Quality Control with Chocolate Chip Cookies

    Science.gov (United States)

    Baker, Ardith

    2014-01-01

    Chocolate chip cookies are used to illustrate the importance and effectiveness of control charts in Statistical Process Control. By counting the number of chocolate chips, creating the spreadsheet, calculating the control limits and graphing the control charts, the student becomes actively engaged in the learning process. In addition, examining…

  4. A Chip for an Implantable Neural Stimulator

    DEFF Research Database (Denmark)

    Gudnason, Gunnar; Bruun, Erik; Haugland, Morten

    2000-01-01

    This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation (FES). The purpose of FES is to restore muscular control in disabled patients. The chip performs all the signal processing required in an implanted neural stimulator. The power and digital data...

  5. Performance evaluation of chip seals in Idaho.

    Science.gov (United States)

    2010-08-01

    The intent of this research project is to identify a wide variety of parameters that influence the performance of pavements treated via chip seals within the State of Idaho. Chip sealing is currently one of the most popular methods of maintenance for...

  6. Simple photolithographic rapid prototyping of microfluidic chips

    DEFF Research Database (Denmark)

    Kunstmann-Olsen, Casper; Hoyland, James; Rubahn, Horst-Günter

    2012-01-01

    Vi præsenterer en simpel metode til at producere støbeforme til støbning af PDMS mikrofluide chips vha. fotolitografi, med 35mm fotonegativer som masker. Vi demonstrer metodens muligheder og begrænsninger. Vi har optimeret processen til at fremstille planare lab-on-a-chip strukturer med meget høj...

  7. Microneedle Array Interface to CE on Chip

    NARCIS (Netherlands)

    Lüttge, Regina; Gardeniers, Johannes G.E.; Vrouwe, E.X.; van den Berg, Albert; Northrup, M.A.; Jensen, K.F; Harrison, D.J.

    2003-01-01

    This paper presents a microneedle array sampler interfaced to a capillary electrophoresis (CE) glass chip with integrated conductivity detection electrodes. A solution of alkali ions was electrokinetically loaded through the microneedles onto the chip and separation was demonstrated compared to a

  8. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  9. METAL CHIP HEATING PROCESS INVESTIGATION (Part I

    Directory of Open Access Journals (Sweden)

    O. M. Dyakonov

    2007-01-01

    Full Text Available The main calculation methods for heat- and mass transfer in porous heterogeneous medium have been considered. The paper gives an evaluation of the possibility to apply them for calculation of metal chip heating process. It has been shown that a description of transfer processes in a chip has its own specific character that is attributed to difference between thermal and physical properties of chip material and lubricant-coolant components on chip surfaces. It has been determined that the known expressions for effective heat transfer coefficients can be used as basic ones while approaching mutually penetrating continuums. A mathematical description of heat- and mass transfer in chip medium can be considered as a basis of mathematical modeling, numerical solution and parameter optimization of the mentioned processes.

  10. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  11. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-15

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

  12. Supply systems of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-01

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

  13. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

    2009-07-01

    The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

  14. Experiment list: SRX122563 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  15. Experiment list: SRX122564 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  16. Experiment list: SRX122488 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  17. Experiment list: SRX122510 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Egr1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110 ht

  18. Experiment list: SRX122491 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  19. Experiment list: SRX122519 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  20. Experiment list: SRX122548 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  1. Experiment list: SRX122468 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rela || treatment=LPS || time=0 min || chip antibody manufacturer 1=Bethyl || chip antibody catalo...g number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372 htt

  2. Experiment list: SRX122561 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  3. Experiment list: SRX122551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ca...talog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A htt

  4. Experiment list: SRX122409 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Irf1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody cata...log number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 htt

  5. Experiment list: SRX122487 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  6. Experiment list: SRX122546 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  7. Experiment list: SRX122552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  8. Experiment list: SRX122547 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  9. Experiment list: SRX214084 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available turer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox17-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufac

  10. Experiment list: SRX122472 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Runx1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564 http

  11. Experiment list: SRX122544 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  12. Experiment list: SRX122408 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Irf1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http

  13. Experiment list: SRX122473 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Runx1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564

  14. Experiment list: SRX122513 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Egr1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110

  15. Experiment list: SRX214077 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available erentiated || treatment=Overexpress Sox17_V5 tagged || cell line=KH2 || chip antibody 1=Sox17 || chip antibody manufacture...r 1=R&D || chip antibody 2=V5 || chip antibody manufacturer 2=Invit

  16. Experiment list: SRX122497 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  17. Experiment list: SRX214082 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available facturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manu

  18. Experiment list: SRX122410 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  19. Experiment list: SRX122567 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  20. Experiment list: SRX122466 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Relb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Bethyl || chip antibody cata...log number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-226 h

  1. Experiment list: SRX122490 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  2. Experiment list: SRX214068 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available inoic acid || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacturer 1=Santa Cruz || chip... antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDat

  3. Experiment list: SRX122558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  4. Experiment list: SRX122494 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-2

  5. Experiment list: SRX122545 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  6. Experiment list: SRX186172 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 1=YY1 || chip antibody manufacturer 1=Abcam || chip antibody 2=YY1 || chip antibody manufacturer 2=Santa Cru...ip-Seq; Mus musculus; ChIP-Seq source_name=Rag1 -/- pro-B cells || chip antibody

  7. Experiment list: SRX122557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  8. Experiment list: SRX122492 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  9. Experiment list: SRX122493 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-200

  10. Experiment list: SRX122571 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http

  11. Experiment list: SRX122411 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  12. Experiment list: SRX122549 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  13. Experiment list: SRX122498 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  14. Experiment list: SRX122516 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  15. Experiment list: SRX122484 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cata...log number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 http

  16. Experiment list: SRX122514 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available tibody=Irf2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog nu...mber 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://db

  17. Experiment list: SRX122570 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  18. Experiment list: SRX214080 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  19. Experiment list: SRX122569 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 h

  20. Experiment list: SRX122511 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Egr1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-11

  1. Experiment list: SRX122471 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Rela || treatment=LPS || time=60 min || chip antibody manufacturer 1=Bethyl || chip antibody cat...alog number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372

  2. Experiment list: SRX122495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Rel || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody catal...og number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http://

  3. Experiment list: SRX122554 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  4. Experiment list: SRX214081 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  5. Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    Science.gov (United States)

    Hashida, Takushi; Nagata, Makoto

    Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

  6. Mesa de coordenadas cartesianas (x,y para la perforación de materiales por medio de un microcontrolador 8051 de intel

    Directory of Open Access Journals (Sweden)

    Omar Yesid Flórez-Prada

    2001-01-01

    Full Text Available In our environment we are surrounded by a number of electronic systems that perform automatic operations according to a number of parameters previously programmed by the operator. This paper presents the prototype of a table of two coordinates (Cartesian plane (X, Y, which uses a development system based on the 8051 microcontroller INTEL (R (computer system, making the system function sending the respective control commands to locate the tool at different points of the work area of the table, the points are previously programmed by the operator, interacting with the keyboard. To make the movements of the table (X, Y, actuator devices responsible for carrying out a linear movement that moves the tool to the specified distance are used.

  7. Simulating the Euclidean time Schroedinger equations using an Intel iPSC/860 hypercube: Application to the t-J model of high-Tc superconductivity

    International Nuclear Information System (INIS)

    Kovarik, M.D.; Barnes, T.; Tennessee Univ., Knoxville, TN

    1993-01-01

    We describe a Monte Carlo simulation of a dynamical fermion problem in two spatial dimensions on an Intel iPSC/860 hypercube. The problem studied is the determination of the dispersion relation of a dynamical hole in the t-J model of the high temperature superconductors. Since this problem involves the motion of many fermions in more than one spatial dimensions, it is representative of the class of systems that suffer from the ''minus sign problem'' of dynamical fermions which has made Monte Carlo simulation very difficult. We demonstrate that for small values of the hole hopping parameter one can extract the entire hole dispersion relation using the GRW Monte Carlo algorithm, which is a simulation of the Euclidean time Schroedinger equation, and present results on 4 x 4 and 6 x 6 lattices. Generalization to physical hopping parameter values wig only require use of an improved trial wavefunction for importance sampling

  8. Instrument for measuring moisture in wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Werme, L

    1980-06-01

    A method to determine the moisture content in wood chips, in batch and on-line, has been investigated. The method can be used for frozen and non frozen chips. Samples of wood chips are thawn and dryed with microwaves. During the drying the sample is weighed continously and the rate of drying is measured. The sample is dried t 10 percent moisture content. The result is extrapolated to the drying rate zero. The acccuracy at the method is 1.6 to 1.7 percent for both frozen and non frozen chips. The accuracy of the method is considered acceptable, but sofisticated sampling equipment is necessary. This makes the method too complex to make the instrument marketable.

  9. Medicaid CHIP Environmental Scanning and Program Char...

    Data.gov (United States)

    U.S. Department of Health & Human Services — ESPC development is sponsored by the CMS Center for Medicare and Medicaid Innovation in partnership with the Center for Medicaid and CHIP Services (CMCS) under the...

  10. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  11. Distributed Processing Using Single-chip Microcomputers

    National Research Council Canada - National Science Library

    Pritchett, William

    1996-01-01

    This project investigates the use of single-chip microprocessors as nodes in a token ring control network and explores the implementation of a protocol to manage communication across such a network...

  12. Optical bio-sensors in microfluidic chips

    NARCIS (Netherlands)

    Pollnau, Markus; Dongre, C.; Pham Van So, P.V.S.; Bernhardi, Edward; Worhoff, Kerstin; de Ridder, R.M.; Hoekstra, Hugo

    2012-01-01

    Direct femtosecond laser writing is used to integrate optical waveguides that intersect the microfluidic channels in a commercial optofluidic chip. With laser excitation, fluorescently labeled DNA molecules of different sizes are separated by capillary electrophoresis with high operating speed and

  13. Optics and molecules on atom chips

    International Nuclear Information System (INIS)

    Tscherneck, M; Holmes, M E; Quinto-Su, P A; Haimberger, C; Kleinert, J; Bigelow, N P

    2005-01-01

    In this paper we will report on four experiments which have been carried out in the last year in our group. All of these experiments are necessary steps towards the trapping and probing of ultracold molecules on a chip surface

  14. The CHIP surveys | IDRC - International Development Research ...

    International Development Research Centre (IDRC) Digital Library (Canada)

    2011-07-08

    Jul 8, 2011 ... Many of the young scholars relied on data generated by the China Household Income Project (CHIP), a collaboration between Chinese and international economists that has tracked inequality in China for the past 20 years.

  15. Industry trends in chip storage and handling

    Science.gov (United States)

    Tim McDonald; Alastair Twaddle

    2000-01-01

    A survey was conducted of US pulp and paper mills to characterize chip pile management trends. The survey was developed by members of the TAPPI Fiber Raw Material Supply Committee and mailed out in December of 1999. There were a total of 80 respondents to the survey. A typical mill was foudn to maintain one sofhvood and one hardwood chip pile, with maximum inventory of...

  16. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  17. Materials for microfluidic chip fabrication.

    Science.gov (United States)

    Ren, Kangning; Zhou, Jianhua; Wu, Hongkai

    2013-11-19

    Through manipulating fluids using microfabricated channel and chamber structures, microfluidics is a powerful tool to realize high sensitive, high speed, high throughput, and low cost analysis. In addition, the method can establish a well-controlled microenivroment for manipulating fluids and particles. It also has rapid growing implementations in both sophisticated chemical/biological analysis and low-cost point-of-care assays. Some unique phenomena emerge at the micrometer scale. For example, reactions are completed in a shorter amount of time as the travel distances of mass and heat are relatively small; the flows are usually laminar; and the capillary effect becomes dominant owing to large surface-to-volume ratios. In the meantime, the surface properties of the device material are greatly amplified, which can lead to either unique functions or problems that we would not encounter at the macroscale. Also, each material inherently corresponds with specific microfabrication strategies and certain native properties of the device. Therefore, the material for making the device plays a dominating role in microfluidic technologies. In this Account, we address the evolution of materials used for fabricating microfluidic chips, and discuss the application-oriented pros and cons of different materials. This Account generally follows the order of the materials introduced to microfluidics. Glass and silicon, the first generation microfluidic device materials, are perfect for capillary electrophoresis and solvent-involved applications but expensive for microfabriaction. Elastomers enable low-cost rapid prototyping and high density integration of valves on chip, allowing complicated and parallel fluid manipulation and in-channel cell culture. Plastics, as competitive alternatives to elastomers, are also rapid and inexpensive to microfabricate. Their broad variety provides flexible choices for different needs. For example, some thermosets support in-situ fabrication of

  18. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  19. Discovery Mondays: Chips with everything!

    CERN Multimedia

    2003-01-01

    Electronics to hear the sound of matter From the TV to the fridge, the wristwatch to the washing machine, hardly any consumer product in this day and age can escape the influence of electronics, and the ever more powerful microchip. So it's hardly surprising to learn that such sophisticated devices as particle detectors are bristling with the best and most powerful microchips technology has to offer! Particle detectors known as trackers are like 3-D digital cameras. They are used to detect the tracks of particles created in the accelerator and to pin down their momentum and thus their identity. A chip seen with a microscope.Come to Microcosm and see with your own eyes a silicon detector, packed full of electronic microchips. Get up closer with a microscope and admire the way in which the fine details of the etchings break down light. Further on, watch a TV as you've never done before - from the inside! Then try out our special simulation game that helps you understand the purpose of a particle detector. Bu...

  20. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  1. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  2. Prototype detection unit for the CHIPS experiment

    Science.gov (United States)

    Pfützner, Maciej M.

    2017-09-01

    CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

  3. The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

    Science.gov (United States)

    Nikolova, Silviya; Stearns, Sally

    2014-03-03

    Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

  4. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  5. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  6. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  7. The single chip microcomputer technique in an intelligent nuclear instrument

    International Nuclear Information System (INIS)

    Wang Tieliu; Sun Punan; Wang Ying

    1995-01-01

    The authors present that how to acquire and process the output signals from the nuclear detector adopting single chip microcomputer technique, including working principles and the designing method of the computer's software and hardware in the single chip microcomputer instrument

  8. Experiment list: SRX180159 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available sd || cell type=hemogenic endothelium || chip antibody=CEBPb || chip antibody vendor=santa cruz biotechnol...ogy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachData/bw/SRX180159.bw http://

  9. Experiment list: SRX112178 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=8WG16 (MMS-126R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm

  10. Experiment list: SRX319550 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e embryonic stem cells || genotype/variation=expressing Flag-bio tagged Myc || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  11. Experiment list: SRX319556 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  12. Experiment list: SRX112184 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Sepharose beads http://dbarchive.biosciencedbc.jp/kyushu-u/m

  13. Experiment list: SRX319558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available | cell type=mouse embryonic stem cells || genotype/variation=expressing control BirA || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  14. Experiment list: SRX319553 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Tip60 || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  15. Experiment list: SRX319557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Nanog || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  16. Experiment list: SRX319555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  17. Experiment list: SRX319551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available use embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dmap1 || chip beads=Dynabeads MyOn...e Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.

  18. Experiment list: SRX185907 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Homo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-...7 || cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_

  19. Experiment list: SRX367330 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siBrd4 http://dbarchive.bi...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  20. Experiment list: SRX367328 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siCTL http://dbarchive.bio...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  1. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...

  2. Experiment list: SRX543048 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea...CID.adh murine thymic lymphoma || development stage=DN3 || chip antibody=rabbit anti-Miz-1 || chip antibody vendor=Santa Cruz Biotech

  3. Lab-on a-Chip

    Science.gov (United States)

    1999-01-01

    Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

  4. Biostability of an implantable glucose sensor chip

    Science.gov (United States)

    Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

    2012-12-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  5. Biostability of an implantable glucose sensor chip

    International Nuclear Information System (INIS)

    Fröhlich, M; Ehwald, K E; Kulse, P; Fursenko, O; Katzer, J; Birkholz, M

    2012-01-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO 2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and R a roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  6. Modified precision-husky progrind H-3045 for chipping biomass

    Science.gov (United States)

    Dana Mitchell; Fernando Seixas; John. Klepac

    2008-01-01

    A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

  7. Silicon microstrip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Masciocchi, S.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.S.; Timm, S.; Vorwalter, K.; Werding, R.

    1995-01-01

    A new silicon strip detector has been designed for the fixed target experiment WA89 at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into a FASTBUS memory. The detector provides a fast readout by offering zero-suppressed data extraction on the chip. The silicon counters are the largest detectors built on a monocrystal so far in order to achieve good transversal acceptance. Construction and performance during the 1993 data taking run are discussed. ((orig.))

  8. MCMII and the TriP chip

    Energy Technology Data Exchange (ETDEWEB)

    Juan Estrada et al.

    2003-12-19

    We describe the development of the electronics that will be used to read out the Fiber Tracker and Preshower detectors in Run IIb. This electronics is needed for operation at 132ns bunch crossing, and may provide a measurement of the z coordinate of the Fiber Tracker hits when operating at 396ns bunch crossing. Specifically, we describe the design and preliminary tests of the Trip chip, MCM IIa, MCM IIb and MCM IIc. This document also serves as a user manual for the Trip chip and the MCM.

  9. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  10. A Neuron- and a Synapse Chip for Artificial Neural Networks

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1992-01-01

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where...

  11. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  12. Wood chip delivery and research project at Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1995-01-01

    In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m 3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m 3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m 3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m 3 /a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

  13. Experiment list: SRX485203 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346544: Rhino ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  14. Experiment list: SRX485202 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346543: Rhino ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  15. Experiment list: SRX485205 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 46546: Rhino ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=R...hino ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made rabb

  16. Experiment list: SRX485212 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346553: Cutoff ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=C...utoff ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female |...| tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit

  17. Experiment list: SRX485210 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6551: Deadlock ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name...=Deadlock ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made

  18. Experiment list: SRX485220 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 53 GSM1346561: RNA Polymerase II ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-...Seq source_name=RNA Polymerase II ChIP from rhino germline knock-down ovaries || developmental stage=4-6 day...s old adult || Sex=female || tissue=ovary || germline knock-down=rhino || chip an

  19. Experiment list: SRX485211 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346552: Cutoff ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=...Cutoff ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=control || chip antibody=custom-made rabb

  20. Experiment list: SRX485204 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346545: Rhino ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rhi...no ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ti...ssue=ovary || germline knock-down=rhino || chip antibody=custom-made rabbit polyc

  1. Experiment list: SRX485208 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346549: Rhino ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq sou...rce_name=Rhino ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=piwi || chip antibody=custom-made ra

  2. Experiment list: SRX485206 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346547: Rhino ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rh...ino ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ...tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit po

  3. Experiment list: SRX485209 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346550: Deadlock ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_nam...e=Deadlock ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=custom-made

  4. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  5. Experiment list: SRX110782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e3 (ab6002, abcam), Pol II (CTD4H8, Millipore) || chip antibody 1 manufacturer=ab...cam || chip antibody 2=Pol II (CTD4H8, Millipore) || chip antibody 2 manufacturer=Millipore http://dbarchive

  6. The parallel processing of EGS4 code on distributed memory scalar parallel computer:Intel Paragon XP/S15-256

    Energy Technology Data Exchange (ETDEWEB)

    Takemiya, Hiroshi; Ohta, Hirofumi; Honma, Ichirou

    1996-03-01

    The parallelization of Electro-Magnetic Cascade Monte Carlo Simulation Code, EGS4 on distributed memory scalar parallel computer: Intel Paragon XP/S15-256 is described. EGS4 has the feature that calculation time for one incident particle is quite different from each other because of the dynamic generation of secondary particles and different behavior of each particle. Granularity for parallel processing, parallel programming model and the algorithm of parallel random number generation are discussed and two kinds of method, each of which allocates particles dynamically or statically, are used for the purpose of realizing high speed parallel processing of this code. Among four problems chosen for performance evaluation, the speedup factors for three problems have been attained to nearly 100 times with 128 processor. It has been found that when both the calculation time for each incident particles and its dispersion are large, it is preferable to use dynamic particle allocation method which can average the load for each processor. And it has also been found that when they are small, it is preferable to use static particle allocation method which reduces the communication overhead. Moreover, it is pointed out that to get the result accurately, it is necessary to use double precision variables in EGS4 code. Finally, the workflow of program parallelization is analyzed and tools for program parallelization through the experience of the EGS4 parallelization are discussed. (author).

  7. A Monte Carlo study of the ''minus sign problem'' in the t-J model using an intel IPSC/860 hypercube

    International Nuclear Information System (INIS)

    Kovarik, M.D.; Barnes, T.; Tennessee Univ., Knoxville, TN

    1993-01-01

    We describe a Monte Carlo simulation of the 2-dimensional t-J model on an Intel iPSC/860 hypercube. The problem studied is the determination of the dispersion relation of a dynamical hole in the t-J model of the high temperature superconductors. Since this problem involves the motion of many fermions in more than one spatial dimensions, it is representative of the class of systems that suffer from the ''minus sign problem'' of dynamical fermions which has made Monte Carlo simulation very difficult. We demonstrate that for small values of the hole hopping parameter one can extract the entire hole dispersion relation using the GRW Monte Carlo algorithm, which is a simulation of the Euclidean time Schroedinger equation, and present results on 4 x 4 and 6 x 6 lattices. We demonstrate that a qualitative picture at higher hopping parameters may be found by extrapolating weak hopping results where the minus sign problem is less severe. Generalization to physical hopping parameter values will only require use of an improved trial wavefunction for importance sampling

  8. Simulating the Effect of Modulated Tool-Path Chip Breaking On Surface Texture and Chip Length

    Energy Technology Data Exchange (ETDEWEB)

    Smith, K.S.; McFarland, J.T.; Tursky, D. A.; Assaid, T. S.; Barkman, W. E.; Babelay, Jr., E. F.

    2010-04-30

    One method for creating broken chips in turning processes involves oscillating the cutting tool in the feed direction utilizing the CNC machine axes. The University of North Carolina at Charlotte and the Y-12 National Security Complex have developed and are refining a method to reliably control surface finish and chip length based on a particular machine's dynamic performance. Using computer simulations it is possible to combine the motion of the machine axes with the geometry of the cutting tool to predict the surface characteristics and map the surface texture for a wide range of oscillation parameters. These data allow the selection of oscillation parameters to simultaneously ensure broken chips and acceptable surface characteristics. This paper describes the machine dynamic testing and characterization activities as well as the computational method used for evaluating and predicting chip length and surface texture.

  9. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  10. "Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

    Directory of Open Access Journals (Sweden)

    Krohn Knut

    2008-08-01

    Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

  11. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  12. Results of irriadiating the APV5 chip

    CERN Document Server

    Raymond, M

    1996-01-01

    An APV5 chip has been irradiated in steps up to 16 Mrads using a Co-60 source in order to confirm the radiation hardness expected from individual transistor and sub-circuit measurements. Full functionality is preserved after irradiation and measurements of the amplifier pulse shape and noise are presented.

  13. Chip based electroanalytical systems for cell analysis

    DEFF Research Database (Denmark)

    Spegel, C.; Heiskanen, A.; Skjolding, L.H.D.

    2008-01-01

    ' measurements of processes related to living cells, i.e., systems without lysing the cells. The focus is on chip based amperometric and impedimetric cell analysis systems where measurements utilizing solely carbon fiber microelectrodes (CFME) and other nonchip electrode formats, such as CFME for exocytosis...

  14. Increasing security in inter-chip communication

    Science.gov (United States)

    Edwards, Nathan J; Hamlet, Jason; Bauer, Todd; Helinski, Ryan

    2014-10-28

    An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

  15. Cytostretch, an Organ-on-Chip Platform

    NARCIS (Netherlands)

    Gaio, N.; van Meer, B.; Quiros Solano, W.F.; Bergers, L.; van de Stolpe, A; Mummery, CL; Sarro, P.M.; Dekker, R.

    2016-01-01

    Organ-on-Chips (OOCs) are micro-fabricated devices which are used to culture cells in order to mimic functional units of human organs. The devices are designed to simulate the physiological environment of tissues in vivo. Cells in some types of OOCs can be stimulated in situ by electrical and/or

  16. Microprocessors: From basic chips to complete systems

    International Nuclear Information System (INIS)

    Dobinson, R.W.

    1985-01-01

    These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/0) devices, etc. (orig./HSI)

  17. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  18. Smart Chips for Smart Surroundings -- 4S

    NARCIS (Netherlands)

    Schuler, Eberhard; König, Ralf; Becker, Jürgen; Rauwerda, G.K.; van de Burgwal, M.D.; Smit, Gerardus Johannes Maria; Cardoso, João M.P.; Hübner, Michael

    2011-01-01

    The overall mission of the 4S project (Smart Chips for Smart Surroundings) was to define and develop efficient flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient System Devices. Reconfigurability offers the needed flexibility and adaptability, it

  19. On-chip mode division multiplexing technologies

    DEFF Research Database (Denmark)

    Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

    2016-01-01

    Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... photonic integrated circuit mode (de) multiplexer for few-mode fibers (FMFs)....

  20. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  1. Microarrays (DNA Chips) for the Classroom Laboratory

    Science.gov (United States)

    Barnard, Betsy; Sussman, Michael; BonDurant, Sandra Splinter; Nienhuis, James; Krysan, Patrick

    2006-01-01

    We have developed and optimized the necessary laboratory materials to make DNA microarray technology accessible to all high school students at a fraction of both cost and data size. The primary component is a DNA chip/array that students "print" by hand and then analyze using research tools that have been adapted for classroom use. The…

  2. Drying characteristics of willow chips and stems

    NARCIS (Netherlands)

    Gigler, J.K.; Loon, van W.K.P.; Seres, I.; Meerdink, G.; Coumans, W.J.

    2000-01-01

    In supply chains of willow (Salix viminalis) biomass to energy plants, drying is advisable in order to enable safe long-term storage, increase boiler efficiency and reduce gaseous emissions. To gain insight into the drying process, drying characteristics of willow chips and stems were investigated

  3. Atom chips: mesoscopic physics with cold atoms

    International Nuclear Information System (INIS)

    Krueger, P.; Wildermuth, S.; Hofferberth, S.; Haller, E.; GAllego Garcia, D.; Schmiedmayer, J.

    2005-01-01

    Full text: Cold neutral atoms can be controlled and manipulated in microscopic potentials near surfaces of atom chips. These integrated micro-devices combine the known techniques of atom optics with the capabilities of well established micro- and nanofabrication technology. In analogy to electronic microchips and integrated fiber optics, the concept of atom chips is suitable to explore the domain of mesoscopic physics with matter waves. We use current and charge carrying structures to form complex potentials with high spatial resolution only microns from the surface. In particular, atoms can be confined to an essentially one-dimensional motion. In this talk, we will give an overview of our experiments studying the manipulation of both thermal atoms and BECs on atom chips. First experiments in the quasi one-dimensional regime will be presented. These experiments profit from strongly reduced residual disorder potentials caused by imperfections of the chip fabrication with respect to previously published experiments. This is due to our purely lithographic fabrication technique that proves to be advantageous over electroplating. We have used one dimensionally confined BECs as an ultra-sensitive probe to characterize these potentials. These smooth potentials allow us to explore various aspects of the physics of degenerate quantum gases in low dimensions. (author)

  4. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  5. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  6. On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

    International Nuclear Information System (INIS)

    Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

    2010-01-01

    We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

  7. On-chip particle trapping and manipulation

    Science.gov (United States)

    Leake, Kaelyn Danielle

    The ability to control and manipulate the world around us is human nature. Humans and our ancestors have used tools for millions of years. Only in recent years have we been able to control objects at such small levels. In order to understand the world around us it is frequently necessary to interact with the biological world. Optical trapping and manipulation offer a non-invasive way to move, sort and interact with particles and cells to see how they react to the world around them. Optical tweezers are ideal in their abilities but they require large, non-portable, and expensive setups limiting how and where we can use them. A cheap portable platform is required in order to have optical manipulation reach its full potential. On-chip technology offers a great solution to this challenge. We focused on the Liquid-Core Anti-Resonant Reflecting Optical Waveguide (liquid-core ARROW) for our work. The ARROW is an ideal platform, which has anti-resonant layers which allow light to be guided in liquids, allowing for particles to easily be manipulated. It is manufactured using standard silicon manufacturing techniques making it easy to produce. The planner design makes it easy to integrate with other technologies. Initially I worked to improve the ARROW chip by reducing the intersection losses and by reducing the fluorescence and background on the ARROW chip. The ARROW chip has already been used to trap and push particles along its channel but here I introduce several new methods of particle trapping and manipulation on the ARROW chip. Traditional two beam traps use two counter propagating beams. A trapping scheme that uses two orthogonal beams which counter to first instinct allow for trapping at their intersection is introduced. This scheme is thoroughly predicted and analyzed using realistic conditions. Simulations of this method were done using a program which looks at both the fluidics and optical sources to model complex situations. These simulations were also used to

  8. TH-A-19A-08: Intel Xeon Phi Implementation of a Fast Multi-Purpose Monte Carlo Simulation for Proton Therapy

    Energy Technology Data Exchange (ETDEWEB)

    Souris, K; Lee, J; Sterpin, E [Universite catholique de Louvain, Brussels (Belgium)

    2014-06-15

    Purpose: Recent studies have demonstrated the capability of graphics processing units (GPUs) to compute dose distributions using Monte Carlo (MC) methods within clinical time constraints. However, GPUs have a rigid vectorial architecture that favors the implementation of simplified particle transport algorithms, adapted to specific tasks. Our new, fast, and multipurpose MC code, named MCsquare, runs on Intel Xeon Phi coprocessors. This technology offers 60 independent cores, and therefore more flexibility to implement fast and yet generic MC functionalities, such as prompt gamma simulations. Methods: MCsquare implements several models and hence allows users to make their own tradeoff between speed and accuracy. A 200 MeV proton beam is simulated in a heterogeneous phantom using Geant4 and two configurations of MCsquare. The first one is the most conservative and accurate. The method of fictitious interactions handles the interfaces and secondary charged particles emitted in nuclear interactions are fully simulated. The second, faster configuration simplifies interface crossings and simulates only secondary protons after nuclear interaction events. Integral depth-dose and transversal profiles are compared to those of Geant4. Moreover, the production profile of prompt gammas is compared to PENH results. Results: Integral depth dose and transversal profiles computed by MCsquare and Geant4 are within 3%. The production of secondaries from nuclear interactions is slightly inaccurate at interfaces for the fastest configuration of MCsquare but this is unlikely to have any clinical impact. The computation time varies between 90 seconds for the most conservative settings to merely 59 seconds in the fastest configuration. Finally prompt gamma profiles are also in very good agreement with PENH results. Conclusion: Our new, fast, and multi-purpose Monte Carlo code simulates prompt gammas and calculates dose distributions in less than a minute, which complies with clinical time

  9. TH-A-19A-08: Intel Xeon Phi Implementation of a Fast Multi-Purpose Monte Carlo Simulation for Proton Therapy

    International Nuclear Information System (INIS)

    Souris, K; Lee, J; Sterpin, E

    2014-01-01

    Purpose: Recent studies have demonstrated the capability of graphics processing units (GPUs) to compute dose distributions using Monte Carlo (MC) methods within clinical time constraints. However, GPUs have a rigid vectorial architecture that favors the implementation of simplified particle transport algorithms, adapted to specific tasks. Our new, fast, and multipurpose MC code, named MCsquare, runs on Intel Xeon Phi coprocessors. This technology offers 60 independent cores, and therefore more flexibility to implement fast and yet generic MC functionalities, such as prompt gamma simulations. Methods: MCsquare implements several models and hence allows users to make their own tradeoff between speed and accuracy. A 200 MeV proton beam is simulated in a heterogeneous phantom using Geant4 and two configurations of MCsquare. The first one is the most conservative and accurate. The method of fictitious interactions handles the interfaces and secondary charged particles emitted in nuclear interactions are fully simulated. The second, faster configuration simplifies interface crossings and simulates only secondary protons after nuclear interaction events. Integral depth-dose and transversal profiles are compared to those of Geant4. Moreover, the production profile of prompt gammas is compared to PENH results. Results: Integral depth dose and transversal profiles computed by MCsquare and Geant4 are within 3%. The production of secondaries from nuclear interactions is slightly inaccurate at interfaces for the fastest configuration of MCsquare but this is unlikely to have any clinical impact. The computation time varies between 90 seconds for the most conservative settings to merely 59 seconds in the fastest configuration. Finally prompt gamma profiles are also in very good agreement with PENH results. Conclusion: Our new, fast, and multi-purpose Monte Carlo code simulates prompt gammas and calculates dose distributions in less than a minute, which complies with clinical time

  10. Microengineered physiological biomimicry: organs-on-chips.

    Science.gov (United States)

    Huh, Dongeun; Torisawa, Yu-suke; Hamilton, Geraldine A; Kim, Hyun Jung; Ingber, Donald E

    2012-06-21

    Microscale engineering technologies provide unprecedented opportunities to create cell culture microenvironments that go beyond current three-dimensional in vitro models by recapitulating the critical tissue-tissue interfaces, spatiotemporal chemical gradients, and dynamic mechanical microenvironments of living organs. Here we review recent advances in this field made over the past two years that are focused on the development of 'Organs-on-Chips' in which living cells are cultured within microfluidic devices that have been microengineered to reconstitute tissue arrangements observed in living organs in order to study physiology in an organ-specific context and to develop specialized in vitro disease models. We discuss the potential of organs-on-chips as alternatives to conventional cell culture models and animal testing for pharmaceutical and toxicology applications. We also explore challenges that lie ahead if this field is to fulfil its promise to transform the future of drug development and chemical safety testing.

  11. Surface enhanced raman spectroscopy on chip

    DEFF Research Database (Denmark)

    Hübner, Jörg; Anhøj, Thomas Aarøe; Zauner, Dan

    2007-01-01

    In this paper we report low resolution surface enhanced Raman spectra (SERS) conducted with a chip based spectrometer. The flat field spectrometer presented here is fabricated in SU-8 on silicon, showing a resolution of around 3 nm and a free spectral range of around 100 nm. The output facet...... is projected onto a CCD element and visualized by a computer. To enhance the otherwise rather weak Raman signal, a nanosurface is prepared and a sample solutions is impregnated on this surface. The surface enhanced Raman signal is picked up using a Raman probe and coupled into the spectrometer via an optical...... fiber. The obtained spectra show that chip based spectrometer together with the SERS active surface can be used as Raman sensor....

  12. On-Chip Microwave Quantum Hall Circulator

    Directory of Open Access Journals (Sweden)

    A. C. Mahoney

    2017-01-01

    Full Text Available Circulators are nonreciprocal circuit elements that are integral to technologies including radar systems, microwave communication transceivers, and the readout of quantum information devices. Their nonreciprocity arises from the interference of microwaves over the centimeter scale of the signal wavelength, in the presence of bulky magnetic media that breaks time-reversal symmetry. Here, we realize a completely passive on-chip microwave circulator with size 1/1000th the wavelength by exploiting the chiral, “slow-light” response of a two-dimensional electron gas in the quantum Hall regime. For an integrated GaAs device with 330  μm diameter and about 1-GHz center frequency, a nonreciprocity of 25 dB is observed over a 50-MHz bandwidth. Furthermore, the nonreciprocity can be dynamically tuned by varying the voltage at the port, an aspect that may enable reconfigurable passive routing of microwave signals on chip.

  13. Microfluidic chip-capillary electrophoresis devices

    CERN Document Server

    Fung, Ying Sing; Du, Fuying; Guo, Wenpeng; Ma, Tongmei; Nie, Zhou; Sun, Hui; Wu, Ruige; Zhao, Wenfeng

    2015-01-01

    Capillary electrophoresis (CE) and microfluidic chip (MC) devices are relatively mature technologies, but this book demonstrates how they can be integrated into a single, revolutionary device that can provide on-site analysis of samples when laboratory services are unavailable. By introducing the combination of CE and MC technology, Microfluidic Chip-Capillary Electrophoresis Devices broadens the scope of chemical analysis, particularly in the biomedical, food, and environmental sciences. The book gives an overview of the development of MC and CE technology as well as technology that now allows for the fabrication of MC-CE devices. It describes the operating principles that make integration possible and illustrates some achievements already made by the application of MC-CE devices in hospitals, clinics, food safety, and environmental research. The authors envision further applications for private and public use once the proof-of-concept stage has been passed and obstacles to increased commercialization are ad...

  14. Heat toxicant contaminant mitigation in potato chips

    DEFF Research Database (Denmark)

    Mariotti, Maria; Cortes, Pablo; Fromberg, Arvid

    2015-01-01

    Heating foods immersed in oil during frying provides many attractive sensorial attributes including taste, flavor and color. However, some toxic compounds formed during frying of potatoes such as furan and acrylamide may constitute an increased cancer risk for consumers. The objective of this work...... was to mitigate the furan and acrylamide formation in potato chips without increasing their oil uptake by optimizing the blanching treatment before final frying. Potato slices were blanched in order to simultaneously leach out ascorbic acid and reducing sugars, the most important precursors of furan...... and acrylamide generation in thermally treated starchy foods. A central composite design was implemented to optimize the temperature-time blanching conditions under which furan, acrylamide and oil content in potato chips were minimized. The optimum blanching conditions were 64 degrees C and 17 min in which...

  15. Technology Roadmap: Lab-on-a-Chip

    OpenAIRE

    Pattharaporn Suntharasaj; Tugrul U Daim

    2010-01-01

    With the integration of microfluidic and MEMS technologies, biochips such as the lab-on-a-chip (LOC) devices are at the brink of revolutionizing the medical disease diagnostics industries. Remarkable advancements in the biochips industry are making products resembling Star Trek.s "tricorder" and handheld medical scanners a reality. Soon, doctors can screen for cancer at the molecular level without costly and cumbersome equipments, and discuss treatment plans based on immediate lab results. Th...

  16. Silicon-Chip-Based Optical Frequency Combs

    Science.gov (United States)

    2015-10-26

    fiber-based polarization controllers and a polarization beam splitter , and the output power is monitored with a sensitive photodiode. We use a...a single CW laser beam coupled to a microresonators can produce stabilized, octave-spanning combs through highly cascaded four-wave mixing (FWM...resonator designs , the resonator and the coupling waveguide are monolithically integrated. Thus, the entire on-chip configuration of CMOS-compatible

  17. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  18. A single chip with multiple talents

    CERN Multimedia

    Francesco Poppi

    2010-01-01

    The Medipix chips developed at CERN are being used in a variety of fields: from medicine to education and back to high-tech engineering. The scene is set for a bright future for this versatile technology.   The Medipix chip. It didn’t take long for a brilliant team of physicists and engineers who were working on pixel detectors for the LHC to realize that the technology had great potential in medical imaging. This was the birth of the Medipix project. Fifteen years later, with the collaboration of 18 research institutes, the team has produced an advanced version of the initial ideas: Medipix3 is a device that can measure very accurately the position and energy of the photons (one by one) that hit the associated detector. Radiography and computed tomography (CT) use X-ray photons to study the human body. The different energies of the photons in the beam can be thought of as the colours of the X-ray spectrum. This is why the use of Medipix3 chips in such diagnostic techniques is referred...

  19. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  20. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  1. A primary battery-on-a-chip using monolayer graphene

    Science.gov (United States)

    Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

    2016-07-01

    We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

  2. Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

    DEFF Research Database (Denmark)

    2000-01-01

    towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

  3. Firing with wood chips in heating and cogeneration plants

    International Nuclear Information System (INIS)

    Kofman, P.D.

    1992-01-01

    The document was produced for use as detailed teaching material aimed at spreading information on the use of wood chips as fuel for heating and cogeneration plants. It includes information and articles on wood fuels generally, combustion values, chopping machines, suppliers, occupational health hazards connected with the handling of wood chips, measuring amounts, the selection of types, prices, ash, environmental aspects and information on the establishment of a wood-chip fired district heating plant. (AB)

  4. Wood chips procurement and research project at the Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1996-01-01

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m 3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m 3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m 3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m 3 /ha

  5. Experiment list: SRX485216 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from rhino germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fema...le || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3

  6. Experiment list: SRX485222 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 4me2 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimethy

  7. Experiment list: SRX485221 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K4me2 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimeth

  8. Experiment list: SRX485215 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from rhino germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=femal...e || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3 a

  9. Experiment list: SRX485218 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_name...=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 anti

  10. Experiment list: SRX485213 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  11. Experiment list: SRX485214 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  12. Experiment list: SRX485217 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from piwi germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 ant

  13. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  14. The Cutting Process, Chips and Cutting Forces in Machining CFRP

    DEFF Research Database (Denmark)

    Koplev, A.; Lystrup, Aage; Vorm, T.

    1983-01-01

    The cutting of unidirectional CFRP, perpendicular as well as parallel to the fibre orientation, is examined. Shaping experiments, ‘quick-stop’ experiments, and a new chip preparation technique are used for the investigation. The formation of the chips, and the quality of the machined surface...... is discussed. The cutting forces parallel and perpendicular to the cutting direction are measured for various parameters, and the results correlated to the formation of chips and the wear of the tool....

  15. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally...

  16. Integrated lasers for polymer Lab-on-a-Chip systems

    DEFF Research Database (Denmark)

    Mappes, Timo; Vannahme, Christoph; Grosmann, Tobias

    2012-01-01

    We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers.......We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers....

  17. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  18. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  19. Methods for size classification of wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Hartmann, Hans; Boehm, Thorsten [Technologie- und Foerderzentrum im Kompetenzzentrum fuer Nachwachsende Rohstoffe (TFZ), Schulgasse 18, D-94315 Straubing (Germany); Daugbjerg Jensen, Peter [Forest and Landscape FLD, The Royal Veterinary and Agricultural University, Rolighedsvej 23, DK-1958 Frederiksberg C (Denmark); Temmerman, Michaeel; Rabier, Fabienne [Centre wallon de Recherches agronomiques CRA-W Departement Genie rural, 146, Chaussee de Namur, B-5030 Gembloux (Belgium); Golser, Michael [Holzforschung Austria HFA Franz Grill-Stra beta e 7, A-1031 Wien (Austria)

    2006-11-15

    Methods for size classification of wood chips were analysed in an international round robin using 13 conventional wood chip samples and two specially prepared standard samples, one from wood chips and one from hog fuel. The true size distribution of these two samples (according to length, width and height) had been determined stereometrically (reference method) using a digital calliper gauge and by weighing each of the about 7000 wood particles per sample. Five different horizontal and three rotary screening devices were tested using five different screen hole diameters (3.15, 8, 16, 45, 63mm, round holes). These systems are compared to a commercially available continuously measuring image analysis equipment. The results show that among the devices of a measuring principle-horizontal and rotary screening-the results are quite comparable, while there is a severe incompatibility when distributions are determined by different measuring principles. Highest conformity with the reference values is given for measurements with an image analysis system, whereas for all machines with horizontal screens the median value of the size distribution only reached between one-third to half of the reference median value for the particle length distribution. These deviations can be attributed to a higher particle misplacement, which is particularly found in the larger fractions. Such differences decrease when the particle's shape is more roundish (i.e. sphericity closer to one). The median values of length distributions from screenings with a rotary classifier are between the measurements from an image analysis and horizontal screening devices. (author)

  20. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  1. Architectures for single-chip image computing

    Science.gov (United States)

    Gove, Robert J.

    1992-04-01

    This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

  2. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

    Science.gov (United States)

    Lee, Dasheng

    2008-01-01

    In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

  3. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    Dasheng Lee

    2008-12-01

    Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

  4. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

    Science.gov (United States)

    Lee, Dasheng

    2008-12-02

    In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

  5. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H.; Seppaenen, V.

    1996-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  6. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H; Seppaenen, V

    1997-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  7. An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

    Science.gov (United States)

    Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

    2001-11-01

    The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

  8. Experiment list: SRX507380 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=anti-HP1 || chip antibody vend...1770: WT anti-HP1- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_anti-HP1 || strain=piwi/

  9. Experiment list: SRX507384 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=Anti-H3K4me2 || chip antibody ... Anti-H3K4me2- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_Anti-H3K4me2 || strain=piwi/

  10. Experiment list: SRX507382 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=Anti-H3K9me3 || chip antibody ... Anti-H3K9me3- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_Anti-H3K9me3 || strain=piwi/

  11. The Chip-Scale Atomic Clock - Recent Development Progress

    Science.gov (United States)

    2004-09-01

    35th Annual Precise Time and Time Interval (PTTI) Meeting 467 THE CHIP-SCALE ATOMIC CLOCK – RECENT DEVELOPMENT PROGRESS R. Lutwak ...1] R. Lutwak , et al., 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs. Conventional Interrogation,” in

  12. A microfluidic chip for electrochemical conversions in drug metabolism studies

    NARCIS (Netherlands)

    Odijk, Mathieu; Baumann, A.; Lohmann, W.; van den Brink, Floris Teunis Gerardus; Olthuis, Wouter; Karst, U.; van den Berg, Albert

    2009-01-01

    We have designed a microfluidic microreactor chip for electrochemical conversion of analytes, containing a palladium reference electrode and platinum working and counter electrodes. The counter electrode is placed in a separate side-channel on chip to prevent unwanted side-products appearing in the

  13. A Process Technology For Conversion Of Dried Cassava Chips Into ...

    African Journals Online (AJOL)

    “Gari”, made from fermented bitter Cassava roots (Manihot esculenta crantz) were successfully processed from already dried Cassava chips at 7% moisture level. Cassava mash at 67% moisture was prepared from dried Cassava chips. This was seeded severally with fresh cassava mash and fermented for 72hours.

  14. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  15. Experiment list: SRX144526 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available stein-Barr Virus transformed 11803840,92.5,91.6,38 GSM922971: NRF2 ChIP vehicle treated rep2; Homo sapiens; ...ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_provider=Coriell; h

  16. Experiment list: SRX176063 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Carcinoma 11279321,95.5,3.6,13985 GSM984395: LNCAP ACH3 vehicle; Homo sapiens; ChIP-Seq source_name=prostat...e cancer cells || cell line=LNCaP || chip antibody=AcH3 || chip antibody manufacturer=Millipore || treatment=EtOH vehicle

  17. Experiment list: SRX176057 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nosis=Carcinoma 21582823,90.1,7.3,1074 GSM984389: 22RV1 AR vehicle; Homo sapiens; ChIP-Seq source_name=prost...ate cancer cells || cell line=22RV1 || chip antibody=AR || chip antibody manufacturer=Abcam || treatment=EtOH vehicle

  18. Experiment list: SRX176054 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nosis=Carcinoma 13338805,91.2,4.9,792 GSM984386: LNCAP AR vehicle; Homo sapiens; ChIP-Seq source_name=prosta...te cancer cells || cell line=LNCaP || chip antibody=AR || chip antibody manufacturer=Abcam || treatment=EtOH vehicle

  19. Experiment list: SRX176067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available sis=Carcinoma 6619400,91.7,7.2,13648 GSM984399: LNCAP H3K4ME3 vehicle; Homo sapiens; ChIP-Seq source_name=pr...ostate cancer cells || cell line=LNCaP || chip antibody=H3K4Me3 || chip antibody manufacturer=Millipore || treatment=EtOH vehicle

  20. Experiment list: SRX144527 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 8704444,92.1,92.5,9 GSM922972: NRF2 ChIP vehicle... treated rep3; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_pr

  1. Experiment list: SRX144525 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 14487710,85.8,82.8,188 GSM922970: NRF2 ChIP vehicle... treated rep1; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial

  2. Experiment list: SRX144524 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 4766716,6.2,89.4,0 GSM922969: NRF2 ChIP vehicle... treated pilot; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_pr

  3. Single-chip microcomputer application in nuclear radiation monitoring instruments

    International Nuclear Information System (INIS)

    Zhang Songshou

    1994-01-01

    The single-chip microcomputer has advantage in many respects i.e. multiple function, small size, low-power consumption,reliability etc. It is widely used now in industry, instrumentation, communication and machinery. The author introduced usage of single-chip microcomputer in nuclear radiation monitoring instruments for control, linear compensation, calculation, changeable parameter presetting and military training

  4. Experiment list: SRX352046 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available SM1232564: CSB M CHIP; Homo sapiens; ChIP-Seq source_name=fibroblast_menadione_CSB-ChIP || cell type=fibroblast || treated with=menad...ione || chip antibody=Mouse monoclonal anti-CSB N Terminus (1B1) http://dbarchive.b

  5. Experiment list: SRX262797 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3T3_SAP1_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechnolo...gy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  6. Experiment list: SRX262799 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_SAP1_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  7. Experiment list: SRX262781 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available _name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biotec...hnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  8. Experiment list: SRX262786 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_MRTFA_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  9. Experiment list: SRX262791 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFB_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-B || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  10. Experiment list: SRX262782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available echnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9...ce_name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biot

  11. Experiment list: SRX262788 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_UO || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechn...ology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eac

  12. Experiment list: SRX262787 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  13. Experiment list: SRX262780 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/...e_name=NIH3T3_SRF_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biote

  14. Experiment list: SRX319552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available embryonic stem cells || genotype/variation=expressing Flag-bio tagged E2F4 || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  15. Experiment list: SRX112179 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =OS25 ES cells || chip antibody=H5 (MMS-129R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads=Magnetic bea...ds http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  16. Experiment list: SRX112176 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  17. An automatic system for elaboration of chip breaking diagrams

    DEFF Research Database (Denmark)

    Andreasen, Jan Lasson; De Chiffre, Leonardo

    1998-01-01

    A laboratory system for fully automatic elaboration of chip breaking diagrams has been developed and tested. The system is based on automatic chip breaking detection by frequency analysis of cutting forces in connection with programming of a CNC-lathe to scan different feeds, speeds and cutting...

  18. Solving wood chip transport problems with computer simulation.

    Science.gov (United States)

    Dennis P. Bradley; Sharon A. Winsauer

    1976-01-01

    Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

  19. Experiment list: SRX185915 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available mo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 |...| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_tar

  20. Experiment list: SRX153147 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...on=Pleura|Tissue Diagnosis=Adenocarcinoma 64054379,98.7,5.2,764 GSM946851: MCF7 H3K27me3; Homo sapiens; ChIP

  1. Experiment list: SRX153146 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...n=Pleura|Tissue Diagnosis=Adenocarcinoma 60170246,98.4,5.7,16756 GSM946850: MCF7 H3K27ac; Homo sapiens; ChIP

  2. Experiment list: SRX185909 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  3. Experiment list: SRX153148 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...n=Pleura|Tissue Diagnosis=Adenocarcinoma 57306360,95.7,15.1,2666 GSM946852: MCF7 H3K9me3; Homo sapiens; ChIP

  4. Experiment list: SRX185917 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  5. Experiment list: SRX150568 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59265240,72.4,16.4,4779 GSM935489: Harvard ChipSeq HeLa-S3 RPC155 std source_name=HeLa-S3 ...|| biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipS

  6. Experiment list: SRX150661 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59396606,71.7,11.1,1200 GSM935582: Harvard ChipSeq HeLa-S3 BRF1 std source_name=HeLa-S3 ||... biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  7. Experiment list: SRX150495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 62508352,67.6,8.4,1556 GSM935416: Harvard ChipSeq HeLa-S3 ZZZ3 std source_name=HeLa-S3 || ...biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  8. Experiment list: SRX150565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Adenocarcinoma 54953593,74.3,12.2,1703 GSM935486: Harvard ChipSeq HeLa-S3 BDP1 std source_name=HeLa-S3 || b...iomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq |

  9. Experiment list: SRX150586 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Barr Virus 33195472,90.4,25.9,15633 GSM935507: Harvard ChipSeq GM12878 NF-YB IgG-mus source_name=GM12878 ||...?PgId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || dat

  10. Experiment list: SRX150496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ein-Barr Virus 63040797,85.0,19.7,1435 GSM935417: Harvard ChipSeq GM12878 SPT20 std source_name=GM12878 || b...gId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || datat

  11. Experiment list: SRX150585 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Barr Virus 32926476,94.0,12.0,2668 GSM935506: Harvard ChipSeq GM12878 NF-YA IgG-mus source_name=GM12878 || ...PgId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || data

  12. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...

  13. SNP typing on the NanoChip electronic microarray

    DEFF Research Database (Denmark)

    Børsting, Claus; Sanchez Sanchez, Juan Jose; Morling, Niels

    2005-01-01

    We describe a single nucleotide polymorphism (SNP) typing protocol developed for the NanoChip electronic microarray. The NanoChip array consists of 100 electrodes covered by a thin hydrogel layer containing streptavidin. An electric currency can be applied to one, several, or all electrodes...

  14. Exploration within the Network-on-Chip Paradigm

    NARCIS (Netherlands)

    Wolkotte, P.T.

    2009-01-01

    A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Its functionality and maximum clock frequency grew steadily over the years. Due to the continuous increase of the number of transistors available on-chip and the operational

  15. Experiment list: SRX119679 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 8,18360 GSM874985: ES.H3K27me3; Homo sapiens; ChIP-Seq source_name=H1 human Embryonic stem cells || cell line=H1 || treatment=diagnos...tic sample (pre-treatment) || chip antibody=H3K27me3 || chip antibody manufacturer=

  16. Experiment list: SRX119684 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 2,13603 GSM874990: ES.H3K79me2; Homo sapiens; ChIP-Seq source_name=H1 human Embryonic stem cell || cell line=H1 || treatment=diagnost...ic sample (pre-treatment) || chip antibody=H3K79me2 || chip antibody manufacturer=A

  17. Experiment list: SRX037432 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available s from PBMC, normal || gender=male || cell type=aTconv cells || chip antibody=H3K4me1 || chip antibody vendo...=peripheral blood mononuclear cells 14792460,17.0,2.9,5804 GSM648494: aTconv-H3K4me1 source_name=aTconv cell

  18. Experiment list: SRX485219 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 56 GSM1346560: RNA Polymerase II ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChI...P-Seq source_name=RNA Polymerase II ChIP from control germline knock-down ovaries || developmental stage=4-6... days old adult || Sex=female || tissue=ovary || germline knock-down=control || c

  19. Experiment list: SRX107410 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Adenocarcinoma 37378122,96.3,56.7,376 GSM838388: h3k36me3 si23 ChIP-Seq; Homo sapiens; ChIP-Seq source_name=Hela cells knock...down Med23 || chip antibody=H3K36me3 || treatment=knockdown Med23 || cell line=HeLa || chip

  20. On-chip integrated lasers for biophotonic applications

    DEFF Research Database (Denmark)

    Mappes, Timo; Wienhold, Tobias; Bog, Uwe

    Meeting the need of biomedical users, we develop disposable Lab-on-a-Chip systems based on commercially available polymers. We are combining passive microfluidics with active optical elements on-chip by integrating multiple solid-state and liquid-core lasers. While covering a wide range of laser ...

  1. Experiment list: SRX160914 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available M970829: IgG for KSHV LANA; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, IgG ChIP || ...cell line=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=Rabbit IgG [Sant

  2. Experiment list: SRX151246 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 11: SMC1 ChIPSeq; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, SMC1 ChIP || cell line...=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=rabbit anti-SMC1 || antib

  3. Experiment list: SRX160915 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available M970828: IgG for CTCF SMC1; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, IgG ChIP || ...cell line=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=Mouse IgG [Santa

  4. Experiment list: SRX151245 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 0: CTCF ChIPSeq; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, CTCF ChIP || cell line=...BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=rabbit anti-CTCF || antibo

  5. Cassava chips quality as influenced by cultivar, blanching time and ...

    African Journals Online (AJOL)

    Currently, fried cassava chips and crisps are increasingly being consumed as snacks; and fried cassava chips are produced by street processors. The quality and safety of these products is not known, therefore, the current study was to establish the influence of cassava cultivar, blanching time and slice thickness on quality ...

  6. Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

    Science.gov (United States)

    Shih, T. I.; Duh, J. G.

    2008-06-01

    The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

  7. Modelling, Synthesis, and Configuration of Networks-on-Chips

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo

    This thesis presents three contributions in two different areas of network-on-chip and system-on-chip research: Application modelling and identifying and solving different optimization problems related to two specific network-on-chip architectures. The contribution related to application modelling...... is an analytical method for deriving the worst-case traffic pattern caused by an application and the cache-coherence protocol in a cache-coherent shared-memory system. The contributions related to network-on-chip optimization problems consist of two parts: The development and evaluation of six heuristics...... for solving the network synthesis problem in the MANGO network-on-chip, and the identification and formalization of the ReNoC configuration problem together with three heuristics for solving it....

  8. Research of Dielectric Breakdown Micro fluidic Sampling Chip

    International Nuclear Information System (INIS)

    Jiang, F.; Lei, Y.; Yu, J.

    2013-01-01

    Micro fluidic chip is mainly driven electrically by external electrode and array electrode, but there are certain disadvantages in both of ways, which affect the promotion and application of micro fluidic technology. This paper discusses a scheme that uses the conductive solution in a microchannel made by PDMS, replacing electrodes and the way of dielectric breakdown to achieve microfluidic chip driver. It could reduce the driving voltage and simplify the chip production process. To prove the feasibility of this method, we produced a micro fluidic chip used in PDMS material with the lithography technology and experimented it. The results showed that using the dielectric breakdown to achieve microfluidic chip driver is feasible, and it has certain application prospect.

  9. Reagent-loaded plastic microfluidic chips for detecting homocysteine

    International Nuclear Information System (INIS)

    Suk, Ji Won; Jang, Jae-Young; Cho, Jun-Hyeong

    2008-01-01

    This report describes the preliminary study on plastic microfluidic chips with pre-loaded reagents for detecting homocysteine (Hcy). All reagents needed in an Hcy immunoassay were included in a microfluidic chip to remove tedious assay steps. A simple and cost-effective bonding method was developed to realize reagent-loaded microfluidic chips. This technique uses an intermediate layer between two plastic substrates by selectively patterning polydimethylsiloxane (PDMS) on the embossed surface of microchannels and fixing the substrates under pressure. Using this bonding method, the competitive immunoassay for SAH, a converted form of Hcy, was performed without any damage to reagents in chips, and the results showed that the fluorescent signal from antibody antigen binding decreased as the SAH concentration increased. Based on the SAH immunoassay, whole immunoassay steps for Hcy detection were carried out in plastic microfluidic chips with all necessary reagents. These experiments demonstrated the feasibility of the Hcy immunoassay in microfluidic devices

  10. Optical continuum generation on a silicon chip

    Science.gov (United States)

    Jalali, Bahram; Boyraz, Ozdal; Koonath, Prakash; Raghunathan, Varun; Indukuri, Tejaswi; Dimitropoulos, Dimitri

    2005-08-01

    Although the Raman effect is nearly two orders of magnitude stronger than the electronic Kerr nonlinearity in silicon, under pulsed operation regime where the pulse width is shorter than the phonon response time, Raman effect is suppressed and Kerr nonlinearity dominates. Continuum generation, made possible by the non-resonant Kerr nonlinearity, offers a technologically and economically appealing path to WDM communication at the inter-chip or intra-chip levels. We have studied this phenomenon experimentally and theoretically. Experimentally, a 2 fold spectral broadening is obtained by launching ~4ps optical pulses with 2.2GW/cm2 peak power into a conventional silicon waveguide. Theoretical calculations, that include the effect of two-photon-absorption, free carrier absorption and refractive index change indicate that up to >30 times spectral broadening is achievable in an optimized device. The broadening is due to self phase modulation and saturates due to two photon absorption. Additionally, we find that free carrier dynamics also contributes to the spectral broadening and cause the overall spectrum to be asymmetric with respect to the pump wavelength.

  11. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  12. Biosensors-on-chip: a topical review

    International Nuclear Information System (INIS)

    Chen, Sensen; Shamsi, Mohtashim H

    2017-01-01

    This review will examine the integration of two fields that are currently at the forefront of science, i.e. biosensors and microfluidics. As a lab-on-a-chip (LOC) technology, microfluidics has been enriched by the integration of various detection tools for analyte detection and quantitation. The application of such microfluidic platforms is greatly increased in the area of biosensors geared towards point-of-care diagnostics. Together, the merger of microfluidics and biosensors has generated miniaturized devices for sample processing and sensitive detection with quantitation. We believe that microfluidic biosensors (biosensors-on-chip) are essential for developing robust and cost effective point-of-care diagnostics. This review is relevant to a variety of disciplines, such as medical science, clinical diagnostics, LOC technologies including MEMs/NEMs, and analytical science. Specifically, this review will appeal to scientists working in the two overlapping fields of biosensors and microfluidics, and will also help new scientists to find their directions in developing point-of-care devices. (topical review)

  13. Nano technologies for Biosensor and Bio chip

    International Nuclear Information System (INIS)

    Kim, I.M.; Park, T.J.; Paskaleva, E.E.; Sun, F.; Seo, J.W.; Mehta, K.K.

    2015-01-01

    The bio sensing devices are characterized by their biological receptors, which have specificity to their corresponding analytes. These analytes are a vast and diverse group of biological molecules, DNAs, proteins (such as antibodies), fatty acids, or entire biological systems, such as pathogenic bacteria, viruses, cancerous cells, or other living organisms. A main challenge in the development of biosensor applications is the efficient recognition of a biological signal in a low signal-to-noise ratio environment, and its transduction into an electrochemical, optical, or other signals. The advent of nano material technology greatly increased the potential for achieving exquisite sensitivity of such devises, due to the innate high surface-to-volume ratio and high reactivity of the nano material. The second major challenge facing the biosensor application, that of sca lability, is addressed by multiplexing and miniaturizing of the biosensor devises into a bio chip. In recent years, biosensor and bio chip technologies have made significant progress by taking advantages of diverse kinds of nano materials that are derived from nano technology

  14. 75 FR 16149 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-April 26, 2010

    Science.gov (United States)

    2010-03-31

    ... DEPARTMENT OF HEALTH AND HUMAN SERVICES Centers for Medicare & Medicaid Services [CMS-2312-N] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP Working Group-- April 26, 2010 AGENCIES: Centers for Medicare & Medicaid Services (CMS), Department of...

  15. 75 FR 30046 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-June 14, 2010

    Science.gov (United States)

    2010-05-28

    ..., Employee Benefits Security Administration, DOL at (202) 693-8335. News media representatives must contact... eligible for benefits under titles XIX or XXI of the Social Security Act (the Act) to enable them to enroll...] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP...

  16. On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

    Directory of Open Access Journals (Sweden)

    Jian Lu

    2008-01-01

    Full Text Available A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC. We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

  17. FY1995 trial production of brain functional chip; 1995 nendo no kino shuseki chip no shisaku

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The present computer system will run on a program which is prepared in advance. On the other hand, the human brain can acquire some processes from learning with experiments. It would be very useful us human nature, if these learning process should be build up artificially. Our aim is to reveal basic self-acquiring mechanism of information and its processes of the brain, and preliminary research, including theoretical problems, for building up specialized processor chip. Many research on the brain have been held at the views of scientifically and medically. However; we focused on the principle brain learning process itself. The results of the research was directly realized on a specialized processor chip tuned for high-speed simulation of neural network. We could pointed out some problems on the present brain type processor, and discussed about basic technique for implementation of the next age brain type processor and theories. (NEDO)

  18. Rework of flip chip bonded radiation pixel detectors

    International Nuclear Information System (INIS)

    Vaehaenen, S.; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S.

    2008-01-01

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process

  19. Rework of flip chip bonded radiation pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Vaehaenen, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)], E-mail: sami.vahanen@vtt.fi; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)

    2008-06-11

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process.

  20. An automatic chip structure optical inspection system for electronic components

    Science.gov (United States)

    Song, Zhichao; Xue, Bindang; Liang, Jiyuan; Wang, Ke; Chen, Junzhang; Liu, Yunhe

    2018-01-01

    An automatic chip structure inspection system based on machine vision is presented to ensure the reliability of electronic components. It consists of four major modules, including a metallographic microscope, a Gigabit Ethernet high-resolution camera, a control system and a high performance computer. An auto-focusing technique is presented to solve the problem that the chip surface is not on the same focusing surface under the high magnification of the microscope. A panoramic high-resolution image stitching algorithm is adopted to deal with the contradiction between resolution and field of view, caused by different sizes of electronic components. In addition, we establish a database to storage and callback appropriate parameters to ensure the consistency of chip images of electronic components with the same model. We use image change detection technology to realize the detection of chip images of electronic components. The system can achieve high-resolution imaging for chips of electronic components with various sizes, and clearly imaging for the surface of chip with different horizontal and standardized imaging for ones with the same model, and can recognize chip defects.