VLSI design

CERN Document Server

Chandrasetty, Vikram Arkalgud

2011-01-01

This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Multi-valued LSI/VLSI logic design

Science.gov (United States)

Santrakul, K.

A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

Modeling selective attention using a neuromorphic analog VLSI device.

Science.gov (United States)

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Applications of VLSI circuits to medical imaging

International Nuclear Information System (INIS)

O'Donnell, M.

1988-01-01

In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

Hybrid VLSI/QCA Architecture for Computing FFTs

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Electro-optic techniques for VLSI interconnect

Science.gov (United States)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

Science.gov (United States)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

CERN Document Server

Pop, Paul; Madsen, Jan

2016-01-01

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

Modularly Integrated MEMS Technology

National Research Council Canada - National Science Library

Eyoum, Marie-Angie N

2006-01-01

Process design, development and integration to fabricate reliable MEMS devices on top of VLSI-CMOS electronics without damaging the underlying circuitry have been investigated throughout this dissertation...

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

Science.gov (United States)

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

GaAs integrated circuits and heterojunction devices

Science.gov (United States)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Artificial immune system algorithm in VLSI circuit configuration

Science.gov (United States)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

A second generation 50 Mbps VLSI level zero processing system prototype

Science.gov (United States)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Built-in self-repair of VLSI memories employing neural nets

Science.gov (United States)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Test methods of total dose effects in very large scale integrated circuits

International Nuclear Information System (INIS)

He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

2004-01-01

A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

How complex can integrated optical circuits become?

NARCIS (Netherlands)

Smit, M.K.; Hill, M.T.; Baets, R.G.F.; Bente, E.A.J.M.; Dorren, H.J.S.; Karouta, F.; Koenraad, P.M.; Koonen, A.M.J.; Leijtens, X.J.M.; Nötzel, R.; Oei, Y.S.; Waardt, de H.; Tol, van der J.J.G.M.; Khoe, G.D.

2007-01-01

The integration scale in Photonic Integrated Circuits will be pushed to VLSI-level in the coming decade. This will bring major changes in both application and manufacturing. In this paper developments in Photonic Integration are reviewed and the limits for reduction of device demensions are

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Science.gov (United States)

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

VLSI structures for track finding

International Nuclear Information System (INIS)

Dell'Orso, M.

1989-01-01

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

NASA Space Engineering Research Center for VLSI systems design

Science.gov (United States)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

A neuromorphic VLSI device for implementing 2-D selective attention systems.

Science.gov (United States)

Indiveri, G

2001-01-01

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Science.gov (United States)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

Metal semiconductor contacts and devices

CERN Document Server

Cohen, Simon S; Einspruch, Norman G

1986-01-01

VLSI Electronics Microstructure Science, Volume 13: Metal-Semiconductor Contacts and Devices presents the physics, technology, and applications of metal-semiconductor barriers in digital integrated circuits. The emphasis is placed on the interplay among the theory, processing, and characterization techniques in the development of practical metal-semiconductor contacts and devices.This volume contains chapters that are devoted to the discussion of the physics of metal-semiconductor interfaces and its basic phenomena; fabrication procedures; and interface characterization techniques, particularl

Lithography for VLSI

CERN Document Server

Einspruch, Norman G

1987-01-01

VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

CERN Document Server

Shirur, Yasha; Prasad, Rekha

2013-01-01

This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

Science.gov (United States)

Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

2003-01-01

Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

Analysis and simulation of semiconductor devices

CERN Document Server

Selberherr, Siegfried

1984-01-01

The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

Energy Technology Data Exchange (ETDEWEB)

Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

1992-01-01

The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

VLSI Design of Trusted Virtual Sensors

Directory of Open Access Journals (Sweden)

Macarena C. Martínez-Rodríguez

2018-01-01

Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

VLSI Design of Trusted Virtual Sensors.

Science.gov (United States)

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

Advanced symbolic analysis for VLSI systems methods and applications

CERN Document Server

Shi, Guoyong; Tlelo Cuautle, Esteban

2014-01-01

This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

VLSI implementations for image communications

CERN Document Server

Pirsch, P

1993-01-01

The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

Science.gov (United States)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

Science.gov (United States)

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

VLSI Design with Alliance Free CAD Tools: an Implementation Example

Directory of Open Access Journals (Sweden)

Chávez-Bracamontes Ramón

2015-07-01

Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

Science.gov (United States)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

Science.gov (United States)

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Opto-VLSI-based reconfigurable free-space optical interconnects architecture

DEFF Research Database (Denmark)

Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

2007-01-01

is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

Thin film device applications

CERN Document Server

Kaur, Inderjeet

1983-01-01

Two-dimensional materials created ab initio by the process of condensation of atoms, molecules, or ions, called thin films, have unique properties significantly different from the corresponding bulk materials as a result of their physical dimensions, geometry, nonequilibrium microstructure, and metallurgy. Further, these characteristic features of thin films can be drasti­ cally modified and tailored to obtain the desired and required physical characteristics. These features form the basis of development of a host of extraordinary active and passive thin film device applications in the last two decades. On the one extreme, these applications are in the submicron dimensions in such areas as very large scale integration (VLSI), Josephson junction quantum interference devices, magnetic bubbles, and integrated optics. On the other extreme, large-area thin films are being used as selective coatings for solar thermal conversion, solar cells for photovoltaic conver­ sion, and protection and passivating layers. Ind...

A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

Science.gov (United States)

Shi, Cong; Luo, Gang

2018-04-01

This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

National Research Council Canada - National Science Library

Horiuchi, Timothy K; Krishnaprasad, P. S

2007-01-01

.... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Formal verification an essential toolkit for modern VLSI design

CERN Document Server

Seligman, Erik; Kumar, M V Achutha Kiran

2015-01-01

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

VLSI signal processing technology

CERN Document Server

Swartzlander, Earl

1994-01-01

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

Particle interaction and displacement damage in silicon devices operated in radiation environments

International Nuclear Information System (INIS)

Leroy, Claude; Rancoita, Pier-Giorgio

2007-01-01

Silicon is used in radiation detectors and electronic devices. Nowadays, these devices achieving submicron technology are parts of integrated circuits of large to very large scale integration (VLSI). Silicon and silicon-based devices are commonly operated in many fields including particle physics experiments, nuclear medicine and space. Some of these fields present adverse radiation environments that may affect the operation of the devices. The particle energy deposition mechanisms by ionization and non-ionization processes are reviewed as well as the radiation-induced damage and its effect on device parameters evolution, depending on particle type, energy and fluence. The temporary or permanent damage inflicted by a single particle (single event effect) to electronic devices or integrated circuits is treated separately from the total ionizing dose (TID) effect for which the accumulated fluence causes degradation and from the displacement damage induced by the non-ionizing energy-loss (NIEL) deposition. Understanding of radiation effects on silicon devices has an impact on their design and allows the prediction of a specific device behaviour when exposed to a radiation field of interest

Nano lasers in photonic VLSI

NARCIS (Netherlands)

Hill, M.T.; Oei, Y.S.; Smit, M.K.

2007-01-01

We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

VLSI and system architecture-the new development of system 5G

Energy Technology Data Exchange (ETDEWEB)

Sakamura, K.; Sekino, A.; Kodaka, T.; Uehara, T.; Aiso, H.

1982-01-01

A research and development proposal is presented for VLSI CAD systems and for a hardware environment called system 5G on which the VLSI CAD systems run. The proposed CAD systems use a hierarchically organized design language to enable design of anything from basic architectures of VLSI to VLSI mask patterns in a uniform manner. The cad systems will eventually become intelligent cad systems that acquire design knowledge and perform automatic design of VLSI chips when the characteristic requirements of VLSI chip is given. System 5G will consist of superinference machines and the 5G communication network. The superinference machine will be built based on a functionally distributed architecture connecting inferommunication network. The superinference machine will be built based on a functionally distributed architecture connecting inference machines and relational data base machines via a high-speed local network. The transfer rate of the local network will be 100 mbps at the first stage of the project and will be improved to 1 gbps. Remote access to the superinference machine will be possible through the 5G communication network. Access to system 5G will use the 5G network architecture protocol. The users will access the system 5G using standardized 5G personal computers. 5G personal logic programming stations, very high intelligent terminals providing an instruction set that supports predicate logic and input/output facilities for audio and graphical information.

A multi coding technique to reduce transition activity in VLSI circuits

International Nuclear Information System (INIS)

Vithyalakshmi, N.; Rajaram, M.

2014-01-01

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

Guide to state-of-the-art electron devices

CERN Document Server

2013-01-01

Concise, high quality and comparative overview of state-of-the-art electron device development, manufacturing technologies and applications Guide to State-of-the-Art Electron Devices marks the 60th anniversary of the IEEE Electron Devices Committee and the 35th anniversary of the IEEE Electron Devices Society, as such it defines the state-of-the-art of electron devices, as well as future directions across the entire field. Spans full range of electron device types such as photovoltaic devices, semiconductor manufacturing and VLSI technology and circuits, covered by IEEE Electron and Devices Society Contributed by internationally respected members of the electron devices community A timely desk reference with fully-integrated colour and a unique lay-out with sidebars to highlight the key terms Discusses the historical developments and speculates on future trends to give a more rounded picture of the topics covered A valuable resource R&D managers; engineers in the semiconductor industry; applied scientists...

Las Vegas is better than determinism in VLSI and distributed computing

DEFF Research Database (Denmark)

Mehlhorn, Kurt; Schmidt, Erik Meineche

1982-01-01

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

Science.gov (United States)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

Science.gov (United States)

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

Handbook of VLSI chip design and expert systems

CERN Document Server

Schwarz, A F

1993-01-01

Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

Science.gov (United States)

2010-10-01

spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

Reliability data collection on IC and VLSI devices tested under accelerated life conditions

International Nuclear Information System (INIS)

Barry, D.M.; Meniconi, M.

1986-01-01

As part of a more general investigation into the reliability and failure causes of semiconductor devices, statistical samples of integrated circuit devices (LM741C) and dynamic random access memory devices (TMS4116) were tested destructively to failure using elevated temperature as the accelerating stress. The devices were operated during the life test and the failure data generated were collected automatically using a multiple question-and-answer program and a process control computer. The failure data were modelled from the lognormal, inverse Gaussian and Weibull distribution using an Arrhenius reaction rate model. The failed devices were later decapsulated for failure cause determination. (orig./DG)

VLSI 'smart' I/O module development

Science.gov (United States)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

Convolving optically addressed VLSI liquid crystal SLM

Science.gov (United States)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Integrated control rod monitoring device

International Nuclear Information System (INIS)

Saito, Katsuhiro

1997-01-01

The present invention provides a device in which an entire control rod driving time measuring device and a control rod position support device in a reactor building and a central control chamber are integrated systematically to save hardwares such as a signal input/output device and signal cables between boards. Namely, (1) functions of the entire control rod driving time measuring device for monitoring control rods which control the reactor power and a control rod position indication device are integrated into one identical system. Then, the entire devices can be made compact by the integration of the functions. (2) The functions of the entire control rod driving time measuring device and the control rod position indication device are integrated in a central operation board and a board in the site. Then, the place for the installation of them can be used in common in any of the cases. (3) The functions of the entire control rod driving time measuring device and the control rod position indication device are integrated to one identical system to save hardware to be used. Then, signal input/output devices and drift branching panel boards in the site and the central operation board can be saved, and cables for connecting both of the boards is no more necessary. (I.S.)

ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

Directory of Open Access Journals (Sweden)

V. I. Romanov

2016-01-01

Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

Integrated optoelectronic materials and circuits for optical interconnects

International Nuclear Information System (INIS)

Hutcheson, L.D.

1988-01-01

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

An efficient interpolation filter VLSI architecture for HEVC standard

Science.gov (United States)

Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

2015-12-01

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

Energy Technology Data Exchange (ETDEWEB)

Zhang, B

1999-07-01

This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

CERN Document Server

2015-01-01

This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

Multi-net optimization of VLSI interconnect

CERN Document Server

Moiseev, Konstantin; Wimer, Shmuel

2015-01-01

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

The VLSI handbook

CERN Document Server

Chen, Wai-Kai

2007-01-01

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

Directory of Open Access Journals (Sweden)

Fazal NOORBASHA

2012-08-01

Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

Science.gov (United States)

2007-03-31

IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

Parallel computation of nondeterministic algorithms in VLSI

Energy Technology Data Exchange (ETDEWEB)

Hortensius, P D

1987-01-01

This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

Proceedings of the workshop on new solid state devices for high energy physics

International Nuclear Information System (INIS)

1987-12-01

This paper contains articles on semiconductor devices used in the detection of high energy particles. Some articles reported: Position sensitive semiconductor devices; Scintillation techniques and optical devices; Radiation damage to detectors; VLSI for physics; and experience with Si detectors in NA32

VLSI-based video event triggering for image data compression

Science.gov (United States)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

A neural network device for on-line particle identification in cosmic ray experiments

International Nuclear Information System (INIS)

Scrimaglio, R.; Finetti, N.; D'Altorio, L.; Rantucci, E.; Raso, M.; Segreto, E.; Tassoni, A.; Cardarilli, G.C.

2004-01-01

On-line particle identification is one of the main goals of many experiments in space both for rare event studies and for optimizing measurements along the orbital trajectory. Neural networks can be a useful tool for signal processing and real time data analysis in such experiments. In this document we report on the performances of a programmable neural device which was developed in VLSI analog/digital technology. Neurons and synapses were accomplished by making use of Operational Transconductance Amplifier (OTA) structures. In this paper we report on the results of measurements performed in order to verify the agreement of the characteristic curves of each elementary cell with simulations and on the device performances obtained by implementing simple neural structures on the VLSI chip. A feed-forward neural network (Multi-Layer Perceptron, MLP) was implemented on the VLSI chip and trained to identify particles by processing the signals of two-dimensional position-sensitive Si detectors. The radiation monitoring device consisted of three double-sided silicon strip detectors. From the analysis of a set of simulated data it was found that the MLP implemented on the neural device gave results comparable with those obtained with the standard method of analysis confirming that the implemented neural network could be employed for real time particle identification

Harnessing VLSI System Design with EDA Tools

CERN Document Server

Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

2012-01-01

This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

Integrated lenses in polystyrene microfluidic devices

KAUST Repository

Fan, Yiqiang; Li, Huawei; Foulds, Ian G.

2013-01-01

This paper reports a new method for integrating microlenses into microfluidic devices for improved observation. Two demonstration microfluidic devices were provided which were fabricated using this new technique. The integrated microlenses were

High performance bio-integrated devices

Science.gov (United States)

Kim, Dae-Hyeong; Lee, Jongha; Park, Minjoon

2014-06-01

In recent years, personalized electronics for medical applications, particularly, have attracted much attention with the rise of smartphones because the coupling of such devices and smartphones enables the continuous health-monitoring in patients' daily life. Especially, it is expected that the high performance biomedical electronics integrated with the human body can open new opportunities in the ubiquitous healthcare. However, the mechanical and geometrical constraints inherent in all standard forms of high performance rigid wafer-based electronics raise unique integration challenges with biotic entities. Here, we describe materials and design constructs for high performance skin-mountable bio-integrated electronic devices, which incorporate arrays of single crystalline inorganic nanomembranes. The resulting electronic devices include flexible and stretchable electrophysiology electrodes and sensors coupled with active electronic components. These advances in bio-integrated systems create new directions in the personalized health monitoring and/or human-machine interfaces.

Trace-based post-silicon validation for VLSI circuits

CERN Document Server

Liu, Xiao

2014-01-01

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

A segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics for a PET scanner

CERN Document Server

Chesi, Enrico Guido; Joram, C; Mathot, S; Séguinot, Jacques; Weilhammer, P; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

2006-01-01

We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is put on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

Hardware Descriptive Languages: An Efficient Approach to Device ...

African Journals Online (AJOL)

Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

National Research Council Canada - National Science Library

Makhijani, Vinod

2002-01-01

...+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech...

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Directory of Open Access Journals (Sweden)

Sergio Saponara

2004-09-01

Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

A Knowledge Based Approach to VLSI CAD

Science.gov (United States)

1983-09-01

Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

CERN Document Server

Williams, John

2008-01-01

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

Integrated lenses in polystyrene microfluidic devices

KAUST Repository

Fan, Yiqiang

2013-04-01

This paper reports a new method for integrating microlenses into microfluidic devices for improved observation. Two demonstration microfluidic devices were provided which were fabricated using this new technique. The integrated microlenses were fabricated using a free-surface thermo-compression molding method on a polystyrene (PS) sheet which was then bonded on top of microfluidic channels as a cover plate, with the convex microlenses providing a magnified image of the channel for the easier observation of the flow in the microchannels. This approach for fabricating the integrated microlens in microfluidic devices is rapid, low cost and without the requirement of cleanroom facilities. © 2013 IEEE.

Numerical analysis of electromigration in thin film VLSI interconnections

NARCIS (Netherlands)

Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

1995-01-01

Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

Design of two easily-testable VLSI array multipliers

Energy Technology Data Exchange (ETDEWEB)

Ferguson, J.; Shen, J.P.

1983-01-01

Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Directory of Open Access Journals (Sweden)

T. Kalavathi Devi

2015-01-01

Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

International Nuclear Information System (INIS)

Jones, W.F.; Byars, L.G.; Casey, M.E.

1988-01-01

A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

VLSI top-down design based on the separation of hierarchies

NARCIS (Netherlands)

Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

1986-01-01

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Directory of Open Access Journals (Sweden)

Rachmad Vidya Wicaksana Putra

2016-06-01

Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

Energy Technology Data Exchange (ETDEWEB)

Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

Integrated Ultrasonic-Photonic Devices

DEFF Research Database (Denmark)

Barretto, Elaine Cristina Saraiva

in channel waveguides and Mach-Zehnder interferometers. Numerical models are developed based on the finite element method, and applied to several scenarios, such as optimization of the geometrical parameters of waveguides, use of slow light in photonic crystal waveguides and use of Lamb waves in membranized......This thesis deals with the modeling, design, fabrication and characterization of integrated ultrasonic-photonic devices, with particular focus on the use of standard semiconductor materials such as GaAs and silicon. The devices are based on the use of guided acoustic waves to modulate the light...... investigated. Comparisons are made with the numerical and experimental results, and they validate the obtained response of the acoustic and photonic components of the device. Finally, a new design for an optical frequency shifter is proposed, posing several advantages over existing devices in terms of size...

High performance VLSI telemetry data systems

Science.gov (United States)

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-01-01

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

VLSI architectures for modern error-correcting codes

CERN Document Server

Zhang, Xinmiao

2015-01-01

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

Integrated Optical lightguide device

NARCIS (Netherlands)

Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

2005-01-01

In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

Integrated Optical lightguide device

NARCIS (Netherlands)

Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

2000-01-01

In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

A novel VLSI processor for high-rate, high resolution spectroscopy

CERN Document Server

Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

2000-01-01

A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

Science.gov (United States)

Carvajal, Gonzalo; Figueroa, Miguel

2014-07-01

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

Simplified nonplanar wafer bonding for heterogeneous device integration

Science.gov (United States)

Geske, Jon; Bowers, John E.; Riley, Anton

2004-07-01

We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Directory of Open Access Journals (Sweden)

I. Hameem Shanavas

2014-01-01

Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

2008-01-21

In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

Development of an integrated pointing device driver for the disabled.

Science.gov (United States)

Shih, Ching-Hsiang; Shih, Ching-Tien

2010-01-01

To help people with disabilities such as those with spinal cord injury (SCI) to effectively utilise commercial pointing devices to operate computers. This study proposes a novel method to integrate the functions of commercial pointing devices. Utilising software technology to develop an integrated pointing device driver (IPDD) for a computer operating system. The proposed IPDD has the following benefits: (1) it does not require additional hardware cost or circuit preservations, (2) it supports all standard interfaces of commercial pointing devices, including PS/2, USB and wireless interfaces and (3) it can integrate any number of devices. The IPDD can be selected and combined according to their physical restriction. The IPDD is a novel method of integrating commercial pointing devices. Through IPDD, people with disabilities can choose a suitable combination of commercial pointing devices to achieve full cursor control and optimise operational performance. In contrast with previous studies, the software-based solution does not require additional hardware or circuit preservations, and it can support unlimited devices. In summary, the IPDD has the benefits of flexibility, low cost and high-device compatibility.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Drift chamber tracking with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-10-01

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

Si light-emitting device in integrated photonic CMOS ICs

Science.gov (United States)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

Integrated Photonic Devices Incorporating Low-Loss Fluorinated Polymer Materials

Directory of Open Access Journals (Sweden)

Hyung-Jong Lee

2011-06-01

Full Text Available Low-loss polymer materials incorporating fluorinated compounds have been utilized for the investigation of various functional optical devices useful for optical communication and optical sensor systems. Since reliability issues concerning the polymer device have been resolved, polymeric waveguide devices have been gradually adopted for commercial application systems. The two most successfully commercialized polymeric integrated optic devices, variable optical attenuators and digital optical switches, are reviewed in this paper. Utilizing unique properties of optical polymers which are not available in other optical materials, novel polymeric optical devices are proposed including widely tunable external cavity lasers and integrated optical current sensors.

The AMchip: A VLSI associative memory for track finding

International Nuclear Information System (INIS)

Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

1992-01-01

An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

Point DCT VLSI Architecture for Emerging HEVC Standard

OpenAIRE

Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

2012-01-01

This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

Atomic layer deposition for graphene device integration

NARCIS (Netherlands)

Vervuurt, R.H.J.; Kessels, W.M.M.; Bol, A.A.

2017-01-01

Graphene is a two dimensional material with extraordinary properties, which make it an interesting material for many optical and electronic devices. The integration of graphene in these devices often requires the deposition of thin dielectric layers on top of graphene. Atomic layer deposition (ALD)

VLSI architecture and design for the Fermat Number Transform implementation

Energy Technology Data Exchange (ETDEWEB)

Pajayakrit, A.

1987-01-01

A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

Integration in design and manufacturing of polymer smart devices

NARCIS (Netherlands)

Bolt, P.J.; Zwart, R.M. de; Tacken, R.A.; Rendering, H.

2009-01-01

Integration of functions in single components is pursued in order to manufacture smaller and smarter polymer micro devices at less cost, through e.g. less assembly steps. It requires integration on both product and production side. This paper addresses the use of molded interconnect device (MID)

Adaptive WTA with an analog VLSI neuromorphic learning chip.

Science.gov (United States)

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

Using Software Technology to Specify Abstract Interfaces in VLSI Design.

Science.gov (United States)

1985-01-01

with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

Sputtering materials for VLSI and thin film devices

CERN Document Server

Sarkar, Jaydeep

2010-01-01

An important resource for students, engineers and researchers working in the area of thin film deposition using physical vapor deposition (e.g. sputtering) for semiconductor, liquid crystal displays, high density recording media and photovoltaic device (e.g. thin film solar cell) manufacturing. This book also reviews microelectronics industry topics such as history of inventions and technology trends, recent developments in sputtering technologies, manufacturing steps that require sputtering of thin films, the properties of thin films and the role of sputtering target performance on overall p

Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

CERN Document Server

Williams, John Michael

2014-01-01

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

VLSI Technology for Cognitive Radio

Science.gov (United States)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

Directory of Open Access Journals (Sweden)

Di Wu

2010-01-01

Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

CMOS and BiCMOS process integration and device characterization

CERN Document Server

El-Kareh, Badih

2009-01-01

Covers both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. This book also covers silicon devices and integrated process technologies. It discusses modern silicon devices, their characteristics, and interactions with process parameters.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

International Nuclear Information System (INIS)

Jian Haifang; Shi Yin

2009-01-01

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

Energy Technology Data Exchange (ETDEWEB)

Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-07-15

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

Design of a VLSI Decoder for Partially Structured LDPC Codes

Directory of Open Access Journals (Sweden)

Fabrizio Vacca

2008-01-01

of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

Integrated Solar-Energy-Harvesting and -Storage Device

Science.gov (United States)

whitacre, Jay; Fleurial, Jean-Pierre; Mojarradi, Mohammed; Johnson, Travis; Ryan, Margaret Amy; Bugga, Ratnakumar; West, William; Surampudi, Subbarao; Blosiu, Julian

2004-01-01

A modular, integrated, completely solid-state system designed to harvest and store solar energy is under development. Called the power tile, the hybrid device consists of a photovoltaic cell, a battery, a thermoelectric device, and a charge-control circuit that are heterogeneously integrated to maximize specific energy capacity and efficiency. Power tiles could be used in a variety of space and terrestrial environments and would be designed to function with maximum efficiency in the presence of anticipated temperatures, temperature gradients, and cycles of sunlight and shadow. Because they are modular in nature, one could use a single power tile or could construct an array of as many tiles as needed. If multiple tiles are used in an array, the distributed and redundant nature of the charge control and distribution hardware provides an extremely fault-tolerant system. The figure presents a schematic view of the device.

DPL/Daedalus design environment (for VLSI)

Energy Technology Data Exchange (ETDEWEB)

Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

1981-01-01

The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

Integrating Touch-Enabled and Mobile Devices into Contemporary Mathematics Education

Science.gov (United States)

Meletiou-Mavrotheris, Maria, Ed.; Mavrou, Katerina, Ed.; Paparistodemou, Efi, Ed.

2015-01-01

Despite increased interest in mobile devices as learning tools, the amount of available primary research studies on their integration into mathematics teaching and learning is still relatively small due to the novelty of these technologies. "Integrating Touch-Enabled and Mobile Devices into Contemporary Mathematics Education" presents…

A full-duplex working integrated optoelectronic device for optical interconnect

Science.gov (United States)

Liu, Kai; Fan, Huize; Huang, Yongqing; Duan, Xiaofeng; Wang, Qi; Ren, Xiaomin; Wei, Qi; Cai, Shiwei

2018-05-01

In this paper, a full-duplex working integrated optoelectronic device is proposed. It is constructed by integrating a vertical cavity surface emitting laser (VCSEL) unit above a resonant cavity enhanced photodetector (RCE-PD) unit. Analysis shows that, the VCSEL unit has a threshold current of 1 mA and a slop efficiency of 0.66 W/A at 849.7 nm, the RCE-PD unit obtains its maximal absorption quantum efficiency of 90.24% at 811 nm with a FWHM of 4 nm. Moreover, the two units of the proposed integrated device can work independently from each other. So that the proposed integrated optoelectronic device can work full-duplex. It can be applied for single fiber bidirectional optical interconnects system.

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

A hybrid approach to device integration on a genetic analysis platform

International Nuclear Information System (INIS)

Brennan, Des; Justice, John; Aherne, Margaret; Galvin, Paul; Jary, Dorothee; Kurg, Ants; Berik, Evgeny; Macek, Milan

2012-01-01

Point-of-care (POC) systems require significant component integration to implement biochemical protocols associated with molecular diagnostic assays. Hybrid platforms where discrete components are combined in a single platform are a suitable approach to integration, where combining multiple device fabrication steps on a single substrate is not possible due to incompatible or costly fabrication steps. We integrate three devices each with a specific system functionality: (i) a silicon electro-wetting-on-dielectric (EWOD) device to move and mix sample and reagent droplets in an oil phase, (ii) a polymer microfluidic chip containing channels and reservoirs and (iii) an aqueous phase glass microarray for fluorescence microarray hybridization detection. The EWOD device offers the possibility of fully integrating on-chip sample preparation using nanolitre sample and reagent volumes. A key challenge is sample transfer from the oil phase EWOD device to the aqueous phase microarray for hybridization detection. The EWOD device, waveguide performance and functionality are maintained during the integration process. An on-chip biochemical protocol for arrayed primer extension (APEX) was implemented for single nucleotide polymorphism (SNiP) analysis. The prepared sample is aspirated from the EWOD oil phase to the aqueous phase microarray for hybridization. A bench-top instrumentation system was also developed around the integrated platform to drive the EWOD electrodes, implement APEX sample heating and image the microarray after hybridization. (paper)

An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

DEFF Research Database (Denmark)

Paaske, Erik; Pedersen, Steen; Sparsø, Jens

1991-01-01

Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

Extended device profiles and testing procedures for the approval process of integrated medical devices using the IEEE 11073 communication standard.

Science.gov (United States)

Janß, Armin; Thorn, Johannes; Schmitz, Malte; Mildner, Alexander; Dell'Anna-Pudlik, Jasmin; Leucker, Martin; Radermacher, Klaus

2018-02-23

Nowadays, only closed and proprietary integrated operating room systems (IORS) from big manufacturers are available on the market. Hence, the interconnection of components from third-party vendors is only possible with increased time and costs. In the context of the German Federal Ministry of Education and Research (BMBF)-funded project OR.NET (2012-2016), the open integration of medical devices from different manufacturers was addressed. An integrated operating theater based on the open communication standard IEEE 11073 shall give clinical operators the opportunity to choose medical devices independently of the manufacturer. This approach would be advantageous especially for hospital operators and small- and medium-sized enterprises (SME) of medical devices. Actual standards and concepts regarding technical feasibility and the approval process do not cope with the requirements for a modular integration of medical devices in the operating room (OR), based on an open communication standard. Therefore, innovative approval strategies and corresponding certification and test procedures, which cover actual legal and normative standards, have to be developed in order to support the future risk management and the usability engineering process of open integrated medical devices in the OR. The use of standardized device and service profiles and a three-step testing procedure, including conformity, interoperability and integration tests are described in this paper and shall support the manufacturers to integrate their medical devices without disclosing the medical devices' risk analysis and related confidential expertise or proprietary information.

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

Integrated multiscale modeling of molecular computing devices

International Nuclear Information System (INIS)

Cummings, Peter T; Leng Yongsheng

2005-01-01

Molecular electronics, in which single organic molecules are designed to perform the functions of transistors, diodes, switches and other circuit elements used in current siliconbased microelecronics, is drawing wide interest as a potential replacement technology for conventional silicon-based lithographically etched microelectronic devices. In addition to their nanoscopic scale, the additional advantage of molecular electronics devices compared to silicon-based lithographically etched devices is the promise of being able to produce them cheaply on an industrial scale using wet chemistry methods (i.e., self-assembly from solution). The design of molecular electronics devices, and the processes to make them on an industrial scale, will require a thorough theoretical understanding of the molecular and higher level processes involved. Hence, the development of modeling techniques for molecular electronics devices is a high priority from both a basic science point of view (to understand the experimental studies in this field) and from an applied nanotechnology (manufacturing) point of view. Modeling molecular electronics devices requires computational methods at all length scales - electronic structure methods for calculating electron transport through organic molecules bonded to inorganic surfaces, molecular simulation methods for determining the structure of self-assembled films of organic molecules on inorganic surfaces, mesoscale methods to understand and predict the formation of mesoscale patterns on surfaces (including interconnect architecture), and macroscopic scale methods (including finite element methods) for simulating the behavior of molecular electronic circuit elements in a larger integrated device. Here we describe a large Department of Energy project involving six universities and one national laboratory aimed at developing integrated multiscale methods for modeling molecular electronics devices. The project is funded equally by the Office of Basic

Fast-prototyping of VLSI

International Nuclear Information System (INIS)

Saucier, G.; Read, E.

1987-01-01

Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

Australian national networked tele-test facility for integrated systems

Science.gov (United States)

Eshraghian, Kamran; Lachowicz, Stefan W.; Eshraghian, Sholeh

2001-11-01

The Australian Commonwealth government recently announced a grant of 4.75 million as part of a 13.5 million program to establish a world class networked IC tele-test facility in Australia. The facility will be based on a state-of-the-art semiconductor tester located at Edith Cowan University in Perth that will operate as a virtual centre spanning Australia. Satellite nodes will be located at the University of Western Australia, Griffith University, Macquarie University, Victoria University and the University of Adelaide. The facility will provide vital equipment to take Australia to the frontier of critically important and expanding fields in microelectronics research and development. The tele-test network will provide state of the art environment for the electronics and microelectronics research and the industry community around Australia to test and prototype Very Large Scale Integrated (VLSI) circuits and other System On a Chip (SOC) devices, prior to moving to the manufacturing stage. Such testing is absolutely essential to ensure that the device performs to specification. This paper presents the current context in which the testing facility is being established, the methodologies behind the integration of design and test strategies and the target shape of the tele-testing Facility.

Simulation of worst-case operating conditions for integrated circuits operating in a total dose environment

International Nuclear Information System (INIS)

Bhuva, B.L.

1987-01-01

Degradations in the circuit performance created by the radiation exposure of integrated circuits are so unique and abnormal that thorough simulation and testing of VLSI circuits is almost impossible, and new ways to estimate the operating performance in a radiation environment must be developed. The principal goal of this work was the development of simulation techniques for radiation effects on semiconductor devices. The mixed-mode simulation approach proved to be the most promising. The switch-level approach is used to identify the failure mechanisms and critical subcircuits responsible for operational failure along with worst-case operating conditions during and after irradiation. For precise simulations of critical subcircuits, SPICE is used. The identification of failure mechanisms enables the circuit designer to improve the circuit's performance and failure-exposure level. Identification of worst-case operating conditions during and after irradiation reduces the complexity of testing VLSI circuits for radiation environments. The results of test circuits for failure simulations using a conventional simulator and the new simulator showed significant time savings using the new simulator. The savings in simulation time proved to be circuit topology-dependent. However, for large circuits, the simulation time proved to be orders of magnitude smaller than simulation time for conventional simulators

Integrated biocircuits: engineering functional multicellular circuits and devices

Science.gov (United States)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

Science.gov (United States)

Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

2016-01-01

A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

Science.gov (United States)

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Integrated circuit devices in control systems of coal mining complexes

Energy Technology Data Exchange (ETDEWEB)

1983-01-01

Systems of automatic monitoring and control of coal mining complexes developed in the 1960's used electromagnetic relays, thyristors, and flip-flops on transistors of varying conductivity. The circuits' designers, devoted much attention to ensuring spark safety, lowering power consumption, and raising noise immunity and repairability of functional devices. The fast development of integrated circuitry led to the use of microelectronic components in most devices of mine automation. An analysis of specifications and experimental research into integrated circuits (IMS) shows that the series K 176 IMS components made by CMOS technology best meet mine conditions of operation. The use of IMS devices under mine conditions has demonstrated their high reliability. Further development of integrated circuitry involve using microprocessors and microcomputers. (SC)

Advanced field-solver techniques for RC extraction of integrated circuits

CERN Document Server

Yu, Wenjian

2014-01-01

Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

Science.gov (United States)

Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

1991-01-01

A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

Integrated microfluidic device for single-cell trapping and spectroscopy

KAUST Repository

Liberale, Carlo

2013-02-13

Optofluidic microsystems are key components towards lab-on-a-chip devices for manipulation and analysis of biological specimens. In particular, the integration of optical tweezers (OT) in these devices allows stable sample trapping, while making available mechanical, chemical and spectroscopic analyses.

Integrated microfluidic device for single-cell trapping and spectroscopy

KAUST Repository

Liberale, Carlo; Cojoc, G.; Bragheri, F.; Minzioni, P.; Perozziello, G.; La Rocca, R.; Ferrara, L.; Rajamanickam, V.; Di Fabrizio, Enzo M.; Cristiani, I.

2013-01-01

Optofluidic microsystems are key components towards lab-on-a-chip devices for manipulation and analysis of biological specimens. In particular, the integration of optical tweezers (OT) in these devices allows stable sample trapping, while making available mechanical, chemical and spectroscopic analyses.

LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

Energy Technology Data Exchange (ETDEWEB)

Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

1984-01-01

Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

CERN Document Server

Hu, Kai; Ho, Tsung-Yi

2017-01-01

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

Plated lamination structures for integrated magnetic devices

Science.gov (United States)

Webb, Bucknell C.

2014-06-17

Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Directory of Open Access Journals (Sweden)

Ying-Lun Chen

2015-08-01

Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

Science.gov (United States)

2011-09-19

... Integrated Circuit Devices and Components Thereof; Notice of Institution of Investigation; Institution of... integrated circuit devices and components thereof by reason of infringement of certain claims of U.S. Patent... after importation of certain digital televisions containing integrated circuit devices and components...

Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices

International Nuclear Information System (INIS)

Van de Wiel, H J; Galagan, Y; Van Lammeren, T J; De Riet, J F J; Gilot, J; Nagelkerke, M G M; Lelieveld, R H C A T; Shanmugam, S; Pagudala, A; Groen, W A; Hui, D

2013-01-01

Highly conductive screen printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) are a viable replacement for indium tin oxide (ITO) and inkjet printed silver as transparent electrode materials. To provide successful integration into organic photovoltaic (OPV) devices, screen printed silver current collecting grids should be embedded into a substrate to avoid topology issues. In this study micron-thick conductive structures are embedded and integrated into OPV devices. The embedded structures are produced roll-to-roll with optimized process settings and materials. Topology measurements show that the embedded grids are well suited for integration into OPV devices since the surface is almost without spikes and has low surface roughness. JV measurements of OPV devices with embedded structures on a polyethylene terephthalate/silicon nitride (PET/SiN) substrate show an efficiency of 2.15%, which is significantly higher than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). The use of embedded screen printed silver instead of ITO and inkjet printed silver in OPV devices will allow for higher efficiency devices which can be produced with larger design and process freedom. (paper)

Vision for single flux quantum very large scale integrated technology

International Nuclear Information System (INIS)

Silver, Arnold; Bunyk, Paul; Kleinsasser, Alan; Spargo, John

2006-01-01

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90-65 nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100 kA cm -2 to achieve junction speeds approximately 1000 GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250 M Josephson junctions cm -2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200 GHz and place approximately 20 K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip

Vision for single flux quantum very large scale integrated technology

Energy Technology Data Exchange (ETDEWEB)

Silver, Arnold [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States); Bunyk, Paul [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States); Kleinsasser, Alan [Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109-8099 (United States); Spargo, John [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States)

2006-05-15

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90-65 nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100 kA cm{sup -2} to achieve junction speeds approximately 1000 GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250 M Josephson junctions cm{sup -2} into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200 GHz and place approximately 20 K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.

Avionic Data Bus Integration Technology

Science.gov (United States)

1991-12-01

address the hardware-software interaction between a digital data bus and an avionic system. Very Large Scale Integration (VLSI) ICs and multiversion ...the SCP. In 1984, the Sperry Corporation developed a fault tolerant system which employed multiversion programming, voting, and monitoring for error... MULTIVERSION PROGRAMMING. N-version programming. 226 N-VERSION PROGRAMMING. The independent coding of a number, N, of redundant computer programs that

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

Directory of Open Access Journals (Sweden)

N.R. Divya

2014-08-01

Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

RFID and Memory Devices Fabricated Integrally on Substrates

Science.gov (United States)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

Science.gov (United States)

Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

1990-01-01

The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

3D-FBK Pixel sensors: recent beam tests results with irradiated devices

CERN Document Server

Micelli, A; Sandaker, H; Stugu, B; Barbero, M; Hugging, F; Karagounis, M; Kostyukhin, V; Kruger, H; Tsung, J W; Wermes, N; Capua, M; Fazio, S; Mastroberardino, A; Susinno, G; Gallrapp, C; Di Girolamo, B; Dobos, D; La Rosa, A; Pernegger, H; Roe, S; Slavicek, T; Pospisil, S; Jakobs, K; Kohler, M; Parzefall, U; Darbo, G; Gariano, G; Gemme, C; Rovani, A; Ruscino, E; Butter, C; Bates, R; Oshea, V; Parker, S; Cavalli-Sforza, M; Grinstein, S; Korokolov, I; Pradilla, C; Einsweiler, K; Garcia-Sciveres, M; Borri, M; Da Via, C; Freestone, J; Kolya, S; Lai, C H; Nellist, C; Pater, J; Thompson, R; Watts, S J; Hoeferkamp, M; Seidel, S; Bolle, E; Gjersdal, H; Sjobaek, K N; Stapnes, S; Rohne, O; Su, D; Young, C; Hansson, P; Grenier, P; Hasi, J; Kenney, C; Kocian, M; Jackson, P; Silverstein, D; Davetak, H; DeWilde, B; Tsybychev, D; Dalla Betta, G F; Gabos, P; Povoli, M; Cobal, M; Giordani, M P; Selmi, L; Cristofoli, A; Esseni, D; Palestri, P; Fleta, C; Lozano, M; Pellegrini, G; Boscardin, M; Bagolini, A; Piemonte, C; Ronchin, S; Zorzi, N; Hansen, T E; Hansen, T; Kok, A; Lietaer, N; Kalliopuska, J; Oja, A

2011-01-01

The Pixel detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider (LHC), and plays a key role in the reconstruction of the primary and secondary vertices of short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology is an innovative combination of very-large-scale integration (VLSI) and Micro-Electro-Mechanical-Systems (MEMS) where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradi...

PLA realizations for VLSI state machines

Science.gov (United States)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Medical Device Integration Model Based on the Internet of Things

Science.gov (United States)

Hao, Aiyu; Wang, Ling

2015-01-01

At present, hospitals in our country have basically established the HIS system, which manages registration, treatment, and charge, among many others, of patients. During treatment, patients need to use medical devices repeatedly to acquire all sorts of inspection data. Currently, the output data of the medical devices are often manually input into information system, which is easy to get wrong or easy to cause mismatches between inspection reports and patients. For some small hospitals of which information construction is still relatively weak, the information generated by the devices is still presented in the form of paper reports. When doctors or patients want to have access to the data at a given time again, they can only look at the paper files. Data integration between medical devices has long been a difficult problem for the medical information system, because the data from medical devices are lack of mandatory unified global standards and have outstanding heterogeneity of devices. In order to protect their own interests, manufacturers use special protocols, etc., thus causing medical decices to still be the "lonely island" of hospital information system. Besides, unfocused application of the data will lead to failure to achieve a reasonable distribution of medical resources. With the deepening of IT construction in hospitals, medical information systems will be bound to develop towards mobile applications, intelligent analysis, and interconnection and interworking, on the premise that there is an effective medical device integration (MDI) technology. To this end, this paper presents a MDI model based on the Internet of Things (IoT). Through abstract classification, this model is able to extract the common characteristics of the devices, resolve the heterogeneous differences between them, and employ a unified protocol to integrate data between devices. And by the IoT technology, it realizes interconnection network of devices and conducts associate matching

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Point DCT VLSI Architecture for Emerging HEVC Standard

Directory of Open Access Journals (Sweden)

Ashfaq Ahmed

2012-01-01

Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

National Research Council Canada - National Science Library

Altmeyer, Ronald

2002-01-01

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

Electronic shift register memory based on molecular electron-transfer reactions

Science.gov (United States)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

Medical device integration using mobile telecommunications infrastructure.

Science.gov (United States)

Moorman, Bridget A; Cockle, Richard A

2013-01-01

Financial pressures, an aging population, and a rising number of patients with chronic diseases, have encouraged the use of remote monitoring technologies. This usually entails at least one physiological parameter measurement for a clinician. Mobile telecommunication technologies lend themselves to this functionality, and in some cases, avoid some of the issues encountered with device integration. Moreover, the inherent characteristics of the mobile telecommunications infrastructure allow a coupling of business and clinical functions that were not possible before. Table I compares and contrasts some key aspect of device integration in and out of a healthcare facility. An HTM professional may be part of the team that acquires and/or manages a system using a mobile telecommunications technology. It is important for HTM professionals to ensure the data is in a standard format so that the interfaces across this system don't become brittle and break easily if one part changes. Moreover, the security and safety considerations of the system and the data should be a primary consideration in and y purchase, with attention given to the proper environmental and encryption mechanisms. Clinical engineers and other HTM professionals are unique in that they understand the patient/clinician/device interface and the need to ensure its safety and effectiveness regardless of geographical environment.

Integration of semiconductor and ceramic superconductor devices for microwave applications

NARCIS (Netherlands)

Klopman, B.B.G.; Klopman, B.B.G.; Wijers, H.W.; Gao, J.; Gao, J.; Gerritsma, G.J.; Rogalla, Horst

1991-01-01

Due to the very-low-loss properties of ceramic superconductors, high-performance microwave resonators and filters can be realized. The fact that these devices may be operated at liquid nitrogen temperature facilitates integration with semiconductor devices. Examples are bandpass amplifiers,

Integration of SPICE with TEK LV500 ASIC Design Verification System

Directory of Open Access Journals (Sweden)

A. Srivastava

1996-01-01

Full Text Available The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500. The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

The Integration of Bacteriorhodopsin Proteins with Semiconductor Heterostructure Devices

Science.gov (United States)

Xu, Jian

2008-03-01

Bioelectronics has emerged as one of the most rapidly developing fields among the active frontiers of interdisciplinary research. A major thrust in this field is aimed at the coupling of the technologically-unmatched performance of biological systems, such as neural and sensing functions, with the well developed technology of microelectronics and optoelectronics. To this end we have studied the integration of a suitably engineered protein, bacteriorhodopsin (BR), with semiconductor optoelectronic devices and circuits. Successful integration will potentially lead to ultrasensitive sensors with polarization selectivity and built-in preprocessing capabilities that will be useful for high speed tracking, motion and edge detection, biological detection, and artificial vision systems. In this presentation we will summarize our progresses in this area, which include fundamental studies on the transient dynamics of photo-induced charge shift in BR and the coupling mechanism at protein-semiconductor interface for effective immobilizing and selectively integrating light sensitive proteins with microelectronic devices and circuits, and the device engineering of BR-transistor-integrated optical sensors as well as their applications in phototransceiver circuits. Work done in collaboration with Pallab Bhattacharya, Jonghyun Shin, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI; Robert R. Birge, Department of Chemistry, University of Connecticut, Storrs, CT 06269; and György V'ar'o, Institute of Biophysics, Biological Research Center of the Hungarian Academy of Science, H-6701 Szeged, Hungary.

Investigating Mobile Devices Integration in Higher Education in Cyprus: Faculty Perspectives

Directory of Open Access Journals (Sweden)

Nikleia Eteokleous

2009-01-01

Full Text Available Mobile devices are everywhere and mobile learning has emerged as a potential educational environment; however it is relatively new to Cyprus educational system. The purpose of this research work is to assess and determine the readiness; and evaluate the viability of integrating mobile technology in Cyprus higher education level. To address the above, a mixed method approach is employed making use of quantitative and qualitative data from faculty members working in three private universities in Cyprus. Faculty reactions were mixed with some of them seeing the benefits for mobile learning while others have doubts. The results summarize the technological and pedagogical aspects to be considered prior integrating mobile devices. Additionally, the study supports that one of the major barriers to educators is the lack of understanding regarding mobile devices integration in the teaching and learning process. Finally, there is a need to develop well-defined and well-structured requirements for mobile integration in the classroom.

A miniaturized silicon based device for nucleic acids electrochemical detection

Directory of Open Access Journals (Sweden)

Salvatore Petralia

2015-12-01

Full Text Available In this paper we describe a novel portable system for nucleic acids electrochemical detection. The core of the system is a miniaturized silicon chip composed by planar microelectrodes. The chip is embedded on PCB board for the electrical driving and reading. The counter, reference and work microelectrodes are manufactured using the VLSI technology, the material is gold for reference and counter electrodes and platinum for working electrode. The device contains also a resistor to control and measuring the temperature for PCR thermal cycling. The reaction chamber has a total volume of 20 μL. It is made in hybrid silicon–plastic technology. Each device contains four independent electrochemical cells.Results show HBV Hepatitis-B virus detection using an unspecific DNA intercalating redox probe based on metal–organic compounds. The recognition event is sensitively detected by square wave voltammetry monitoring the redox signals of the intercalator that strongly binds to the double-stranded DNA. Two approaches were here evaluated: (a intercalation of electrochemical unspecific probe on ds-DNA on homogeneous solution (homogeneous phase; (b grafting of DNA probes on electrode surface (solid phase.The system and the method here reported offer better advantages in term of analytical performances compared to the standard commercial optical-based real-time PCR systems, with the additional incomes of being potentially cheaper and easier to integrate in a miniaturized device. Keywords: Electrochemical detection, Real time PCR, Unspecific DNA intercalator

Medicine Delivery Device with Integrated Sterilization and Detection

Science.gov (United States)

Shearn, Michael J.; Greer, Harold F.; Manohara, Harish

2013-01-01

Sterile delivery devices can be created by integrating a medicine delivery instrument with surfaces that are coated with germicidal and anti-fouling material. This requires that a large-surface-area template be developed within a constrained volume to ensure good contact between the delivered medicine and the germicidal material. Both of these can be integrated using JPL-developed silicon nanotip or cryo-etch black silicon technologies with atomic layer deposition (ALD) coating of specific germicidal layers. The application of semiconductor processing techniques and technologies to the problems of fluid manipulation and delivery has enabled the integration of chemical, electrical, and mechanical manipulation of samples all within a single microfluidic device. This approach has been successfully applied at JPL to the automated processing, detection, and analysis of minute quantities (parts per trillion level) of biomaterials to develop instruments for in situ exploration or extraterrestrial bodies. The same nanofabrication techniques that are used to produce a microfluidics device are also capable of synthesizing extremely high-surface-area templates in precise locations, and coating those surfaces with conformal films to manipulate their surface properties. This methodology has been successfully applied at JPL to produce patterned and coated silicon nanotips (also known as black silicon) to manipulate the hydrophilicity of surfaces to direct the spreading of fluids in microdevices. JPL's ALD technique is an ideal method to produce the highly conformal coatings required for this type of application. Certain materials, such as TiO2, have germicidal and anti-fouling properties when they are illuminated with UV light. The proposed delivery device contacts medicine with this high-surface-area black silicon surface coated with a thin-film germicidal deposited conformally with ALD. The coating can also be illuminated with ultraviolet light for the purpose of sterilization

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

Science.gov (United States)

2012-06-13

... of certain radio frequency integrated circuits and devices containing same by reason of infringement... importation of certain radio frequency integrated circuits and devices containing same that infringe one or... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated...

A manufacturable process integration approach for graphene devices

Science.gov (United States)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Evaluation of polymer based third order nonlinear integrated optics devices

NARCIS (Netherlands)

Driessen, A.; Hoekstra, Hugo; Blom, F.C.; Horst, F.; Horst, F.; Krijnen, Gijsbertus J.M.; van Schoot, J.B.P.; van Schoot, J.B.P.; Lambeck, Paul; Popma, T.J.A.; Diemeer, Mart

Nonlinear polymers are promising materials for high speed active integrated optics devices. In this paper we evaluate the perspectives polymer based nonlinear optical devices can offer. Special attention is directed to the materials aspects. In our experimental work we applied mainly Akzo Nobel DANS

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design

DEFF Research Database (Denmark)

Araci, Ismail Emre; Pop, Paul; Chakrabarty, Krishnendu

2015-01-01

of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, “microfluidic Very Large-Scale Integration” (mVLSI). A roadblock......Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus...... presents the state-of-the-art in the mVLSI platforms and emerging research challenges in the area of continuous-flow microfluidics, focusing on testing techniques and fault-tolerant design....

Device- and service profiles for integrated or systems based on open standards

Directory of Open Access Journals (Sweden)

Mildner Alexander

2015-09-01

Full Text Available Integrated OR systems nowadays are closed and proprietary, so that the interconnection of components from third-party vendors is only possible with high time and cost effort. An integrated operating theatre with open interfaces, giving clinical operators the opportunity to choose individual medical devices from different manufacturers, is currently being developed in the framework of the BMBF (Federal Ministry of Education and Research funded project OR.NET [1]. Actual standards and concepts regarding technical feasibility and accreditation process do not cope with the requirements for modular integration based on an open standard. Therefore, strategies as well as service and device profiles to enable a procedure for risk management and certifiability are in the focus of the project work. Amongst others, a concept for User Interface Profiles (UI-Profiles has been conceived in order to describe medical device functions and the entire user interface regarding Human-Machine-Interaction (HMI characteristics with the aim to identify human-induced risks of central user interfaces. The use of standardized device and service profiles shall allow the manufacturers to integrate their medical devices in the OR.NET network, without disclosing the medical devices’ risk analysis and related confidential knowledge or proprietary information.

A technique for estimating the probability of radiation-stimulated failures of integrated microcircuits in low-intensity radiation fields: Application to the Spektr-R spacecraft

Science.gov (United States)

Popov, V. D.; Khamidullina, N. M.

2006-10-01

In developing radio-electronic devices (RED) of spacecraft operating in the fields of ionizing radiation in space, one of the most important problems is the correct estimation of their radiation tolerance. The “weakest link” in the element base of onboard microelectronic devices under radiation effect is the integrated microcircuits (IMC), especially of large scale (LSI) and very large scale (VLSI) degree of integration. The main characteristic of IMC, which is taken into account when making decisions on using some particular type of IMC in the onboard RED, is the probability of non-failure operation (NFO) at the end of the spacecraft’s lifetime. It should be noted that, until now, the NFO has been calculated only from the reliability characteristics, disregarding the radiation effect. This paper presents the so-called “reliability” approach to determination of radiation tolerance of IMC, which allows one to estimate the probability of non-failure operation of various types of IMC with due account of radiation-stimulated dose failures. The described technique is applied to RED onboard the Spektr-R spacecraft to be launched in 2007.

Operation of a Fast-RICH Prototype with VLSI readout electronics

Energy Technology Data Exchange (ETDEWEB)

Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

1994-04-01

We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

Power efficient and high performance VLSI architecture for AES algorithm

Directory of Open Access Journals (Sweden)

K. Kalaiselvi

2015-09-01

Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

Comparison of costs of integrating working level devices

International Nuclear Information System (INIS)

Langner, G.H. Jr.

1977-01-01

For the purpose of deciding upon the method for making routine field measurements of radon and radon daughter products there are primarily two factors to be taken into consideration: how well the various methods measure the parameter of interest and how much they cost. For the purpose of measuring the annual average working level within a structure there are available basically two devices: the integrating air sampler and track etch film. The cost and manpower requirements for each of these two devices are discussed

Towards Integrating Distributed Energy Resources and Storage Devices in Smart Grid.

Science.gov (United States)

Xu, Guobin; Yu, Wei; Griffith, David; Golmie, Nada; Moulema, Paul

2017-02-01

Internet of Things (IoT) provides a generic infrastructure for different applications to integrate information communication techniques with physical components to achieve automatic data collection, transmission, exchange, and computation. The smart grid, as one of typical applications supported by IoT, denoted as a re-engineering and a modernization of the traditional power grid, aims to provide reliable, secure, and efficient energy transmission and distribution to consumers. How to effectively integrate distributed (renewable) energy resources and storage devices to satisfy the energy service requirements of users, while minimizing the power generation and transmission cost, remains a highly pressing challenge in the smart grid. To address this challenge and assess the effectiveness of integrating distributed energy resources and storage devices, in this paper we develop a theoretical framework to model and analyze three types of power grid systems: the power grid with only bulk energy generators, the power grid with distributed energy resources, and the power grid with both distributed energy resources and storage devices. Based on the metrics of the power cumulative cost and the service reliability to users, we formally model and analyze the impact of integrating distributed energy resources and storage devices in the power grid. We also use the concept of network calculus, which has been traditionally used for carrying out traffic engineering in computer networks, to derive the bounds of both power supply and user demand to achieve a high service reliability to users. Through an extensive performance evaluation, our data shows that integrating distributed energy resources conjointly with energy storage devices can reduce generation costs, smooth the curve of bulk power generation over time, reduce bulk power generation and power distribution losses, and provide a sustainable service reliability to users in the power grid.

A graphene integrated highly transparent resistive switching memory device

Science.gov (United States)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Integrated-optic current sensors with a multimode interference waveguide device.

Science.gov (United States)

Kim, Sung-Moon; Chu, Woo-Sung; Kim, Sang-Guk; Oh, Min-Cheol

2016-04-04

Optical current sensors based on polarization-rotated reflection interferometry are demonstrated using polymeric integrated optics and various functional optical waveguide devices. Interferometric sensors normally require bias feedback control for maintaining the operating point, which increases the cost. In order to resolve this constraint of feedback control, a multimode interference (MMI) waveguide device is integrated onto the current-sensor optical chip in this work. From the multiple outputs of the MMI, a 90° phase-shifted transfer function is obtained. Using passive quadrature demodulation, we demonstrate that the sensor could maintain the output signal regardless of the drift in the operating bias-point.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices

KAUST Repository

Li, Wenjie; Fu, Hui-chun; Li, Linsen; Cabá n-Acevedo, Miguel; He, Jr-Hau; Jin, Song

2016-01-01

photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly

Carbon nanotube based VLSI interconnects analysis and design

CERN Document Server

Kaushik, Brajesh Kumar

2015-01-01

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

An analog VLSI real time optical character recognition system based on a neural architecture

International Nuclear Information System (INIS)

Bo, G.; Caviglia, D.; Valle, M.

1999-01-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

An analog VLSI real time optical character recognition system based on a neural architecture

Energy Technology Data Exchange (ETDEWEB)

Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

1999-03-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

Integration of Capacitive Micromachined Ultrasound Transducers to Microfluidic Devices

KAUST Repository

Viržonis, Darius; Kodzius, Rimantas; Vanagas, Galius

2013-01-01

The design and manufacturing flexibility of capacitive micromachined ultrasound transducers (CMUT) makes them attractive option for integration with microfluidic devices both for sensing and fluid manipulation. CMUT concept is introduced here

A new approximation of Fermi-Dirac integrals of order 1/2 for degenerate semiconductor devices

Science.gov (United States)

AlQurashi, Ahmed; Selvakumar, C. R.

2018-06-01

There had been tremendous growth in the field of Integrated circuits (ICs) in the past fifty years. Scaling laws mandated both lateral and vertical dimensions to be reduced and a steady increase in doping densities. Most of the modern semiconductor devices have invariably heavily doped regions where Fermi-Dirac Integrals are required. Several attempts have been devoted to developing analytical approximations for Fermi-Dirac Integrals since numerical computations of Fermi-Dirac Integrals are difficult to use in semiconductor devices, although there are several highly accurate tabulated functions available. Most of these analytical expressions are not sufficiently suitable to be employed in semiconductor device applications due to their poor accuracy, the requirement of complicated calculations, and difficulties in differentiating and integrating. A new approximation has been developed for the Fermi-Dirac integrals of the order 1/2 by using Prony's method and discussed in this paper. The approximation is accurate enough (Mean Absolute Error (MAE) = 0.38%) and easy enough to be used in semiconductor device equations. The new approximation of Fermi-Dirac Integrals is applied to a more generalized Einstein Relation which is an important relation in semiconductor devices.

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

Wearable Fall Detector using Integrated Sensors and Energy Devices

Science.gov (United States)

Jung, Sungmook; Hong, Seungki; Kim, Jaemin; Lee, Sangkyu; Hyeon, Taeghwan; Lee, Minbaek; Kim, Dae-Hyeong

2015-11-01

Wearable devices have attracted great attentions as next-generation electronic devices. For the comfortable, portable, and easy-to-use system platform in wearable electronics, a key requirement is to replace conventional bulky and rigid energy devices into thin and deformable ones accompanying the capability of long-term energy supply. Here, we demonstrate a wearable fall detection system composed of a wristband-type deformable triboelectric generator and lithium ion battery in conjunction with integrated sensors, controllers, and wireless units. A stretchable conductive nylon is used as electrodes of the triboelectric generator and the interconnection between battery cells. Ethoxylated polyethylenimine, coated on the surface of the conductive nylon electrode, tunes the work function of a triboelectric generator and maximizes its performance. The electrical energy harvested from the triboelectric generator through human body motions continuously recharges the stretchable battery and prolongs hours of its use. The integrated energy supply system runs the 3-axis accelerometer and related electronics that record human body motions and send the data wirelessly. Upon the unexpected fall occurring, a custom-made software discriminates the fall signal and an emergency alert is immediately sent to an external mobile device. This wearable fall detection system would provide new opportunities in the mobile electronics and wearable healthcare.

Integration of Capacitive Micromachined Ultrasound Transducers to Microfluidic Devices

KAUST Repository

Viržonis, Darius

2013-10-22

The design and manufacturing flexibility of capacitive micromachined ultrasound transducers (CMUT) makes them attractive option for integration with microfluidic devices both for sensing and fluid manipulation. CMUT concept is introduced here by presentin

3D integration of planar crossbar memristive devices with CMOS substrate

International Nuclear Information System (INIS)

Lin, Peng; Pi, Shuang; Xia, Qiangfei

2014-01-01

Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. (paper)

Integration Head Mounted Display Device and Hand Motion Gesture Device for Virtual Reality Laboratory

Science.gov (United States)

Rengganis, Y. A.; Safrodin, M.; Sukaridhoto, S.

2018-01-01

Virtual Reality Laboratory (VR Lab) is an innovation for conventional learning media which show us whole learning process in laboratory. There are many tools and materials are needed by user for doing practical in it, so user could feel new learning atmosphere by using this innovation. Nowadays, technologies more sophisticated than before. So it would carry in education and it will be more effective, efficient. The Supported technologies are needed us for making VR Lab such as head mounted display device and hand motion gesture device. The integration among them will be used us for making this research. Head mounted display device for viewing 3D environment of virtual reality laboratory. Hand motion gesture device for catching user real hand and it will be visualized in virtual reality laboratory. Virtual Reality will show us, if using the newest technologies in learning process it could make more interesting and easy to understand.

Vlsi implementation of flexible architecture for decision tree classification in data mining

Science.gov (United States)

Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

2017-07-01

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

Systematic configuration and automatic tuning of neuromorphic systems

OpenAIRE

Sheik Sadique; Stefanini Fabio; Neftci Emre; Chicca Elisabetta; Indiveri Giacomo

2011-01-01

In the past recent years several research groups have proposed neuromorphic Very Large Scale Integration (VLSI) devices that implement event-based sensors or biophysically realistic networks of spiking neurons. It has been argued that these devices can be used to build event-based systems, for solving real-world applications in real-time, with efficiencies and robustness that cannot be achieved with conventional computing technologies. In order to implement complex event-based neuromorphic sy...

Integrated devices for quantum information and quantum simulation with polarization encoded qubits

Science.gov (United States)

Sansoni, Linda; Sciarrino, Fabio; Mataloni, Paolo; Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto

2012-06-01

The ability to manipulate quantum states of light by integrated devices may open new perspectives both for fundamental tests of quantum mechanics and for novel technological applications. The technology for handling polarization-encoded qubits, the most commonly adopted approach, was still missing in quantum optical circuits until the ultrafast laser writing (ULW) technique was adopted for the first time to realize integrated devices able to support and manipulate polarization encoded qubits.1 Thanks to this method, polarization dependent and independent devices can be realized. In particular the maintenance of polarization entanglement was demonstrated in a balanced polarization independent integrated beam splitter1 and an integrated CNOT gate for polarization qubits was realized and carachterized.2 We also exploited integrated optics for quantum simulation tasks: by adopting the ULW technique an integrated quantum walk circuit was realized3 and, for the first time, we investigate how the particle statistics, either bosonic or fermionic, influences a two-particle discrete quantum walk. Such experiment has been realized by adopting two-photon entangled states and an array of integrated symmetric directional couplers. The polarization entanglement was exploited to simulate the bunching-antibunching feature of non interacting bosons and fermions. To this scope a novel three-dimensional geometry for the waveguide circuit is introduced, which allows accurate polarization independent behaviour, maintaining a remarkable control on both phase and balancement of the directional couplers.

Integrating nanosphere lithography in device fabrication

Science.gov (United States)

Laurvick, Tod V.; Coutu, Ronald A.; Lake, Robert A.

2016-03-01

This paper discusses the integration of nanosphere lithography (NSL) with other fabrication techniques, allowing for nano-scaled features to be realized within larger microelectromechanical system (MEMS) based devices. Nanosphere self-patterning methods have been researched for over three decades, but typically not for use as a lithography process. Only recently has progress been made towards integrating many of the best practices from these publications and determining a process that yields large areas of coverage, with repeatability and enabled a process for precise placement of nanospheres relative to other features. Discussed are two of the more common self-patterning methods used in NSL (i.e. spin-coating and dip coating) as well as a more recently conceived variation of dip coating. Recent work has suggested the repeatability of any method depends on a number of variables, so to better understand how these variables affect the process a series of test vessels were developed and fabricated. Commercially available 3-D printing technology was used to incrementally alter the test vessels allowing for each variable to be investigated individually. With these deposition vessels, NSL can now be used in conjunction with other fabrication steps to integrate features otherwise unattainable through current methods, within the overall fabrication process of larger MEMS devices. Patterned regions in 1800 series photoresist with a thickness of ~700nm are used to capture regions of self-assembled nanospheres. These regions are roughly 2-5 microns in width, and are able to control the placement of 500nm polystyrene spheres by controlling where monolayer self-assembly occurs. The resulting combination of photoresist and nanospheres can then be used with traditional deposition or etch methods to utilize these fine scale features in the overall design.

Development and Testing of an Integrated Sandia Cooler Thermoelectric Device (SCTD).

Energy Technology Data Exchange (ETDEWEB)

Johnson, Terry A.; Staats, Wayne Lawrence,; Leick, Michael Thomas; Zimmerman, Mark D.; Radermacher, Reinhard; Martin, Cara; Nasuta, Dennis; Kalinowski, Paul; Hoffman, William

2014-12-01

This report describes a FY14 effort to develop an integrated Sandia Cooler T hermoelectric D evice (SCTD) . The project included a review of feasible thermoelectric (TE) cooling applications, baseline performance testing of an existing TE device, analysis and design development of an integrated SCTD assembly, and performance measurement and validation of the integrated SCTD prototype.

An architecture for integrating planar and 3D cQED devices

Energy Technology Data Exchange (ETDEWEB)

Axline, C.; Reagor, M.; Heeres, R.; Reinhold, P.; Wang, C.; Shain, K.; Pfaff, W.; Chu, Y.; Frunzio, L.; Schoelkopf, R. J. [Department of Applied Physics, Yale University, New Haven, Connecticut 06511 (United States)

2016-07-25

Numerous loss mechanisms can limit coherence and scalability of planar and 3D-based circuit quantum electrodynamics (cQED) devices, particularly due to their packaging. The low loss and natural isolation of 3D enclosures make them good candidates for coherent scaling. We introduce a coaxial transmission line device architecture with coherence similar to traditional 3D cQED systems. Measurements demonstrate well-controlled external and on-chip couplings, a spectrum absent of cross-talk or spurious modes, and excellent resonator and qubit lifetimes. We integrate a resonator-qubit system in this architecture with a seamless 3D cavity, and separately pattern a qubit, readout resonator, Purcell filter, and high-Q stripline resonator on a single chip. Device coherence and its ease of integration make this a promising tool for complex experiments.

A Sensor Middleware for integration of heterogeneous medical devices.

Science.gov (United States)

Brito, M; Vale, L; Carvalho, P; Henriques, J

2010-01-01

In this paper, the architecture of a modular, service-oriented, Sensor Middleware for data acquisition and processing is presented. The described solution was developed with the purpose of solving two increasingly relevant problems in the context of modern pHealth systems: i) to aggregate a number of heterogeneous, off-the-shelf, devices from which clinical measurements can be acquired and ii) to provide access and integration with an 802.15.4 network of wearable sensors. The modular nature of the Middleware provides the means to easily integrate pre-processing algorithms into processing pipelines, as well as new drivers for adding support for new sensor devices or communication technologies. Tests performed with both real and artificially generated data streams show that the presented solution is suitable for use both in a Windows PC or a Windows Mobile PDA with minimal overhead.

A novel configurable VLSI architecture design of window-based image processing method

Science.gov (United States)

Zhao, Hui; Sang, Hongshi; Shen, Xubang

2018-03-01

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

Integration of active devices on smart polymers for neural interfaces

Science.gov (United States)

Avendano-Bolivar, Adrian Emmanuel

The increasing ability to ever more precisely identify and measure neural interactions and other phenomena in the central and peripheral nervous systems is revolutionizing our understanding of the human body and brain. To facilitate further understanding, more sophisticated neural devices, perhaps using microelectronics processing, must be fabricated. Materials often used in these neural interfaces, while compatible with these fabrication processes, are not optimized for long-term use in the body and are often orders of magnitude stiffer than the tissue with which they interact. Using the smart polymer substrates described in this work, suitability for processing as well as chronic implantation is demonstrated. We explore how to integrate reliable circuitry onto these flexible, biocompatible substrates that can withstand the aggressive environment of the body. To increase the capabilities of these devices beyond individual channel sensing and stimulation, active electronics must also be included onto our systems. In order to add this functionality to these substrates and explore the limits of these devices, we developed a process to fabricate single organic thin film transistors with mobilities up to 0.4 cm2/Vs and threshold voltages close to 0V. A process for fabricating organic light emitting diodes on flexible substrates is also addressed. We have set a foundation and demonstrated initial feasibility for integrating multiple transistors onto thin-film flexible devices to create new applications, such as matrix addressable functionalized electrodes and organic light emitting diodes. A brief description on how to integrate waveguides for their use in optogenetics is addressed. We have built understanding about device constraints on mechanical, electrical and in vivo reliability and how various conditions affect the electronics' lifetime. We use a bi-layer gate dielectric using an inorganic material such as HfO 2 combined with organic Parylene-c. A study of

Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Science.gov (United States)

Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

2015-02-01

We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

Directory of Open Access Journals (Sweden)

Adrian Iovan

2012-12-01

Full Text Available Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

Directory of Open Access Journals (Sweden)

Massimiliano eGiulioni

2012-02-01

Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

Science.gov (United States)

Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

2011-01-01

We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

New developments in double sided silicon strip detectors

International Nuclear Information System (INIS)

Becker, H.; Boulos, T.; Cattaneo, P.; Dietl, H.; Hauff, D.; Holl, P.; Lange, E.; Lutz, G.; Moser, H.G.; Schwarz, A.S.; Settles, R.; Struder, L.; Kemmer, J.; Buttler, W.

1990-01-01

A new type of double sided silicon strip detector has been built and tested using highly density VLSI readout electronics connected to both sides. Capacitive coupling of the strips to the readout electronics has been achieved by integrating the capacitors into the detector design, which was made possible by introducing a new detector biasing concept. Schemes to simplify the technology of the fabrication of the detectors are discussed. The static performance properties of the devices as well as implications of the use of VLSI electronics in their readout are described. Prototype detectors of the described design equipped with high density readout electronics have been installed in the ALEPH detector at LEP. Test results on the performance are given

Integrated neuron circuit for implementing neuromorphic system with synaptic device

Science.gov (United States)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Directory of Open Access Journals (Sweden)

Georgios Passas

2012-01-01

Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices

KAUST Repository

Li, Wenjie

2016-09-21

Building on regenerative photoelectrochemical solar cells and emerging electrochemical redox flow batteries (RFBs), more efficient, scalable, compact, and cost-effective hybrid energy conversion and storage devices could be realized. An integrated photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly charged by solar light without external bias, and discharged like normal RFBs with an energy storage density of 1.15 Wh L−1 and a solar-to-output electricity efficiency (SOEE) of 1.7 % over many cycles. The concept exploits a previously undeveloped design connecting two major energy technologies and promises a general approach for storing solar energy electrochemically with high theoretical storage capacity and efficiency.

Evaluating and Predicting Patient Safety for Medical Devices With Integral Information Technology

Science.gov (United States)

2005-01-01

323 Evaluating and Predicting Patient Safety for Medical Devices with Integral Information Technology Jiajie Zhang, Vimla L. Patel, Todd R...errors are due to inappropriate designs for user interactions, rather than mechanical failures. Evaluating and predicting patient safety in medical ...the users on the identified trouble spots in the devices. We developed two methods for evaluating and predicting patient safety in medical devices

Framework for the Integration of Mobile Device Features in PLM

OpenAIRE

Hopf, Jens Michael

2016-01-01

Currently, companies have covered their business processes with stationary workstations while mobile business applications have limited relevance. Companies can cover their overall business processes more time-efficiently and cost-effectively when they integrate mobile users in workflows using mobile device features. The objective is a framework that can be used to model and control business applications for PLM processes using mobile device features to allow a totally new user experience.

Heterogenous integration of a thin-film GaAs photodetector and a microfluidic device on a silicon substrate

International Nuclear Information System (INIS)

Song, Fuchuan; Xiao, Jing; Udawala, Fidaali; Seo, Sang-Woo

2011-01-01

In this paper, heterogeneous integration of a III–V semiconductor thin-film photodetector (PD) with a microfluidic device is demonstrated on a SiO 2 –Si substrate. Thin-film format of optical devices provides an intimate integration of optical functions with microfluidic devices. As a demonstration of a multi-material and functional system, the biphasic flow structure in the polymeric microfluidic channels was co-integrated with a III–V semiconductor thin-film PD. The fluorescent drops formed in the microfluidic device are successfully detected with an integrated thin-film PD on a silicon substrate. The proposed three-dimensional integration structure is an alternative approach to combine optical functions with microfluidic functions on silicon-based electronic functions.

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices.

Science.gov (United States)

Li, Wenjie; Fu, Hui-Chun; Li, Linsen; Cabán-Acevedo, Miguel; He, Jr-Hau; Jin, Song

2016-10-10

Building on regenerative photoelectrochemical solar cells and emerging electrochemical redox flow batteries (RFBs), more efficient, scalable, compact, and cost-effective hybrid energy conversion and storage devices could be realized. An integrated photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly charged by solar light without external bias, and discharged like normal RFBs with an energy storage density of 1.15 Wh L -1 and a solar-to-output electricity efficiency (SOEE) of 1.7 % over many cycles. The concept exploits a previously undeveloped design connecting two major energy technologies and promises a general approach for storing solar energy electrochemically with high theoretical storage capacity and efficiency. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fabricating a multi-level barrier-integrated microfluidic device using grey-scale photolithography

International Nuclear Information System (INIS)

Nam, Yoonkwang; Kim, Minseok; Kim, Taesung

2013-01-01

Most polymer-replica-based microfluidic devices are mainly fabricated by using standard soft-lithography technology so that multi-level masters (MLMs) require multiple spin-coatings, mask alignments, exposures, developments, and bakings. In this paper, we describe a simple method for fabricating MLMs for planar microfluidic channels with multi-level barriers (MLBs). A single photomask is necessary for standard photolithography technology to create a polydimethylsiloxane grey-scale photomask (PGSP), which adjusts the total amount of UV absorption in a negative-tone photoresist via a wide range of dye concentrations. Since the PGSP in turn adjusts the degree of cross-linking of the photoresist, this method enables the fabrication of MLMs for an MLB-integrated microfluidic device. Since the PGSP-based soft-lithography technology provides a simple but powerful fabrication method for MLBs in a microfluidic device, we believe that the fabrication method can be widely used for micro total analysis systems that benefit from MLBs. We demonstrate an MLB-integrated microfluidic device that can separate microparticles. (paper)

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Silicon integrated circuits advances in materials and device research

CERN Document Server

Kahng, Dawon

1981-01-01

Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

Custom VLSI circuits for high energy physics

International Nuclear Information System (INIS)

Parker, S.

1998-06-01

This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner's guide through the maze, and that is the main purpose of this text

Custom VLSI circuits for high energy physics

Energy Technology Data Exchange (ETDEWEB)

Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

1998-06-01

This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

Toward Wearable Self-Charging Power Systems: The Integration of Energy-Harvesting and Storage Devices.

Science.gov (United States)

Pu, Xiong; Hu, Weiguo; Wang, Zhong Lin

2018-01-01

One major challenge for wearable electronics is that the state-of-the-art batteries are inadequate to provide sufficient energy for long-term operations, leading to inconvenient battery replacement or frequent recharging. Other than the pursuit of high energy density of secondary batteries, an alternative approach recently drawing intensive attention from the research community, is to integrate energy-generation and energy-storage devices into self-charging power systems (SCPSs), so that the scavenged energy can be simultaneously stored for sustainable power supply. This paper reviews recent developments in SCPSs with the integration of various energy-harvesting devices (including piezoelectric nanogenerators, triboelectric nanogenerators, solar cells, and thermoelectric nanogenerators) and energy-storage devices, such as batteries and supercapacitors. SCPSs with multiple energy-harvesting devices are also included. Emphasis is placed on integrated flexible or wearable SCPSs. Remaining challenges and perspectives are also examined to suggest how to bring the appealing SCPSs into practical applications in the near future. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integrated nanohole array surface plasmon resonance sensing device using a dual-wavelength source

International Nuclear Information System (INIS)

Escobedo, C; Vincent, S; Choudhury, A I K; Campbell, J; Gordon, R; Brolo, A G; Sinton, D

2011-01-01

In this paper, we demonstrate a compact integrated nanohole array-based surface plasmon resonance sensing device. The unit includes a LED light source, driving circuitry, CCD detector, microfluidic network and computer interface, all assembled from readily available commercial components. A dual-wavelength LED scheme was implemented to increase spectral diversity and isolate intensity variations to be expected in the field. The prototype shows bulk sensitivity of 266 pixel intensity units/RIU and a limit of detection of 6 × 10 −4 RIU. Surface binding tests were performed, demonstrating functionality as a surface-based sensing system. This work is particularly relevant for low-cost point-of-care applications, especially those involving multiple tests and field studies. While nanohole arrays have been applied to many sensing applications, and their suitability to device integration is well established, this is the first demonstration of a fully integrated nanohole array-based sensing device.

Dynamic Neural Fields as a Step Towards Cognitive Neuromorphic Architectures

Directory of Open Access Journals (Sweden)

Yulia eSandamirskaya

2014-01-01

Full Text Available Dynamic Field Theory (DFT is an established framework for modelling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF. Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analogue Very Large Scale Integration (VLSI device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

Power and hydrogen production from ammonia in a micro-thermophotovoltaic device integrated with a micro-reformer

International Nuclear Information System (INIS)

Um, Dong Hyun; Kim, Tae Young; Kwon, Oh Chae

2014-01-01

Power and hydrogen (H 2 ) production by burning and reforming ammonia (NH 3 ) in a micro-TPV (microscale-thermophotovoltaic) device integrated with a micro-reformer is studied experimentally. A heat-recirculating micro-emitter with the cyclone and helical adapters that enhance the residence time of fed fuel-air mixtures and uniform burning burns H 2 -added NH 3 -air mixtures. A micro-reformer that converts NH 3 to H 2 using ruthenium as a catalyst surrounds the micro-emitter as a heat source. The micro-reformer is surrounded by a chamber, the inner and outer walls of which have installations of gallium antimonide photovoltaic cells and cooling fins. For the micro-reformer-integrated micro-TPV device the maximum overall efficiency of 8.1% with electrical power of 4.5 W and the maximum NH 3 conversion rate of 96.0% with the H 2 production rate of 22.6 W (based on lower heating value) are obtained, indicating that the overall efficiency is remarkably enhanced compared with 2.0% when the micro-TPV device operates alone. This supports the potential of improving the overall efficiency of a micro-TPV device through integrating it with a micro-reformer. Also, the feasibility of using NH 3 as a carbon-free fuel for both burning and reforming in practical micro power and H 2 generation devices has been demonstrated. - Highlights: • Performance of micro-TPV device integrated with micro-reformer is evaluated. • Feasibility of using NH 3 –H 2 blends in integrated system has been demonstrated. • Integration with micro-reformer improves performance of micro-TPV device. • Maximum overall efficiency of 8.1% is found compared with 2.0% without integration

System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Very Large Scale Integration Biochips

DEFF Research Database (Denmark)

Minhass, Wajid Hassan

Microfluidic biochips integrate different biochemical analysis functionalities on-chip and offer several advantages over the conventional biochemical laboratories. In this thesis, we focus on the flow-based biochips. The basic building block of such a chip is a valve which can be fabricated at very...... propose a framework for mapping the biochemical applications onto the mVLSI biochips, binding and scheduling the operations and performing fluid routing. A control synthesis framework for determining the exact valve activation sequence required to execute the application is also proposed. In order...... to reduce the macro-assembly around the chip and enhance chip scalability, we propose an approach for the biochip pin count minimization. We also propose a throughput maximization scheme for the cell culture mVLSI biochips, saving time and reducing costs. We have extensively evaluated the proposed...

An electron undulating ring for VLSI lithography

International Nuclear Information System (INIS)

Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

1985-01-01

The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

A design approach for integrating thermoelectric devices using topology optimization

DEFF Research Database (Denmark)

Soprani, Stefano; Haertel, Jan Hendrik Klaas; Lazarov, Boyan Stefanov

2016-01-01

Efficient operation of thermoelectric devices strongly relies on the thermal integration into the energy conversion system in which they operate. Effective thermal integration reduces the temperature differences between the thermoelectric module and its thermal reservoirs, allowing the system...... to operate more efficiently. This work proposes and experimentally demonstrates a topology optimization approach as a design tool for efficient integration of thermoelectric modules into systems with specific design constraints. The approach allows thermal layout optimization of thermoelectric systems...... for different operating conditions and objective functions, such as temperature span, efficiency, and power recoveryrate. As a specific application, the integration of a thermoelectric cooler into the electronics section ofa downhole oil well intervention tool is investigated, with the objective of minimizing...

Semiconductor Devices Inspired By and Integrated With Biology

Energy Technology Data Exchange (ETDEWEB)

Rogers, John [University of Illinois

2012-04-25

Biology is curved, soft and elastic; silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that adopt biologically inspired designs or require intimate integration with the human body. This talk describes the development of ideas for electronics that offer the performance of state-of-the-art, wafer- based systems but with the mechanical properties of a rubber band. We explain the underlying materials science and mechanics of these approaches, and illustrate their use in (1) bio- integrated, ‘tissue-like’ electronics with unique capabilities for mapping cardiac and neural electrophysiology, and (2) bio-inspired, ‘eyeball’ cameras with exceptional imaging properties enabled by curvilinear, Petzval designs.

Integrating mobile devices into nursing curricula: opportunities for implementation using Rogers' Diffusion of Innovation model.

Science.gov (United States)

Doyle, Glynda J; Garrett, Bernie; Currie, Leanne M

2014-05-01

To identify studies reporting mobile device integration into undergraduate and graduate nursing curricula. To explore the potential use of Rogers' Diffusion of Innovation model as a framework to guide implementation of mobile devices into nursing curricula. Literature review and thematic categorization. Literature published up until June 2013 was searched using EBSCO, PubMed, and Google Scholar. The literature was reviewed for research articles pertaining to mobile device use in nursing education. Research articles were grouped by study design, and articles were classified by: 1) strategies for individual adopters and 2) strategies for organizations. Rogers' Diffusion of Innovation theory was used to categorize reported implementation strategies. Fifty-two research studies were identified. Strategies for implementation were varied, and challenges to integrating mobile devices include lack of administrative support and time/funding to educate faculty as well as students. Overall, the use of mobile devices appears to provide benefits to nursing students; however the research evidence is limited. Anticipating challenges and ensuring a well laid out strategic plan can assist in supporting successful integration of mobile devices. Crown Copyright © 2013. Published by Elsevier Ltd. All rights reserved.

Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

2004-06-01

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

Lithography for enabling advances in integrated circuits and devices.

Science.gov (United States)

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Integrated visualization of simulation results and experimental devices in virtual-reality space

International Nuclear Information System (INIS)

Ohtani, Hiroaki; Ishiguro, Seiji; Shohji, Mamoru; Kageyama, Akira; Tamura, Yuichi

2011-01-01

We succeeded in integrating the visualization of both simulation results and experimental device data in virtual-reality (VR) space using CAVE system. Simulation results are shown using Virtual LHD software, which can show magnetic field line, particle trajectory, and isosurface of plasma pressure of the Large Helical Device (LHD) based on data from the magnetohydrodynamics equilibrium simulation. A three-dimensional mouse, or wand, determines the initial position and pitch angle of a drift particle or the starting point of a magnetic field line, interactively in the VR space. The trajectory of a particle and the stream-line of magnetic field are calculated using the Runge-Kutta-Huta integration method on the basis of the results obtained after pointing the initial condition. The LHD vessel is objectively visualized based on CAD-data. By using these results and data, the simulated LHD plasma can be interactively drawn in the objective description of the LHD experimental vessel. Through this integrated visualization, it is possible to grasp the three-dimensional relationship of the positions between the device and plasma in the VR space, opening a new path in contribution to future research. (author)

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Optical device terahertz integration in a two-dimensional-three-dimensional heterostructure.

Science.gov (United States)

Feng, Zhifang; Lin, Jie; Feng, Shuai

2018-01-10

The transmission properties of an off-planar integrated circuit including two wavelength division demultiplexers are designed, simulated, and analyzed in detail by the finite-difference time-domain method. The results show that the wavelength selection for different ports (0.404[c/a] at B 2 port, 0.389[c/a] at B 3 port, and 0.394[c/a] at B 4 port) can be realized by adjusting the parameters. It is especially important that the off-planar integration between two complex devices is also realized. These simulated results give valuable promotions in the all-optical integrated circuit, especially in compact integration.

Highly functional tunnelling devices integrated in 3D

DEFF Research Database (Denmark)

Wernersson, Lars-Erik; Lind, Erik; Lindström, Peter

2003-01-01

a new type of tunnelling transistor, namely a resonant-tunnelling permeable base transistor. A simple model based on a piece-wise linear approximation is used in Cadence to describe the current-voltage characteristics of the transistor. This model is further introduced into a small signal equivalent...... simultaneously on both tunnelling structures and the obtained characteristics are the result of the interplay between the two tunnelling structures and the gate. An equivalent circuit model is developed and we show how this interaction influences the current-voltage characteristics. The gate may be used......We present a new technology for integrating tunnelling devices in three dimensions. These devices are fabricated by the combination of the growth of semiconductor heterostructures with the controlled introduction of metallic elements into an epitaxial layer by an overgrowth technique. First, we use...

Integration of semiconductor and ceramic superconductor devices for microwave applications

International Nuclear Information System (INIS)

Klopman, B.B.G.; Weijers, H.W.; Gao, J.; Gerritsma, G.J.; Rogalla, H.

1991-01-01

Due to the very low-loss properties of ceramic superconductors high-performance microwave resonators and filters can be realized. The fact that these devices may be operated at liquid nitrogen temperature, facilitates the integration with semiconductor devices. Examples are bandpass amplifiers, microwave-operated SQUIDs combined with GaAs preamplifiers, detectors, and MOSFET low-frequency amplifiers. This paper discusses the design of such circuits on a single one inch alumina substrate using surface mount techniques. Furthermore data on circuits that have been realized in our laboratory will be presented

Growth of Si nanocrystals on alumina and integration in memory devices

Science.gov (United States)

Baron, T.; Fernandes, A.; Damlencourt, J. F.; De Salvo, B.; Martin, F.; Mazen, F.; Haukka, S.

2003-06-01

We present a detailed study of the growth of Si quantum dots (Si QDs) by low pressure chemical vapor deposition on alumina dielectric deposited by atomic layer deposition. The Si QDs density is very high, 1012 cm-2, for a mean diameter between 5 and 10 nm. Al2O3/Si QD stacks have been integrated in memory devices as granular floating gate. The devices demonstrate good charge storage and data retention characteristics.

Integrating bar-code devices with computerized MC and A systems

International Nuclear Information System (INIS)

Anderson, L.K.; Boor, M.G.; Hurford, J.M.

1998-01-01

Over the past seven years, Los Alamos National Laboratory developed several generations of computerized nuclear materials control and accountability (MC and A) systems for tracking and reporting the storage, movement, and management of nuclear materials at domestic and international facilities. During the same period, Oak Ridge National Laboratory was involved with automated data acquisition (ADA) equipment, including installation of numerous bar-code scanning stations at various facilities to serve as input devices to computerized systems. Bar-code readers, as well as other ADA devices, reduce input errors, provide faster input, and allow the capture of data in remote areas where workstations do not exist. Los Alamos National Laboratory and Oak Ridge National Laboratory teamed together to implement the integration of bar-code hardware technology with computerized MC and A systems. With the expertise of both sites, the two technologies were successfully merged with little difficulty. Bar-code input is now available with several functions of the MC and A systems: material movements within material balance areas (MBAs), material movements between MBAs, and physical inventory verification. This paper describes the various components required for the integration of these MC and A systems with the installed bar-code reader devices and the future directions for these technologies

Fabricating process of hollow out-of-plane Ni microneedle arrays and properties of the integrated microfluidic device

Science.gov (United States)

Zhu, Jun; Cao, Ying; Wang, Hong; Li, Yigui; Chen, Xiang; Chen, Di

2013-07-01

Although microfluidic devices that integrate microfluidic chips with hollow out-of-plane microneedle arrays have many advantages in transdermal drug delivery applications, difficulties exist in their fabrication due to the special three-dimensional structures of hollow out-of-plane microneedles. A new, cost-effective process for the fabrication of a hollow out-of-plane Ni microneedle array is presented. The integration of PDMS microchips with the Ni hollow microneedle array and the properties of microfluidic devices are also presented. The integrated microfluidic devices provide a new approach for transdermal drug delivery.

Digital Systems Validation Handbook. Volume 2. Chapter 18. Avionic Data Bus Integration Technology

Science.gov (United States)

1993-11-01

interaction between a digital data bus and an avionic system. Very Large Scale Integration (VLSI) ICs and multiversion software, which make up digital...1984, the Sperry Corporation developed a fault tolerant system which employed multiversion programming, voting, and monitoring for error detection and...formulate all the significant behavior of a system. MULTIVERSION PROGRAMMING. N-version programming. N-VERSION PROGRAMMING. The independent coding of a

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

Science.gov (United States)

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Process automation system for integration and operation of Large Volume Plasma Device

International Nuclear Information System (INIS)

Sugandhi, R.; Srivastava, P.K.; Sanyasi, A.K.; Srivastav, Prabhakar; Awasthi, L.M.; Mattoo, S.K.

2016-01-01

Highlights: • Analysis and design of process automation system for Large Volume Plasma Device (LVPD). • Data flow modeling for process model development. • Modbus based data communication and interfacing. • Interface software development for subsystem control in LabVIEW. - Abstract: Large Volume Plasma Device (LVPD) has been successfully contributing towards understanding of the plasma turbulence driven by Electron Temperature Gradient (ETG), considered as a major contributor for the plasma loss in the fusion devices. Large size of the device imposes certain difficulties in the operation, such as access of the diagnostics, manual control of subsystems and large number of signals monitoring etc. To achieve integrated operation of the machine, automation is essential for the enhanced performance and operational efficiency. Recently, the machine is undergoing major upgradation for the new physics experiments. The new operation and control system consists of following: (1) PXIe based fast data acquisition system for the equipped diagnostics; (2) Modbus based Process Automation System (PAS) for the subsystem controls and (3) Data Utilization System (DUS) for efficient storage, processing and retrieval of the acquired data. In the ongoing development, data flow model of the machine’s operation has been developed. As a proof of concept, following two subsystems have been successfully integrated: (1) Filament Power Supply (FPS) for the heating of W- filaments based plasma source and (2) Probe Positioning System (PPS) for control of 12 number of linear probe drives for a travel length of 100 cm. The process model of the vacuum production system has been prepared and validated against acquired pressure data. In the next upgrade, all the subsystems of the machine will be integrated in a systematic manner. The automation backbone is based on 4-wire multi-drop serial interface (RS485) using Modbus communication protocol. Software is developed on LabVIEW platform using

Process automation system for integration and operation of Large Volume Plasma Device

Energy Technology Data Exchange (ETDEWEB)

Sugandhi, R., E-mail: ritesh@ipr.res.in; Srivastava, P.K.; Sanyasi, A.K.; Srivastav, Prabhakar; Awasthi, L.M.; Mattoo, S.K.

2016-11-15

Highlights: • Analysis and design of process automation system for Large Volume Plasma Device (LVPD). • Data flow modeling for process model development. • Modbus based data communication and interfacing. • Interface software development for subsystem control in LabVIEW. - Abstract: Large Volume Plasma Device (LVPD) has been successfully contributing towards understanding of the plasma turbulence driven by Electron Temperature Gradient (ETG), considered as a major contributor for the plasma loss in the fusion devices. Large size of the device imposes certain difficulties in the operation, such as access of the diagnostics, manual control of subsystems and large number of signals monitoring etc. To achieve integrated operation of the machine, automation is essential for the enhanced performance and operational efficiency. Recently, the machine is undergoing major upgradation for the new physics experiments. The new operation and control system consists of following: (1) PXIe based fast data acquisition system for the equipped diagnostics; (2) Modbus based Process Automation System (PAS) for the subsystem controls and (3) Data Utilization System (DUS) for efficient storage, processing and retrieval of the acquired data. In the ongoing development, data flow model of the machine’s operation has been developed. As a proof of concept, following two subsystems have been successfully integrated: (1) Filament Power Supply (FPS) for the heating of W- filaments based plasma source and (2) Probe Positioning System (PPS) for control of 12 number of linear probe drives for a travel length of 100 cm. The process model of the vacuum production system has been prepared and validated against acquired pressure data. In the next upgrade, all the subsystems of the machine will be integrated in a systematic manner. The automation backbone is based on 4-wire multi-drop serial interface (RS485) using Modbus communication protocol. Software is developed on LabVIEW platform using

Bio-inspired optical rotation sensor

Science.gov (United States)

O'Carroll, David C.; Shoemaker, Patrick A.; Brinkworth, Russell S. A.

2007-01-01

Traditional approaches to calculating self-motion from visual information in artificial devices have generally relied on object identification and/or correlation of image sections between successive frames. Such calculations are computationally expensive and real-time digital implementation requires powerful processors. In contrast flies arrive at essentially the same outcome, the estimation of self-motion, in a much smaller package using vastly less power. Despite the potential advantages and a few notable successes, few neuromorphic analog VLSI devices based on biological vision have been employed in practical applications to date. This paper describes a hardware implementation in aVLSI of our recently developed adaptive model for motion detection. The chip integrates motion over a linear array of local motion processors to give a single voltage output. Although the device lacks on-chip photodetectors, it includes bias circuits to use currents from external photodiodes, and we have integrated it with a ring-array of 40 photodiodes to form a visual rotation sensor. The ring configuration reduces pattern noise and combined with the pixel-wise adaptive characteristic of the underlying circuitry, permits a robust output that is proportional to image rotational velocity over a large range of speeds, and is largely independent of either mean luminance or the spatial structure of the image viewed. In principle, such devices could be used as an element of a velocity-based servo to replace or augment inertial guidance systems in applications such as mUAVs.

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Directory of Open Access Journals (Sweden)

HOO, C.-S.

2013-02-01

Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

Science.gov (United States)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

Energy Technology Data Exchange (ETDEWEB)

Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

1983-07-01

This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

Thermal management in MoS{sub 2} based integrated device using near-field radiation

Energy Technology Data Exchange (ETDEWEB)

Peng, Jiebin [Department of Physics, National University of Singapore, Singapore 117546 (Singapore); Zhang, Gang, E-mail: zhangg@ihpc.a-star.edu.sg [Institute of High Performance Computing, A*STAR, Singapore 138632 (Singapore); Li, Baowen [Department of Mechanical Engineering, University of Colorado, Boulder, Colorado 80309 (United States)

2015-09-28

Recently, wafer-scale growth of monolayer MoS{sub 2} films with spatial homogeneity is realized on SiO{sub 2} substrate. Together with the latest reported high mobility, MoS{sub 2} based integrated electronic devices are expected to be fabricated in the near future. Owing to the low lattice thermal conductivity in monolayer MoS{sub 2}, and the increased transistor density accompanied with the increased power density, heat dissipation will become a crucial issue for these integrated devices. In this letter, using the formalism of fluctuation electrodynamics, we explored the near-field radiative heat transfer from a monolayer MoS{sub 2} to graphene. We demonstrate that in resonance, the maximum heat transfer via near-field radiation between MoS{sub 2} and graphene can be ten times higher than the in-plane lattice thermal conduction for MoS{sub 2} sheet. Therefore, an efficient thermal management strategy for MoS{sub 2} integrated device is proposed: Graphene sheet is brought into close proximity, 10–20 nm from MoS{sub 2} device; heat energy transfer from MoS{sub 2} to graphene via near-field radiation; this amount of heat energy then be conducted to contact due to ultra-high lattice thermal conductivity of graphene. Our work sheds light for developing cooling strategy for nano devices constructing with low thermal conductivity materials.

An integrated semiconductor device enabling non-optical genome sequencing.

Science.gov (United States)

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Integrated Lateral Flow Device for Flow Control with Blood Separation and Biosensing

Directory of Open Access Journals (Sweden)

Veronica Betancur

2017-12-01

Full Text Available Lateral flow devices are versatile and serve a wide variety of purposes, including medical, agricultural, environmental, and military applications. Yet, the most promising opportunities of these devices for diagnosis might reside in point-of-care (POC applications. Disposable paper-based lateral flow strips have been of particular interest, because they utilize low-cost materials and do not require expensive fabrication instruments. However, there are constraints on tuning flow rates and immunoassays functionalization in papers, as well as technical challenges in sensors’ integration and concentration units for low-abundant molecular detection. In the present work, we demonstrated an integrated lateral flow device that applied the capillary forces with functionalized polymer-based microfluidics as a strategy to realize a portable, simplified, and self-powered lateral flow device (LFD. The polydimethylsiloxane (PDMS surface was rendered hydrophilic via functionalization with different concentrations of Pluronic F127. Controlled flow is a key variable for immunoassay-based applications for providing enough time for protein binding to antibodies. The flow rate of the integrated LFD was regulated by the combination of multiple factors, including Pluronic F127 functionalized surface properties and surface treatments of microchannels, resistance of the integrated flow resistor, the dimensions of the microstructures and the spacing between them in the capillary pump, the contact angles, and viscosity of the fluids. Various plasma flow rates were regulated and achieved in the whole device. The LFD combined the ability to separate high quality plasma from human whole blood by using a highly asymmetric plasma separation membrane, and created controlled and steady fluid flow using capillary forces produced by the interfacial tensions. Biomarker immunoglobulin G (IgG detection from plasma was demonstrated with a graphene nanoelectronic sensor integrated

Closed-loop model: An optimization of integrated thin-film magnetic devices

Energy Technology Data Exchange (ETDEWEB)

El-Ghazaly, Amal, E-mail: amale@stanford.edu [Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Sato, Noriyuki [Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); White, Robert M. [Materials Science and Engineering, Stanford University, Stanford, CA 94305 (United States); Wang, Shan X. [Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Materials Science and Engineering, Stanford University, Stanford, CA 94305 (United States)

2017-06-15

Highlights: • An analytical model for inductance of thin-film magnetic devices was developed. • Different device topologies and magnetic permeabilities were addressed. • Inductance of various topologies were calculated and compared with simulation. • The model predicts simulated values with excellent accuracy. - Abstract: A generic analytical model has been developed to fully describe the flux closure through magnetic inductors. The model was applied to multiple device topologies including solenoidal single return path and dual return path inductors as well as spiral magnetic inductors for a variety of permeabilities and dimensions. The calculated inductance values from the analytical model were compared with simulated results for each of the analyzed device topologies and found to agree within 0.1 nH for the range of typical thin-film magnetic permeabilities (∼10{sup 2} to 10{sup 3}). Furthermore, the model can be used to evaluate behavior in other integrated or discrete magnetic devices with either non-isotropic or isotropic permeability and used to produce more efficient device designs in the future.

Medical Device Integrated Vital Signs Monitoring Application with Real-Time Clinical Decision Support.

Science.gov (United States)

Moqeem, Aasia; Baig, Mirza; Gholamhosseini, Hamid; Mirza, Farhaan; Lindén, Maria

2018-01-01

This research involves the design and development of a novel Android smartphone application for real-time vital signs monitoring and decision support. The proposed application integrates market available, wireless and Bluetooth connected medical devices for collecting vital signs. The medical device data collected by the app includes heart rate, oxygen saturation and electrocardiograph (ECG). The collated data is streamed/displayed on the smartphone in real-time. This application was designed by adopting six screens approach (6S) mobile development framework and focused on user-centered approach and considered clinicians-as-a-user. The clinical engagement, consultations, feedback and usability of the application in the everyday practices were considered critical from the initial phase of the design and development. Furthermore, the proposed application is capable to deliver rich clinical decision support in real-time using the integrated medical device data.

The Marketing Plan: An Integrative Device for Teaching Marketing Management.

Science.gov (United States)

Berdine, W. R.; Petersen, James C.

1980-01-01

The importance of the marketing plan is stressed as an integrative device for teaching marketing management, and a structure is presented to assist students in designing a marketing plan. Components of this plan include marketing objectives, targeting market and buying motives, external environment and competition, product, price, and promotion.…

The MMI Device Ontology: Enabling Sensor Integration

Science.gov (United States)

Rueda, C.; Galbraith, N.; Morris, R. A.; Bermudez, L. E.; Graybeal, J.; Arko, R. A.; Mmi Device Ontology Working Group

2010-12-01

The Marine Metadata Interoperability (MMI) project has developed an ontology for devices to describe sensors and sensor networks. This ontology is implemented in the W3C Web Ontology Language (OWL) and provides an extensible conceptual model and controlled vocabularies for describing heterogeneous instrument types, with different data characteristics, and their attributes. It can help users populate metadata records for sensors; associate devices with their platforms, deployments, measurement capabilities and restrictions; aid in discovery of sensor data, both historic and real-time; and improve the interoperability of observational oceanographic data sets. We developed the MMI Device Ontology following a community-based approach. By building on and integrating other models and ontologies from related disciplines, we sought to facilitate semantic interoperability while avoiding duplication. Key concepts and insights from various communities, including the Open Geospatial Consortium (eg., SensorML and Observations and Measurements specifications), Semantic Web for Earth and Environmental Terminology (SWEET), and W3C Semantic Sensor Network Incubator Group, have significantly enriched the development of the ontology. Individuals ranging from instrument designers, science data producers and consumers to ontology specialists and other technologists contributed to the work. Applications of the MMI Device Ontology are underway for several community use cases. These include vessel-mounted multibeam mapping sonars for the Rolling Deck to Repository (R2R) program and description of diverse instruments on deepwater Ocean Reference Stations for the OceanSITES program. These trials involve creation of records completely describing instruments, either by individual instances or by manufacturer and model. Individual terms in the MMI Device Ontology can be referenced with their corresponding Uniform Resource Identifiers (URIs) in sensor-related metadata specifications (e

An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

1995-01-01

A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

Integrated Microfibre Device for Refractive Index and Temperature Sensing

Directory of Open Access Journals (Sweden)

Sulaiman W. Harun

2012-08-01

Full Text Available A microfibre device integrating a microfibre knot resonator in a Sagnac loop reflector is proposed for refractive index and temperature sensing. The reflective configuration of this optical structure offers the advantages of simple fabrication and ease of sensing. To achieve a balance between responsiveness and robustness, the entire microfibre structure is embedded in low index Teflon, except for the 0.5–2 mm diameter microfibre knot resonator sensing region. The proposed sensor has exhibited a linear spectral response with temperature and refractive index. A small change in free spectral range is observed when the microfibre device experiences a large refractive index change in the surrounding medium. The change is found to be in agreement with calculated results based on dispersion relationships.

Thin-film luminescent concentrators for integrated devices: a cookbook.

Science.gov (United States)

Evenson, S A; Rawicz, A H

1995-11-01

A luminescent concentrator (LC) is a nonimaging optical device used for collecting light energy. As a result of its unique properties, a LC also offers the possibility of separating different portions of the spectrum and concentrating them at the same time. Hence, LC's can be applied to a whole range of problems requiring the collection, manipulation, and distribution or measurement of light. Further-more, as described in our previous research, thin-film LC elements can be deposited directly over sensor and processing electronics in the form of integrated LC devices. As an aid to further research, the materials and technology required to fabricate these thin-film LC elements through the use of an ultraviolet-curable photopolymer are documented in detail.

InP monolithically integrated label swapper device for spectral amplitude coded optical packet networks

NARCIS (Netherlands)

Muñoz, P.; García-Olcina, R.; Doménech, J.D.; Rius, M.; Sancho, J.C.; Capmany, J.; Chen, L.R.; Habib, C.; Leijtens, X.J.M.; Vries, de T.; Heck, M.J.R.; Augustin, L.M.; Nötzel, R.; Robbins, D.J.

2010-01-01

In this paper a label swapping device, for spectral amplitude coded optical packet networks, fully integrated using InP technology is presented. Compared to previous demonstrations using discrete component assembly, the device footprint is reduced by a factor of 105 and the operation speed is

A design approach for integrating thermoelectric devices using topology optimization

International Nuclear Information System (INIS)

Soprani, S.; Haertel, J.H.K.; Lazarov, B.S.; Sigmund, O.; Engelbrecht, K.

2016-01-01

Highlights: • The integration of a thermoelectric (TE) cooler into a robotic tool is optimized. • Topology optimization is suggested as design tool for TE integrated systems. • A 3D optimization technique using temperature dependent TE properties is presented. • The sensitivity of the optimization process to the boundary conditions is studied. • A working prototype is constructed and compared to the model results. - Abstract: Efficient operation of thermoelectric devices strongly relies on the thermal integration into the energy conversion system in which they operate. Effective thermal integration reduces the temperature differences between the thermoelectric module and its thermal reservoirs, allowing the system to operate more efficiently. This work proposes and experimentally demonstrates a topology optimization approach as a design tool for efficient integration of thermoelectric modules into systems with specific design constraints. The approach allows thermal layout optimization of thermoelectric systems for different operating conditions and objective functions, such as temperature span, efficiency, and power recovery rate. As a specific application, the integration of a thermoelectric cooler into the electronics section of a downhole oil well intervention tool is investigated, with the objective of minimizing the temperature of the cooled electronics. Several challenges are addressed: ensuring effective heat transfer from the load, minimizing the thermal resistances within the integrated system, maximizing the thermal protection of the cooled zone, and enhancing the conduction of the rejected heat to the oil well. The design method incorporates temperature dependent properties of the thermoelectric device and other materials. The 3D topology optimization model developed in this work was used to design a thermoelectric system, complete with insulation and heat sink, that was produced and tested. Good agreement between experimental results and

An optoelectronic integrated device including a laser and its driving circuit

Energy Technology Data Exchange (ETDEWEB)

Matsueda, H.; Nakano, H.; Tanaka, T.P.

1984-10-01

A monolithic optoelectronic integrated circuit (OEIC) including a laser diode, photomonitor and driving and detecting circuits has been fabricated on a semi-insulating GaAs substrate. The OEIC has a horizontal integrating structure which is suitable for realising high-density multifunctional devices. The fabricating process and the static and dynamic characteristics of the optical and electronic elements are described. The preliminary results of the co-operative operation of the laser and its driving circuit are also presented.

A Printed Equilibrium Dialysis Device with Integrated Membranes for Improved Binding Affinity Measurements.

Science.gov (United States)

Pinger, Cody W; Heller, Andrew A; Spence, Dana M

2017-07-18

Equilibrium dialysis is a simple and effective technique used for investigating the binding of small molecules and ions to proteins. A three-dimensional (3D) printer was used to create a device capable of measuring binding constants between a protein and a small ion based on equilibrium dialysis. Specifically, the technology described here enables the user to customize an equilibrium dialysis device to fit their own experiments by choosing membranes of various material and molecular-weight cutoff values. The device has dimensions similar to that of a standard 96-well plate, thus being amenable to automated sample handlers and multichannel pipettes. The device consists of a printed base that hosts multiple windows containing a porous regenerated-cellulose membrane with a molecular-weight cutoff of ∼3500 Da. A key step in the fabrication process is a print-pause-print approach for integrating membranes directly into the windows subsequently inserted into the base. The integrated membranes display no leaking upon placement into the base. After characterizing the system's requirements for reaching equilibrium, the device was used to successfully measure an equilibrium dissociation constant for Zn 2+ and human serum albumin (K d = (5.62 ± 0.93) × 10 -7 M) under physiological conditions that is statistically equal to the constants reported in the literature.

Microfluidic device for continuous single cells analysis via Raman spectroscopy enhanced by integrated plasmonic nanodimers

KAUST Repository

Perozziello, Gerardo; Candeloro, Patrizio; De Grazia, Antonio; Esposito, Francesco; Allione, Marco; Coluccio, Maria Laura; Tallerico, Rossana; Valpapuram, Immanuel; Tirinato, Luca; Das, Gobind; Giugni, Andrea; Torre, Bruno; Veltri, Pierangelo; Kruhne, Ulrich; Della Valle, Giuseppe; Di Fabrizio, Enzo M.

2015-01-01

In this work a Raman flow cytometer is presented. It consists of a microfluidic device that takes advantages of the basic principles of Raman spectroscopy and flow cytometry. The microfluidic device integrates calibrated microfluidic channels- where

Applications of Si/SiGe heterostructures to CMOS devices

International Nuclear Information System (INIS)

Sidek, R.M.

1999-03-01

For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

Use of integrity control and automatic start of reserve in a multi-channel temperature and flow rate control device

International Nuclear Information System (INIS)

Strzalkowski, L.

1975-01-01

A way to increase reliability of process quantity control is control of the integrity of the control plants themselves. The possibilities of integrity control on control devices having simply duplicated control channels or working on the basis of the ''two-from-three'' principle are valued. A highly reliable integrity control is possible by use of test signals. For an appropriate control device, structure and function of the assemblies are described. The integrity control device may be used in the water coolant temperature and flow rate control system for all technological channels of the research reactor ''Maria''

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Science.gov (United States)

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

Science.gov (United States)

2012-10-04

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...,783; and 6,847,904. The complaint further alleges the existence of a domestic industry. The Commission...

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Directory of Open Access Journals (Sweden)

Yuan-Jyun Chang

2016-12-01

Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

A Novel Pseudo-PMOS Integrated ISFET Device for Water Quality Monitoring

Directory of Open Access Journals (Sweden)

Pawan Whig

2013-01-01

Full Text Available The paper presents a performance analysis of novel CMOS Integrated pseudo-PMOS ISFET (PP-ISFET having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which is used for water quality monitoring. The conventional devices, generally used, consume high power and are not stable for long term monitoring. The conventional device has the drawbacks of low value of slew rate, high power consumption, and nonlinear characteristics, but in this novel design, due to zero static power, less load capacitance on input signals, faster switching, fewer transistors, and higher circuit density, the device exhibits a better slew rate and piecewise linear characteristics and is seen consuming low power of the order of 30 mW. The proposed circuit reduces total power consumption per cycle, increases the speed of operation, is fairly linear, and is simple to implement.

Recent Results with a segmented Hybrid Photon Detector for a novel parallax-free PET Scanner for Brain Imaging

CERN Document Server

Braem, André; Joram, Christian; Mathot, Serge; Séguinot, Jacques; Weilhammer, Peter; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

2007-01-01

We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is laid on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

Integrated development environment for fuzzy logic applications

Science.gov (United States)

Pagni, Andrea; Poluzzi, Rinaldo; Rizzotto, GianGuido; Lo Presti, Matteo

1993-12-01

During the last five years, Fuzzy Logic has gained enormous popularity, both in the academic and industrial worlds, breaking up the traditional resistance against changes thanks to its innovative approach to problems formalization. The success of this new methodology is pushing the creation of a brand new class of devices, called Fuzzy Machines, to overcome the limitations of traditional computing systems when acting as Fuzzy Systems and adequate Software Tools to efficiently develop new applications. This paper aims to present a complete development environment for the definition of fuzzy logic based applications. The environment is also coupled with a sophisticated software tool for semiautomatic synthesis and optimization of the rules with stability verifications. Later it is presented the architecture of WARP, a dedicate VLSI programmable chip allowing to compute in real time a fuzzy control process. The article is completed with two application examples, which have been carried out exploiting the aforementioned tools and devices.

Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

CERN Document Server

Ramachandran, S

2007-01-01

Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

An integrated fiber and stone basket device for use in Thulium fiber laser lithotripsy

Science.gov (United States)

Wilson, Christopher R.; Hutchens, Thomas C.; Hardy, Luke A.; Irby, Pierce B.; Fried, Nathaniel M.

2014-03-01

The Thulium fiber laser (TFL) is being explored as an alternative laser lithotripter to the Holmium:YAG laser. The TFL's superior near-single mode beam profile enables higher power transmission through smaller fibers with reduced proximal fiber tip damage. Recent studies have also reported that attaching hollow steel tubing to the distal fiber tip decreases fiber degradation and burn-back without compromising stone ablation rates. However, significant stone retropulsion was observed, which increased with pulse rate. In this study, the hollow steel tip fiber design was integrated with a stone basket to minimize stone retropulsion during ablation. A device was constructed consisting of a 100-μm-core, 140-μm-OD silica fiber outfitted with 5-mm-long stainless steel tubing at the distal tip, and integrated with a 1.3-Fr (0.433-mm-OD) disposable nitinol wire basket, to form an overall 1.9-Fr (0.633-mm- OD) integrated device. This compact design may provide several potential advantages including increased flexibility, higher saline irrigation rates through the ureteroscope working channel, and reduced fiber tip degradation compared to separate fiber and stone basket manipulation. TFL pulse energy of 31.5 mJ with 500 μs pulse duration and pulse rate of 500 Hz was delivered through the integrated fiber/basket device in contact with human uric acid stones, ex vivo. TFL stone ablation rates measured 1.5 +/- 0.2 mg/s, comparable to 1.7 +/- 0.3 mg/s (P > 0.05) using standard bare fiber tips separately with a stone basket. With further development, this device may be useful for minimizing stone retropulsion, thus enabling more efficient TFL lithotripsy at higher pulse rates.

Microfluidic device for continuous single cells analysis via Raman spectroscopy enhanced by integrated plasmonic nanodimers

DEFF Research Database (Denmark)

Perozziello, Gerardo; Candeloro, Patrizio; De Grazia, Antonio

2016-01-01

In this work a Raman flow cytometer is presented. It consists of a microfluidic device that takes advantages of the basic principles of Raman spectroscopy and flow cytometry. The microfluidic device integrates calibrated microfluidic channels-where the cells can flow one-by-one -, allowing single...... cell Raman analysis. The microfluidic channel integrates plasmonic nanodimers in a fluidic trapping region. In this way it is possible to perform Enhanced Raman Spectroscopy on single cell. These allow a label-free analysis, providing information about the biochemical content of membrane and cytoplasm...

Label swapper device for spectral amplitude coded optical packet networks monolithically integrated on InP.

Science.gov (United States)

Muñoz, P; García-Olcina, R; Habib, C; Chen, L R; Leijtens, X J M; de Vries, T; Robbins, D; Capmany, J

2011-07-04

In this paper the design, fabrication and experimental characterization of an spectral amplitude coded (SAC) optical label swapper monolithically integrated on Indium Phosphide (InP) is presented. The device has a footprint of 4.8x1.5 mm2 and is able to perform label swapping operations required in SAC at a speed of 155 Mbps. The device was manufactured in InP using a multiple purpose generic integration scheme. Compared to previous SAC label swapper demonstrations, using discrete component assembly, this label swapper chip operates two order of magnitudes faster.

Integrating the results of user research into medical device development: insights from a case study.

Science.gov (United States)

Martin, Jennifer L; Barnett, Julie

2012-07-19

It is well established that considering users is an important aspect of medical device development. However it is also well established that there are numerous barriers to successfully conducting user research and integrating the results into product development. It is not sufficient to simply conduct user research, it must also be effectively integrated into product development. A case study of the development of a new medical imaging device was conducted to examine in detail how users were involved in a medical device development project. Two user research studies were conducted: a requirements elicitation interview study and an early prototype evaluation using contextual inquiry. A descriptive in situ approach was taken to investigate how these studies contributed to the product development process and how the results of this work influenced the development of the technology. Data was collected qualitatively through interviews with the development team, participant observation at development meetings and document analysis. The focus was on investigating the barriers that exist to prevent user data from being integrated into product development. A number of individual, organisational and system barriers were identified that functioned to prevent the results of the user research being fully integrated into development. The user and technological aspects of development were seen as separate work streams during development. The expectations of the developers were that user research would collect requirements for the appearance of the device, rather than challenge its fundamental concept. The manner that the user data was communicated to the development team was not effective in conveying the significance or breadth of the findings. There are a range of informal and formal organisational processes that can affect the uptake of user data during medical device development. Adopting formal decision making processes may assist manufacturers to take a more integrated and

Integrating the results of user research into medical device development: insights from a case study

Directory of Open Access Journals (Sweden)

Martin Jennifer L

2012-07-01

Full Text Available Abstract Background It is well established that considering users is an important aspect of medical device development. However it is also well established that there are numerous barriers to successfully conducting user research and integrating the results into product development. It is not sufficient to simply conduct user research, it must also be effectively integrated into product development. Methods A case study of the development of a new medical imaging device was conducted to examine in detail how users were involved in a medical device development project. Two user research studies were conducted: a requirements elicitation interview study and an early prototype evaluation using contextual inquiry. A descriptive in situ approach was taken to investigate how these studies contributed to the product development process and how the results of this work influenced the development of the technology. Data was collected qualitatively through interviews with the development team, participant observation at development meetings and document analysis. The focus was on investigating the barriers that exist to prevent user data from being integrated into product development. Results A number of individual, organisational and system barriers were identified that functioned to prevent the results of the user research being fully integrated into development. The user and technological aspects of development were seen as separate work streams during development. The expectations of the developers were that user research would collect requirements for the appearance of the device, rather than challenge its fundamental concept. The manner that the user data was communicated to the development team was not effective in conveying the significance or breadth of the findings. Conclusion There are a range of informal and formal organisational processes that can affect the uptake of user data during medical device development. Adopting formal decision

Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

Directory of Open Access Journals (Sweden)

Horiuchi Timothy

2003-01-01

Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

International Nuclear Information System (INIS)

Sawadsaringkarn, Y; Kimura, H; Maezawa, Y; Nakajima, A; Kobayashi, T; Sasagawa, K; Noda, T; Tokuda, T; Ohta, J

2012-01-01

A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

A High Performance VLSI Computer Architecture For Computer Graphics

Science.gov (United States)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

Crystalline Silicon Interconnected Strips (XIS). Introduction to a New, Integrated Device and Module Concept

Energy Technology Data Exchange (ETDEWEB)

Van Roosmalen, J.; Bronsveld, P.; Mewe, A.; Janssen, G.; Stodolny, M.; Cobussen-Pool, E.; Bennett, I.; Weeber, A.; Geerligs, B. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG, Petten (Netherlands)

2012-06-15

A new device concept for high efficiency, low cost, wafer based silicon solar cells is introduced. To significantly lower the costs of Si photovoltaics, high efficiencies and large reductions of metals and silicon costs are required. To enable this, the device architecture was adapted into low current devices by applying thin silicon strips, to which a special high efficiency back-contact heterojunction cell design was applied. Standard industrial production processes can be used for our fully integrated cell and module design, with a cost reduction potential below 0.5 euro/Wp. First devices have been realized demonstrating the principle of a series connected back contact hybrid silicon heterojunction module concept.

Monolithic integration of optical waveguides for absorbance detection in microfabricated electrophoresis devices

DEFF Research Database (Denmark)

Mogensen, Klaus Bo; Petersen, Nickolaj Jacob; Hübner, Jörg

2001-01-01

. The waveguides on the device were connected to optical fibers, which enabled alignment free operation due to the absence of free-space optics. A 750 mum long U-shaped detection cell was used to facilitate longitudinal absorption detection. To minimize geometrically induced band broadening at the turn in the U......The fabrication and performance of an electrophoretic separation chip with integrated of optical waveguides for absorption detection is presented. The device was fabricated on a silicon substrate by standard microfabrication techniques with the use of two photolithographic mask steps...

Integration of dispenser-printed ultra-low-voltage thermoelectric and energy storage devices

International Nuclear Information System (INIS)

Wang, Z; Chen, A; Winslow, R; Madan, D; Nill, M; Wright, P K; Juang, R C; Evans, J W

2012-01-01

This paper reports on an integrated energy harvesting prototype that consists of dispenser-printed thermoelectric energy harvesting and electrochemical energy storage devices. Parallel-connected thermoelectric devices with low internal resistances were designed, fabricated and characterized. The use of a commercially available dc-to-dc converter was explored to step-up a 27.1 mV input voltage from a printed thermoelectric device to a regulated 2.34 V output at a maximum of 34% conversion efficiency. The regulated power succeeds in charging dispenser-printed, zinc-based micro-batteries with charging efficiencies of up to 67%. The prototype presented in this work demonstrates the feasibility of deploying a printable, cost-effective and perpetual power solution for practical wireless sensor network applications. (paper)

Methods for integrating a functional component into a microfluidic device

Science.gov (United States)

Simmons, Blake; Domeier, Linda; Woo, Noble; Shepodd, Timothy; Renzi, Ronald F.

2014-08-19

Injection molding is used to form microfluidic devices with integrated functional components. One or more functional components are placed in a mold cavity, which is then closed. Molten thermoplastic resin is injected into the mold and then cooled, thereby forming a solid substrate including the functional component(s). The solid substrate including the functional component(s) is then bonded to a second substrate, which may include microchannels or other features.

The development of differential inductors using double air-bridge structure based on integrated passive device technology

Science.gov (United States)

Li, Yang; Yao, Zhao; Fu, Xiao-Qian; Li, Zhi-Ming; Shan, Fu-Kai; Wang, Cong

2017-05-01

Recently, integrated passive devices have become increasingly popular; inductor realization, in particular, offers interesting high performance for RF modules and systems. In this paper, a development of differential inductor fabricated by integrated passive devices technology using a double air-bridge structure is presented. A study of the model development of the differential inductor is first demonstrated. In this model section, a segment box analysis method is applied to provide a clear presentation of the differential inductor. Compared with other work that only shows a brief description of the process, the integrated passive devices process used to fabricate the inductor in this study is elaborated on. Finally, a characterization of differential inductors with different physical layout parameters is illustrated based on inductance and quality factors, which provides a valuable reference for realizing high performance. The proposed work provides a good solution for the design, fabrication and practical application of RF modules and systems.

Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

Institute of Scientific and Technical Information of China (English)

Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

2012-01-01

Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

Automated microfluidic devices integrating solid-phase extraction, fluorescent labeling, and microchip electrophoresis for preterm birth biomarker analysis.

Science.gov (United States)

Sahore, Vishal; Sonker, Mukul; Nielsen, Anna V; Knob, Radim; Kumar, Suresh; Woolley, Adam T

2018-01-01

We have developed multichannel integrated microfluidic devices for automated preconcentration, labeling, purification, and separation of preterm birth (PTB) biomarkers. We fabricated multilayer poly(dimethylsiloxane)-cyclic olefin copolymer (PDMS-COC) devices that perform solid-phase extraction (SPE) and microchip electrophoresis (μCE) for automated PTB biomarker analysis. The PDMS control layer had a peristaltic pump and pneumatic valves for flow control, while the PDMS fluidic layer had five input reservoirs connected to microchannels and a μCE system. The COC layers had a reversed-phase octyl methacrylate porous polymer monolith for SPE and fluorescent labeling of PTB biomarkers. We determined μCE conditions for two PTB biomarkers, ferritin (Fer) and corticotropin-releasing factor (CRF). We used these integrated microfluidic devices to preconcentrate and purify off-chip-labeled Fer and CRF in an automated fashion. Finally, we performed a fully automated on-chip analysis of unlabeled PTB biomarkers, involving SPE, labeling, and μCE separation with 1 h total analysis time. These integrated systems have strong potential to be combined with upstream immunoaffinity extraction, offering a compact sample-to-answer biomarker analysis platform. Graphical abstract Pressure-actuated integrated microfluidic devices have been developed for automated solid-phase extraction, fluorescent labeling, and microchip electrophoresis of preterm birth biomarkers.

Real time track finding in a drift chamber with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-01-01

In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices.

Science.gov (United States)

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F; Ross, Caroline A

2013-11-08

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO₂ -δ , Co- or Fe-substituted SrTiO 3- δ , as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti 0.2 Ga 0.4 Fe 0.4 )O 3- δ and polycrystalline (CeY₂)Fe₅O 12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY₂)Fe₅O 12 /silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Novel developments in mobile sensing based on the integration of microfluidic devices and smartphones.

Science.gov (United States)

Yang, Ke; Peretz-Soroka, Hagit; Liu, Yong; Lin, Francis

2016-03-21

Portable electronic devices and wireless communication systems enable a broad range of applications such as environmental and food safety monitoring, personalized medicine and healthcare management. Particularly, hybrid smartphone and microfluidic devices provide an integrated solution for the new generation of mobile sensing applications. Such mobile sensing based on microfluidic devices (broadly defined) and smartphones (MS(2)) offers a mobile laboratory for performing a wide range of bio-chemical detection and analysis functions such as water and food quality analysis, routine health tests and disease diagnosis. MS(2) offers significant advantages over traditional platforms in terms of test speed and control, low cost, mobility, ease-of-operation and data management. These improvements put MS(2) in a promising position in the fields of interdisciplinary basic and applied research. In particular, MS(2) enables applications to remote in-field testing, homecare, and healthcare in low-resource areas. The marriage of smartphones and microfluidic devices offers a powerful on-chip operating platform to enable various bio-chemical tests, remote sensing, data analysis and management in a mobile fashion. The implications of such integration are beyond telecommunication and microfluidic-related research and technology development. In this review, we will first provide the general background of microfluidic-based sensing, smartphone-based sensing, and their integration. Then, we will focus on several key application areas of MS(2) by systematically reviewing the important literature in each area. We will conclude by discussing our perspectives on the opportunities, issues and future directions of this emerging novel field.

Novel Developments of Mobile Sensing Based on the Integration of Microfluidic Devices and Smartphone

Science.gov (United States)

Yang, Ke; Peretz-Soroka, Hagit; Liu, Yong; Lin, Francis

2016-01-01

Portable electronic devices and wireless communication systems enable a broad range of applications such as environmental and food safety monitoring, personalized medicine and healthcare management. Particularly, hybrid smartphone and microfluidic devices provide an integrated solution for the new generation of mobile sensing applications. Such mobile sensing based on microfluidic devices (broadly defined) and smartphones (MS2) offers a mobile laboratory for performing a wide range of bio-chemical detection and analysis functions such as water and food quality analysis, routine health tests and disease diagnosis. MS2 offers significant advantages over traditional platforms in terms of test speed and control, low cost, mobility, ease-of-operation and data management. These improvements put MS2 in a promising position in the fields of interdisciplinary basic and applied research. In particular, MS2 enables applications to remote infield testing, homecare, and healthcare in low-resource areas. The marriage of smartphones and microfluidic devices offers a powerful on-chip operating platform to enable various bio-chemical tests, remote sensing, data analysis and management in a mobile fashion. The implications of such integration are beyond telecommunication and microfluidic-related research and technology development. In this review, we will first provide the general background of microfluidic-based sensing, smartphone-based sensing, and their integration. Then, we will focus on several key application areas of MS2 by systematically reviewing the important literature in each area. We will conclude by discussing our perspectives on the opportunities, issues and future directions of this emerging novel field. PMID:26899264

Portable blood extraction device integrated with biomedical monitoring system

Science.gov (United States)

Khumpuang, S.; Horade, M.; Fujioka, K.; Sugiyama, S.

2006-01-01

Painless and portable blood extraction device has been immersed in the world of miniaturization on bio-medical research particularly in manufacturing point-of-care systems. The fabrication of a blood extraction device integrated with an electrolyte-monitoring system is reported in this paper. The device has advantages in precise controlled dosage of blood extracted including the slightly damaged blood vessels and nervous system. The in-house blood diagnostic will become simple for the patients. Main components of the portable system are; the blood extraction device and electrolyte-monitoring system. The monitoring system consists of ISFET (Ion Selective Field Effect Transistor) for measuring the concentration level of minerals in blood. In this work, we measured the level of 3 ions; Na+, K+ and Cl-. The mentioned ions are frequently required the measurement since their concentration levels in the blood can indicate whether the kidney, pancreas, liver or heart is being malfunction. The fabrication of the whole system and experimentation on each ISM (Ion Sensitive Membrane) will be provided. Taking the advantages of LIGA technology, the 100 hollow microneedles fabricated by Synchrotron Radiation deep X-ray lithography through PCT (Plane-pattern to Cross-section Transfer) technique have been consisted in 5x5 mm2 area. The microneedle is 300 μm in base-diameter, 500 μm-pitch, 800 μm-height and 50 μm hole-diameter. The total size of the blood extraction device is 2x2x2 cm 3. The package is made from a plastic socket including slots for inserting microneedle array and ISFET connecting to an electrical circuit for the monitoring. Through the dimensional design for simply handling and selection of disposable material, the patients can self-evaluate the critical level of the body minerals in anywhere and anytime.

The gate oxide integrity of CVD tungsten polycide

International Nuclear Information System (INIS)

Wu, N.W.; Su, W.D.; Chang, S.W.; Tseng, M.F.

1988-01-01

CVD tungsten polycide has been demonstrated as a good gate material in recent very large scale integration (VLSI) technology. CVD tungsten silicide offers advantages of low resistivity, high temperature stability and good step coverage. On the other hand, the polysilicon underlayer preserves most characteristics of the polysilicon gate and acts as a stress buffer layer to absorb part of the thermal stress origin from the large thermal expansion coefficient of tungsten silicide. Nevertheless, the gate oxide of CVD tungsten polycide is less stable or reliable than that of polysilicon gate. In this paper, the gate oxide integrity of CVD tungsten polycide with various thickness combinations and different thermal processes have been analyzed by several electrical measurements including breakdown yield, breakdown fluence, room temperature TDDB, I-V characteristics, electron traps and interface state density

Integration of smart wearable mobile devices and cloud computing in South African healthcare

CSIR Research Space (South Africa)

Mvelase, PS

2015-11-01

Full Text Available Integration of Smart Wearable Mobile Devices and Cloud Computing in South African Healthcare Promise MVELASE, Zama DLAMINI, Angeline DLUDLA, Happy SITHOLE Abstract: The acceptance of cloud computing is increasing in a fast pace in distributed...

CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

International Nuclear Information System (INIS)

Seidl, Albert; Klose, Helmut; Svoboda, Mildos

2004-01-01

1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

Space Radiation Environment Prediction for VLSI microelectronics devices onboard a LEO Satellite using OMERE-Trad Software

Science.gov (United States)

Sajid, Muhammad

This tutorial/survey paper presents the assessment/determination of level of hazard/threat to emerging microelectronics devices in Low Earth Orbit (LEO) space radiation environment with perigee at 300 Km, apogee at 600Km altitude having different orbital inclinations to predict the reliability of onboard Bulk Built-In Current Sensor (BBICS) fabricated in 350nm technology node at OptMA Lab. UFMG Brazil. In this context, the various parameters for space radiation environment have been analyzed to characterize the ionizing radiation environment effects on proposed BBICS. The Space radiation environment has been modeled in the form of particles trapped in Van-Allen radiation belts(RBs), Energetic Solar Particles Events (ESPE) and Galactic Cosmic Rays (GCR) where as its potential effects on Device- Under-Test (DUT) has been predicted in terms of Total Ionizing Dose (TID), Single-Event Effects (SEE) and Displacement Damage Dose (DDD). Finally, the required mitigation techniques including necessary shielding requirements to avoid undesirable effects of radiation environment at device level has been estimated /determined with assumed standard thickness of Aluminum shielding. In order to evaluate space radiation environment and analyze energetic particles effects on BBICS, OMERE toolkit developed by TRAD was utilized.

Integrated optical circuits for numerical computation

Science.gov (United States)

Verber, C. M.; Kenan, R. P.

1983-01-01

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

DEFF Research Database (Denmark)

Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

1991-01-01

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

Directory of Open Access Journals (Sweden)

Mehmet Cengiz Onbasli

2013-11-01

Full Text Available Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4O3−δ and polycrystalline (CeY2Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Device for the integral measurement of ionizing radiations

International Nuclear Information System (INIS)

Micheron, Francois.

1980-01-01

This invention relates to devices for the integral determination of ionizing radiations, particularly to the construction of a portable dosemeter. Portable measuring instruments have been suggested in the past, particularly dosemeters in which the discharge of a capacitor under the action of ionizing radiations is measured. Since the charge of a capacitor is not stable owing to dielectric imperfections, these measuring instruments have to be recalibrated at frequent intervals. To overcome this drawback, the invention suggests using the discharge of an electret, electrically charged to a pre-set initial value, under the action of ionizing radiations, as the transducer means of a dosemeter used in conjunction with display or warning systems [fr

Fabrication of integrated metallic MEMS devices

DEFF Research Database (Denmark)

Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

2002-01-01

A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators are characteri......A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

International Nuclear Information System (INIS)

Kim, Y; Pham, C; Chang, J P

2015-01-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

Nanowire-integrated microporous silicon membrane for continuous fluid transport in micro cooling device

International Nuclear Information System (INIS)

So, Hongyun; Pisano, Albert P.; Cheng, Jim C.

2013-01-01

We report an efficient passive micro pump system combining the physical properties of nanowires and micropores. This nanowire-integrated microporous silicon membrane was created to feed coolant continuously onto the surface of the wick in a micro cooling device to ensure it remains hydrated and in case of dryout, allow for regeneration of the system. The membrane was fabricated by photoelectrochemical etching to form micropores followed by hydrothermal growth of nanowires. This study shows a promising approach to address thermal management challenges for next generation electronic devices with absence of external power

Integrated electrokinetically driven microfluidic devices with pH-mediated solid-phase extraction coupled to microchip electrophoresis for preterm birth biomarkers.

Science.gov (United States)

Sonker, Mukul; Knob, Radim; Sahore, Vishal; Woolley, Adam T

2017-07-01

Integration in microfluidics is important for achieving automation. Sample preconcentration integrated with separation in a microfluidic setup can have a substantial impact on rapid analysis of low-abundance disease biomarkers. Here, we have developed a microfluidic device that uses pH-mediated solid-phase extraction (SPE) for the enrichment and elution of preterm birth (PTB) biomarkers. Furthermore, this SPE module was integrated with microchip electrophoresis for combined enrichment and separation of multiple analytes, including a PTB peptide biomarker (P1). A reversed-phase octyl methacrylate monolith was polymerized as the SPE medium in polyethylene glycol diacrylate modified cyclic olefin copolymer microfluidic channels. Eluent for pH-mediated SPE of PTB biomarkers on the monolith was optimized using different pH values and ionic concentrations. Nearly 50-fold enrichment was observed in single channel SPE devices for a low nanomolar solution of P1, with great elution time reproducibility (electrophoresis in our integrated device with ∼15-fold enrichment. This device shows important progress towards an integrated electrokinetically operated platform for preconcentration and separation of biomarkers. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integrative Multi-Spectral Sensor Device for Far-Infrared and Visible Light Fusion

Science.gov (United States)

Qiao, Tiezhu; Chen, Lulu; Pang, Yusong; Yan, Gaowei

2018-06-01

Infrared and visible light image fusion technology is a hot spot in the research of multi-sensor fusion technology in recent years. Existing infrared and visible light fusion technologies need to register before fusion because of using two cameras. However, the application effect of the registration technology has yet to be improved. Hence, a novel integrative multi-spectral sensor device is proposed for infrared and visible light fusion, and by using the beam splitter prism, the coaxial light incident from the same lens is projected to the infrared charge coupled device (CCD) and visible light CCD, respectively. In this paper, the imaging mechanism of the proposed sensor device is studied with the process of the signals acquisition and fusion. The simulation experiment, which involves the entire process of the optic system, signal acquisition, and signal fusion, is constructed based on imaging effect model. Additionally, the quality evaluation index is adopted to analyze the simulation result. The experimental results demonstrate that the proposed sensor device is effective and feasible.

Microfluidic device for continuous single cells analysis via Raman spectroscopy enhanced by integrated plasmonic nanodimers

KAUST Repository

Perozziello, Gerardo

2015-12-11

In this work a Raman flow cytometer is presented. It consists of a microfluidic device that takes advantages of the basic principles of Raman spectroscopy and flow cytometry. The microfluidic device integrates calibrated microfluidic channels- where the cells can flow one-by-one -, allowing single cell Raman analysis. The microfluidic channel integrates plasmonic nanodimers in a fluidic trapping region. In this way it is possible to perform Enhanced Raman Spectroscopy on single cell. These allow a label-free analysis, providing information about the biochemical content of membrane and cytoplasm of the each cell. Experiments are performed on red blood cells (RBCs), peripheral blood lymphocytes (PBLs) and myelogenous leukemia tumor cells (K562). © 2015 Optical Society of America.

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

Science.gov (United States)

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Science.gov (United States)

McEwan, Alistair; van Schaik, André

2003-12-01

The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

Science.gov (United States)

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Graphene-Based Integrated Photovoltaic Energy Harvesting/Storage Device.

Science.gov (United States)

Chien, Chih-Tao; Hiralal, Pritesh; Wang, Di-Yan; Huang, I-Sheng; Chen, Chia-Chun; Chen, Chun-Wei; Amaratunga, Gehan A J

2015-06-24

Energy scavenging has become a fundamental part of ubiquitous sensor networks. Of all the scavenging technologies, solar has the highest power density available. However, the energy source is erratic. Integrating energy conversion and storage devices is a viable route to obtain self-powered electronic systems which have long-term maintenance-free operation. In this work, we demonstrate an integrated-power-sheet, consisting of a string of series connected organic photovoltaic cells (OPCs) and graphene supercapacitors on a single substrate, using graphene as a common platform. This results in lighter and more flexible power packs. Graphene is used in different forms and qualities for different functions. Chemical vapor deposition grown high quality graphene is used as a transparent conductor, while solution exfoliated graphene pastes are used as supercapacitor electrodes. Solution-based coating techniques are used to deposit the separate components onto a single substrate, making the process compatible with roll-to-roll manufacture. Eight series connected OPCs based on poly(3-hexylthiophene)(P3HT):phenyl-C61-butyric acid methyl ester (PC60 BM) bulk-heterojunction cells with aluminum electrodes, resulting in a ≈5 V open-circuit voltage, provide the energy harvesting capability. Supercapacitors based on graphene ink with ≈2.5 mF cm(-2) capacitance provide the energy storage capability. The integrated-power-sheet with photovoltaic (PV) energy harvesting and storage functions had a mass of 0.35 g plus the substrate. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integrative device and process of oxidization, degassing, acidity adjustment of 1BP from APOR process

Energy Technology Data Exchange (ETDEWEB)

Zuo, Chen; Zheng, Weifang, E-mail: wfazh@ciae.ac.cn; Yan, Taihong; He, Hui; Li, Gaoliang; Chang, Shangwen; Li, Chuanbo; Yuan, Zhongwei

2016-02-15

Graphical abstract: Previous (left) and present (right) device of oxidation, degassing, acidity adjustment of 1BP. - Highlights: • We designed an integrative device and process. • The utilization efficiency of N{sub 2}O{sub 4} is increased significantly. • Our work results in considerable simplification of the device. • Process parameters are determined by experiments. - Abstract: Device and process of oxidization, degassing, acidity adjustment of 1BP (The Pu production feed from U/Pu separation section) from APOR process (Advanced Purex Process based on Organic Reductants) were improved through rational design and experiments. The device was simplified and the process parameters, such as feed position and flow ratio, were determined by experiments. Based on this new device and process, the reductants N,N-dimethylhydroxylamine (DMHAN) and methylhydrazine (MMH) in 1BP solution could be oxidized with much less N{sub 2}O{sub 4} consumption.

The Integration of GPS Navigator Device with Vehicles Tracking System for Rental Cars Firms

OpenAIRE

Omarah O. Alharaki; Fahad S. Alaieri; Akram M. Zeki

2010-01-01

The aim of this research is to integrate the GPS tracking system (tracking device and web-based application) with GPS navigator for rental cars, allowing the company to use various applications to monitor and manage the cars. This is enable the firms and customers to communicate with each other via the GPS navigator. The system should be developed by applying new features in GPS tracking application devices in vehicles. This paper also proposes new features that can be applied to the GPS Navi...

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Directory of Open Access Journals (Sweden)

Urard Pascal

2006-01-01

Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

Facilitating Integration of Electron Beam Lithography Devices with Interactive Videodisc, Computer-Based Simulation and Job Aids.

Science.gov (United States)

Von Der Linn, Robert Christopher

A needs assessment of the Grumman E-Beam Systems Group identified the requirement for additional skill mastery for the engineers who assemble, integrate, and maintain devices used to manufacture integrated circuits. Further analysis of the tasks involved led to the decision to develop interactive videodisc, computer-based job aids to enable…

Controlling Underwater Robots with Electronic Nervous Systems

Directory of Open Access Journals (Sweden)

Joseph Ayers

2010-01-01

Full Text Available We are developing robot controllers based on biomimetic design principles. The goal is to realise the adaptive capabilities of the animal models in natural environments. We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration electronic neuron (aVLSI networks. DTM networks are realised using neurons based on a 1-D or 2-D Map with two additional parameters that define silent, spiking and bursting regimes. Electronic neurons (ENs based on Hindmarsh–Rose (HR dynamics can be instantiated in analogue VLSI and exhibit similar behaviour to those based on discrete components. We have constructed locomotor central pattern generators (CPGs with aVLSI networks that can be modulated to select different behaviours on the basis of selective command input. The two technologies can be fused by interfacing the signals from the DTM circuits directly to the aVLSI CPGs. Using DTMs, we have been able to simulate complex sensory fusion for rheotaxic behaviour based on both hydrodynamic and optical flow senses. We will illustrate aspects of controllers for ambulatory biomimetic robots. These studies indicate that it is feasible to fabricate an electronic nervous system controller integrating both aVLSI CPGs and layered DTM exteroceptive reflexes.

A compact electroencephalogram recording device with integrated audio stimulation system

Science.gov (United States)

Paukkunen, Antti K. O.; Kurttio, Anttu A.; Leminen, Miika M.; Sepponen, Raimo E.

2010-06-01

A compact (96×128×32 mm3, 374 g), battery-powered, eight-channel electroencephalogram recording device with an integrated audio stimulation system and a wireless interface is presented. The recording device is capable of producing high-quality data, while the operating time is also reasonable for evoked potential studies. The effective measurement resolution is about 4 nV at 200 Hz sample rate, typical noise level is below 0.7 μVrms at 0.16-70 Hz, and the estimated operating time is 1.5 h. An embedded audio decoder circuit reads and plays wave sound files stored on a memory card. The activities are controlled by an 8 bit main control unit which allows accurate timing of the stimuli. The interstimulus interval jitter measured is less than 1 ms. Wireless communication is made through bluetooth and the data recorded are transmitted to an external personal computer (PC) interface in real time. The PC interface is implemented with LABVIEW® and in addition to data acquisition it also allows online signal processing, data storage, and control of measurement activities such as contact impedance measurement, for example. The practical application of the device is demonstrated in mismatch negativity experiment with three test subjects.

Future evolution of the Fast TracKer (FTK) processing unit

CERN Document Server

Gentsos, C; The ATLAS collaboration; Giannetti, P; Magalotti, D; Nikolaidis, S

2014-01-01

The Fast Tracker (FTK) processor [1] for the ATLAS experiment has a computing core made of 128 Processing Units that reconstruct tracks in the silicon detector in a ~100 μsec deep pipeline. The track parameter resolution provided by FTK enables the HLT trigger to identify efficiently and reconstruct significant samples of fermionic Higgs decays. Data processing speed is achieved with custom VLSI pattern recognition, linearized track fitting executed inside modern FPGAs, pipelining, and parallel processing. One large FPGA executes full resolution track fitting inside low resolution candidate tracks found by a set of 16 custom Asic devices, called Associative Memories (AM chips) [2]. The FTK dual structure, based on the cooperation of VLSI dedicated AM and programmable FPGAs, is maintained to achieve further technology performance, miniaturization and integration of the current state of the art prototypes. This allows to fully exploit new applications within and outside the High Energy Physics field. We plan t...

ELEC-2002: Electronics in HEP

CERN Multimedia

Davide Vitè

2002-01-01

ELEC-2002 is a 15-session modern electronic course, given by CERN physicists and engineers, in a new format within the framework of the Technical Training Programme. This course is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2002 is composed of two terms: sessions take place on Tuesdays and Thursdays from 14h00 to 16h30. Spring term: Integrated circuits and VLSI technology for physics (April 2002) Introduction to VLSI (Paulo Moreira, 9 April) Basic digital design (Paulo Moreira, 11 April) Analogue design technologies (Francis Anghinolfi, 16 April) Radiation effects in electronics devices and circuits (Federico Faccio, 18 April) Digital design: design methodology and tools (Jorgen Christiansen, 23 April) Digital design: production (Jorgen Christiansen, 25 Apr...

Integrated base stations and a method of transmitting data units in a communications system for mobile devices

NARCIS (Netherlands)

Bosch, H.G.P.; Mullender, Sape J.; Narlikar, G.J.; Samuel, L.G.; Yagati, L.N.

2006-01-01

Integrated base stations and a method of transmitting data units in a communications system for mobile devices. In one embodiment, an integrated base station includes a communications processor having a protocol stack configured with a media access control layer and a physical layer.

Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

Science.gov (United States)

Cai, Jinguang; Lv, Chao; Watanabe, Akira

2018-01-10

Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

A surface-integral-equation approach to the propagation of waves in EBG-based devices

NARCIS (Netherlands)

Lancellotti, V.; Tijhuis, A.G.

2012-01-01

We combine surface integral equations with domain decomposition to formulate and (numerically) solve the problem of electromagnetic (EM) wave propagation inside finite-sized structures. The approach is of interest for (but not limited to) the analysis of devices based on the phenomenon of

Monolithic photonic integration technology platform and devices at wavelengths beyond 2 μm for gas spectroscopy applications

NARCIS (Netherlands)

Latkowski, S.; van Veldhoven, P.J.; Hänsel, A.; D'Agostino, D.; Rabbani-Haghighi, H.; Docter, B.; Bhattacharya, N.; Thijs, P.J.A.; Ambrosius, H.P.M.M.; Smit, M.K.; Williams, K.A.; Bente, E.A.J.M.

2017-01-01

In this paper a generic monolithic photonic integration technology platform and tunable laser devices for gas sensing applications at 2 μm will be presented. The basic set of long wavelength optical functions which is fundamental for a generic photonic integration approach is realized using planar,

Single integrated device for optical CDMA code processing in dual-code environment.

Science.gov (United States)

Huang, Yue-Kai; Glesk, Ivan; Greiner, Christoph M; Iazkov, Dmitri; Mossberg, Thomas W; Wang, Ting; Prucnal, Paul R

2007-06-11

We report on the design, fabrication and performance of a matching integrated optical CDMA encoder-decoder pair based on holographic Bragg reflector technology. Simultaneous encoding/decoding operation of two multiple wavelength-hopping time-spreading codes was successfully demonstrated and shown to support two error-free OCDMA links at OC-24. A double-pass scheme was employed in the devices to enable the use of longer code length.

Organic Optical Sensor Based on Monolithic Integration of Organic Electronic Devices

Directory of Open Access Journals (Sweden)

Hoi Lam Tam

2015-09-01

Full Text Available A novel organic optical sensor that integrates a front organic light-emitting diode (OLED and an organic photodiode (OPD is demonstrated. The stripe-shaped cathode is used in the OLED components to create light signals, while the space between the stripe-shaped cathodes serves as the detection window for integrated OPD units. A MoO3 (5 nm/Ag (15 nm bi-layer inter-electrode is interposed between the vertically stacked OLED and OPD units, serving simultaneously as the cathode for the front OLED and an anode for the upper OPD units in the sensor. In the integrated sensor, the emission of the OLED units is confined by the area of the opaque stripe-shaped cathodes, optimized to maximize the reflected light passing through the window space for detection by the OPD components. This can ensure high OLED emission output, increasing the signal/noise ratio. The design and fabrication flexibility of an integrated OLED/OPD device also has low cost benefits, and is light weight and ultra-thin, making it possible for application in wearable units, finger print identification, image sensors, smart light sources, and compact information systems.

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1982-01-01

A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

Fabrication and Characterization of All-Polystyrene Microfluidic Devices with Integrated Electrodes and Tubing.

Science.gov (United States)

Pentecost, Amber M; Martin, R Scott

2015-01-01

A new method of fabricating all-polystyrene devices with integrated electrodes and fluidic tubing is described. As opposed to expensive polystyrene (PS) fabrication techniques that use hot embossing and bonding with a heated lab press, this approach involves solvent-based etching of channels and lamination-based bonding of a PS cover, all of which do not need to occur in a clean room. PS has been studied as an alternative microchip substrate to PDMS, as it is more hydrophilic, biologically compatible in terms of cell adhesion, and less prone to absorption of hydrophobic molecules. The etching/lamination-based method described here results in a variety of all-PS devices, with or without electrodes and tubing. To characterize the devices, micrographs of etched channels (straight and intersected channels) were taken using confocal and scanning electron microscopy. Microchip-based electrophoresis with repetitive injections of fluorescein was conducted using a three-sided PS (etched pinched, twin-tee channel) and one-sided PDMS device. Microchip-based flow injection analysis, with dopamine and NO as analytes, was used to characterize the performance of all-PS devices with embedded tubing and electrodes. Limits of detection for dopamine and NO were 130 nM and 1.8 μM, respectively. Cell immobilization studies were also conducted to assess all-PS devices for cellular analysis. This paper demonstrates that these easy to fabricate devices can be attractive alternative to other PS fabrication methods for a wide variety of analytical and cell culture applications.

Indoor Navigation Design Integrated with Smart Phones and Rfid Devices

Science.gov (United States)

Ortakci, Y.; Demiral, E.; Atila, U.; Karas, I. R.

2015-10-01

High rise, complex and huge buildings in the cities are almost like a small city with their tens of floors, hundreds of corridors and rooms and passages. Due to size and complexity of these buildings, people need guidance to find their way to the destination in these buildings. In this study, a mobile application is developed to visualize pedestrian's indoor position as 3D in their smartphone and RFID Technology is used to detect the position of pedestrian. While the pedestrian is walking on his/her way on the route, smartphone will guide the pedestrian by displaying the photos of indoor environment on the route. Along the tour, an RFID (Radio-Frequency Identification) device is integrated to the system. The pedestrian will carry the RFID device during his/her tour in the building. The RFID device will send the position data to the server directly in every two seconds periodically. On the other side, the pedestrian will just select the destination point in the mobile application on smartphone and sent the destination point to the server. The shortest path from the pedestrian position to the destination point is found out by the script on the server. This script also sends the environment photo of the first node on the acquired shortest path to the client as an indoor navigation module.

Micro- and nano-scale optical devices for high density photonic integrated circuits at near-infrared wavelengths

Science.gov (United States)

Chatterjee, Rohit

In this research work, we explore fundamental silicon-based active and passive photonic devices that can be integrated together to form functional photonic integrated circuits. The devices which include power splitters, switches and lenses are studied starting from their physics, their design and fabrication techniques and finally from an experimental standpoint. The experimental results reveal high performance devices that are compatible with standard CMOS fabrication processes and can be easily integrated with other devices for near infrared telecom applications. In Chapter 2, a novel method for optical switching using nanomechanical proximity perturbation technique is described and demonstrated. The method which is experimentally demonstrated employs relatively low powers, small chip footprint and is compatible with standard CMOS fabrication processes. Further, in Chapter 3, this method is applied to develop a hitless bypass switch aimed at solving an important issue in current wavelength division multiplexing systems namely hitless switching of reconfigurable optical add drop multiplexers. Experimental results are presented to demonstrate the application of the nanomechanical proximity perturbation technique to practical situations. In Chapter 4, a fundamental photonic component namely the power splitter is described. Power splitters are important components for any photonic integrated circuits because they help split the power from a single light source to multiple devices on the same chip so that different operations can be performed simultaneously. The power splitters demonstrated in this chapter are based on multimode interference principles resulting in highly compact low loss and highly uniform power splitting to split the power of the light from a single channel to two and four channels. These devices can further be scaled to achieve higher order splitting such as 1x16 and 1x32 power splits. Finally in Chapter 5 we overcome challenges in device

Optically induced dielectropheresis sorting with automated medium exchange in an integrated optofluidic device resulting in higher cell viability.

Science.gov (United States)

Lee, Gwo-Bin; Wu, Huan-Chun; Yang, Po-Fu; Mai, John D

2014-08-07

We demonstrated the integration of a microfluidic device with an optically induced dielectrophoresis (ODEP) device such that the critical medium replacement process was performed automatically and the cells could be subsequently manipulated by using digitally projected optical images. ODEP has been demonstrated to generate sufficient forces for manipulating particles/cells by projecting a light pattern onto photoconductive materials which creates virtual electrodes. The production of the ODEP force usually requires a medium that has a suitable electrical conductivity and an appropriate dielectric constant. Therefore, a 0.2 M sucrose solution is commonly used. However, this requires a complicated medium replacement process before one is able to manipulate cells. Furthermore, the 0.2 M sucrose solution is not suitable for the long-term viability of cells. In comparison to conventional manual processes, our automated medium replacement process only took 25 minutes. Experimental data showed that there was up to a 96.2% recovery rate for the manipulated cells. More importantly, the survival rate of the cells was greatly enhanced due to this faster automated process. This newly developed microfluidic chip provided a promising platform for the rapid replacement of the cell medium and this was also the first time that an ODEP device was integrated with other active flow control components in a microfluidic device. By improving cell viability after cell manipulation, this design may contribute to the practical integration of ODEP modules into other lab-on-a-chip devices and biomedical applications in the future.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Directory of Open Access Journals (Sweden)

Alistair McEwan

2003-06-01

Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

FISHprep: A Novel Integrated Device for Metaphase FISH Sample Preparation

DEFF Research Database (Denmark)

Shah, Pranjul Jaykumar; Vedarethinam, Indumathi; Kwasny, Dorota

2011-01-01

We present a novel integrated device for preparing metaphase chromosomes spread slides (FISHprep). The quality of cytogenetic analysis from patient samples greatly relies on the efficiency of sample pre-treatment and/or slide preparation. In cytogenetic slide preparation, cell cultures...... are routinely used to process samples (for culture, arrest and fixation of cells) and/or to expand limited amount of samples (in case of prenatal diagnostics). Arguably, this expansion and other sample pretreatments form the longest part of the entire diagnostic protocols spanning over 3–4 days. We present here...... with minimal handling for metaphase FISH slide preparation....

Design of a terminal solution for integration of in-home health care devices and services towards the Internet-of-Things

Science.gov (United States)

Pang, Zhibo; Zheng, Lirong; Tian, Junzhe; Kao-Walter, Sharon; Dubrova, Elena; Chen, Qiang

2015-01-01

In-home health care services based on the Internet-of-Things are promising to resolve the challenges caused by the ageing of population. But the existing research is rather scattered and shows lack of interoperability. In this article, a business-technology co-design methodology is proposed for cross-boundary integration of in-home health care devices and services. In this framework, three key elements of a solution (business model, device and service integration architecture and information system integration architecture) are organically integrated and aligned. In particular, a cooperative Health-IoT ecosystem is formulated, and information systems of all stakeholders are integrated in a cooperative health cloud as well as extended to patients' home through the in-home health care station (IHHS). Design principles of the IHHS includes the reuse of 3C platform, certification of the Health Extension, interoperability and extendibility, convenient and trusted software distribution, standardised and secured electrical health care record handling, effective service composition and efficient data fusion. These principles are applied to the design of an IHHS solution called iMedBox. Detailed device and service integration architecture and hardware and software architecture are presented and verified by an implemented prototype. The quantitative performance analysis and field trials have confirmed the feasibility of the proposed design methodology and solution.

An electrically actuated imperfect microbeam: Dynamical integrity for interpreting and predicting the device response

KAUST Repository

Ruzziconi, Laura

2013-02-20

In this study we deal with a microelectromechanical system (MEMS) and develop a dynamical integrity analysis to interpret and predict the experimental response. The device consists of a clamped-clamped polysilicon microbeam, which is electrostatically and electrodynamically actuated. It has non-negligible imperfections, which are a typical consequence of the microfabrication process. A single-mode reduced-order model is derived and extensive numerical simulations are performed in a neighborhood of the first symmetric natural frequency, via frequency response diagrams and behavior chart. The typical softening behavior is observed and the overall scenario is explored, when both the frequency and the electrodynamic voltage are varied. We show that simulations based on direct numerical integration of the equation of motion in time yield satisfactory agreement with the experimental data. Nevertheless, these theoretical predictions are not completely fulfilled in some aspects. In particular, the range of existence of each attractor is smaller in practice than in the simulations. This is because these theoretical curves represent the ideal limit case where disturbances are absent, which never occurs under realistic conditions. A reliable prediction of the actual (and not only theoretical) range of existence of each attractor is essential in applications. To overcome this discrepancy and extend the results to the practical case where disturbances exist, a dynamical integrity analysis is developed. After introducing dynamical integrity concepts, integrity profiles and integrity charts are drawn. They are able to describe if each attractor is robust enough to tolerate the disturbances. Moreover, they detect the parameter range where each branch can be reliably observed in practice and where, instead, becomes vulnerable, i.e. they provide valuable information to operate the device in safe conditions according to the desired outcome and depending on the expected disturbances

77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

Science.gov (United States)

2012-11-14

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation in its Entirety AGENCY: U.S. International Trade Commission. ACTION...

1 million-Q optomechanical microdisk resonators for sensing with very large scale integration

Science.gov (United States)

Hermouet, M.; Sansa, M.; Banniard, L.; Fafin, A.; Gely, M.; Allain, P. E.; Santos, E. Gil; Favero, I.; Alava, T.; Jourdan, G.; Hentz, S.

2018-02-01

Cavity optomechanics have become a promising route towards the development of ultrasensitive sensors for a wide range of applications including mass, chemical and biological sensing. In this study, we demonstrate the potential of Very Large Scale Integration (VLSI) with state-of-the-art low-loss performance silicon optomechanical microdisks for sensing applications. We report microdisks exhibiting optical Whispering Gallery Modes (WGM) with 1 million quality factors, yielding high displacement sensitivity and strong coupling between optical WGMs and in-plane mechanical Radial Breathing Modes (RBM). Such high-Q microdisks with mechanical resonance frequencies in the 102 MHz range were fabricated on 200 mm wafers with Variable Shape Electron Beam lithography. Benefiting from ultrasensitive readout, their Brownian motion could be resolved with good Signal-to-Noise ratio at ambient pressure, as well as in liquid, despite high frequency operation and large fluidic damping: the mechanical quality factor reduced from few 103 in air to 10's in liquid, and the mechanical resonance frequency shifted down by a few percent. Proceeding one step further, we performed an all-optical operation of the resonators in air using a pump-probe scheme. Our results show our VLSI process is a viable approach for the next generation of sensors operating in vacuum, gas or liquid phase.

Neuron Stimulation Device Integrated with Silicon Nanowire-Based Photodetection Circuit on a Flexible Substrate

Directory of Open Access Journals (Sweden)

Suk Won Jung

2016-12-01

Full Text Available This paper proposes a neural stimulation device integrated with a silicon nanowire (SiNW-based photodetection circuit for the activation of neurons with light. The proposed device is comprised of a voltage divider and a current driver in which SiNWs are used as photodetector and field-effect transistors; it has the functions of detecting light, generating a stimulation signal in proportion to the light intensity, and transmitting the signal to a micro electrode. To show the applicability of the proposed neural stimulation device as a high-resolution retinal prosthesis system, a high-density neural stimulation device with a unit cell size of 110 × 110 μ m and a resolution of 32 × 32 was fabricated on a flexible film with a thickness of approximately 50 μm. Its effectiveness as a retinal stimulation device was then evaluated using a unit cell in an in vitro animal experiment involving the retinal tissue of retinal Degeneration 1 (rd1 mice. Experiments wherein stimulation pulses were applied to the retinal tissues successfully demonstrate that the number of spikes in neural response signals increases in proportion to light intensity.

Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

Energy Technology Data Exchange (ETDEWEB)

Liu, T.; Deptuch, G.; Hoff, J.; Jindariani, S.; Joshi, S.; Olsen, J.; Tran, N.; Trimpl, M.

2015-02-01

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

Very high frame rate volumetric integration of depth images on mobile devices.

Science.gov (United States)

Kähler, Olaf; Adrian Prisacariu, Victor; Yuheng Ren, Carl; Sun, Xin; Torr, Philip; Murray, David

2015-11-01

Volumetric methods provide efficient, flexible and simple ways of integrating multiple depth images into a full 3D model. They provide dense and photorealistic 3D reconstructions, and parallelised implementations on GPUs achieve real-time performance on modern graphics hardware. To run such methods on mobile devices, providing users with freedom of movement and instantaneous reconstruction feedback, remains challenging however. In this paper we present a range of modifications to existing volumetric integration methods based on voxel block hashing, considerably improving their performance and making them applicable to tablet computer applications. We present (i) optimisations for the basic data structure, and its allocation and integration; (ii) a highly optimised raycasting pipeline; and (iii) extensions to the camera tracker to incorporate IMU data. In total, our system thus achieves frame rates up 47 Hz on a Nvidia Shield Tablet and 910 Hz on a Nvidia GTX Titan XGPU, or even beyond 1.1 kHz without visualisation.

A City Parking Integration System Combined with Cloud Computing Technologies and Smart Mobile Devices

Science.gov (United States)

Yeh, Her-Tyan; Chen, Bing-Chang; Wang, Bo-Xun

2016-01-01

The current study applied cloud computing technology and smart mobile devices combined with a streaming server for parking lots to plan a city parking integration system. It is also equipped with a parking search system, parking navigation system, parking reservation service, and car retrieval service. With this system, users can quickly find…

Multi-purpose logical device with integrated circuit for the automation of mine water disposal

Energy Technology Data Exchange (ETDEWEB)

Pop, E.; Pasculescu, M.

1980-06-01

After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Fabrication and characterization of an integrated ionic device from suspended polypyrrole and alamethicin-reconstituted lipid bilayer membranes

International Nuclear Information System (INIS)

Northcutt, Robert; Sundaresan, Vishnu-Baba

2012-01-01

Conducting polymers are electroactive materials that undergo conformal relaxation of the polymer backbone in the presence of an electrical field through ion exchange with solid or aqueous electrolytes. This conformal relaxation and the associated morphological changes make conducting polymers highly suitable for actuation and sensing applications. Among smart materials, bioderived active materials also use ion transport for sensing and actuation functions via selective ion transport. The transporter proteins extracted from biological cell membranes and reconstituted into a bilayer lipid membrane in bioderived active materials regulate ion transport for engineering functions. The protein transporter reconstituted in the bilayer lipid membrane is referred to as the bioderived membrane and serves as the active component in bioderived active materials. Inspired by the similarities in the physics of transduction in conducting polymers and bioderived active materials, an integrated ionic device is formed from the bioderived membrane and the conducting polymer membrane. This ionic device is fabricated into a laminated thin-film membrane and a common ion that can be processed by the bioderived and the conducting polymer membranes couple the ionic function of these two membranes. An integrated ionic device, fabricated from polypyrrole (PPy) doped with sodium dodecylbenzenesulfonate (NaDBS) and an alamethicin-reconstituted DPhPC bilayer lipid membrane, is presented in this paper. A voltage-gated sodium current regulates the electrochemical response in the PPy(DBS) layer. The integrated device is fabricated on silicon-based substrates through microfabrication, electropolymerization, and vesicle fusion, and ionic activity is characterized through electrochemical measurements. (paper)

System-on-fluidics immunoassay device integrating wireless radio-frequency-identification sensor chips.

Science.gov (United States)

Yazawa, Yoshiaki; Oonishi, Tadashi; Watanabe, Kazuki; Shiratori, Akiko; Funaoka, Sohei; Fukushima, Masao

2014-09-01

A simple and sensitive point-of-care-test (POCT) device for chemiluminescence (CL) immunoassay was devised and tested. The device consists of a plastic flow-channel reactor and two wireless-communication sensor chips, namely, a photo-sensor chip and a temperature-sensor chip. In the flow-channel reactor, a target antigen is captured by an antibody immobilized on the inner wall of the flow-channel and detected with enzyme labeled antibody by using CL substrate. The CL signal corresponding to the amount of antigen is measured by a newly developed radio-frequency-identification (RFID) sensor, which enables batteryless operation and wireless data communication with an external reader. As for the POCT device, its usage environment, especially temperature, varies for each measurement. Hence, temperature compensation is a key issue in regard to eliminating dark-signal fluctuation, which is a major factor in deterioration of the precision of the POCT device. A two-stage temperature-compensation scheme was adopted. As for the first stage, the signals of two photodiodes, one with an open window and one with a sealed window, integrated on the photo-sensor chip are differentiated to delete the dark signal. As for the second stage, the differentiated signal fluctuation caused by a temperature variation is compensated by using the other sensor chip (equipped with a temperature sensor). The dark-level fluctuation caused by temperature was reduced from 0.24 to 0.02 pA/°C. The POCT device was evaluated as a CL immunoassay of thyroid-stimulating hormone (TSH). The flow rate of the CL reagent in the flow channel was optimized. As a result, the detection limit of the POCT device was 0.08 ng/ml (i.e., 0.4 μIU/ml). Copyright © 2014 The Society for Biotechnology, Japan. Published by Elsevier B.V. All rights reserved.

Three-Dimensional Hetero-Integration of Faceted GaN on Si Pillars for Efficient Light Energy Conversion Devices.

Science.gov (United States)

Kim, Dong Rip; Lee, Chi Hwan; Cho, In Sun; Jang, Hanmin; Jeon, Min Soo; Zheng, Xiaolin

2017-07-25

An important pathway for cost-effective light energy conversion devices, such as solar cells and light emitting diodes, is to integrate III-V (e.g., GaN) materials on Si substrates. Such integration first necessitates growth of high crystalline III-V materials on Si, which has been the focus of many studies. However, the integration also requires that the final III-V/Si structure has a high light energy conversion efficiency. To accomplish these twin goals, we use single-crystalline microsized Si pillars as a seed layer to first grow faceted Si structures, which are then used for the heteroepitaxial growth of faceted GaN films. These faceted GaN films on Si have high crystallinity, and their threading dislocation density is similar to that of GaN grown on sapphire. In addition, the final faceted GaN/Si structure has great light absorption and extraction characteristics, leading to improved performance for GaN-on-Si light energy conversion devices.

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

Science.gov (United States)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

Science.gov (United States)

Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

1989-01-01

The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

A new laryngeal mask supraglottic airway device with integrated balloon line: a descriptive and comparative bench study

Directory of Open Access Journals (Sweden)

Zhou YH

2016-11-01

Full Text Available YingHai Zhou,1 Korinne Jew2 1Research & Development, Patient Monitoring & Recovery, Medtronic Technology Center, Shanghai, People’s Republic of China; 2Medical Affairs, Minimally Invasive Therapies Group, Medtronic, Boulder, CO, USA Abstract: Laryngeal masks are invasive devices for airway management placed in the supraglottic position. The Shiley™ laryngeal mask (Shiley™ LM features an integrated inflation tube and airway shaft to facilitate product insertion and reduce the chance of tube occlusion when patients bite down. This study compared the Shiley LM to two other disposable laryngeal mask devices, the Ambu® AuraStraight™ and the LMA Unique™. Overall device design, tensile strength, flexibility of various structures, and sealing performance were measured. The Shiley LM is structurally stronger and its shaft is more resistant to compression than the other devices. The Shiley LM is generally less flexible than the other devices, but this relationship varies with device size. Sealing performance of the devices was similar in a bench assay. The results of this bench study demonstrate that the new Shiley LM resembles other commercially available laryngeal mask devices, though it exhibits greater tensile strength and lower flexibility. Keywords: laryngeal mask, supraglottic airway, supralaryngeal device

Transparent Electrodes Based on Silver Nanowire Networks: From Physical Considerations towards Device Integration.

Science.gov (United States)

Bellet, Daniel; Lagrange, Mélanie; Sannicolo, Thomas; Aghazadehchors, Sara; Nguyen, Viet Huong; Langley, Daniel P; Muñoz-Rojas, David; Jiménez, Carmen; Bréchet, Yves; Nguyen, Ngoc Duy

2017-05-24

The past few years have seen a considerable amount of research devoted to nanostructured transparent conducting materials (TCM), which play a pivotal role in many modern devices such as solar cells, flexible light-emitting devices, touch screens, electromagnetic devices, and flexible transparent thin film heaters. Currently, the most commonly used TCM for such applications (ITO: Indium Tin oxide) suffers from two major drawbacks: brittleness and indium scarcity. Among emerging transparent electrodes, silver nanowire (AgNW) networks appear to be a promising substitute to ITO since such electrically percolating networks exhibit excellent properties with sheet resistance lower than 10 Ω/sq and optical transparency of 90%, fulfilling the requirements of most applications. In addition, AgNW networks also exhibit very good mechanical flexibility. The fabrication of these electrodes involves low-temperature processing steps and scalable methods, thus making them appropriate for future use as low-cost transparent electrodes in flexible electronic devices. This contribution aims to briefly present the main properties of AgNW based transparent electrodes as well as some considerations relating to their efficient integration in devices. The influence of network density, nanowire sizes, and post treatments on the properties of AgNW networks will also be evaluated. In addition to a general overview of AgNW networks, we focus on two important aspects: (i) network instabilities as well as an efficient Atomic Layer Deposition (ALD) coating which clearly enhances AgNW network stability and (ii) modelling to better understand the physical properties of these networks.

Integrating Sphere-based Weathering Device

Data.gov (United States)

Federal Laboratory Consortium — Description:In the artificial ultraviolet (UV) weathering of materials, a need exists for weathering devices that can uniformly illuminate test specimens with a high...

An Integrated Quantum Dot Barcode Smartphone Optical Device for Wireless Multiplexed Diagnosis of Infected Patients

Science.gov (United States)

Ming, Kevin

Integrating mobile-cellular devices with multiplex molecular diagnostics can potentially provide the most powerful platform for tracking, managing and preventing the transmission of infectious diseases. With over 6.9 billion subscriptions globally, handheld mobile-cellular devices can be programmed to spatially map, temporally track, and transmit information on infections over wide geographical space and boundaries. Current cell phone diagnostic technologies have poor limit of detection, dynamic range, and cannot detect multiple pathogen targets simultaneously, limiting their utility to single infections with high load. Here we combined recent advances in quantum dot barcode technology for molecular detection with smartphones to engineer a simple and low-cost chip-based wireless multiplex diagnostic device. We validated our device using a variety of synthetic genomic targets for the respiratory virus and blood-borne pathogens, and demonstrated that it could detect clinical samples after simple amplification. More importantly, we confirmed that the device is capable of detecting patients infected with a single or multiple infectious pathogens (e.g., HIV and hepatitis B) in a single test. This device advances the capacity for global surveillance of infectious diseases and has the potential to accelerate knowledge exchange-transfer of emerging or exigent disease threats with healthcare and military organizations in real-time.

Medical device integration: CIOs must bridge the digital divide between devices and electronic medical records.

Science.gov (United States)

Raths, David

2009-02-01

To get funding approved for medical device integration, ClOs suggest focusing on specific patient safety or staff efficiency pain points. Organizations that make clinical engineering part of their IT team report fewer chain-of-command issues. It also helps IT people understand the clinical goals because the engineering people have been working closely with clinicians for years. A new organization has formed to work on collaboration between clinical engineers and IT professionals. For more information, go to www.ceitcollaboration.org. ECRI Institute has written a guide to handling the convergence of medical technology and hospital networks. Its "Medical Technology for the IT Professional: An Essential Guide for Working in Today's Healthcare Setting" also details how IT professionals can assist hospital technology planning and acquisition, and provide ongoing support for IT-based medical technologies. For more information, visit www.ecri.org/ITresource.

Label swapper device for spectral amplitude coded optical packet networks monolithically integrated on InP

NARCIS (Netherlands)

Muñoz, P.; García-Olcina, R.; Habib, C.; Chen, L.R.; Leijtens, X.J.M.; Vries, de T.; Robbins, D.J.; Capmany, J.

2011-01-01

In this paper the design, fabrication and experimental characterization of an spectral amplitude coded (SAC) optical label swapper monolithically integrated on Indium Phosphide (InP) is presented. The device has a footprint of 4.8x1.5 mm2 and is able to perform label swapping operations required in

A simple and cost-effective method for fabrication of integrated electronic-microfluidic devices using a laser-patterned PDMS layer

KAUST Repository

Li, Ming

2011-12-03

We report a simple and cost-effective method for fabricating integrated electronic-microfluidic devices with multilayer configurations. A CO 2 laser plotter was employed to directly write patterns on a transferred polydimethylsiloxane (PDMS) layer, which served as both a bonding and a working layer. The integration of electronics in microfluidic devices was achieved by an alignment bonding of top and bottom electrode-patterned substrates fabricated with conventional lithography, sputtering and lift-off techniques. Processes of the developed fabrication method were illustrated. Major issues associated with this method as PDMS surface treatment and characterization, thickness-control of the transferred PDMS layer, and laser parameters optimization were discussed, along with the examination and testing of bonding with two representative materials (glass and silicon). The capability of this method was further demonstrated by fabricating a microfluidic chip with sputter-coated electrodes on the top and bottom substrates. The device functioning as a microparticle focusing and trapping chip was experimentally verified. It is confirmed that the proposed method has many advantages, including simple and fast fabrication process, low cost, easy integration of electronics, strong bonding strength, chemical and biological compatibility, etc. © Springer-Verlag 2011.

Integrating wireless sensor networks with CE devices for health care activity tracking in the home environment

NARCIS (Netherlands)

Bosman, R.P.; Lukkien, J.J.; Verhoeven, R.

2009-01-01

Wireless sensing devices containing limited processing and communication capabilities are becoming available for all sorts of purposes. An important problem is to integrate networks of these sensors with the existing CE en IT infrastructure such that a) data coming out of the sensor network can be

Femtosecond Laser Direct Write Integration of Multi-Protein Patterns and 3D Microstructures into 3D Glass Microfluidic Devices

Directory of Open Access Journals (Sweden)

Daniela Serien

2018-01-01

Full Text Available Microfluidic devices and biochips offer miniaturized laboratories for the separation, reaction, and analysis of biochemical materials with high sensitivity and low reagent consumption. The integration of functional or biomimetic elements further functionalizes microfluidic devices for more complex biological studies. The recently proposed ship-in-a-bottle integration based on laser direct writing allows the construction of microcomponents made of photosensitive polymer inside closed microfluidic structures. Here, we expand this technology to integrate proteinaceous two-dimensional (2D and three-dimensional (3D microstructures with the aid of photo-induced cross-linking into glass microchannels. The concept is demonstrated with bovine serum albumin and enhanced green fluorescent protein, each mixed with photoinitiator (Sodium 4-[2-(4-Morpholino benzoyl-2-dimethylamino] butylbenzenesulfonate. Unlike the polymer integration, fabrication over the entire channel cross-section is challenging. Two proteins are integrated into the same channel to demonstrate multi-protein patterning. Using 50% w/w glycerol solvent instead of 100% water achieves almost the same fabrication resolution for in-channel fabrication as on-surface fabrication due to the improved refractive index matching, enabling the fabrication of 3D microstructures. A glycerol-water solvent also reduces the risk of drying samples. We believe this technology can integrate diverse proteins to contribute to the versatility of microfluidics.

Integration of human factors and ergonomics during medical device design and development: it's all about communication.

Science.gov (United States)

Vincent, Christopher James; Li, Yunqiu; Blandford, Ann

2014-05-01

Manufacturers of interactive medical devices, such as infusion pumps, need to ensure that devices minimise the risk of unintended harm during use. However, development teams face challenges in incorporating Human Factors. The aim of the research reported here was to better understand the constraints under which medical device design and development take place. We report the results of a qualitative study based on 19 semi-structured interviews with professionals involved in the design, development and deployment of interactive medical devices. A thematic analysis was conducted. Multiple barriers to designing for safety and usability were identified. In particular, we identified barriers to communication both between the development organisation and the intended users and between different teams within the development organisation. We propose the use of mediating representations. Artefacts such as personas and scenarios, known to provide integration across multiple perspectives, are an essential component of designing for safety and usability. Copyright © 2013 Elsevier Ltd and The Ergonomics Society. All rights reserved.

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

Science.gov (United States)

Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

2012-01-01

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Emergent auditory feature tuning in a real-time neuromorphic VLSI system

Directory of Open Access Journals (Sweden)

Sadique eSheik

2012-02-01

Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Integration of Mobile Devices to Facilitate Patient Care and Teaching During Family-Centered Rounds.

Science.gov (United States)

Byrd, Angela S; McMahon, Pamela M; Vath, Richard J; Bolton, Michael; Roy, Melissa

2018-01-01

The increasing prevalence of mobile devices in clinical settings has the potential to improve both patient care and education. The benefits are particularly promising in the context of family-centered rounds in inpatient pediatric settings. We aimed to increase mobile device usage by inpatient rounding teams by 50% in 6 months. We hoped to demonstrate that use of mobile devices would improve access to patient care and educational information and to determine if use would improve efficiency and perceptions of clinical teaching. We designed a mixed-methods study involving pre- and post-implementation surveys to residents, families, and faculty as well as direct observations of family-centered rounds. We conducted rapid cycles of continual quality improvement by using the Plan-Do-Study-Act framework involving 3 interventions. Pre-intervention, the mobile computing cart was used for resident education on average 3.3 times per rounding session. After cycle 3, teaching through the use of mobile devices increased by ∼79% to 5.9 times per rounding session. On the basis of survey data, we determined there was a statistically significant increase in residents' perception of feeling prepared for rounds, receiving teaching on clinical care, and ability to teach families. Additionally, average time spent per patient on rounds decreased after implementation of mobile devices. Integration of mobile devices into a pediatric hospital medicine teaching service can facilitate patient care and perception of resident teaching by extending the utility of electronic medical records in care decisions and by improving access to knowledge resources. Copyright © 2018 by the American Academy of Pediatrics.

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

Three-dimensional image acquisition and reconstruction system on a mobile device based on computer-generated integral imaging.

Science.gov (United States)

Erdenebat, Munkh-Uchral; Kim, Byeong-Jun; Piao, Yan-Ling; Park, Seo-Yeon; Kwon, Ki-Chul; Piao, Mei-Lan; Yoo, Kwan-Hee; Kim, Nam

2017-10-01

A mobile three-dimensional image acquisition and reconstruction system using a computer-generated integral imaging technique is proposed. A depth camera connected to the mobile device acquires the color and depth data of a real object simultaneously, and an elemental image array is generated based on the original three-dimensional information for the object, with lens array specifications input into the mobile device. The three-dimensional visualization of the real object is reconstructed on the mobile display through optical or digital reconstruction methods. The proposed system is implemented successfully and the experimental results certify that the system is an effective and interesting method of displaying real three-dimensional content on a mobile device.

Silicon Carbide Power Devices and Integrated Circuits

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

OC ToGo: bed site image integration into OpenClinica with mobile devices

Science.gov (United States)

Haak, Daniel; Gehlen, Johan; Jonas, Stephan; Deserno, Thomas M.

2014-03-01

Imaging and image-based measurements nowadays play an essential role in controlled clinical trials, but electronic data capture (EDC) systems insufficiently support integration of captured images by mobile devices (e.g. smartphones and tablets). The web application OpenClinica has established as one of the world's leading EDC systems and is used to collect, manage and store data of clinical trials in electronic case report forms (eCRFs). In this paper, we present a mobile application for instantaneous integration of images into OpenClinica directly during examination on patient's bed site. The communication between the Android application and OpenClinica is based on the simple object access protocol (SOAP) and representational state transfer (REST) web services for metadata, and secure file transfer protocol (SFTP) for image transfer, respectively. OpenClinica's web services are used to query context information (e.g. existing studies, events and subjects) and to import data into the eCRF, as well as export of eCRF metadata and structural information. A stable image transfer is ensured and progress information (e.g. remaining time) visualized to the user. The workflow is demonstrated for a European multi-center registry, where patients with calciphylaxis disease are included. Our approach improves the EDC workflow, saves time, and reduces costs. Furthermore, data privacy is enhanced, since storage of private health data on the imaging devices becomes obsolete.

Heterogeneous MEMS device assembly and integration

Science.gov (United States)

Topart, Patrice; Picard, Francis; Ilias, Samir; Alain, Christine; Chevalier, Claude; Fisette, Bruno; Paultre, Jacques E.; Généreux, Francis; Legros, Mathieu; Lepage, Jean-François; Laverdière, Christian; Ngo Phong, Linh; Caron, Jean-Sol; Desroches, Yan

2014-03-01

In recent years, smart phone applications have both raised the pressure for cost and time to market reduction, and the need for high performance MEMS devices. This trend has led the MEMS community to develop multi-die packaging of different functionalities or multi-technology (i.e. wafer) approaches to fabricate and assemble devices respectively. This paper reports on the fabrication, assembly and packaging at INO of various MEMS devices using heterogeneous assembly at chip and package-level. First, the performance of a giant (e.g. about 3 mm in diameter), electrostatically actuated beam steering mirror is presented. It can be rotated about two perpendicular axes to steer an optical beam within an angular cone of up to 60° in vector scan mode with an angular resolution of 1 mrad and a response time of 300 ms. To achieve such angular performance relative to mirror size, the microassembly was performed from sub-components fabricated from 4 different wafers. To combine infrared detection with inertial sensing, an electroplated proof mass was flip-chipped onto a 256×1 pixel uncooled bolometric FPA and released using laser ablation. In addition to the microassembly technology, performance results of packaged devices are presented. Finally, to simulate a 3072×3 pixel uncooled detector for cloud and fire imaging in mid and long-wave IR, the staggered assembly of six 512×3 pixel FPAs with a less than 50 micron pixel co-registration is reported.

Neutron measuring device

International Nuclear Information System (INIS)

Hatayama, Akiyoshi; Seki, Eiji; Kita, Yoshio; Nishitani, Takeo.

1993-01-01

The device of the present invention concerns measurement for neutrons in a tokamak type thermonuclear device and it can measure total amount of generated neutrons accurately throughout the operation period even if an error is caused in counted values by plasma disruption. That is, the device comprises (1) a means for detecting presence or absence of occurrence of plasma disruption and the time for the initiation of the occurrence, (2) a first data processing means for processing detection signals, (3) a means for detecting neutrons generated in plasmas and (4) a second data processing means for calculating integrated values for the number of neutrons generated from the start to the completion of electric discharge when no disruption occurs and calculating integrated values for the number of generated neutrons from the start of electric discharge to the time at the initiation of occurrence of the disruption when disruption is present. In the thus constituted device, even if an error is caused by frequent occurrence of plasma disruption, total time integrated amount of neutrons generated in the plasmas can be measured accurately. (I.S.)

Plasma facing device of thermonuclear device

International Nuclear Information System (INIS)

Sumita, Hideo; Ioki, Kimihiro.

1993-01-01

The present invention improves integrity of thermal structures of a plasma facing device. That is, in the plasma facing device, an armour block portion from a metal cooling pipe to a carbon material comprises a mixed material of the metal as the constituent material of the cooling pipe and ceramics. Then, the mixing ratio of the composition is changed continuously or stepwise to suppress peakings of remaining stresses upon production and thermal stresses upon exertion of thermal loads. Accordingly, thermal integrity of the structural materials can further be improved. In this case, a satisfactory characteristic can be obtained also by using ceramics instead of carbon for the mixed material, and the characteristic such as heat expansion coefficient is similar to that of the armour tile. (I.S.)

Water Capture Device Signal Integration Board

Science.gov (United States)

Chamberlin, Kathryn J.; Hartnett, Andrew J.

2018-01-01

I am a junior in electrical engineering at Arizona State University, and this is my second internship at Johnson Space Center. I am an intern in the Command and Data Handling Branch of Avionics Division (EV2), my previous internship was also in EV2. During my previous internship I was assigned to the Water Capture Device payload, where I designed a prototype circuit board for the electronics system of the payload. For this internship, I have come back to the Water Capture Device project to further the work on the electronics design I completed previously. The Water Capture Device is an experimental payload to test the functionality of two different phase separators aboard the International Space Station (ISS). A phase separator sits downstream of a condensing heat exchanger (CHX) and separates the water from the air particles for environmental control on the ISS. With changing CHX technology, new phase separators are required. The goal of the project is to develop a test bed for the two phase separators to determine the best solution.

Electrochemical solid-phase microextraction of anions and cations using polypyrrole coatings and an integrated three-electrode device.

Science.gov (United States)

Liljegren, Gustav; Pettersson, Jean; Markides, Karin E; Nyholm, Leif

2002-05-01

A method for the extraction, transfer and desorption of anions and cations under controlled potential conditions employing a new integrated three-electrode device is described. The device, containing working, reference and counter electrodes, was prepared from tubes that could be moved vertically with respect to each other. In this way, a small amount of solvent, held by capillary force, remained between the electrodes when the device was lifted out of a solution after an extraction. This design allowed the potential control to be maintained at all times. With the new integrated device, it was possible to perform potential controlled desorption into vials containing as little as 200 microl of solution. The required ion exchange capacity was obtained by electrodeposition of a polypyrrole coating on the surface of the glassy carbon working electrode. Solid-phase microextractions of several cations or anions were performed simultaneously under potentiostatic control by doping the polypyrrole coating with different anions such as perchlorate and p-toluenesulfonate. The efficiency of the extractions, which could be altered by varying the potential of the working electrode, could be increased by 150 to 200% compared to extractions using normal solid-phase microextraction conditions under open circuit conditions. A constant potential of +1.0 V and -0.5 V with respect to the silver pseudo reference electrode, was found to be well-suited for the extraction of samples containing ppm concentrations of anions (chloride, nitrite, bromide, nitrate, sulfate and phosphate) and cations (cadmium, cobalt and zinc), respectively.

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

Science.gov (United States)

2012-03-29

...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR 210.8(b)).

Coupled Cryogenic Thermal and Electrical Models for Transient Analysis of Superconducting Power Devices with Integrated Cryogenic Systems

Science.gov (United States)

Satyanarayana, S.; Indrakanti, S.; Kim, J.; Kim, C.; Pamidi, S.

2017-12-01

Benefits of an integrated high temperature superconducting (HTS) power system and the associated cryogenic systems on board an electric ship or aircraft are discussed. A versatile modelling methodology developed to assess the cryogenic thermal behavior of the integrated system with multiple HTS devices and the various potential configurations are introduced. The utility and effectiveness of the developed modelling methodology is demonstrated using a case study involving a hypothetical system including an HTS propulsion motor, an HTS generator and an HTS power cable cooled by an integrated cryogenic helium circulation system. Using the methodology, multiple configurations are studied. The required total cooling power and the ability to maintain each HTS device at the required operating temperatures are considered for each configuration and the trade-offs are discussed for each configuration. Transient analysis of temperature evolution in the cryogenic helium circulation loop in case of a system failure is carried out to arrive at the required critical response time. The analysis was also performed for a similar liquid nitrogen circulation for an isobaric condition and the cooling capacity ratio is used to compare the relative merits of the two cryogens.

A comprehensive model on field-effect pnpn devices (Z2-FET)

Science.gov (United States)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

Integrated electrochromic iris device for low power and space-limited applications

International Nuclear Information System (INIS)

Deutschmann, T; Oesterschulze, E

2014-01-01

We present a micro-electrooptical iris based on the electrochromic polymer poly(3,4-ethylenedioxythiophene). Two ring-shaped concentric polymer-segments embedded in a transparent electrochemical cell form the micro iris. The polymer layers change their absorption when an external voltage is applied. This iris device benefits from the absence of any mechanically moving part. This renders a very slim design possible, which is suited for small integrated camera systems. During operation the polymer maintains its absorbing state without power consumption. Its low driving voltage of maximum 1.5 V is beneficial for battery powered applications. The impact of the iris on the depth of focus and transmission control as well as its dynamical behavior will be addressed. (paper)

Studies of the LBL CMOS integrated amplifier/discriminator for randomly timed inputs from fixed target experiments

International Nuclear Information System (INIS)

Russ, J.S.; Yarema, R.J.; Zimmerman, T.

1988-12-01

A group at Lawrence Berkeley Laboratory has reported an elegant CMOS VLSI circuit for amplifying, discriminating, and encoding the signals from highly-segmented charge output devices, e.g., silicon strip detectors or pad readout structures in gaseous detectors. The design exploits switched capacitor circuits and the well-known time structure of data acquisition in colliding beam accelerators to cancel leakage effects and switching noise. For random inputs, these methods are not directly applicable. However, the high speed of the reset switches makes possible a mode of operation for fixed target experiments that uses fast resets to erase unwanted data from random triggers. Data acquisition in this mode has been performed. Details of operation and measurements of noise and rate capability will be presented. 8 refs., 6 figs

An in-fiber integrated optofluidic device based on an optical fiber with an inner core.

Science.gov (United States)

Yang, Xinghua; Yuan, Tingting; Teng, Pingping; Kong, Depeng; Liu, Chunlan; Li, Entao; Zhao, Enming; Tong, Chengguo; Yuan, Libo

2014-06-21

A new kind of optofluidic in-fiber integrated device based on a specially designed hollow optical fiber with an inner core is designed. The inlets and outlets are built by etching the surface of the optical fiber without damaging the inner core. A reaction region between the end of the fiber and a solid point obtained after melting is constructed. By injecting samples into the fiber, the liquids can form steady microflows and react in the region. Simultaneously, the emission from the chemiluminescence reaction can be detected from the remote end of the optical fiber through evanescent field coupling. The concentration of ascorbic acid (AA or vitamin C, Vc) is determined by the emission intensity of the reaction of Vc, H2O2, luminol, and K3Fe(CN)6 in the optical fiber. A linear sensing range of 0.1-3.0 mmol L(-1) for Vc is obtained. The emission intensity can be determined within 2 s at a total flow rate of 150 μL min(-1). Significantly, this work presents information for the in-fiber integrated optofluidic devices without spatial optical coupling.

VLSI Architecture and Design

OpenAIRE

Johnsson, Lennart

1980-01-01

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible....

SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation

Directory of Open Access Journals (Sweden)

Chi-Un Lei

2014-12-01

Full Text Available Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a “VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques” framework (known as SIM-DSP framework, which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole based DCT bases, and error can be analyzed through Parseval’s theorem. Practical examples are given to show the applicability of our proposed framework.

Towards transparent all-optical label-swapped networks: 40 Gbit/s ultra-fast dynamic wavelength routing using integrated devices

DEFF Research Database (Denmark)

Seoane, Jorge; Holm-Nielsen, Pablo Villanueva; Jeppesen, Palle

2006-01-01

All-optical routing of 40 Gbit/s 1.6 ns packets is demonstrated employing integrated devices based on SOA-MZIs. The scheme allows wavelength transparent operation and sub-nanosecond dynamic wavelength selection for future packet/label switched networks....

Photovoltaic device and method

Science.gov (United States)

Cleereman, Robert J; Lesniak, Michael J; Keenihan, James R; Langmaid, Joe A; Gaston, Ryan; Eurich, Gerald K; Boven, Michelle L

2015-01-27

The present invention is premised upon an improved photovoltaic device ("PVD") and method of use, more particularly to an improved photovoltaic device with an integral locator and electrical terminal mechanism for transferring current to or from the improved photovoltaic device and the use as a system.

Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity

International Nuclear Information System (INIS)

Kang, S.H.; Lee, K.

2013-01-01

A spintronic integrated circuit (IC) is made of a combination of a semiconductor IC and a dense array of nanometer-scale magnetic tunnel junctions. This emerging field is of growing scientific and engineering interest, owing to its potential to bring disruptive device innovation to the world of electronics. This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic). This paper reviews recent advances in spintronic IC. Key discoveries and breakthroughs in materials and devices are highlighted in light of the broader perspective of their application in low-energy mobile computing and connectivity systems, which have emerged as leading drivers for the prevailing electronics ecosystem

Definition of information technology architectures for continuous data management and medical device integration in diabetes.

Science.gov (United States)

Hernando, M Elena; Pascual, Mario; Salvador, Carlos H; García-Sáez, Gema; Rodríguez-Herrero, Agustín; Martínez-Sarriegui, Iñaki; Gómez, Enrique J

2008-09-01

The growing availability of continuous data from medical devices in diabetes management makes it crucial to define novel information technology architectures for efficient data storage, data transmission, and data visualization. The new paradigm of care demands the sharing of information in interoperable systems as the only way to support patient care in a continuum of care scenario. The technological platforms should support all the services required by the actors involved in the care process, located in different scenarios and managing diverse information for different purposes. This article presents basic criteria for defining flexible and adaptive architectures that are capable of interoperating with external systems, and integrating medical devices and decision support tools to extract all the relevant knowledge to support diabetes care.

An analysis of structure strength and ergonomic value of mechanical systems of integrated kidney and thyroid diagnosis device

International Nuclear Information System (INIS)

M-Awwaluddin Tri Hardjanto; Abdul Jalil

2016-01-01

The has been performed to ensure the security of the device, understand the patient's as well as operator problem and complaints, as part of the efforts to improve the performance of these devices. The analysis is done by calculating the strength of arm, the main frame chairs, and frame backrest patients, as well as analyzing the static anthropometry data for Indonesian man to determine the size of the dental chair and adjusting the size of the seat. We also use the dynamic anthropometry data for Indonesian man to determine the layout and range of movement of the operator while operating the integrated device The analysis showed that the structure is safe because the actual stress that occurs is still below the limit value of 248 MPa. The device also has good ergonomic value so that it can be bulk produced. (author)

Nanofabrication Technology for Production of Quantum Nano-Electronic Devices Integrating Niobium Electrodes and Optically Transparent Gates

Science.gov (United States)

2018-01-01

TECHNICAL REPORT 3086 January 2018 Nanofabrication Technology for Production of Quantum Nano-electronic Devices Integrating Niobium Electrodes...work described in this report was performed for the by the Advanced Concepts and Applied Research Branch (Code 71730) and the Science and Technology ...Applied Sciences Division iii EXECUTIVE SUMMARY This technical report demonstrates nanofabrication technology for Niobium heterostructures and

Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization

National Research Council Canada - National Science Library

Selvakkumaran, Navaratnasothie; Karypis, George

2004-01-01

... subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in VLSI CAD as they allow to both minimize and evenly distribute the interconnects across the physical devices...

Development of an Integrated Countermeasure Device for Long Duration Space Flight and Exploration Missions

Science.gov (United States)

Lee, S. M. C.; Streeper, T.; Spiering, B. A.; Loehr, J. A.; Guilliams, M. E.; Bloomberg, J. J.; Mulavara, A. P.; Cavanagh, P. R.; Lang, T.

2010-01-01

Musculoskeletal, cardiovascular, and sensorimotor deconditioning have been observed consistently in astronauts and cosmonauts following long-duration spaceflight. Studies in bed rest, a spaceflight analog, have shown that high intensity resistive or aerobic exercise attenuates or prevents musculoskeletal and cardiovascular deconditioning, respectively, but complete protection has not been achieved during spaceflight. Exercise countermeasure hardware used during earlier International Space Station (ISS) missions included a cycle ergometer, a treadmill, and the interim resistive exercise device (iRED). Effectiveness of the countermeasures may have been diminished by limited loading characteristics of the iRED as well as speed restrictions and subject harness discomfort during treadmill exercise. The Advanced Resistive Exercise Device (ARED) and the second generation treadmill were designed to address many of the limitations of their predecessors, and anecdotal reports from ISS crews suggest that their conditioning is better preserved since the new hardware was delivered in 2009. However, several countermeasure devices to protect different physiologic systems will not be practical during exploration missions when the available volume and mass will be severely restricted. The combined countermeasure device (CCD) integrates a suite of hardware into one device intended to prevent spaceflight-induced musculoskeletal, cardiovascular, and sensorimotor deconditioning. The CCD includes pneumatic loading devices with attached cables for resistive exercise, a cycle for aerobic exercise, and a 6 degree of freedom motion platform for balance training. In a proof of concept test, ambulatory untrained subjects increased muscle strength (58%) as well as aerobic capacity (26%) after 12-weeks of exercise training with the CCD (without balance training), improvements comparable to those observed with traditional exercise training. These preliminary results suggest that this CCD can

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

A Karaoke System with Real-Time Media Merging and Sharing Functions for a Cloud-Computing-Integrated Mobile Device

Directory of Open Access Journals (Sweden)

Her-Tyan Yeh

2013-01-01

Full Text Available Mobile devices such as personal digital assistants (PDAs, smartphones, and tablets have increased in popularity and are extremely efficient for work-related, social, and entertainment uses. Popular entertainment services have also attracted substantial attention. Thus, relevant industries have exerted considerable efforts in establishing a method by which mobile devices can be used to develop excellent and convenient entertainment services. Because cloud-computing technology is mature and possesses a strong computing processing capacity, integrating this technology into the entertainment service function in mobile devices can reduce the data load on a system and maintain mobile device performances. This study combines cloud computing with a mobile device to design a karaoke system that contains real-time media merging and sharing functions. This system enables users to download music videos (MVs from their mobile device and sing and record their singing by using the device. They can upload the recorded song to the cloud server where it is merged with real-time media. Subsequently, by employing a media streaming technology, users can store their personal MVs in their mobile device or computer and instantaneously share these videos with others on the Internet. Through this process, people can instantly watch shared videos, enjoy the leisure and entertainment effects of mobile devices, and satisfy their desire for singing.

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

Development of a real-world direct interface for integrated DNA extraction and amplification in a microfluidic device.

Science.gov (United States)

Shaw, Kirsty J; Joyce, Domino A; Docker, Peter T; Dyer, Charlotte E; Greenway, Gillian M; Greenman, John; Haswell, Stephen J

2011-02-07

Integrated DNA extraction and amplification have been carried out in a microfluidic device using electro-osmotic pumping (EOP) for fluidic control. All the necessary reagents for performing both DNA extraction and polymerase chain reaction (PCR) amplification were pre-loaded into the microfluidic device following encapsulation in agarose gel. Buccal cells were collected using OmniSwabs [Whatman™, UK] and manually added to a chaotropic binding/lysis solution pre-loaded into the microfluidic device. The released DNA was then adsorbed onto a silica monolith contained within the DNA extraction chamber and the microfluidic device sealed using polymer electrodes. The washing and elution steps for DNA extraction were carried out using EOP, resulting in transfer of the eluted DNA into the PCR chamber. Thermal cycling, achieved using a Peltier element, resulted in amplification of the Amelogenin locus as confirmed using conventional capillary gel electrophoresis. It was demonstrated that the PCR reagents could be stored in the microfluidic device for at least 8 weeks at 4 °C with no significant loss of activity. Such methodology lends itself to the production of 'ready-to-use' microfluidic devices containing all the necessary reagents for sample processing, with many obvious applications in forensics and clinical medicine.

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

Science.gov (United States)

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-06-17

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

Preclinical evaluation and intraoperative human retinal imaging with a high-resolution microscope-integrated spectral domain optical coherence tomography device.

Science.gov (United States)

Hahn, Paul; Migacz, Justin; O'Donnell, Rachelle; Day, Shelley; Lee, Annie; Lin, Phoebe; Vann, Robin; Kuo, Anthony; Fekrat, Sharon; Mruthyunjaya, Prithvi; Postel, Eric A; Izatt, Joseph A; Toth, Cynthia A

2013-01-01

The authors have recently developed a high-resolution microscope-integrated spectral domain optical coherence tomography (MIOCT) device designed to enable OCT acquisition simultaneous with surgical maneuvers. The purpose of this report is to describe translation of this device from preclinical testing into human intraoperative imaging. Before human imaging, surgical conditions were fully simulated for extensive preclinical MIOCT evaluation in a custom model eye system. Microscope-integrated spectral domain OCT images were then acquired in normal human volunteers and during vitreoretinal surgery in patients who consented to participate in a prospective institutional review board-approved study. Microscope-integrated spectral domain OCT images were obtained before and at pauses in surgical maneuvers and were compared based on predetermined diagnostic criteria to images obtained with a high-resolution spectral domain research handheld OCT system (HHOCT; Bioptigen, Inc) at the same time point. Cohorts of five consecutive patients were imaged. Successful end points were predefined, including ≥80% correlation in identification of pathology between MIOCT and HHOCT in ≥80% of the patients. Microscope-integrated spectral domain OCT was favorably evaluated by study surgeons and scrub nurses, all of whom responded that they would consider participating in human intraoperative imaging trials. The preclinical evaluation identified significant improvements that were made before MIOCT use during human surgery. The MIOCT transition into clinical human research was smooth. Microscope-integrated spectral domain OCT imaging in normal human volunteers demonstrated high resolution comparable to tabletop scanners. In the operating room, after an initial learning curve, surgeons successfully acquired human macular MIOCT images before and after surgical maneuvers. Microscope-integrated spectral domain OCT imaging confirmed preoperative diagnoses, such as full-thickness macular hole

A microfluidic device integrating plasmonic nanodevices for Raman spectroscopy analysis on trapped single living cells

KAUST Repository

Perozziello, Gerardo; Catalano, Rossella; Francardi, Marco; Rondanina, Eliana; Pardeo, Francesca; De Angelis, Francesco De; Malara, Natalia Maria; Candeloro, Patrizio; Morrone, Giovanni; Di Fabrizio, Enzo M.

2013-01-01

In this work we developed a microfluidic device integrating nanoplasmonic devices combined with fluidic trapping regions. The microfuidic traps allow to capture single cells in areas where plasmonic sensors are placed. In this way it is possible to perform Enhanced Raman analysis on the cell membranes. Moreover, by changing direction of the flux it is possible to change the orientation of the cell in the trap, so that it is possible to analyze different points of the membrane of the same cell. We shows an innovative procedure to fabricate and assembly the microfluidic device which combine photolithography, focused ion beam machining, and hybrid bonding between a polymer substrate and lid of Calcium fluoride. This procedure is compatible with the fabrication of the plasmonic sensors in close proximity of the microfluidic traps. Moreover, the use of Calcium fluoride as lid allows full compatibility with Raman measurements producing negligible Raman background signal and avoids Raman artifacts. Finally, we performed Raman analysis on cells to monitor their oxidative stress under particular non physiological conditions. © 2013 Elsevier B.V. All rights reserved.

A microfluidic device integrating plasmonic nanodevices for Raman spectroscopy analysis on trapped single living cells

KAUST Repository

Perozziello, Gerardo

2013-11-01

In this work we developed a microfluidic device integrating nanoplasmonic devices combined with fluidic trapping regions. The microfuidic traps allow to capture single cells in areas where plasmonic sensors are placed. In this way it is possible to perform Enhanced Raman analysis on the cell membranes. Moreover, by changing direction of the flux it is possible to change the orientation of the cell in the trap, so that it is possible to analyze different points of the membrane of the same cell. We shows an innovative procedure to fabricate and assembly the microfluidic device which combine photolithography, focused ion beam machining, and hybrid bonding between a polymer substrate and lid of Calcium fluoride. This procedure is compatible with the fabrication of the plasmonic sensors in close proximity of the microfluidic traps. Moreover, the use of Calcium fluoride as lid allows full compatibility with Raman measurements producing negligible Raman background signal and avoids Raman artifacts. Finally, we performed Raman analysis on cells to monitor their oxidative stress under particular non physiological conditions. © 2013 Elsevier B.V. All rights reserved.

78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

Science.gov (United States)

2013-02-14

...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR 210.8(b)).

Bridging ultrahigh-Q devices and photonic circuits

Science.gov (United States)

Yang, Ki Youl; Oh, Dong Yoon; Lee, Seung Hoon; Yang, Qi-Fan; Yi, Xu; Shen, Boqiang; Wang, Heming; Vahala, Kerry

2018-05-01

Optical microresonators are essential to a broad range of technologies and scientific disciplines. However, many of their applications rely on discrete devices to attain challenging combinations of ultra-low-loss performance (ultrahigh Q) and resonator design requirements. This prevents access to scalable fabrication methods for photonic integration and lithographic feature control. Indeed, finding a microfabrication bridge that connects ultrahigh-Q device functions with photonic circuits is a priority of the microcavity field. Here, an integrated resonator having a record Q factor over 200 million is presented. Its ultra-low-loss and flexible cavity design brings performance to integrated systems that has been the exclusive domain of discrete silica and crystalline microcavity devices. Two distinctly different devices are demonstrated: soliton sources with electronic repetition rates and high-coherence/low-threshold Brillouin lasers. This multi-device capability and performance from a single integrated cavity platform represents a critical advance for future photonic circuits and systems.

Power spectrum analysis for defect screening in integrated circuit devices

Science.gov (United States)

Tangyunyong, Paiboon; Cole Jr., Edward I.; Stein, David J.

2011-12-01

A device sample is screened for defects using its power spectrum in response to a dynamic stimulus. The device sample receives a time-varying electrical signal. The power spectrum of the device sample is measured at one of the pins of the device sample. A defect in the device sample can be identified based on results of comparing the power spectrum with one or more power spectra of the device that have a known defect status.

A one-semester course in modeling of VSLI interconnections

CERN Document Server

Goel, Ashok

2015-01-01

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

Microfluidics & nanotechnology: Towards fully integrated analytical devices for the detection of cancer biomarkers

KAUST Repository

Perozziello, Gerardo; Candeloro, Patrizio; Gentile, Francesco T.; Nicastri, Annalisa; Perri, Angela Mena; Coluccio, Maria Laura; Adamo, A.; Pardeo, Francesca; Catalano, Rossella; Parrotta, Elvira; Espinosa, Horacio Dante; Cuda, Giovanni; Di Fabrizio, Enzo M.

2014-01-01

In this paper, we describe an innovative modular microfluidic platform allowing filtering, concentration and analysis of peptides from a complex mixture. The platform is composed of a microfluidic filtering device and a superhydrophobic surface integrating surface enhanced Raman scattering (SERS) sensors. The microfluidic device was used to filter specific peptides (MW 1553.73 D) derived from the BRCA1 protein, a tumor-suppressor molecule which plays a pivotal role in the development of breast cancers, from albumin (66.5 KD), the most represented protein in human plasma. The filtering process consisted of driving the complex mixture through a porous membrane having a cut-off of 12-14 kD by hydrodynamic flow. The filtered samples coming out of the microfluidic device were subsequently deposited on a superhydrophobic surface formed by micro pillars on top of which nanograins were fabricated. The nanograins coupled to a Raman spectroscopy instrument acted as a SERS sensor and allowed analysis of the filtered sample on top of the surface once it evaporated. By using the presented platform, we demonstrate being able to sort small peptides from bigger proteins and to detect them by using a label-free technique at a resolution down to 0.1 ng μL-1. The combination of microfluidics and nanotechnology to develop the presented microfluidic platform may give rise to a new generation of biosensors capable of detecting low concentration samples from complex mixtures without the need for any sample pretreatment or labelling. The developed devices could have future applications in the field of early diagnosis of severe illnesses, e.g. early cancer detection. This journal is

Analogue and Mixed-Signal Integrated Circuits for Space Applications

CERN Document Server

2014-01-01

The purpose of AMICSA 2014 (organised in collaboration of ESA and CERN) is to provide an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

Integration of single oocyte trapping, in vitro fertilization and embryo culture in a microwell-structured microfluidic device.

Science.gov (United States)

Han, Chao; Zhang, Qiufang; Ma, Rui; Xie, Lan; Qiu, Tian; Wang, Lei; Mitchelson, Keith; Wang, Jundong; Huang, Guoliang; Qiao, Jie; Cheng, Jing

2010-11-07

In vitro fertilization (IVF) therapy is an important treatment for human infertility. However, the methods for clinical IVF have only changed slightly over decades: culture medium is held in oil-covered drops in Petri dishes and manipulation occurs by manual pipetting. Here we report a novel microwell-structured microfluidic device that integrates single oocyte trapping, fertilization and subsequent embryo culture. A microwell array was used to capture and hold individual oocytes during the flow-through process of oocyte and sperm loading, medium substitution and debris cleaning. Different microwell depths were compared by computational modeling and flow washing experiments for their effectiveness in oocyte trapping and debris removal. Fertilization was achieved in the microfluidic devices with similar fertilization rates to standard oil-covered drops in Petri dishes. Embryos could be cultured to blastocyst stages in our devices with developmental status individually monitored and tracked. The results suggest that the microfluidic device may bring several advantages to IVF practices by simplifying oocyte handling and manipulation, allowing rapid and convenient medium changing, and enabling automated tracking of any single embryo development.

Use of mobile devices in nursing student-nurse teacher cooperation during the clinical practicum: an integrative review.

Science.gov (United States)

Strandell-Laine, Camilla; Stolt, Minna; Leino-Kilpi, Helena; Saarikoski, Mikko

2015-03-01

To identify and appraise study findings on the use of mobile devices, in particular for what purposes and how, in nursing student-nurse teacher cooperation during the clinical practicum. A systematic literature search was conducted using the PubMed/Medline, CINAHL, PsycINFO and ERIC for primary empirical studies published in English. An integrative literature review was undertaken. Quality appraisal of the included studies was conducted using design-specific standardized checklists. Studies were thematically analyzed. Based on the inclusion and exclusion criteria, eleven studies were included in the review. Weaknesses in designs, samples, questionnaires and results, compromised comparison and/or generalization of the findings of the studies. Three main themes were identified: (1) features of mobile devices (2) utility of mobile devices and (3) barriers to the use of mobile devices. Problems of connectivity were the main challenges reported in the use of mobile devices. Participants used mobile devices primarily as reference tools, but less frequently as tools for reflection, assessment or cooperation during the clinical practicum. Interest in mobile device use during the clinical practicum was reported, but training and ongoing support are needed. As only a small number of eligible primary empirical studies were found, it is not possible to draw firm conclusions on the results. In the future, rigorous primary empirical studies are needed to explore the potential of mobile devices in providing a supplementary pedagogical method in nursing student-nurse teacher cooperation during the clinical practicum. Robust study designs, including experimental ones, are clearly needed to assess the effectiveness of mobile devices in nursing student-nurse teacher cooperation during the clinical practicum. Copyright © 2014 Elsevier Ltd. All rights reserved.

Effects of Thermal Resistance on One-Dimensional Thermal Analysis of the Epidermal Flexible Electronic Devices Integrated with Human Skin

Science.gov (United States)

Li, He; Cui, Yun

2017-12-01

Nowadays, flexible electronic devices are increasingly used in direct contact with human skin to monitor the real-time health of human body. Based on the Fourier heat conduction equation and Pennes bio-heat transfer equation, this paper deduces the analytical solutions of one - dimensional heat transfer for flexible electronic devices integrated with human skin under the condition of a constant power. The influence of contact thermal resistance between devices and skin is considered as well. The corresponding finite element model is established to verify the correctness of analytical solutions. The results show that the finite element analysis agrees well with the analytical solution. With bigger thermal resistance, temperature increase of skin surface will decrease. This result can provide guidance for the design of flexible electronic devices to reduce the negative impact that exceeding temperature leave on human skin.

Micro/Nano Fabricated Solid-State Thermoelectric Generator Devices for Integrated High Voltage Power Sources

Science.gov (United States)

Fleurial, J.-P.; Ryan, M. A.; Snyder, G. J.; Huang, C.-K.; Whitacre, J. F.; Patel, J.; Lim, J.; Borshchevsky, A.

2002-01-01

Deep space missions have a strong need for compact, high power density, reliable and long life electrical power generation and storage under extreme temperature conditions. Except for electrochemical batteries and solar cells, there are currently no available miniaturized power sources. Conventional power generators devices become inefficient in extreme environments (such as encountered in Mars, Venus or outer planet missions) and rechargeable energy storage devices can only be operated in a narrow temperature range thereby limiting mission duration. The planned development of much smaller spacecrafts incorporating a variety of micro/nanodevices and miniature vehicles will require novel, reliable power technologies. It is also expected that such micro power sources could have a wide range of terrestrial applications, in particular when the limited lifetime and environmental limitations of batteries are key factors. Advanced solid-state thermoelectric combined with radioisotope or waste heat sources and low profile energy storage devices are ideally suited for these applications. The Jet Propulsion Laboratory has been actively pursuing the development of thermoelectric micro/nanodevices that can be fabricated using a combination of electrochemical deposition and integrated circuit processing techniques. Some of the technical challenges associated with these micro/nanodevice concepts, their expected level of performance and experimental fabrication and testing results to date are presented and discussed.

Simulation of a spiking neuron circuit using carbon nanotube transistors

Energy Technology Data Exchange (ETDEWEB)

Najari, Montassar, E-mail: malnjar@jazanu.edu.sa [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); IKCE unit, Jazan University, Jazan (Saudi Arabia); El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); Jelliti, Sami, E-mail: sjelliti@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Hakami, Othman Mousa, E-mail: omhakami@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Faculty of Sciences, Jazan University, Jazan (Saudi Arabia)

2016-06-10

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

Simulation of a spiking neuron circuit using carbon nanotube transistors

International Nuclear Information System (INIS)

Najari, Montassar; El-Grour, Tarek; Jelliti, Sami; Hakami, Othman Mousa

2016-01-01

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

User centered integration of Internet of Things devices

Science.gov (United States)

Manione, Roberto

2017-06-01

This paper discusses an IoT framework which allows rapid and easy setup and customization of end-to-end solutions for field data collection and presentation; it is effective in the development of both informative and transactional applications for a wide range of application fields, such as home, industry and environment. On the "far-end" of the chain are the IoT devices gathering the signals; they are developed used a full Model Based approach, where programming is not required: the TaskScript technology is used to this purpose, which supports a choice of physical boards and boxes equipped with a range of Input and Output interfaces, and with a Tcp/Ip interface. The development of the needed specific IoT devices takes advantage of the available "standard" hardware; the software development of the algorithms for sampling, conditioning and uploading signals to the Cloud is supported by a graphical-only IDE. On the "near-end" of the chain is the presentation Interface, through which users can browse through the information provided by their IoT devices; it is implemented in a Conversational way, using the Bot paradigm: Bots are conversational automatons, to whom users can "chat". They are accessed via mainstream Messenger programs, such as Telegram(C), Skype(C) or others, available on smartphones, tablets or desktops; unlike apps, bots do not need installation on the user device. A message Broker has been implemented, to mediate among the far-end and the near-end of the chain, providing the needed services; its behavior is driven by a set of rules provided on a per-device basis, at configuration level; the Broker is able to store messages received from the devices, process and forward them to the specified recipient(s) according to the provided rules; finally, finally is it is able to send transactional commands, from users back to the requested device, to implement not only field observation but also field control. IoT solutions implemented with the proposed

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

Science.gov (United States)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

A Microfluidic Device with an Integrated Waveguide Beam Splitter for Velocity Measurements of Flowing Particles by Fourier Transformation

DEFF Research Database (Denmark)

Mogensen, Klaus Bo; Kwok, Y.C.; Eijkel, J.C.T.

2003-01-01

A microfabricated capillary electrophoresis device for velocity measurements of flowing particles is presented. It consists of a 1 x 128 planar waveguide beam splitter monolithically integrated with an electrically insulated fluidic channel network for fluorescence excitation at multiple points...... optics. The integrated planar waveguide beam splitter was, furthermore, permanently connected to the light source by a glued-on optical fiber, to achieve a robust and alignment-free operation of the system. The velocity was measured using a Fourier transformation with a Shah function, since the response...... of the fight array was designed to approximate a square profile. Deviations from this response were observed as a result of the multimode nature of the integrated waveguides....

Electrical Impedance Spectroscopy for Detection of Cells in Suspensions Using Microfluidic Device with Integrated Microneedles

Directory of Open Access Journals (Sweden)

Muhammad Asraf Mansor

2017-02-01

Full Text Available In this study, we introduce novel method of flow cytometry for cell detection based on impedance measurements. The state of the art method for impedance flow cytometry detection utilizes an embedded electrode in the microfluidic to perform measurement of electrical impedance of the presence of cells at the sensing area. Nonetheless, this method requires an expensive and complicated electrode fabrication process. Furthermore, reuse of the fabricated electrode also requires an intensive and tedious cleaning process. Due to that, we present a microfluidic device with integrated microneedles. The two microneedles are placed at the half height of the microchannel for cell detection and electrical measurement. A commercially-available Tungsten needle was utilized for the microneedles. The microneedles are easily removed from the disposable PDMS (Polydimethylsiloxane microchannel and can be reused with a simple cleaning process, such as washing by ultrasonic cleaning. Although this device was low cost, it preserves the core functionality of the sensor, which is capable of detecting passing cells at the sensing area. Therefore, this device is suitable for low-cost medical and food safety screening and testing process in developing countries.

Integration of gamma cameras and PET devices of multiple vendors in several locations

International Nuclear Information System (INIS)

Dresel, S.; Vollmar, C.; Sengupta, S.; Hahn, K.

2002-01-01

Full text: The Department of Nuclear Medicine of the University of Munich consists of four independently operated locations with a total of 18 gamma cameras (of three vendors), one PET scanner and one coincidence gamma camera. Recent hardware improvements, the installation and development of fast networks and new technologies for storage of large data volumes all contribute to the propagation of digital reading and reporting of nuclear medicine studies. Thus, the vision of a fully digitized nuclear medicine department becomes reality. In 1997 the department started with a strategy to fully integrate the entire number of imaging devices into one network for filmless reading, archiving and distributing nuclear medicine studies throughout the hospitals. The decision was made to use HERMES workstations (Nuclear Diagnostics, Sweden) to connect all primary imaging modalities. The purpose of the workstations located in the Nuclear Medicine departments is threefold: postprocessing, reading and archiving of all data. The workstations are networked throughout the different hospitals and are able to read the proprietary or DICOM data of the vendors of the gamma camera and PET equipment. The HERMES system is connected via DICOM interface to a long term storage device (AGFA, Germany). Additionally a JAVA (SUN Microsystems, USA) based software (JARVIS, Nuclear Diagnostics) is available to view all data from any computer using a web browser. Furthermore all data is linked to the hospital information system and selected imaging data are distributed throughout the hospitals. After commencement of full service of the network in 2000 the department is over 95 % filmfree. The high costs of purchasing hardware- and software-components are compensated for by saving costs of films and by the improvement of the work flow. Independently from these issues, filmless reporting proves to be advantageous over conventional film reading in many facts that justify to switch to a digital department

Microfluidic devices and methods for integrated flow cytometry

Science.gov (United States)

Srivastava, Nimisha [Goleta, CA; Singh, Anup K [Danville, CA

2011-08-16

Microfluidic devices and methods for flow cytometry are described. In described examples, various sample handling and preparation steps may be carried out within a same microfluidic device as flow cytometry steps. A combination of imaging and flow cytometry is described. In some examples, spiral microchannels serve as incubation chambers. Examples of automated sample handling and flow cytometry are described.

A Laboratory Experimental Study: An FBG-PVC Tube Integrated Device for Monitoring the Slip Surface of Landslides

Science.gov (United States)

Zhang, Shaojie; Chen, Jiang; Teng, Pengxiao; Wei, Fangqiang; Chen, Qiao

2017-01-01

A new detection device was designed by integrating fiber Bragg grating (FBG) and polyvinyl chloride (PVC) tube in order to monitor the slip surface of a landslide. Using this new FBG-based device, a corresponding slope model with a pre-set slip surface was designed, and seven tests with different soil properties were carried out in laboratory conditions. The FBG sensing fibers were fixed on the PVC tube to measure strain distributions of PVC tube at different elevation. Test results indicated that the PVC tube could keep deformation compatible with soil mass. The new device was able to monitor slip surface location before sliding occurrence, and the location of monitored slip surface was about 1–2 cm above the pre-set slip surface, which basically agreed with presupposition results. The monitoring results are expected to be used to pre-estimate landslide volume and provide a beneficial option for evaluating the potential impact of landslides on shipping safety in the Three Gorges area. PMID:29084157

Microfluidic chip-capillary electrophoresis devices

CERN Document Server

Fung, Ying Sing; Du, Fuying; Guo, Wenpeng; Ma, Tongmei; Nie, Zhou; Sun, Hui; Wu, Ruige; Zhao, Wenfeng

2015-01-01

Capillary electrophoresis (CE) and microfluidic chip (MC) devices are relatively mature technologies, but this book demonstrates how they can be integrated into a single, revolutionary device that can provide on-site analysis of samples when laboratory services are unavailable. By introducing the combination of CE and MC technology, Microfluidic Chip-Capillary Electrophoresis Devices broadens the scope of chemical analysis, particularly in the biomedical, food, and environmental sciences. The book gives an overview of the development of MC and CE technology as well as technology that now allows for the fabrication of MC-CE devices. It describes the operating principles that make integration possible and illustrates some achievements already made by the application of MC-CE devices in hospitals, clinics, food safety, and environmental research. The authors envision further applications for private and public use once the proof-of-concept stage has been passed and obstacles to increased commercialization are ad...

Speech Enhancement of Mobile Devices Based on the Integration of a Dual Microphone Array and a Background Noise Elimination Algorithm.

Science.gov (United States)

Chen, Yung-Yue

2018-05-08

Mobile devices are often used in our daily lives for the purposes of speech and communication. The speech quality of mobile devices is always degraded due to the environmental noises surrounding mobile device users. Regretfully, an effective background noise reduction solution cannot easily be developed for this speech enhancement problem. Due to these depicted reasons, a methodology is systematically proposed to eliminate the effects of background noises for the speech communication of mobile devices. This methodology integrates a dual microphone array with a background noise elimination algorithm. The proposed background noise elimination algorithm includes a whitening process, a speech modelling method and an H ₂ estimator. Due to the adoption of the dual microphone array, a low-cost design can be obtained for the speech enhancement of mobile devices. Practical tests have proven that this proposed method is immune to random background noises, and noiseless speech can be obtained after executing this denoise process.

Speech Enhancement of Mobile Devices Based on the Integration of a Dual Microphone Array and a Background Noise Elimination Algorithm

Directory of Open Access Journals (Sweden)

Yung-Yue Chen

2018-05-01

Full Text Available Mobile devices are often used in our daily lives for the purposes of speech and communication. The speech quality of mobile devices is always degraded due to the environmental noises surrounding mobile device users. Regretfully, an effective background noise reduction solution cannot easily be developed for this speech enhancement problem. Due to these depicted reasons, a methodology is systematically proposed to eliminate the effects of background noises for the speech communication of mobile devices. This methodology integrates a dual microphone array with a background noise elimination algorithm. The proposed background noise elimination algorithm includes a whitening process, a speech modelling method and an H2 estimator. Due to the adoption of the dual microphone array, a low-cost design can be obtained for the speech enhancement of mobile devices. Practical tests have proven that this proposed method is immune to random background noises, and noiseless speech can be obtained after executing this denoise process.

Fuel cell-powered microfluidic platform for lab-on-a-chip applications: Integration into an autonomous amperometric sensing device.

Science.gov (United States)

Esquivel, J P; Colomer-Farrarons, J; Castellarnau, M; Salleras, M; del Campo, F J; Samitier, J; Miribel-Català, P; Sabaté, N

2012-11-07

The present paper reports for the first time the integration of a microfluidic system, electronics modules, amperometric sensor and display, all powered by a single micro direct methanol fuel cell. In addition to activating the electronic circuitry, the integrated power source also acts as a tuneable micropump. The electronics fulfil several functions. First, they regulate the micro fuel cell output power, which off-gas controls the flow rate of different solutions toward an electrochemical sensor through microfluidic channels. Secondly, as the fuel cell powers a three-electrode electrochemical cell, the electronics compare the working electrode output signal with a set reference value. Thirdly, if the concentration measured by the sensor exceeds this threshold value, the electronics switch on an integrated organic display. This integrated approach pushes forward the development of truly autonomous point-of-care devices relying on electrochemical detection.

Wearable Fall Detector using Integrated Sensors and Energy Devices

OpenAIRE

Sungmook Jung; Seungki Hong; Jaemin Kim; Sangkyu Lee; Taeghwan Hyeon; Minbaek Lee; Dae-Hyeong Kim

2015-01-01

Wearable devices have attracted great attentions as next-generation electronic devices. For the comfortable, portable, and easy-to-use system platform in wearable electronics, a key requirement is to replace conventional bulky and rigid energy devices into thin and deformable ones accompanying the capability of long-term energy supply. Here, we demonstrate a wearable fall detection system composed of a wristband-type deformable triboelectric generator and lithium ion battery in conjunction wi...

Retrofits for Energy Efficient Office Buildings: Integration of Optimized Photovoltaics in the Form of Responsive Shading Devices

Directory of Open Access Journals (Sweden)

Hardi K. Abdullah

2017-11-01

Full Text Available This study presents a retrofit strategy: integrating optimized photovoltaics (PV in the form of responsive shading devices using a dual-axis solar tracking system. A prototype-based model was fabricated to compare the efficiency of PV in this implementation with the conventional fixed installation. The office building, T1 Empire World in Erbil, was selected as a retrofit case study and for the application of the proposed integration system. In order to assess the effectiveness of the proposed retrofit method, the energy performance of the base case is simulated to be compared later with the energy performance simulations after the integration technique. The amount of generated electricity from the PV surfaces of the integrated shading elements is calculated. The energy simulations were performed using OpenStudio® (NREL, Washington, DC, USA, EnergyPlusTM (NREL, Washington, DC, USA, and Grasshopper/ Ladybug tools in which the essential results were recorded for the baseline reference, as well as the energy performance of the retrofitted building. The results emphasize that the PV-integrated responsive shading devices can maximize the efficiency of PV cells by 36.8% in comparison to the fixed installation. The integrated system can provide approximately 15.39% of the electricity demand for operating the building. This retrofit method has reduced the total site energy consumption by 33.2% compared to the existing building performance. Total electricity end-use of the various utilities was lowered by 33.5%, and the total natural gas end-use of heating demand was reduced by 30.9%. Therefore, the percentage reduction in electricity cooling demand in July and August is 42.7% due to minimizing the heat gain in summer through blocking the sun’s harsh rays from penetrating into interior spaces of the building. In general, this system has multiple benefits, starting with being extremely efficient and viable in generating sustainable alternative energy�

Energy harvesting: an integrated view of materials, devices and applications

Science.gov (United States)

Radousky, H. B.; Liang, H.

2012-12-01

Energy harvesting refers to the set of processes by which useful energy is captured from waste, environmental, or mechanical sources and is converted into a usable form. The discipline of energy harvesting is a broad topic that includes established methods and materials such as photovoltaics and thermoelectrics, as well as more recent technologies that convert mechanical energy, magnetic energy and waste heat to electricity. This article will review various state-of-the-art materials and devices for direct energy conversion and in particular will include multistep energy conversion approaches. The article will highlight the nano-materials science underlying energy harvesting principles and devices, but also include more traditional bulk processes and devices as appropriate and synergistic. Emphasis is placed on device-design innovations that lead to higher efficiency energy harvesting or conversion technologies ranging from the cm/mm-scale down to MEMS/NEMS (micro- and nano-electromechanical systems) devices. Theoretical studies are reviewed, which address transport properties, crystal chemistry, thermodynamic analysis, energy transfer, system efficiency and device operation. New developments in experimental methods; device design and fabrication; nanostructured materials fabrication; materials properties; and device performance measurement techniques are discussed.

Heterostructures and quantum devices

CERN Document Server

Einspruch, Norman G

1994-01-01

Heterostructure and quantum-mechanical devices promise significant improvement in the performance of electronic and optoelectronic integrated circuits (ICs). Though these devices are the subject of a vigorous research effort, the current literature is often either highly technical or narrowly focused. This book presents heterostructure and quantum devices to the nonspecialist, especially electrical engineers working with high-performance semiconductor devices. It focuses on a broad base of technical applications using semiconductor physics theory to develop the next generation of electrical en

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

International Nuclear Information System (INIS)

Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

2014-01-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

Multilayer Integrated Film Bulk Acoustic Resonators

CERN Document Server

Zhang, Yafei

2013-01-01

Multilayer Integrated Film Bulk Acoustic Resonators mainly introduces the theory, design, fabrication technology and application of a recently developed new type of device, multilayer integrated film bulk acoustic resonators, at the micro and nano scale involving microelectronic devices, integrated circuits, optical devices, sensors and actuators, acoustic resonators, micro-nano manufacturing, multilayer integration, device theory and design principles, etc. These devices can work at very high frequencies by using the newly developed theory, design, and fabrication technology of nano and micro devices. Readers in fields of IC, electronic devices, sensors, materials, and films etc. will benefit from this book by learning the detailed fundamentals and potential applications of these advanced devices. Prof. Yafei Zhang is the director of the Ministry of Education’s Key Laboratory for Thin Films and Microfabrication Technology, PRC; Dr. Da Chen was a PhD student in Prof. Yafei Zhang’s research group.

Block QCA Fault-Tolerant Logic Gates

Science.gov (United States)

Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

2003-01-01

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA

An example of technological transfer to industry: the 'IMI' project

International Nuclear Information System (INIS)

Stefanini, A.; Amendolia, S.R.; Annovazzi, A.; Baldelli, P.; Bigongiari, A.; Bisogni, M.G.; Catarsi, F.; Cetronio, A.; Chianella, M.; Cinti, M.N.; Delogu, P.; Fantacci, M.E.; Galimberti, D.; Gambaccini, M.; Gilardoni, C.; Iurlaro, G.; Lanzieri, C.; Meoni, M.; Novelli, M.; Pani, R.; Passuello, G.; Pellegrini, R.; Pieracci, M.; Quattrocchi, M.; Rosso, V.; Venturelli, L.

2004-01-01

Several INFN Sections and Departments of Physics of Italian Universities have spent many man-years in the attempt to adapt detector and read-out technologies, originally developed in the field of High Energy Physics, to the domain of biomedical apparatuses. The research covered such areas as the exploitation of crystals for the production of monochromatic X-ray beams, the development of devices for efficient X-ray detection, the design of advanced VLSI electronics, the improvement of Position Sensitive Photomultiplier Tubes and crystals for Nuclear Medicine gamma-cameras. These studies have been integrated in the Integrated Mammographic Imaging (IMI) project, funded by the Italian Government through the law 46/82 (art.10) and is carried on by five high-technology industries in Italy, namely LABEN, CAEN, AMS, GILARDONI and POL.HI.TECH. We report on the status of this technological transfer project

An example of technological transfer to industry: the 'IMI' project

Energy Technology Data Exchange (ETDEWEB)

Stefanini, A.; Amendolia, S.R.; Annovazzi, A.; Baldelli, P.; Bigongiari, A.; Bisogni, M.G.; Catarsi, F.; Cetronio, A.; Chianella, M.; Cinti, M.N.; Delogu, P.; Fantacci, M.E.; Galimberti, D.; Gambaccini, M.; Gilardoni, C.; Iurlaro, G.; Lanzieri, C.; Meoni, M.; Novelli, M.; Pani, R.; Passuello, G.; Pellegrini, R.; Pieracci, M.; Quattrocchi, M.; Rosso, V. E-mail: valeria.rosso@pi.infn.it; Venturelli, L

2004-02-01

Several INFN Sections and Departments of Physics of Italian Universities have spent many man-years in the attempt to adapt detector and read-out technologies, originally developed in the field of High Energy Physics, to the domain of biomedical apparatuses. The research covered such areas as the exploitation of crystals for the production of monochromatic X-ray beams, the development of devices for efficient X-ray detection, the design of advanced VLSI electronics, the improvement of Position Sensitive Photomultiplier Tubes and crystals for Nuclear Medicine gamma-cameras. These studies have been integrated in the Integrated Mammographic Imaging (IMI) project, funded by the Italian Government through the law 46/82 (art.10) and is carried on by five high-technology industries in Italy, namely LABEN, CAEN, AMS, GILARDONI and POL.HI.TECH. We report on the status of this technological transfer project.

Integrated silicon optoelectronics

CERN Document Server

Zimmermann, Horst

2000-01-01

'Integrated Silicon Optoelectronics'assembles optoelectronics and microelectronics The book concentrates on silicon as the major basis of modern semiconductor devices and circuits Starting from the basics of optical emission and absorption and from the device physics of photodetectors, the aspects of the integration of photodetectors in modern bipolar, CMOS, and BiCMOS technologies are discussed Detailed descriptions of fabrication technologies and applications of optoelectronic integrated circuits are included The book, furthermore, contains a review of the state of research on eagerly expected silicon light emitters In order to cover the topic of the book comprehensively, integrated waveguides, gratings, and optoelectronic power devices are included in addition Numerous elaborate illustrations promote an easy comprehension 'Integrated Silicon Optoelectronics'will be of value to engineers, physicists, and scientists in industry and at universities The book is also recommendable for graduate students speciali...

Multifunctional Energy Storage and Conversion Devices.

Science.gov (United States)

Huang, Yan; Zhu, Minshen; Huang, Yang; Pei, Zengxia; Li, Hongfei; Wang, Zifeng; Xue, Qi; Zhi, Chunyi

2016-10-01

Multifunctional energy storage and conversion devices that incorporate novel features and functions in intelligent and interactive modes, represent a radical advance in consumer products, such as wearable electronics, healthcare devices, artificial intelligence, electric vehicles, smart household, and space satellites, etc. Here, smart energy devices are defined to be energy devices that are responsive to changes in configurational integrity, voltage, mechanical deformation, light, and temperature, called self-healability, electrochromism, shape memory, photodetection, and thermal responsivity. Advisable materials, device designs, and performances are crucial for the development of energy electronics endowed with these smart functions. Integrating these smart functions in energy storage and conversion devices gives rise to great challenges from the viewpoint of both understanding the fundamental mechanisms and practical implementation. Current state-of-art examples of these smart multifunctional energy devices, pertinent to materials, fabrication strategies, and performances, are highlighted. In addition, current challenges and potential solutions from materials synthesis to device performances are discussed. Finally, some important directions in this fast developing field are considered to further expand their application. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Signal Processing in Medical Ultrasound B-mode Imaging

International Nuclear Information System (INIS)

Song, Tai Kyong

2000-01-01

Ultrasonic imaging is the most widely used modality among modern imaging device for medical diagnosis and the system performance has been improved dramatically since early 90's due to the rapid advances in DSP performance and VLSI technology that made it possible to employ more sophisticated algorithms. This paper describes 'main stream' digital signal processing functions along with the associated implementation considerations in modern medical ultrasound imaging systems. Topics covered include signal processing methods for resolution improvement, ultrasound imaging system architectures, roles and necessity of the applications of DSP and VLSI technology in the development of the medical ultrasound imaging systems, and array signal processing techniques for ultrasound focusing

Integration of the GET electronics for the CHIMERA and FARCOS devices

Science.gov (United States)

De Filippo, E.; Acosta, L.; Auditore, L.; Boiano, C.; Cardella, G.; Castoldi, A.; D’Andrea, M.; De Luca, S.; Favela, F.; Fichera, F.; Giudice, N.; Gnoffo, B.; Grimaldi, A.; Guazzoni, C.; Lanzalone, G.; Librizzi, F.; Litrico, P.; Maiolino, C.; Maffesanti, S.; Martorana, NS; Pagano, A.; Pagano, EV; Papa, M.; Parsani, T.; Passaro, G.; Pirrone, S.; Politi, G.; Previdi, F.; Quattrocchi, L.; Rizzo, F.; Russotto, P.; Saccà, G.; Salemi, G.; Sciliberto, D.; Trifirò, A.; Trimarchi, M.

2018-05-01

A new front-end based on digital GET electronics has been adopted for the readout of the CsI(Tl) detectors of the CHIMERA 4π multi-detector and for the new modular Femtoscopy Array for Correlation and Spectroscopy (FARCOS). It is expected that the coupling of CHIMERA with the FARCOS array, featuring high angular and energy resolution, and the adoption of the new digital electronics will be well suited for improving specific future data analysis, with the full shape storage of the signals, in the field of heavy ion reactions with stable and exotic beams around the Fermi energies domain. Integration of the GET electronics with CHIMERA and FARCOS devices and with the local analog data acquisition will be briefly discussed. We present some results from previous experimental tests and from the first in-beam experiment (Hoyle-Gamma) with the coupled GET+CHIMERA data acquisition.

High voltage semiconductor devices and methods of making the devices

Energy Technology Data Exchange (ETDEWEB)

Matocha, Kevin; Chatty, Kiran; Banerjee, Sujit

2018-01-23

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

A Ubiquitous Sensor Network Platform for Integrating Smart Devices into the Semantic Sensor Web

Science.gov (United States)

de Vera, David Díaz Pardo; Izquierdo, Álvaro Sigüenza; Vercher, Jesús Bernat; Gómez, Luis Alfonso Hernández

2014-01-01

Ongoing Sensor Web developments make a growing amount of heterogeneous sensor data available to smart devices. This is generating an increasing demand for homogeneous mechanisms to access, publish and share real-world information. This paper discusses, first, an architectural solution based on Next Generation Networks: a pilot Telco Ubiquitous Sensor Network (USN) Platform that embeds several OGC® Sensor Web services. This platform has already been deployed in large scale projects. Second, the USN-Platform is extended to explore a first approach to Semantic Sensor Web principles and technologies, so that smart devices can access Sensor Web data, allowing them also to share richer (semantically interpreted) information. An experimental scenario is presented: a smart car that consumes and produces real-world information which is integrated into the Semantic Sensor Web through a Telco USN-Platform. Performance tests revealed that observation publishing times with our experimental system were well within limits compatible with the adequate operation of smart safety assistance systems in vehicles. On the other hand, response times for complex queries on large repositories may be inappropriate for rapid reaction needs. PMID:24945678

Helping To Integrate The Visually Challenged Into Mainstream Society Through A Low-Cost Braille Device

Directory of Open Access Journals (Sweden)

Desirée Jordan

2013-06-01

Full Text Available The visually challenged are often alienated from mainstream society because of their disabilities. This problem is even more pronounced in developing countries which often do not have the resources necessary to integrate this people group into their communities or even help them to become independent. It should therefore be the aim of governments in developing countries to provide this vulnerable people group with access to assistive technologies at a low cost. This paper describes an ongoing project that aims to provide low-cost assistive technologies to the visually challenged in Barbados. As a part of this project a study was conducted on a sample of visually challenged members of the Barbados Association for the Blind and Deaf to determine their ICT skills, knowledge of Braille and their use of assistive technologies. An analysis of the results prompted the design and creation of a low-cost Braille device prototype. The cost of this prototype was about one-half that of a commercially available device and can be used without a screen reader. This device should help create equal opportunities for the visually challenged in Barbados and other developing countries. It should also allow the visually challenged to become more independent.

SafeNet: a methodology for integrating general-purpose unsafe devices in safe-robot rehabilitation systems.

Science.gov (United States)

Vicentini, Federico; Pedrocchi, Nicola; Malosio, Matteo; Molinari Tosatti, Lorenzo

2014-09-01

Robot-assisted neurorehabilitation often involves networked systems of sensors ("sensory rooms") and powerful devices in physical interaction with weak users. Safety is unquestionably a primary concern. Some lightweight robot platforms and devices designed on purpose include safety properties using redundant sensors or intrinsic safety design (e.g. compliance and backdrivability, limited exchange of energy). Nonetheless, the entire "sensory room" shall be required to be fail-safe and safely monitored as a system at large. Yet, sensor capabilities and control algorithms used in functional therapies require, in general, frequent updates or re-configurations, making a safety-grade release of such devices hardly sustainable in cost-effectiveness and development time. As such, promising integrated platforms for human-in-the-loop therapies could not find clinical application and manufacturing support because of lacking in the maintenance of global fail-safe properties. Under the general context of cross-machinery safety standards, the paper presents a methodology called SafeNet for helping in extending the safety rate of Human Robot Interaction (HRI) systems using unsafe components, including sensors and controllers. SafeNet considers, in fact, the robotic system as a device at large and applies the principles of functional safety (as in ISO 13489-1) through a set of architectural procedures and implementation rules. The enabled capability of monitoring a network of unsafe devices through redundant computational nodes, allows the usage of any custom sensors and algorithms, usually planned and assembled at therapy planning-time rather than at platform design-time. A case study is presented with an actual implementation of the proposed methodology. A specific architectural solution is applied to an example of robot-assisted upper-limb rehabilitation with online motion tracking. Copyright © 2014 Elsevier Ireland Ltd. All rights reserved.

Gravitational field-flow fractionation integrated with chemiluminescence detection for a self-standing point-of-care compact device in bioanalysis.

Science.gov (United States)

Casolari, S; Roda, B; Mirasoli, M; Zangheri, M; Patrono, D; Reschiglian, P; Roda, A

2013-01-07

A "Point-Of-Care-Testing" (POCT) system relies on portable and simply operated self-standing analytical devices. To fulfill diagnostic requirements, the POCT system should provide highly sensitive simultaneous detection of several biomarkers of the pathology of interest (multiplexing) in a short assay time. One of the main unsolved issues in POCT device development is the integration of pre-analytical sample preparation procedures in the miniaturized device. In this work, an integrated POCT system based on gravitational field-flow fractionation (GrFFF) and chemiluminescence (CL) detection is presented for the on-line sample pre-analytical treatment and/or clean-up and analysis of biological fluids. As a proof of principle for the new GrFFF-CL POCT system, the automatic on-line analysis of plasma alkaline phosphatase activity, a biomarker of obstructive liver diseases and bone disorders, starting from whole blood samples was developed. The GrFFF-CL POCT system was able to give quantitative results on blood samples from control and patients with low sample volume (0.5 μL) and reagent consumption, short analysis time (10 minutes), high reproducibility and with a linear range of 50-1400 IU L(-1). The system can be easily applied to on-line prepare plasma from whole blood for other clinical biomarkers and for other assay formats, based on immunoassay or DNA hybridization.

Lie group model neuromorphic geometric engine for real-time terrain reconstruction from stereoscopic aerial photos

Science.gov (United States)

Tsao, Thomas R.; Tsao, Doris

1997-04-01

In the 1980's, neurobiologist suggested a simple mechanism in primate visual cortex for maintaining a stable and invariant representation of a moving object. The receptive field of visual neurons has real-time transforms in response to motion, to maintain a stable representation. When the visual stimulus is changed due to motion, the geometric transform of the stimulus triggers a dual transform of the receptive field. This dual transform in the receptive fields compensates geometric variation in the stimulus. This process can be modelled using a Lie group method. The massive array of affine parameter sensing circuits will function as a smart sensor tightly coupled to the passive imaging sensor (retina). Neural geometric engine is a neuromorphic computing device simulating our Lie group model of spatial perception of primate's primal visual cortex. We have developed the computer simulation and experimented on realistic and synthetic image data, and performed a preliminary research of using analog VLSI technology for implementation of the neural geometric engine. We have benchmark tested on DMA's terrain data with their result and have built an analog integrated circuit to verify the computational structure of the engine. When fully implemented on ANALOG VLSI chip, we will be able to accurately reconstruct a 3D terrain surface in real-time from stereoscopic imagery.

Total integrated dose testing of solid-state scientific CD4011, CD4013, and CD4060 devices by irradiation with CO-60 gamma rays

Science.gov (United States)

Dantas, A. R. V.; Gauthier, M. K.; Coss, J. R.

1985-01-01

The total integrated dose response of three CMOS devices manufactured by Solid State Scientific has been measured using CO-60 gamma rays. Key parameter measurements were made and compared for each device type. The data show that the CD4011, CD4013, and CD4060 produced by this manufacturers should not be used in any environments where radiation levels might exceed 1,000 rad(Si).

Feasibility study on an integrated AEC-grid device for the optimization of image quality and exposure dose in mammography

Science.gov (United States)

Kim, Kyo-Tae; Yun, Ryang-Young; Han, Moo-Jae; Heo, Ye-Ji; Song, Yong-Keun; Heo, Sung-Wook; Oh, Kyeong-Min; Park, Sung-Kwang

2017-10-01

Currently, in the radiation diagnosis field, mammography is used for the early detection of breast cancer. In addition, studies are being conducted on a grid to produce high-quality images. Although the grid ratio of the grid, which affects the scattering removal rate, must be increased to improve image quality, it increases the total exposure dose. While the use of automatic exposure control is recommended to minimize this problem, existing mammography equipment, unlike general radiography equipment, is mounted on the back of a detector. Therefore, the device is greatly affected by the detector and supporting device, and it is difficult to control the exposure dose. Accordingly, in this research, an integrated AEC-grid device that simultaneously performs AEC and grid functions was used to minimize the unnecessary exposure dose while removing scattering, thereby realizing superior image quality.

Bose, Prof. Dwarka Nath

Indian Academy of Sciences (India)

Dwarka Nath Ph.D. (Reading), FNASc. Date of birth: 15 June 1938. Specialization: Optoelectronics, Semiconductor Materials & Devices, VLSI Technology, Solar Photovoltaics Address: 7/2, Short Street, Kolkata 700 016, W.B.. Contact: Residence: (033) 2287 5679. Mobile: 98308 57849. Email: dwarkabose322@gmail.com.

FPGA-based multimodal embedded sensor system integrating low- and mid-level vision.

Science.gov (United States)

Botella, Guillermo; Martín H, José Antonio; Santos, Matilde; Meyer-Baese, Uwe

2011-01-01

Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

Directory of Open Access Journals (Sweden)

B. SENTHILKUMAR

2015-05-01

Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

Fractional-order devices

CERN Document Server

Biswas, Karabi; Caponetto, Riccardo; Mendes Lopes, António; Tenreiro Machado, José António

2017-01-01

This book focuses on two specific areas related to fractional order systems – the realization of physical devices characterized by non-integer order impedance, usually called fractional-order elements (FOEs); and the characterization of vegetable tissues via electrical impedance spectroscopy (EIS) – and provides readers with new tools for designing new types of integrated circuits. The majority of the book addresses FOEs. The interest in these topics is related to the need to produce “analogue” electronic devices characterized by non-integer order impedance, and to the characterization of natural phenomena, which are systems with memory or aftereffects and for which the fractional-order calculus tool is the ideal choice for analysis. FOEs represent the building blocks for designing and realizing analogue integrated electronic circuits, which the authors believe hold the potential for a wealth of mass-market applications. The freedom to choose either an integer- or non-integer-order analogue integrator...

Nanotube devices based crossbar architecture: toward neuromorphic computing

International Nuclear Information System (INIS)

Zhao, W S; Gamrat, C; Agnus, G; Derycke, V; Filoramo, A; Bourgoin, J-P

2010-01-01

Nanoscale devices such as carbon nanotube and nanowires based transistors, memristors and molecular devices are expected to play an important role in the development of new computing architectures. While their size represents a decisive advantage in terms of integration density, it also raises the critical question of how to efficiently address large numbers of densely integrated nanodevices without the need for complex multi-layer interconnection topologies similar to those used in CMOS technology. Two-terminal programmable devices in crossbar geometry seem particularly attractive, but suffer from severe addressing difficulties due to cross-talk, which implies complex programming procedures. Three-terminal devices can be easily addressed individually, but with limited gain in terms of interconnect integration. We show how optically gated carbon nanotube devices enable efficient individual addressing when arranged in a crossbar geometry with shared gate electrodes. This topology is particularly well suited for parallel programming or learning in the context of neuromorphic computing architectures.

All-integrated and highly sensitive paper based device with sample treatment platform for Cd2+ immunodetection in drinking/tap waters.

Science.gov (United States)

López Marzo, Adaris M; Pons, Josefina; Blake, Diane A; Merkoçi, Arben

2013-04-02

Nowadays, the development of systems, devices, or methods that integrate several process steps into one multifunctional step for clinical, environmental, or industrial purposes constitutes a challenge for many ongoing research projects. Here, we present a new integrated paper based cadmium (Cd(2+)) immunosensing system in lateral flow format, which integrates the sample treatment process with the analyte detection process. The principle of Cd(2+) detection is based on competitive reaction between the cadmium-ethylenediaminetetraacetic acid-bovine serum albumin-gold nanoparticles (Cd-EDTA-BSA-AuNP) conjugate deposited on the conjugation pad strip and the Cd-EDTA complex formed in the analysis sample for the same binding sites of the 2A81G5 monoclonal antibody (mAb), specific to Cd-EDTA but not Cd(2+) free, which is immobilized onto the test line. This platform operates without any sample pretreatment step for Cd(2+) detection thanks to an extra conjugation pad that ensures Cd(2+) complexation with EDTA and interference masking through ovalbumin (OVA). The detection and quantification limits found for the device were 0.1 and 0.4 ppb, respectively, these being the lowest limits reported up to now for metal sensors based on paper. The accuracy of the device was evaluated by addition of known quantities of Cd(2+) to different drinking water samples and subsequent Cd(2+) content analysis. Sample recoveries ranged from 95 to 105% and the coefficient of variation for the intermediate precision assay was less than 10%. In addition, the results obtained here were compared with those obtained with the well-established inductively coupled plasma emission spectroscopy (ICPES) and the analysis of certificate standard samples.

fast minimization on the xiao map using row group structure rules

African Journals Online (AJOL)

user

1989-09-01

Sep 1, 1989 ... insignificant thereby changing the focus of digital design from gate minimization to package or chip minmisation [1]. Gate level minimization still remains relevant despite the advent of large scale integrated circuit (LSI) and very large scale integrated circuit. (VLSI). For example, map entered variable.