Magneto-optical non-reciprocal devices in silicon photonics

Directory of Open Access Journals (Sweden)

Yuya Shoji

2014-01-01

Full Text Available Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm.

Silicon photonics fundamentals and devices

CERN Document Server

Deen, M Jamal

2012-01-01

The creation of affordable high speed optical communications using standard semiconductor manufacturing technology is a principal aim of silicon photonics research. This would involve replacing copper connections with optical fibres or waveguides, and electrons with photons. With applications such as telecommunications and information processing, light detection, spectroscopy, holography and robotics, silicon photonics has the potential to revolutionise electronic-only systems. Providing an overview of the physics, technology and device operation of photonic devices using exclusively silicon and related alloys, the book includes: * Basic Properties of Silicon * Quantum Wells, Wires, Dots and Superlattices * Absorption Processes in Semiconductors * Light Emitters in Silicon * Photodetectors , Photodiodes and Phototransistors * Raman Lasers including Raman Scattering * Guided Lightwaves * Planar Waveguide Devices * Fabrication Techniques and Material Systems Silicon Photonics: Fundamentals and Devices outlines ...

Photonic integration and photonics-electronics convergence on silicon platform

CERN Document Server

Liu, Jifeng; Baba, Toshihiko; Vivien, Laurent; Xu, Dan-Xia

2015-01-01

Silicon photonics technology, which has the DNA of silicon electronics technology, promises to provide a compact photonic integration platform with high integration density, mass-producibility, and excellent cost performance. This technology has been used to develop and to integrate various photonic functions on silicon substrate. Moreover, photonics-electronics convergence based on silicon substrate is now being pursued. Thanks to these features, silicon photonics will have the potential to be a superior technology used in the construction of energy-efficient cost-effective apparatuses for various applications, such as communications, information processing, and sensing. Considering the material characteristics of silicon and difficulties in microfabrication technology, however, silicon by itself is not necessarily an ideal material. For example, silicon is not suitable for light emitting devices because it is an indirect transition material. The resolution and dynamic range of silicon-based interference de...

Implantation damage in silicon devices

International Nuclear Information System (INIS)

Nicholas, K.H.

1977-01-01

Ion implantation, is an attractive technique for producing doped layers in silicon devices but the implantation process involves disruption of the lattice and defects are formed, which can degrade device properties. Methods of minimizing such damage are discussed and direct comparisons made between implantation and diffusion techniques in terms of defects in the final devices and the electrical performance of the devices. Defects are produced in the silicon lattice during implantation but they are annealed to form secondary defects even at room temperature. The annealing can be at a low temperature ( 0 C) when migration of defects in silicon in generally small, or at high temperature when they can grow well beyond the implanted region. The defect structures can be complicated by impurity atoms knocked into the silicon from surface layers by the implantation. Defects can also be produced within layers on top of the silicon and these can be very important in device fabrication. In addition to affecting the electrical properties of the final device, defects produced during fabrication may influence the chemical properties of the materials. The use of these properties to improve devices are discussed as well as the degradation they can cause. (author)

Mid-infrared integrated photonics on silicon: a perspective

Directory of Open Access Journals (Sweden)

Lin Hongtao

2017-12-01

Full Text Available The emergence of silicon photonics over the past two decades has established silicon as a preferred substrate platform for photonic integration. While most silicon-based photonic components have so far been realized in the near-infrared (near-IR telecommunication bands, the mid-infrared (mid-IR, 2–20-μm wavelength band presents a significant growth opportunity for integrated photonics. In this review, we offer our perspective on the burgeoning field of mid-IR integrated photonics on silicon. A comprehensive survey on the state-of-the-art of key photonic devices such as waveguides, light sources, modulators, and detectors is presented. Furthermore, on-chip spectroscopic chemical sensing is quantitatively analyzed as an example of mid-IR photonic system integration based on these basic building blocks, and the constituent component choices are discussed and contrasted in the context of system performance and integration technologies.

Athermal Photonic Devices and Circuits on a Silicon Platform

Science.gov (United States)

Raghunathan, Vivek

In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

Science.gov (United States)

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Single-Event Effects in Silicon and Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Hybrid Integrated Silicon Microfluidic Platform for Fluorescence Based Biodetection

Directory of Open Access Journals (Sweden)

André Darveau

2007-09-01

Full Text Available The desideratum to develop a fully integrated Lab-on-a-chip device capable ofrapid specimen detection for high throughput in-situ biomedical diagnoses and Point-of-Care testing applications has called for the integration of some of the novel technologiessuch as the microfluidics, microphotonics, immunoproteomics and Micro ElectroMechanical Systems (MEMS. In the present work, a silicon based microfluidic device hasbeen developed for carrying out fluorescence based immunoassay. By hybrid attachment ofthe microfluidic device with a Spectrometer-on-chip, the feasibility of synthesizing anintegrated Lab-on-a-chip type device for fluorescence based biosensing has beendemonstrated. Biodetection using the microfluidic device has been carried out usingantigen sheep IgG and Alexafluor-647 tagged antibody particles and the experimentalresults prove that silicon is a compatible material for the present application given thevarious advantages it offers such as cost-effectiveness, ease of bulk microfabrication,superior surface affinity to biomolecules, ease of disposability of the device etc., and is thussuitable for fabricating Lab-on-a-chip type devices.

Synthesis and properties of silicon nanowire devices

Science.gov (United States)

Byon, Kumhyo

Silicon nanowire (SiNW) is a very attractive one-dimensional material for future nanoelectronic applications. Reliable control of key field effect transistor (FET) parameters such as conductance, mobility, threshold voltage and on/off ratio is crucial to the applications of SiNW to working logic devices and integrated circuits. In this thesis, we fabricated silicon nanowire field effect transistors (SiNW FETs) and studied the dependence of their electrical transport properties upon various parameters including SiNW growth conditions, post-growth doping, and contact annealing. From these studies, we found how different processes control important FET characteristics. Key accomplishments of this thesis include p-channel enhancement mode FETs, n-channel FETs by post-growth vapor doping and high performance ambipolar devices. In the first part of this work, single crystalline SiNWs were synthesized by thermal evaporation without gold catalysts. FETs were fabricated using both as-grown SiNWs and post-growth n-doped SiNWs. FET from p-type source materials behaves as a p-channel enhancement mode FET which is predominant in logic devices due to its fast operation and low power consumption. Using bismuth vapor, the as-grown SiNWs were doped into n-type materials. The majority carriers in SiNWs can therefore be controlled by proper choice of the vapor phase dopant species. Post-growth doping using vapor phase is applicable to other nanowire systems. In the second part, high performance ambipolar FETs were fabricated. A two step annealing process was used to control the Schottky barrier between SiNW and metal contacts in order to enhance device performance. Initial p-channel SiNW FETs were converted into ambipolar SiNW FETs after contact annealing. Furthermore, significant increases in both on/off ratio and channel mobilities were achieved after contact annealing. Promising device structures to implement ambipolar devices into large scale integrated circuits were proposed

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics

Directory of Open Access Journals (Sweden)

Sandro Rao

2016-01-01

Full Text Available Hydrogenated amorphous silicon (a-Si:H shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34–40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

Cobalt micro-magnet integration on silicon MOS quantum dots

Science.gov (United States)

Camirand Lemyre, Julien; Rochette, Sophie; Anderson, John; Manginell, Ronald P.; Pluym, Tammy; Ward, Dan; Carroll, Malcom S.; Pioro-Ladrière, Michel

Integration of cobalt micro-magnets on silicon metal-oxide-semiconductor (MOS) quantum dot devices has been investigated. The micro-magnets are fabricated in a lift-off process with e-beam lithography and deposited directly on top of an etched poly-silicon gate stack. Among the five resist stacks tested, one is found to be compatible with our MOS specific materials (Si and SiO2) . Moreover, devices with and without additional Al2O3 insulating layer show no additional gate leakage after processing. Preliminary transport data indicates electrostatic stability of our devices with integrated magnets. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Neuron Stimulation Device Integrated with Silicon Nanowire-Based Photodetection Circuit on a Flexible Substrate

Directory of Open Access Journals (Sweden)

Suk Won Jung

2016-12-01

Full Text Available This paper proposes a neural stimulation device integrated with a silicon nanowire (SiNW-based photodetection circuit for the activation of neurons with light. The proposed device is comprised of a voltage divider and a current driver in which SiNWs are used as photodetector and field-effect transistors; it has the functions of detecting light, generating a stimulation signal in proportion to the light intensity, and transmitting the signal to a micro electrode. To show the applicability of the proposed neural stimulation device as a high-resolution retinal prosthesis system, a high-density neural stimulation device with a unit cell size of 110 × 110 μ m and a resolution of 32 × 32 was fabricated on a flexible film with a thickness of approximately 50 μm. Its effectiveness as a retinal stimulation device was then evaluated using a unit cell in an in vitro animal experiment involving the retinal tissue of retinal Degeneration 1 (rd1 mice. Experiments wherein stimulation pulses were applied to the retinal tissues successfully demonstrate that the number of spikes in neural response signals increases in proportion to light intensity.

System-level integration of active silicon photonic biosensors

Science.gov (United States)

Laplatine, L.; Al'Mrayat, O.; Luan, E.; Fang, C.; Rezaiezadeh, S.; Ratner, D. M.; Cheung, K.; Dattner, Y.; Chrostowski, L.

2017-02-01

Biosensors based on silicon photonic integrated circuits have attracted a growing interest in recent years. The use of sub-micron silicon waveguides to propagate near-infrared light allows for the drastic reduction of the optical system size, while increasing its complexity and sensitivity. Using silicon as the propagating medium also leverages the fabrication capabilities of CMOS foundries, which offer low-cost mass production. Researchers have deeply investigated photonic sensor devices, such as ring resonators, interferometers and photonic crystals, but the practical integration of silicon photonic biochips as part of a complete system has received less attention. Herein, we present a practical system-level architecture which can be employed to integrate the aforementioned photonic biosensors. We describe a system based on 1 mm2 dies that integrate germanium photodetectors and a single light coupling device. The die are embedded into a 16x16 mm2 epoxy package to enable microfluidic and electrical integration. First, we demonstrate a simple process to mimic Fan-Out Wafer-level-Packaging, which enables low-cost mass production. We then characterize the photodetectors in the photovoltaic mode, which exhibit high sensitivity at low optical power. Finally, we present a new grating coupler concept to relax the lateral alignment tolerance down to +/- 50 μm at 1-dB (80%) power penalty, which should permit non-experts to use the biochips in a"plug-and-play" style. The system-level integration demonstrated in this study paves the way towards the mass production of low-cost and highly sensitive biosensors, and can facilitate their wide adoption for biomedical and agro-environmental applications.

Integration of lateral porous silicon membranes into planar microfluidics.

Science.gov (United States)

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Neuron-inspired flexible memristive device on silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2017-06-18

Comprehensive understanding of the world\\'s most energy efficient powerful computer, the human brain, is an elusive scientific issue. Still, already gained knowledge indicates memristors can be used as a building block to model the brain. At the same time, brain cortex is folded allowing trillions of neurons to be integrated in a compact volume. Therefore, we report flexible aluminium oxide based memristive devices fabricated and then derived from widely used bulk mono-crystalline silicon (100). We use complementary metal oxide semiconductor based processes to layout the foundation for ultra large scale integration (ULSI) of such memory devices to advance the task of comprehending a physical model of human brain.

Silicon analog components device design, process integration, characterization, and reliability

CERN Document Server

El-Kareh, Badih

2015-01-01

This book covers modern analog components, their characteristics, and interactions with process parameters. It serves as a comprehensive guide, addressing both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. Based on the authors’ extensive experience in the development of analog devices, this book is intended for engineers and scientists in semiconductor research, development and manufacturing. The problems at the end of each chapter and the numerous charts, figures and tables also make it appropriate for use as a text in graduate and advanced undergraduate courses in electrical engineering and materials science.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

Science.gov (United States)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon.

Science.gov (United States)

Tokel, Onur; Turnali, Ahmet; Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F Ömer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e. , " in-chip" microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances.

Silicon solid state devices and radiation detection

CERN Document Server

Leroy, Claude

2012-01-01

This book addresses the fundamental principles of interaction between radiation and matter, the principles of working and the operation of particle detectors based on silicon solid state devices. It covers a broad scope with respect to the fields of application of radiation detectors based on silicon solid state devices from low to high energy physics experiments including in outer space and in the medical environment. This book covers stateof- the-art detection techniques in the use of radiation detectors based on silicon solid state devices and their readout electronics, including the latest developments on pixelated silicon radiation detector and their application.

Flexible integration of free-standing nanowires into silicon photonics.

Science.gov (United States)

Chen, Bigeng; Wu, Hao; Xin, Chenguang; Dai, Daoxin; Tong, Limin

2017-06-14

Silicon photonics has been developed successfully with a top-down fabrication technique to enable large-scale photonic integrated circuits with high reproducibility, but is limited intrinsically by the material capability for active or nonlinear applications. On the other hand, free-standing nanowires synthesized via a bottom-up growth present great material diversity and structural uniformity, but precisely assembling free-standing nanowires for on-demand photonic functionality remains a great challenge. Here we report hybrid integration of free-standing nanowires into silicon photonics with high flexibility by coupling free-standing nanowires onto target silicon waveguides that are simultaneously used for precise positioning. Coupling efficiency between a free-standing nanowire and a silicon waveguide is up to ~97% in the telecommunication band. A hybrid nonlinear-free-standing nanowires-silicon waveguides Mach-Zehnder interferometer and a racetrack resonator for significantly enhanced optical modulation are experimentally demonstrated, as well as hybrid active-free-standing nanowires-silicon waveguides circuits for light generation. These results suggest an alternative approach to flexible multifunctional on-chip nanophotonic devices.Precisely assembling free-standing nanowires for on-demand photonic functionality remains a challenge. Here, Chen et al. integrate free-standing nanowires into silicon waveguides and show all-optical modulation and light generation on silicon photonic chips.

Integration of mask and silicon metrology in DFM

Science.gov (United States)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based

David Adler Lectureship Award Talk: III-V Semiconductor Nanowires on Silicon for Future Devices

Science.gov (United States)

Riel, Heike

Bottom-up grown nanowires are very attractive materials for direct integration of III-V semiconductors on silicon thus opening up new possibilities for the design and fabrication of nanoscale devices for electronic, optoelectronic as well as quantum information applications. Template-Assisted Selective Epitaxy (TASE) allows the well-defined and monolithic integration of complex III-V nanostructures and devices on silicon. Achieving atomically abrupt heterointerfaces, high crystal quality and control of dimension down to 1D nanowires enabled the demonstration of FETs and tunnel devices based on In(Ga)As and GaSb. Furthermore, the strong influence of strain on nanowires as well as results on quantum transport studies of InAs nanowires with well-defined geometry will be presented.

Hybrid integration of carbon nanotubes in silicon photonic structures

Science.gov (United States)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

Medicine Delivery Device with Integrated Sterilization and Detection

Science.gov (United States)

Shearn, Michael J.; Greer, Harold F.; Manohara, Harish

2013-01-01

Sterile delivery devices can be created by integrating a medicine delivery instrument with surfaces that are coated with germicidal and anti-fouling material. This requires that a large-surface-area template be developed within a constrained volume to ensure good contact between the delivered medicine and the germicidal material. Both of these can be integrated using JPL-developed silicon nanotip or cryo-etch black silicon technologies with atomic layer deposition (ALD) coating of specific germicidal layers. The application of semiconductor processing techniques and technologies to the problems of fluid manipulation and delivery has enabled the integration of chemical, electrical, and mechanical manipulation of samples all within a single microfluidic device. This approach has been successfully applied at JPL to the automated processing, detection, and analysis of minute quantities (parts per trillion level) of biomaterials to develop instruments for in situ exploration or extraterrestrial bodies. The same nanofabrication techniques that are used to produce a microfluidics device are also capable of synthesizing extremely high-surface-area templates in precise locations, and coating those surfaces with conformal films to manipulate their surface properties. This methodology has been successfully applied at JPL to produce patterned and coated silicon nanotips (also known as black silicon) to manipulate the hydrophilicity of surfaces to direct the spreading of fluids in microdevices. JPL's ALD technique is an ideal method to produce the highly conformal coatings required for this type of application. Certain materials, such as TiO2, have germicidal and anti-fouling properties when they are illuminated with UV light. The proposed delivery device contacts medicine with this high-surface-area black silicon surface coated with a thin-film germicidal deposited conformally with ALD. The coating can also be illuminated with ultraviolet light for the purpose of sterilization

Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Movable MEMS Devices on Flexible Silicon

KAUST Repository

Ahmed, Sally

2013-05-05

Flexible electronics have gained great attention recently. Applications such as flexible displays, artificial skin and health monitoring devices are a few examples of this technology. Looking closely at the components of these devices, although MEMS actuators and sensors can play critical role to extend the application areas of flexible electronics, fabricating movable MEMS devices on flexible substrates is highly challenging. Therefore, this thesis reports a process for fabricating free standing and movable MEMS devices on flexible silicon substrates; MEMS flexure thermal actuators have been fabricated to illustrate the viability of the process. Flexure thermal actuators consist of two arms: a thin hot arm and a wide cold arm separated by a small air gap; the arms are anchored to the substrate from one end and connected to each other from the other end. The actuator design has been modified by adding etch holes in the anchors to suit the process of releasing a thin layer of silicon from the bulk silicon substrate. Selecting materials that are compatible with the release process was challenging. Moreover, difficulties were faced in the fabrication process development; for example, the structural layer of the devices was partially etched during silicon release although it was protected by aluminum oxide which is not attacked by the releasing gas . Furthermore, the thin arm of the thermal actuator was thinned during the fabrication process but optimizing the patterning and etching steps of the structural layer successfully solved this problem. Simulation was carried out to compare the performance of the original and the modified designs for the thermal actuators and to study stress and temperature distribution across a device. A fabricated thermal actuator with a 250 μm long hot arm and a 225 μm long cold arm separated by a 3 μm gap produced a deflection of 3 μm before silicon release, however, the fabrication process must be optimized to obtain fully functioning

Integration of functional complex oxide nanomaterials on silicon

Directory of Open Access Journals (Sweden)

Jose Manuel eVila-Fungueiriño

2015-06-01

Full Text Available The combination of standard wafer-scale semiconductor processing with the properties of functional oxides opens up to innovative and more efficient devices with high value applications that can be produced at large scale. This review uncovers the main strategies that are successfully used to monolithically integrate functional complex oxide thin films and nanostructures on silicon: the chemical solution deposition approach (CSD and the advanced physical vapor deposition techniques such as oxide molecular beam epitaxy (MBE. Special emphasis will be placed on complex oxide nanostructures epitaxially grown on silicon using the combination of CSD and MBE. Several examples will be exposed, with a particular stress on the control of interfaces and crystallization mechanisms on epitaxial perovskite oxide thin films, nanostructured quartz thin films, and octahedral molecular sieve nanowires. This review enlightens on the potential of complex oxide nanostructures and the combination of both chemical and physical elaboration techniques for novel oxide-based integrated devices.

Spike-Timing Dependent Plasticity in Unipolar Silicon Oxide RRAM Devices.

Science.gov (United States)

Zarudnyi, Konstantin; Mehonic, Adnan; Montesi, Luca; Buckwell, Mark; Hudziak, Stephen; Kenyon, Anthony J

2018-01-01

Resistance switching, or Resistive RAM (RRAM) devices show considerable potential for application in hardware spiking neural networks (neuro-inspired computing) by mimicking some of the behavior of biological synapses, and hence enabling non-von Neumann computer architectures. Spike-timing dependent plasticity (STDP) is one such behavior, and one example of several classes of plasticity that are being examined with the aim of finding suitable algorithms for application in many computing tasks such as coincidence detection, classification and image recognition. In previous work we have demonstrated that the neuromorphic capabilities of silicon-rich silicon oxide (SiO x ) resistance switching devices extend beyond plasticity to include thresholding, spiking, and integration. We previously demonstrated such behaviors in devices operated in the unipolar mode, opening up the question of whether we could add plasticity to the list of features exhibited by our devices. Here we demonstrate clear STDP in unipolar devices. Significantly, we show that the response of our devices is broadly similar to that of biological synapses. This work further reinforces the potential of simple two-terminal RRAM devices to mimic neuronal functionality in hardware spiking neural networks.

Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

International Nuclear Information System (INIS)

Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

2015-01-01

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

Porous silicon technology for integrated microsystems

Science.gov (United States)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

Mechanical engineering and design of silicon-based particle tracking devices

International Nuclear Information System (INIS)

Miller, W.O.; Thompson, T.C.; Gamble, M.T.; Reid, R.S.; Woloshun, K.A.; Dransfield, G.D.; Ziock, H.J.

1990-01-01

The Mechanical Engineering and Electronics Division of the Los Alamos National Laboratory has been investigating silicon-based particle tracking device technology as part of the Superconducting Super Collider-sponsored silicon subsystem collaboration. Structural, thermal, and materials issues have been addressed. This paper discussed detector structural integrity and stability, including detailed finite element models of the silicon chip support and predictive methods used in designing with advanced composite materials. Electronic thermal loading and efficient dissipation of such energy using heat pipe technology has been investigated. The use of materials whose coefficients of thermal expansion are engineered to match silicon or to be near zero, as appropriate, have been explored. Material analysis and test results from radiation, chemical, and static loading are compared with analytical predictions and discussed. 1 ref., 2 figs., 1 tab

Integrated Ultrasonic-Photonic Devices

DEFF Research Database (Denmark)

Barretto, Elaine Cristina Saraiva

in channel waveguides and Mach-Zehnder interferometers. Numerical models are developed based on the finite element method, and applied to several scenarios, such as optimization of the geometrical parameters of waveguides, use of slow light in photonic crystal waveguides and use of Lamb waves in membranized......This thesis deals with the modeling, design, fabrication and characterization of integrated ultrasonic-photonic devices, with particular focus on the use of standard semiconductor materials such as GaAs and silicon. The devices are based on the use of guided acoustic waves to modulate the light...... investigated. Comparisons are made with the numerical and experimental results, and they validate the obtained response of the acoustic and photonic components of the device. Finally, a new design for an optical frequency shifter is proposed, posing several advantages over existing devices in terms of size...

From silicon to organic nanoparticle memory devices.

Science.gov (United States)

Tsoukalas, D

2009-10-28

After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices

KAUST Repository

Li, Wenjie; Fu, Hui-chun; Li, Linsen; Cabá n-Acevedo, Miguel; He, Jr-Hau; Jin, Song

2016-01-01

photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly

Single-Event Effects in Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Nonlinear silicon photonics

Science.gov (United States)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2016-01-01

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Surface wave photonic device based on porous silicon multilayers

International Nuclear Information System (INIS)

Guillermain, E.; Lysenko, V.; Benyattou, T.

2006-01-01

Porous silicon is widely studied in the field of photonics due to its interesting optical properties. In this work, we present theoretical and first experimental studies of a new kind of porous silicon photonic device based on optical surface wave. A theoretical analysis of the device is presented using plane-wave approximation. The porous silicon multilayered structures are realized using electrochemical etching of p + -type silicon. Morphological and optical characterizations of the realized structures are reported

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices.

Science.gov (United States)

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F; Ross, Caroline A

2013-11-08

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO₂ -δ , Co- or Fe-substituted SrTiO 3- δ , as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti 0.2 Ga 0.4 Fe 0.4 )O 3- δ and polycrystalline (CeY₂)Fe₅O 12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY₂)Fe₅O 12 /silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

Science.gov (United States)

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Integrated nanophotonic frequency shifter on the silicon-organic hybrid (SOH) platform for laser vibrometry

International Nuclear Information System (INIS)

Lauermann, M.; Weimann, C.; Palmer, R.; Schindler, P. C.; Koeber, S.; Freude, W.; Koos, C.; Rembe, C.

2014-01-01

We demonstrate a waveguide-based frequency shifter on the silicon photonic platform, enabling frequency shifts up to 10 GHz. The device is realized by silicon-organic hybrid (SOH) integration. Temporal shaping of the drive signal allows the suppression of spurious side-modes by more than 23 dB

Integrated nanophotonic frequency shifter on the silicon-organic hybrid (SOH) platform for laser vibrometry

Energy Technology Data Exchange (ETDEWEB)

Lauermann, M.; Weimann, C.; Palmer, R.; Schindler, P. C. [Institute of Photonics and Quantum Electronics, Karlsruhe Institute of Technology, 76131 Karlsruhe (Germany); Koeber, S.; Freude, W., E-mail: christian.koos@kit.edu; Koos, C., E-mail: christian.koos@kit.edu [Institute of Photonics and Quantum Electronics, Karlsruhe Institute of Technology, 76131 Karlsruhe, Germany and Institute of Microstructure Technology, Karlsruhe Institute of Technology, 76344 Eggenstein-Leopoldshafen (Germany); Rembe, C. [Polytec GmbH, 76337 Waldbronn (Germany)

2014-05-27

We demonstrate a waveguide-based frequency shifter on the silicon photonic platform, enabling frequency shifts up to 10 GHz. The device is realized by silicon-organic hybrid (SOH) integration. Temporal shaping of the drive signal allows the suppression of spurious side-modes by more than 23 dB.

Porous silicon carbide (SIC) semiconductor device

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Silicon spintronics with ferromagnetic tunnel devices

International Nuclear Information System (INIS)

Jansen, R; Sharma, S; Dash, S P; Min, B C

2012-01-01

In silicon spintronics, the unique qualities of ferromagnetic materials are combined with those of silicon, aiming at creating an alternative, energy-efficient information technology in which digital data are represented by the orientation of the electron spin. Here we review the cornerstones of silicon spintronics, namely the creation, detection and manipulation of spin polarization in silicon. Ferromagnetic tunnel contacts are the key elements and provide a robust and viable approach to induce and probe spins in silicon, at room temperature. We describe the basic physics of spin tunneling into silicon, the spin-transport devices, the materials aspects and engineering of the magnetic tunnel contacts, and discuss important quantities such as the magnitude of the spin accumulation and the spin lifetime in the silicon. We highlight key experimental achievements and recent progress in the development of a spin-based information technology. (topical review)

Silicon hybrid integration

International Nuclear Information System (INIS)

Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

2011-01-01

Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

Optoelectronic Device Integration in Silicon (OpSIS)

Science.gov (United States)

2015-10-26

silicon-on-insulator," Opt. Express 22, 17872-17879 (2014) Y. Yang, C. Galland, Y. Liu, K. Tan , R. Ding, Q. Li, K. Bergman, T. Baehr-Jones, M...Jaeger, Nicolas AF; Chrostowski, Lukas; “Electrically tunable resonant filters in phase-shifted contra- directional couplers” IEEE Group IV Photonics... Nicolas AF; Chrostowski, Lukas; “Silicon photonic grating-assisted, contra-directional couplers” Optics express Vol. 21, No. 3; 3633-3650 (2013

Recent results from the development of silicon detectors with integrated electronics

Energy Technology Data Exchange (ETDEWEB)

Dalla Betta, G.-F. E-mail: dallabe@dit.unitn.it; Boscardin, M.; Batignani, G.; Bettarini, S.; Bisogni, M.G.; Bosisio, L.; Carpinelli, M.; Ciacchi, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Novelli, M.; Piemonte, C.; Rachevskaia, I.; Rama, M.; Ratti, L.; Re, V.; Ronchin, S.; Sandrelli, F.; Simi, G.; Speziali, V.; Rosso, V.; Traversi, G.; Zorzi, N

2004-02-01

In the past few years we have developed a technological process allowing for the fabrication of radiation detectors with integrated electronics on high-resistivity silicon substrates. We report on some recent results relevant to the process optimisation and to device/circuit characterization.

Recent results from the development of silicon detectors with integrated electronics

International Nuclear Information System (INIS)

Dalla Betta, G.-F.; Boscardin, M.; Batignani, G.; Bettarini, S.; Bisogni, M.G.; Bosisio, L.; Carpinelli, M.; Ciacchi, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Novelli, M.; Piemonte, C.; Rachevskaia, I.; Rama, M.; Ratti, L.; Re, V.; Ronchin, S.; Sandrelli, F.; Simi, G.; Speziali, V.; Rosso, V.; Traversi, G.; Zorzi, N.

2004-01-01

In the past few years we have developed a technological process allowing for the fabrication of radiation detectors with integrated electronics on high-resistivity silicon substrates. We report on some recent results relevant to the process optimisation and to device/circuit characterization

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

Directory of Open Access Journals (Sweden)

Mehmet Cengiz Onbasli

2013-11-01

Full Text Available Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4O3−δ and polycrystalline (CeY2Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Integrated multiscale modeling of molecular computing devices

International Nuclear Information System (INIS)

Cummings, Peter T; Leng Yongsheng

2005-01-01

Molecular electronics, in which single organic molecules are designed to perform the functions of transistors, diodes, switches and other circuit elements used in current siliconbased microelecronics, is drawing wide interest as a potential replacement technology for conventional silicon-based lithographically etched microelectronic devices. In addition to their nanoscopic scale, the additional advantage of molecular electronics devices compared to silicon-based lithographically etched devices is the promise of being able to produce them cheaply on an industrial scale using wet chemistry methods (i.e., self-assembly from solution). The design of molecular electronics devices, and the processes to make them on an industrial scale, will require a thorough theoretical understanding of the molecular and higher level processes involved. Hence, the development of modeling techniques for molecular electronics devices is a high priority from both a basic science point of view (to understand the experimental studies in this field) and from an applied nanotechnology (manufacturing) point of view. Modeling molecular electronics devices requires computational methods at all length scales - electronic structure methods for calculating electron transport through organic molecules bonded to inorganic surfaces, molecular simulation methods for determining the structure of self-assembled films of organic molecules on inorganic surfaces, mesoscale methods to understand and predict the formation of mesoscale patterns on surfaces (including interconnect architecture), and macroscopic scale methods (including finite element methods) for simulating the behavior of molecular electronic circuit elements in a larger integrated device. Here we describe a large Department of Energy project involving six universities and one national laboratory aimed at developing integrated multiscale methods for modeling molecular electronics devices. The project is funded equally by the Office of Basic

Ultrafast triggered transient energy storage by atomic layer deposition into porous silicon for integrated transient electronics

Science.gov (United States)

Douglas, Anna; Muralidharan, Nitin; Carter, Rachel; Share, Keith; Pint, Cary L.

2016-03-01

Here we demonstrate the first on-chip silicon-integrated rechargeable transient power source based on atomic layer deposition (ALD) coating of vanadium oxide (VOx) into porous silicon. A stable specific capacitance above 20 F g-1 is achieved until the device is triggered with alkaline solutions. Due to the rational design of the active VOx coating enabled by ALD, transience occurs through a rapid disabling step that occurs within seconds, followed by full dissolution of all active materials within 30 minutes of the initial trigger. This work demonstrates how engineered materials for energy storage can provide a basis for next-generation transient systems and highlights porous silicon as a versatile scaffold to integrate transient energy storage into transient electronics.Here we demonstrate the first on-chip silicon-integrated rechargeable transient power source based on atomic layer deposition (ALD) coating of vanadium oxide (VOx) into porous silicon. A stable specific capacitance above 20 F g-1 is achieved until the device is triggered with alkaline solutions. Due to the rational design of the active VOx coating enabled by ALD, transience occurs through a rapid disabling step that occurs within seconds, followed by full dissolution of all active materials within 30 minutes of the initial trigger. This work demonstrates how engineered materials for energy storage can provide a basis for next-generation transient systems and highlights porous silicon as a versatile scaffold to integrate transient energy storage into transient electronics. Electronic supplementary information (ESI) available: (i) Experimental details for ALD and material fabrication, ellipsometry film thickness, preparation of gel electrolyte and separator, details for electrochemical measurements, HRTEM image of VOx coated porous silicon, Raman spectroscopy for VOx as-deposited as well as annealed in air for 1 hour at 450 °C, SEM and transient behavior dissolution tests of uniformly coated VOx on

Emerging heterogeneous integrated photonic platforms on silicon

Directory of Open Access Journals (Sweden)

Fathpour Sasan

2015-05-01

Full Text Available Silicon photonics has been established as a mature and promising technology for optoelectronic integrated circuits, mostly based on the silicon-on-insulator (SOI waveguide platform. However, not all optical functionalities can be satisfactorily achieved merely based on silicon, in general, and on the SOI platform, in particular. Long-known shortcomings of silicon-based integrated photonics are optical absorption (in the telecommunication wavelengths and feasibility of electrically-injected lasers (at least at room temperature. More recently, high two-photon and free-carrier absorptions required at high optical intensities for third-order optical nonlinear effects, inherent lack of second-order optical nonlinearity, low extinction ratio of modulators based on the free-carrier plasma effect, and the loss of the buried oxide layer of the SOI waveguides at mid-infrared wavelengths have been recognized as other shortcomings. Accordingly, several novel waveguide platforms have been developing to address these shortcomings of the SOI platform. Most of these emerging platforms are based on heterogeneous integration of other material systems on silicon substrates, and in some cases silicon is integrated on other substrates. Germanium and its binary alloys with silicon, III–V compound semiconductors, silicon nitride, tantalum pentoxide and other high-index dielectric or glass materials, as well as lithium niobate are some of the materials heterogeneously integrated on silicon substrates. The materials are typically integrated by a variety of epitaxial growth, bonding, ion implantation and slicing, etch back, spin-on-glass or other techniques. These wide range of efforts are reviewed here holistically to stress that there is no pure silicon or even group IV photonics per se. Rather, the future of the field of integrated photonics appears to be one of heterogenization, where a variety of different materials and waveguide platforms will be used for

Nanophotonic integrated circuits from nanoresonators grown on silicon.

Science.gov (United States)

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Science.gov (United States)

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Electrical effects of transient neutron irradiation of silicon devices

International Nuclear Information System (INIS)

Hjalmarson, H.P.; Pease, R.L.; Van Ginhoven, R.M.; Schultz, P.A.; Modine, N.A.

2007-01-01

The key effects of combined transient neutron and ionizing radiation on silicon diodes and bipolar junctions transistors are described. The results show that interstitial defect reactions dominate the annealing effects in the first stage of annealing for certain devices. Furthermore, the results show that oxide trapped charge can influence the effects of bulk silicon displacement damage for particular devices

Micro-fabricated silicon devices for advanced thermal management and integration of particle tracking detectors

CERN Document Server

Romagnoli, Giulia; Gambaro, Carla

Since their first studies targeting the cooling of high-power computing chips, micro-channel devices are proven to provide a very efficient cooling system. In the last years micro-channel cooling has been successfully applied to the cooling of particle detectors at CERN. Thanks to their high thermal efficiency, they can guarantee a good heat sink for the cooling of silicon trackers, fundamental for the reduction of the radiation damage caused by the beam interactions. The radiation damage on the silicon detector is increasing with temperature and furthermore the detectors are producing heat that should be dissipated in the supporting structure. Micro-channels guarantee a distributed and uniform thermal exchange, thanks to the high flexibility of the micro-fabrication process that allows a large variety of channel designs. The thin nature of the micro-channels etched inside silicon wafers, is fulfilling the physics requirement of minimization of the material crossed by the particle beam. Furthermore micro-chan...

InP membrane on silicon integration technology

NARCIS (Netherlands)

Smit, M.K.

2013-01-01

Integration of light sources in silicon photonics is usually done with an active InP-based layer stack on a silicon-based photonic circuit-layer. InP Membrane On Silicon (IMOS) technology integrates all functionality in a single InP-based layer.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Hybrid graphene/silicon integrated optical isolators with photonic spin–orbit interaction

International Nuclear Information System (INIS)

Ma, Jingwen; Sun, Xiankai; Xi, Xiang; Yu, Zejie

2016-01-01

Optical isolators are an important building block in photonic computation and communication. In traditional optics, isolators are realized with magneto-optical garnets. However, it remains challenging to incorporate such materials on an integrated platform because of the difficulty in material growth and bulky device footprint. Here, we propose an ultracompact integrated isolator by exploiting graphene's magneto-optical property on a silicon-on-insulator platform. The photonic nonreciprocity is achieved because the cyclotrons in graphene experiencing different optical spins exhibit different responses to counterpropagating light. Taking advantage of cavity resonance effects, we have numerically optimized a device design, which shows excellent isolation performance with the extinction ratio over 45 dB and the insertion loss around 12 dB at a wavelength near 1.55 μm. Featuring graphene's CMOS compatibility and substantially reduced device footprint, our proposal sheds light on monolithic integration of nonreciprocal photonic devices.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

International Nuclear Information System (INIS)

Strobel, Sebastian; Hernandez, Rocio Murcia; Hansen, Allan G; Tornow, Marc

2008-01-01

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10 -18 farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian; Hernandez, Rocio Murcia [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall 3, 85748 Garching (Germany); Hansen, Allan G; Tornow, Marc [Institut fuer Halbleitertechnik, Technische Universitaet Braunschweig, Hans-Sommer-Strasse 66, 38106 Braunschweig (Germany)], E-mail: m.tornow@tu-bs.de

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10{sup -18} farad and asymmetric resistances of 30 and 300 M{omega}, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

Science.gov (United States)

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

The design and investigation of hybrid ferromagnetic/silicon spin electronic devices

International Nuclear Information System (INIS)

Pugh, D.I.

2001-01-01

The focus of this study concerns the design and investigation of ferromagnetic/silicon hybrid spin electronic devices as part of a wider project to design a novel spin valve transistor. The key issue to obtain a room temperature spin electronic device is the electrical injection of a spin polarised current from a ferromagnetic contact into a semiconductor. Despite many attempts concentrating on GaAs and InAs only small (< 1%) effects have been observed, making it difficult to confirm spin injection. Lateral devices were designed and fabricated using standard device fabrication procedures to produce arrays of Co/Si/So junctions. Subsequent designs aimed to reduce the number of junctions and improve device isolation. Evidence for spin dependent MR of up to 0.56% was observed in Co/p-Si/Co junctions with silicon gaps up to 16 μm in length. The maximum MR was observed when the first Co/Si Schottky barrier was reverse biased forming a high resistance interface. Vertical devices were designed in an attempt to eliminate any alternative current paths by using a well defined, 1 μm thick silicon membrane. Despite attempts to include oxide barriers, no spin dependent MR was observed in these devices. However, a novel vertical silicon based design has been made which should facilitate further advanced studies of spin injection and transport. The spin diffusion length in n-type silicon has been calculated as a function of doping concentration and temperature by considering the spin relaxation mechanisms in the semiconductor. Discussion has been made concerning p-type silicon and comparisons made with GaAs, indicating that n-Si should show longer spin diffusion lengths. The key design criteria for designing room temperature spin electronic devices have been highlighted. These include the use of a high leakage Schottky barrier or tunnel barrier between the ferromagnet and p-Si and a contact to the silicon to enable appropriate biasing to each FM/Si interface. (author)

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

Science.gov (United States)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

Science.gov (United States)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

Science.gov (United States)

Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

2013-07-29

We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

High-performance RF coil inductors on silicon

Energy Technology Data Exchange (ETDEWEB)

Malba, V.; Young, D.; Ou, J.J.; Bernhardt, A.F.; Boser, B.E.

1998-03-01

Strong demand for wireless communication devices has motivated research directed toward monolithic integration of transceivers. The fundamental electronic component least compatible with silicon integrated circuits is the inductor, although a number of inductors are required to implement oscillators, filters and matching networks in cellular devices. Spiral inductors have been integrated into the silicon IC metallization sequence but have not performed adequately due to coupling to the silicon which results in parasitic capacitance and loss. We have, for the first time, fabricated three dimensional coil inductors on silicon which have significantly lower capacitive coupling and loss and which now exceed the requirements of potential applications. Quality factors of 30 at 1 GHz have been measured in single turn devices and Q > 16 in 2 and 4 turn devices. The reduced Q for multiturn devices appears to be related to eddy currents in outer turns generated by magnetic fields from current in neighboring turns. Higher Q values significantly in excess of 30 are anticipated using modified coil designs.

A low cost and hybrid technology for integrating silicon sensors or actuators in polymer microfluidic systems

International Nuclear Information System (INIS)

Charlot, Samuel; Gué, Anne-Marie; Tasselli, Josiane; Marty, Antoine; Abgrall, Patrick; Estève, Daniel

2008-01-01

This paper describes a new technology permitting a hybrid integration of silicon chips in polymer (PDMS and SU8) microfluidic structures. This two-step technology starts with transferring the silicon device onto a rigid substrate (typically PCB) and planarizing it, and then it proceeds with stacking of the polymer-made fluidic network onto the device. The technology is low cost, based on screen printing and lamination, can be applied to treat large surface areas, and is compatible with standard photolithography and vacuum based approaches. We show, as an example, the integration of a thermal sensor inside channels made of PDMS or SU8. The developed structures had no fluid leaks at the Si/polymer interfaces and the electrical circuit was perfectly tightproof. (note)

Three-Dimensional Integration of Black Phosphorus Photodetector with Silicon Photonics and Nanoplasmonics.

Science.gov (United States)

Chen, Che; Youngblood, Nathan; Peng, Ruoming; Yoo, Daehan; Mohr, Daniel A; Johnson, Timothy W; Oh, Sang-Hyun; Li, Mo

2017-02-08

We demonstrate the integration of a black phosphorus photodetector in a hybrid, three-dimensional architecture of silicon photonics and metallic nanoplasmonics structures. This integration approach combines the advantages of the low propagation loss of silicon waveguides, high-field confinement of a plasmonic nanogap, and the narrow bandgap of black phosphorus to achieve high responsivity for detection of telecom-band, near-infrared light. Benefiting from an ultrashort channel (∼60 nm) and near-field enhancement enabled by the nanogap structure, the photodetector shows an intrinsic responsivity as high as 10 A/W afforded by internal gain mechanisms, and a 3 dB roll-off frequency of 150 MHz. This device demonstrates a promising approach for on-chip integration of three distinctive photonic systems, which, as a generic platform, may lead to future nanophotonic applications for biosensing, nonlinear optics, and optical signal processing.

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

A manufacturable process integration approach for graphene devices

Science.gov (United States)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

High-contrast gratings for long-wavelength laser integration on silicon

Science.gov (United States)

Sciancalepore, Corrado; Descos, Antoine; Bordel, Damien; Duprez, Hélène; Letartre, Xavier; Menezo, Sylvie; Ben Bakir, Badhise

2014-02-01

Silicon photonics is increasingly considered as the most promising way-out to the relentless growth of data traffic in today's telecommunications infrastructures, driving an increase in transmission rates and computing capabilities. This is in fact challenging the intrinsic limit of copper-based, short-reach interconnects and microelectronic circuits in data centers and server architectures to offer enough modulation bandwidth at reasonable power dissipation. In the context of the heterogeneous integration of III-V direct-bandgap materials on silicon, optics with high-contrast metastructures enables the efficient implementation of optical functions such as laser feedback, input/output (I/O) to active/passive components, and optical filtering, while heterogeneous integration of III-V layers provides sufficient optical gain, resulting in silicon-integrated laser sources. The latest ensure reduced packaging costs and reduced footprint for the optical transceivers, a key point for the short reach communications. The invited talk will introduce the audience to the latest breakthroughs concerning the use of high-contrast gratings (HCGs) for the integration of III-V-on-Si verticalcavity surface-emitting lasers (VCSELs) as well as Fabry-Perot edge-emitters (EELs) in the main telecom band around 1.55 μm. The strong near-field mode overlap within HCG mirrors can be exploited to implement unique optical functions such as dense wavelength division multiplexing (DWDM): a 16-λ100-GHz-spaced channels VCSEL array is demonstrated. On the other hand, high fabrication yields obtained via molecular wafer bonding of III-V alloys on silicon-on-insulator (SOI) conjugate excellent device performances with cost-effective high-throughput production, supporting industrial needs for a rapid research-to-market transfer.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

Silicon photonics fiber-to-the-home transceiver array based on transfer-printing-based integration of III-V photodetectors.

Science.gov (United States)

Zhang, Jing; De Groote, Andreas; Abbasi, Amin; Loi, Ruggero; O'Callaghan, James; Corbett, Brian; Trindade, António José; Bower, Christopher A; Roelkens, Gunther

2017-06-26

A 4-channel silicon photonics transceiver array for Point-to-Point (P2P) fiber-to-the-home (FTTH) optical networks at the central office (CO) side is demonstrated. A III-V O-band photodetector array was integrated onto the silicon photonic transmitter through transfer printing technology, showing a polarization-independent responsivity of 0.39 - 0.49 A/W in the O-band. The integrated PDs (30 × 40 μm 2 mesa) have a 3 dB bandwidth of 11.5 GHz at -3 V bias. Together with high-speed C-band silicon ring modulators whose bandwidth is up to 15 GHz, operation of the transceiver array at 10 Gbit/s is demonstrated. The use of transfer printing for the integration of the III-V photodetectors allows for an efficient use of III-V material and enables the scalable integration of III-V devices on silicon photonics wafers, thereby reducing their cost.

A hybrid approach to device integration on a genetic analysis platform

International Nuclear Information System (INIS)

Brennan, Des; Justice, John; Aherne, Margaret; Galvin, Paul; Jary, Dorothee; Kurg, Ants; Berik, Evgeny; Macek, Milan

2012-01-01

Point-of-care (POC) systems require significant component integration to implement biochemical protocols associated with molecular diagnostic assays. Hybrid platforms where discrete components are combined in a single platform are a suitable approach to integration, where combining multiple device fabrication steps on a single substrate is not possible due to incompatible or costly fabrication steps. We integrate three devices each with a specific system functionality: (i) a silicon electro-wetting-on-dielectric (EWOD) device to move and mix sample and reagent droplets in an oil phase, (ii) a polymer microfluidic chip containing channels and reservoirs and (iii) an aqueous phase glass microarray for fluorescence microarray hybridization detection. The EWOD device offers the possibility of fully integrating on-chip sample preparation using nanolitre sample and reagent volumes. A key challenge is sample transfer from the oil phase EWOD device to the aqueous phase microarray for hybridization detection. The EWOD device, waveguide performance and functionality are maintained during the integration process. An on-chip biochemical protocol for arrayed primer extension (APEX) was implemented for single nucleotide polymorphism (SNiP) analysis. The prepared sample is aspirated from the EWOD oil phase to the aqueous phase microarray for hybridization. A bench-top instrumentation system was also developed around the integrated platform to drive the EWOD electrodes, implement APEX sample heating and image the microarray after hybridization. (paper)

Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices

International Nuclear Information System (INIS)

Van de Wiel, H J; Galagan, Y; Van Lammeren, T J; De Riet, J F J; Gilot, J; Nagelkerke, M G M; Lelieveld, R H C A T; Shanmugam, S; Pagudala, A; Groen, W A; Hui, D

2013-01-01

Highly conductive screen printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) are a viable replacement for indium tin oxide (ITO) and inkjet printed silver as transparent electrode materials. To provide successful integration into organic photovoltaic (OPV) devices, screen printed silver current collecting grids should be embedded into a substrate to avoid topology issues. In this study micron-thick conductive structures are embedded and integrated into OPV devices. The embedded structures are produced roll-to-roll with optimized process settings and materials. Topology measurements show that the embedded grids are well suited for integration into OPV devices since the surface is almost without spikes and has low surface roughness. JV measurements of OPV devices with embedded structures on a polyethylene terephthalate/silicon nitride (PET/SiN) substrate show an efficiency of 2.15%, which is significantly higher than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). The use of embedded screen printed silver instead of ITO and inkjet printed silver in OPV devices will allow for higher efficiency devices which can be produced with larger design and process freedom. (paper)

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang

2014-01-01

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.

Self-consistent modeling of amorphous silicon devices

International Nuclear Information System (INIS)

Hack, M.

1987-01-01

The authors developed a computer model to describe the steady-state behaviour of a range of amorphous silicon devices. It is based on the complete set of transport equations and takes into account the important role played by the continuous distribution of localized states in the mobility gap of amorphous silicon. Using one set of parameters they have been able to self-consistently simulate the current-voltage characteristics of p-i-n (or n-i-p) solar cells under illumination, the dark behaviour of field-effect transistors, p-i-n diodes and n-i-n diodes in both the ohmic and space charge limited regimes. This model also describes the steady-state photoconductivity of amorphous silicon, in particular, its dependence on temperature, doping and illumination intensity

Process for forming a porous silicon member in a crystalline silicon member

Science.gov (United States)

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Strain-Induced Spin-Resonance Shifts in Silicon Devices

Science.gov (United States)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

Effects of radiation on MOS structures and silicon devices

International Nuclear Information System (INIS)

Braeunig, D.; Fahrner, W.

1983-02-01

A comprehensive view of radiation effects on MOS structures and silicon devices is given. In the introduction, the interaction of radiation with semiconductor material is presented. In the next section, the electrical degradation of semiconductor devices due to this interaction is discussed. The commonly used hardening techniques are shown. The last section deals with testing of radiation hardness of devices. (orig.) [de

Silicon wafers for integrated circuit process

OpenAIRE

Leroy , B.

1986-01-01

Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

Noise and degradation of amorphous silicon devices

NARCIS (Netherlands)

Bakker, J.P.R.

2003-01-01

Electrical noise measurements are reported on two devices of the disordered semiconductor hydrogenated amorphous silicon (a-Si:H). The material is applied in sandwich structures and in thin-film transistors (TFTs). In a sandwich configuration of an intrinsic layer and two thin doped layers, the

Long-wavelength III-V/silicon photonic integrated circuits

NARCIS (Netherlands)

Roelkens, G.C.; Kuyken, B.; Leo, F.; Hattasan, N.; Ryckeboer, E.M.P.; Muneeb, M.; Hu, C.L.; Malik, A.; Hens, Z.; Baets, R.G.F.; Shimura, Y.; Gencarelli, F.; Vincent, B.; Loo, van de R.; Verheyen, P.A.; Lepage, G.; Campenhout, van J.; Cerutti, L.; Rodriquez, J.B.; Tournie, E.; Chen, X; Nedeljkovic, G.; Mashanovich, G.; Liu, X.; Green, W.S.

2013-01-01

We review our work in the field of short-wave infrared and mid-infrared photonic integrated circuits for applications in spectroscopic sensing systems. Passive silicon waveguide circuits, GeSn photodetectors, the integration of III-V and IV-VI semiconductors on these circuits, and silicon nonlinear

Comparison of Six Different Silicones In Vitro for Application as Glaucoma Drainage Device

Directory of Open Access Journals (Sweden)

Claudia Windhövel

2018-02-01

Full Text Available Silicones are widely used in medical applications. In ophthalmology, glaucoma drainage devices are utilized if conservative therapies are not applicable or have failed. Long-term success of these devices is limited by failure to control intraocular pressure due to fibrous encapsulation. Therefore, different medical approved silicones were tested in vitro for cell adhesion, cell proliferation and viability of human Sclera (hSF and human Tenon fibroblasts (hTF. The silicones were analysed also depending on the sample preparation according to the manufacturer’s instructions. The surface quality was characterized with environmental scanning electron microscope (ESEM and water contact angle measurements. All silicones showed homogeneous smooth and hydrophobic surfaces. Cell adhesion was significantly reduced on all silicones compared to the negative control. Proliferation index and cell viability were not influenced much. For development of a new glaucoma drainage device, the silicones Silbione LSR 4330 and Silbione LSR 4350, in this study, with low cell counts for hTF and low proliferation indices for hSF, and silicone Silastic MDX4-4210, with low cell counts for hSF and low proliferation indices for hTF, have shown the best results in vitro. Due to the high cell adhesion shown on Silicone LSR 40, 40,026, this material is unsuitable.

Practical silicon Light emitting devices fabricated by standard IC technology

International Nuclear Information System (INIS)

Aharoni, H.; Monuko du Plessis; Snyman, L.W.

2004-01-01

Full Text:Research activities are described with regard to the development of a comprehensive approach for the practical realization of single crystal Silicon Light Emitting Devices (Si-LEDs). Several interesting suggestions for the fabrication of such devices were made in the literature but they were not adopted by the semiconductor industry because they involve non-standard fabrication schemes, requiring special production lines. Our work presents an alternative approach, proposed and realized in practice by us, permitting the fabrication of Si-LEDs using the standard conventional fully industrialized IC technology ''as is'' without any adaptation. It enables their fabrication in the same production lines of the presently existing IC industry. This means that Si-LEDs can now be fabricated simultaneously with other components, such as transistors, on the same silicon chip, using the same masks and processing procedures. The result is that the yield, reliability, and price of the above Si-LEDs are the same as the other Si devices integrated on the same chip. In this work some structural details of several practical Si-LED's designed by us, as well as experimental results describing their performance are presented. These Si-LED's were fabricated to our specifications utilizing standard CMOS/BiCMOS technology, a fact which comprises an achievement by itself. The structure of the Si-LED's, is designed according to specifications such as the required operating voltage, overall light output intensity, its dependence(linear, or non-linear) on the input signal (voltage or current), light generations location (bulk, or near-surface), the emission pattern and uniformity. Such structural design present a problem since the designer can not use any structural parameters (such as doping levels and junction depths for example) but only those which already exist in the production lines. Since the fabrication procedures in these lines are originally designed for processing of

Semiconductor Devices Inspired By and Integrated With Biology

Energy Technology Data Exchange (ETDEWEB)

Rogers, John [University of Illinois

2012-04-25

Biology is curved, soft and elastic; silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that adopt biologically inspired designs or require intimate integration with the human body. This talk describes the development of ideas for electronics that offer the performance of state-of-the-art, wafer- based systems but with the mechanical properties of a rubber band. We explain the underlying materials science and mechanics of these approaches, and illustrate their use in (1) bio- integrated, ‘tissue-like’ electronics with unique capabilities for mapping cardiac and neural electrophysiology, and (2) bio-inspired, ‘eyeball’ cameras with exceptional imaging properties enabled by curvilinear, Petzval designs.

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

Science.gov (United States)

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices

KAUST Repository

Li, Wenjie

2016-09-21

Building on regenerative photoelectrochemical solar cells and emerging electrochemical redox flow batteries (RFBs), more efficient, scalable, compact, and cost-effective hybrid energy conversion and storage devices could be realized. An integrated photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly charged by solar light without external bias, and discharged like normal RFBs with an energy storage density of 1.15 Wh L−1 and a solar-to-output electricity efficiency (SOEE) of 1.7 % over many cycles. The concept exploits a previously undeveloped design connecting two major energy technologies and promises a general approach for storing solar energy electrochemically with high theoretical storage capacity and efficiency.

An improved PIN photodetector with integrated JFET on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Piemonte, Claudio; Boscardin, Maurizio; Gregori, Paolo; Zorzi, Nicola; Fazzi, Alberto; Pignatel, Giorgio U.

2006-01-01

We report on a PIN photodetector integrated with a Junction Field Effect Transistor (JFET) on a high-resistivity silicon substrate. Owing to a modified fabrication technology, the electrical and noise characteristics of the JFET transistor have been enhanced with respect to the previous versions of the device, allowing the performance to be significantly improved. In this paper, the main design and technological aspects relevant to the proposed structure are addressed and experimental results from the electrical characterization are discussed

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

Science.gov (United States)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier

Amorphous silicon rich silicon nitride optical waveguides for high density integrated optics

DEFF Research Database (Denmark)

Philipp, Hugh T.; Andersen, Karin Nordström; Svendsen, Winnie Edith

2004-01-01

Amorphous silicon rich silicon nitride optical waveguides clad in silica are presented as a high-index contrast platform for high density integrated optics. Performance of different cross-sectional geometries have been measured and are presented with regards to bending loss and insertion loss...

Performance of integrated retainer rings in silicon micro-turbines with thrust style micro-ball bearings

International Nuclear Information System (INIS)

Hergert, Robert J; Holmes, Andrew S; Hanrahan, Brendan; Ghodssi, Reza

2013-01-01

This work explores the performance of different silicon retainer ring designs when integrated into silicon micro-turbines (SMTs) incorporating thrust style bearings supported on 500 µm diameter steel balls. Experimental performance curves are presented for SMTs with rotor diameters of 5 mm and 10 mm, each with five different retainer designs varying in mechanical rigidity, ball pocket shape and ball complement. It was found that the different retainer designs yielded different performance curves, with the closed pocket designs consistently requiring lower input power for a given rotation speed, and the most rigid retainers giving the best performance overall. Both 5 mm and 10 mm diameter devices have shown repeatable performance at rotation speeds up to and exceeding 20 000 RPM with input power levels below 2 W, and devices were tested for over 2.5 million revolutions without failure. Retainer rings are commonly used in macro-scale bearings to ensure uniform spacing between the rolling elements. The integration of retainers into micro-bearings could lower costs by reducing the number of balls required for stable operation, and also open up the possibility of ‘smart’ bearings with integrated sensors to monitor the bearing status. (paper)

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Science.gov (United States)

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Fabrication and optical characterization of light trapping silicon nanopore and nanoscrew devices

International Nuclear Information System (INIS)

Jin, Hyunjong; Logan Liu, G

2012-01-01

We have fabricated nanotextured Si substrates that exhibit controllable optical reflection intensities and colors. Si nanopore has a photon trapping nanostructure but has abrupt changes in the index of refraction displaying a darkened specular reflection. Nanoscrew Si shows graded refractive-index photon trapping structures that enable diffuse reflection to be as low as 2.2% over the visible wavelengths. By tuning the 3D nanoscale silicon structure, the optical reflection peak wavelength and intensity are changed in the wavelength range of 300–800 nm, making the surface have different reflectivity and apparent colors. The relation between the surface optical properties with the spatial features of the photon trapping nanostructures is examined. Integration of photon trapping structures with planar Si structure on the same substrate is also demonstrated. The tunable photon trapping silicon structures have potential applications in enhancing the performance of semiconductor photoelectric devices. (paper)

Plasmonic nanofocusing of light in an integrated silicon photonics platform.

Science.gov (United States)

Desiatov, Boris; Goykhman, Ilya; Levy, Uriel

2011-07-04

The capability to focus electromagnetic energy at the nanoscale plays an important role in nanoscinece and nanotechnology. It allows enhancing light matter interactions at the nanoscale with applications related to nonlinear optics, light emission and light detection. It may also be used for enhancing resolution in microscopy, lithography and optical storage systems. Hereby we propose and experimentally demonstrate the nanoscale focusing of surface plasmons by constructing an integrated plasmonic/photonic on chip nanofocusing device in silicon platform. The device was tested directly by measuring the optical intensity along it using a near-field microscope. We found an order of magnitude enhancement of the intensity at the tip's apex. The spot size is estimated to be 50 nm. The demonstrated device may be used as a building block for "lab on a chip" systems and for enhancing light matter interactions at the apex of the tip.

Integrated Photoelectrochemical Solar Energy Conversion and Organic Redox Flow Battery Devices.

Science.gov (United States)

Li, Wenjie; Fu, Hui-Chun; Li, Linsen; Cabán-Acevedo, Miguel; He, Jr-Hau; Jin, Song

2016-10-10

Building on regenerative photoelectrochemical solar cells and emerging electrochemical redox flow batteries (RFBs), more efficient, scalable, compact, and cost-effective hybrid energy conversion and storage devices could be realized. An integrated photoelectrochemical solar energy conversion and electrochemical storage device is developed by integrating regenerative silicon solar cells and 9,10-anthraquinone-2,7-disulfonic acid (AQDS)/1,2-benzoquinone-3,5-disulfonic acid (BQDS) RFBs. The device can be directly charged by solar light without external bias, and discharged like normal RFBs with an energy storage density of 1.15 Wh L -1 and a solar-to-output electricity efficiency (SOEE) of 1.7 % over many cycles. The concept exploits a previously undeveloped design connecting two major energy technologies and promises a general approach for storing solar energy electrochemically with high theoretical storage capacity and efficiency. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonlinear Silicon Photonic Signal Processing Devices for Future Optical Networks

Directory of Open Access Journals (Sweden)

Cosimo Lacava

2017-01-01

Full Text Available In this paper, we present a review on silicon-based nonlinear devices for all optical nonlinear processing of complex telecommunication signals. We discuss some recent developments achieved by our research group, through extensive collaborations with academic partners across Europe, on optical signal processing using silicon-germanium and amorphous silicon based waveguides as well as novel materials such as silicon rich silicon nitride and tantalum pentoxide. We review the performance of four wave mixing wavelength conversion applied on complex signals such as Differential Phase Shift Keying (DPSK, Quadrature Phase Shift Keying (QPSK, 16-Quadrature Amplitude Modulation (QAM and 64-QAM that dramatically enhance the telecom signal spectral efficiency, paving the way to next generation terabit all-optical networks.

Localized synthesis, assembly and integration of silicon nanowires

Science.gov (United States)

Englander, Ongi

Localized synthesis, assembly and integration of one-dimensional silicon nanowires with MEMS structures is demonstrated and characterized in terms of local synthesis processes, electric-field assisted self-assembly, and a proof-of-concept nanoelectromechanical system (HEMS) demonstration. Emphasis is placed on the ease of integration, process control strategies, characterization techniques and the pursuit of integrated devices. A top-down followed by a bottom-up integration approach is utilized. Simple MEMS heater structures are utilized as the microscale platforms for the localized, bottom-up synthesis of one-dimensional nanostructures. Localized heating confines the high temperature region permitting only localized nanostructure synthesis and allowing the surroundings to remain at room temperature thus enabling CMOS compatible post-processing. The vapor-liquid-solid (VLS) process in the presence of a catalytic nanoparticle, a vapor phase reactant, and a specific temperature environment is successfully employed locally. Experimentally, a 5nm thick gold-palladium layer is used as the catalyst while silane is the vapor phase reactant. The current-voltage behavior of the MEMS structures can be correlated to the approximate temperature range required for the VLS reaction to take place. Silicon nanowires averaging 45nm in diameter and up to 29mum in length synthesized at growth rates of up to 1.5mum/min result. By placing two MEMS structures in close proximity, 4--10mum apart, localized silicon nanowire growth can be used to link together MEMS structures to yield a two-terminal, self-assembled micro-to-nano system. Here, one MEMS structure is designated as the hot growth structure while a nearby structure is designated as the cold secondary structure, whose role is to provide a natural stopping point for the VLS reaction. The application of a localized electric-field, 5 to 13V/mum in strength, during the synthesis process, has been shown to improve nanowire

Integrated double-sided silicon microstrip detectors

Directory of Open Access Journals (Sweden)

Perevertailo V. L.

2011-11-01

Full Text Available The problems of design, technology and manufacturing double-sided silicon microstrip detectors using standard equipment production line in mass production of silicon integrated circuits are considered. The design of prototype high-energy particles detector for experiment ALICE (CERN is presented. The parameters of fabricated detectors are comparable with those of similar foreign detectors, but they are distinguished by lesser cost.

High-efficiency power transfer for silicon-based photonic devices

Science.gov (United States)

Son, Gyeongho; Yu, Kyoungsik

2018-02-01

We demonstrate an efficient coupling of guided light of 1550 nm from a standard single-mode optical fiber to a silicon waveguide using the finite-difference time-domain method and propose a fabrication method of tapered optical fibers for efficient power transfer to silicon-based photonic integrated circuits. Adiabatically-varying fiber core diameters with a small tapering angle can be obtained using the tube etching method with hydrofluoric acid and standard single-mode fibers covered by plastic jackets. The optical power transmission of the fundamental HE11 and TE-like modes between the fiber tapers and the inversely-tapered silicon waveguides was calculated with the finite-difference time-domain method to be more than 99% at a wavelength of 1550 nm. The proposed method for adiabatic fiber tapering can be applied in quantum optics, silicon-based photonic integrated circuits, and nanophotonics. Furthermore, efficient coupling within the telecommunication C-band is a promising approach for quantum networks in the future.

Materials issues in silicon integrated circuit processing

International Nuclear Information System (INIS)

Wittmer, M.; Stimmell, J.; Strathman, M.

1986-01-01

The symposium on ''Materials Issues in Integrated Circuit Processing'' sought to bring together all of the materials issued pertinent to modern integrated circuit processing. The inherent properties of the materials are becoming an important concern in integrated circuit manufacturing and accordingly research in materials science is vital for the successful implementation of modern integrated circuit technology. The session on Silicon Materials Science revealed the advanced stage of knowledge which topics such as point defects, intrinsic and extrinsic gettering and diffusion kinetics have achieved. Adaption of this knowledge to specific integrated circuit processing technologies is beginning to be addressed. The session on Epitaxy included invited papers on epitaxial insulators and IR detectors. Heteroepitaxy on silicon is receiving great attention and the results presented in this session suggest that 3-d integrated structures are an increasingly realistic possibility. Progress in low temperature silicon epitaxy and epitaxy of thin films with abrupt interfaces was also reported. Diffusion and Ion Implantation were well presented. Regrowth of implant-damaged layers and the nature of the defects which remain after regrowth were discussed in no less than seven papers. Substantial progress was also reported in the understanding of amorphising boron implants and the use of gallium implants for the formation of shallow p/sup +/ -layers

Silicon Photonics: All-Optical Devices for Linear and Nonlinear Applications

Science.gov (United States)

Driscoll, Jeffrey B.

Silicon photonics has grown rapidly since the first Si electro-optic switch was demonstrated in 1987, and the field has never grown more quickly than it has over the past decade, fueled by milestone achievements in semiconductor processing technologies for low loss waveguides, high-speed Si modulators, Si lasers, Si detectors, and an enormous toolbox of passive and active integrated devices. Silicon photonics is now on the verge of major commercialization breakthroughs, and optical communication links remain the force driving integrated and Si photonics towards the first commercial telecom and datacom transceivers; however other potential and future applications are becoming uncovered and refined as researchers reveal the benefits of manipulating photons on the nanoscale. This thesis documents an exploration into the unique guided-wave and nonlinear properties of deeply-scaled high-index-contrast sub-wavelength Si waveguides. It is found that the tight confinement inherent to single-mode channel waveguides on the silicon-on-insulator platform lead to a rich physics, which can be leveraged for new devices extending well beyond simple passive interconnects and electro-optic devices. The following chapters will concentrate, in detail, on a number of unique physical features of Si waveguides and extend these attributes towards new and interesting devices. Linear optical properties and nonlinear optical properties are investigated, both of which are strongly affected by tight optical confinement of the guided waveguide modes. As will be shown, tight optical confinement directly results in strongly vectoral modal components, where the electric and magnetic fields of the guided modes extend into all spatial dimensions, even along the axis of propagation. In fact, the longitudinal electric and magnetic field components can be just as strong as the transverse fields, directly affecting the modal group velocity and energy transport properties since the longitudinal fields

Monolithic integration of optical waveguides for absorbance detection in microfabricated electrophoresis devices

DEFF Research Database (Denmark)

Mogensen, Klaus Bo; Petersen, Nickolaj Jacob; Hübner, Jörg

2001-01-01

. The waveguides on the device were connected to optical fibers, which enabled alignment free operation due to the absence of free-space optics. A 750 mum long U-shaped detection cell was used to facilitate longitudinal absorption detection. To minimize geometrically induced band broadening at the turn in the U......The fabrication and performance of an electrophoretic separation chip with integrated of optical waveguides for absorption detection is presented. The device was fabricated on a silicon substrate by standard microfabrication techniques with the use of two photolithographic mask steps...

Proton irradiation effects in silicon devices

Energy Technology Data Exchange (ETDEWEB)

Simoen, E; Vanhellemont, J; Alaerts, A [IMEC, Leuven (Belgium); and others

1997-03-01

Proton irradiation effects in silicon devices are studied for components fabricated in various substrates in order to reveal possible hardening effects. The degradation of p-n junction diodes increases in first order proportionally with the fluence, when submitted to 10 MeV proton irradiations in the range 5x10{sup 9} cm{sup -2} to 5x10{sup 11} cm{sup -2}. The damage coefficients for both p- and n-type Czochralski, Float-Zone and epitaxial wafers are reported. Charge-Coupled Devices fabricated in a 1.2 {mu}m CCD-CMOS technology are shown to be quite resistant to 59 MeV H{sup +} irradiations, irrespective of the substrate type. (author)

Defects in silicon effect on device performance and relationship to crystal growth conditions

Science.gov (United States)

Jastrzebski, L.

1985-01-01

A relationship between material defects in silicon and the performance of electronic devices will be described. A role which oxygen and carbon in silicon play during the defects generation process will be discussed. The electronic properties of silicon are a strong function of the oxygen state in the silicon. This state controls mechanical properties of silicon efficiency for internal gettering and formation of defects in the device's active area. In addition, to temperature, time, ambience, and the cooling/heating rates of high temperature treatments, the oxygen state is a function of the crystal growth process. The incorporation of carbon and oxygen into silicon crystal is controlled by geometry and rotation rates applied to crystal and crucible during crystal growths. Also, formation of nucleation centers for oxygen precipitation is influenced by the growth process, although there is still a controversy which parameters play a major role. All these factors will be reviewed with special emphasis on areas which are still ambiguous and controversial.

Solid state MEMS devices on flexible and semi-transparent silicon (100) platform

KAUST Repository

Ahmed, Sally; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2014-01-01

We report fabrication of MEMS thermal actuators on flexible and semi-transparent silicon fabric released from bulk silicon (100). We fabricated the devices first and then released the top portion of the silicon (≈ 19 μm) which is flexible and semi-transparent. We also performed chemical mechanical polishing to reuse the remaining wafer. A tested thermal actuator with 3 μm wide 240 μm hot arm and 10 μm wide 185 μm long cold arm deflected by 1.7 μm at 1 V. The fabricated thermal actuators exhibit similar performance before and after bending. We believe the demonstrated process will expand the horizon of flexible electronics into MEMS world devices. © 2014 IEEE.

The first results of siliconization on SWIP-RFP device

International Nuclear Information System (INIS)

Zhang Peng; Li Qiang; Luo Cuiwen; Li Jieping; Qian Shangjie; Fang Shuiquan; Yi Ping; Xue Jun; Li Kehua; Luo Junlin; Hong Wenyu; Cao Zeng; Zhang Nianman; Wang Quanming; Li Jie; Huang Ming; Zhong Yunze; Zhang Qingchun; Luo Cuixian

1997-01-01

The first results of reversed field pinch (RFP) and ultra low safety factor (ULQ) plasma experiments with siliconization on SWIP-RFP device are presented in this paper. The siliconization decreases the impurity concentrations in the plasma and increases the configuration sustainment time. Ion temperature has been estimated with the CV line of the visible light spectra and the broadening of CIII lines in vacuum ultraviolet (VUV) region. The anomalous ion heating as well as the anomalous resistance were observed. (orig.)

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Science.gov (United States)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Periodically poled silicon

Science.gov (United States)

Hon, Nick K.; Tsia, Kevin K.; Solli, Daniel R.; Khurgin, Jacob B.; Jalali, Bahram

2010-02-01

Bulk centrosymmetric silicon lacks second-order optical nonlinearity χ(2) - a foundational component of nonlinear optics. Here, we propose a new class of photonic device which enables χ(2) as well as quasi-phase matching based on periodic stress fields in silicon - periodically-poled silicon (PePSi). This concept adds the periodic poling capability to silicon photonics, and allows the excellent crystal quality and advanced manufacturing capabilities of silicon to be harnessed for devices based on χ(2)) effects. The concept can also be simply achieved by having periodic arrangement of stressed thin films along a silicon waveguide. As an example of the utility, we present simulations showing that mid-wave infrared radiation can be efficiently generated through difference frequency generation from near-infrared with a conversion efficiency of 50% based on χ(2) values measurements for strained silicon reported in the literature [Jacobson et al. Nature 441, 199 (2006)]. The use of PePSi for frequency conversion can also be extended to terahertz generation. With integrated piezoelectric material, dynamically control of χ(2)nonlinearity in PePSi waveguide may also be achieved. The successful realization of PePSi based devices depends on the strength of the stress induced χ(2) in silicon. Presently, there exists a significant discrepancy in the literature between the theoretical and experimentally measured values. We present a simple theoretical model that produces result consistent with prior theoretical works and use this model to identify possible reasons for this discrepancy.

Synthesis of silicon nanocomposite for printable photovoltaic devices on flexible substrate

Science.gov (United States)

Odo, E. A.; Faremi, A. A.

2017-06-01

Renewed interest has been established in the preparation of silicon nanoparticles for electronic device applications. In this work, we report on the production of silicon powders using a simple ball mill and of silicon nanocomposite ink for screen-printable photovoltaic device on a flexible substrate. Bulk single crystalline silicon was milled for 25 h in the ball mill. The structural properties of the produced silicon nanoparticles were investigated using X-ray diffraction (XRD) and transmission electron microscopy. The results show that the particles remained highly crystalline, though transformed from their original single crystalline state to polycrystalline. The elemental composition using energy dispersive X-ray florescence spectroscopy (EDXRF) revealed that contamination from iron (Fe) and chromium (Cr) of the milling media and oxygen from the atmosphere were insignificant. The size distribution of the nanoparticles follows a lognormal pattern that ranges from 60 nm to about 1.2 μm and a mean particle size of about 103 nm. Electrical characterization of screen-printed PN structures of the nanocomposite formed by embedding the powder into a suitable water-soluble polymer on Kapton sheet reveals an enhanced photocurrent transport resulting from photo-induced carrier generation in the depletion region with energy greater that the Schottky barrier height at the metal-composite interface.

Analysis of silicon-based integrated photovoltaic-electrochemical hydrogen generation system under varying temperature and illumination

Institute of Scientific and Technical Information of China (English)

Vishwa Bhatt; Brijesh Tripathi; Pankaj Yadav; Manoj Kumar

2017-01-01

Last decade witnessed tremendous research and development in the area of photo-electrolytic hydrogen generation using chemically stable nanostructured photo-cathode/anode materials.Due to intimately coupled charge separation and photo-catalytic processes,it is very difficult to optimize individual components of such system leading to a very low demonstrated solar-to-fuel efficiency (SFE) of less than 1％.Recently there has been growing interest in an integrated photovoltaic-electrochemical (PV-EC) system based on GaAs solar cells with the demonstrated SFE of 24.5％ under concentrated illumination condition.But a high cost of GaAs based solar cells and recent price drop of poly-crystalline silicon (pc-Si) solar cells motivated researchers to explore silicon based integrated PV-EC system.In this paper a theoretical framework is introduced to model silicon-based integrated PV-EC device.The theoretical framework is used to analyze the coupling and kinetic losses of a silicon solar cell based integrated PV-EC water splitting system under varying temperature and illumination.The kinetic loss occurs in the range of 19.1％-27.9％ and coupling loss takes place in the range of 5.45％-6.74％ with respect to varying illumination in the range of 20-100 mW/cm2.Similarly,the effect of varying temperature has severe impact on the performance of the system,wherein the coupling loss occurs in the range of 0.84％-21.51％ for the temperature variation from 25 to 50 ℃.

Towards neuromorphic electronics: Memristors on foldable silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-11-01

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex\\'s folded pattern for ultra-compact design.

Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

Directory of Open Access Journals (Sweden)

Kuen-Hsien Wu

2015-09-01

Full Text Available Porous-silicon (PS multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells.

Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

DEFF Research Database (Denmark)

Li, Helong; Munk-Nielsen, Stig; Wang, Xiongfei

2016-01-01

This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influ......This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then......, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance...... of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed...

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem

2016-09-26

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem; Seif, Johannes Peter; Riesen, Yannick; Tomasi, Andrea; Jeangros, Quentin; Wyrsch, Nicolas; Haug, Franz-Josef; De Wolf, Stefaan; Ballif, Christophe

2016-01-01

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Directory of Open Access Journals (Sweden)

Zahra Bisadi

2018-02-01

Full Text Available A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Silicon Photonics II Components and Integration

CERN Document Server

Lockwood, David J

2011-01-01

This book is volume II of a series of books on silicon photonics. It gives a fascinating picture of the state-of-the-art in silicon photonics from a component perspective. It presents a perspective on what can be expected in the near future. It is formed from a selected number of reviews authored by world leaders in the field, and is written from both academic and industrial viewpoints. An in-depth discussion of the route towards fully integrated silicon photonics is presented. This book will be useful not only to physicists, chemists, materials scientists, and engineers but also to graduate students who are interested in the fields of micro- and nanophotonics and optoelectronics.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

Energy Technology Data Exchange (ETDEWEB)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan [Photovoltaics and Thin-Film Electronics Laboratory, Institute of Microengineering (IMT), Ecole Polytechnique Fédérale de Lausanne (EPFL), Rue de la Maladière 71b, CH-2002 Neuchâtel (Switzerland); Menda, Deneb; Özdemir, Orhan [Department of Physics, Yıldız Technical University, Davutpasa Campus, TR-34210 Esenler, Istanbul (Turkey); Descoeudres, Antoine; Barraud, Loris [CSEM, PV-Center, Jaquet-Droz 1, CH-2002 Neuchâtel (Switzerland)

2016-08-07

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation of such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto; Sevilla, Galo T.; Ghoneim, Mohamed T.; Inayat, Salman Bin; Ahmed, Sally; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2014-01-01

In today's traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

Science.gov (United States)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Optimized optical devices for edge-coupling-enabled silicon photonics platform

Science.gov (United States)

Png, Ching Eng; Ang, Thomas Y. L.; Ong, Jun Rong; Lim, Soon Thor; Sahin, Ezgi; Chen, G. F. R.; Tan, D. T. H.; Guo, Tina X.; Wang, Hong

2018-02-01

We present a library of high-performance passive and active silicon photonic devices at the C-band that is specifically designed and optimized for edge-coupling-enabled silicon photonics platform. These devices meet the broadband (100 nm), low-loss (= 25 Gb/s), and polarization diversity requirements (TE and TM polarization extinction ratio beam splitters (PBSs), and high-speed modulators are some of the devices within our library. In particular, we have designed and fabricated inverse taper fiber-to-waveguide edge couplers of tip widths ranging from 120 nm to 200 nm, and we obtained a low coupling loss of 1.80+/-0.28 dB for 160 nm tip width. To achieve polarization diversity operation for inverse tapers, we have experimentally realized different designs of polarization beam splitters (PBS). Our optimized PBS has a measured extinction ratio of <= 25 dB for both the quasiTE modes, and quasi-TM modes. Additionally, a broadband (100 nm) directional coupler with a 50/50 power splitting ratio was experimentally realized on a small footprint of 20×3 μm2 . Last but not least, high-speed silicon modulators with a range of carrier doping concentrations and offset of the PN junction can be used to optimise the modulation efficiency, and insertion losses for operation at 25 GHz.

Molecular monolayers for electrical passivation and functionalization of silicon-based solar energy devices

NARCIS (Netherlands)

Veerbeek, Janneke; Firet, Nienke J.; Vijselaar, Wouter; Elbersen, R.; Gardeniers, Han; Huskens, Jurriaan

2017-01-01

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.

2018-01-15

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent, with Kaneka setting the world\\'s silicon solar cell efficiency record of 26.63% using silicon heterojunction contacts in an interdigitated configuration. Although passivating-contact solar cells are remarkably efficient, their underlying device physics is not yet completely understood, not in the least because they are constructed from diverse materials that may introduce electronic barriers in the current flow. To bridge this gap in understanding, we explore the device physics of passivating contact silicon heterojunction (SHJ) solar cells. Here, we identify the key properties of heterojunctions that affect cell efficiency, analyze the dependence of key heterojunction properties on carrier transport under light and dark conditions, provide a self-consistent multiprobe approach to extract heterojunction parameters using several characterization techniques (including dark J-V, light J-V, C-V, admittance spectroscopy, and Suns-Voc), propose design guidelines to address bottlenecks in energy production in SHJ cells, and develop a process-to-module modeling framework to establish the module\\'s performance limits. We expect that our proposed guidelines resulting from this multiscale and self-consistent framework will improve the performance of future SHJ cells as well as other passivating contact-based solar cells.

Tin (Sn) for enhancing performance in silicon CMOS

KAUST Repository

Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

2013-01-01

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

Tin (Sn) for enhancing performance in silicon CMOS

KAUST Repository

Hussain, Aftab M.

2013-10-01

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

Luneburg lens in silicon photonics.

Science.gov (United States)

Di Falco, Andrea; Kehr, Susanne C; Leonhardt, Ulf

2011-03-14

The Luneburg lens is an aberration-free lens that focuses light from all directions equally well. We fabricated and tested a Luneburg lens in silicon photonics. Such fully-integrated lenses may become the building blocks of compact Fourier optics on chips. Furthermore, our fabrication technique is sufficiently versatile for making perfect imaging devices on silicon platforms.

Hybrid III-V/silicon lasers

Science.gov (United States)

Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

2014-05-01

The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

Friction and dynamically dissipated energy dependence on temperature in polycrystalline silicon MEMS devices

NARCIS (Netherlands)

Gkouzou, A.; Kokorian, J.; Janssen, G.C.A.M.; van Spengen, W.M.

2017-01-01

In this paper, we report on the influence of capillary condensation on the sliding friction of sidewall surfaces in polycrystalline silicon micro-electromechanical
systems (MEMS). We developed a polycrystalline silicon MEMS tribometer, which is a microscale test device with two components

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

Science.gov (United States)

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.; De Wolf, Stefaan; Alam, Muhammad A.

2018-01-01

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent

Silicon photonics for telecommunications and biomedicine

CERN Document Server

Fathpour, Sasan

2011-01-01

Given silicon's versatile material properties, use of low-cost silicon photonics continues to move beyond light-speed data transmission through fiber-optic cables and computer chips. Its application has also evolved from the device to the integrated-system level. A timely overview of this impressive growth, Silicon Photonics for Telecommunications and Biomedicine summarizes state-of-the-art developments in a wide range of areas, including optical communications, wireless technologies, and biomedical applications of silicon photonics. With contributions from world experts, this reference guides

A physically transient form of silicon electronics.

Science.gov (United States)

Hwang, Suk-Won; Tao, Hu; Kim, Dae-Hyeong; Cheng, Huanyu; Song, Jun-Kyul; Rill, Elliott; Brenckle, Mark A; Panilaitis, Bruce; Won, Sang Min; Kim, Yun-Soung; Song, Young Min; Yu, Ki Jun; Ameen, Abid; Li, Rui; Su, Yewang; Yang, Miaomiao; Kaplan, David L; Zakin, Mitchell R; Slepian, Marvin J; Huang, Yonggang; Omenetto, Fiorenzo G; Rogers, John A

2012-09-28

A remarkable feature of modern silicon electronics is its ability to remain physically invariant, almost indefinitely for practical purposes. Although this characteristic is a hallmark of applications of integrated circuits that exist today, there might be opportunities for systems that offer the opposite behavior, such as implantable devices that function for medically useful time frames but then completely disappear via resorption by the body. We report a set of materials, manufacturing schemes, device components, and theoretical design tools for a silicon-based complementary metal oxide semiconductor (CMOS) technology that has this type of transient behavior, together with integrated sensors, actuators, power supply systems, and wireless control strategies. An implantable transient device that acts as a programmable nonantibiotic bacteriocide provides a system-level example.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.; Rojas, Jhonathan Prieto; Ahmed, Sally; Hussain, Aftab M.; Inayat, Salman Bin; Hussain, Muhammad Mustafa

2013-01-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.

2013-06-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Integrated control rod monitoring device

International Nuclear Information System (INIS)

Saito, Katsuhiro

1997-01-01

The present invention provides a device in which an entire control rod driving time measuring device and a control rod position support device in a reactor building and a central control chamber are integrated systematically to save hardwares such as a signal input/output device and signal cables between boards. Namely, (1) functions of the entire control rod driving time measuring device for monitoring control rods which control the reactor power and a control rod position indication device are integrated into one identical system. Then, the entire devices can be made compact by the integration of the functions. (2) The functions of the entire control rod driving time measuring device and the control rod position indication device are integrated in a central operation board and a board in the site. Then, the place for the installation of them can be used in common in any of the cases. (3) The functions of the entire control rod driving time measuring device and the control rod position indication device are integrated to one identical system to save hardware to be used. Then, signal input/output devices and drift branching panel boards in the site and the central operation board can be saved, and cables for connecting both of the boards is no more necessary. (I.S.)

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

Directory of Open Access Journals (Sweden)

L. Aluigi

2013-09-01

Full Text Available The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer Design Automation on Silicon (MIDAS that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer on the bases of the design entries (specifications. It draws the inductor (transformer layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM. Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment.

Strong quantum-confined stark effect in germanium quantum-well structures on silicon

International Nuclear Information System (INIS)

Kuo, Y.; Lee, Y. K.; Gei, Y.; Ren, S; Roth, J. E.; Miller, D. A.; Harris, J. S.

2006-01-01

Silicon is the dominant semiconductor for electronics, but there is now a growing need to integrate such component with optoelectronics for telecommunications and computer interconnections. Silicon-based optical modulators have recently been successfully demonstrated but because the light modulation mechanisms in silicon are relatively weak, long (for example, several millimeters) devices or sophisticated high-quality-factor resonators have been necessary. Thin quantum-well structures made from III-V semiconductors such as GaAs, InP and their alloys exhibit the much stronger Quantum-Confined Stark Effect (QCSE) mechanism, which allows modulator structures with only micrometers of optical path length. Such III-V materials are unfortunately difficult to integrate with silicon electronic devices. Germanium is routinely integrated with silicon in electronics, but previous silicon-germanium structures have also not shown strong modulation effects. Here we report the discovery of the QCSE, at room temperature, in thin germanium quantum-well structures grown on silicon. The QCSE here has strengths comparable to that in III-V materials. Its clarity and strength are particularly surprising because germanium is an indirect gap semiconductor, such semiconductors often display much weak optical effects than direct gap materials (such as the III-V materials typically used for optoelectronics). This discovery is very promising for small, high-speed, low-power optical output devices fully compatible with silicon electronics manufacture. (author)

Label-Free Virus Capture and Release by a Microfluidic Device Integrated with Porous Silicon Nanowire Forest.

Science.gov (United States)

Xia, Yiqiu; Tang, Yi; Yu, Xu; Wan, Yuan; Chen, Yizhu; Lu, Huaguang; Zheng, Si-Yang

2017-02-01

Viral diseases are perpetual threats to human and animal health. Detection and characterization of viral pathogens require accurate, sensitive, and rapid diagnostic assays. For field and clinical samples, the sample preparation procedures limit the ultimate performance and utility of the overall virus diagnostic protocols. This study presents the development of a microfluidic device embedded with porous silicon nanowire (pSiNW) forest for label-free size-based point-of-care virus capture in a continuous curved flow design. The pSiNW forests with specific interwire spacing are synthesized in situ on both bottom and sidewalls of the microchannels in a batch process. With the enhancement effect of Dean flow, this study demonstrates that about 50% H5N2 avian influenza viruses are physically trapped without device clogging. A unique feature of the device is that captured viruses can be released by inducing self-degradation of the pSiNWs in physiological aqueous environment. About 60% of captured viruses can be released within 24 h for virus culture, subsequent molecular diagnosis, and other virus characterization and analyses. This device performs viable, unbiased, and label-free virus isolation and release. It has great potentials for virus discovery, virus isolation and culture, functional studies of virus pathogenicity, transmission, drug screening, and vaccine development. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Off-axis electron holography for the measurement of active dopants in silicon semiconductor devices

International Nuclear Information System (INIS)

Cooper, David

2016-01-01

There is a need in the semiconductor industry for a dopant profiling technique with nm-scale resolution. Here we demonstrate that off-axis electron holography can be used to provide maps of the electrostatic potential in semiconductor devices with nm-scale resolution. In this paper we will discuss issues regarding the spatial resolution and precision of the technique. Then we will discuss problems with specimen preparation and how this affects the accuracy of the measurements of the potentials. Finally we show results from experimental off-axis electron holography applied to nMOS and pMOS CMOS devices grown on bulk silicon and silicon- on-insulator type devices and present solutions to common problems that are encountered when examining these types of devices. (paper)

Silicon Photonic Integrated Circuit Mode Multiplexer

DEFF Research Database (Denmark)

Ding, Yunhong; Ou, Haiyan; Xu, Jing

2013-01-01

We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully...

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2014-12-01

Today\\'s mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Kutbee, Arwa T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Today's mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

A silicon integrated micro nano-positioning XY-stage for nano-manipulation

International Nuclear Information System (INIS)

Sun Lining; Wang Jiachou; Rong Weibin; Li Xinxin; Bao Haifei

2008-01-01

An integrated micro XY-stage with a 2 × 2 mm 2 movable table is designed and fabricated for application in nanometer-scale operation and nanometric positioning precision. The device integrates the functions of both actuating and sensing in a monolithic chip and is mainly composed of a silicon-based XY-stage, comb-drive actuator and a displacement sensor, which are developed by using double-sided bulk-micromachining technology. The high-aspect-ratio comb-driven XY-stage is achieved by deep reactive ion etching (DRIE) on both sides of the wafer. The displacement sensor is formed on four vertical sidewall surface piezoresistors with a full Wheatstone bridge circuit, where a novel fabrication process of a vertical sidewall surface piezoresistor is proposed. Comprehensive design and analysis of the comb actuator, the piezoresistive displacement sensor and the XY-stage are given in full detail, and the experimental results verify the design and fabrication of the device. The final realization of the device shows that the sensitivity of the fabricated piezoresistive sensors is better than 1.17 mV µm −1 without amplification, and the linearity is better than 0.814%. Under 28.5 V driving voltage, a ±10 µm single-axis displacement is measured without crosstalk and the resonant frequency is measured at 983 Hz in air

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

Science.gov (United States)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

DEFF Research Database (Denmark)

Strobel, S.; Albert, E.; Csaba, G.

2009-01-01

We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

Science.gov (United States)

Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

2017-02-15

An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

3D silicon neural probe with integrated optical fibers for optogenetic modulation.

Science.gov (United States)

Kim, Eric G R; Tu, Hongen; Luo, Hao; Liu, Bin; Bao, Shaowen; Zhang, Jinsheng; Xu, Yong

2015-07-21

Optogenetics is a powerful modality for neural modulation that can be useful for a wide array of biomedical studies. Penetrating microelectrode arrays provide a means of recording neural signals with high spatial resolution. It is highly desirable to integrate optics with neural probes to allow for functional study of neural tissue by optogenetics. In this paper, we report the development of a novel 3D neural probe coupled simply and robustly to optical fibers using a hollow parylene tube structure. The device shanks are hollow tubes with rigid silicon tips, allowing the insertion and encasement of optical fibers within the shanks. The position of the fiber tip can be precisely controlled relative to the electrodes on the shank by inherent design features. Preliminary in vivo rat studies indicate that these devices are capable of optogenetic modulation simultaneously with 3D neural signal recording.

A miniaturized silicon based device for nucleic acids electrochemical detection

Directory of Open Access Journals (Sweden)

Salvatore Petralia

2015-12-01

Full Text Available In this paper we describe a novel portable system for nucleic acids electrochemical detection. The core of the system is a miniaturized silicon chip composed by planar microelectrodes. The chip is embedded on PCB board for the electrical driving and reading. The counter, reference and work microelectrodes are manufactured using the VLSI technology, the material is gold for reference and counter electrodes and platinum for working electrode. The device contains also a resistor to control and measuring the temperature for PCR thermal cycling. The reaction chamber has a total volume of 20 μL. It is made in hybrid silicon–plastic technology. Each device contains four independent electrochemical cells.Results show HBV Hepatitis-B virus detection using an unspecific DNA intercalating redox probe based on metal–organic compounds. The recognition event is sensitively detected by square wave voltammetry monitoring the redox signals of the intercalator that strongly binds to the double-stranded DNA. Two approaches were here evaluated: (a intercalation of electrochemical unspecific probe on ds-DNA on homogeneous solution (homogeneous phase; (b grafting of DNA probes on electrode surface (solid phase.The system and the method here reported offer better advantages in term of analytical performances compared to the standard commercial optical-based real-time PCR systems, with the additional incomes of being potentially cheaper and easier to integrate in a miniaturized device. Keywords: Electrochemical detection, Real time PCR, Unspecific DNA intercalator

RFID and Memory Devices Fabricated Integrally on Substrates

Science.gov (United States)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

Subwavelength silicon photonics

International Nuclear Information System (INIS)

Cheben, P.; Bock, P.J.; Schmid, J.H.; Lapointe, J.; Janz, S.; Xu, D.-X.; Densmore, A.; Delage, A.; Lamontagne, B.; Florjanczyk, M.; Ma, R.

2011-01-01

With the goal of developing photonic components that are compatible with silicon microelectronic integrated circuits, silicon photonics has been the subject of intense research activity. Silicon is an excellent material for confining and manipulating light at the submicrometer scale. Silicon optoelectronic integrated devices have the potential to be miniaturized and mass-produced at affordable cost for many applications, including telecommunications, optical interconnects, medical screening, and biological and chemical sensing. We review recent advances in silicon photonics research at the National Research Council Canada. A new type of optical waveguide is presented, exploiting subwavelength grating (SWG) effect. We demonstrate subwavelength grating waveguides made of silicon, including practical components operating at telecom wavelengths: input couplers, waveguide crossings and spectrometer chips. SWG technique avoids loss and wavelength resonances due to diffraction effects and allows for single-mode operation with direct control of the mode confinement by changing the refractive index of a waveguide core over a range as broad as 1.6 - 3.5 simply by lithographic patterning. The light can be launched to these waveguides with a coupling loss as small as 0.5 dB and with minimal wavelength dependence, using coupling structures similar to that shown in Fig. 1. The subwavelength grating waveguides can cross each other with minimal loss and negligible crosstalk which allows massive photonic circuit connectivity to overcome the limits of electrical interconnects. These results suggest that the SWG waveguides could become key elements for future integrated photonic circuits. (authors)

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto

2013-01-07

Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

Science.gov (United States)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Micromachined silicon cantilevers with integrated high-frequency magnetoimpedance sensors for simultaneous strain and magnetic field detection

Science.gov (United States)

Buettel, G.; Joppich, J.; Hartmann, U.

2017-12-01

Giant magnetoimpedance (GMI) measurements in the high-frequency regime utilizing a coplanar waveguide with an integrated Permalloy multilayer and micromachined on a silicon cantilever are reported. The fabrication process is described in detail. The aspect ratio of the magnetic multilayer in the magnetoresistive and magnetostrictive device was varied. Tensile strain and compressive strain were applied. Vector network analyzer measurements in the range from the skin effect to ferromagnetic resonance confirm the technological potential of GMI-based micro-electro-mechanical devices for strain and magnetic field sensing applications. The strain-impedance gauge factor was quantified by finite element strain calculations and reaches a maximum value of almost 200.

Environmentally benign silicon solar cell manufacturing

Energy Technology Data Exchange (ETDEWEB)

Tsuo, Y.S. [National Renewable Energy Lab., Golden, CO (United States); Gee, J.M. [Sandia National Labs., Albuquerque, NM (United States); Menna, P. [National Agency for New Technologies Energy and Environment, Portici (Italy); Strebkov, D.S.; Pinov, A.; Zadde, V. [Intersolarcenter, Moscow (Russian Federation)

1998-09-01

The manufacturing of silicon devices--from polysilicon production, crystal growth, ingot slicing, wafer cleaning, device processing, to encapsulation--requires many steps that are energy intensive and use large amounts of water and toxic chemicals. In the past two years, the silicon integrated-circuit (IC) industry has initiated several programs to promote environmentally benign manufacturing, i.e., manufacturing practices that recover, recycle, and reuse materials resources with a minimal consumption of energy. Crystalline-silicon solar photovoltaic (PV) modules, which accounted for 87% of the worldwide module shipments in 1997, are large-area devices with many manufacturing steps similar to those used in the IC industry. Obviously, there are significant opportunities for the PV industry to implement more environmentally benign manufacturing approaches. Such approaches often have the potential for significant cost reduction by reducing energy use and/or the purchase volume of new chemicals and by cutting the amount of used chemicals that must be discarded. This paper will review recent accomplishments of the IC industry initiatives and discuss new processes for environmentally benign silicon solar-cell manufacturing.

Towards Cost-Effective Crystalline Silicon Based Flexible Solar Cells: Integration Strategy by Rational Design of Materials, Process, and Devices

KAUST Repository

Bahabry, Rabab R.

2017-11-30

The solar cells market has an annual growth of more than 30 percent over the past 15 years. At the same time, the cost of the solar modules diminished to meet both of the rapid global demand and the technological improvements. In particular for the crystalline silicon solar cells, the workhorse of this technology. The objective of this doctoral thesis is enhancing the efficiency of c-Si solar cells while exploring the cost reduction via innovative techniques. Contact metallization and ultra-flexible wafer based c-Si solar cells are the main areas under investigation. First, Silicon-based solar cells typically utilize screen printed Silver (Ag) metal contacts which affect the optimal electrical performance. To date, metal silicide-based ohmic contacts are occasionally used for the front contact grid lines. In this work, investigation of the microstructure and the electrical characteristics of nickel monosilicide (NiSi) ohmic contacts on the rear side of c-Si solar cells has been carried out. Significant enhancement in the fill factor leading to increasing the total power conversion efficiency is observed. Second, advanced classes of modern application require a new generation of versatile solar cells showcasing extreme mechanical resilience. However, silicon is a brittle material with a fracture strains <1%. Highly flexible Si-based solar cells are available in the form thin films which seem to be disadvantageous over thick Si solar cells due to the reduction of the optical absorption with less active Si material. Here, a complementary metal oxide semiconductor (CMOS) technology based integration strategy is designed where corrugation architecture to enable an ultra-flexible solar cell module from bulk mono-crystalline silicon solar wafer with 17% efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness and achieves flexibility via interdigitated back contacts. These cells

Dopant atoms as quantum components in silicon nanoscale devices

Science.gov (United States)

Zhao, Xiaosong; Han, Weihua; Wang, Hao; Ma, Liuhong; Li, Xiaoming; Zhang, Wang; Yan, Wei; Yang, Fuhua

2018-06-01

Recent progress in nanoscale fabrication allows many fundamental studies of the few dopant atoms in various semiconductor nanostructures. Since the size of nanoscale devices has touched the limit of the nature, a single dopant atom may dominate the performance of the device. Besides, the quantum computing considered as a future choice beyond Moore's law also utilizes dopant atoms as functional units. Therefore, the dopant atoms will play a significant role in the future novel nanoscale devices. This review focuses on the study of few dopant atoms as quantum components in silicon nanoscale device. The control of the number of dopant atoms and unique quantum transport characteristics induced by dopant atoms are presented. It can be predicted that the development of nanoelectronics based on dopant atoms will pave the way for new possibilities in quantum electronics. Project supported by National Key R&D Program of China (No. 2016YFA0200503).

Porous silicon structures with high surface area/specific pore size

Science.gov (United States)

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

MEMS monocrystalline-silicon based thermal devices for chemical and microfluidic applications

NARCIS (Netherlands)

Mihailovic, M.

2011-01-01

This thesis explores the employment of monocrystalline silicon in microsystems as an active material for different thermal functions, such as heat generation and heat transfer by conduction. In chapter 1 applications that need thermal micro devices, micro heaters and micro heat exchangers, are

Electronic spectrum of a deterministic single-donor device in silicon

International Nuclear Information System (INIS)

Fuechsle, Martin; Miwa, Jill A.; Mahapatra, Suddhasatta; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.

2013-01-01

We report the fabrication of a single-electron transistor (SET) based on an individual phosphorus dopant that is deterministically positioned between the dopant-based electrodes of a transport device in silicon. Electronic characterization at mK-temperatures reveals a charging energy that is very similar to the value expected for isolated P donors in a bulk Si environment. Furthermore, we find indications for bulk-like one-electron excited states in the co-tunneling spectrum of the device, in sharp contrast to previous reports on transport through single dopants

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

2007-07-25

A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

Fibre optic communication key devices

CERN Document Server

Grote, Norbert

2017-01-01

The book gives an in-depth description of key devices of current and next generation fibre optic communication networks. Devices treated include semiconductor lasers, optical amplifiers, modulators, wavelength filters and other passives, detectors, all-optical switches, but relevant properties of optical fibres and network aspects are included as well. The presentations include the physical principles underlying the various devices, technologies used for their realization, typical performance characteristics and limitations, but development trends towards more advanced components are also illustrated. This new edition of a successful book was expanded and updated extensively. The new edition covers among others lasers for optical communication, optical switches, hybrid integration, monolithic integration and silicon photonics. The main focus is on Indium phosphide-based structures but silicon photonics is included as well. The book covers relevant principles, state-of-the-art implementations, status of curren...

Effects of plasma-deposited silicon nitride passivation on the radiation hardness of CMOS integrated circuits

International Nuclear Information System (INIS)

Clement, J.J.

1980-01-01

The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2013-01-01

(100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

Integration of the End Cap TEC+ of the CMS Silicon Strip Tracker

CERN Document Server

Adler, Volker; Ageron, Michel; Agram, Jean-Laurent; Atz, Bernd; Barvich, Tobias; Baulieu, Guillaume; Beaumont, Willem; Beissel, Franz; Bergauer, Thomas; Berst, Jean-Daniel; Blüm, Peter; Bock, E; Bogelsbacher, F; de Boer, Wim; Bonnet, Jean-Luc; Bonnevaux, Alain; Boudoul, Gaelle; Bouhali, Othmane; Braunschweig, Wolfgang; Bremer, R; Brom, Jean-Marie; Butz, Erik; Chabanat, Eric; Chabert, Eric Christian; Clerbaux, Barbara; Contardo, Didier; De Callatay, Bernard; Dehm, Philip; Delaere, Christophe; Della Negra, Rodolphe; Dewulf, Jean-Paul; D'Hondt, Jorgen; Didierjean, Francois; Dierlamm, Alexander; Dirkes, Guido; Dragicevic, Marko; Drouhin, Frédéric; Ernenwein, Jean-Pierre; Esser, Hans; Estre, Nicolas; Fahrer, Manuel; Feld, Lutz; Fernández, J; Florins, Benoit; Flossdorf, Alexander; Flucke, Gero; Flügge, Günter; Fontaine, Jean-Charles; Freudenreich, Klaus; Frey, Martin; Friedl, Markus; Furgeri, Alexander; Giraud, Noël; Goerlach, Ulrich; Goorens, Robert; Graehling, Philippe; Grégoire, Ghislain; Gregoriev, E; Gross, Laurent; Hansel, S; Haroutunian, Roger; Hartmann, Frank; Heier, Stefan; Hermanns, Thomas; Heydhausen, Dirk; Heyninck, Jan; Hosselet, J; Hrubec, Josef; Jahn, Dieter; Juillot, Pierre; Kaminski, Jochen; Karpinski, Waclaw; Kaussen, Gordon; Keutgen, Thomas; Klanner, Robert; Klein, Katja; König, Stefan; Kosbow, M; Krammer, Manfred; Ledermann, Bernhard; Lemaître, Vincent; De Lentdecker, Gilles; Linn, Alexander; Lounis, Abdenour; Lübelsmeyer, Klaus; Lumb, Nicholas; Maazouzi, Chaker; Mahmoud, Tariq; Michotte, Daniel; Militaru, Otilia; Mirabito, Laurent; Müller, Thomas; Neukermans, Lionel; Ollivetto, C; Olzem, Jan; Ostapchuk, Andrey; Pandoulas, Demetrios; Pein, Uwe; Pernicka, Manfred; Perriès, Stephane; Piaseki, C; Pierschel, Gerhard; Piotrzkowski, Krzysztof; Poettgens, Michael; Pooth, Oliver; Rouby, Xavier; Sabellek, Andreas; Schael, Stefan; Schirm, Norbert; Schleper, Peter; Schmitz, Stefan Antonius; Schultz von Dratzig, Arndt; Siedling, Rolf; Simonis, Hans-Jürgen; Stahl, Achim; Steck, Pia; Steinbruck, G; Stoye, Markus; Strub, Roger; Tavernier, Stefaan; Teyssier, Daniel; Theel, Andreas; Trocmé, Benjamin; Udo, Fred; Van der Donckt, M; Van der Velde, C; Van Hove, Pierre; Vanlaer, Pascal; Van Lancker, Luc; Van Staa, Rolf; Vanzetto, Sylvain; Weber, Markus; Weiler, Thomas; Weseler, Siegfried; Wickens, John; Wittmer, Bruno; Wlochal, Michael; De Wolf, Eddi A; Zhukov, Valery; Zoeller, Marc Henning

2009-01-01

The silicon strip tracker of the CMS experiment has been completed and inserted into the CMS detector in late 2007. The largest sub-system of the tracker is its end cap system, comprising two large end caps (TEC) each containing 3200 silicon strip modules. To ease construction, the end caps feature a modular design: groups of about 20 silicon modules are placed on sub-assemblies called petals and these self-contained elements are then mounted into the TEC support structures. Each end cap consists of 144 petals, and the insertion of these petals into the end cap structure is referred to as TEC integration. The two end caps were integrated independently in Aachen (TEC+) and at CERN (TEC--). This note deals with the integration of TEC+, describing procedures for end cap integration and for quality control during testing of integrated sections of the end cap and presenting results from the testing.

Compact integrated optical devices for optical sensor and switching applications

NARCIS (Netherlands)

Kauppinen, L.J.

2010-01-01

This thesis describes the design, fabrication, and characterization of compact optical devices for sensing and switching applications. Our focus has been to realize the devices using CMOS-compatible fabrication processes. Particularly the silicon photonics fabrication platform, ePIXfab, has been

Fabrication of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Holland, S.

1988-06-01

A new process for the fabrication of silicon p-i-n diode radiation detectors is described. The utilization of backside gettering in the fabrication process results in the actual physical removal of detrimental impurities from critical device regions. This reduces the sensitivity of detector properties to processing variables while yielding low diode reverse-leakage currents. In addition, gettering permits the use of processing temperatures compatible with integrated-circuit fabrication. P-channel MOSFETs and silicon p-i-n diodes have been fabricated simultaneously on 10 kΩ/centerreverse arrowdot/cm silicon using conventional integrated-circuit processing techniques. 25 refs., 5 figs

Packaging of silicon sensors for microfluidic bio-analytical applications

International Nuclear Information System (INIS)

Wimberger-Friedl, Reinhold; Prins, Menno; Megens, Mischa; Dittmer, Wendy; Witz, Christiane de; Nellissen, Ton; Weekamp, Wim; Delft, Jan van; Ansems, Will; Iersel, Ben van

2009-01-01

A new industrial concept is presented for packaging biosensor chips in disposable microfluidic cartridges to enable medical diagnostic applications. The inorganic electronic substrates, such as silicon or glass, are integrated in a polymer package which provides the electrical and fluidic interconnections to the world and provides mechanical strength and protection for out-of-lab use. The demonstrated prototype consists of a molded interconnection device (MID), a silicon-based giant magneto-resistive (GMR) biosensor chip, a flex and a polymer fluidic part with integrated tubing. The various processes are compatible with mass manufacturing and run at a high yield. The devices show a reliable electrical interconnection between the sensor chip and readout electronics during extended wet operation. Sandwich immunoassays were carried out in the cartridges with surface functionalized sensor chips. Biological response curves were determined for different concentrations of parathyroid hormone (PTH) on the packaged biosensor, which demonstrates the functionality and biocompatibility of the devices. The new packaging concept provides a platform for easy further integration of electrical and fluidic functions, as for instance required for integrated molecular diagnostic devices in cost-effective mass manufacturing

Epitaxial III-V nanowires on silicon for vertical devices

NARCIS (Netherlands)

Bakkers, E.P.A.M.; Borgström, M.T.; Einden, Van Den W.; Weert, van M.H.M.; Helman, A.; Verheijen, M.A.

2006-01-01

We show the epitaxial integration of III-V semiconductor nanowires with silicon technology. The wires are grown by the Vapor-Liquid-Solid (VLS) mechanism with laser ablation as well as metal organic vapor phase epitaxy. The VLS growth enables the fabrication of complex axial and radial

Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

GaN-on-Silicon - Present capabilities and future directions

Science.gov (United States)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Passive technologies for future large-scale photonic integrated circuits on silicon: polarization handling, light non-reciprocity and loss reduction

Directory of Open Access Journals (Sweden)

Daoxin Dai

2012-03-01

Full Text Available Silicon-based large-scale photonic integrated circuits are becoming important, due to the need for higher complexity and lower cost for optical transmitters, receivers and optical buffers. In this paper, passive technologies for large-scale photonic integrated circuits are described, including polarization handling, light non-reciprocity and loss reduction. The design rule for polarization beam splitters based on asymmetrical directional couplers is summarized and several novel designs for ultra-short polarization beam splitters are reviewed. A novel concept for realizing a polarization splitter–rotator is presented with a very simple fabrication process. Realization of silicon-based light non-reciprocity devices (e.g., optical isolator, which is very important for transmitters to avoid sensitivity to reflections, is also demonstrated with the help of magneto-optical material by the bonding technology. Low-loss waveguides are another important technology for large-scale photonic integrated circuits. Ultra-low loss optical waveguides are achieved by designing a Si3N4 core with a very high aspect ratio. The loss is reduced further to <0.1 dB m−1 with an improved fabrication process incorporating a high-quality thermal oxide upper cladding by means of wafer bonding. With the developed ultra-low loss Si3N4 optical waveguides, some devices are also demonstrated, including ultra-high-Q ring resonators, low-loss arrayed-waveguide grating (demultiplexers, and high-extinction-ratio polarizers.

The use of silicon devices (diodes, RAMs, etc.) for alpha particle detection

International Nuclear Information System (INIS)

Agosteo, S.; Foglio Para, A.

1993-01-01

Silicon electronic devices (diodes, random access memories (RAMs), etc.) can be employed in alpha particle detection and spectroscopy with a good energy resolution. The detection mechanisms are first discussed; the performances of these devices operating in the pulse and in the current mode are then described starting from the pioneering works of the last decade. Some peculiar applications of RAMs are finally reported. (author). 7 refs, 5 figs, 1 tab

A 40-GBd QPSK/16-QAM integrated silicon coherent receiver

NARCIS (Netherlands)

Verbist, J.; Zhang, J.; Moeneclaey, B.; Soenen, W.; Van Weerdenburg, J.J.A.; Van Uden, R.; Okonkwo, C.M.; Bauwelinck, J.; Roelkens, G.; Yin, X.

2016-01-01

Through co-design of a dual SiGe transimpedance amplifier and an integrated silicon photonic circuit, we realized for the first time an ultra-compact and low-power silicon single-polarization coherent receiver operating at 40 GBd. A bit-error rate of <3.8× 10-3 was obtained for an optical

Silicide/Silicon Heterointerfaces, Reaction Kinetics and Ultra-short Channel Devices

Science.gov (United States)

Tang, Wei

Nickel silicide is one of the electrical contact materials widely used on very large scale integration (VLSI) of Si devices in microelectronic industry. This is because the silicide/silicon interface can be formed in a highly controlled manner to ensure reproducibility of optimal structural and electrical properties of the metal-Si contacts. These advantages can be inherited to Si nanowire (NW) field-effect transistors (FET) device. Due to the technological importance of nickel silicides, fundamental materials science of nickel silicides formation (Ni-Si reaction), especially in nanoscale, has raised wide interest and stimulate new insights and understandings. In this dissertation, in-situ transmission electron microscopy (TEM) in combination with FET device characterization will be demonstrated as useful tools in nano-device fabrication as well as in gaining insights into the process of nickel silicide formation. The shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) has been demonstrated by controlled reaction with Ni leads on an in-situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 ºC. NiSi2 is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (microA/microm) and a maximum transconductance of 430 (microS/microm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of (17 nm -- 3.6 microm). Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs

Thin film silicon by a microwave plasma deposition technique: Growth and devices, and, interface effects in amorphous silicon/crystalline silicon solar cells

Science.gov (United States)

Jagannathan, Basanth

Thin film silicon (Si) was deposited by a microwave plasma CVD technique, employing double dilution of silane, for the growth of low hydrogen content Si films with a controllable microstructure on amorphous substrates at low temperatures (prepared by this technique. Such films showed a dark conductivity ˜10sp{-6} S/cm, with a conduction activation energy of 0.49 eV. Film growth and properties have been compared for deposition in Ar and He carrier systems and growth models have been proposed. Low temperature junction formation by undoped thin film silicon was examined through a thin film silicon/p-type crystalline silicon heterojunctions. The thin film silicon layers were deposited by rf glow discharge, dc magnetron sputtering and microwave plasma CVD. The hetero-interface was identified by current transport analysis and high frequency capacitance methods as the key parameter controlling the photovoltaic (PV) response. The effect of the interface on the device properties (PV, junction, and carrier transport) was examined with respect to modifications created by chemical treatment, type of plasma species, their energy and film microstructure interacting with the substrate. Thermally stimulated capacitance was used to determine the interfacial trap parameters. Plasma deposition of thin film silicon on chemically clean c-Si created electron trapping sites while hole traps were seen when a thin oxide was present at the interface. Under optimized conditions, a 10.6% efficient cell (11.5% with SiOsb2 A/R) with an open circuit voltage of 0.55 volts and a short circuit current density of 30 mA/cmsp2 was fabricated.

Design Procedure and Fabrication of Reproducible Silicon Vernier Devices for High-Performance Refractive Index Sensing.

Science.gov (United States)

Troia, Benedetto; Khokhar, Ali Z; Nedeljkovic, Milos; Reynolds, Scott A; Hu, Youfang; Mashanovich, Goran Z; Passaro, Vittorio M N

2015-06-10

In this paper, we propose a generalized procedure for the design of integrated Vernier devices for high performance chemical and biochemical sensing. In particular, we demonstrate the accurate control of the most critical design and fabrication parameters of silicon-on-insulator cascade-coupled racetrack resonators operating in the second regime of the Vernier effect, around 1.55 μm. The experimental implementation of our design strategies has allowed a rigorous and reliable investigation of the influence of racetrack resonator and directional coupler dimensions as well as of waveguide process variability on the operation of Vernier devices. Figures of merit of our Vernier architectures have been measured experimentally, evidencing a high reproducibility and a very good agreement with the theoretical predictions, as also confirmed by relative errors even lower than 1%. Finally, a Vernier gain as high as 30.3, average insertion loss of 2.1 dB and extinction ratio up to 30 dB have been achieved.

Molecular Monolayers for Electrical Passivation and Functionalization of Silicon-Based Solar Energy Devices.

Science.gov (United States)

Veerbeek, Janneke; Firet, Nienke J; Vijselaar, Wouter; Elbersen, Rick; Gardeniers, Han; Huskens, Jurriaan

2017-01-11

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based solar cells. Organic monolayers were coupled to silicon surfaces by hydrosilylation in order to avoid an insulating silicon oxide layer at the surface. Monolayers of 1-tetradecyne were shown to passivate silicon micropillar-based solar cells with radial junctions, by which the efficiency increased from 8.7% to 9.9% for n + /p junctions and from 7.8% to 8.8% for p + /n junctions. This electrical passivation of the surface, most likely by removal of dangling bonds, is reflected in a higher shunt resistance in the J-V measurements. Monolayers of 1,8-nonadiyne were still reactive for click chemistry with a model catalyst, thus enabling simultaneous passivation and future catalyst coupling.

Lanthanide-Assisted Deposition of Strongly Electro-optic PZT Thin Films on Silicon: Toward Integrated Active Nanophotonic Devices.

Science.gov (United States)

George, J P; Smet, P F; Botterman, J; Bliznuk, V; Woestenborghs, W; Van Thourhout, D; Neyts, K; Beeckman, J

2015-06-24

The electro-optical properties of lead zirconate titanate (PZT) thin films depend strongly on the quality and crystallographic orientation of the thin films. We demonstrate a novel method to grow highly textured PZT thin films on silicon using the chemical solution deposition (CSD) process. We report the use of ultrathin (5-15 nm) lanthanide (La, Pr, Nd, Sm) based intermediate layers for obtaining preferentially (100) oriented PZT thin films. X-ray diffraction measurements indicate preferentially oriented intermediate Ln2O2CO3 layers providing an excellent lattice match with the PZT thin films grown on top. The XRD and scanning electron microscopy measurements reveal that the annealed layers are dense, uniform, crack-free and highly oriented (>99.8%) without apparent defects or secondary phases. The EDX and HRTEM characterization confirm that the template layers act as an efficient diffusion barrier and form a sharp interface between the substrate and the PZT. The electrical measurements indicate a dielectric constant of ∼650, low dielectric loss of ∼0.02, coercive field of 70 kV/cm, remnant polarization of 25 μC/cm(2), and large breakdown electric field of 1000 kV/cm. Finally, the effective electro-optic coefficients of the films are estimated with a spectroscopic ellipsometer measurement, considering the electric field induced variations in the phase reflectance ratio. The electro-optic measurements reveal excellent linear effective pockels coefficients of 110 to 240 pm/V, which makes the CSD deposited PZT thin film an ideal candidate for Si-based active integrated nanophotonic devices.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

Science.gov (United States)

Tour, James M; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2013-11-26

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the the gap region between the first electical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Device for fracturing silicon-carbide coatings on nuclear-fuel particles

Science.gov (United States)

Turner, L.J.; Willey, M.G.; Tiegs, S.M.; Van Cleve, J.E. Jr.

This invention is a device for fracturing particles. It is designed especially for use in hot cells designed for the handling of radioactive materials. In a typical application, the device is used to fracture a hard silicon-carbide coating present on carbon-matrix microspheres containing nuclear-fuel materials, such as uranium or thorium compounds. To promote remote control and facilitate maintenance, the particle breaker is pneumatically operated and contains no moving parts. It includes means for serially entraining the entrained particles on an anvil housed in a leak-tight chamber. The flow rate of the gas is at a value effecting fracture of the particles; preferably, it is at a value fracturing them into product particulates of fluidizable size. The chamber is provided with an outlet passage whose cross-sectional area decreases in the direction away from the chamber. The outlet is connected tangentially to a vertically oriented vortex-flow separator for recovering the product particulates entrained in the gas outflow from the chamber. The invention can be used on a batch or continuous basis to fracture the silicon-carbide coatings on virtually all of the particles fed thereto.

Graphene-on-silicon hybrid plasmonic-photonic integrated circuits.

Science.gov (United States)

Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

2017-06-16

Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

Science.gov (United States)

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

International Nuclear Information System (INIS)

Holland, S.

1991-11-01

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

Fabrication of micromirrors with pyramidal shape using anisotropic etching of silicon

OpenAIRE

Moktadir, Z.; Vijaya Prakash, G.; Trupke, M.; Koukharenko, E.; Kraft, M.; Baumberg, J.J.; Eriksson, S.; Hinds, E.A.

2005-01-01

Gold micro-mirrors have been formed in silicon in an inverted pyramidal shape. The pyramidal structures are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micro-mirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into MOEMS systems.

In Situ TEM Creation of Nanowire Devices

DEFF Research Database (Denmark)

Alam, Sardar Bilal

Integration of silicon nanowires (SiNWs) as active components in devices requires that desired mechanical, thermal and electrical interfaces can be established between the nanoscale geometry of the SiNW and the microscale architecture of the device. In situ transmission electron microscopy (TEM),...

Advances in silicon nanophotonics

DEFF Research Database (Denmark)

Hvam, Jørn Märcher; Pu, Minhao

Silicon has long been established as an ideal material for passive integrated optical circuitry due to its high refractive index, with corresponding strong optical confinement ability, and its low-cost CMOS-compatible manufacturability. However, the inversion symmetry of the silicon crystal lattice.......g. in high-bit-rate optical communication circuits and networks, it is vital that the nonlinear optical effects of silicon are being strongly enhanced. This can among others be achieved in photonic-crystal slow-light waveguides and in nano-engineered photonic-wires (Fig. 1). In this talk I shall present some...... recent advances in this direction. The efficient coupling of light between optical fibers and the planar silicon devices and circuits is of crucial importance. Both end-coupling (Fig. 1) and grating-coupling solutions will be discussed along with polarization issues. A new scheme for a hybrid III...

Integrated lenses in polystyrene microfluidic devices

KAUST Repository

Fan, Yiqiang; Li, Huawei; Foulds, Ian G.

2013-01-01

This paper reports a new method for integrating microlenses into microfluidic devices for improved observation. Two demonstration microfluidic devices were provided which were fabricated using this new technique. The integrated microlenses were

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

Science.gov (United States)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Optimization and validation of highly selective microfluidic integrated silicon nanowire chemical sensor

Science.gov (United States)

Ehfaed, Nuri. A. K. H.; Bathmanathan, Shillan A. L.; Dhahi, Th S.; Adam, Tijjani; Hashim, Uda; Noriman, N. Z.

2017-09-01

The study proposed characterization and optimization of silicon nanosensor for specific detection of heavy metal. The sensor was fabricated in-house and conventional photolithography coupled with size reduction via dry etching process in an oxidation furnace. Prior to heavy metal heavy metal detection, the capability to aqueous sample was determined utilizing serial DI water at various. The sensor surface was surface modified with Organofunctional alkoxysilanes (3-aminopropyl) triethoxysilane (APTES) to create molecular binding chemistry. This has allowed interaction between heavy metals being measured and the sensor component resulting in increasing the current being measured. Due to its, excellent detection capabilities, this sensor was able to identify different group heavy metal species. The device was further integrated with sub-50 µm for chemical delivery.

Impurity engineering of Czochralski silicon used for ultra large-scaled-integrated circuits

Science.gov (United States)

Yang, Deren; Chen, Jiahe; Ma, Xiangyang; Que, Duanlin

2009-01-01

Impurities in Czochralski silicon (Cz-Si) used for ultra large-scaled-integrated (ULSI) circuits have been believed to deteriorate the performance of devices. In this paper, a review of the recent processes from our investigation on internal gettering in Cz-Si wafers which were doped with nitrogen, germanium and/or high content of carbon is presented. It has been suggested that those impurities enhance oxygen precipitation, and create both denser bulk microdefects and enough denuded zone with the desirable width, which is benefit of the internal gettering of metal contamination. Based on the experimental facts, a potential mechanism of impurity doping on the internal gettering structure is interpreted and, a new concept of 'impurity engineering' for Cz-Si used for ULSI is proposed.

Silicon Nanowires for All-Optical Signal Processing in Optical Communication

DEFF Research Database (Denmark)

Pu, Minhao; Hu, Hao; Ji, Hua

2012-01-01

Silicon (Si), the second most abundant element on earth, has dominated in microelectronics for many decades. It can also be used for photonic devices due to its transparency in the range of optical telecom wavelengths which will enable a platform for a monolithic integration of optics...... and microelectronics. Silicon photonic nanowire waveguides fabricated on silicon-on-insulator (SOI) substrates are crucial elements in nano-photonic integrated circuits. The strong light confinement in nanowires induced by high index contrast SOI material enhances the nonlinear effects in the silicon nanowire core...... such as four-wave mixing (FWM) which is an imperative process for optical signal processing. Since the current mature silicon fabrication technology enables a precise dimension control on nanowires, dispersion engineering can be performed by tailoring nanowire dimensions to realize an efficient nonlinear...

High performance bio-integrated devices

Science.gov (United States)

Kim, Dae-Hyeong; Lee, Jongha; Park, Minjoon

2014-06-01

In recent years, personalized electronics for medical applications, particularly, have attracted much attention with the rise of smartphones because the coupling of such devices and smartphones enables the continuous health-monitoring in patients' daily life. Especially, it is expected that the high performance biomedical electronics integrated with the human body can open new opportunities in the ubiquitous healthcare. However, the mechanical and geometrical constraints inherent in all standard forms of high performance rigid wafer-based electronics raise unique integration challenges with biotic entities. Here, we describe materials and design constructs for high performance skin-mountable bio-integrated electronic devices, which incorporate arrays of single crystalline inorganic nanomembranes. The resulting electronic devices include flexible and stretchable electrophysiology electrodes and sensors coupled with active electronic components. These advances in bio-integrated systems create new directions in the personalized health monitoring and/or human-machine interfaces.

A review of recent progress in heterogeneous silicon tandem solar cells

Science.gov (United States)

Yamaguchi, Masafumi; Lee, Kan-Hua; Araki, Kenji; Kojima, Nobuaki

2018-04-01

Silicon solar cells are the most established solar cell technology and are expected to dominate the market in the near future. As state-of-the-art silicon solar cells are approaching the Shockley-Queisser limit, stacking silicon solar cells with other photovoltaic materials to form multi-junction devices is an obvious pathway to further raise the efficiency. However, many challenges stand in the way of fully realizing the potential of silicon tandem solar cells because heterogeneously integrating silicon with other materials often degrades their qualities. Recently, above or near 30% silicon tandem solar cell has been demonstrated, showing the promise of achieving high-efficiency and low-cost solar cells via silicon tandem. This paper reviews the recent progress of integrating solar cell with other mainstream solar cell materials. The first part of this review focuses on the integration of silicon with III-V semiconductor solar cells, which is a long-researched topic since the emergence of III-V semiconductors. We will describe the main approaches—heteroepitaxy, wafer bonding and mechanical stacking—as well as other novel approaches. The second part introduces the integration of silicon with polycrystalline thin-film solar cells, mainly perovskites on silicon solar cells because of its rapid progress recently. We will also use an analytical model to compare the material qualities of different types of silicon tandem solar cells and project their practical efficiency limits.

Integrated Microfluidic Gas Sensors for Water Monitoring

Science.gov (United States)

Zhu, L.; Sniadecki, N.; DeVoe, D. L.; Beamesderfer, M.; Semancik, S.; DeVoe, D. L.

2003-01-01

A silicon-based microhotplate tin oxide (SnO2) gas sensor integrated into a polymer-based microfluidic system for monitoring of contaminants in water systems is presented. This device is designed to sample a water source, control the sample vapor pressure within a microchannel using integrated resistive heaters, and direct the vapor past the integrated gas sensor for analysis. The sensor platform takes advantage of novel technology allowing direct integration of discrete silicon chips into a larger polymer microfluidic substrate, including seamless fluidic and electrical interconnects between the substrate and silicon chip.

Ultra-fast photon counting with a passive quenching silicon photomultiplier in the charge integration regime

Science.gov (United States)

Zhang, Guoqing; Lina, Liu

2018-02-01

An ultra-fast photon counting method is proposed based on the charge integration of output electrical pulses of passive quenching silicon photomultipliers (SiPMs). The results of the numerical analysis with actual parameters of SiPMs show that the maximum photon counting rate of a state-of-art passive quenching SiPM can reach ~THz levels which is much larger than that of the existing photon counting devices. The experimental procedure is proposed based on this method. This photon counting regime of SiPMs is promising in many fields such as large dynamic light power detection.

High-speed detection at two micrometres with monolithic silicon photodiodes

Science.gov (United States)

Ackert, Jason J.; Thomson, David J.; Shen, Li; Peacock, Anna C.; Jessop, Paul E.; Reed, Graham T.; Mashanovich, Goran Z.; Knights, Andrew P.

2015-06-01

With continued steep growth in the volume of data transmitted over optical networks there is a widely recognized need for more sophisticated photonics technologies to forestall a ‘capacity crunch’. A promising solution is to open new spectral regions at wavelengths near 2 μm and to exploit the long-wavelength transmission and amplification capabilities of hollow-core photonic-bandgap fibres and the recently available thulium-doped fibre amplifiers. To date, photodetector devices for this window have largely relied on III-V materials or, where the benefits of integration with silicon photonics are sought, GeSn alloys, which have been demonstrated thus far with only limited utility. Here, we describe a silicon photodiode operating at 20 Gbit s-1 in this wavelength region. The detector is compatible with standard silicon processing and is integrated directly with silicon-on-insulator waveguides, which suggests future utility in silicon-based mid-infrared integrated optics for applications in communications.

Carbon nanotube network-silicon oxide non-volatile switches.

Science.gov (United States)

Liao, Albert D; Araujo, Paulo T; Xu, Runjie; Dresselhaus, Mildred S

2014-12-08

The integration of carbon nanotubes with silicon is important for their incorporation into next-generation nano-electronics. Here we demonstrate a non-volatile switch that utilizes carbon nanotube networks to electrically contact a conductive nanocrystal silicon filament in silicon dioxide. We form this device by biasing a nanotube network until it physically breaks in vacuum, creating the conductive silicon filament connected across a small nano-gap. From Raman spectroscopy, we observe coalescence of nanotubes during breakdown, which stabilizes the system to form very small gaps in the network~15 nm. We report that carbon nanotubes themselves are involved in switching the device to a high resistive state. Calculations reveal that this switching event occurs at ~600 °C, the temperature associated with the oxidation of nanotubes. Therefore, we propose that, in switching to a resistive state, the nanotube oxidizes by extracting oxygen from the substrate.

Fifth workshop on the role of impurities and defects in silicon device processing. Extended abstracts

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.L.; Luque, A.; Sopori, B.; Swanson, D.; Gee, J.; Kalejs, J.; Jastrzebski, L.; Tan, T.

1995-08-01

This workshop dealt with engineering aspects and material properties of silicon electronic devices. Crystalline silicon growth, modeling, and properties are discussed in general and as applied to solar cells. Topics considered in discussions of silicon growth include: casting, string ribbons, Al backside contacts, ion implantation, gettering, passivation, and ultrasound treatments. Properties studies include: Electronic properties of defects and impurities, dopant and carrier concentrations, structure and bonding, nitrogen effects, degradation of bulk diffusion length, and recombination parameters. Individual papers from the workshop are indexed separately on the Energy Data Bases.

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Mode-locked silicon evanescent lasers.

Science.gov (United States)

Koch, Brian R; Fang, Alexander W; Cohen, Oded; Bowers, John E

2007-09-03

We demonstrate electrically pumped lasers on silicon that produce pulses at repetition rates up to 40 GHz. The mode locked lasers generate 4 ps pulses with low jitter and extinction ratios above 18 dB, making them suitable for data and telecommunication transmitters and for clock generation and distribution. Results of both passive and hybrid mode locking are discussed. This type of device could enable new silicon based integrated technologies, such as optical time division multiplexing (OTDM), wavelength division multiplexing (WDM), and optical code division multiple access (OCDMA).

Development and characterisation of silicon photomultipliers with bulk-integrated quench resistors for future applications in particle and astroparticle physics

International Nuclear Information System (INIS)

Jendrysik, Christian

2014-01-01

This thesis deals with the development and characterisation of a novel silicon photomultiplier concept with bulk-integrated quench resistors. The approach allows the realisation of a free entrance window and high fill factors, which leads to an improvement of the detection efficiency. With first prototype productions a proof of concept was possible. A full characterisation provided promising results, in particular with respect to the photon detection efficiency. By customising the simulation tools, a reliable description of the devices was achieved. In addition, conceptual studies of the next device generation demonstrated the possibility of single cell readout, expanding the application range of those detectors to particle tracking.

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

International Nuclear Information System (INIS)

Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

2013-01-01

Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

Science.gov (United States)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices

International Nuclear Information System (INIS)

Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.

2004-01-01

Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

Science.gov (United States)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

All-(111) surface silicon nanowire field effect transistor devices: Effects of surface preparations

NARCIS (Netherlands)

Masood, M.N.; Carlen, Edwin; van den Berg, Albert

2014-01-01

Etching/hydrogen termination of All-(111) surface silicon nanowire field effect (SiNW-FET) devices developed by conventional photolithography and plane dependent wet etchings is studied with X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM) and

Enhanced Electroluminescence from Silicon Quantum Dots Embedded in Silicon Nitride Thin Films Coupled with Gold Nanoparticles in Light Emitting Devices

Directory of Open Access Journals (Sweden)

Ana Luz Muñoz-Rosas

2018-03-01

Full Text Available Nowadays, the use of plasmonic metal layers to improve the photonic emission characteristics of several semiconductor quantum dots is a booming tool. In this work, we report the use of silicon quantum dots (SiQDs embedded in a silicon nitride thin film coupled with an ultra-thin gold film (AuNPs to fabricate light emitting devices. We used the remote plasma enhanced chemical vapor deposition technique (RPECVD in order to grow two types of silicon nitride thin films. One with an almost stoichiometric composition, acting as non-radiative spacer; the other one, with a silicon excess in its chemical composition, which causes the formation of silicon quantum dots imbibed in the silicon nitride thin film. The ultra-thin gold film was deposited by the direct current (DC-sputtering technique, and an aluminum doped zinc oxide thin film (AZO which was deposited by means of ultrasonic spray pyrolysis, plays the role of the ohmic metal-like electrode. We found that there is a maximum electroluminescence (EL enhancement when the appropriate AuNPs-spacer-SiQDs configuration is used. This EL is achieved at a moderate turn-on voltage of 11 V, and the EL enhancement is around four times bigger than the photoluminescence (PL enhancement of the same AuNPs-spacer-SiQDs configuration. From our experimental results, we surmise that EL enhancement may indeed be due to a plasmonic coupling. This kind of silicon-based LEDs has the potential for technology transfer.

Monolithic nanoscale photonics-electronics integration in silicon and other group IV elements

CERN Document Server

Radamson, Henry

2014-01-01

Silicon technology is evolving rapidly, particularly in board-to-board or chip-to chip applications. Increasingly, the electronic parts of silicon technology will carry out the data processing, while the photonic parts take care of the data communication. For the first time, this book describes the merging of photonics and electronics in silicon and other group IV elements. It presents the challenges, the limitations, and the upcoming possibilities of these developments. The book describes the evolution of CMOS integrated electronics, status and development, and the fundamentals of silicon p

Analysis of quantum ballistic electron transport in ultrasmall silicon devices including space-charge and geometric effects

Science.gov (United States)

Laux, S. E.; Kumar, A.; Fischetti, M. V.

2004-05-01

A two-dimensional device simulation program which self consistently solves the Schrödinger and Poisson equations with current flow is described in detail. Significant approximations adopted in this work are the absence of scattering and a simple six-valley, parabolic band structure for silicon. A modified version of the quantum transmitting boundary method is used to describe open boundary conditions permitting current flow in device solutions far from equilibrium. The continuous energy spectrum of the system is discretized by temporarily imposing two different forms of closed boundary conditions, resulting in energies which sample the density-of-states and establish the wave function normalization conditions. These standing wave solutions ("normal modes") are decomposed into their traveling wave constituents, each of which represents injection from only one of the open boundary contacts ("traveling eigencomponents"). These current-carrying states are occupied by a drifted Fermi distribution associated with their injecting contact and summed to form the electron density in the device. Holes are neglected in this calculation. The Poisson equation is solved on the same finite element computational mesh as the Schrödinger equation; devices of arbitrary geometry can be modeled. Computational performance of the program including characterization of a "Broyden+Newton" algorithm employed in the iteration for self consistency is described. Device results are presented for a narrow silicon resonant tunneling diode (RTD) and many variants of idealized silicon double-gate field effect transistors (DGFETs). The RTD results show two resonant conduction peaks, each of which demonstrates hysteresis. Three 7.5 nm channel length DGFET structures with identical intrinsic device configurations but differing access geometries (straight, taper and "dog bone") are studied and found to have differing current flows owing to quantum-mechanical reflection in their access regions

Nonclassical light sources for silicon photonics

Science.gov (United States)

Bajoni, Daniele; Galli, Matteo

2017-09-01

Quantum photonics has recently attracted a lot of attention for its disruptive potential in emerging technologies like quantum cryptography, quantum communication and quantum computing. Driven by the impressive development in nanofabrication technologies and nanoscale engineering, silicon photonics has rapidly become the platform of choice for on-chip integration of high performing photonic devices, now extending their functionalities towards quantum-based applications. Focusing on quantum Information Technology (qIT) as a key application area, we review recent progress in integrated silicon-based sources of nonclassical states of light. We assess the state of the art in this growing field and highlight the challenges that need to be overcome to make quantum photonics a reliable and widespread technology.

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Roadmap for integration of InP based photonics and silicon electronics

NARCIS (Netherlands)

Williams, K.A.

2015-01-01

We identify the synergies and a roadmap for the intimate integration of InP photonic integrated circuits and Silicon electronic ICs using wafer-scale processes. Advantages are foreseen in terms of bandwidth, energy savings and package simplification.

A Novel Silicon Micromachined Integrated MCM Thermal Management System

Science.gov (United States)

Kazmierczak, M. J.; Henderson, H. T.; Gerner, F. M.

1997-01-01

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high

Simultaneous optical and electrical modeling of plasmonic light trapping in thin-film amorphous silicon photovoltaic devices

Science.gov (United States)

Gandhi, Keyur K.; Nejim, Ahmed; Beliatis, Michail J.; Mills, Christopher A.; Henley, Simon J.; Silva, S. Ravi P.

2015-01-01

Rapid prototyping of photovoltaic (PV) cells requires a method for the simultaneous simulation of the optical and electrical characteristics of the device. The development of nanomaterial-enabled PV cells only increases the complexity of such simulations. Here, we use a commercial technology computer aided design (TCAD) software, Silvaco Atlas, to design and model plasmonic gold nanoparticles integrated in optoelectronic device models of thin-film amorphous silicon (a-Si:H) PV cells. Upon illumination with incident light, we simulate the optical and electrical properties of the cell simultaneously and use the simulation to produce current-voltage (J-V) and external quantum efficiency plots. Light trapping due to light scattering and localized surface plasmon resonance interactions by the nanoparticles has resulted in the enhancement of both the optical and electrical properties due to the reduction in the recombination rates in the photoactive layer. We show that the device performance of the modeled plasmonic a-Si:H PV cells depends significantly on the position and size of the gold nanoparticles, which leads to improvements either in optical properties only, or in both optical and electrical properties. The model provides a route to optimize the device architecture by simultaneously optimizing the optical and electrical characteristics, which leads to a detailed understanding of plasmonic PV cells from a design perspective and offers an advanced tool for rapid device prototyping.

An innovative large scale integration of silicon nanowire-based field effect transistors

Science.gov (United States)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Silicone metalization

Energy Technology Data Exchange (ETDEWEB)

Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

2008-12-09

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Silicon Integrated Dual-Mode Interferometer with Differential Outputs

Directory of Open Access Journals (Sweden)

Niklas Hoppe

2017-09-01

Full Text Available The dual-mode interferometer (DMI is an attractive alternative to Mach-Zehnder interferometers for sensor purposes, achieving sensitivities to refractive index changes close to state-of-the-art. Modern designs on silicon-on-insulator (SOI platforms offer thermally stable and compact devices with insertion losses of less than 1 dB and high extinction ratios. Compact arrays of multiple DMIs in parallel are easy to fabricate due to the simple structure of the DMI. In this work, the principle of operation of an integrated DMI with differential outputs is presented which allows the unambiguous phase shift detection with a single wavelength measurement, rather than using a wavelength sweep and evaluating the optical output power spectrum. Fluctuating optical input power or varying attenuation due to different analyte concentrations can be compensated by observing the sum of the optical powers at the differential outputs. DMIs with two differential single-mode outputs are fabricated in a 250 nm SOI platform, and corresponding measurements are shown to explain the principle of operation in detail. A comparison of DMIs with the conventional Mach-Zehnder interferometer using the same technology concludes this work.

Thermally controlled coupling of a rolled-up microtube integrated with a waveguide on a silicon electronic-photonic integrated circuit.

Science.gov (United States)

Zhong, Qiuhang; Tian, Zhaobing; Veerasubramanian, Venkat; Dastjerdi, M Hadi Tavakoli; Mi, Zetian; Plant, David V

2014-05-01

We report on the first experimental demonstration of the thermal control of coupling strength between a rolled-up microtube and a waveguide on a silicon electronic-photonic integrated circuit. The microtubes are fabricated by selectively releasing a coherently strained GaAs/InGaAs heterostructure bilayer. The fabricated microtubes are then integrated with silicon waveguides using an abruptly tapered fiber probe. By tuning the gap between the microtube and the waveguide using localized heaters, the microtube-waveguide evanescent coupling is effectively controlled. With heating, the extinction ratio of a microtube whispering-gallery mode changes over an 18 dB range, while the resonant wavelength remains approximately unchanged. Utilizing this dynamic thermal tuning effect, we realize coupling modulation of the microtube integrated with the silicon waveguide at 2 kHz with a heater voltage swing of 0-6 V.

Controlling the flow of light with silicon nanostructures

International Nuclear Information System (INIS)

Park, W

2010-01-01

Silicon is an important material for integrated photonics applications. High refractive index and transparency in the infrared region makes it an ideal platform to implement nanostructures for novel optical devices. We fabricated silicon photonic crystals and experimentally demonstrated negative refraction and self-collimation. We also used heterodyne near-field scanning optical microscope to directly visualize the anomalous wavefronts. When the periodicity is much smaller than wavelength, silicon photonic crystal can be described by the effective medium theory. By engineering effective refractive index with silicon nanorod size, we demonstrated an all-dielectric cloak structure which can hide objects in front of a highly reflecting plane. The work discussed in this review shows the powerful design flexibility and versatility of silicon nanostructures

Space and military radiation effects in silicon-on-insulator devices

International Nuclear Information System (INIS)

Schwank, J.R.

1996-09-01

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

Will silicon be the photonic material of the third millenium?

International Nuclear Information System (INIS)

Pavesi, L

2003-01-01

Silicon microphotonics, a technology which merges photonics and silicon microelectronic components, is rapidly evolving. Many different fields of application are emerging: transceiver modules for optical communication systems, optical bus systems for ULSI circuits, I/O stages for SOC, displays, .... In this review I will give a brief motivation for silicon microphotonics and try to give the state-of-the-art of this technology. The ingredient still lacking is the silicon laser: a review of the various approaches will be presented. Finally, I will try to draw some conclusions where silicon is predicted to be the material to achieve a full integration of electronic and optical devices. (topical review)

Second-harmonic generation in substoichiometric silicon nitride layers

Science.gov (United States)

Pecora, Emanuele; Capretti, Antonio; Miano, Giovanni; Dal Negro, Luca

2013-03-01

Harmonic generation in optical circuits offers the possibility to integrate wavelength converters, light amplifiers, lasers, and multiple optical signal processing devices with electronic components. Bulk silicon has a negligible second-order nonlinear optical susceptibility owing to its crystal centrosymmetry. Silicon nitride has its place in the microelectronic industry as an insulator and chemical barrier. In this work, we propose to take advantage of silicon excess in silicon nitride to increase the Second Harmonic Generation (SHG) efficiency. Thin films have been grown by reactive magnetron sputtering and their nonlinear optical properties have been studied by femtosecond pumping over a wide range of excitation wavelengths, silicon nitride stoichiometry and thermal processes. We demonstrate SHG in the visible range (375 - 450 nm) using a tunable 150 fs Ti:sapphire laser, and we optimize the SH emission at a silicon excess of 46 at.% demonstrating a maximum SHG efficiency of 4x10-6 in optimized films. Polarization properties, generation efficiency, and the second order nonlinear optical susceptibility are measured for all the investigated samples and discussed in terms of an effective theoretical model. Our findings show that the large nonlinear optical response demonstrated in optimized Si-rich silicon nitride materials can be utilized for the engineering of nonlinear optical functions and devices on a Si chip.

Integrated lenses in polystyrene microfluidic devices

KAUST Repository

Fan, Yiqiang

2013-04-01

This paper reports a new method for integrating microlenses into microfluidic devices for improved observation. Two demonstration microfluidic devices were provided which were fabricated using this new technique. The integrated microlenses were fabricated using a free-surface thermo-compression molding method on a polystyrene (PS) sheet which was then bonded on top of microfluidic channels as a cover plate, with the convex microlenses providing a magnified image of the channel for the easier observation of the flow in the microchannels. This approach for fabricating the integrated microlens in microfluidic devices is rapid, low cost and without the requirement of cleanroom facilities. © 2013 IEEE.

High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

Directory of Open Access Journals (Sweden)

Xianshu eLuo

2015-04-01

Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

International Nuclear Information System (INIS)

Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

2014-01-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

Improved luminescence properties of nanocrystalline silicon based electroluminescent device by annealing

International Nuclear Information System (INIS)

Sato, Keisuke; Hirakuri, Kenji

2006-01-01

We report an annealing effect on electrical and luminescence properties of a red electroluminescent device consisting of nanocrystalline silicon (nc-Si). The red luminescence was generated by flowing the forward current into the device at a low threshold direct current (DC) forward voltage with a rise of annealing temperature up to 500 deg. C. Moreover, the luminescence of the device annealed at 500 deg. C was more intense than that of the device annealed at 200 deg. C or less under the same forward current density, because of the injection of a large quantity of carriers to the radiative recombination centers at the nc-Si surface vicinity. These were attained by a low resistivity of indium tin oxide (ITO) electrode and good contact at the ITO electrode/luminous layer interface region by the annealing treatment. The above results indicated that the annealing treatment of the device is effective for the realization of high luminance due to the improvement in the injection efficiency of carriers to the radiative recombination centers

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

Science.gov (United States)

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Thermoelectric characteristics of Pt-silicide/silicon multi-layer structured p-type silicon

International Nuclear Information System (INIS)

Choi, Wonchul; Jun, Dongseok; Kim, Soojung; Shin, Mincheol; Jang, Moongyu

2015-01-01

Electric and thermoelectric properties of silicide/silicon multi-layer structured devices were investigated with the variation of silicide/silicon heterojunction numbers from 3 to 12 layers. For the fabrication of silicide/silicon multi-layered structure, platinum and silicon layers are repeatedly sputtered on the (100) silicon bulk substrate and rapid thermal annealing is carried out for the silicidation. The manufactured devices show ohmic current–voltage (I–V) characteristics. The Seebeck coefficient of bulk Si is evaluated as 195.8 ± 15.3 μV/K at 300 K, whereas the 12 layered silicide/silicon multi-layer structured device is evaluated as 201.8 ± 9.1 μV/K. As the temperature increases to 400 K, the Seebeck coefficient increases to 237.2 ± 4.7 μV/K and 277.0 ± 1.1 μV/K for bulk and 12 layered devices, respectively. The increase of Seebeck coefficient in multi-layered structure is mainly attributed to the electron filtering effect due to the Schottky barrier at Pt-silicide/silicon interface. At 400 K, the thermal conductivity is reduced by about half of magnitude compared to bulk in multi-layered device which shows the efficient suppression of phonon propagation by using Pt-silicide/silicon hetero-junctions. - Highlights: • Silicide/silicon multi-layer structured is proposed for thermoelectric devices. • Electric and thermoelectric properties with the number of layer are investigated. • An increase of Seebeck coefficient is mainly attributed the Schottky barrier. • Phonon propagation is suppressed with the existence of Schottky barrier. • Thermal conductivity is reduced due to the suppression of phonon propagation

Silicon nanophotonics for scalable quantum coherent feedback networks

International Nuclear Information System (INIS)

Sarovar, Mohan; Brif, Constantin; Soh, Daniel B.S.; Cox, Jonathan; DeRose, Christopher T.; Camacho, Ryan; Davids, Paul

2016-01-01

The emergence of coherent quantum feedback control (CQFC) as a new paradigm for precise manipulation of dynamics of complex quantum systems has led to the development of efficient theoretical modeling and simulation tools and opened avenues for new practical implementations. This work explores the applicability of the integrated silicon photonics platform for implementing scalable CQFC networks. If proven successful, on-chip implementations of these networks would provide scalable and efficient nanophotonic components for autonomous quantum information processing devices and ultra-low-power optical processing systems at telecommunications wavelengths. We analyze the strengths of the silicon photonics platform for CQFC applications and identify the key challenges to both the theoretical formalism and experimental implementations. In particular, we determine specific extensions to the theoretical CQFC framework (which was originally developed with bulk-optics implementations in mind), required to make it fully applicable to modeling of linear and nonlinear integrated optics networks. We also report the results of a preliminary experiment that studied the performance of an in situ controllable silicon nanophotonic network of two coupled cavities and analyze the properties of this device using the CQFC formalism. (orig.)

Silicon nanophotonics for scalable quantum coherent feedback networks

Energy Technology Data Exchange (ETDEWEB)

Sarovar, Mohan; Brif, Constantin [Sandia National Laboratories, Livermore, CA (United States); Soh, Daniel B.S. [Sandia National Laboratories, Livermore, CA (United States); Stanford University, Edward L. Ginzton Laboratory, Stanford, CA (United States); Cox, Jonathan; DeRose, Christopher T.; Camacho, Ryan; Davids, Paul [Sandia National Laboratories, Albuquerque, NM (United States)

2016-12-15

The emergence of coherent quantum feedback control (CQFC) as a new paradigm for precise manipulation of dynamics of complex quantum systems has led to the development of efficient theoretical modeling and simulation tools and opened avenues for new practical implementations. This work explores the applicability of the integrated silicon photonics platform for implementing scalable CQFC networks. If proven successful, on-chip implementations of these networks would provide scalable and efficient nanophotonic components for autonomous quantum information processing devices and ultra-low-power optical processing systems at telecommunications wavelengths. We analyze the strengths of the silicon photonics platform for CQFC applications and identify the key challenges to both the theoretical formalism and experimental implementations. In particular, we determine specific extensions to the theoretical CQFC framework (which was originally developed with bulk-optics implementations in mind), required to make it fully applicable to modeling of linear and nonlinear integrated optics networks. We also report the results of a preliminary experiment that studied the performance of an in situ controllable silicon nanophotonic network of two coupled cavities and analyze the properties of this device using the CQFC formalism. (orig.)

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-08-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

Science.gov (United States)

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

Potassium ions in SiO2: electrets for silicon surface passivation

Science.gov (United States)

Bonilla, Ruy S.; Wilshaw, Peter R.

2018-01-01

This manuscript reports an experimental and theoretical study of the transport of potassium ions in thin silicon dioxide films. While alkali contamination was largely researched in the context of MOSFET instability, recent reports indicate that potassium ions can be embedded into oxide films to produce dielectric materials with permanent electric charge, also known as electrets. These electrets are integral to a number of applications, including the passivation of silicon surfaces for optoelectronic devices. In this work, electric field assisted migration of ions is used to rapidly drive K+ into SiO2 and produce effective passivation of silicon surfaces. Charge concentrations of up to ~5  ×  1012 e cm-2 have been achieved. This charge was seen to be stable for over 1500 d, with decay time constants as high as 17 000 d, producing an effectively passivated oxide-silicon interface with SRV  industrial manufacture of silicon optoelectronic devices.

Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits.

Science.gov (United States)

Shang, Kuanping; Pathak, Shibnath; Guan, Binbin; Liu, Guangyao; Yoo, S J B

2015-08-10

We design, fabricate, and demonstrate a silicon nitride (Si(3)N(4)) multilayer platform optimized for low-loss and compact multilayer photonic integrated circuits. The designed platform, with 200 nm thick waveguide core and 700 nm interlayer gap, is compatible for active thermal tuning and applicable to realizing compact photonic devices such as arrayed waveguide gratings (AWGs). We achieve ultra-low loss vertical couplers with 0.01 dB coupling loss, multilayer crossing loss of 0.167 dB at 90° crossing angle, 50 μm bending radius, 100 × 2 μm(2) footprint, lateral misalignment tolerance up to 400 nm, and less than -52 dB interlayer crosstalk at 1550 nm wavelength. Based on the designed platform, we demonstrate a 27 × 32 × 2 multilayer star coupler.

Silicon photonic integration in telecommunications

Directory of Open Access Journals (Sweden)

Christopher Richard Doerr

2015-08-01

Full Text Available Silicon photonics is the guiding of light in a planar arrangement of silicon-based materials to perform various functions. We focus here on the use of silicon photonics to create transmitters and receivers for fiber-optic telecommunications. As the need to squeeze more transmission into a given bandwidth, a given footprint, and a given cost increases, silicon photonics makes more and more economic sense.

SILICON CARBIDE MICRO-DEVICES FOR COMBUSTION GAS SENSING UNDER HARSH CONDITIONS

Energy Technology Data Exchange (ETDEWEB)

Ruby N. Ghosh; Peter Tobias; Roger G. Tobin

2004-04-01

A sensor based on the wide bandgap semiconductor, silicon carbide (SiC), has been developed for the detection of combustion products in power plant environments. The sensor is a catalytic gate field effect device that can detect hydrogen containing species in chemically reactive, high temperature environments. Robust metallization and electrical contacting techniques have been developed for device operation at elevated temperatures. To characterize the time response of the sensor responses in the millisecond range, a conceptually new apparatus has been built. Software has been developed to cope with the requirements of fast sensor control and data recording. In addition user friendly software has been developed to facilitate use of the SiC sensors for industrial process control applications.

Gamma non-ionizing energy loss: Comparison with the damage factor in silicon devices

Science.gov (United States)

El Allam, E.; Inguimbert, C.; Meulenberg, A.; Jorio, A.; Zorkani, I.

2018-03-01

The concept of non-ionizing energy loss (NIEL) has been demonstrated to be a successful approach to describe the displacement damage effects in silicon materials and devices. However, some discrepancies exist in the literature between experimental damage factors and theoretical NIELs. 60Co gamma rays having a low NIEL are an interesting particle source that can be used to validate the NIEL scaling approach. This paper presents different 60Co gamma ray NIEL values for silicon targets. They are compared with the radiation-induced increase in the thermal generation rate of carriers per unit fluence. The differences between the different models, including one using molecular dynamics, are discussed.

Radiation Hardness tests with neutron flux on different Silicon photomultiplier devices

Science.gov (United States)

Cattaneo, P. W.; Cervi, T.; Menegolli, A.; Oddone, M.; Prata, M.; Prata, M. C.; Rossella, M.

2017-07-01

Radiation hardness is an important requirement for solid state readout devices operating in high radiation environments common in particle physics experiments. The MEG II experiment, at PSI, Switzerland, investigates the forbidden decay μ+ → e+ γ. Exploiting the most intense muon beam of the world. A significant flux of non-thermal neutrons (kinetic energy Ek>= 0.5 MeV) is present in the experimental hall produced along the beam-line and in the hall itself. We present the effects of neutron fluxes comparable to the MEG II expected doses on several Silicon Photomultiplier (SiPMs). The tested models are: AdvanSiD ASD-NUV3S-P50 (used in MEG II experiment), AdvanSiD ASD-NUV3S-P40, AdvanSiD ASD-RGB3S-P40, Hamamatsu and Excelitas C30742-33-050-X. The neutron source is the thermal Sub-critical Multiplication complex (SM1) moderated with water, located at the University of Pavia (Italy). We report the change of SiPMs most important electric parameters: dark current, dark pulse frequency, gain, direct bias resistance, as a function of the integrated neutron fluency.

Modeling optical transmissivity of graphene grate in on-chip silicon photonic device

Directory of Open Access Journals (Sweden)

Iraj S. Amiri

2018-06-01

Full Text Available A three-dimensional (3-D finite-difference-time-domain (FDTD analysis was used to simulate a silicon photonic waveguide. We have calculated power and transmission of the graphene used as single or multilayers to study the light transmission behavior. A new technique has been developed to define the straight silicon waveguide integrated with grate graphene layer. The waveguide has a variable grate spacing to be filled by the graphene layer. The number of graphene atomic layers varies between 100 and 1000 (or 380 nm and 3800 nm, the transmitted power obtained varies as ∼30% and ∼80%. The ∼99%, blocking of the light was occurred in 10,000 (or 38,000 nm atomic layers of the graphene grate. Keywords: Optical waveguide, Silicon waveguide, Grate, Graphene, Optical transmissivity

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

Science.gov (United States)

Marrs, Michael A; Raupp, Gregory B

2016-07-26

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm² and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Novel technique for reliability testing of silicon integrated circuits

NARCIS (Netherlands)

Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

2001-01-01

We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

Infrared transparent graphene heater for silicon photonic integrated circuits.

Science.gov (United States)

Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

2016-04-18

Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

Radio frequency siliconization: An approach to the coating for the future large superconducting fusion devices

International Nuclear Information System (INIS)

Li, J.; Zhao, Y.P.; Wan, B.N.; Gong, X.Z.; Zhen, M.; Gu, X.M.; Zhang, X.D.; Luo, J.R.; Wan, Y.X.; Xie, J.K.; Li, C.F.; Chen, J.L.; Toi, K.; Noda, N.; Watari, T.

2001-01-01

Radio frequency (rf) siliconization has been carried out on the HT-7 superconducting tokamak in the presence of a high magnetic field, which is a try on superconducting tokamaks. Three different procedures of rf siliconization have been tested and a very promising method to produce high quality silicon films was found after comparing the film properties and plasma performance produced by these three different procedures. The Si/C films are amorphous, semitransparent, and homogeneous throughout the layer and adhere firmly to all the substrates. The advantages of silicon atoms as a powerful radiator and a good oxygen getter have been proved. An outstanding merit of rf siliconization to superconducting devices is its fast recovery after a serious degradation of the condition due to the leakage of air to good wall conditions. A wider stable operation region has been obtained and plasma performance is improved immediately after each siliconization due to significant reduction of impurities. Energy confinement time increases more than 50% and particle confinement time increases by a factor of 2. The lifetime of the silicon film is more than 400 standard ohmic heated plasma discharges. Simulation shows that the confinement improvement is due to the reduction of the electron thermal diffusivity in the outer region of the plasma

Passive Temperature Stabilization of Silicon Photonic Devices Using Liquid Crystals

Directory of Open Access Journals (Sweden)

Joanna Ptasinski

2014-03-01

Full Text Available In this work we explore the negative thermo-optic properties of liquid crystal claddings for passive temperature stabilization of silicon photonic integrated circuits. Photonic circuits are playing an increasing role in communications and computing, but they suffer from temperature dependent performance variation. Most existing techniques aimed at compensation of thermal effects rely on power hungry Joule heating. We show that integrating a liquid crystal cladding helps to minimize the effects of a temperature dependent drift. The advantage of liquid crystals lies in their high negative thermo-optic coefficients in addition to low absorption at the infrared wavelengths.

A simple and cost-effective method for fabrication of integrated electronic-microfluidic devices using a laser-patterned PDMS layer

KAUST Repository

Li, Ming

2011-12-03

We report a simple and cost-effective method for fabricating integrated electronic-microfluidic devices with multilayer configurations. A CO 2 laser plotter was employed to directly write patterns on a transferred polydimethylsiloxane (PDMS) layer, which served as both a bonding and a working layer. The integration of electronics in microfluidic devices was achieved by an alignment bonding of top and bottom electrode-patterned substrates fabricated with conventional lithography, sputtering and lift-off techniques. Processes of the developed fabrication method were illustrated. Major issues associated with this method as PDMS surface treatment and characterization, thickness-control of the transferred PDMS layer, and laser parameters optimization were discussed, along with the examination and testing of bonding with two representative materials (glass and silicon). The capability of this method was further demonstrated by fabricating a microfluidic chip with sputter-coated electrodes on the top and bottom substrates. The device functioning as a microparticle focusing and trapping chip was experimentally verified. It is confirmed that the proposed method has many advantages, including simple and fast fabrication process, low cost, easy integration of electronics, strong bonding strength, chemical and biological compatibility, etc. © Springer-Verlag 2011.

Monolithic integration of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Batignani, Giovanni; Boscardin, Maurizio; Bosisio, Luciano; Gregori, Paolo; Pancheri, Lucio; Piemonte, Claudio; Ratti, Lodovico; Verzellesi, Giovanni; Zorzi, Nicola

2007-01-01

We report on the most recent results from an R and D activity aimed at the development of silicon radiation detectors with embedded front-end electronics. The key features of the fabrication technology and the available active devices are described. Selected results from the characterization of transistors and test structures are presented and discussed, and the considered application fields are addressed

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

International Nuclear Information System (INIS)

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

2014-01-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

Integrating a Silicon Solar Cell with a Triboelectric Nanogenerator via a Mutual Electrode for Harvesting Energy from Sunlight and Raindrops.

Science.gov (United States)

Liu, Yuqiang; Sun, Na; Liu, Jiawei; Wen, Zhen; Sun, Xuhui; Lee, Shuit-Tong; Sun, Baoquan

2018-03-27

Solar cells, as promising devices for converting light into electricity, have a dramatically reduced performance on rainy days. Here, an energy harvesting structure that integrates a solar cell and a triboelectric nanogenerator (TENG) device is built to realize power generation from both sunlight and raindrops. A heterojunction silicon (Si) solar cell is integrated with a TENG by a mutual electrode of a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) film. Regarding the solar cell, imprinted PEDOT:PSS is used to reduce light reflection, which leads to an enhanced short-circuit current density. A single-electrode-mode water-drop TENG on the solar cell is built by combining imprinted polydimethylsiloxane (PDMS) as a triboelectric material combined with a PEDOT:PSS layer as an electrode. The increasing contact area between the imprinted PDMS and water drops greatly improves the output of the TENG with a peak short-circuit current of ∼33.0 nA and a peak open-circuit voltage of ∼2.14 V, respectively. The hybrid energy harvesting system integrated electrode configuration can combine the advantages of high current level of a solar cell and high voltage of a TENG device, promising an efficient approach to collect energy from the environment in different weather conditions.

Compact high-efficiency vortex beam emitter based on a silicon photonics micro-ring

DEFF Research Database (Denmark)

Li, Shimao; Ding, Yunhong; Guan, Xiaowei

2018-01-01

Photonic integrated devices that emit vortex beam carrying orbital angular momentum are becoming key components for multiple applications. Here we propose and demonstrate a high-efficiency vortex beam emitter based on a silicon micro-ring resonator integrated with a metal mirror. Such a compact...

Silicon light-emitting diodes and lasers photon breeding devices using dressed photons

CERN Document Server

Ohtsu, Motoichi

2016-01-01

This book focuses on a novel phenomenon named photon breeding. It is applied to realizing light-emitting diodes and lasers made of indirect-transition-type silicon bulk crystals in which the light-emission principle is based on dressed photons. After presenting physical pictures of dressed photons and dressed-photon phonons, the principle of light emission by using dressed-photon phonons is reviewed. A novel phenomenon named photon breeding is also reviewed. Next, the fabrication and operation of light emitting diodes and lasers are described The role of coherent phonons in these devices is discussed. Finally, light-emitting diodes using other relevant crystals are described and other relevant devices are also reviewed.

3D Integration for Wireless Multimedia

Science.gov (United States)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology

Promising silicones modified with cationic biocides for the development of antimicrobial medical devices.

Science.gov (United States)

Ghamrawi, Sarah; Bouchara, Jean-Philippe; Tarasyuk, Oksana; Rogalsky, Sergiy; Lyoshina, Lyudmila; Bulko, Olga; Bardeau, Jean-François

2017-06-01

We have tested silicones containing 2% or 5% of the cationic biocides polyhexamethylene guanidine dodecylbenzenesulfonate (PHMG-DBS), 1-octyl-3-methylimidazolium tetrafluoroborate (OMIM-BF 4 ) or 1-dodecyl-3-methylimidazolium tetrafluoroborate (DMIM-BF 4 ) against the major relevant bacterial and yeast species in health care-associated infections (HCAI). Study conducted according to the international standard ISO 22196 revealed that silicones containing 2% or 5% DMIM-BF 4 or 5% PHMG-DBS presented the highest antimicrobial activity, leading to a logarithmic growth reduction of 3.03 to 6.46 and 3.65 to 4.85 depending on the bacterial or fungal species. Heat-pretreated silicones containing 2% DMIM-BF 4 kept a high activity, with at least a 3-log reduction in bacterial growth, except against P. aeruginosa where there was only a 1.1-log reduction. After 33days, the release ratio of cationic biocide from silicone films containing 5% of DMIM-BF 4 was found to be 5.6% in pure water and 1.9% in physiological saline solution, respectively. No leaching of PHMG-DBS polymeric biocide was detected under the same conditions. These results demonstrate unambiguously that silicones containing 2% DMIM-BF 4 or 5% PHMG-DBS present high antimicrobial activity, as well as high leaching resistance and therefore may be good candidates for the development of safer medical devices. Copyright © 2017 Elsevier B.V. All rights reserved.

Synthesis, Characterization and Optical Constants of Silicon Oxycarbide

Directory of Open Access Journals (Sweden)

Memon Faisal Ahmed

2017-01-01

Full Text Available High refractive index glasses are preferred in integrated photonics applications to realize higher integration scale of passive devices. With a refractive index that can be tuned between SiO2 (1.45 and a-SiC (3.2, silicon oxycarbide SiOC offers this flexibility. In the present work, silicon oxycarbide thin films from 0.1 – 2.0 μm thickness are synthesized by reactive radio frequency magnetron sputtering a silicon carbide SiC target in a controlled argon and oxygen environment. The refractive index n and material extinction coefficient k of the silicon oxycarbide films are acquired with variable angle spectroscopic ellipsometry over the UV-Vis-NIR wavelength range. Keeping argon and oxygen gases in the constant ratio, the refractive index n is found in the range from 1.41 to 1.93 at 600 nm which is almost linearly dependent on RF power of sputtering. The material extinction coefficient k has been estimated to be less than 10-4 for the deposited silicon oxycarbide films in the visible and near-infrared wavelength regions. Morphological and structural characterizations with SEM and XRD confirms the amorphous phase of the SiOC films.

ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

Science.gov (United States)

Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

Integration of silicon-based neural probes and micro-drive arrays for chronic recording of large populations of neurons in behaving animals.

Science.gov (United States)

Michon, Frédéric; Aarts, Arno; Holzhammer, Tobias; Ruther, Patrick; Borghs, Gustaaf; McNaughton, Bruce; Kloosterman, Fabian

2016-08-01

Understanding how neuronal assemblies underlie cognitive function is a fundamental question in system neuroscience. It poses the technical challenge to monitor the activity of populations of neurons, potentially widely separated, in relation to behaviour. In this paper, we present a new system which aims at simultaneously recording from a large population of neurons from multiple separated brain regions in freely behaving animals. The concept of the new device is to combine the benefits of two existing electrophysiological techniques, i.e. the flexibility and modularity of micro-drive arrays and the high sampling ability of electrode-dense silicon probes. Newly engineered long bendable silicon probes were integrated into a micro-drive array. The resulting device can carry up to 16 independently movable silicon probes, each carrying 16 recording sites. Populations of neurons were recorded simultaneously in multiple cortical and/or hippocampal sites in two freely behaving implanted rats. Current approaches to monitor neuronal activity either allow to flexibly record from multiple widely separated brain regions (micro-drive arrays) but with a limited sampling density or to provide denser sampling at the expense of a flexible placement in multiple brain regions (neural probes). By combining these two approaches and their benefits, we present an alternative solution for flexible and simultaneous recordings from widely distributed populations of neurons in freely behaving rats.

Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Science.gov (United States)

Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

2015-02-01

We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

Ferroelectric and piezoelectric properties of epitaxial PZT films and devices on silicon

NARCIS (Netherlands)

Nguyen, Duc Minh

2010-01-01

In this thesis, the integration of lead zirconate titanate Pb(Zr,Ti)O3 (PZT) thin films into piezoelectric microelectromechanical systems (MEMS) based on silicon is studied. In these structures, all epitaxial oxide layers (thin film/electrode/buffer-layer(s)) were deposited by pulsed laser

High-speed all-optical logic inverter based on stimulated Raman scattering in silicon nanocrystal.

Science.gov (United States)

Sen, Mrinal; Das, Mukul K

2015-11-01

In this paper, we propose a new device architecture for an all-optical logic inverter (NOT gate), which is cascadable with a similar device. The inverter is based on stimulated Raman scattering in silicon nanocrystal waveguides, which are embedded in a silicon photonic crystal structure. The Raman response function of silicon nanocrystal is evaluated to explore the transfer characteristic of the inverter. A maximum product criterion for the noise margin is taken to analyze the cascadability of the inverter. The time domain response of the inverter, which explores successful inversion operation at 100 Gb/s, is analyzed. Propagation delay of the inverter is on the order of 5 ps, which is less than the delay in most of the electronic logic families as of today. Overall dimension of the device is around 755  μm ×15  μm, which ensures integration compatibility with the matured silicon industry.

Active phase correction of high resolution silicon photonic arrayed waveguide gratings.

Science.gov (United States)

Gehl, M; Trotter, D; Starbuck, A; Pomerene, A; Lentine, A L; DeRose, C

2017-03-20

Arrayed waveguide gratings provide flexible spectral filtering functionality for integrated photonic applications. Achieving narrow channel spacing requires long optical path lengths which can greatly increase the footprint of devices. High index contrast waveguides, such as those fabricated in silicon-on-insulator wafers, allow tight waveguide bends which can be used to create much more compact designs. Both the long optical path lengths and the high index contrast contribute to significant optical phase error as light propagates through the device. Therefore, silicon photonic arrayed waveguide gratings require active or passive phase correction following fabrication. Here we present the design and fabrication of compact silicon photonic arrayed waveguide gratings with channel spacings of 50, 10 and 1 GHz. The largest device, with 11 channels of 1 GHz spacing, has a footprint of only 1.1 cm2. Using integrated thermo-optic phase shifters, the phase error is actively corrected. We present two methods of phase error correction and demonstrate state-of-the-art cross-talk performance for high index contrast arrayed waveguide gratings. As a demonstration of possible applications, we perform RF channelization with 1 GHz resolution. Additionally, we generate unique spectral filters by applying non-zero phase offsets calculated by the Gerchberg Saxton algorithm.

A multilayered integrated sensor for three-dimensional, micro total analysis systems

International Nuclear Information System (INIS)

Xiao, Jing; Song, Fuchuan; Seo, Sang-Woo

2013-01-01

This paper presents a layer-by-layer integration approach of different functional devices and demonstrates a heterogeneously integrated optical sensor featuring a micro-ring resonator and a high-speed thin-film InGaAs-based photodetector co-integrated with a microfluidic droplet generation device. A thin optical device structure allows a seamless integration with other polymer-based devices on a silicon platform. The integrated sensor successfully demonstrates its transient measurement capability of two-phase liquid flow in a microfluidic droplet generation device. The proposed approach represents an important step toward fully integrated micro total analysis systems. (paper)

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

Science.gov (United States)

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-12-01

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

Enhanced vapour sensing using silicon nanowire devices coated with Pt nanoparticle functionalized porous organic frameworks

KAUST Repository

Cao, Anping

2018-03-09

Recently various porous organic frameworks (POFs, crystalline or amorphous materials) have been discovered, and used for a wide range of applications, including molecular separations and catalysis. Silicon nanowires (SiNWs) have been extensively studied for diverse applications, including as transistors, solar cells, lithium ion batteries and sensors. Here we demonstrate the functionalization of SiNW surfaces with POFs and explore its effect on the electrical sensing properties of SiNW-based devices. The surface modification by POFs was easily achieved by polycondensation on amine-modified SiNWs. Platinum nanoparticles were formed in these POFs by impregnation with chloroplatinic acid followed by chemical reduction. The final hybrid system showed highly enhanced sensitivity for methanol vapour detection. We envisage that the integration of SiNWs with POF selector layers, loaded with different metal nanoparticles will open up new avenues, not only in chemical and biosensing, but also in separations and catalysis.

Silicon germanium mask for deep silicon etching

KAUST Repository

Serry, Mohamed

2014-07-29

Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF.sub.6/O.sub.2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from -80 degrees Celsius to -140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Silicon germanium mask for deep silicon etching

KAUST Repository

Serry, Mohamed; Rubin, Andrew; Refaat, Mohamed; Sedky, Sherif; Abdo, Mohammad

2014-01-01

Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF.sub.6/O.sub.2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from -80 degrees Celsius to -140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

High-dimensional quantum key distribution based on multicore fiber using silicon photonic integrated circuits

DEFF Research Database (Denmark)

Ding, Yunhong; Bacco, Davide; Dalgaard, Kjeld

2017-01-01

is intrinsically limited to 1 bit/photon. Here we propose and experimentally demonstrate, for the first time, a high-dimensional quantum key distribution protocol based on space division multiplexing in multicore fiber using silicon photonic integrated lightwave circuits. We successfully realized three mutually......-dimensional quantum states, and enables breaking the information efficiency limit of traditional quantum key distribution protocols. In addition, the silicon photonic circuits used in our work integrate variable optical attenuators, highly efficient multicore fiber couplers, and Mach-Zehnder interferometers, enabling...

Photoconductance-calibrated photoluminescence lifetime imaging of crystalline silicon

International Nuclear Information System (INIS)

Herlufsen, Sandra; Schmidt, Jan; Hinken, David; Bothe, Karsten; Brendel, Rolf

2008-01-01

We use photoluminescence (PL) measurements by a silicon charge-coupled device camera to generate high-resolution lifetime images of multicrystalline silicon wafers. Absolute values of the excess carrier density are determined by calibrating the PL image by means of contactless photoconductance measurements. The photoconductance setup is integrated in the camera-based PL setup and therefore identical measurement conditions are realised. We demonstrate the validity of this method by comparison with microwave-detected photoconductance decay measurements. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (Abstract Copyright [2008], Wiley Periodicals, Inc.)

Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

Energy Technology Data Exchange (ETDEWEB)

Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

2009-06-10

We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

Energy Technology Data Exchange (ETDEWEB)

Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

2014-05-15

The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

Strained Silicon Photonics

Directory of Open Access Journals (Sweden)

Ralf B. Wehrspohn

2012-05-01

Full Text Available A review of recent progress in the field of strained silicon photonics is presented. The application of strain to waveguide and photonic crystal structures can be used to alter the linear and nonlinear optical properties of these devices. Here, methods for the fabrication of strained devices are summarized and recent examples of linear and nonlinear optical devices are discussed. Furthermore, the relation between strain and the enhancement of the second order nonlinear susceptibility is investigated, which may enable the construction of optically active photonic devices made of silicon.

Silicon fiber with p-n junction

International Nuclear Information System (INIS)

Homa, D.; Cito, A.; Pickrell, G.; Hill, C.; Scott, B.

2014-01-01

In this study, we fabricated a p-n junction in a fiber with a phosphorous doped silicon core and fused silica cladding. The fibers were fabricated via a hybrid process of the core-suction and melt-draw techniques and maintained overall diameters ranging from 200 to 900 μm and core diameters of 20–800 μm. The p-n junction was formed by doping the fiber with boron and confirmed via the current-voltage characteristic. The demonstration of a p-n junction in a melt-drawn silicon core fiber paves the way for the seamless integration of optical and electronic devices in fibers.

Development of the external cooling device of increase the productivity of neutron-transmutation-doped silicon semiconductor (NTD-Si) (Joint research)

International Nuclear Information System (INIS)

Hirose, Akira; Wada, Shigeru; Sasajima, Fumio; Kusunoki, Tsuyoshi; Kameyama, Iwao; Aizawa, Ryouji; Kikuchi, Naoyuki

2007-01-01

Neutron-Transmutation-Doped Silicon Semiconductor (hereinafter referred as 'NTD-Si') is the best semiconductor for the power device. The needs of NTD-Si increase recently in proportion to the popularization of hybrid-cars. A fission research reactor, which is a steady state neutron source, is being expected as the best device to meet the needs. So far, we have reconsidered the existing approach which is employed for NTD-Si production works at the research reactors JRR-3, JRR-4 and JMTR of JAEA so as to meet the needs. As one of the effective measures, we found out that the productivity can be increased by incorporating a new device to cool down radioactivity of irradiated silicon ingots at the place outside the main stream from the loading of silicon ingots to the withdrawal of irradiated ingots to the existing JRR-3 Uniformity Irradiation System. Consequently, we developed and installed the device (hereinafter referred as 'external cooling device'). After an ingot was irradiated once, it is turned over manually and irradiated again in order to irradiate the ingot uniformly. With the conventional system, it was necessary to wait the radioactivity of ingot decrease less than the permissible level with holding the ingot in the irradiation equipment. It was effective to shorten the waiting period by using an external cooling device for production increase of NTD-Si. It is expected that the productivity of NTD-Si will be increased by using the external cooling device. This report mentions the design of the external cooling device and verification between its design specifications and the performance of the device completed. (author)

The mid-IR silicon photonics sensor platform (Conference Presentation)

Science.gov (United States)

Kimerling, Lionel; Hu, Juejun; Agarwal, Anuradha M.

2017-02-01

Advances in integrated silicon photonics are enabling highly connected sensor networks that offer sensitivity, selectivity and pattern recognition. Cost, performance and the evolution path of the so-called `Internet of Things' will gate the proliferation of these networks. The wavelength spectral range of 3-8um, commonly known as the mid-IR, is critical to specificity for sensors that identify materials by detection of local vibrational modes, reflectivity and thermal emission. For ubiquitous sensing applications in this regime, the sensors must move from premium to commodity level manufacturing volumes and cost. Scaling performance/cost is critically dependent on establishing a minimum set of platform attributes for point, wearable, and physical sensing. Optical sensors are ideal for non-invasive applications. Optical sensor device physics involves evanescent or intra-cavity structures for applied to concentration, interrogation and photo-catalysis functions. The ultimate utility of a platform is dependent on sample delivery/presentation modalities; system reset, recalibration and maintenance capabilities; and sensitivity and selectivity performance. The attributes and performance of a unified Glass-on-Silicon platform has shown good prospects for heterogeneous integration on materials and devices using a low cost process flow. Integrated, single mode, silicon photonic platforms offer significant performance and cost advantages, but they require discovery and qualification of new materials and process integration schemes for the mid-IR. Waveguide integrated light sources based on rare earth dopants and Ge-pumped frequency combs have promise. Optical resonators and waveguide spirals can enhance sensitivity. PbTe materials are among the best choices for a standard, waveguide integrated photodetector. Chalcogenide glasses are capable of transmitting mid-IR signals with high transparency. Integrated sensor case studies of i) high sensitivity analyte detection in

Synthesis of silicon nanocrystals in silane plasmas for nanoelectronics and large area electronic devices

International Nuclear Information System (INIS)

Roca i Cabarrocas, P; Nguyen-Tran, Th; Djeridane, Y; Abramov, A; Johnson, E; Patriarche, G

2007-01-01

The synthesis of silicon nanocrystals in standard radio-frequency glow discharge systems is studied with respect to two main objectives: (i) the production of devices based on quantum size effects associated with the small dimensions of silicon nanocrystals and (ii) the synthesis of polymorphous and polycrystalline silicon films in which silicon nanocrystals are the elementary building blocks. In particular we discuss results on the mechanisms of nanocrystal formation and their transport towards the substrate. We found that silicon nanocrystals can contribute to a significant fraction of deposition (50-70%) and that they can be positively charged. This has a strong influence on their deposition because positively charged nanocrystals will be accelerated towards the substrate with energy of the order of the plasma potential. However, the important parameter with respect to the deposition of charged nanocrystals is not the accelerating voltage but the energy per atom and thus a doubling of the diameter will result in a decrease in the energy per atom by a factor of 8. To leverage this geometrical advantage we propose the use of more electronegative gases, which may have a strong effect on the size and charge distribution of the nanocrystals. This is illustrated in the case of deposition from silicon tetrafluoride plasmas in which we observe low-frequency plasma fluctuations, associated with successive generations of nanocrystals. The contribution of larger nanocrystals to deposition results in a lower energy per deposited atom and thus polycrystalline films

Software-defined networking control plane for seamless integration of multiple silicon photonic switches in Datacom networks.

Science.gov (United States)

Shen, Yiwen; Hattink, Maarten H N; Samadi, Payman; Cheng, Qixiang; Hu, Ziyiz; Gazman, Alexander; Bergman, Keren

2018-04-16

Silicon photonics based switches offer an effective option for the delivery of dynamic bandwidth for future large-scale Datacom systems while maintaining scalable energy efficiency. The integration of a silicon photonics-based optical switching fabric within electronic Datacom architectures requires novel network topologies and arbitration strategies to effectively manage the active elements in the network. We present a scalable software-defined networking control plane to integrate silicon photonic based switches with conventional Ethernet or InfiniBand networks. Our software-defined control plane manages both electronic packet switches and multiple silicon photonic switches for simultaneous packet and circuit switching. We built an experimental Dragonfly network testbed with 16 electronic packet switches and 2 silicon photonic switches to evaluate our control plane. Observed latencies occupied by each step of the switching procedure demonstrate a total of 344 µs control plane latency for data-center and high performance computing platforms.

Hierarchical modeling of heat transfer in silicon-based electronic devices

Science.gov (United States)

Goicochea Pineda, Javier V.

In this work a methodology for the hierarchical modeling of heat transfer in silicon-based electronic devices is presented. The methodology includes three steps to integrate the different scales involved in the thermal analysis of these devices. The steps correspond to: (i) the estimation of input parameters and thermal properties required to solve the Boltzmann transport equation (BTE) for phonons by means of molecular dynamics (MD) simulations, (ii) the quantum correction of some of the properties estimated with MD to make them suitable for BTE and (iii) the numerical solution of the BTE using the lattice Boltzmann method (LBM) under the single mode relaxation time approximation subject to different initial and boundary conditions, including non-linear dispersion relations and different polarizations in the [100] direction. Each step of the methodology is validated with numerical, analytical or experimental reported data. In the first step of the methodology, properties such as, phonon relaxation times, dispersion relations, group and phase velocities and specific heat are obtained with MD at of 300 and 1000 K (i.e. molecular temperatures). The estimation of the properties considers the anhamonic nature of the potential energy function, including the thermal expansion of the crystal. Both effects are found to modify the dispersion relations with temperature. The behavior of the phonon relaxation times for each mode (i.e. longitudinal and transverse, acoustic and optical phonons) is identified using power functions. The exponents of the acoustic modes are agree with those predicted theoretically perturbation theory at high temperatures, while those for the optical modes are higher. All properties estimated with MD are validated with values for the thermal conductivity obtained from the Green-Kubo method. It is found that the relative contribution of acoustic modes to the overall thermal conductivity is approximately 90% at both temperatures. In the second step

Feasibility studies of microelectrode silicon detectors with integrated electronics

International Nuclear Information System (INIS)

Dalla Betta, G.-F.; Batignani, G.; Bettarini, S.; Boscardin, M.; Bosisio, L.; Carpinelli, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Lusiani, A.; Manghisoni, M.; Pignatel, G.U.; Rama, M.; Ratti, L.; Re, V.; Sandrelli, F.; Speziali, V.; Svelto, F.; Zorzi, N.

2002-01-01

We describe our experience on design and fabrication, on high-resistivity silicon substrates, of microstrip detectors and integrated electronics, devoted to high-energy physics experiments and medical/industrial imaging applications. We report on the full program of our collaboration, with particular regards to the tuning of a new fabrication process, allowing for the production of good quality transistors, while keeping under control the basic detector parameters, such as leakage current. Experimental results on JFET and bipolar transistors are presented, and a microstrip detector with an integrated JFET in source-follower configuration is introduced

Silicon Microspheres Photonics

International Nuclear Information System (INIS)

Serpenguzel, A.

2008-01-01

Electrophotonic integrated circuits (EPICs), or alternatively, optoelectronic integrated circuit (OEICs) are the natural evolution of the microelectronic integrated circuit (IC) with the addition of photonic capabilities. Traditionally, the IC industry has been based on group IV silicon, whereas the photonics industry on group III-V semiconductors. However, silicon based photonic microdevices have been making strands in siliconizing photonics. Silicon microspheres with their high quality factor whispering gallery modes (WGMs), are ideal candidates for wavelength division multiplexing (WDM) applications in the standard near-infrared communication bands. In this work, we will discuss the possibility of using silicon microspheres for photonics applications in the near-infrared

Integrated Optical lightguide device

NARCIS (Netherlands)

Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

2005-01-01

In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

Integrated Optical lightguide device

NARCIS (Netherlands)

Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

2000-01-01

In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

Ultra-short silicon MMI duplexer

Science.gov (United States)

Yi, Huaxiang; Huang, Yawen; Wang, Xingjun; Zhou, Zhiping

2012-11-01

The fiber-to-the-home (FTTH) systems are growing fast these days, where two different wavelengths are used for upstream and downstream traffic, typically 1310nm and 1490nm. The duplexers are the key elements to separate these wavelengths into different path in central offices (CO) and optical network unit (ONU) in passive optical network (PON). Multimode interference (MMI) has some benefits to be a duplexer including large fabrication tolerance, low-temperature dependence, and low-polarization dependence, but its size is too large to integrate in conventional case. Based on the silicon photonics platform, ultra-short silicon MMI duplexer was demonstrated to separate the 1310nm and 1490nm lights. By studying the theory of self-image phenomena in MMI, the first order images are adopted in order to keep the device short. A cascaded MMI structure was investigated to implement the wavelength splitting, where both the light of 1310nm and 1490nm was input from the same port, and the 1490nm light was coupling cross the first MMI and output at the cross-port in the device while the 1310nm light was coupling through the first and second MMI and output at the bar-port in the device. The experiment was carried on with the SOI wafer of 340nm top silicon. The cascaded MMI was investigated to fold the length of the duplexer as short as 117μm with the extinct ratio over 10dB.

Oxygen defect processes in silicon and silicon germanium

KAUST Repository

Chroneos, A.

2015-06-18

Silicon and silicon germanium are the archetypical elemental and alloy semiconductor materials for nanoelectronic, sensor, and photovoltaic applications. The investigation of radiation induced defects involving oxygen, carbon, and intrinsic defects is important for the improvement of devices as these defects can have a deleterious impact on the properties of silicon and silicon germanium. In the present review, we mainly focus on oxygen-related defects and the impact of isovalent doping on their properties in silicon and silicon germanium. The efficacy of the isovalent doping strategies to constrain the oxygen-related defects is discussed in view of recent infrared spectroscopy and density functional theory studies.

Oxygen defect processes in silicon and silicon germanium

KAUST Repository

Chroneos, A.; Sgourou, E. N.; Londos, C. A.; Schwingenschlö gl, Udo

2015-01-01

Silicon and silicon germanium are the archetypical elemental and alloy semiconductor materials for nanoelectronic, sensor, and photovoltaic applications. The investigation of radiation induced defects involving oxygen, carbon, and intrinsic defects is important for the improvement of devices as these defects can have a deleterious impact on the properties of silicon and silicon germanium. In the present review, we mainly focus on oxygen-related defects and the impact of isovalent doping on their properties in silicon and silicon germanium. The efficacy of the isovalent doping strategies to constrain the oxygen-related defects is discussed in view of recent infrared spectroscopy and density functional theory studies.

Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

2009-07-01

Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Insertable B-Layer integration in the ATLAS experiment and development of future 3D silicon pixel sensors

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00371528; Røhne, Ole

This work has two distinct objectives: the development of software for the integration of the Insertable B-Layer (IBL) in the ATLAS offline software framework and the study of the performance of 3D silicon sensors produced by SINTEF for future silicon pixel detectors. The former task consists in the implementation of the IBL byte stream converter. This offline tool performs the decoding of the binary-formatted data coming from the detector into information (e.g. hit position and Time over Threshold) that is stored in a format used in the reconstruction data flow. It also encodes the information extracted from simulations into a simulated IBL byte stream. The tool has been successfully used since the beginning of the LHC Run II data taking. The experimental work on SINTEF 3D sensors was performed in the framework of the development of pixel sensors for the next generation of tracking detectors. Preliminary tests on SINTEF 3D sensors showed that the majority of these devices suffers from high leakage currents, ...

Silicon micro-fluidic cooling for NA62 GTK pixel detectors

CERN Document Server

Romagnoli, G; Brunel, B; Catinaccio, A; Degrange, J; Mapelli, A; Morel, M; Noel, J; Petagna, P

2015-01-01

Silicon micro-channel cooling is being studied for efficient thermal management in application fields such as high power computing and 3D electronic integration. This concept has been introduced in 2010 for the thermal management of silicon pixel detectors in high energy physics experiments. Combining the versatility of standard micro-fabrication processes with the high thermal efficiency typical of micro-fluidics, it is possible to produce effective thermal management devices that are well adapted to different detector configurations. The production of very thin cooling devices in silicon enables a minimization of material of the tracking sensors and eliminates mechanical stresses due to the mismatch of the coefficient of thermal expansion between detectors and cooling systems. The NA62 experiment at CERN will be the first high particle physics experiment that will install a micro-cooling system to perform the thermal management of the three detection planes of its Gigatracker pixel detector.

Material synthesis for silicon integrated-circuit applications using ion implantation

Science.gov (United States)

Lu, Xiang

As devices scale down into deep sub-microns, the investment cost and complexity to develop more sophisticated device technologies have increased substantially. There are some alternative potential technologies, such as silicon-on-insulator (SOI) and SiGe alloys, that can help sustain this staggering IC technology growth at a lower cost. Surface SiGe and SiGeC alloys with germanium peak composition up to 16 atomic percent are formed using high-dose ion implantation and subsequent solid phase epitaxial growth. RBS channeling spectra and cross-sectional TEM studies show that high quality SiGe and SiGeC crystals with 8 atomic percent germanium concentration are formed at the silicon surface. Extended defects are formed in SiGe and SiGeC with 16 atomic percent germanium concentration. X-ray diffraction experiments confirm that carbon reduces the lattice strain in SiGe alloys but without significant crystal quality improvement as detected by RBS channeling spectra and XTEM observations. Separation by plasma implantation of oxygen (SPIMOX) is an economical method for SOI wafer fabrication. This process employs plasma immersion ion implantation (PIII) for the implantation of oxygen ions. The implantation rate for Pm is considerably higher than that of conventional implantation. The feasibility of SPIMOX has been demonstrated with successful fabrication of SOI structures implementing this process. Secondary ion mass spectrometry (SIMS) analysis and cross-sectional transmission electron microscopy (XTEM) micrographs of the SPIMOX sample show continuous buried oxide under single crystal overlayer with sharp silicon/oxide interfaces. The operational phase space of implantation condition, oxygen dose and annealing requirement has been identified. Physical mechanisms of hydrogen induced silicon surface layer cleavage have been investigated using a combination of microscopy and hydrogen profiling techniques. The evolution of the silicon cleavage phenomenon is recorded by a series

Integrated Silicon Carbide Power Electronic Block

Energy Technology Data Exchange (ETDEWEB)

Radhakrishnan, Rahul [Global Power Technologies Group, Inc., Lake Forest, CA (United States)

2017-11-07

Research involved in this project is aimed at monolithically integrating an anti-parallel diode to the SiC MOSFET switch, so as to avoid having to use an external anti-parallel diode in power circuit applications. SiC MOSFETs are replacing Si MOSFETs and IGBTs in many applications, yet the high bandgap of the body diode in SiC MOSFET and consequent need for an external anti-parallel diode increases costs and discourages circuit designers from adopting this technology. Successful demonstration and subsequent commercialization of this technology would reduce SiC MOSFET cost and additionally reduce component count as well as other costs at the power circuit level. In this Phase I project, we have created multiple device designs, set up a process for device fabrication at the 150mm SiC foundry XFAB Texas, demonstrated unit-processes for device fabrication in short loops and started full flow device fabrication. Key findings of the development activity were: The limits of coverage of photoresist over the topology of thick polysilicon structures covered with oxide, which required larger feature dimensions to overcome; and The insufficient process margin for removing oxide spacers from polysilicon field ring features which could result in loss of some features without further process development No fundamental obstacles were uncovered during the process development. Given sufficient time for additional development it is likely that processes could be tuned to realize the monolithically integrated SiC JBS diode and MOSFET. Sufficient funds were not available in this program to resolve processing difficulties and fabricate the devices.

Mode converter based on an inverse taper for multimode silicon nanophotonic integrated circuits.

Science.gov (United States)

Dai, Daoxin; Mao, Mao

2015-11-02

An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

Science.gov (United States)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Fabrication and characterization of an integrated ionic device from suspended polypyrrole and alamethicin-reconstituted lipid bilayer membranes

International Nuclear Information System (INIS)

Northcutt, Robert; Sundaresan, Vishnu-Baba

2012-01-01

Conducting polymers are electroactive materials that undergo conformal relaxation of the polymer backbone in the presence of an electrical field through ion exchange with solid or aqueous electrolytes. This conformal relaxation and the associated morphological changes make conducting polymers highly suitable for actuation and sensing applications. Among smart materials, bioderived active materials also use ion transport for sensing and actuation functions via selective ion transport. The transporter proteins extracted from biological cell membranes and reconstituted into a bilayer lipid membrane in bioderived active materials regulate ion transport for engineering functions. The protein transporter reconstituted in the bilayer lipid membrane is referred to as the bioderived membrane and serves as the active component in bioderived active materials. Inspired by the similarities in the physics of transduction in conducting polymers and bioderived active materials, an integrated ionic device is formed from the bioderived membrane and the conducting polymer membrane. This ionic device is fabricated into a laminated thin-film membrane and a common ion that can be processed by the bioderived and the conducting polymer membranes couple the ionic function of these two membranes. An integrated ionic device, fabricated from polypyrrole (PPy) doped with sodium dodecylbenzenesulfonate (NaDBS) and an alamethicin-reconstituted DPhPC bilayer lipid membrane, is presented in this paper. A voltage-gated sodium current regulates the electrochemical response in the PPy(DBS) layer. The integrated device is fabricated on silicon-based substrates through microfabrication, electropolymerization, and vesicle fusion, and ionic activity is characterized through electrochemical measurements. (paper)

Technology for the compatible integration of silicon detectors with readout electronics

International Nuclear Information System (INIS)

Zimmer, G.

1984-01-01

Compatible integration of detectors and readout electronics on the same silicon substrate is of growing interest. As the methods of microelectronics technology have already been adapted for detector fabrication, a common technology basis for detectors and readout electronics is available. CMOS technology exhibits most attractive features for the compatible realization of readout electronics when advanced LSI processing steps are combined with detector requirements. The essential requirements for compatible integration are the availability of high resistivity (100)-oriented single crystalline silicon substrate, the formation of suitably doped areas for MOS circuits and the isolation of the low voltage circuit from the detector operated at much higher supply voltage. Junction isolation as a first approach based on present production technology and dielectric isolation based on an advanced SOI-LSI technology are discussed as the most promising solutions for present and future applications, respectively. (orig.)

Simplified nonplanar wafer bonding for heterogeneous device integration

Science.gov (United States)

Geske, Jon; Bowers, John E.; Riley, Anton

2004-07-01

We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

Integrated GaN photonic circuits on silicon (100) for second harmonic generation

OpenAIRE

Xiong, Chi; Pernice, Wolfram; Ryu, Kevin K.; Schuck, Carsten; Fong, King Y.; Palacios, Tomas; Tang, Hong X.

2014-01-01

We demonstrate second order optical nonlinearity in a silicon architecture through heterogeneous integration of single-crystalline gallium nitride (GaN) on silicon (100) substrates. By engineering GaN microrings for dual resonance around 1560 nm and 780 nm, we achieve efficient, tunable second harmonic generation at 780 nm. The \\{chi}(2) nonlinear susceptibility is measured to be as high as 16 plus minus 7 pm/V. Because GaN has a wideband transparency window covering ultraviolet, visible and ...

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

Science.gov (United States)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Core-shell heterojunction of silicon nanowire arrays and carbon quantum dots for photovoltaic devices and self-driven photodetectors.

Science.gov (United States)

Xie, Chao; Nie, Biao; Zeng, Longhui; Liang, Feng-Xia; Wang, Ming-Zheng; Luo, Linbao; Feng, Mei; Yu, Yongqiang; Wu, Chun-Yan; Wu, Yucheng; Yu, Shu-Hong

2014-04-22

Silicon nanostructure-based solar cells have lately intrigued intensive interest because of their promising potential in next-generation solar energy conversion devices. Herein, we report a silicon nanowire (SiNW) array/carbon quantum dot (CQD) core-shell heterojunction photovoltaic device by directly coating Ag-assisted chemical-etched SiNW arrays with CQDs. The heterojunction with a barrier height of 0.75 eV exhibited excellent rectifying behavior with a rectification ratio of 10(3) at ±0.8 V in the dark and power conversion efficiency (PCE) as high as 9.10% under AM 1.5G irradiation. It is believed that such a high PCE comes from the improved optical absorption as well as the optimized carrier transfer and collection capability. Furthermore, the heterojunction could function as a high-performance self-driven visible light photodetector operating in a wide switching wavelength with good stability, high sensitivity, and fast response speed. It is expected that the present SiNW array/CQD core-shell heterojunction device could find potential applications in future high-performance optoelectronic devices.

HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

Science.gov (United States)

Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

2000-08-01

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

Porous silicon: silicon quantum dots for photonic applications

International Nuclear Information System (INIS)

Pavesi, L.; Guardini, R.

1996-01-01

Porous silicon formation and structure characterization are briefly illustrated. Its luminescence properties rae presented and interpreted on the basis of exciton recombination in quantum dot structures: the trap-controlled hopping mechanism is used to describe the recombination dynamics. Porous silicon application to photonic devices is considered: porous silicon multilayer in general, and micro cavities in particular are described. The present situation in the realization of porous silicon LEDs is considered, and future developments in this field of research are suggested. (author). 30 refs., 30 figs., 13 tabs

MOS structures containing silicon nanoparticles for memory device applications

International Nuclear Information System (INIS)

Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

2008-01-01

Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

Silicon photonic crystal all-optical logic gates

Energy Technology Data Exchange (ETDEWEB)

Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

2013-01-03

All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

Energy Technology Data Exchange (ETDEWEB)

Zerrouk, D.

1997-07-18

Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Energy Technology Data Exchange (ETDEWEB)

Hutchinson, David [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Department of Physics and Nuclear Engineering, United States Military Academy, West Point NY 10996 (United States); Mathews, Jay [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States); Department of Physics, University of Dayton, Dayton, OH 45469 (United States); Sullivan, Joseph T.; Buonassisi, Tonio [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Akey, Austin [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Aziz, Michael J. [Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Persans, Peter [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Warrender, Jeffrey M., E-mail: jwarrend@post.harvard.edu [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States)

2016-05-15

We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE) is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011)] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011)], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Directory of Open Access Journals (Sweden)

David Hutchinson

2016-05-01

Full Text Available We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

From physics to devices light emissions in silicon from physics to devices

CERN Document Server

Lockwood, David J; Weber, Eicke R; Lockwood, David J

1997-01-01

Since its inception in 1966, the series of numbered volumes known as Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors.The"Willardson and Beer"Series, as it is widely known, has succeeded in publishing numerous landmark volumes and chapters. Not only did many of these volumes make an impact at the time of their publication, but they continue to be well-cited years after their original release. Recently, Professor Eicke R. Weber of the University of California at Berkeley joined as a co-editor of the series. Professor Weber, a well-known expert in the field of semiconductor materials, will further contribute to continuing the series' tradition of publishing timely, highly relevant, and long-impacting volumes. Some of the recent volumes, such as Hydrogen in Semiconductors, Imperfections in III/V Materials, Epitaxial Microstructures, High-Speed Heterostructure Devices,Oxygen in Silicon, and others promise indeed that this traditi...

Strategies for doped nanocrystalline silicon integration in silicon heterojunction solar cells

Czech Academy of Sciences Publication Activity Database

Seif, J.; Descoeudres, A.; Nogay, G.; Hänni, S.; de Nicolas, S.M.; Holm, N.; Geissbühler, J.; Hessler-Wyser, A.; Duchamp, M.; Dunin-Borkowski, R.E.; Ledinský, Martin; De Wolf, S.; Ballif, C.

2016-01-01

Roč. 6, č. 5 (2016), s. 1132-1140 ISSN 2156-3381 R&D Projects: GA MŠk LM2015087 Institutional support: RVO:68378271 Keywords : microcrystalline silicon * nanocrystalline silicon * silicon heterojunctions (SHJs) * solar cells Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.712, year: 2016

Silicon-based optical integrated circuits for terabit communication networks

International Nuclear Information System (INIS)

Svidzinsky, K K

2003-01-01

A brief review is presented of the development of silicon-based optical integrated circuits used as components in modern all-optical communication networks with the terabit-per-second transmission capacity. The designs and technologies for manufacturing these circuits are described and the problems related to their development and application in WDM communication systems are considered. (special issue devoted to the memory of academician a m prokhorov)

Development of an integrated pointing device driver for the disabled.

Science.gov (United States)

Shih, Ching-Hsiang; Shih, Ching-Tien

2010-01-01

To help people with disabilities such as those with spinal cord injury (SCI) to effectively utilise commercial pointing devices to operate computers. This study proposes a novel method to integrate the functions of commercial pointing devices. Utilising software technology to develop an integrated pointing device driver (IPDD) for a computer operating system. The proposed IPDD has the following benefits: (1) it does not require additional hardware cost or circuit preservations, (2) it supports all standard interfaces of commercial pointing devices, including PS/2, USB and wireless interfaces and (3) it can integrate any number of devices. The IPDD can be selected and combined according to their physical restriction. The IPDD is a novel method of integrating commercial pointing devices. Through IPDD, people with disabilities can choose a suitable combination of commercial pointing devices to achieve full cursor control and optimise operational performance. In contrast with previous studies, the software-based solution does not require additional hardware or circuit preservations, and it can support unlimited devices. In summary, the IPDD has the benefits of flexibility, low cost and high-device compatibility.

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film

International Nuclear Information System (INIS)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-01-01

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices’ applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H 2 O 2 /HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing. (paper)

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film.

Science.gov (United States)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-04-17

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices' applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H2O2/HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing.

Effect of Silicon Nanowire on Crystalline Silicon Solar Cell Characteristics

OpenAIRE

Zahra Ostadmahmoodi Do; Tahereh Fanaei Sheikholeslami; Hassan Azarkish

2016-01-01

Nanowires (NWs) are recently used in several sensor or actuator devices to improve their ordered characteristics. Silicon nanowire (Si NW) is one of the most attractive one-dimensional nanostructures semiconductors because of its unique electrical and optical properties. In this paper, silicon nanowire (Si NW), is synthesized and characterized for application in photovoltaic device. Si NWs are prepared using wet chemical etching method which is commonly used as a simple and low cost method fo...

Mid-infrared materials and devices on a Si platform for optical sensing

Science.gov (United States)

Singh, Vivek; Lin, Pao Tai; Patel, Neil; Lin, Hongtao; Li, Lan; Zou, Yi; Deng, Fei; Ni, Chaoying; Hu, Juejun; Giammarco, James; Soliani, Anna Paola; Zdyrko, Bogdan; Luzinov, Igor; Novak, Spencer; Novak, Jackie; Wachtel, Peter; Danto, Sylvain; Musgraves, J David; Richardson, Kathleen; Kimerling, Lionel C; Agarwal, Anuradha M

2014-01-01

In this article, we review our recent work on mid-infrared (mid-IR) photonic materials and devices fabricated on silicon for on-chip sensing applications. Pedestal waveguides based on silicon are demonstrated as broadband mid-IR sensors. Our low-loss mid-IR directional couplers demonstrated in SiNx waveguides are useful in differential sensing applications. Photonic crystal cavities and microdisk resonators based on chalcogenide glasses for high sensitivity are also demonstrated as effective mid-IR sensors. Polymer-based functionalization layers, to enhance the sensitivity and selectivity of our sensor devices, are also presented. We discuss the design of mid-IR chalcogenide waveguides integrated with polycrystalline PbTe detectors on a monolithic silicon platform for optical sensing, wherein the use of a low-index spacer layer enables the evanescent coupling of mid-IR light from the waveguides to the detector. Finally, we show the successful fabrication processing of our first prototype mid-IR waveguide-integrated detectors. PMID:27877641

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

Science.gov (United States)

Horst, Folkert; Green, William M J; Assefa, Solomon; Shank, Steven M; Vlasov, Yurii A; Offrein, Bert Jan

2013-05-20

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

International Nuclear Information System (INIS)

Qian Li-Bo; Xia Yin-Shui; Zhu Zhang-Ming; Ding Rui-Xue; Yang Yin-Tang

2014-01-01

Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three-dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 mV and 379 mV reductions in the peak noise voltage, respectively

Flexible and tunable silicon photonic circuits on plastic substrates

Science.gov (United States)

Chen, Yu; Li, Huan; Li, Mo

2012-09-01

Flexible microelectronics has shown tremendous promise in a broad spectrum of applications, especially those that cannot be addressed by conventional microelectronics in rigid materials and constructions. These unconventional yet important applications range from flexible consumer electronics to conformal sensor arrays and biomedical devices. A recent paradigm shift in implementing flexible electronics is to physically transfer highly integrated devices made in high-quality, crystalline semiconductors on to plastic substrates. Here we demonstrate a flexible form of silicon photonics using the transfer-and-bond fabrication method. Photonic circuits including interferometers and resonators have been transferred onto flexible plastic substrates with preserved functionalities and performance. By mechanically deforming, the optical characteristics of the devices can be tuned reversibly over a remarkably large range. The demonstration of the new flexible photonic systems based on the silicon-on-plastic (SOP) platform could open the door to many future applications, including tunable photonics, optomechanical sensors and biomechanical and bio-photonic probes.

Modeling optical transmissivity of graphene grate in on-chip silicon photonic device

Science.gov (United States)

Amiri, Iraj S.; Ariannejad, M. M.; Jalil, M. A.; Ali, J.; Yupapin, P.

2018-06-01

A three-dimensional (3-D) finite-difference-time-domain (FDTD) analysis was used to simulate a silicon photonic waveguide. We have calculated power and transmission of the graphene used as single or multilayers to study the light transmission behavior. A new technique has been developed to define the straight silicon waveguide integrated with grate graphene layer. The waveguide has a variable grate spacing to be filled by the graphene layer. The number of graphene atomic layers varies between 100 and 1000 (or 380 nm and 3800 nm), the transmitted power obtained varies as ∼30% and ∼80%. The ∼99%, blocking of the light was occurred in 10,000 (or 38,000 nm) atomic layers of the graphene grate.

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

Silicon photonics for multicore fiber communication

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

We review our recent work on silicon photonics for multicore fiber communication, including multicore fiber fan-in/fan-out, multicore fiber switches towards reconfigurable optical add/drop multiplexers. We also present multicore fiber based quantum communication using silicon devices.......We review our recent work on silicon photonics for multicore fiber communication, including multicore fiber fan-in/fan-out, multicore fiber switches towards reconfigurable optical add/drop multiplexers. We also present multicore fiber based quantum communication using silicon devices....

Fully integrated monolithic opoelectronic transducer for real.time protein and DNA detection

DEFF Research Database (Denmark)

Misiakos, Konstatinos; S. Petrou, Panagiota; E. Kakabakos, Sotirios

2010-01-01

The development and testing of a portable bioanalytical device which was capable for real-time monitoring of binding assays was demonstrated. The device was based on arrays of nine optoelectronic transducers monolithically integrated on silicon chips. The optocouplers consisted of nine silicon av...... by exploiting wavelength filtering on photonic crystal engineered waveguides. The proposed miniaturized sensing device with proper packaging and accompanied by a portable instrument can find wide application as a platform for reliable and cost effective point-of-care diagnosis....

Silicon-based sleeve devices for chemical reactions

Science.gov (United States)

Northrup, M. Allen; Mariella, Jr., Raymond P.; Carrano, Anthony V.; Balch, Joseph W.

1996-01-01

A silicon-based sleeve type chemical reaction chamber that combines heaters, such as doped polysilicon for heating, and bulk silicon for convection cooling. The reaction chamber combines a critical ratio of silicon and silicon nitride to the volume of material to be heated (e.g., a liquid) in order to provide uniform heating, yet low power requirements. The reaction chamber will also allow the introduction of a secondary tube (e.g., plastic) into the reaction sleeve that contains the reaction mixture thereby alleviating any potential materials incompatibility issues. The reaction chamber may be utilized in any chemical reaction system for synthesis or processing of organic, inorganic, or biochemical reactions, such as the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction, which are examples of a synthetic, thermal-cycling-based reaction. The reaction chamber may also be used in synthesis instruments, particularly those for DNA amplification and synthesis.

Ordered silicon nanostructures for silicon-based photonics devices

Czech Academy of Sciences Publication Activity Database

Fojtík, A.; Valenta, J.; Pelant, Ivan; Kálal, M.; Fiala, P.

2007-01-01

Roč. 5, Suppl. (2007), S250-S253 ISSN 1671-7694 R&D Projects: GA AV ČR IAA1010316 Grant - others:GA MŠk(CZ) ME 933 Institutional research plan: CEZ:AV0Z10100521 Keywords : nanocrystals * silicon * self-assembled monolayers Subject RIV: BM - Solid Matter Physics ; Magnetism

Ultrahigh-density trench cpacitors in silicon and their application to integrated DC-DC conversion

NARCIS (Netherlands)

Roozeboom, F.; Bergveld, H.J.; Nowak, K.; Le Cornec, F.; Guiraud, L.; Bunel, C.; Iochem, S.; Ferreira, J.; Ledain, S.; Pieraerts, E.; Pommier, M.

2009-01-01

This paper addresses silicon-based integration of passive components applied to 3D integration with dies of other technologies within one package. Particularly, the development of high-density trench capacitors has enabled the realization of small-formfactor DC-DC converters. As illustration, an

Radiation-hard silicon photonics for high energy physics and beyond

CERN Multimedia

CERN. Geneva

2016-01-01

Silicon photonics (SiPh) is currently being investigated as a promising technology for future radiation hard optical links. The possibility of integrating SiPh devices with electronics and/or silicon particle sensors as well as an expected very high resistance against radiation damage make this technology particularly interesting for potential use close to the interaction points in future in high energy physics experiments and other radiation-sensitive applications. The presentation will summarize the outcomes of the research on radiation hard SiPh conducted within the ICE-DIP projected.

Characterization of Amorphous Silicon Advanced Materials and PV Devices: Final Technical Report, 15 December 2001--31 January 2005

Energy Technology Data Exchange (ETDEWEB)

Taylor, P. C.

2005-11-01

The major objectives of this subcontract have been: (1) understand the microscopic properties of the defects that contribute to the Staebler-Wronski effect to eliminate this effect, (2) perform correlated studies on films and devices made by novel techniques, especially those with promise to improve stability or deposition rates, (3) understand the structural, electronic, and optical properties of films of hydrogenated amorphous silicon (a-Si:H) made on the boundary between the amorphous and microcrystalline phases, (4) search for more stable intrinsic layers of a-Si:H, (5) characterize the important defects, impurities, and metastabilities in the bulk and at surfaces and interfaces in a-Si:H films and devices and in important alloy systems, and (6) make state-of-the-art plasma-enhanced chemical vapor deposition (PECVD) devices out of new, advanced materials, when appropriate. All of these goals are highly relevant to improving photovoltaic devices based on a-Si:H and related alloys. With regard to the first objective, we have identified a paired hydrogen site that may be the defect that stabilizes the silicon dangling bonds formed in the Staebler-Wronski effect.

Photosensitive N channel MOSFET device on silicon on sapphire substrate

International Nuclear Information System (INIS)

Le Goascoz, V.; Borel, J.

1975-01-01

An anomalous behavior of the N channel output current characteristic in a SOS MOSFET with a floating bulk is described. Such a phenomenon can be used in a photosensitive device with internal gain. Such devices can be used on SOS substrates to achieve integrated circuits with high insulating voltages and data transmission by optical means [fr

Optimization of metallic microheaters for high-speed reconfigurable silicon photonics.

Science.gov (United States)

Atabaki, A H; Shah Hosseini, E; Eftekhar, A A; Yegnanarayanan, S; Adibi, A

2010-08-16

The strong thermooptic effect in silicon enables low-power and low-loss reconfiguration of large-scale silicon photonics. Thermal reconfiguration through the integration of metallic microheaters has been one of the more widely used reconfiguration techniques in silicon photonics. In this paper, structural and material optimizations are carried out through heat transport modeling to improve the reconfiguration speed of such devices, and the results are experimentally verified. Around 4 micros reconfiguration time are shown for the optimized structures. Moreover, sub-microsecond reconfiguration time is experimentally demonstrated through the pulsed excitation of the microheaters. The limitation of this pulsed excitation scheme is also discussed through an accurate system-level model developed for the microheater response.

A novel Silicon Photomultiplier with bulk integrated quench resistors: utilization in optical detection and tracking applications for particle physics

Energy Technology Data Exchange (ETDEWEB)

Petrovics, Stefan, E-mail: stp@hll.mpg.de [Halbleiterlabor der Max-Planck Gesellschaft, Otto-Hahn-Ring 6, D-81739 Munich (Germany); Andricek, Ladislav [Halbleiterlabor der Max-Planck Gesellschaft, Otto-Hahn-Ring 6, D-81739 Munich (Germany); Diehl, Inge; Hansen, Karsten [DESY, Notkestrasse 85, D-22607 Hamburg (Germany); Jendrysik, Christian [Infineon Technologies AG, Am Campeon 1-12, D-85579 Neubiberg (Germany); Krueger, Katja [DESY, Notkestrasse 85, D-22607 Hamburg (Germany); Lehmann, Raik; Ninkovic, Jelena [Halbleiterlabor der Max-Planck Gesellschaft, Otto-Hahn-Ring 6, D-81739 Munich (Germany); Reckleben, Christian [DESY, Notkestrasse 85, D-22607 Hamburg (Germany); Richter, Rainer; Schaller, Gerhard; Schopper, Florian [Halbleiterlabor der Max-Planck Gesellschaft, Otto-Hahn-Ring 6, D-81739 Munich (Germany); Sefkow, Felix [DESY, Notkestrasse 85, D-22607 Hamburg (Germany)

2017-02-11

Silicon Photomultipliers (SiPMs) are a promising candidate for replacing conventional photomultiplier tubes (PMTs) in many applications, thanks to ongoing developments and advances in their technology. Conventional SiPMs are generally an array of avalanche photo diodes, operated in Geiger mode and read out in parallel, thus leading to the necessity of a high ohmic quenching resistor. This resistor enables passive quenching and is usually located on top of the array, limiting the fill factor of the device. In this paper, a novel detector concept with a bulk integrated quenching resistor will be recapped. In addition, due to other advantages of this novel detector design, a new concept, in which these devices will be utilized as tracking detectors for particle physics applications will be introduced, as well as first simulation studies and experimental measurements of this new approach. - Highlights: • A novel SiPM concept with bulk integrated quenching resistor is shown. • First prototypes of these SiPMs as tracking detectors are proposed. • Simulations of the Geiger efficiency suggest feasible operations at low overbias. • First measurements of the electron detection efficiency show promising results. • Measurements are in good agreement with the simulations.

Silicon-Based Technology for Integrated Waveguides and mm-Wave Systems

DEFF Research Database (Denmark)

Jovanovic, Vladimir; Gentile, Gennaro; Dekker, Ronald

2015-01-01

IC processing is used to develop technology for silicon-filled millimeter-wave-integrated waveguides. The front-end process defines critical waveguide sections and enables integration of dedicated components, such as RF capacitors and resistors. Wafer gluing is used to strengthen the mechanical...... support and deep reactive-ion etching forms the waveguide bulk with smooth and nearly vertical sidewalls. Aluminum metallization covers the etched sidewalls, fully enclosing the waveguides in metal from all sides. Waveguides are fabricated with a rectangular cross section of 560 μm x 280 μm. The measured...

Brain inspired high performance electronics on flexible silicon

KAUST Repository

Sevilla, Galo T.

2014-06-01

Brain\\'s stunning speed, energy efficiency and massive parallelism makes it the role model for upcoming high performance computation systems. Although human brain components are a million times slower than state of the art silicon industry components [1], they can perform 1016 operations per second while consuming less power than an electrical light bulb. In order to perform the same amount of computation with today\\'s most advanced computers, the output of an entire power station would be needed. In that sense, to obtain brain like computation, ultra-fast devices with ultra-low power consumption will have to be integrated in extremely reduced areas, achievable only if brain folded structure is mimicked. Therefore, to allow brain-inspired computation, flexible and transparent platform will be needed to achieve foldable structures and their integration on asymmetric surfaces. In this work, we show a new method to fabricate 3D and planar FET architectures in flexible and semitransparent silicon fabric without comprising performance and maintaining cost/yield advantage offered by silicon-based electronics.

Enhanced UV photoresponse of KrF-laser-synthesized single-wall carbon nanotubes/n-silicon hybrid photovoltaic devices.

Science.gov (United States)

Le Borgne, V; Gautier, L A; Castrucci, P; Del Gobbo, S; De Crescenzi, M; El Khakani, M A

2012-06-01

We report on the KrF-laser ablation synthesis, purification and photocurrent generation properties of single-wall carbon nanotubes (SWCNTs). The thermally purified SWCNTs are integrated into hybrid photovoltaic (PV) devices by spin-coating them onto n-Si substrates. These novel SWCNTs/n-Si hybrid devices are shown to generate significant photocurrent (PC) over the entire 250-1050 nm light spectrum with external quantum efficiencies (EQE) reaching up to ~23%. Our SWCNTs/n-Si hybrid devices are not only photoactive in the traditional spectral range of Si solar cells, but generate also significant PC in the UV domain (below 400 nm). This wider spectral response is believed to be the result of PC generation from both the SWCNTs themselves and the tremendous number of local p-n junctions created at the nanotubes/Si interface. To assess the prevalence of these two contributions, the EQE spectra and J-V characteristics of these hybrid devices were investigated in both planar and top-down configurations, as a function of SWCNTs' film thickness. A sizable increase in EQE in the near UV with respect to the silicon is observed in both configurations, with a more pronounced UV photoresponse in the planar mode, confirming thereby the role of SWCNTs in the photogeneration process. The PC generation is found to reach its maximum for an optimal the SWCNT film thickness, which is shown to correspond to the best trade-off between lowest electrical resistance and highest optical transparency. Finally, by analyzing the J-V characteristics of our SWCNTs/n-Si devices with an equivalent circuit model, we were able to point out the contribution of the various electrical components involved in the photogeneration process. The SWCNTs-based devices demonstrated here open up the prospect for their use in highly effective photovoltaics and/or UV-light sensors.

Si light-emitting device in integrated photonic CMOS ICs

Science.gov (United States)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

Integrated Photonic Devices Incorporating Low-Loss Fluorinated Polymer Materials

Directory of Open Access Journals (Sweden)

Hyung-Jong Lee

2011-06-01

Full Text Available Low-loss polymer materials incorporating fluorinated compounds have been utilized for the investigation of various functional optical devices useful for optical communication and optical sensor systems. Since reliability issues concerning the polymer device have been resolved, polymeric waveguide devices have been gradually adopted for commercial application systems. The two most successfully commercialized polymeric integrated optic devices, variable optical attenuators and digital optical switches, are reviewed in this paper. Utilizing unique properties of optical polymers which are not available in other optical materials, novel polymeric optical devices are proposed including widely tunable external cavity lasers and integrated optical current sensors.

Semiconductor integrated circuits

International Nuclear Information System (INIS)

Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

1979-01-01

An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

Investigation of silicon/silicon germanium multiple quantum well layers in silicon avalanche photodiodes

International Nuclear Information System (INIS)

Loudon, A.Y.

2002-01-01

Silicon single photon avalanche diodes (SPADs) are currently utilised in many single photon counting systems due to their high efficiency, fast response times, low voltage operation and potentially low cost. For fibre based applications however (at wavelengths 1.3 and 1.55μm) and eye-safe wavelength applications (>1.4μm), Si devices are not suitable due to their 1.1μm absorption edge and hence greatly reduced absorption above this wavelength. InGaAs/InP or Ge SPADs absorb at these longer wavelengths, but both require cryogenic cooling for low noise operation and III-V integration with conventional Si circuitry is difficult. Si/SiGe is currently attracting great interest for optoelectronic applications and attempts to combine Si avalanche photodiodes with Si/SiGe multiple quantum well absorbing layers have been successful. Here, an effort to utilise this material system has shown an improvement in photon counting efficiency above 1.1μm of more than 30 times compared to an all-Si control device. In addition to its longer wavelength response, this Si/SiGe device has room temperature operation, low cost fabrication and is compatible with conventional Si circuitry. (author)

Characterization of Czochralski Silicon Detectors

OpenAIRE

Luukka, Panja-Riina; Haerkoenen, Jaakko

2012-01-01

This thesis describes the characterization of irradiated and non-irradiated segmenteddetectors made of high-resistivity (>1 kΩcm) magnetic Czochralski (MCZ) silicon. It isshown that the radiation hardness (RH) of the protons of these detectors is higher thanthat of devices made of traditional materials such as Float Zone (FZ) silicon or DiffusionOxygenated Float Zone (DOFZ) silicon due to the presence of intrinsic oxygen (> 5 x1017 cm-3). The MCZ devices therefore present an interesting alter...

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

Science.gov (United States)

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea; Paviet-Salomon, Bertrand; Jeangros, Quentin; Haschke, Jan; Christmann, Gabriel; Barraud, Loris; Descoeudres, Antoine; Seif, Johannes Peter; Nicolay, Sylvain; Despeisse, Matthieu; De Wolf, Stefaan; Ballif, Christophe

2017-01-01

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea

2017-04-24

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Catastrophic degradation of the interface of epitaxial silicon carbide on silicon at high temperatures

Energy Technology Data Exchange (ETDEWEB)

Pradeepkumar, Aiswarya; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca [Queensland Micro and Nanotechnology Centre and Environmental Futures Research Institute, Griffith University, Nathan QLD 4111 (Australia); Boeckl, John J. [Materials and Manufacturing Directorate, Air Force Research Laboratories, Wright-Patterson Air Force Base, Ohio 45433 (United States); Hellerstedt, Jack; Fuhrer, Michael S. [Monash Centre for Atomically Thin Materials, Monash University, Monash, VIC 3800 (Australia)

2016-07-04

Epitaxial cubic silicon carbide on silicon is of high potential technological relevance for the integration of a wide range of applications and materials with silicon technologies, such as micro electro mechanical systems, wide-bandgap electronics, and graphene. The hetero-epitaxial system engenders mechanical stresses at least up to a GPa, pressures making it extremely challenging to maintain the integrity of the silicon carbide/silicon interface. In this work, we investigate the stability of said interface and we find that high temperature annealing leads to a loss of integrity. High–resolution transmission electron microscopy analysis shows a morphologically degraded SiC/Si interface, while mechanical stress measurements indicate considerable relaxation of the interfacial stress. From an electrical point of view, the diode behaviour of the initial p-Si/n-SiC junction is catastrophically lost due to considerable inter-diffusion of atoms and charges across the interface upon annealing. Temperature dependent transport measurements confirm a severe electrical shorting of the epitaxial silicon carbide to the underlying substrate, indicating vast predominance of the silicon carriers in lateral transport above 25 K. This finding has crucial consequences on the integration of epitaxial silicon carbide on silicon and its potential applications.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

Science.gov (United States)

Shen, Wen-Wei; Chen, Kuan-Neng

2017-12-01

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

White-light emission from porous-silicon-aluminium Schottky junctions

International Nuclear Information System (INIS)

Masini, G.; La Monica, S.; Maiello, G.

1996-01-01

Porous-silicon-based white-light-emitting devices are presented. The fabrication process on different substrates is described. The peculiarities of technological steps for device fabrication (porous-silicon formation and aluminium treatment) are underlined. Doping profile of the porous layer, current-voltage characteristics, time response, lifetime tests and electroluminescence emission spectrum of the device are presented. A model for electrical behaviour of Al/porous silicon Schottky junction is presented. Electroluminescence spectrum of the presented devices showed strong similarities with white emission from crystalline silicon junctions in the breakdown region

Atomic and electronic structures of novel silicon surface structures

Energy Technology Data Exchange (ETDEWEB)

Terry, J.H. Jr.

1997-03-01

The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

Micromachined silicon seismic accelerometer development

Energy Technology Data Exchange (ETDEWEB)

Barron, C.C.; Fleming, J.G.; Montague, S. [and others

1996-08-01

Batch-fabricated silicon seismic transducers could revolutionize the discipline of seismic monitoring by providing inexpensive, easily deployable sensor arrays. Our ultimate goal is to fabricate seismic sensors with sensitivity and noise performance comparable to short-period seismometers in common use. We expect several phases of development will be required to accomplish that level of performance. Traditional silicon micromachining techniques are not ideally suited to the simultaneous fabrication of a large proof mass and soft suspension, such as one needs to achieve the extreme sensitivities required for seismic measurements. We have therefore developed a novel {open_quotes}mold{close_quotes} micromachining technology that promises to make larger proof masses (in the 1-10 mg range) possible. We have successfully integrated this micromolding capability with our surface-micromachining process, which enables the formation of soft suspension springs. Our calculations indicate that devices made in this new integrated technology will resolve down to at least sub-{mu}G signals, and may even approach the 10{sup -10} G/{radical}Hz acceleration levels found in the low-earth-noise model.

Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

Atomic layer deposition for graphene device integration

NARCIS (Netherlands)

Vervuurt, R.H.J.; Kessels, W.M.M.; Bol, A.A.

2017-01-01

Graphene is a two dimensional material with extraordinary properties, which make it an interesting material for many optical and electronic devices. The integration of graphene in these devices often requires the deposition of thin dielectric layers on top of graphene. Atomic layer deposition (ALD)

Methods and mechanisms of gettering of silicon structures in the production of integrated circuits

Directory of Open Access Journals (Sweden)

Pilipenko V. A.

2013-05-01

Full Text Available Increasing the degree of integration of hardware components imposes more stringent requirements for the reduction of the concentration of contaminants and oxidation stacking faults in the original silicon wafers with its preservation in the IC manufacturing process cycle. This causes high relevance of the application of gettering in modern microelectronic technology. The existing methods of silicon wafers gettering and the mechanisms of their occurrence are considered.

Integration in design and manufacturing of polymer smart devices

NARCIS (Netherlands)

Bolt, P.J.; Zwart, R.M. de; Tacken, R.A.; Rendering, H.

2009-01-01

Integration of functions in single components is pursued in order to manufacture smaller and smarter polymer micro devices at less cost, through e.g. less assembly steps. It requires integration on both product and production side. This paper addresses the use of molded interconnect device (MID)

Thin film silicon photovoltaics: Architectural perspectives and technological issues

Energy Technology Data Exchange (ETDEWEB)

Mercaldo, Lucia Vittoria; Addonizio, Maria Luisa; Noce, Marco Della; Veneri, Paola Delli; Scognamiglio, Alessandra; Privato, Carlo [ENEA, Portici Research Center, Piazzale E. Fermi, 80055 Portici (Napoli) (Italy)

2009-10-15

Thin film photovoltaics is a particularly attractive technology for building integration. In this paper, we present our analysis on architectural issues and technological developments of thin film silicon photovoltaics. In particular, we focus on our activities related to transparent and conductive oxide (TCO) and thin film amorphous and microcrystalline silicon solar cells. The research on TCO films is mainly dedicated to large-area deposition of zinc oxide (ZnO) by low pressure-metallorganic chemical vapor deposition. ZnO material, with a low sheet resistance (<8 {omega}/sq) and with an excellent transmittance (>82%) in the whole wavelength range of photovoltaic interest, has been obtained. ''Micromorph'' tandem devices, consisting of an amorphous silicon top cell and a microcrystalline silicon bottom cell, are fabricated by using the very high frequency plasma enhanced chemical vapor deposition technique. An initial efficiency of 11.1% (>10% stabilized) has been obtained. (author)

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

Science.gov (United States)

Gowda, Srivardhan Shivappa

studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable

Integrating a dual-silicon photoelectrochemical cell into a redox flow battery for unassisted photocharging.

Science.gov (United States)

Liao, Shichao; Zong, Xu; Seger, Brian; Pedersen, Thomas; Yao, Tingting; Ding, Chunmei; Shi, Jingying; Chen, Jian; Li, Can

2016-05-04

Solar rechargeable flow cells (SRFCs) provide an attractive approach for in situ capture and storage of intermittent solar energy via photoelectrochemical regeneration of discharged redox species for electricity generation. However, overall SFRC performance is restricted by inefficient photoelectrochemical reactions. Here we report an efficient SRFC based on a dual-silicon photoelectrochemical cell and a quinone/bromine redox flow battery for in situ solar energy conversion and storage. Using narrow bandgap silicon for efficient photon collection and fast redox couples for rapid interface charge injection, our device shows an optimal solar-to-chemical conversion efficiency of ∼5.9% and an overall photon-chemical-electricity energy conversion efficiency of ∼3.2%, which, to our knowledge, outperforms previously reported SRFCs. The proposed SRFC can be self-photocharged to 0.8 V and delivers a discharge capacity of 730 mAh l(-1). Our work may guide future designs for highly efficient solar rechargeable devices.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Inkjet 3D printing of UV and thermal cure silicone elastomers for dielectric elastomer actuators

Science.gov (United States)

McCoul, David; Rosset, Samuel; Schlatter, Samuel; Shea, Herbert

2017-12-01

Dielectric elastomer actuators (DEAs) are an attractive form of electromechanical transducer, possessing high energy densities, an efficient design, mechanical compliance, high speed, and noiseless operation. They have been incorporated into a wide variety of devices, such as microfluidic systems, cell bioreactors, tunable optics, haptic displays, and actuators for soft robotics. Fabrication of DEA devices is complex, and the majority are inefficiently made by hand. 3D printing offers an automated and flexible manufacturing alternative that can fabricate complex, multi-material, integrated devices consistently and in high resolution. We present a novel additive manufacturing approach to DEA devices in which five commercially available, thermal and UV-cure DEA silicone rubber materials have been 3D printed with a drop-on-demand, piezoelectric inkjet system. Using this process, 3D structures and high-quality silicone dielectric elastomer membranes as thin as 2 μm have been printed that exhibit mechanical and actuation performance at least as good as conventionally blade-cast membranes. Printed silicone membranes exhibited maximum tensile strains of up to 727%, and DEAs with printed silicone dielectrics were actuated up to 6.1% area strain at a breakdown strength of 84 V μm-1 and also up to 130 V μm-1 at 2.4% strain. This approach holds great potential to manufacture reliable, high-performance DEA devices with high throughput.

Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

International Nuclear Information System (INIS)

Neamen, D.; Shedd, W.; Buchanan, B.

1975-01-01

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

Epitaxial growth of silicon for layer transfer

Science.gov (United States)

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Integration of the end cap TEC+ of the CMS silicon strip tracker

Energy Technology Data Exchange (ETDEWEB)

Bremer, Richard

2008-04-28

CMS is the first large experiment of high-energy particle physics whose inner tracking system is exclusively instrumented with silicon detector modules. This tracker comprises 15 148 silicon strip modules enclosing the interaction point in 10-12 layers. The 1. Physikalisches Institut B of RWTH Aachen was deeply involved in the completion of the end caps of the tracking system. The institute played a leading role in the end cap design, produced virtually all support structures and several important electrical components, designed and built the laser alignment system of the tracker, performed system tests and finally integrated one of the two end caps in Aachen. This integration constitutes the central part of the present thesis work. The main focus was on the development of methods to recognise defects early in the integration process and to assert the detector's functionality. Characteristic quantities such as the detector noise or the optical gain of the readout chain were determined during integration as well as during a series of tests performed after transport of the end cap from Aachen to CERN. The procedures followed during the mechanical integration of the detector and during the commissioning of integrated sectors are explained, and the software packages developed for quality assurance are described. In addition, results of the detector readout are presented. During the integration phase, sub-structures of the end cap - named petals - were subjected to a reception test which has also been designed and operated as part of this thesis work. The test setup and software developed for the test are introduced and an account of the analysis of the recorded data is given. Before the end cap project entered the production phase, a final test beam experiment was performed in which the suitability of a system of two fully equipped petals for operation at the LHC was checked. The measured ratio of the signal induced in the silicon sensors by minimal ionising

Integration of the end cap TEC+ of the CMS silicon strip tracker

International Nuclear Information System (INIS)

Bremer, Richard

2008-01-01

CMS is the first large experiment of high-energy particle physics whose inner tracking system is exclusively instrumented with silicon detector modules. This tracker comprises 15 148 silicon strip modules enclosing the interaction point in 10-12 layers. The 1. Physikalisches Institut B of RWTH Aachen was deeply involved in the completion of the end caps of the tracking system. The institute played a leading role in the end cap design, produced virtually all support structures and several important electrical components, designed and built the laser alignment system of the tracker, performed system tests and finally integrated one of the two end caps in Aachen. This integration constitutes the central part of the present thesis work. The main focus was on the development of methods to recognise defects early in the integration process and to assert the detector's functionality. Characteristic quantities such as the detector noise or the optical gain of the readout chain were determined during integration as well as during a series of tests performed after transport of the end cap from Aachen to CERN. The procedures followed during the mechanical integration of the detector and during the commissioning of integrated sectors are explained, and the software packages developed for quality assurance are described. In addition, results of the detector readout are presented. During the integration phase, sub-structures of the end cap - named petals - were subjected to a reception test which has also been designed and operated as part of this thesis work. The test setup and software developed for the test are introduced and an account of the analysis of the recorded data is given. Before the end cap project entered the production phase, a final test beam experiment was performed in which the suitability of a system of two fully equipped petals for operation at the LHC was checked. The measured ratio of the signal induced in the silicon sensors by minimal ionising particles

Towards a fully integrated indium-phosphide membrane on silicon photonics platform

NARCIS (Netherlands)

van Engelen, J.P.; Pogoretskiy, V.; Smit, M.K.; van der Tol, J.J.G.M.; Jiao, Y.

2017-01-01

Recently a uni-traveling-carrier photodetector with high speed (> 67GHz) and a high-gain optical amplifier (110/cm at 4 kA/cm2) have been demonstrated using the InP membrane-on-Silicon (IMOS) integration technology. Passives in IMOS have shown features comparable to SOI platforms due to the tight

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

Science.gov (United States)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Science.gov (United States)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Inorganic Photovoltaics Materials and Devices: Past, Present, and Future

Science.gov (United States)

Hepp, Aloysius F.; Bailey, Sheila G.; Rafaelle, Ryne P.

2005-01-01

This report describes recent aspects of advanced inorganic materials for photovoltaics or solar cell applications. Specific materials examined will be high-efficiency silicon, gallium arsenide and related materials, and thin-film materials, particularly amorphous silicon and (polycrystalline) copper indium selenide. Some of the advanced concepts discussed include multi-junction III-V (and thin-film) devices, utilization of nanotechnology, specifically quantum dots, low-temperature chemical processing, polymer substrates for lightweight and low-cost solar arrays, concentrator cells, and integrated power devices. While many of these technologies will eventually be used for utility and consumer applications, their genesis can be traced back to challenging problems related to power generation for aerospace and defense. Because this overview of inorganic materials is included in a monogram focused on organic photovoltaics, fundamental issues and metrics common to all solar cell devices (and arrays) will be addressed.

Characterization of Czochralski silicon detectors

OpenAIRE

Luukka, Panja-Riina

2006-01-01

This thesis describes the characterization of irradiated and non-irradiated segmented detectors made of high-resistivity (>1 kΩcm) magnetic Czochralski (MCZ) silicon. It is shown that the radiation hardness (RH) of the protons of these detectors is higher than that of devices made of traditional materials such as Float Zone (FZ) silicon or Diffusion Oxygenated Float Zone (DOFZ) silicon due to the presence of intrinsic oxygen (> 5 × 1017 cm−3). The MCZ devices therefore present an interesting ...

Energy Conversion Properties of ZnSiP2, a Lattice-Matched Material for Silicon-Based Tandem Photovoltaics

Energy Technology Data Exchange (ETDEWEB)

Martinez, Aaron D.; Warren, Emily L.; Gorai, Prashun; Borup, Kasper A.; Krishna, Lakshmi; Kuciauskas, Darius; Dippo, Patricia C.; Ortiz, Brenden R.; Stradins, Paul; Stevanovic, Vladan; Toberer, Eric S.; Tamboli, Adele C.

2016-11-21

ZnSiP2 demonstrates promising potential as an optically active material on silicon. There has been a longstanding need for wide band gap materials that can be integrated with Si for tandem photovoltaics and other optoelectronic applications. ZnSiP2 is an inexpensive, earth abundant, wide band gap material that is stable and lattice matched with silicon. This conference proceeding summarizes our PV-relevant work on bulk single crystal ZnSiP2, highlighting the key findings and laying the ground work for integration into Si-based tandem devices.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Single- and double- lumen silicone breast implant integrity: prospective evaluation of MR and US criteria.

Science.gov (United States)

Berg, W A; Caskey, C I; Hamper, U M; Kuhlman, J E; Anderson, N D; Chang, B W; Sheth, S; Zerhouni, E A

1995-10-01

To evaluate the accuracy of magnetic resonance (MR) and ultrasound (US) criteria for breast implant integrity. One hundred twenty-two single-lumen silicone breast implants and 22 bilumen implants were evaluated with surface coil MR imaging and US and surgically removed. MR criteria for implant failure were a collapsed implant shell ("linguine sign"), foci of silicone outside the shell ("noose sign"), and extracapsular gel, US criteria were collapsed shell, low-level echoes within the gel, and "snowstorm" echoes of extracapsular silicone. Among single-lumen implants, MR imaging depicted 39 of 40 ruptures, 14 of 28 with minimal leakage; 49 of 54 intact implants were correctly interpreted. US depicted 26 of 40 ruptured implants, four of 28 with minimal leakage, and 30 of 54 intact implants. Among bilumen implants, MR imaging depicted four of five implants with rupture of both lumina and nine of 10 as intact; US depicted one rupture and helped identify two of 10 as intact. Mammography accurately depicted the status of 29 of 30 bilumen implants with MR imaging correlation. MR imaging depicts implant integrity more accurately than US; neither method reliably depicts minimal leakage with shell collapse. Mammography is useful in screening bilumen implant integrity.

The TIGRESS Integrated Plunger ancillary systems for electromagnetic transition rate studies at TRIUMF

International Nuclear Information System (INIS)

Voss, P.; Henderson, R.; Andreoiu, C.; Ashley, R.; Austin, R.A.E.; Ball, G.C.; Bender, P.C.; Bey, A.; Cheeseman, A.; Chester, A.; Cross, D.S.; Drake, T.E.; Garnsworthy, A.B.; Hackman, G.; Holland, R.; Ketelhut, S.; Kowalski, P.; Krücken, R.; Laffoley, A.T.; Leach, K.G.

2014-01-01

The TIGRESS Integrated Plunger device is a new experimental tool for nuclear structure investigations via gamma-ray spectroscopy with post-accelerated beams from the ISAC-II facility at TRIUMF. Several ancillary detection systems integral to the device's capabilities for charged-particle tagging and light-ion identification following a variety of nuclear reaction mechanisms have been constructed and characterized. In particular, a silicon PIN diode wall, an annular silicon segmented detector, and a CsI(Tl) scintillator wall have together enabled particle-gamma correlations for reaction channel selectivity and precision kinematic reconstruction in recent measurements. We highlight the construction, characteristics, and implementation of the device's ancillary detectors as they enable a rich set of electromagnetic transition rate measurements via Doppler-shift lifetime techniques and low-energy Coulomb excitation

Computer-aided engineering of semiconductor integrated circuits

Science.gov (United States)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Substrate-bias effect on the breakdown characteristic in a new silicon high-voltage device structure

International Nuclear Information System (INIS)

Li Qi; Wang Weidong; Zhao Qiuming; Wei Xueming

2012-01-01

A novel silicon double-RESURF LDMOS structure with an improved breakdown characteristic by substrate bias technology (SB) is reported. The P-type epitaxial layer is embedded between an N-type drift region and an N-type substrate to block the conduction path in the off-state and change the distributions of the bulk electric field. The substrate bias strengthens the charge share effect of the drift region near the source, and the vertical electric field peak under the drain is decreased, which is especially helpful in improving the vertical breakdown voltage in a lateral power device with a thin drift region. The numerical results by MEDICI indicate that the breakdown voltage of the proposed device is increased by 97% compared with a conventional LDMOS, while maintaining a lowon-resistance. (semiconductor devices)

Nanostructured silicon for photonics from materials to devices

CERN Document Server

Gaburro, Z; Daldosso, N

2006-01-01

The use of light to channel signals around electronic chips could solve several current problems in microelectronic evolution including: power dissipation, interconnect bottlenecks, input/output from/to optical communication channels, poor signal bandwidth, etc. It is unfortunate that silicon is not a good photonic material: it has a poor light-emission efficiency and exhibits a negligible electro-optical effect. Silicon photonics is a field having the objective of improving the physical properties of silicon; thus turning it into a photonic material and permitting the full convergence of elec

Stable configurations of graphene on silicon

Energy Technology Data Exchange (ETDEWEB)

Javvaji, Brahmanandam; Shenoy, Bhamy Maithry [Department of Aerospace Engineering, Indian Institute of Science, Bangalore 560012 (India); Mahapatra, D. Roy, E-mail: droymahapatra@aero.iisc.ernet.in [Department of Aerospace Engineering, Indian Institute of Science, Bangalore 560012 (India); Ravikumar, Abhilash [Department of Metallurgical and Materials Engineering, National Institute of Technology Karnataka, Surathkal 575025 (India); Hegde, G.M. [Center for Nano Science and Engineering, Indian Institute of Science, Bangalore 560012 (India); Rizwan, M.R. [Department of Metallurgical and Materials Engineering, National Institute of Technology Karnataka, Surathkal 575025 (India)

2017-08-31

Highlights: • Simulations of epitaxial growth process for silicon–graphene system is performed. • Identified the most favourable orientation of graphene sheet on silicon substrate. • Atomic local strain due to the silicon–carbon bond formation is analyzed. - Abstract: Integration of graphene on silicon-based nanostructures is crucial in advancing graphene based nanoelectronic device technologies. The present paper provides a new insight on the combined effect of graphene structure and silicon (001) substrate on their two-dimensional anisotropic interface. Molecular dynamics simulations involving the sub-nanoscale interface reveal a most favourable set of temperature independent orientations of the monolayer graphene sheet with an angle of ∽15° between its armchair direction and [010] axis of the silicon substrate. While computing the favorable stable orientations, both the translation and the rotational vibrations of graphene are included. The possible interactions between the graphene atoms and the silicon atoms are identified from their coordination. Graphene sheet shows maximum bonding density with bond length 0.195 nm and minimum bond energy when interfaced with silicon substrate at 15° orientation. Local deformation analysis reveals probability distribution with maximum strain levels of 0.134, 0.047 and 0.029 for 900 K, 300 K and 100 K, respectively in silicon surface for 15° oriented graphene whereas the maximum probable strain in graphene is about 0.041 irrespective of temperature. Silicon–silicon dimer formation is changed due to silicon–carbon bonding. These results may help further in band structure engineering of silicon–graphene lattice.

Comparative analysis for evaluating the traceability of interventional devices using blood vessel phantom models made of PVA-H or silicone.

Science.gov (United States)

Yu, Chang-Ho; Kwon, Tae-Kyu; Park, Chan Hee; Ohta, Makoto; Kim, Sung Hoon

2015-01-01

In this paper, we investigated the parameters with effective traceability to assess the mechanical properties of interventional devices. In our evaluation system, a box-shaped poly (vinyl alcohol) hydrogel (PVA-H) and silicone were prepared with realistic geometry, and the measurement and evaluation of traceability were carried out on devices using load hand force. The phantom models had a total of five curve pathways to reach the aneurysm sac. Traceability depends on the performance of the interventional devices in order to pass through the curved part of the model simulation track. The traceability of the guide wire was found to be much better than that of the balloon and stent loading catheter, as it reached the aneurysm sac in both phantom models. Observation using the video record is another advantage of our system, because the high transparency of the materials with silicone and PVA-H can allow visualization of the inside of an artery.

Realization of an integrated VDF/TrFE copolymer-on-silicon pyroelectric sensor

NARCIS (Netherlands)

Setiadi, D.; Setiadi, D.; Regtien, Paulus P.L.; Sarro, P.M.

1995-01-01

An integrated pyroelectric sensor based on a vinylidene fluoride trifluoroethylene (VDF/TrFE) copolymer is presented. A silicon substrate that contains FET readout electronics is coated with the VDF/TrFE copolymer film using a spin-coating technique. On-chip poling of the copolymer has been applied

High quality silicon-based substrates for microwave and millimeter wave passive circuits

Science.gov (United States)

Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

2017-09-01

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous

EDITORIAL: Special issue on silicon photonics

Science.gov (United States)

Reed, Graham; Paniccia, Mario; Wada, Kazumi; Mashanovich, Goran

2008-06-01

The technology now known as silicon photonics can be traced back to the pioneering work of Soref in the mid-1980s (see, for example, Soref R A and Lorenzo J P 1985 Electron. Lett. 21 953). However, the nature of the research conducted today, whilst it builds upon that early work, is unrecognizable in terms of technology metrics such as device efficiency, device data rate and device dimensions, and even in targeted applications areas. Today silicon photonics is still evolving, and is enjoying a period of unprecedented attention in terms of research focus. This has resulted in orders-of-magnitude improvement in device performance over the last few years to levels many thought were impossible. However, despite the existence of the research field for more than two decades, silicon is still regarded as a 'new' optical material, one that is being manipulated and modified to satisfy the requirements of a range of applications. This is somewhat ironic since silicon is one of the best known and most thoroughly studied materials, thanks to the electronics industry that has made silicon its material of choice. The principal reasons for the lack of study of this 'late developer' are that (i) silicon is an indirect bandgap material and (ii) it does not exhibit a linear electro-optic (Pockels) effect. The former condition means that it is difficult to make a laser in silicon based on the intrinsic performance of the material, and consequently, in recent years, researchers have attempted to modify the material to artificially engineer the conditions for lasing to be viable (see, for example, the review text, Jalali B et al 2008 Silicon Lasers in Silicon Photonics: The State of the Art ed G T Reed (New York: Wiley)). The latter condition means that optical modulators are intrinsically less efficient in silicon than in some other materials, particularly when targeting the popular telecommunications wavelengths around 1.55 μm. Therefore researchers have sought alternative

The development of the market for neutron transmutation doped silicon

International Nuclear Information System (INIS)

Herzer, H.; Vieweg-Gutberlet, G.

1984-01-01

Neutron transmutation doped silicon was introduced to the electronic device market in the 1975-1976 time period. Today, neutron transmutation doping is definitely a mature technology applied mainly to semiconductor power devices. There is no doubt that the power device sector will remain the major consumer of NTD silicon in the near future. This paper examines the possible application of NTD silicon to other areas of the semiconductor market, and concludes that the need for NTD silicon will continue to grow and will expand into other applications. Consequently, unless new reactor capacities become available by the end of the decade, NTD silicon applications will probably be limited mainly to power and sensor devices

Silicon-Nitride-based Integrated Optofluidic Biochemical Sensors using a Coupled-Resonator Optical Waveguide

Directory of Open Access Journals (Sweden)

Jiawei eWANG

2015-04-01

Full Text Available Silicon nitride (SiN is a promising material platform for integrating photonic components and microfluidic channels on a chip for label-free, optical biochemical sensing applications in the visible to near-infrared wavelengths. The chip-scale SiN-based optofluidic sensors can be compact due to a relatively high refractive index contrast between SiN and the fluidic medium, and low-cost due to the complementary metal-oxide-semiconductor (CMOS-compatible fabrication process. Here, we demonstrate SiN-based integrated optofluidic biochemical sensors using a coupled-resonator optical waveguide (CROW in the visible wavelengths. The working principle is based on imaging in the far field the out-of-plane elastic-light-scattering patterns of the CROW sensor at a fixed probe wavelength. We correlate the imaged pattern with reference patterns at the CROW eigenstates. Our sensing algorithm maps the correlation coefficients of the imaged pattern with a library of calibrated correlation coefficients to extract a minute change in the cladding refractive index. Given a calibrated CROW, our sensing mechanism in the spatial domain only requires a fixed-wavelength laser in the visible wavelengths as a light source, with the probe wavelength located within the CROW transmission band, and a silicon digital charge-coupled device (CCD / CMOS camera for recording the light scattering patterns. This is in sharp contrast with the conventional optical microcavity-based sensing methods that impose a strict requirement of spectral alignment with a high-quality cavity resonance using a wavelength-tunable laser. Our experimental results using a SiN CROW sensor with eight coupled microrings in the 680nm wavelength reveal a cladding refractive index change of ~1.3 × 10^-4 refractive index unit (RIU, with an average sensitivity of ~281 ± 271 RIU-1 and a noise-equivalent detection limit (NEDL of 1.8 ×10^-8 RIU ~ 1.0 ×10^-4 RIU across the CROW bandwidth of ~1 nm.

Ensembles of indium phosphide nanowires: physical properties and functional devices integrated on non-single crystal platforms

International Nuclear Information System (INIS)

Kobayashi, Nobuhiko P.; Lohn, Andrew; Onishi, Takehiro; Mathai, Sagi; Li, Xuema; Straznicky, Joseph; Wang, Shih-Yuan; Williams, R.S.; Logeeswaran, V.J.; Islam, M.S.

2009-01-01

A new route to grow an ensemble of indium phosphide single-crystal semiconductor nanowires is described. Unlike conventional epitaxial growth of single-crystal semiconductor films, the proposed route for growing semiconductor nanowires does not require a single-crystal semiconductor substrate. In the proposed route, instead of using single-crystal semiconductor substrates that are characterized by their long-range atomic ordering, a template layer that possesses short-range atomic ordering prepared on a non-single-crystal substrate is employed. On the template layer, epitaxial information associated with its short-range atomic ordering is available within an area that is comparable to that of a nanowire root. Thus the template layer locally provides epitaxial information required for the growth of semiconductor nanowires. In the particular demonstration described in this paper, hydrogenated silicon was used as a template layer for epitaxial growth of indium phosphide nanowires. The indium phosphide nanowires grown on the hydrogenerated silicon template layer were found to be single crystal and optically active. Simple photoconductors and pin-diodes were fabricated and tested with the view towards various optoelectronic device applications where group III-V compound semiconductors are functionally integrated onto non-single-crystal platforms. (orig.)

Ensembles of indium phosphide nanowires: physical properties and functional devices integrated on non-single crystal platforms

Energy Technology Data Exchange (ETDEWEB)

Kobayashi, Nobuhiko P.; Lohn, Andrew; Onishi, Takehiro [University of California, Santa Cruz (United States). Baskin School of Engineering; NASA Ames Research Center, Nanostructured Energy Conversion Technology and Research (NECTAR), Advanced Studies Laboratories, Univ. of California Santa Cruz, Moffett Field, CA (United States); Mathai, Sagi; Li, Xuema; Straznicky, Joseph; Wang, Shih-Yuan; Williams, R.S. [Hewlett-Packard Laboratories, Information and Quantum Systems Laboratory, Palo Alto, CA (United States); Logeeswaran, V.J.; Islam, M.S. [University of California Davis, Electrical and Computer Engineering, Davis, CA (United States)

2009-06-15

A new route to grow an ensemble of indium phosphide single-crystal semiconductor nanowires is described. Unlike conventional epitaxial growth of single-crystal semiconductor films, the proposed route for growing semiconductor nanowires does not require a single-crystal semiconductor substrate. In the proposed route, instead of using single-crystal semiconductor substrates that are characterized by their long-range atomic ordering, a template layer that possesses short-range atomic ordering prepared on a non-single-crystal substrate is employed. On the template layer, epitaxial information associated with its short-range atomic ordering is available within an area that is comparable to that of a nanowire root. Thus the template layer locally provides epitaxial information required for the growth of semiconductor nanowires. In the particular demonstration described in this paper, hydrogenated silicon was used as a template layer for epitaxial growth of indium phosphide nanowires. The indium phosphide nanowires grown on the hydrogenerated silicon template layer were found to be single crystal and optically active. Simple photoconductors and pin-diodes were fabricated and tested with the view towards various optoelectronic device applications where group III-V compound semiconductors are functionally integrated onto non-single-crystal platforms. (orig.)

All-solid-state supercapacitors on silicon using graphene from silicon carbide

Energy Technology Data Exchange (ETDEWEB)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au [Environmental Futures Research Institute, Griffith University, Nathan 4111 (Australia); Wood, Barry [Centre for Microscopy and Microanalysis, The University of Queensland, St. Lucia 4072 (Australia)

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

International Nuclear Information System (INIS)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca; Wood, Barry

2016-01-01

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm"−"2 with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

Study of harsh environment operation of flexible ferroelectric memory integrated with PZT and silicon fabric