Test Structures For Bumpy Integrated Circuits

Science.gov (United States)

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Micro-relay technology for energy-efficient integrated circuits

CERN Document Server

Kam, Hei

2015-01-01

This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

Science.gov (United States)

2017-03-01

Despite all actions and concerns, this problem continues to escalate due to offshore fabrication of the integrated circuits ICs [1]. In order to...diagnosis and fault isolation in ICs, as well as the characterization of the functionality of ICs including malicious circuitry. Integrated circuits ...Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits   contains the RF-switch matrix and broad-band (BB) low noise amplifiers (LNAs

Ni-Cr thin film resistor fabrication for GaAs monolithic microwave integrated circuits

International Nuclear Information System (INIS)

Vinayak, Seema; Vyas, H.P.; Muraleedharan, K.; Vankar, V.D.

2006-01-01

Different Ni-Cr alloys were sputter-deposited on silicon nitride-coated GaAs substrates and covered with a spin-coated polyimide layer to develop thin film metal resistors for GaAs monolithic microwave integrated circuits (MMICs). The contact to the resistors was made through vias in the polyimide layer by sputter-deposited Ti/Au interconnect metal. The variation of contact resistance, sheet resistance (R S ) and temperature coefficient of resistance (TCR) of the Ni-Cr resistors with fabrication process parameters such as polyimide curing thermal cycles and surface treatment given to the wafer prior to interconnect metal deposition has been studied. The Ni-Cr thin film resistors exhibited lower R S and higher TCR compared to the as-deposited Ni-Cr film that was not subjected to thermal cycles involved in the MMIC fabrication process. The change in resistivity and TCR values of Ni-Cr films during the MMIC fabrication process was found to be dependent on the Ni-Cr alloy composition

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

Science.gov (United States)

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Computer-aided engineering of semiconductor integrated circuits

Science.gov (United States)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

An optoelectronic integrated device including a laser and its driving circuit

Energy Technology Data Exchange (ETDEWEB)

Matsueda, H.; Nakano, H.; Tanaka, T.P.

1984-10-01

A monolithic optoelectronic integrated circuit (OEIC) including a laser diode, photomonitor and driving and detecting circuits has been fabricated on a semi-insulating GaAs substrate. The OEIC has a horizontal integrating structure which is suitable for realising high-density multifunctional devices. The fabricating process and the static and dynamic characteristics of the optical and electronic elements are described. The preliminary results of the co-operative operation of the laser and its driving circuit are also presented.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

Science.gov (United States)

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Energy-efficient neuron, synapse and STDP integrated circuits.

Science.gov (United States)

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film

International Nuclear Information System (INIS)

Gao, Pingqi; Zhang, Qing

2014-01-01

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm 2  V −1  s −1 , a subthreshold slope as low as 150 mV  dec −1 , operating gate voltages less than 2 V, on/off ratios larger than 10 4 and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. (paper)

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

High transition temperature superconducting integrated circuit

International Nuclear Information System (INIS)

DiIorio, M.S.

1985-01-01

This thesis describes the design and fabrication of the first superconducting integrated circuit capable of operating at over 10K. The primary component of the circuit is a dc SQUID (Superconducting QUantum Interference Device) which is extremely sensitive to magnetic fields. The dc SQUID consists of two superconductor-normal metal-superconductor (SNS) Josephson microbridges that are fabricated using a novel step-edge process which permits the use of high transition temperature superconductors. By utilizing electron-beam lithography in conjunction with ion-beam etching, very small microbridges can be produced. Such microbridges lead to high performance dc SQUIDs with products of the critical current and normal resistance reaching 1 mV at 4.2 K. These SQUIDs have been extensively characterized, and exhibit excellent electrical characteristics over a wide temperature range. In order to couple electrical signals into the SQUID in a practical fashion, a planar input coil was integrated for efficient coupling. A process was developed to incorporate the technologically important high transition temperature superconducting materials, Nb-Sn and Nb-Ge, using integrated circuit techniques. The primary obstacles were presented by the metallurgical idiosyncrasies of the various materials, such as the need to deposit the superconductors at elevated temperatures, 800-900 0 C, in order to achieve a high transition temperature

Vertically integrated circuit development at Fermilab for detectors

International Nuclear Information System (INIS)

Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

2013-01-01

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

Integrated digital superconducting logic circuits for the quantum synthesizer. Report

International Nuclear Information System (INIS)

Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.

2006-11-01

This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-Al x O y /Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

Microwave GaAs Integrated Circuits On Quartz Substrates

Science.gov (United States)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Organic printed photonics: From microring lasers to integrated circuits.

Science.gov (United States)

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-09-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

Mouldable all-carbon integrated circuits.

Science.gov (United States)

Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

2013-01-01

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

Science.gov (United States)

2016-03-01

ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for...originator. ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo...To) October 2015–January 2016 4. TITLE AND SUBTITLE Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

High-voltage integrated transmitting circuit with differential driving for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

2016-01-01

In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

Utilization of process TEG for fabrication of HTS circuits

International Nuclear Information System (INIS)

Hato, T.; Okada, Y.; Maruyama, M.; Suzuki, H.; Wakana, H.; Adachi, S.; Kawabe, U.; Tanabe, K.

2006-01-01

We improved the fabrication process of high-temperature superconducting (HTS) sampler circuits with multilayer structures by utilizing a test elements group (TEG). Among a lot of difficulties in the HTS circuit fabrication process, loss of oxygen is one of the most significant problems. Since the film transition temperature (T c ) has a strong relationship with the resistance at room temperature, we fabricated a test pattern on the same wafer of the circuits and measured the resistance at room temperature by using a prober to estimate the T c of each layer. By introducing the measurement of the normal resistance after each process, we found better process conditions without a T c drop. Moreover, we constructed a low-temperature probing system, in which we can measure the junction TEG. The system enabled feedback of the fabrication condition soon after the junction process. The utilization of the process TEG contributed to reproducible fabrication of HTS circuits and that is a promising advance of the HTS circuit technology

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

Science.gov (United States)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

Micro-coolers fabricated as a component in an integrated circuit

International Nuclear Information System (INIS)

Glover, James; Oxley, Chris H; Khalid, Ata; Cumming, David; Stephen, Alex; Dunn, Geoff

2015-01-01

The packing density and power capacity of integrated electronics is increasing resulting in higher thermal flux densities. Improved thermal management techniques are required and one approach is to include thermoelectric coolers as part of the integrated circuit. An analysis will be described showing that the supporting substrate will have a large influence on the cooling capacity of the thermoelectric cooler. In particular, for materials with a low ZT figure of merit (for example gallium arsenide (GaAs) based compounds) the substrate will have to be substantially thinned to obtain cooling, which may preclude the use of thermoelectric coolers, for example, as part of a GaAs based integrated circuit. Further, using experimental techniques to measure only the small positive cooling temperature difference (ΔT) between the anode (T h ) and the cathode (T c ) contacts can be misinterpreted as cooling when in fact it is heating. (paper)

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Scalable Fabrication of Integrated Nanophotonic Circuits on Arrays of Thin Single Crystal Diamond Membrane Windows.

Science.gov (United States)

Piracha, Afaq H; Rath, Patrik; Ganesan, Kumaravelu; Kühn, Stefan; Pernice, Wolfram H P; Prawer, Steven

2016-05-11

Diamond has emerged as a promising platform for nanophotonic, optical, and quantum technologies. High-quality, single crystalline substrates of acceptable size are a prerequisite to meet the demanding requirements on low-level impurities and low absorption loss when targeting large photonic circuits. Here, we describe a scalable fabrication method for single crystal diamond membrane windows that achieves three major goals with one fabrication method: providing high quality diamond, as confirmed by Raman spectroscopy; achieving homogeneously thin membranes, enabled by ion implantation; and providing compatibility with established planar fabrication via lithography and vertical etching. On such suspended diamond membranes we demonstrate a suite of photonic components as building blocks for nanophotonic circuits. Monolithic grating couplers are used to efficiently couple light between photonic circuits and optical fibers. In waveguide coupled optical ring resonators, we find loaded quality factors up to 66 000 at a wavelength of 1560 nm, corresponding to propagation loss below 7.2 dB/cm. Our approach holds promise for the scalable implementation of future diamond quantum photonic technologies and all-diamond photonic metrology tools.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

Science.gov (United States)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Radiation effects in semiconductors: technologies for hardened integrated circuits

International Nuclear Information System (INIS)

Charlot, J.M.

1983-09-01

Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

Radiation effects in semiconductors: technologies for hardened integrated circuits

International Nuclear Information System (INIS)

Charlot, J.M.

1984-01-01

Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

Microwave integrated circuit for Josephson voltage standards

Science.gov (United States)

Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

1980-01-01

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Integrated polarization beam splitter with relaxed fabrication tolerances

OpenAIRE

Perez-Galacho, D.; Halir, R.; Ortega-Monux, A.; Alonso-Ramos, C.; Zhang, R.; Runge, P.; Janiak, K.; Bach, H-G; Steffan, A. G.; Molina-Fernandez, I.

2013-01-01

Polarization handling is a key requirement for the next generation of photonic integrated circuits (PICs). Integrated polarization beam splitters (PBS) are central elements for polarization management, but their use in PICs is hindered by poor fabrication tolerances. In this work we present a fully passive, highly fabrication tolerant polarization beam splitter, based on an asymmetrical Mach-Zehnder interferometer (MZI) with a Si/SiO2 Periodic Layer Structure (PLS) on top of one of its arms. ...

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

Science.gov (United States)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Integrated biocircuits: engineering functional multicellular circuits and devices

Science.gov (United States)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Fabrication and simulation of organic transistors and functional circuits

Energy Technology Data Exchange (ETDEWEB)

Taylor, D. Martin, E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Patchett, Eifion R.; Williams, Aled [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Ding, Ziqian; Assender, Hazel E. [Department of Materials, Oxford University, Parks Road, Oxford OX1 3PH (United Kingdom); Morrison, John J.; Yeates, Stephen G. [School of Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom)

2015-07-29

Highlights: • Development of roll-to-roll fabrication protocol for organic TFTs and circuits. • Bottom-gate polystyrene/DNTT TFTs much better than top-gate TFTs. • High-yield and high mobility with polystyrene-buffered TPGDA. • Fabrication of functional circuits – ring oscillators and logic gates. • New baseline process allows TFT parameter extraction and circuit simulation. - Abstract: We report the development of a vacuum-evaporation route for the roll-to-roll fabrication of functioning organic circuits. A number of key findings and observations are highlighted which influenced the eventual fabrication protocol adopted. Initially, the role of interface roughness in determining carrier mobility in thin film transistors (TFTs) is investigated. Then it is shown that TFT yield is higher for devices fabricated on a flash-evaporated-plasma-polymerised tri(propyleneglycol) diacrylate (TPGDA) gate dielectric than for TFTs based on a spin-coated polystyrene (PS) dielectric. However, a degradation in mobility is observed which is attributed to the highly polar TPGDA surface. It is shown that high mobility, low gate-leakage currents and excellent stability are restored when the surface of TPGDA was buffered with a thin, spin-coated PS film. The resulting baseline process allowed arrays of functional circuits such as ring oscillators, NOR/NAND logic gates and S–R latches to be fabricated with high yield and their performance to be simulated.

Design and characterization of integrated components for SiN photonic quantum circuits.

Science.gov (United States)

Poot, Menno; Schuck, Carsten; Ma, Xiao-Song; Guo, Xiang; Tang, Hong X

2016-04-04

The design, fabrication, and detailed calibration of essential building blocks towards fully integrated linear-optics quantum computation are discussed. Photonic devices are made from silicon nitride rib waveguides, where measurements on ring resonators show small propagation losses. Directional couplers are designed to be insensitive to fabrication variations. Their offset and coupling lengths are measured, as well as the phase difference between the transmitted and reflected light. With careful calibrations, the insertion loss of the directional couplers is found to be small. Finally, an integrated controlled-NOT circuit is characterized by measuring the transmission through different combinations of inputs and outputs. The gate fidelity for the CNOT operation with this circuit is estimated to be 99.81% after post selection. This high fidelity is due to our robust design, good fabrication reproducibility, and extensive characterizations.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

Science.gov (United States)

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

Science.gov (United States)

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

Science.gov (United States)

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

On-chip multi-wavelength laser sources fabricated using generic photonic integration technology

NARCIS (Netherlands)

Latkowski, S.; Williams, K.A.; Bente, E.A.J.M.

Generic photonic integration technology platforms allow for design and fabrication of large complexity application specific photonic integrated circuits. Monolithic active-passive integration on indium phosphide substrate naturally enables a reliable co-integration of optical gain elements and

Organic-inorganic hybrid material SUNCONNECT® for photonic integrated circuit

Science.gov (United States)

Nawata, Hideyuki; Oshima, Juro; Kashino, Tsubasa

2018-02-01

In this paper, we report the feature and properties about organic-inorganic hybrid material, "SUNCONNECT®" for photonic integrated circuit. "SUNCONNECT®" materials have low propagation loss at 1310nm (0.29dB/cm) and 1550nm (0.45dB/cm) respectively. In addition, the material has high thermal resistance both high temperature annealing test at 300°C and also 260°C solder heat resistance test. For actual device application, high reliability is required. 85°C /85% test was examined by using multi-mode waveguide. As a result, it indicated that variation of insertion loss property was not changed significantly after high temperature / high humidity test. For the application to photonic integrated circuit, it was demonstrated to fabricate polymer optical waveguide by using three different methods. Single-micron core pattern can be fabricated on cladding layer by using UV lithography with proximity gap exposure. Also, single-mode waveguide can be also fabricated with over cladding. On the other hands, "Mosquito method" and imprint method can be applied to fabricate polymer optical waveguide. Remarkably, these two methods can fabricate gradedindex type optical waveguide without using photo mask. In order to evaluate the optical performance, NFP's observation, measurement of insertion loss and propagation loss by cut-back methods were carried out by using each waveguide sample.

Photonic integrated circuits: new challenges for lithography

Science.gov (United States)

Bolten, Jens; Wahlbrink, Thorsten; Prinzen, Andreas; Porschatis, Caroline; Lerch, Holger; Giesecke, Anna Lena

2016-10-01

In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today's low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

Data readout system utilizing photonic integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

2013-10-11

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Integrated circuit and method of arbitration in a network on an integrated circuit.

NARCIS (Netherlands)

2011-01-01

The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

Science.gov (United States)

Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

2016-02-08

Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications.

Lithography for enabling advances in integrated circuits and devices.

Science.gov (United States)

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Organic membrane photonic integrated circuits (OMPICs).

Science.gov (United States)

Amemiya, Tomohiro; Kanazawa, Toru; Hiratani, Takuo; Inoue, Daisuke; Gu, Zhichen; Yamasaki, Satoshi; Urakami, Tatsuhiro; Arai, Shigehisa

2017-08-07

We propose the concept of organic membrane photonic integrated circuits (OMPICs), which incorporate various functions needed for optical signal processing into a flexible organic membrane. We describe the structure of several devices used within the proposed OMPICs (e.g., transmission lines, I/O couplers, phase shifters, photodetectors, modulators), and theoretically investigate their characteristics. We then present a method of fabricating the photonic devices monolithically in an organic membrane and demonstrate the operation of transmission lines and I/O couplers, the most basic elements of OMPICs.

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

Directory of Open Access Journals (Sweden)

Zong Yao

2016-06-01

Full Text Available This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts, the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

Integrated circuits and logic operations based on single-layer MoS2.

Science.gov (United States)

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Integrated polarization beam splitter with relaxed fabrication tolerances.

Science.gov (United States)

Pérez-Galacho, D; Halir, R; Ortega-Moñux, A; Alonso-Ramos, C; Zhang, R; Runge, P; Janiak, K; Bach, H-G; Steffan, A G; Molina-Fernández, Í

2013-06-17

Polarization handling is a key requirement for the next generation of photonic integrated circuits (PICs). Integrated polarization beam splitters (PBS) are central elements for polarization management, but their use in PICs is hindered by poor fabrication tolerances. In this work we present a fully passive, highly fabrication tolerant polarization beam splitter, based on an asymmetrical Mach-Zehnder interferometer (MZI) with a Si/SiO(2) Periodic Layer Structure (PLS) on top of one of its arms. By engineering the birefringence of the PLS we are able to design the MZI arms so that sensitivities to the most critical fabrication errors are greatly reduced. Our PBS design tolerates waveguide width variations of 400nm maintaining a polarization extinction ratio better than 13dB in the complete C-Band.

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

Enchanced total dose damage in junction field effect transistors and related linear integrated circuits

International Nuclear Information System (INIS)

Flament, O.; Autran, J.L.; Roche, P.; Leray, J.L.; Musseau, O.

1996-01-01

Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elevated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits

A photonic circuit for complementary frequency shifting, in-phase quadrature/single sideband modulation and frequency multiplication: analysis and integration feasibility

Science.gov (United States)

Hasan, Mehedi; Hu, Jianqi; Nikkhah, Hamdam; Hall, Trevor

2017-08-01

A novel photonic integrated circuit architecture for implementing orthogonal frequency division multiplexing by means of photonic generation of phase-correlated sub-carriers is proposed. The circuit can also be used for implementing complex modulation, frequency up-conversion of the electrical signal to the optical domain and frequency multiplication. The principles of operation of the circuit are expounded using transmission matrices and the predictions of the analysis are verified by computer simulation using an industry-standard software tool. Non-ideal scenarios that may affect the correct function of the circuit are taken into consideration and quantified. The discussion of integration feasibility is illustrated by a photonic integrated circuit that has been fabricated using 'library' components and which features most of the elements of the proposed circuit architecture. The circuit is found to be practical and may be fabricated in any material platform that offers a linear electro-optic modulator such as organic or ferroelectric thin films hybridized with silicon photonics.

InP-based three-dimensional photonic integrated circuits

Science.gov (United States)

Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

Science.gov (United States)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

Science.gov (United States)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

High-T /SUB c/ Superconducting integrated circuit: a dc SQUID with input coil

International Nuclear Information System (INIS)

Di Iorio, M.S.; Beasley, M.R.

1985-01-01

We have fabricated a high transition temperature superconducting integrated circuit consisting of a dc SQUID and an input coupling coil. The purpose is to ascertain the generic problems associated with constructing a high-T /SUB c/ circuit as well as to fabricate a high performance dc SQUID. The superconductor used for both the SQUID and the input coil is Nb 3 Sn which must be deposited at 800 0 C. Importantly, the insulator separating SQUID and input coil maintains its integrity at this elevated temperature. A hole in the insulator permits contact to the innermost winding of the coil. This contact has been achieved without significant degradation of the superconductivity. Consequently, the device operates over a wide temperature range, from below 4.2 K to near T /SUB c/

Gigahertz flexible graphene transistors for microwave integrated circuits.

Science.gov (United States)

Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

2014-08-26

Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

Fabrication of Circuit QED Quantum Processors, Part 2: Advanced Semiconductor Manufacturing Perspectives

Science.gov (United States)

Michalak, D. J.; Bruno, A.; Caudillo, R.; Elsherbini, A. A.; Falcon, J. A.; Nam, Y. S.; Poletto, S.; Roberts, J.; Thomas, N. K.; Yoscovits, Z. R.; Dicarlo, L.; Clarke, J. S.

Experimental quantum computing is rapidly approaching the integration of sufficient numbers of quantum bits for interesting applications, but many challenges still remain. These challenges include: realization of an extensible design for large array scale up, sufficient material process control, and discovery of integration schemes compatible with industrial 300 mm fabrication. We present recent developments in extensible circuits with vertical delivery. Toward the goal of developing a high-volume manufacturing process, we will present recent results on a new Josephson junction process that is compatible with current tooling. We will then present the improvements in NbTiN material uniformity that typical 300 mm fabrication tooling can provide. While initial results on few-qubit systems are encouraging, advanced processing control is expected to deliver the improvements in qubit uniformity, coherence time, and control required for larger systems. Research funded by Intel Corporation.

Performance of digital integrated circuit technologies at very high temperatures

Energy Technology Data Exchange (ETDEWEB)

Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

1980-01-01

Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

Optoelectronic integrated circuits utilising vertical-cavity surface-emitting semiconductor lasers

International Nuclear Information System (INIS)

Zakharov, S D; Fyodorov, V B; Tsvetkov, V V

1999-01-01

Optoelectronic integrated circuits with additional optical inputs/outputs, in which vertical-cavity surface-emitting (VCSE) lasers perform the data transfer functions, are considered. The mutual relationship and the 'affinity' between optical means for data transfer and processing, on the one hand, and the traditional electronic component base, on the other, are demonstrated in the case of implementation of three-dimensional interconnects with a high transmission capacity. Attention is drawn to the problems encountered when semiconductor injection lasers are used in communication lines. It is shown what role can be played by VCSE lasers in solving these problems. A detailed analysis is made of the topics relating to possible structural and technological solutions in the fabrication of single lasers and of their arrays, and also of the problems hindering integrating of lasers into emitter arrays. Considerable attention is given to integrated circuits with optoelectronic smart pixels. Various technological methods for vertical integration of GaAs VCSE lasers with the silicon substrate of a microcircuit (chip) are discussed. (review)

Thermionic integrated circuits: electronics for hostile environments

International Nuclear Information System (INIS)

Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

1985-01-01

Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

Integrated coherent matter wave circuits

International Nuclear Information System (INIS)

Ryu, C.; Boshier, M. G.

2015-01-01

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

Variational integrators for electric circuits

International Nuclear Information System (INIS)

Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

2013-01-01

In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Derbenwick, G.F.; Hughes, R.C.

1977-01-01

Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

Development of wide range charge integration application specified integrated circuit for photo-sensor

Energy Technology Data Exchange (ETDEWEB)

Katayose, Yusaku, E-mail: katayose@ynu.ac.jp [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan); Ikeda, Hirokazu [Institute of Space and Astronautical Science (ISAS)/Japan Aerospace Exploration Agency (JAXA), 3-1-1 Yoshinodai, Chuo-ku, Sagamihara, Kanagawa 252-5210 (Japan); Tanaka, Manobu [National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Shibata, Makio [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan)

2013-01-21

A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10{sup −4} fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

Energy Technology Data Exchange (ETDEWEB)

Zerrouk, D.

1997-07-18

Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

Integrated optical circuits for numerical computation

Science.gov (United States)

Verber, C. M.; Kenan, R. P.

1983-01-01

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

Analog integrated circuit for micro-gyro interface realized by multi-chip service in Japan; Multi chip service ni yoru micro gyro interface shuseki kairo no sekkei to shisaku

Energy Technology Data Exchange (ETDEWEB)

Maenaka, K.; Fujita, T.; Okamoto, K.; Maeda, M. [Himeji Institute of Technology, Hyogo (Japan)

1998-10-01

This paper deals with an analog integrated circuit for micro-machined gyroscopes with capacitive output. The Integrated circuit was fabricated as a part of the first project from the `Micromachining Multi-Chip Service Cooperative Re-search Committee` organized by The Institute of Electrical Engineers Japan. This multi-chip service project offers a master slice chip with an equivalent of 9 blocks of operational amplifier circuits. Our integrated circuit includes a modulator, demodulator and synchronous rectifier for detecting small changes in the capacitance of a silicon gyroscope. In the paper, the experimental results of fabricated samples will be described. 13 refs., 15 figs.

New Structure for a Six-Port Reflectometer in Monolithic Microwave Integrated-Circuit Technology

OpenAIRE

Wiedmann , Frank; Huyart , Bernard; Bergeault , Eric; Jallet , Louis

1997-01-01

International audience; This paper presents a new structure for a six-port reflectometer which due to its simplicity can be implemented very easily in monolithic microwave integrated-circuit (MMIC) technology. It uses nonmatched diode detectors with a high input impedance which are placed around a phase shifter in conjunction with a power divider for the reference detector. The circuit has been fabricated using the F20 GaAs process of the GEC–Marconi foundry and operates between 1.3 GHz and 3...

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

Science.gov (United States)

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

Science.gov (United States)

Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

2016-02-01

Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed. Copyright © 2015 Elsevier Ltd. All rights reserved.

Secure integrated circuits and systems

CERN Document Server

Verbauwhede, Ingrid MR

2010-01-01

On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

Radio-frequency integrated-circuit engineering

CERN Document Server

Nguyen, Cam

2015-01-01

Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

Integrated optoelectronic materials and circuits for optical interconnects

International Nuclear Information System (INIS)

Hutcheson, L.D.

1988-01-01

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

Flexible circuits with integrated switches for robotic shape sensing

Science.gov (United States)

Harnett, C. K.

2016-05-01

Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutiérrez-Heredia, Gerardo

2010-10-04

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas \\'parylene only\\' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutié rrez-Heredia, Gerardo; Gonzá lez, Luis A.; Alshareef, Husam N.; Gnade, Bruce E.; Quevedo-Ló pez, Manuel Angel Quevedo

2010-01-01

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

Science.gov (United States)

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Integrated optical serializer designed and fabricated in a generic InP based technology

NARCIS (Netherlands)

Stopinski, S.T.; Malinowski, M.; Piramidowicz, R.; Smit, M.K.; Leijtens, X.J.M.

2012-01-01

This work presents design and characterization results of an optical pulse serializer, realized as an Application Specific Photonic Integrated Circuit (ASPIC) in a novel, generic InPbased technology and fabricated in a multi-project wafer run. The measurement results show high-speed (32 Gbit/s)

Design automation for integrated nonlinear logic circuits (Conference Presentation)

Science.gov (United States)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

Design and application of multilayer monolithic microwave integrated circuit transformers

Energy Technology Data Exchange (ETDEWEB)

Economides, S.B

1999-07-01

fabricated on standard foundry processes. With careful modelling it is also feasible to integrate the two couplers into a single tri-filar transformer structure. This is a robust balun topology, which could be widely adopted. A push-pull MESFET amplifier with 8 dB gain demonstrated this at 12 GHz, using the balun chips connected to amplifier circuits. (author)

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

Science.gov (United States)

Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

1991-01-01

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Semiconductors integrated circuit design for manufacturability

CERN Document Server

Balasinki, Artur

2011-01-01

Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

Science.gov (United States)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Semiconductor integrated circuits

International Nuclear Information System (INIS)

Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

1979-01-01

An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

Silicon integrated circuit process

International Nuclear Information System (INIS)

Lee, Jong Duck

1985-12-01

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Silicon integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Lee, Jong Duck

1985-12-15

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Compact beam splitters with deep gratings for miniature photonic integrated circuits: design and implementation aspects.

Science.gov (United States)

Chen, Chin-Hui; Klamkin, Jonathan; Nicholes, Steven C; Johansson, Leif A; Bowers, John E; Coldren, Larry A

2009-09-01

We present an extensive study of an ultracompact grating-based beam splitter suitable for photonic integrated circuits (PICs) that have stringent density requirements. The 10 microm long beam splitter exhibits equal splitting, low insertion loss, and also provides a high extinction ratio in an integrated coherent balanced receiver. We further present the design strategies for avoiding mode distortion in the beam splitter and discuss optimization of the widths of the detectors to improve insertion loss and extinction ratio of the coherent receiver circuit. In our study, we show that the grating-based beam splitter is a competitive technology having low fabrication complexity for ultracompact PICs.

Design of analog integrated circuits and systems

CERN Document Server

Laker, Kenneth R

1994-01-01

This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

Photonic Integrated Circuits

Science.gov (United States)

Krainak, Michael; Merritt, Scott

2016-01-01

Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

A novel readout integrated circuit for ferroelectric FPA detector

Science.gov (United States)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Thermally controlled coupling of a rolled-up microtube integrated with a waveguide on a silicon electronic-photonic integrated circuit.

Science.gov (United States)

Zhong, Qiuhang; Tian, Zhaobing; Veerasubramanian, Venkat; Dastjerdi, M Hadi Tavakoli; Mi, Zetian; Plant, David V

2014-05-01

We report on the first experimental demonstration of the thermal control of coupling strength between a rolled-up microtube and a waveguide on a silicon electronic-photonic integrated circuit. The microtubes are fabricated by selectively releasing a coherently strained GaAs/InGaAs heterostructure bilayer. The fabricated microtubes are then integrated with silicon waveguides using an abruptly tapered fiber probe. By tuning the gap between the microtube and the waveguide using localized heaters, the microtube-waveguide evanescent coupling is effectively controlled. With heating, the extinction ratio of a microtube whispering-gallery mode changes over an 18 dB range, while the resonant wavelength remains approximately unchanged. Utilizing this dynamic thermal tuning effect, we realize coupling modulation of the microtube integrated with the silicon waveguide at 2 kHz with a heater voltage swing of 0-6 V.

Inverted process for graphene integrated circuits fabrication.

Science.gov (United States)

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-06-07

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

International Nuclear Information System (INIS)

Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

2010-01-01

A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Science.gov (United States)

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Method for deposition of a conductor in integrated circuits

Science.gov (United States)

Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

1997-01-01

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Integrated circuits based on conjugated polymer monolayer.

Science.gov (United States)

Li, Mengmeng; Mangalore, Deepthi Kamath; Zhao, Jingbo; Carpenter, Joshua H; Yan, Hongping; Ade, Harald; Yan, He; Müllen, Klaus; Blom, Paul W M; Pisula, Wojciech; de Leeuw, Dago M; Asadi, Kamal

2018-01-31

It is still a great challenge to fabricate conjugated polymer monolayer field-effect transistors (PoM-FETs) due to intricate crystallization and film formation of conjugated polymers. Here we demonstrate PoM-FETs based on a single monolayer of a conjugated polymer. The resulting PoM-FETs are highly reproducible and exhibit charge carrier mobilities reaching 3 cm 2  V -1  s -1 . The high performance is attributed to the strong interactions of the polymer chains present already in solution leading to pronounced edge-on packing and well-defined microstructure in the monolayer. The high reproducibility enables the integration of discrete unipolar PoM-FETs into inverters and ring oscillators. Real logic functionality has been demonstrated by constructing a 15-bit code generator in which hundreds of self-assembled PoM-FETs are addressed simultaneously. Our results provide the state-of-the-art example of integrated circuits based on a conjugated polymer monolayer, opening prospective pathways for bottom-up organic electronics.

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

Science.gov (United States)

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Active components for integrated plasmonic circuits

DEFF Research Database (Denmark)

Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

2009-01-01

We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

Vertically Integrated Circuits at Fermilab

International Nuclear Information System (INIS)

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

2009-01-01

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Parameter tolerance of the SQUID bootstrap circuit

International Nuclear Information System (INIS)

Zhang Guofeng; Dong Hui; Xie Xiaoming; Jiang Mianheng; Zhang Yi; Krause, Hans-Joachim; Braginski, Alex I; Offenhäusser, Andreas

2012-01-01

We recently demonstrated and analysed the voltage-biased SQUID bootstrap circuit (SBC) conceived to suppress the preamplifier noise contribution in the absence of flux modulation readout. Our scheme contains both the additional voltage and current feedbacks. In this study, we analysed the tolerance of the SBC noise suppression performance to spreads in SQUID and SBC circuit parameters. Analytical results were confirmed by experiments. A one-time adjustable current feedback can be used to extend the tolerance to spreads such as those caused by the integrated circuit fabrication process. This should help to improve the fabrication yield of SBC devices integrated on one chip—as required for multi-channel SQUID systems.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

Thermally-isolated silicon-based integrated circuits and related methods

Science.gov (United States)

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Method of making thermally-isolated silicon-based integrated circuits

Science.gov (United States)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.; Bauer, Todd

2017-11-21

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Development of 3D integrated circuits for HEP

International Nuclear Information System (INIS)

Yarema, R.; Fermilab

2006-01-01

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

Science.gov (United States)

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Materials issues in silicon integrated circuit processing

International Nuclear Information System (INIS)

Wittmer, M.; Stimmell, J.; Strathman, M.

1986-01-01

The symposium on ''Materials Issues in Integrated Circuit Processing'' sought to bring together all of the materials issued pertinent to modern integrated circuit processing. The inherent properties of the materials are becoming an important concern in integrated circuit manufacturing and accordingly research in materials science is vital for the successful implementation of modern integrated circuit technology. The session on Silicon Materials Science revealed the advanced stage of knowledge which topics such as point defects, intrinsic and extrinsic gettering and diffusion kinetics have achieved. Adaption of this knowledge to specific integrated circuit processing technologies is beginning to be addressed. The session on Epitaxy included invited papers on epitaxial insulators and IR detectors. Heteroepitaxy on silicon is receiving great attention and the results presented in this session suggest that 3-d integrated structures are an increasingly realistic possibility. Progress in low temperature silicon epitaxy and epitaxy of thin films with abrupt interfaces was also reported. Diffusion and Ion Implantation were well presented. Regrowth of implant-damaged layers and the nature of the defects which remain after regrowth were discussed in no less than seven papers. Substantial progress was also reported in the understanding of amorphising boron implants and the use of gallium implants for the formation of shallow p/sup +/ -layers

60-GHz integrated-circuit high data rate quadriphase shift keying exciter and modulator

Science.gov (United States)

Grote, A.; Chang, K.

1984-01-01

An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modlator packaged into a small volume of 1.8 x 2.5 x 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.

A Fault Tolerant Integrated Circuit Memory

OpenAIRE

Barton, Anthony Francis

1980-01-01

Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

Long-wavelength III-V/silicon photonic integrated circuits

NARCIS (Netherlands)

Roelkens, G.C.; Kuyken, B.; Leo, F.; Hattasan, N.; Ryckeboer, E.M.P.; Muneeb, M.; Hu, C.L.; Malik, A.; Hens, Z.; Baets, R.G.F.; Shimura, Y.; Gencarelli, F.; Vincent, B.; Loo, van de R.; Verheyen, P.A.; Lepage, G.; Campenhout, van J.; Cerutti, L.; Rodriquez, J.B.; Tournie, E.; Chen, X; Nedeljkovic, G.; Mashanovich, G.; Liu, X.; Green, W.S.

2013-01-01

We review our work in the field of short-wave infrared and mid-infrared photonic integrated circuits for applications in spectroscopic sensing systems. Passive silicon waveguide circuits, GeSn photodetectors, the integration of III-V and IV-VI semiconductors on these circuits, and silicon nonlinear

Silicon carbide MOSFET integrated circuit technology

Energy Technology Data Exchange (ETDEWEB)

Brown, D.M.; Downey, E.; Ghezzo, M.; Kretchmer, J.; Krishnamurthy, V.; Hennessy, W.; Michon, G. [General Electric Co., Schenectady, NY (United States). Corporate Research and Development Center

1997-07-16

The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described. These activities resulted in the design, fabrication and demonstration of the World`s first SiC analog IC - a monolithic MOSFET operational amplifier. Research tasks required for the development of a planar SiC MOSFET IC technology included characterization of the SiC/SiO{sub 2} interface using thermally grown oxides: high temperature (350 C) reliability studies of thermally grown oxides: ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes: epitaxial layer characterization: N channel inversion and depletion mode MOSFETs; device isolation methods and finally integrated circuit design, fabrication and testing of the World`s first monolithic SiC operational amplifier IC. These studies defined a SiC n-channel depletion mode MOSFET IC technology and outlined tasks required to improve all types of SiC devices. For instance, high temperature circuit drift instabilities at 350 C were discovered and characterized. This type of instability needs to be understood and resolved because it affects the high temperature reliability of other types of SiC devices. Improvements in SiC wafer surface quality and the use of deposited oxides instead of thermally grown SiO{sub 2} gate dielectrics will probably be required for enhanced reliability. The slow reverse recovery time exhibited by n{sup +}-p diodes formed by N ion implantation is a problem that needs to be resolved for all types of planar bipolar devices. The reproducibility of acceptor implants needs to be improved before CMOS ICs and many types of power device structures will be manufacturable. (orig.) 51 refs.

Compact Circuit Preprocesses Accelerometer Output

Science.gov (United States)

Bozeman, Richard J., Jr.

1993-01-01

Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

Science.gov (United States)

Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

RFID and Memory Devices Fabricated Integrally on Substrates

Science.gov (United States)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

Highly efficient integrated rectifier and voltage boosting circuits for energy harvesting applications

Directory of Open Access Journals (Sweden)

D. Maurath

2008-05-01

Full Text Available This paper presents novel circuit concepts for integrated rectifiers and voltage converting interfaces for energy harvesting micro-generators. In the context of energy harvesting, usually only small voltages are supplied by vibration-driven generators. Therefore, rectification with minimum voltage losses and low reverse currents is an important issue. This is realized by novel integrated rectifiers which were fabricated and are presented in this article. Additionally, there is a crucial need for dynamic load adaptation as well as voltage up-conversion. A circuit concept is presented, which is able to obtain both requirements. This generator interface adapts its input impedance for an optimal energy transfer efficiency. Furthermore, this generator interface provides implicit voltage up-conversion, whereas the generator output energy is stored on a buffer, which is connected to the output of the voltage converting interface. As simulations express, this fully integrated converter is able to boost ac-voltages greater than |0.35 V| to an output dc-voltage of 2.0 V–2.5 V. Thereby, high harvesting efficiencies above 80% are possible within the entire operational range.

INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

OpenAIRE

Krüger, Jens; Gausa, Dominik

2015-01-01

WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

GaAs Photonic Integrated Circuit (PIC) development for high performance communications

Energy Technology Data Exchange (ETDEWEB)

Sullivan, C.T.

1998-03-01

Sandia has established a foundational technology in photonic integrated circuits (PICs) based on the (Al,Ga,In)As material system for optical communication, radar control and testing, and network switching applications at the important 1.3{mu}m/1.55{mu}m wavelengths. We investigated the optical, electrooptical, and microwave performance characteristics of the fundamental building-block PIC elements designed to be as simple and process-tolerant as possible, with particular emphasis placed on reducing optical insertion loss. Relatively conventional device array and circuit designs were built using these PIC elements: (1) to establish a baseline performance standard; (2) to assess the impact of epitaxial growth accuracy and uniformity, and of fabrication uniformity and yield; (3) to validate our theoretical and numerical models; and (4) to resolve the optical and microwave packaging issues associated with building fully packaged prototypes. Novel and more complex PIC designs and fabrication processes, viewed as higher payoff but higher risk, were explored in a parallel effort with the intention of meshing those advances into our baseline higher-yield capability as they mature. The application focus targeted the design and fabrication of packaged solitary modulators meeting the requirements of future wideband and high-speed analog and digital data links. Successfully prototyped devices are expected to feed into more complex PICs solving specific problems in high-performance communications, such as optical beamforming networks for phased array antennas.

Hybdrid integral circuit for proportional chambers

International Nuclear Information System (INIS)

Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

1978-01-01

Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

Integrated circuits, and design and manufacture thereof

Science.gov (United States)

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

Science.gov (United States)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Integrated optical circuit comprising a polarization convertor

NARCIS (Netherlands)

1998-01-01

An integrated optical circuit includes a first device and a second device, which devices are connected by a polarization convertor. The polarization convertor includes a curved section of a waveguide, integrated in the optical circuit. The curved section may have several differently curved

Design and fabrication of ZnO/TiO2-based thin-film inverter circuits using solution processing techniques

International Nuclear Information System (INIS)

Liau, Leo Chau-Kuang; Kuo, Juo-Wei; Chiang, Hsin-Ni

2012-01-01

Novel and cost-effective ceramic-based thin-film inverter circuits, based on two layers of TiO 2 and ZnO films to construct junction field-effect transistors (FETs), were designed and fabricated by solution coating techniques. The double layers of the sol–gel ZnO and TiO 2 films were coated and characterized as a diode according to the current–voltage performance. Two types of FETs, the p-channel (p-FET) and the n-channel (n-FET) devices, were produced using different coating sequences of ZnO and TiO 2 layers. Both of the transistor performances were evaluated by analyzing the source–drain current versus voltage (I ds –V ds ) data with the control of the gate voltage (V g ). The ZnO/TiO 2 -based inverter circuits, such as the complementary-FET device, were further fabricated using the integration of the p-FET and the n-FET. The voltage transfer characteristics of the inverters were estimated by the tests of the input voltage (V in ) versus the output voltage (V out ) for the thin-film inverter circuits. (paper)

Transistor and integrated circuit manufacture

Energy Technology Data Exchange (ETDEWEB)

Colman, D

1978-09-27

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

Transistor and integrated circuit manufacture

International Nuclear Information System (INIS)

Colman, D.

1978-01-01

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

Design of 3D integrated circuits and systems

CERN Document Server

Sharma, Rohit

2014-01-01

Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

Low-loss, compact, and fabrication-tolerant Si-wire 90° waveguide bend using clothoid and normal curves for large scale photonic integrated circuits.

Science.gov (United States)

Fujisawa, Takeshi; Makino, Shuntaro; Sato, Takanori; Saitoh, Kunimasa

2017-04-17

Ultimately low-loss 90° waveguide bend composed of clothoid and normal curves is proposed for dense optical interconnect photonic integrated circuits. By using clothoid curves at the input and output of 90° waveguide bend, straight and bent waveguides are smoothly connected without increasing the footprint. We found that there is an optimum ratio of clothoid curves in the bend and the bending loss can be significantly reduced compared with normal bend. 90% reduction of the bending loss for the bending radius of 4 μm is experimentally demonstrated with excellent agreement between theory and experiment. The performance is compared with the waveguide bend with offset, and the proposed bend is superior to the waveguide bend with offset in terms of fabrication tolerance.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

Directory of Open Access Journals (Sweden)

Kyeonghwan Park

2017-04-01

Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Science.gov (United States)

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

Directory of Open Access Journals (Sweden)

Heck Martijn J.R.

2016-06-01

Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

Science.gov (United States)

Heck, Martijn J. R.

2017-01-01

Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

Silicon nitride tri-layer vertical Y-junction and 3D couplers with arbitrary splitting ratio for photonic integrated circuits.

Science.gov (United States)

Shang, Kuanping; Pathak, Shibnath; Liu, Guangyao; Feng, Shaoqi; Li, Siwei; Lai, Weicheng; Yoo, S J B

2017-05-01

We designed and demonstrated a tri-layer Si3N4/SiO2 photonic integrated circuit capable of vertical interlayer coupling with arbitrary splitting ratios. Based on this multilayer photonic integrated circuit platform with each layer thicknesses of 150 nm, 50 nm, and 150 nm, we designed and simulated the vertical Y-junctions and 3D couplers with arbitrary power splitting ratios between 1:10 and 10:1 and with negligible(< -50 dB) reflection. Based on the design, we fabricated and demonstrated tri-layer vertical Y-junctions with the splitting ratios of 1:1 and 3:2 with excess optical losses of 0.230 dB. Further, we fabricated and demonstrated the 1 × 3 3D couplers with the splitting ratio of 1:1:4 for symmetric structures and variable splitting ratio for asymmetric structures.

Integrated circuit cooled turbine blade

Science.gov (United States)

Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

2017-08-29

A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

Parallel sparse direct solver for integrated circuit simulation

CERN Document Server

Chen, Xiaoming; Yang, Huazhong

2017-01-01

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

International Nuclear Information System (INIS)

Fourie, Coenrad J; Wetzstein, Olaf; Kunert, Jürgen; Ortlepp, Thomas

2011-01-01

Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHT's 1 kA cm −2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

Neural Networks Integrated Circuit for Biomimetics MEMS Microrobot

Directory of Open Access Journals (Sweden)

Ken Saito

2014-06-01

Full Text Available In this paper, we will propose the neural networks integrated circuit (NNIC which is the driving waveform generator of the 4.0, 2.7, 2.5 mm, width, length, height in size biomimetics microelectromechanical systems (MEMS microrobot. The microrobot was made from silicon wafer fabricated by micro fabrication technology. The mechanical system of the robot was equipped with small size rotary type actuators, link mechanisms and six legs to realize the ant-like switching behavior. The NNIC generates the driving waveform using synchronization phenomena such as biological neural networks. The driving waveform can operate the actuators of the MEMS microrobot directly. Therefore, the NNIC bare chip realizes the robot control without using any software programs or A/D converters. The microrobot performed forward and backward locomotion, and also changes direction by inputting an external single trigger pulse. The locomotion speed of the microrobot was 26.4 mm/min when the step width was 0.88 mm. The power consumption of the system was 250 mWh when the room temperature was 298 K.

Method of manufacturing Josephson junction integrated circuits

International Nuclear Information System (INIS)

Jillie, D.W. Jr.; Smith, L.N.

1985-01-01

Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groudplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Pikor, A.; Reiss, E.M.

1980-01-01

Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

Addressable-Matrix Integrated-Circuit Test Structure

Science.gov (United States)

Sayah, Hoshyar R.; Buehler, Martin G.

1991-01-01

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Post irradiation effects (PIE) in integrated circuits

International Nuclear Information System (INIS)

Barnes, C.E.; Shaw, D.C.; Fleetwood, D.M.; Winokur, P.S.

1992-01-01

Post Irradiation Effects (PIE) ranging from normal recovery catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE recipe used for radiation hardness assurance must be chosen with care. In this paper, the authors provide examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

Integrated microchannel cooling in a three dimensional integrated circuit: A thermal management

Directory of Open Access Journals (Sweden)

Wang Kang-Jia

2016-01-01

Full Text Available Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

Refractory silicides for integrated circuits

International Nuclear Information System (INIS)

Murarka, S.P.

1980-01-01

Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

Fabrication of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Holland, S.

1988-06-01

A new process for the fabrication of silicon p-i-n diode radiation detectors is described. The utilization of backside gettering in the fabrication process results in the actual physical removal of detrimental impurities from critical device regions. This reduces the sensitivity of detector properties to processing variables while yielding low diode reverse-leakage currents. In addition, gettering permits the use of processing temperatures compatible with integrated-circuit fabrication. P-channel MOSFETs and silicon p-i-n diodes have been fabricated simultaneously on 10 kΩ/centerreverse arrowdot/cm silicon using conventional integrated-circuit processing techniques. 25 refs., 5 figs

An integrated circuit switch

Science.gov (United States)

Bonin, E. L.

1969-01-01

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

Integrated Circuit Design in US High-Energy Physics

Energy Technology Data Exchange (ETDEWEB)

Geronimo, G. D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Bebek, C. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lippe, H. V. D. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Haller, G. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Grillo, AA [Univ. of California, Santa Cruz, CA (United States); Newcomer, M [Univ. of Pennsylvania, Philadelphia, PA (United States)

2013-07-10

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

Wide-band polarization controller for Si photonic integrated circuits.

Science.gov (United States)

Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

2016-12-15

A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

Directory of Open Access Journals (Sweden)

Seok Young Ji

2018-02-01

Full Text Available The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

Science.gov (United States)

Ji, Seok Young; Choi, Wonsuk; Jeon, Jin-Woo; Chang, Won Seok

2018-01-01

The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag) nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations. PMID:29425144

Analysis and Evaluation of Statistical Models for Integrated Circuits Design

Directory of Open Access Journals (Sweden)

Sáenz-Noval J.J.

2011-10-01

Full Text Available Statistical models for integrated circuits (IC allow us to estimate the percentage of acceptable devices in the batch before fabrication. Actually, Pelgrom is the statistical model most accepted in the industry; however it was derived from a micrometer technology, which does not guarantee reliability in nanometric manufacturing processes. This work considers three of the most relevant statistical models in the industry and evaluates their limitations and advantages in analog design, so that the designer has a better criterion to make a choice. Moreover, it shows how several statistical models can be used for each one of the stages and design purposes.

A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Directory of Open Access Journals (Sweden)

Ming-Zhi Yang

2013-03-01

Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Test and Diagnosis of Integrated Circuits

OpenAIRE

Bosio , Alberto

2015-01-01

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

Science.gov (United States)

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

Science.gov (United States)

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Science.gov (United States)

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Monolithic microwave integrated circuit water vapor radiometer

Science.gov (United States)

Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

1991-01-01

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

An integrated control and readout circuit for implantable multi-target electrochemical biosensing.

Science.gov (United States)

Ghoreishizadeh, Sara S; Baj-Rossi, Camilla; Cavallini, Andrea; Carrara, Sandro; De Micheli, Giovanni

2014-12-01

We describe an integrated biosensor capable of sensing multiple molecular targets using both cyclic voltammetry (CV) and chronoamperometry (CA). In particular, we present our custom IC to realize voltage control and current readout of the biosensors. A mixed-signal circuit block generates sub-Hertz triangular waveform for the biosensors by means of a direct-digital-synthesizer to control CV. A current to pulse-width converter is realized to output the data for CA measurement. The IC is fabricated in 0.18 μm technology. It consumes 220 μW from 1.8 V supply voltage, making it suitable for remotely-powered applications. Electrical measurements show excellent linearity in sub- μA current range. Electrochemical measurements including CA measurements of glucose and lactate and CV measurements of the anti-cancer drug Etoposide have been acquired with the fabricated IC and compared with a commercial equipment. The results obtained with the fabricated IC are in good agreement with those of the commercial equipment for both CV and CA measurements.

Active quenching circuit for a InGaAs single-photon avalanche diode

International Nuclear Information System (INIS)

Zheng Lixia; Wu Jin; Xi Shuiqing; Shi Longxing; Liu Siyang; Sun Weifeng

2014-01-01

We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications. (semiconductor integrated circuits)

Integrated differential high-voltage transmitting circuit for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

2015-01-01

In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

Conductus makes high-Tc integrated circuit

International Nuclear Information System (INIS)

Anon.

1991-01-01

This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step

An analog integrated circuit design laboratory

OpenAIRE

Mondragon-Torres, A.F.; Mayhugh, Jr.; Pineda de Gyvez, J.; Silva-Martinez, J.; Sanchez-Sinencio, E.

2003-01-01

We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the ...

Passive technologies for future large-scale photonic integrated circuits on silicon: polarization handling, light non-reciprocity and loss reduction

Directory of Open Access Journals (Sweden)

Daoxin Dai

2012-03-01

Full Text Available Silicon-based large-scale photonic integrated circuits are becoming important, due to the need for higher complexity and lower cost for optical transmitters, receivers and optical buffers. In this paper, passive technologies for large-scale photonic integrated circuits are described, including polarization handling, light non-reciprocity and loss reduction. The design rule for polarization beam splitters based on asymmetrical directional couplers is summarized and several novel designs for ultra-short polarization beam splitters are reviewed. A novel concept for realizing a polarization splitter–rotator is presented with a very simple fabrication process. Realization of silicon-based light non-reciprocity devices (e.g., optical isolator, which is very important for transmitters to avoid sensitivity to reflections, is also demonstrated with the help of magneto-optical material by the bonding technology. Low-loss waveguides are another important technology for large-scale photonic integrated circuits. Ultra-low loss optical waveguides are achieved by designing a Si3N4 core with a very high aspect ratio. The loss is reduced further to <0.1 dB m−1 with an improved fabrication process incorporating a high-quality thermal oxide upper cladding by means of wafer bonding. With the developed ultra-low loss Si3N4 optical waveguides, some devices are also demonstrated, including ultra-high-Q ring resonators, low-loss arrayed-waveguide grating (demultiplexers, and high-extinction-ratio polarizers.

Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

Energy Technology Data Exchange (ETDEWEB)

Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2016-04-12

In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

Fabricating an organic complementary inverter by integrating two transistors on a single substrate

International Nuclear Information System (INIS)

Wang Jun; Wei Bin; Zhang Jianhua

2008-01-01

Organic complementary inverters were fabricated by integrating two transistors of different electric type on a single substrate. One is a p-type organic heterojunction transistor with a depletion–accumulation mode that acts as a load element. The other is an n-type transistor with an accumulation mode that acts as a drive element. Typical inverter characteristics with a voltage gain of 12 were obtained. Compared with conventional devices, our organic complementary inverter used only one-step patterning of an organic semiconductor, and simultaneously suppressed the leakage current between supply voltage and ground. Therefore, current studies provide a simpler path to fabrication of organic complementary circuits

Pulsed laser-induced SEU in integrated circuits

International Nuclear Information System (INIS)

Buchner, S.; Kang, K.; Stapor, W.J.; Campbell, A.B.; Knudson, A.R.; McDonald, P.; Rivet, S.

1990-01-01

The authors have used a pulsed picosecond laser to measure the threshold for single event upset (SEU) and single event latchup (SEL) for two different kinds of integrated circuits. The relative thresholds show good agreement with published ion upset data. The consistency of the results together with the advantages of using a laser system suggest that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Science.gov (United States)

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Enabling the Internet of Things from integrated circuits to integrated systems

CERN Document Server

2017-01-01

This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardwar...

Analog integrated circuits design for processing physiological signals.

Science.gov (United States)

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

Application specific integrated circuits and hybrid micro circuits for nuclear instrumentation

International Nuclear Information System (INIS)

Chandratre, V.B.; Sukhwani, Menka; Mukhopadhyay, P.K.; Shastrakar, R.S.; Sudheer, M.; Shedam, V.; Keni, Anubha

2009-01-01

Rapid development in semiconductor technology, sensors, detectors and requirements of high energy physics experiments as well as advances in commercially available nuclear instruments have lead to challenges for instrumentation. These challenges are met with development of Application Specific Integrated Circuits and Hybrid Micro Circuits. This paper discusses various activities in ASIC and HMC development in Bhabha Atomic Research Centre. (author)

Adaptive control of power supply for integrated circuits

NARCIS (Netherlands)

2012-01-01

The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally

A novel and simple method of printing flexible conductive circuits on PET fabrics

International Nuclear Information System (INIS)

Wang, Zehong; Wang, Wei; Jiang, Zhikang; Yu, Dan

2017-01-01

Highlights: • A simple preparation of nano-silver conductive ink was proposed. • Conductive pattern was printed on PET fabrics without heat sintering. • The surface resistivity of printed pattern is low to 0.197 Ω cm. - Abstract: Flexible conductive circuits on PET fabrics were fabricated by a simple approach. Firstly, well dispersed nano-silver colloids with average size of 87 nm were synthesized with poly (vinyl pyrrolidone). Then, by adding polyurethane and thickening agent into these colloids, Ag NP-based ink was produced and printed on PET fabrics by screen printing. Conductive patterns were achieved through the swelling process of polyurethane and the decrease of contact resistance between nano-silver particles when immersed in dichloromethane (DCM) and diallyldimethylammonium chloride (DMDAAC) mixed solution. After it was dried at 40 °C,the surface resistivity was about 0.197 Ω cm with width 1.9 mm, and thickness 20 μm. Moreover, the effects of different DCM contents on the conductivity and the film forming ability have been investigated. We believe these foundings will provide some important analysis for printing flexible conductive circuits on textiles.

A novel and simple method of printing flexible conductive circuits on PET fabrics

Energy Technology Data Exchange (ETDEWEB)

Wang, Zehong; Wang, Wei [College of Chemistry, Chemical Engineering and Biotechnology, Donghua University, Shanghai 201620 (China); Key Laboratory of Textile Science & Technology, Ministry of Education (China); Jiang, Zhikang [Saintyear Holding Group Co., Ltd. (China); Yu, Dan, E-mail: vchtian@163.com [College of Chemistry, Chemical Engineering and Biotechnology, Donghua University, Shanghai 201620 (China); Key Laboratory of Textile Science & Technology, Ministry of Education (China); Saintyear Holding Group Co., Ltd. (China)

2017-02-28

Highlights: • A simple preparation of nano-silver conductive ink was proposed. • Conductive pattern was printed on PET fabrics without heat sintering. • The surface resistivity of printed pattern is low to 0.197 Ω cm. - Abstract: Flexible conductive circuits on PET fabrics were fabricated by a simple approach. Firstly, well dispersed nano-silver colloids with average size of 87 nm were synthesized with poly (vinyl pyrrolidone). Then, by adding polyurethane and thickening agent into these colloids, Ag NP-based ink was produced and printed on PET fabrics by screen printing. Conductive patterns were achieved through the swelling process of polyurethane and the decrease of contact resistance between nano-silver particles when immersed in dichloromethane (DCM) and diallyldimethylammonium chloride (DMDAAC) mixed solution. After it was dried at 40 °C,the surface resistivity was about 0.197 Ω cm with width 1.9 mm, and thickness 20 μm. Moreover, the effects of different DCM contents on the conductivity and the film forming ability have been investigated. We believe these foundings will provide some important analysis for printing flexible conductive circuits on textiles.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

Science.gov (United States)

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

Science.gov (United States)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

Science.gov (United States)

Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

2017-05-01

This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

Science.gov (United States)

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Printed organic thin-film transistor-based integrated circuits

International Nuclear Information System (INIS)

Mandal, Saumen; Noh, Yong-Young

2015-01-01

Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

Design structure for in-system redundant array repair in integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Topology Optimization of Building Blocks for Photonic Integrated Circuits

DEFF Research Database (Denmark)

Jensen, Jakob Søndergaard; Sigmund, Ole

2005-01-01

Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

Microphotonic devices for compact planar lightwave circuits and sensor systems

Science.gov (United States)

Cardenas Gonzalez, Jaime

2005-07-01

Higher levels of integration in planar lightwave circuits and sensor systems can reduce fabrication costs and broaden viable applications for optical network and sensor systems. For example, increased integration and functionality can lead to sensor systems that are compact enough for easy transport, rugged enough for field applications, and sensitive enough even for laboratory applications. On the other hand, more functional and compact planar lightwave circuits can make optical networks components less expensive for the metro and access markets in urban areas and allow penetration of fiber to the home. Thus, there is an important area of opportunity for increased integration to provide low cost, compact solutions in both network components and sensor systems. In this dissertation, a novel splitting structure for microcantilever deflection detection is introduced. The splitting structure is designed so that its splitting ratio is dependent on the vertical position of the microcantilever. With this structure, microcantilevers sensitized to detect different analytes or biological agents can be integrated into an array on a single chip. Additionally, the integration of a depolarizer into the optoelectronic integrated circuit in an interferometric fiber optic gyroscope is presented as a means for cost reduction. The savings come in avoiding labor intensive fiber pigtailing steps by permitting batch fabrication of these components. In particular, this dissertation focuses on the design of the waveguides and polarization rotator, and the impact of imperfect components on the performance of the depolarizer. In the area of planar lightwave circuits, this dissertation presents the development of a fabrication process for single air interface bends (SAIBs). SAIBs can increase integration by reducing the area necessary to make a waveguide bend. Fabrication and measurement of a 45° SAIB with a bend efficiency of 93.4% for TM polarization and 92.7% for TE polarization are

Wireless neural recording with single low-power integrated circuit.

Science.gov (United States)

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

Science.gov (United States)

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

2014-01-01

-out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

A complementary metal oxide semiconductor—integrable conditioning circuit for resistive chemical sensor management

International Nuclear Information System (INIS)

Depari, Alessandro; Flammini, Alessandra; De Marcellis, Andrea; Ferri, Giuseppe

2011-01-01

This paper presents a new interface circuit (for MOX-based resistive chemical sensors) capable of overcoming the main limit of the circuits based on the resistance-to-time approach, i.e. the long measuring time with high-value resistances. The system is designed to operate with a single supply of 3.3 V, thus facilitating an ASIC implementation together with digital electronics for a first data analysis and transmission. This is particularly advantageous when the elaboration process requires a large computational load and a data pre-elaboration is advisable. Simulations of the integrable solution of the system have shown the feasibility of the proposed approach. A prototype with discrete components has been furthermore fabricated and experimentally tested, showing good performance in the range 0.5 MΩ to 10 GΩ with a maximum measuring time of 60 ms

A new integrated microwave SQUID circuit design

International Nuclear Information System (INIS)

Erne, S.N.; Finnegan, T.F.

1980-01-01

In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

Directory of Open Access Journals (Sweden)

S. A. Chizhik

2013-01-01

Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

Directory of Open Access Journals (Sweden)

Ming-Zhi Yang

2014-10-01

Full Text Available The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2011-11-01

Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Integrated Circuit Immunity

Science.gov (United States)

Sketoe, J. G.; Clark, Anthony

2000-01-01

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

How complex can integrated optical circuits become?

NARCIS (Netherlands)

Smit, M.K.; Hill, M.T.; Baets, R.G.F.; Bente, E.A.J.M.; Dorren, H.J.S.; Karouta, F.; Koenraad, P.M.; Koonen, A.M.J.; Leijtens, X.J.M.; Nötzel, R.; Oei, Y.S.; Waardt, de H.; Tol, van der J.J.G.M.; Khoe, G.D.

2007-01-01

The integration scale in Photonic Integrated Circuits will be pushed to VLSI-level in the coming decade. This will bring major changes in both application and manufacturing. In this paper developments in Photonic Integration are reviewed and the limits for reduction of device demensions are

Frontiers in Planar Lightwave Circuit Technology Design, Simulation, and Fabrication

CERN Document Server

Janz, Siegfried; Tanev, Stoyan

2005-01-01

This book is the result of the NATO Advanced Research Workshop on Frontiers in Planar Lightwave Circuit Technology, which took place in Ottawa, Canada from September 21-25, 2004. Many of the world’s leading experts in integrated photonic design, theory and experiment were invited to give lectures in their fields of expertise, and participate in discussions on current research and applications, as well as the new directions planar lightwave circuit technology is evolving towards. The sum of their contributions to this book constitutes an excellent record of many key issues and scientific problems in planar lightwave circuit research at the time of writing. In this volume the reader will find detailed overviews of experimental and theoretical work in high index contrast waveguide systems, micro-optical resonators, nonlinear optics, and advanced optical simulation methods, as well as articles describing emerging applications of integrated optics for medical and biological applications.

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2009-02-01

Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

Monolitic integrated circuit for the strobed charge-to-time converter

International Nuclear Information System (INIS)

Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

1985-01-01

The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

Integrated electric circuit CAD system in Minolta Camera Co. Ltd

Energy Technology Data Exchange (ETDEWEB)

Nakagami, Tsuyoshi; Hirata, Sumiaki; Matsumura, Fumihiko

1988-08-26

Development background, fundamental concept, details and future plan of the integrated electric circuit CAD system for OA equipment are presented. The central integrated database is basically intended to store experiences or know-hows, to cover the wide range of data required for designs, and to provide a friendly interface. This easy-to-use integrated database covers the drawing data, parts information, design standards, know-hows and system data. The system contains the circuit design function to support drawing circuit diagrams, the wiring design function to support the wiring and arrangement of printed circuit boards and various parts integratedly, and the function to verify designs, to make full use of parts or technical information, to maintain the system security. In the future, as the system will be wholly in operation, the design period reduction, quality improvement and cost saving will be attained by this integrated design system. (19 figs, 2 tabs)

Power management techniques for integrated circuit design

CERN Document Server

Chen, Ke-Horng

2016-01-01

This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

Integrated coincidence circuits

International Nuclear Information System (INIS)

Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

1976-01-01

The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

Science.gov (United States)

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering ; security; trusted electronics Introduction Integrated Circuit (IC) designs are... Circuit camouflage is hardware obfuscation technology that prevents reverse engineering of a fabricated device by utilizing a relatively small...obfuscated with circuit camouflage technology, this type of attack becomes much more difficult because a reverse engineer cannot extract a gate- level

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

Directory of Open Access Journals (Sweden)

Chih-Ting Lin

2012-08-01

Full Text Available A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

Active Trimming of Hybrid Integrated Circuits

OpenAIRE

Németh, P.; Krémer, P.

1984-01-01

One of the more important fields of the microelectronics industry is the manufacturing of hybrid integrated circuits.An important part of the manufacturing process is concerned with the trimming of the hybrid integratedl circuits. This article deals with the basic principles of active trimming and introduces a microprocessor controlled trimming machine. By comparing active trimming with passive techniques, it can be shown that the active system has some advantages. This article outlines these...

Integrated circuit implementation of fuzzy controllers

OpenAIRE

Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

1996-01-01

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

The integrated circuit IC EMP transient state disturbance effect experiment method investigates

International Nuclear Information System (INIS)

Li Xiaowei

2004-01-01

Transient state disturbance characteristic study on the integrated circuit, IC, need from its coupling path outset. Through cable (aerial) coupling, EMP converts to an pulse current voltage and results in the impact to the integrated circuit I/O orifice passing the cable. Aiming at the armament system construction feature, EMP effect to the integrated circuit, IC inside the system is analyzed. The integrated circuit, IC EMP effect experiment current injection method is investigated and a few experiments method is given. (authors)

An integrated circuit/packet switched video conferencing system

Energy Technology Data Exchange (ETDEWEB)

Kippenhan Junior, H.A.; Lidinsky, W.P.; Roediger, G.A. [Fermi National Accelerator Lab., Batavia, IL (United States). HEP Network Resource Center; Waits, T.A. [Rutgers Univ., Piscataway, NJ (United States). Dept. of Physics and Astronomy

1996-07-01

The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

An integrated circuit/packet switched video conferencing system

International Nuclear Information System (INIS)

Kippenhan Junior, H.A.; Lidinsky, W.P.; Roediger, G.A.; Waits, T.A.

1996-01-01

The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

Wireless Neural Recording With Single Low-Power Integrated Circuit

Science.gov (United States)

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Monolithic photonic integrated circuit with a GaN-based bent waveguide

Science.gov (United States)

Cai, Wei; Qin, Chuan; Zhang, Shuai; Yuan, Jialei; Zhang, Fenghua; Wang, Yongjin

2018-06-01

Integration of a transmitter, waveguide and receiver into a single chip can generate a multicomponent system with multiple functionalities. Here, we fabricate and characterize a GaN-based photonic integrated circuit (PIC) on a GaN-on-silicon platform. With removal of the silicon and back wafer thinning of the epitaxial film, ultrathin membrane-type devices and highly confined suspended GaN waveguides were formed. Two suspended-membrane InGaN/GaN multiple-quantum-well diodes (MQW-diodes) served as an MQW light-emitting diode (MQW-LED) to emit light and an MQW photodiode (MQW-PD) to sense light. The optical interconnects between the MQW-LED and MQW-PD were achieved using the GaN bent waveguide. The GaN-based PIC consisting of an MQW-LED, waveguides and an MQW-PD forms an in-plane light communication system with a data transmission rate of 70 Mbps.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

Directory of Open Access Journals (Sweden)

Chris R. Bowen

2011-05-01

Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

Science.gov (United States)

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

Microwave integrated circuits for space applications

Science.gov (United States)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Technique for selection of transient radiation-hard junction-isolated integrated circuits

International Nuclear Information System (INIS)

Crowley, J.L.; Junga, F.A.; Stultz, T.J.

1976-01-01

A technique is presented which demonstrates the feasibility of selecting junction-isolated integrated circuits (JI/ICS) for use in transient radiation environments. The procedure guarantees that all PNPN paths within the integrated circuit are identified and describes the methods used to determine whether the paths represent latchup susceptible structures. Two examples of the latchup analysis are given involving an SSI and an LSI bipolar junction-isolated integrated circuit

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

International Nuclear Information System (INIS)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-01-01

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Energy Technology Data Exchange (ETDEWEB)

Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

2015-11-15

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Long-wavelength photonic integrated circuits and avalanche photodetectors

Science.gov (United States)

Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

Linear integrated circuits

CERN Document Server

Carr, Joseph

1996-01-01

The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

Diagnosis of soft faults in analog integrated circuits based on fractional correlation

International Nuclear Information System (INIS)

Deng Yong; Shi Yibing; Zhang Wei

2012-01-01

Aiming at the problem of diagnosing soft faults in analog integrated circuits, an approach based on fractional correlation is proposed. First, the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions. Then, the calculated fractional correlation functions are used to form the fault signatures of the CUT. By comparing the fault signatures, the different soft faulty conditions of the CUT are identified and the faults are located. Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits. (semiconductor integrated circuits)

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

Science.gov (United States)

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

2017-01-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

Directory of Open Access Journals (Sweden)

Yuharu Shinki

2017-08-01

Full Text Available This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

Science.gov (United States)

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

2017-08-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Progress in radiation immune thermionic integrated circuits

International Nuclear Information System (INIS)

Lynn, D.K.; McCormick, J.B.

1985-08-01

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

Progress in radiation immune thermionic integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

Infrared transparent graphene heater for silicon photonic integrated circuits.

Science.gov (United States)

Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

2016-04-18

Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

A TDC integrated circuit for drift chamber readout

International Nuclear Information System (INIS)

Passaseo, M.; Petrolo, E.; Veneziano, S.

1995-01-01

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

A TDC integrated circuit for drift chamber readout

Energy Technology Data Exchange (ETDEWEB)

Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

1995-12-11

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

Latch-up in CMOS integrated circuits

International Nuclear Information System (INIS)

Estreich, D.B.; Dutton, R.W.

1978-04-01

An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

A fast charge integrating and shaping circuit

International Nuclear Information System (INIS)

Kulka, Z.; Szoncso, F.

1990-01-01

The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)

Coplanar strips for Josephson voltage standard circuits

International Nuclear Information System (INIS)

Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

2001-01-01

We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

A SQUID Bootstrap Circuit with a Large Parameter Tolerance

International Nuclear Information System (INIS)

Zhang Guo-Feng; Kong Xiang-Yan; Xie Xiao-Ming; Zhang Yi; Krause Hans-Joachim; Offenhäusser Andreas

2013-01-01

The voltage biased (SQUID) bootstrap circuit (SBC) was recently introduced as an effective means to reduce the preamplifier noise contribution. We analyze the tolerances of the SBC noise suppression performance to spreads in SQUID and SBC circuit parameters. It is found that the tolerance to spread mainly caused by the integrated circuit fabrication process could be extended by a one-time adjustable current feedback. A helium-cooled niobium SQUID with a loop inductance of 350 pH is employed to experimentally verify the analysis. From this work, design criteria for fully integrated SBC devices with a high yield can be derived

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

Science.gov (United States)

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Maximum Temperature Detection System for Integrated Circuits

Science.gov (United States)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Fabrication and characterization of aluminum airbridges for superconducting microwave circuits

International Nuclear Information System (INIS)

Chen, Zijun; Kelly, J.; Barends, R.; Bochmann, J.; Chen, Yu; Chiaro, B.; Dunsworth, A.; Jeffrey, E.; Mutus, J. Y.; O'Malley, P. J. J.; Neill, C.; Roushan, P.; Sank, D.; Vainsencher, A.; Wenner, J.; White, T. C.; Megrant, A.; Cleland, A. N.; Martinis, John M.

2014-01-01

Superconducting microwave circuits based on coplanar waveguides (CPW) are susceptible to parasitic slotline modes which can lead to loss and decoherence. We motivate the use of superconducting airbridges as a reliable method for preventing the propagation of these modes. We describe the fabrication of these airbridges on superconducting resonators, which we use to measure the loss due to placing airbridges over CPW lines. We find that the additional loss at single photon levels is small, and decreases at higher drive powers

Radio frequency integrated circuit design for cognitive radio systems

CERN Document Server

Fahim, Amr

2015-01-01

This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

Lateral power transistors in integrated circuits

CERN Document Server

Erlbacher, Tobias

2014-01-01

This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access

OpenAIRE

Massad, Mohamed El; Garg, Siddharth; Tripunitara, Mahesh

2017-01-01

Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and obser...

Speech recognition by means of a three-integrated-circuit set

Energy Technology Data Exchange (ETDEWEB)

Zoicas, A.

1983-11-03

The author uses pattern recognition methods for detecting word boundaries, and monitors incoming speech at 12 millisecond intervals. Frequency is divided into eight bands and analysis is achieved in an analogue interface integrated circuit, a pipeline digital processor and a control integrated circuit. Applications are suggested, including speech input to personal computers. 3 references.

DMILL circuits. The hardened electronics decuples its performances

International Nuclear Information System (INIS)

Anon.

1998-01-01

Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

LC Quadrature Generation in Integrated Circuits

DEFF Research Database (Denmark)

Christensen, Kåre Tais

2001-01-01

Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...

Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

Science.gov (United States)

Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

2015-06-01

Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

Heavy ions testing experimental results on programmable integrated circuits

International Nuclear Information System (INIS)

Velazco, R.; Provost-Grellier, A.

1988-01-01

The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

Smart Power: New power integrated circuit technologies and their applications

Science.gov (United States)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

Interconnect rise time in superconducting integrating circuits

International Nuclear Information System (INIS)

Preis, D.; Shlager, K.

1988-01-01

The influence of resistive losses on the voltage rise time of an integrated-circuit interconnection is reported. A distribution-circuit model is used to present the interconnect. Numerous parametric curves are presented based on numerical evaluation of the exact analytical expression for the model's transient response. For the superconducting case in which the series resistance of the interconnect approaches zero, the step-response rise time is longer but signal strength increases significantly

Integrated circuit for processing a low-frequency signal from a seismic detector

Energy Technology Data Exchange (ETDEWEB)

Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex ' Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

2011-12-15

Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

PETRIC - A positron emission tomography readout integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

2000-11-05

We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

Silicon Photonic Integrated Circuit Mode Multiplexer

DEFF Research Database (Denmark)

Ding, Yunhong; Ou, Haiyan; Xu, Jing

2013-01-01

We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully...

Integrated optical switch circuit operating under FPGA control

NARCIS (Netherlands)

Stabile, R.; Zal, M.; Williams, K.A.; Bienstman, P.; Morthier, G.; Roelkens, G.; et al., xx

2011-01-01

Integrated photonic circuits are enabling an abrupt step change in networking systems providing massive bandwidth and record transmission. The increasing complexity of high connectivity photonic integrated switches requires sophisticated control planes and more intimate high speed electronics. Here

Experimentally verified inductance extraction and parameter study for superconductive integrated circuit wires crossing ground plane holes

International Nuclear Information System (INIS)

Fourie, Coenrad J; Wetzstein, Olaf; Kunert, Juergen; Meyer, Hans-Georg; Toepfer, Hannes

2013-01-01

As the complexity of rapid single flux quantum (RSFQ) circuits increases, both current and power consumption of the circuits become important design criteria. Various new concepts such as inductive biasing for energy efficient RSFQ circuits and inductively coupled RSFQ cells for current recycling have been proposed to overcome increasingly severe design problems. Both of these techniques use ground plane holes to increase the inductance or coupling factor of superconducting integrated circuit wires. New design tools are consequently required to handle the new topographies. One important issue in such circuit design is the accurate calculation of networks of inductances even in the presence of finite holes in the ground plane. We show how a fast network extraction method using InductEx, which is a pre- and post-processor for the magnetoquasistatic field solver FastHenry, is used to calculate the inductances of a set of SQUIDs (superconducting quantum interference devices) with ground plane holes of different sizes. The results are compared to measurements of physical structures fabricated with the IPHT Jena 1 kA cm −2 RSFQ niobium process to verify accuracy. We then do a parameter study and derive empirical equations for fast and useful estimation of the inductance of wires surrounded by ground plane holes. We also investigate practical circuits and show excellent accuracy. (paper)

A new approach of optimization procedure for superconducting integrated circuits

International Nuclear Information System (INIS)

Saitoh, K.; Soutome, Y.; Tarutani, Y.; Takagi, K.

1999-01-01

We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region. (author)

Investigation for connecting waveguide in off-planar integrated circuits.

Science.gov (United States)

Lin, Jie; Feng, Zhifang

2017-09-01

The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

A numerical integration-based yield estimation method for integrated circuits

International Nuclear Information System (INIS)

Liang Tao; Jia Xinzhang

2011-01-01

A novel integration-based yield estimation method is developed for yield optimization of integrated circuits. This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal, the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation (BCT). In order to reduce the estimation variances of the model parameters of the density function, orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations. The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed. Two yield estimation examples, a fourth-order OTA-C filter and a three-dimensional (3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values. Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases. Therefore, our method is more suitable for parametric yield optimization. (semiconductor integrated circuits)

A numerical integration-based yield estimation method for integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Liang Tao; Jia Xinzhang, E-mail: tliang@yahoo.cn [Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

2011-04-15

A novel integration-based yield estimation method is developed for yield optimization of integrated circuits. This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal, the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation (BCT). In order to reduce the estimation variances of the model parameters of the density function, orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations. The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed. Two yield estimation examples, a fourth-order OTA-C filter and a three-dimensional (3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values. Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases. Therefore, our method is more suitable for parametric yield optimization. (semiconductor integrated circuits)

Integration of microelectronic chips in microfluidic systems on printed circuit board

International Nuclear Information System (INIS)

Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

2012-01-01

A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

Science.gov (United States)

2011-09-19

... Integrated Circuit Devices and Components Thereof; Notice of Institution of Investigation; Institution of... integrated circuit devices and components thereof by reason of infringement of certain claims of U.S. Patent... after importation of certain digital televisions containing integrated circuit devices and components...

Trends in integrated circuit design for particle physics experiments

International Nuclear Information System (INIS)

Atkin, E V

2017-01-01

Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation. (paper)

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

Directory of Open Access Journals (Sweden)

Cheng-Yang Liu

2009-12-01

Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

Nano integrated circuit process

International Nuclear Information System (INIS)

Yoon, Yung Sup

2004-02-01

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

Nano integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Yoon, Yung Sup

2004-02-15

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

A new high-voltage level-shifting circuit for half-bridge power ICs

International Nuclear Information System (INIS)

Kong Moufu; Chen Xingbi

2013-01-01

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well. (semiconductor integrated circuits)

116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

International Nuclear Information System (INIS)

Long Shanli; Liu Yan; He Kejun; Tang Xinggang; Chen Qian

2014-01-01

A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is −116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm 2 and the current is 3.5 mA. (semiconductor integrated circuits)

Programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-04-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Reduction of EMC Emissions in Mixed Signal Integrated Circuits with Embedded LIN Driver

Directory of Open Access Journals (Sweden)

P. Hartl

2016-06-01

Full Text Available This paper describes several methods for reduction of electromagnetic emissions (EME of mixed signal integrated circuits (IC. The focus is on the impact that a LIN bus communication block has on a complex IC which contains analog blocks, noisy digital block, micro-core (µC and several types of memories. It is used in an automotive environment, where EMC emission reduction is one of the key success factors. Several proposed methods for EME reduction are described and implemented on three test chips. These methods include current consumption reduction, internal on-chip decoupling, ground separation and different linear voltage regulator topologies. Measurement results of several fabricated test chips are shown and discussed.

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

Science.gov (United States)

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

International Nuclear Information System (INIS)

Takano, H.; Hosogi, K.; Kato, T.

1995-01-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

Science.gov (United States)

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure

Directory of Open Access Journals (Sweden)

Hong-Quan ZHao

2012-01-01

Full Text Available One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD- based arithmetic logic unit (ALU is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.

A miniature rigid/flex salinity measurement device fabricated using printed circuit processing techniques

International Nuclear Information System (INIS)

Broadbent, H A; Ketterl, T P; Reid, C S

2010-01-01

The design, fabrication and initial performance of a single substrate, miniature, low-cost conductivity, temperature, depth (CTD) sensor board with interconnects are presented. In combination these sensors measure ocean salinity. The miniature CTD device board was designed and fabricated as the main component of a 50 mm × 25 mm × 25 mm animal-attached biologger. The board was fabricated using printed circuit processes and consists of two distinct regions on a continuous single liquid crystal polymer substrate: an 18 mm × 28 mm rigid multi-metal sensor section and a 72 mm long flexible interconnect section. The 95% confidence intervals for the conductivity, temperature and pressure sensors were demonstrated to be ±0.083 mS cm −1 , 0.01 °C, and ±0.135 dbar, respectively.

Superconductor-insulator-normal-conductor-insulator-superconductor (Nb/Al{sub x}O{sub y}/Al/Al{sub x}O{sub y}/Nb) process development for integrated circuit applications

Energy Technology Data Exchange (ETDEWEB)

Balashov, D.; Buchholz, F.M.; Schulze, H.; Khabipov, M.I.; Kessel, W.; Niemeyer, J. [Physikalisch-Technische Bundesanstalt, Braunschweig (Germany)

1998-12-01

The paper reports on recent developments in a new technology process in LTS implementation to fabricate intrinsically shunted tunnel junctions. The process has been realized in SINIS Nb/Al{sub x}O{sub y}/Al/Al{sub x}O{sub y}/Nb multilayer thin-film technology. In various test series, circuits containing a large variety of single junctions and junction arrays of different contact areas and sizes were fabricated and measured. By variation of the oxidation parameters the fabrication process has been optimized for application in integrated circuits operating in RSFQ impulse logic. The junction parameter values realized for the critical current density j{sub c} range to up to about j{sub c} = 1000 A cm{sup -2}, those for the characteristic voltage V{sub c} to up to about V{sub c} = 230 {mu}V. The junctions show nearly non-hysteretic current-voltage characteristics; the intra-wafer parameter spread is below 10%. The junctions realized fulfil the requirements imposed for digital RSFQ circuit operation at clock frequencies in the lower GHz frequency range. (author)

Trigger circuits for the PHENIX electromagnetic calorimeter

International Nuclear Information System (INIS)

Frank, S.S.; Britton, C.L. Jr.; Winterberg, A.L.; Young, G.R.

1997-11-01

Monolithic and discrete circuits have been developed to provide trigger signals for the PHENIX electromagnetic calorimeter detector. These trigger circuits are deadtimeless and create overlapping 4 by 4 energy sums, a cosmic muon trigger, and a 144 channel energy sum. The front end electronics of the PHENIX system sample the energy and timing channels at each bunch crossing (BC) but it is not known immediately if this data is of interest. The information from the trigger circuits is used to determine if the data collected is of interest and should be digitized and stored or discarded. This paper presents details of the design, issues affecting circuit performance, characterization of prototypes fabricated in 1.2 microm Orbit CMOS, and integration of the circuits into the EMCal electronics system

Silicon integrated circuits advances in materials and device research

CERN Document Server

Kahng, Dawon

1981-01-01

Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

Science.gov (United States)

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

High-precision high-sensitivity clock recovery circuit for a mobile payment application

International Nuclear Information System (INIS)

Sun Lichong; Yan Na; Min Hao; Ren Wenliang

2011-01-01

This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop. Compared with clock recovery in conventional 13.56 MHz transponders, this circuit can recover a high-precision consecutive carrier clock from the on/off keying (OOK) signal sent by interrogators. Fabricated by a SMIC 0.18-μm EEPROM CMOS process, this chip works from a single power supply as low as 1.5 V Measurement results show that this circuit provides 0.34% frequency deviation and 8 mV sensitivity. (semiconductor integrated circuits)

Multislice imaging of integrated circuits by precession X-ray ptychography.

Science.gov (United States)

Shimomura, Kei; Hirose, Makoto; Takahashi, Yukio

2018-01-01

A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wide Q range and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

3D circuit integration for Vertex and other detectors

Energy Technology Data Exchange (ETDEWEB)

Yarema, Ray; /Fermilab

2007-09-01

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Photonic integrated circuits : a new approach to laser technology

NARCIS (Netherlands)

Piramidowicz, R.; Stopinski, S.T.; Lawniczuk, K.; Welikow, K.; Szczepanski, P.; Leijtens, X.J.M.; Smit, M.K.

2012-01-01

In this work a brief review on photonic integrated circuits (PICs) is presented with a specific focus on integrated lasers and amplifiers. The work presents the history of development of the integration technology in photonics and its comparison to microelectronics. The major part of the review is

A Solder Based Self Assembly Project in an Introductory IC Fabrication Course

Science.gov (United States)

Rao, Madhav; Lusth, John C.; Burkett, Susan L.

2015-01-01

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student's curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course…

Electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and graphical user interface platform for aviation industries training purposes

Science.gov (United States)

Burhan, I.; Azman, A. A.; Othman, R.

2016-10-01

An electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and Visual Basic (VB) platform is fabricated as a supporting tool to existing teaching and learning process, and to achieve the objectives and learning outcomes towards enhancing the student's knowledge and hands-on skill, especially in electro pneumatic devices. The existing learning process for electro pneumatic courses conducted in the classroom does not emphasize on simulation and complex practical aspects. VB is used as the platform for graphical user interface (GUI) while PIC as the interface circuit between the GUI and hardware of electro pneumatic apparatus. Fabrication of electro pneumatic trainer interfacing between PIC and VB has been designed and improved by involving multiple types of electro pneumatic apparatus such as linear drive, air motor, semi rotary motor, double acting cylinder and single acting cylinder. Newly fabricated electro pneumatic trainer microcontroller interface can be programmed and re-programmed for numerous combination of tasks. Based on the survey to 175 student participants, 97% of the respondents agreed that the newly fabricated trainer is user friendly, safe and attractive, and 96.8% of the respondents strongly agreed that there is improvement in knowledge development and also hands-on skill in their learning process. Furthermore, the Lab Practical Evaluation record has indicated that the respondents have improved their academic performance (hands-on skills) by an average of 23.5%.

GaAs integrated circuits and heterojunction devices

Science.gov (United States)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Thermally-induced voltage alteration for integrated circuit analysis

Energy Technology Data Exchange (ETDEWEB)

Cole, E.I. Jr.

2000-06-20

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

Science.gov (United States)

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Single-event effects in analog and mixed-signal integrated circuits

International Nuclear Information System (INIS)

Turflinger, T.L.

1996-01-01

Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested. Analog circuit single-particle transients require modified test techniques and data analysis. Existing work is reviewed and future concerns are outlined

Ultra low-power integrated circuit design for wireless neural interfaces

CERN Document Server

Holleman, Jeremy; Otis, Brian

2014-01-01

Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

Energy Technology Data Exchange (ETDEWEB)

Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

2000-08-10

With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

Hybrid integrated circuit for charge-to-time interval conversion

Energy Technology Data Exchange (ETDEWEB)

Basiladze, S.G.; Dotsenko, Yu.Yu.; Man' yakov, P.K.; Fedorchenko, S.N. (Joint Inst. for Nuclear Research, Dubna (USSR))

The hybrid integrated circuit for charge-to time interval conversion with nanosecond input fast response is described. The circuit can be used in energy measuring channels, time-to-digital converters and in the modified variant in amplitude-to-digital converters. The converter described consists of a buffer amplifier, a linear transmission circuit, a direct current source and a unit of time interval separation. The buffer amplifier represents a current follower providing low input and high output resistances by the current feedback. It is concluded that the described converter excelled the QT100B circuit analogous to it in a number of parameters especially, in thermostability.

Package Holds Five Monolithic Microwave Integrated Circuits

Science.gov (United States)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

Science.gov (United States)

Roham, Masoud; Halpern, Jeffrey M.; Martin, Heidi B.; Chiel, Hillel J.

2015-01-01

An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order ΔΣ modulator (ΔΣM) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 μm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of ~250 fA, ~1.5 pA, ~4.5 pA, and ~17 pA were achieved for input currents in the range of ±5, ±37, ±150, and ±600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 μM wirelessly over a transmission distance of ~0.5 m in flow injection analysis experiments. PMID:18990633

Wireless amperometric neurochemical monitoring using an integrated telemetry circuit.

Science.gov (United States)

Roham, Masoud; Halpern, Jeffrey M; Martin, Heidi B; Chiel, Hillel J; Mohseni, Pedram

2008-11-01

An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order Delta Sigma modulator (Delta Sigma M) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 microm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of approximately 250 fA, approximately 1.5 pA, approximately 4.5 pA, and approximately 17 pA were achieved for input currents in the range of +/-5, +/-37, +/-150, and +/-600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 microM wirelessly over a transmission distance of approximately 0.5 m in flow injection analysis experiments.

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

Energy Technology Data Exchange (ETDEWEB)

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

A CMOS integrated timing discriminator circuit for fast scintillation counters

International Nuclear Information System (INIS)

Jochmann, M.W.

1998-01-01

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

Integrated circuits with emitter coupling and their application in nanosecond nuclear electronics

International Nuclear Information System (INIS)

Basiladze, S.G.

1976-01-01

Principal static and dynamic characteristics are considered of integrated circuits with emitter coupling, as well as problems of signal transmission. Diagrams are given of amplifiers, discriminators, time interval drivers, generators, etc. Systems and units of nanosecond electronics employing integrated circuits with emitter coupling are briefly described

Investigation of the use of microwave image line integrated circuits for use in radiometers and other microwave devices in X-band and above

Science.gov (United States)

Knox, R. M.; Toulios, P. P.; Onoda, G. Y.

1972-01-01

Program results are described in which the use of a/high permittivity rectangular dielectric image waveguide has been investigated for use in microwave and millimeter wavelength circuits. Launchers from rectangular metal waveguide to image waveguide are described. Theoretical and experimental evaluations of the radiation from curved image waveguides are given. Measurements of attenuation due to conductor and dielectric losses, adhesives, and gaps between the dielectric waveguide and the image plane are included. Various passive components are described and evaluations given. Investigations of various techniques for fabrication of image waveguide circuits using ceramic waveguides are also presented. Program results support the evaluation of the image line approach as an advantageous method for realizing low loss integrated electronic circuits for X-band and above.

Natural printed silk substrate circuit fabricated via surface modification using one step thermal transfer and reduction graphene oxide

Science.gov (United States)

Cao, Jiliang; Huang, Zhan; Wang, Chaoxia

2018-05-01

Graphene conductive silk substrate is a preferred material because of its biocompatibility, flexibility and comfort. A flexible natural printed silk substrate circuit was fabricated by one step transfer of graphene oxide (GO) paste from transfer paper to the surface of silk fabric and reduction of the GO to reduced graphene oxide (RGO) using a simple hot press treatment. The GO paste was obtained through ultrasonic stirring exfoliation under low temperature, and presented excellent printing rheological properties at high concentration. The silk fabric was obtained a surface electric resistance as low as 12.15 KΩ cm-1, in the concentration of GO 50 g L-1 and hot press at 220 °C for 120 s. Though the whiteness and strength decreased with the increasing of hot press temperature and time slowly, the electric conductivity of RGO surface modification silk substrate improved obviously. The surface electric resistance of RGO/silk fabrics increased from 12.15 KΩ cm-1 to 18.05 KΩ cm-1, 28.54 KΩ cm-1 and 32.53 KΩ cm-1 after 10, 20 and 30 washing cycles, respectively. The results showed that the printed silk substrate circuit has excellent washability. This process requires no chemical reductant, and the reduction efficiency and reduction degree of GO is high. This time-effective and environmentally-friendly one step thermal transfer and reduction graphene oxide onto natural silk substrate method can be easily used to production of reduced graphene oxide (RGO) based flexible printed circuit.

Design of Microcantilever-Based Biosensor with Digital Feedback Control Circuit

Directory of Open Access Journals (Sweden)

Jayu P. Kalambe

2012-01-01

Full Text Available This paper present the design of cantilever-based biosensors with new readout, which hold promises as fast and cheap “point of care” device as well as interesting research tools. The fabrication process and related issues of the cantilever based bio-sensor are discussed. Coventorware simulation is carried out to analyze the device behavior. A fully integrated control circuit has been designed to solve manufacturing challenge which will take care of positioning of the cantilever instead of creating nanometer gap between the electrodes. The control circuit will solve the manufacturing challenge faced by the readout methods where it is essential to maintain precise gap between the electrodes. The circuit can take care of variation obtained due to fabrication process and maintain the precise gap between the electrodes by electrostatic actuation. The control circuit consist of analog and digital modules. The reliability issues of the sensor are also discussed.

Lithographic technology for microwave integrated circuits

OpenAIRE

Shepherd, PR; Evans, PSA; Ramsey, BJ; Harrison, DJ

1997-01-01

Conductive lithographic films (CLFs) have been developed primarily as substitutes for resin/laminate boards, which share properties with the metallisation patterns used in planar microwave integrated circuits (MICs). The authors examine the microwave properties of the films and show that, although the losses are greater, they have potential as an alternative to the traditional manufacturing process of MICs.

FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

Directory of Open Access Journals (Sweden)

Zhengwei Hao

2012-01-01

Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

Accurate Electromagnetic Modeling Methods for Integrated Circuits

NARCIS (Netherlands)

Sheng, Z.

2010-01-01

The present development of modern integrated circuits (IC’s) is characterized by a number of critical factors that make their design and verification considerably more difficult than before. This dissertation addresses the important questions of modeling all electromagnetic behavior of features on

Lithography requirements in complex VLSI device fabrication

International Nuclear Information System (INIS)

Wilson, A.D.

1985-01-01

Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

Electron commutator on integrated circuits

International Nuclear Information System (INIS)

Demidenko, V.V.

1975-01-01

The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

Integrated circuit cell library

Science.gov (United States)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

International Nuclear Information System (INIS)

Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

2010-01-01

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

A programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-01-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

Single-crystal silicon trench etching for fabrication of highly integrated circuits

Science.gov (United States)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

Integrated Circuits in the Introductory Electronics Laboratory

Science.gov (United States)

English, Thomas C.; Lind, David A.

1973-01-01

Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

Science.gov (United States)

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

Science.gov (United States)

2011-07-14

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-786] In the Matter of Certain Integrated Circuits... sale within the United States after importation of certain integrated circuits, chipsets, and products... after importation of certain integrated circuits, chipsets, and products containing same including...

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

Science.gov (United States)

2010-02-04

... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... (collectively ``Seagate''). Qimonda accuses of infringement certain LSI integrated circuits, as well as certain...

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

Science.gov (United States)

2012-06-13

... of certain radio frequency integrated circuits and devices containing same by reason of infringement... importation of certain radio frequency integrated circuits and devices containing same that infringe one or... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated...

Quantum Bridge Fabrication Using Photolithography

International Nuclear Information System (INIS)

Quinones, R.

2001-01-01

The need for high-speed performance electronics in computers integrated circuits and sensors, require the fabrication of low energy consumption diodes. Nano fabrication methods require new techniques and equipment. We are currently developing a procedure to fabricate a diode based on quantum-effects. The device will act like a traditional diode, but the nanometer scale will allow it to reach high speeds without over heating. This new diode will be on a nano-bridge so it can be attenuated by an electromagnetic wave. The goal is to obtain similar current vs voltage response as in a silicon diode

Low-power analog integrated circuits for wireless ECG acquisition systems.

Science.gov (United States)

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

Directory of Open Access Journals (Sweden)

De-Hao Lu

2010-11-01

Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Optoelectronic circuits in nanometer CMOS technology

CERN Document Server

Atef, Mohamed

2016-01-01

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

Monolithic microwave integrated circuits: Interconnections and packaging considerations

Science.gov (United States)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

1984-01-01

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Monolithic microwave integrated circuits: Interconnections and packaging considerations

Science.gov (United States)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

75 FR 16837 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

Science.gov (United States)

2010-04-02

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-709] In the Matter of Certain Integrated Circuits... importation of certain integrated circuits, chipsets, and products containing same including televisions... importation, or the sale within the United States after importation of certain integrated circuits, chipsets...

Silicon-based optical integrated circuits for terabit communication networks

International Nuclear Information System (INIS)

Svidzinsky, K K

2003-01-01

A brief review is presented of the development of silicon-based optical integrated circuits used as components in modern all-optical communication networks with the terabit-per-second transmission capacity. The designs and technologies for manufacturing these circuits are described and the problems related to their development and application in WDM communication systems are considered. (special issue devoted to the memory of academician a m prokhorov)

Development of integrated thermionic circuits for high-temperature applications

International Nuclear Information System (INIS)

McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.; Derouin, C.; Roybal, L.; Dooley, R.

1981-01-01

A class of devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 0 C is described. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500 0 C environments for extended periods of time

Microcontroller based Integrated Circuit Tester

OpenAIRE

Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

2015-01-01

The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

Status of readout integrated circuits for radiation detector

International Nuclear Information System (INIS)

Moon, B. S.; Hong, S. B.; Cheng, J. E. and others

2001-09-01

In this report, we describe the current status of readout integrated circuits developed for radiation detectors, along with new technologies being applied to this field. The current status of ASCIC chip development related to the readout electronics is also included in this report. Major sources of this report are from product catalogs and web sites of the related industries. In the field of semiconductor process technology in Korea, the current status of the multi-project wafer(MPW) of IDEC, the multi-project chip(MPC) of ISRC and other domestic semiconductor process industries is described. In the case of other countries, the status of the MPW of MOSIS in USA and the MPW of EUROPRACTICE in Europe is studied. This report also describes the technologies and products of readout integrated circuits of industries worldwide

Development of a Multi-User Polyimide-MEMS Fabrication Process and its Application to MicroHotplates

KAUST Repository

Lizardo, Ernesto B.

2013-01-01

Micro-electro-mechanical systems (MEMS) became possible thanks to the silicon based technology used to fabricate integrated circuits. Originally, MEMS fabrication was limited to silicon based techniques and materials, but the expansion of MEMS

Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits.

Science.gov (United States)

Shang, Kuanping; Pathak, Shibnath; Guan, Binbin; Liu, Guangyao; Yoo, S J B

2015-08-10

We design, fabricate, and demonstrate a silicon nitride (Si(3)N(4)) multilayer platform optimized for low-loss and compact multilayer photonic integrated circuits. The designed platform, with 200 nm thick waveguide core and 700 nm interlayer gap, is compatible for active thermal tuning and applicable to realizing compact photonic devices such as arrayed waveguide gratings (AWGs). We achieve ultra-low loss vertical couplers with 0.01 dB coupling loss, multilayer crossing loss of 0.167 dB at 90° crossing angle, 50 μm bending radius, 100 × 2 μm(2) footprint, lateral misalignment tolerance up to 400 nm, and less than -52 dB interlayer crosstalk at 1550 nm wavelength. Based on the designed platform, we demonstrate a 27 × 32 × 2 multilayer star coupler.

Field analysis and enhancement of multi-pole magnetic components fabricated on printed circuit board

International Nuclear Information System (INIS)

Chiu, K.-C.; Chen, C.-S.

2007-01-01

A multi-pole magnetic component magnetized with a fine magnetic pole pitch of less than 1 mm is very difficult to achieve by using traditional methods. Moreover, it requires a precise mechanical process and a complicated magnetization system. Different fine magnetic pole pitches of 300, 350 and 400 μm have been accomplished on 9-pole magnetic components through the printed circuit board (PCB) manufacturing technology. Additionally, another fine magnetic pole pitch of 500 μm was also fabricated on a dual-layered (DL) wire circuit structure to investigate the field enhancement. After measurements, a gain factor of 1.37 was obtained in the field strength. The field variations among different magnetic pole pitches were analyzed in this paper

Integrated Fabrication of a Microgripper

Institute of Scientific and Technical Information of China (English)

无

1999-01-01

Successful implementation of simple mechanism on silicon chip is a prerequisite for monolithic microrobot-ic systems. This paper describes the integrated fabrication of polycrystalline silicon microgripper. Link, fixed andactive joint, and sliding flange structures with dimensions of micrometers have been fabricated on the substrate ofmonocrystalline silicon using silicon microfabrication technology. This microgripper, which may be applied to trans-ducers or sensors, can be batch-fabricated in IC-compatible process. The movable mechanical elements are built onlayers that are later removed, so that they are free for translation and rotation. Under external driving, a microgrip-per cut from substrate would be able to catch tiny filament or small particle with dimension of 10～ 200 micrometers.

A fast novel soft-start circuit for peak current-mode DC—DC buck converters

International Nuclear Information System (INIS)

Li Jie; Yang Miao; Sun Weifeng; Lu Xiaoxia; Xu Shen; Lu Shengli

2013-01-01

A fully integrated soft-start circuit for DC—DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections: an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC—DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 μm CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 μs start-up time. The inductor current and the output voltage increase smoothly over the whole load range. (semiconductor integrated circuits)

Integrated Circuits for Analog Signal Processing

CERN Document Server

2013-01-01

  This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

High-frequency analog integrated circuit design

CERN Document Server

1995-01-01

To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

Substrate optimization for integrated circuit antennas

OpenAIRE

Alexopoulos, N. G.; Katehi, P. B.; Rutledge, D. B.

1982-01-01

Imaging systems in microwaves, millimeter and submillimeter wave applications employ printed circuit antenna elements. The effect of substrate properties is analyzed in this paper by both reciprocity theorem as well as integral equation approach for infinitesimally short as well as finite length dipole and slot elements. Radiation efficiency and substrate surface wave guidance is studied for practical substrate materials as GaAs, Silicon, Quartz and Duroid.

Viewing Integrated-Circuit Interconnections By SEM

Science.gov (United States)

Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

1990-01-01

Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

Directory of Open Access Journals (Sweden)

Arun Kaintura

2018-02-01

Full Text Available Advances in manufacturing process technology are key ensembles for the production of integrated circuits in the sub-micrometer region. It is of paramount importance to assess the effects of tolerances in the manufacturing process on the performance of modern integrated circuits. The polynomial chaos expansion has emerged as a suitable alternative to standard Monte Carlo-based methods that are accurate, but computationally cumbersome. This paper provides an overview of the most recent developments and challenges in the application of polynomial chaos-based techniques for uncertainty quantification in integrated circuits, with particular focus on high-dimensional problems.

A novel fabrication method for surface integration of metal structures into polymers (SIMSIP)

Science.gov (United States)

Carrion-Gonzalez, Hector

Recently developed flexible electronics applications require that the thin metal films embedded on elastomer substrates also be flexible. These electronic systems are radically different in terms of performance and functionality than conventional silicon-based devices. A key question is whether the metal deposited on flexible films can survive large strains without rupture. Cumbersome macro-fabrication methods have been developed for functional and bendable electronics (e.g., interconnects) encapsulated between layers of polymer films. However, future electronic applications may require electronic flexible devices to be in intimate contact with curved surfaces (e.g., retinal implants) and to be robust enough to withstand large and repeated mechanical deformations. In this research, a novel technique for surface integration of metal structures into polymers (SIMSIP) was developed. Surface embedding, as opposed to placing metal on polymers, provides better adherence while leaving the surface accessible for contacts. This was accomplished by first fabricating the micro-scale metal patterns on a quartz or Teflon mother substrate, and then embedding them to a flexible polyimide thin film. The technique was successfully used to embed micro-metal structures of gold (Au), silver (Ag), and copper (Cu) into polyimide films without affecting the functional properties of the either the metals or the polymers. Experimental results confirm the successful surface-embedding of metal structures as narrow as 0.6 microm wide for different geometries commonly used in circuit design. Although similar approaches exist in literature, the proposed methodology provides a simpler and more reliable way of producing flexible circuits/electronics that is also suitable for high volume manufacturing. In order to demonstrate the flexibility of metal interconnects fabricated using the SIMSIP technique, multiple Au electrodes (5 microm and 2.5 microm wide) were tested using the X-theta bending

A microelectromechanical accelerometer fabricated using printed circuit processing techniques

Science.gov (United States)

Rogers, J. E.; Ramadoss, R.; Ozmun, P. M.; Dean, R. N.

2008-01-01

A microelectromechanical systems (MEMS) capacitive-type accelerometer fabricated using printed circuit processing techniques is presented. A Kapton polymide film is used as the structural layer for fabricating the MEMS accelerometer. The accelerometer proof mass along with four suspension beams is defined in the Kapton polyimide film. The proof mass is suspended above a Teflon substrate using a spacer. The deflection of the proof mass is detected using a pair of capacitive sensing electrodes. The top electrode of the accelerometer is defined on the top surface of the Kapton film. The bottom electrode is defined in the metallization on the Teflon substrate. The initial gap height is determined by the distance between the bottom electrode and the Kapton film. For an applied external acceleration (normal to the proof mass), the proof mass deflects toward or away from the fixed bottom electrode due to inertial force. This deflection causes either a decrease or increase in the air-gap height thereby either increasing or decreasing the capacitance between the top and the bottom electrodes. An example PCB MEMS accelerometer with a square proof mass of membrane area 6.4 mm × 6.4 mm is reported. The measured resonant frequency is 375 Hz and the Q-factor in air is 0.52.

A microelectromechanical accelerometer fabricated using printed circuit processing techniques

International Nuclear Information System (INIS)

Rogers, J E; Ramadoss, R; Ozmun, P M; Dean, R N

2008-01-01

A microelectromechanical systems (MEMS) capacitive-type accelerometer fabricated using printed circuit processing techniques is presented. A Kapton polymide film is used as the structural layer for fabricating the MEMS accelerometer. The accelerometer proof mass along with four suspension beams is defined in the Kapton polyimide film. The proof mass is suspended above a Teflon substrate using a spacer. The deflection of the proof mass is detected using a pair of capacitive sensing electrodes. The top electrode of the accelerometer is defined on the top surface of the Kapton film. The bottom electrode is defined in the metallization on the Teflon substrate. The initial gap height is determined by the distance between the bottom electrode and the Kapton film. For an applied external acceleration (normal to the proof mass), the proof mass deflects toward or away from the fixed bottom electrode due to inertial force. This deflection causes either a decrease or increase in the air-gap height thereby either increasing or decreasing the capacitance between the top and the bottom electrodes. An example PCB MEMS accelerometer with a square proof mass of membrane area 6.4 mm × 6.4 mm is reported. The measured resonant frequency is 375 Hz and the Q-factor in air is 0.52

A wireless integrated circuit for 100-channel charge-balanced neural stimulation.

Science.gov (United States)

Thurgood, B K; Warren, D J; Ledbetter, N M; Clark, G A; Harrison, R R

2009-12-01

The authors present the design of an integrated circuit for wireless neural stimulation, along with benchtop and in - vivo experimental results. The chip has the ability to drive 100 individual stimulation electrodes with constant-current pulses of varying amplitude, duration, interphasic delay, and repetition rate. The stimulation is performed by using a biphasic (cathodic and anodic) current source, injecting and retracting charge from the nervous system. Wireless communication and power are delivered over a 2.765-MHz inductive link. Only three off-chip components are needed to operate the stimulator: a 10-nF capacitor to aid in power-supply regulation, a small capacitor (power and command reception. The chip was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process. The chip was able to activate motor fibers to produce muscle twitches via a Utah Slanted Electrode Array implanted in cat sciatic nerve, and to activate sensory fibers to recruit evoked potentials in somatosensory cortex.

InP-based photonic integrated circuit platform on SiC wafer.

Science.gov (United States)

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

CERN Document Server

A Papa, David

2013-01-01

This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

Design of Integrated Circuits Approaching Terahertz Frequencies

DEFF Research Database (Denmark)

Yan, Lei

In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...... heterodyne receivers with requirements of room temperature operation, low system complexity, and high sensitivity, monolithic integrated Schottky diode technology is chosen for the implementation of submillimeterwave components. The corresponding subharmonic mixer and multiplier for a THz radiometer system...

SiGe Integrated Circuit Developments for SQUID/TES Readout

Science.gov (United States)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

2018-03-01

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

Science.gov (United States)

Kumar, Annie; Lee, Shuh-Ying; Yadav, Sachin; Tan, Kian Hua; Loke, Wan Khai; Dong, Yuan; Lee, Kwang Hong; Wicaksono, Satrio; Liang, Gengchiau; Yoon, Soon-Fatt; Antoniadis, Dimitri; Yeo, Yee-Chia; Gong, Xiao

2017-12-11

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an I ON /I OFF ratio of more than 10 6 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

Science.gov (United States)

Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Deeply-etched DBR mirrors for photonic integrated circuits and tunable lasers

NARCIS (Netherlands)

Docter, B.

2009-01-01

Deeply-etched Distributed Bragg Reflector (DBR) mirrors are a new versatile building block for Photonic Integrated Circuits that allows us to create more complex circuits for optical telecommunication applications. The DBR mirrors increase the device design flexibility because the mirrors can be

Transient-induced latchup in CMOS integrated circuits

CERN Document Server

Ker, Ming-Dou

2009-01-01

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

Science.gov (United States)

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Experimental demonstration of interferometric imaging using photonic integrated circuits.

Science.gov (United States)

Su, Tiehui; Scott, Ryan P; Ogden, Chad; Thurman, Samuel T; Kendrick, Richard L; Duncan, Alan; Yu, Runxiang; Yoo, S J B

2017-05-29

This paper reports design, fabrication, and demonstration of a silica photonic integrated circuit (PIC) capable of conducting interferometric imaging with multiple baselines around λ = 1550 nm. The PIC consists of four sets of five waveguides (total of twenty waveguides), each leading to a three-band spectrometer (total of sixty waveguides), after which a tunable Mach-Zehnder interferometer (MZI) constructs interferograms from each pair of the waveguides. A total of thirty sets of interferograms (ten pairs of three spectral bands) is collected by the detector array at the output of the PIC. The optical path difference (OPD) of each interferometer baseline is kept to within 1 µm to maximize the visibility of the interference measurement. We constructed an experiment to utilize the two baselines for complex visibility measurement on a point source and a variable width slit. We used the point source to demonstrate near unity value of the PIC instrumental visibility, and used the variable slit to demonstrate visibility measurement for a simple extended object. The experimental result demonstrates the visibility of baseline 5 and 20 mm for a slit width of 0 to 500 µm in good agreement with theoretical predictions.

Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Engel, G.L., E-mail: gengel@siue.ed [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Hall, M.J.; Proctor, J.M. [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J. [Departments of Chemistry and Physics, Washington University, Saint Louis, MO 63130 (United States)

2009-12-21

This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-mum process (C5N).

Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

International Nuclear Information System (INIS)

Engel, G.L.; Hall, M.J.; Proctor, J.M.; Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J.

2009-01-01

This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-μm process (C5N).

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

Science.gov (United States)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

Graphene integrated circuits: new prospects towards receiver realisation.

Science.gov (United States)

Saeed, Mohamed; Hamed, Ahmed; Wang, Zhenxing; Shaygan, Mehrdad; Neumaier, Daniel; Negra, Renato

2017-12-21

This work demonstrates a design approach which enables the fabrication of fully integrated radio frequency (RF) and millimetre-wave frequency direct-conversion graphene receivers by adapting the frontend architecture to exploit the state-of-the-art performance of the recently reported wafer-scale CVD metal-insulator-graphene (MIG) diodes. As a proof-of-concept, we built a fully integrated microwave receiver in the frequency range 2.1-2.7 GHz employing the strong nonlinearity and the high responsivity of MIG diodes to successfully receive and demodulate complex, digitally modulated communication signals at 2.45 GHz. In addition, the fabricated receiver uses zero-biased MIG diodes and consumes zero dc power. With the flexibility to be fabricated on different substrates, the prototype receiver frontend is fabricated on a low-cost, glass substrate utilising a custom-developed MMIC process backend which enables the high performance of passive components. The measured performance of the prototype makes it suitable for Internet-of-Things (IoT) and Radio Frequency Identification (RFID) systems for medical and communication applications.

Integrated circuit devices in control systems of coal mining complexes

Energy Technology Data Exchange (ETDEWEB)

1983-01-01

Systems of automatic monitoring and control of coal mining complexes developed in the 1960's used electromagnetic relays, thyristors, and flip-flops on transistors of varying conductivity. The circuits' designers, devoted much attention to ensuring spark safety, lowering power consumption, and raising noise immunity and repairability of functional devices. The fast development of integrated circuitry led to the use of microelectronic components in most devices of mine automation. An analysis of specifications and experimental research into integrated circuits (IMS) shows that the series K 176 IMS components made by CMOS technology best meet mine conditions of operation. The use of IMS devices under mine conditions has demonstrated their high reliability. Further development of integrated circuitry involve using microprocessors and microcomputers. (SC)

Vacuum die attach for integrated circuits

Science.gov (United States)

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Integrated all optical transmodulator circuits with non-linear gain elements and tunable optical fibers

NARCIS (Netherlands)

Kuindersma, P.I.; Leijtens, X.J.M.; Zantvoort, van J.H.C.; Waardt, de H.

2012-01-01

We characterize integrated InP circuits for high speed ‘all-optical’ signal processing. Single chip circuits act as optical transistors. Transmodulation is performed by non-linear gain sections. Integrated tunable filters give signal equalization in time domain.

Bridging ultrahigh-Q devices and photonic circuits

Science.gov (United States)

Yang, Ki Youl; Oh, Dong Yoon; Lee, Seung Hoon; Yang, Qi-Fan; Yi, Xu; Shen, Boqiang; Wang, Heming; Vahala, Kerry

2018-05-01

Optical microresonators are essential to a broad range of technologies and scientific disciplines. However, many of their applications rely on discrete devices to attain challenging combinations of ultra-low-loss performance (ultrahigh Q) and resonator design requirements. This prevents access to scalable fabrication methods for photonic integration and lithographic feature control. Indeed, finding a microfabrication bridge that connects ultrahigh-Q device functions with photonic circuits is a priority of the microcavity field. Here, an integrated resonator having a record Q factor over 200 million is presented. Its ultra-low-loss and flexible cavity design brings performance to integrated systems that has been the exclusive domain of discrete silica and crystalline microcavity devices. Two distinctly different devices are demonstrated: soliton sources with electronic repetition rates and high-coherence/low-threshold Brillouin lasers. This multi-device capability and performance from a single integrated cavity platform represents a critical advance for future photonic circuits and systems.

Evaluation of 320x240 pixel LEC GaAs Schottky barrier X-ray imaging arrays, hybridized to CMOS readout circuit based on charge integration

CERN Document Server

Irsigler, R; Alverbro, J; Borglind, J; Froejdh, C; Helander, P; Manolopoulos, S; O'Shea, V; Smith, K

1999-01-01

320x240 pixels GaAs Schottky barrier detector arrays were fabricated, hybridized to silicon readout circuits, and subsequently evaluated. The detector chip was based on semi-insulating LEC GaAs material. The square shaped pixel detector elements were of the Schottky barrier type and had a pitch of 38 mu m. The GaAs wafers were thinned down prior to the fabrication of the ohmic back contact. After dicing, the chips were indium bump, flip-chip bonded to CMOS readout circuits based on charge integration, and finally evaluated. A bias voltage between 50 and 100 V was sufficient to operate the detector. Results on I-V characteristics, noise behaviour and response to X-ray radiation are presented. Images of various objects and slit patterns were acquired by using a standard dental imaging X-ray source. The work done was a part of the XIMAGE project financed by the European Community (Brite-Euram). (author)

Aluminum nitride nanophotonic circuits operating at ultraviolet wavelengths

Energy Technology Data Exchange (ETDEWEB)

Stegmaier, M.; Ebert, J.; Pernice, W. H. P., E-mail: wolfram.pernice@kit.edu [Institute of Nanotechnology, Karlsruhe Institute of Technology, 76133 Karlsruhe (Germany); Meckbach, J. M.; Ilin, K.; Siegel, M. [Institute of Micro- und Nanoelectronic Systems, Karlsruhe Institute of Technology, 76187 Karlsruhe (Germany)

2014-03-03

Aluminum nitride (AlN) has recently emerged as a promising material for integrated photonics due to a large bandgap and attractive optical properties. Exploiting the wideband transparency, we demonstrate waveguiding in AlN-on-Insulator circuits from near-infrared to ultraviolet wavelengths using nanophotonic components with dimensions down to 40 nm. By measuring the propagation loss over a wide spectral range, we conclude that both scattering and absorption of AlN-intrinsic defects contribute to strong attenuation at short wavelengths, thus providing guidelines for future improvements in thin-film deposition and circuit fabrication.

A full feature FASTBUS slave interface using semicustom integrated circuits

International Nuclear Information System (INIS)

Skegg, R.; Daviel, A.; Downing, R.

1986-01-01

Two semi-custom integrated circuits have been designed and manufactured which enable the construction of a full featured FASTBUS slave interface without the need for a detailed knowledge of the FASTBUS protocol. A relatively small amount of board space is required compared to implementations using conventional circuits. The semi-custom devices are described in detail, and an application example is given. (orig.)

Application specific integrated circuit for high temperature oil well applications

Energy Technology Data Exchange (ETDEWEB)

Fallet, T.; Gakkestad, J.; Forre, G.

1994-12-31

This paper describes the design of an integrated BiCMOS circuit for high temperature applications. The circuit contains Pierce oscillators with automatic gain control, and measurements show that it is operating up to 266{sup o}C. The relative frequency variation up to 200 {sup o}C is less than 60 ppm caused mainly by the crystal element itself. 4 refs., 7 figs.

Radiation sensitivity of integrated circuits Pt. 1

International Nuclear Information System (INIS)

Bereczkine Kerenyi, Ilona

1986-01-01

The cosmic ray sensitivity of CMOS integrated circuits are overviewed in three parts. The aim is to analyze the effects of ionizing radiation on the degradation of electronic parameters, the effects of the electric state during irradiation, and the radiation hardening of ICs. In this Part 1 a general introduction of the response of semiconductors to cosmic radiation is given, and the radiation tolerance and hardening of small-scale integrated CMOS ICs is analyzed in detail. The devices include various basic inverters and simple gate ICs. (R.P.)

Silicon wafers for integrated circuit process

OpenAIRE

Leroy , B.

1986-01-01

Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

The RD53A Integrated Circuit

CERN Document Server

Garcia-Sciveres, Maurice

2017-01-01

Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Science.gov (United States)

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

Designing charge-sensitive preamplifiers based on low-noise analog integrated circuits

International Nuclear Information System (INIS)

Agakhanyan, T.M.

1998-01-01

The methodology for designing charge-sensitive preamplifiers on the low-noise analog integral circuits, including all the stages: the mathematical synthesis with optimization of the intermediate function; the scheme-technical synthesis with parametric optimization of the scheme and analysis of draft projects with the parameter verification is presented. The designing is conducted on the basis of requirements for signal parameters and noise indices of the preamplifier. The system of automated designing of the charge-sensitive preamplifiers on the low-noise analog integral circuits is developed [ru

Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

International Nuclear Information System (INIS)

Sohn, S.Y.

1999-01-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach

Inverter circuits on freestanding flexible substrate using ZnO nanoparticles for cost-efficient electronics

Science.gov (United States)

Vidor, Fábio F.; Meyers, Thorsten; Müller, Kathrin; Wirth, Gilson I.; Hilleringmann, Ulrich

2017-11-01

Driven by the Internet of Things (IoT), flexible and transparent smart systems have been intensively researched by the scientific community and by several companies. This technology is already available for consumers in a wide range of innovative products, e.g., flexible displays, radio-frequency identification tags and wearable electronic skins which, for instance, collect and analyze data for medical applications. For these systems, thin-film transistors (TFTs) are the key elements responsible for the driving currents. Solution-based materials such as nanoparticle dispersions avail the fabrication on large-area substrates with high throughput processes. In this study, we discuss the integration of ZnO nanoparticle thin-film transistors and inverter circuits on freestanding polymeric substrates enclosing the main issues concerning the transfer of the integration process from a rigid substrate to a flexible one. The TFTs depict VON between -0.2 and 1 V, ION/IOFF > 104 and field-effect mobility >0.5 cm2 V-1 s-1. Additionally, in order to enhance the transistors and inverters performance, an adaptation on the device configuration, from an inverted coplanar to an inverted staggered setup, was conducted and analyzed. By employing the inverted staggered setup a considerable increase in the contact quality between the semiconductor and the drain and source electrodes was observed. As the integrated devices depict electrical characteristics which enable the fabrication of electronic circuits for the low-cost sector, inverters were fabricated and characterized, evaluating the circuit's gain as function of the applied supply voltage and circuit's geometric ratio.

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

Science.gov (United States)

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

A high-precision synchronization circuit for clock distribution

International Nuclear Information System (INIS)

Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

2015-01-01

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

Wafer-level testing and test during burn-in for integrated circuits

CERN Document Server

Bahukudumbi, Sudarshan

2010-01-01

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

International Nuclear Information System (INIS)

Lashin, A. V.; Kozyrev, A. V.

2015-01-01

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

Boson sampling with integrated optical circuits

International Nuclear Information System (INIS)

Bentivegna, M.

2014-01-01

Simulating the evolution of non-interacting bosons through a linear transformation acting on the system’s Fock state is strongly believed to be hard for a classical computer. This is commonly known as the Boson Sampling problem, and has recently got attention as the first possible way to demonstrate the superior computational power of quantum devices over classical ones. In this paper we describe the quantum optics approach to this problem, highlighting the role of integrated optical circuits.

The single-event effect evaluation technology for nano integrated circuits

International Nuclear Information System (INIS)

Zheng Hongchao; Zhao Yuanfu; Yue Suge; Fan Long; Du Shougang; Chen Maoxin; Yu Chunqing

2015-01-01

Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

Neuromorphic Silicon Neuron Circuits

Science.gov (United States)

Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

2011-01-01

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

Neuromorphic silicon neuron circuits

Directory of Open Access Journals (Sweden)

Giacomo eIndiveri

2011-05-01

Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

On-chip enzymatic microbiofuel cell-powered integrated circuits.

Science.gov (United States)

Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

2017-05-16

A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

Science.gov (United States)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

Energy Technology Data Exchange (ETDEWEB)

Sohn, S.Y

1999-12-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach.

Experimental Verification of Guided-Wave Lumped Circuits Using Waveguide Metamaterials

Science.gov (United States)

Li, Yue; Zhang, Zhijun

2018-04-01

Through the construction and characterization in microwave frequencies, we experimentally demonstrate our recently developed theory of waveguide lumped circuits, i.e., waveguide metatronics [Sci. Adv. 2, e1501790 (2016), 10.1126/sciadv.1501790], as a method to design subwavelength-scaled analog circuits. In the paradigm of waveguide metatronics, numbers of lumped inductors and capacitors are easily integrated functionally inside the waveguide, which is an irreplaceable transmission line in millimeter-wave and terahertz systems with the advantages of low radiation loss and low crosstalk. An example of multiple-ordered metatronic filters with layered structures is fabricated utilizing the technique of substrate integrated waveguides, which can be easily constructed by the printed-circuit-board process. The materials used in the construction are also typical microwave materials with positive permittivity, low loss, and negligible dispersion, imitating the plasmonic materials with negative permittivity in the optical domain. The results verify the theory of waveguide metatronics, which provides an efficient platform of functional lumped circuit design for guided-wave processing.

Thermal measurement a requirement for monolithic microwave integrated circuit design

OpenAIRE

Hopper, Richard; Oxley, C. H.

2008-01-01

The thermal management of structures such as Monolithic Microwave Integrated Circuits (MMICs) is important, given increased circuit packing densities and RF output powers. The paper will describe the IR measurement technology necessary to obtain accurate temperature profiles on the surface of semiconductor devices. The measurement procedure will be explained, including the device mounting arrangement and emissivity correction technique. The paper will show how the measurement technique has be...

Generation of optical vortices in an integrated optical circuit

Science.gov (United States)

Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

2017-09-01

In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

Post-irradiation effects in CMOS integrated circuits

International Nuclear Information System (INIS)

Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

1988-01-01

The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

Micro- and nano-scale optical devices for high density photonic integrated circuits at near-infrared wavelengths

Science.gov (United States)

Chatterjee, Rohit

In this research work, we explore fundamental silicon-based active and passive photonic devices that can be integrated together to form functional photonic integrated circuits. The devices which include power splitters, switches and lenses are studied starting from their physics, their design and fabrication techniques and finally from an experimental standpoint. The experimental results reveal high performance devices that are compatible with standard CMOS fabrication processes and can be easily integrated with other devices for near infrared telecom applications. In Chapter 2, a novel method for optical switching using nanomechanical proximity perturbation technique is described and demonstrated. The method which is experimentally demonstrated employs relatively low powers, small chip footprint and is compatible with standard CMOS fabrication processes. Further, in Chapter 3, this method is applied to develop a hitless bypass switch aimed at solving an important issue in current wavelength division multiplexing systems namely hitless switching of reconfigurable optical add drop multiplexers. Experimental results are presented to demonstrate the application of the nanomechanical proximity perturbation technique to practical situations. In Chapter 4, a fundamental photonic component namely the power splitter is described. Power splitters are important components for any photonic integrated circuits because they help split the power from a single light source to multiple devices on the same chip so that different operations can be performed simultaneously. The power splitters demonstrated in this chapter are based on multimode interference principles resulting in highly compact low loss and highly uniform power splitting to split the power of the light from a single channel to two and four channels. These devices can further be scaled to achieve higher order splitting such as 1x16 and 1x32 power splits. Finally in Chapter 5 we overcome challenges in device

Universal discrete Fourier optics RF photonic integrated circuit architecture.

Science.gov (United States)

Hall, Trevor J; Hasan, Mehedi

2016-04-04

This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

Ultra-low power integrated circuit design circuits, systems, and applications

CERN Document Server

Li, Dongmei; Wang, Zhihua

2014-01-01

This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

Enhanced Impurity-Free Intermixing Bandgap Engineering for InP-Based Photonic Integrated Circuits

Science.gov (United States)

Cui, Xiao; Zhang, Can; Liang, Song; Zhu, Hong-Liang; Hou, Lian-Ping

2014-04-01

Impurity-free intermixing of InGaAsP multiple quantum wells (MQW) using sputtering Cu/SiO2 layers followed by rapid thermal processing (RTP) is demonstrated. The bandgap energy could be modulated by varying the sputtering power and time of Cu, RTP temperature and time to satisfy the demands for lasers, modulators, photodetector, and passive waveguides for the photonic integrated circuits with a simple procedure. The blueshift of the bandgap wavelength of MQW is experimentally investigated on different sputtering and annealing conditions. It is obvious that the introduction of the Cu layer could increase the blueshift more greatly than the common impurity free vacancy disordering technique. A maximum bandgap blueshift of 172 nm is realized with an annealing condition of 750°C and 200s. The improved technique is promising for the fabrication of the active/passive optoelectronic components on a single wafer with simple process and low cost.

Smart fabric sensors and e-textile technologies: a review

International Nuclear Information System (INIS)

Castano, Lina M; Flatau, Alison B

2014-01-01

This paper provides a review of recent developments in the rapidly changing and advancing field of smart fabric sensor and electronic textile technologies. It summarizes the basic principles and approaches employed when building fabric sensors as well as the most commonly used materials and techniques used in electronic textiles. This paper shows that sensing functionality can be created by intrinsic and extrinsic modifications to textile substrates depending on the level of integration into the fabric platform. The current work demonstrates that fabric sensors can be tailored to measure force, pressure, chemicals, humidity and temperature variations. Materials, connectors, fabric circuits, interconnects, encapsulation and fabrication methods associated with fabric technologies prove to be customizable and versatile but less robust than their conventional electronics counterparts. The findings of this survey suggest that a complete smart fabric system is possible through the integration of the different types of textile based functional elements. This work intends to be a starting point for standardization of smart fabric sensing techniques and e-textile fabrication methods. (topical review)

RD53A Integrated Circuit Specifications

OpenAIRE

Garcia-Sciveres, Mauricio

2015-01-01

Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with...

Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

Science.gov (United States)

2018-01-01

HAS BEEN REVIEWED AND IS APPROVED FOR PUBLICATION IN ACCORDANCE WITH ASSIGNED DISTRIBUTION STATEMENT. FOR THE CHIEF ENGINEER : / S / / S...bridged high-performance computing, nanotechnology , and integrated circuits & systems. 15. SUBJECT TERMS neuromorphic computing, neuron design, spike...multidisciplinary effort encompassed high-performance computing, nanotechnology , integrated circuits, and integrated systems. The project’s architecture was

Prediction of ionizing radiation effects in integrated circuits using black-box models

International Nuclear Information System (INIS)

Williamson, P.W.

1976-10-01

A method is described which allows general black-box modelling of integrated circuits as distinct from the existing method of deriving the radiation induced response of the model from actual terminal measurements on the device during irradiation. Both digital and linear circuits are discussed. (author)

Monolithically integrated 8-channel WDM reflective modulator

NARCIS (Netherlands)

Stopinski, S.T.; Malinowski, M.; Piramidowicz, R.; Smit, M.K.; Leijtens, X.J.M.

2013-01-01

In this work the design and characterization of a monolithically integrated photonic circuit acting as a reflective modulator for eight WDM channels is presented. The chip was designed and fabricated in a generic integration technology

Accurate Models for Evaluating the Direct Conducted and Radiated Emissions from Integrated Circuits

Directory of Open Access Journals (Sweden)

Domenico Capriglione

2018-03-01

Full Text Available This paper deals with the electromagnetic compatibility (EMC issues related to the direct and radiated emissions from a high-speed integrated circuits (ICs. These emissions are evaluated here by means of circuital and electromagnetic models. As for the conducted emission, an equivalent circuit model is derived to describe the IC and the effect of its loads (package, printed circuit board, decaps, etc., based on the Integrated Circuit Emission Model template (ICEM. As for the radiated emission, an electromagnetic model is proposed, based on the superposition of the fields generated in the far field region by the loop currents flowing into the IC and the package pins. A custom experimental setup is designed for validating the models. Specifically, for the radiated emission measurement, a custom test board is designed and realized, able to highlight the contribution of the direct emission from the IC, usually hidden by the indirect emission coming from the printed circuit board. Measurements of the package currents and of the far-field emitted fields are carried out, providing a satisfactory agreement with the model predictions.

Radiation response of high speed CMOS integrated circuits

International Nuclear Information System (INIS)

Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

1987-01-01

This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

Digital integrated circuit design using Verilog and SystemVerilog

CERN Document Server

Mehler, Ronald W

2014-01-01

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

Economic testing of large integrated switching circuits - a challenge to the test engineer

International Nuclear Information System (INIS)

Kreinberg, W.

1978-01-01

With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

Issues of verification and validation of application-specific integrated circuits in reactor trip systems

International Nuclear Information System (INIS)

Battle, R.E.; Alley, G.T.

1993-01-01

Concepts of using application-specific integrated circuits (ASICs) in nuclear reactor safety systems are evaluated. The motivation for this evaluation stems from the difficulty of proving that software-based protection systems are adequately reliable. Important issues concerning the reliability of computers and software are identified and used to evaluate features of ASICS. These concepts indicate that ASICs have several advantages over software for simple systems. The primary advantage of ASICs over software is that verification and validation (V ampersand V) of ASICs can be done with much higher confidence than can be done with software. A method of performing this V ampersand V on ASICS is being developed at Oak Ridge National Laboratory. The purpose of the method's being developed is to help eliminate design and fabrication errors. It will not solve problems with incorrect requirements or specifications

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

Science.gov (United States)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

Integrating nanosphere lithography in device fabrication

Science.gov (United States)

Laurvick, Tod V.; Coutu, Ronald A.; Lake, Robert A.

2016-03-01

This paper discusses the integration of nanosphere lithography (NSL) with other fabrication techniques, allowing for nano-scaled features to be realized within larger microelectromechanical system (MEMS) based devices. Nanosphere self-patterning methods have been researched for over three decades, but typically not for use as a lithography process. Only recently has progress been made towards integrating many of the best practices from these publications and determining a process that yields large areas of coverage, with repeatability and enabled a process for precise placement of nanospheres relative to other features. Discussed are two of the more common self-patterning methods used in NSL (i.e. spin-coating and dip coating) as well as a more recently conceived variation of dip coating. Recent work has suggested the repeatability of any method depends on a number of variables, so to better understand how these variables affect the process a series of test vessels were developed and fabricated. Commercially available 3-D printing technology was used to incrementally alter the test vessels allowing for each variable to be investigated individually. With these deposition vessels, NSL can now be used in conjunction with other fabrication steps to integrate features otherwise unattainable through current methods, within the overall fabrication process of larger MEMS devices. Patterned regions in 1800 series photoresist with a thickness of ~700nm are used to capture regions of self-assembled nanospheres. These regions are roughly 2-5 microns in width, and are able to control the placement of 500nm polystyrene spheres by controlling where monolayer self-assembly occurs. The resulting combination of photoresist and nanospheres can then be used with traditional deposition or etch methods to utilize these fine scale features in the overall design.

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

Science.gov (United States)

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Logistic Regression Modeling of Diminishing Manufacturing Sources for Integrated Circuits

National Research Council Canada - National Science Library

Gravier, Michael

1999-01-01

.... This thesis draws on available data from the electronics integrated circuit industry to attempt to assess whether statistical modeling offers a viable method for predicting the presence of DMSMS...

Experimental Study of WBFC method for testing electromagnetic immunity of integrated circuits

OpenAIRE

香川, 直己; カガワ, ナオキ; Naoki, KAGAWA

2004-01-01

The author made a workbench faraday cage, WBFC, in order to estimate performance of the WBFC method for the measurement of common mode noise immunity of integrated circuits. In this report, characteristics of the constructed workbench faraday cage and results of experimental study of effects of the common mode noise on a circuit board including an electronic device are shown. Selected DUT, LM324 is popular operational amplifier for electrical circuits in vehicles.

X-Band GaN Power Amplifier MMIC with a Third Harmonic-Tuned Circuit