LEIR commissioning successfully completed

CERN Multimedia

2006-01-01

An important milestone has been passed in the preparation of the injector complex to supply ions to the LHC experiments. The LEIR lead-ion beam, seen on one of the control screens just before the PS injection region. The Low-Energy Ion Ring - LEIR for short - has passed its first tests with flying colours. On 12 May, the ring that will accumulate lead ions for the LHC was shut down after seven months of tests (see Bulletin 44/2005). 'The commissioning phase was a resounding success,' enthuses a satisfied Michel Chanel, head of the LEIR construction project. After several months of fine-tuning, the LEIR team has achieved its aim of producing the kind of beam required for first lead-ion collisions in the LHC in 2008. This involved creating bunches containing 230 million ions, in line with the specifications for those first beams. This success can be put down to the machine's outstanding design and components. 'It's a great achivement by all the teams involved in the machine's construction,' underlines Christian...

Hardware implementation of the ORNL fissile mass flow monitor

International Nuclear Information System (INIS)

McEvers, J.; Sumner, J.; Jones, R.; Ferrell, R.; Martin, C.; Uckan, T.; March-Leuba, J.

1998-01-01

This paper provides an overall description of the implementation of the Oak Ridge National Laboratory (ORNL) Fissile Mass Flow Monitor, which is part of a Blend Down Monitoring System (BDMS) developed by the US Department of Energy (DOE). The Fissile Mass Flow Monitor is designed to measure the mass flow of fissile material through a gaseous or liquid process stream. It consists of a source-modulator assembly, a detector assembly, and a cabinet that houses all control, data acquisition, and supporting electronics equipment. The development of this flow monitor was first funded by DOE/NE in September 95, and an initial demonstration by ORNL was described in previous INMM meetings. This methodology was chosen by DOE/NE for implementation in November 1996, and the hardware/software development is complete. Successful BDMS installation and operation of the complete BDMS has been demonstrated in the Paducah Gaseous Diffusion Plant (PGDP), which is operated by Lockheed Martin Utility Services, Inc. for the US Enrichment Corporation and regulated by the Nuclear Regulatory Commission. Equipment for two BDMS units has been shipped to the Russian Federation

Commissioning of closed loop controls at CPP, HWP, Manuguru (Paper No. 3.5)

International Nuclear Information System (INIS)

Basu, Sukumar; Narasimham, P.L.

1992-01-01

The captive power plant (CPP) for Heavy Water Plant, Manuguru is equipped with 3x265 T/hr steam capacity boilers. The control system is built around ASEA master hardware for sequence interlocks, closed loop control, and data acquisition functions. This paper describes the configuration of the system hardware, the steps carried out during commissioning of closed loop controls in distributed digital control systems and also the problems faced during the commissioning of closed loops. (author). 3 figs

COMMISSIONING AND DETECTOR PERFORMANCE GROUPS (DPG)

CERN Multimedia

Tiziano Camporesi

Pit commissioning activities The last 4 months have seen various major achievements in hardware commissioning, global data taking, readiness of the DPGs to deal with LHC data flows and alignment and calibration workflows. Since February, the global commissioning has been characterized on the one side by more and more of the final CMS detector becoming available for global readout and triggering and on the other side by consolidation of many of the central software infrastructure and of most of the services infrastructure. The reliability of services like cooling, power, gas has markedly improved with respect to what we observed in the second half of 2007.   Of particular note are the delivery of all low voltage power supplies, the commissioning of the final power distribution, the progressive commissioning ( still ongoing)  of the Detector Safety System and of the associated DCS early warning and alarm system. On the detector side, while already we are used to seeing all of HCAL being exe...

COMMISSIONING AND DETECTOR PERFORMANCE GROUPS

CERN Multimedia

D. Acosta

The commissioning effort is presently addressing two main areas: the commissioning of the hardware components at the pit and the coordination of the activities of the newly constituted Detector Performance groups (DPGs). At point 5, a plan regarding the service cavern and the commissioning of the connections of the off-detector electronics (for the data collection line and trigger primitive generation) to the central DAQ and the central Trigger has been defined. This activity was started early February and will continue until May. It began with Tracker electronics followed so far by HCAL and CSC. The goal is to have by May every detector commission, as much as possible, their data transfer paths from FED to Central DAQ as well as their trigger setups between TPGs and Global Level 1 trigger. The next focus is on connections of front-ends to the service cavern. This depends strongly on the installations of services. Presently the only detector which has its link fibers connected to the off-detector electr...

Hardware Development Process for Human Research Facility Applications

Science.gov (United States)

Bauer, Liz

2000-01-01

The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

ROS Installation and Commissioning

CERN Multimedia

Gorini, B

The ATLAS Readout group (a sub-group of TDAQ) has now completed the installation and commissioning of all of the Readout System (ROS) units. Event data from ATLAS is initially handled by detector specific hardware and software, but following a Level 1 Accept the data passes from the detector specific Readout Drivers (RODs) to the ROS, the first stage of the central ATLAS DAQ. Within the final ATLAS TDAQ system the ROS stores the data and on request makes it available to the Level 2 Trigger (L2) processors and to the Event Builder (EB) as required. The ROS is implemented as a large number of PCs housing custom built cards (ROBINs) and running custom multi-threaded software. Each ROBIN card (shown below) contains buffer memories to store the data, plus a field programmable gate array ( FPGA ) and an embedded PowerPC processor for management of the memories and data requests, and is implemented as a 64-bit 66 MHz PCI card. Both the software and the ROBIN cards have been designed and developed by the Readout g...

Hardware Support for Fine-Grain Multi-Threading in LEON3

Czech Academy of Sciences Publication Activity Database

Daněk, Martin; Kafka, Leoš; Kohout, Lukáš; Sýkora, Jaroslav

2011-01-01

Roč. 4, č. 1 (2011), s. 27-34 ISSN 1844-9689 R&D Projects: GA MŠk 7E08013 Grant - others:European Commission(BE) FP7-ICT-215216 Keywords : multithreading * microthreading * SPARC * microarchitecture * FPGA Subject RIV: JC - Computer Hardware ; Software http://library.utia.cas.cz/separaty/2011/ZS/danek-0380861.pdf

Commissioning of the LHC

CERN Multimedia

CERN. Geneva

2007-01-01

The LHC construction is now approaching the end and it is now time to prepare for commissioning with beam. The behavior of a proton storage ring is much different to that of LEP, which profited from strong radiation damping to keep the beam stable. Our last experience with a hadron collider at CERN goes back more than 15 years when the proton-antiproton collider last operated. Ppbar taught us a lot about the machine physics of bunched beam proton storage rings and was essential input for the design of the LHC. After a short presentation of where we stand today with machine installation and hardware commissioning, I will discuss the main machine physics issues that will have to be dealt with in the LHC.

The Hardware Topological Trigger of ATLAS: Commissioning and Operations

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00226165; The ATLAS collaboration

2018-01-01

The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. To improve the physics potential reach in ATLAS, during the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software level. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. For individual blades, real-time information from calorimeter and muon Level-1 trigger systems, is processed by four individual state-of-the-art FPGAs. It needs to deal with a large input bandwidth of up to 6 Tb/s, optical connectivity and low processing latency on the real-time data path. The L1Topo firmware apply measurements of angles between jets and/or leptons and several...

Construction and commissioning of the national synchrotron light source

International Nuclear Information System (INIS)

Galayda, J.N.; Blume, M.

1985-01-01

The road from conception to completion of a large facility like the National Synchrotron Light Source (NSLS) is a long and tortuous one. More than fifteen years have passed since the first discussions of a synchrotron radiation source at BNL, and there have been many twists and turns in the process. In putting together an accelerator project like this, there are many critical skills that must be assembled, and budgets, schedules and organizations must be properly examined. The lessons learned in design and commissioning of the NSLS rings may be summarized as follows: (1) the damped emittances expected of a Chasman-Green lattice are attainable at high current, if ion trapping problems can be circumvented; (2) there have been no unexpected effects from the rather strong sextupoles required to correct the chromaticities in this type of lattice; (3) the most important beam instabilities are coupled-bunch, and can be counteracted; and (4) commissioning the NSLS rings was mostly an effort to bring the hardware into conformation with the original ring design; achievement of the specified magnetic fields, injection timing, vacuum, RF voltages, etc. led to ring performance which was easily good enough to begin operation

The LISA Pathfinder interferometry-hardware and system testing

Energy Technology Data Exchange (ETDEWEB)

Audley, H; Danzmann, K; MarIn, A Garcia; Heinzel, G; Monsky, A; Nofrarias, M; Steier, F; Bogenstahl, J [Albert-Einstein-Institut, Max-Planck-Institut fuer Gravitationsphysik und Universitaet Hannover, 30167 Hannover (Germany); Gerardi, D; Gerndt, R; Hechenblaikner, G; Johann, U; Luetzow-Wentzky, P; Wand, V [EADS Astrium GmbH, Friedrichshafen (Germany); Antonucci, F [Dipartimento di Fisica, Universita di Trento and INFN, Gruppo Collegato di Trento, 38050 Povo, Trento (Italy); Armano, M [European Space Astronomy Centre, European Space Agency, Villanueva de la Canada, 28692 Madrid (Spain); Auger, G; Binetruy, P [APC UMR7164, Universite Paris Diderot, Paris (France); Benedetti, M [Dipartimento di Ingegneria dei Materiali e Tecnologie Industriali, Universita di Trento and INFN, Gruppo Collegato di Trento, Mesiano, Trento (Italy); Boatella, C, E-mail: antonio.garcia@aei.mpg.de [CNES, DCT/AQ/EC, 18 Avenue Edouard Belin, 31401 Toulouse, Cedex 9 (France)

2011-05-07

Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

Completed installations and the individual commissioning of the KSTAR MG system

Energy Technology Data Exchange (ETDEWEB)

Kim, Chang-Hwan, E-mail: kch2004@nfri.re.kr [National Fusion Research Institute, 169-148 Gwahangno, Yusung-gu, Daejeon 305-333 (Korea, Republic of); Eom, Dae-young; Lee, Woo-Jin; Kong, Jong-Dea; Joung, Nam-Young; Kim, Yang-Soo; Kwon, Myeun [National Fusion Research Institute, 169-148 Gwahangno, Yusung-gu, Daejeon 305-333 (Korea, Republic of); Jang, Eun; Han, Chul-Woo; Lee, Sel-Ki; Kim, Gwang-Seon; Maeng, Jae-Hoon [Vitzrotech Co., Ltd, 605-2 Seonggok-dong, Danwon-gu, Ansan, Gyeonggi-do 425-833 (Korea, Republic of)

2014-04-15

Highlights: • All components of the MG system were made from each professional supplier and installed completely in the NFRI site. • The building and the overhead crane which need to install the MG system, were built in two sections. One is for the bearing, rotor and stator and the other section is for the VVVF and excitation system. • The dummy coil testing will commence in July 2013 and the comprehensive performance test of MG will be tested from August when the MPS commissioning is processing with superconducting coil. - Abstract: Peak power of 200 MVA is required in order to achieve the goal within a long pulse scenario for the final operation of the Korean Superconducting Tokamak Advanced Research (KSTAR). The available grid power is only 100 MVA at the National Fusion Research Institute (NFRI) site. Motor generator (MG) was considered as a method of resolving such problems. The design of the KSTAR MG system was completed in July 2010 and individual devices were produced by relevant manufacturers. The installation of individual devices was completed in December 2012. Specifically, the stator and rotor were assembled at the site due to their large size and weight. The bearings, variable voltage variable frequency (VVVF) and excitation systems were transported and installed on site after being manufactured externally. The building used for MG installation was built in 2011. With the building designed for ease of installation, an overhead crane was designed to allow access to the loading bay. In this paper, we discuss the installation of the MG system and the construction of the building suitable for installation of individual devices. In addition, performance on the test results of individual devices is also discussed.

Commissioning of the LHC Beam Transfer Line TI 8

International Nuclear Information System (INIS)

Uythoven, J.A.; Arduini, G.; Goddard, B.; Jacquet, D.; Kain, V.; Lamont, M.; Mertens, V.; Spinks, A.; Wenninger, J.; Chao, Y.-C.

2005-01-01

The first of the two LHC transfer lines was commissioned in autumn 2004. Beam reached an absorber block located some 2.5 km downstream of the SPS extraction point at the first shot, without the need of any threading. The hardware preparation and commissioning phase will be summarized, followed by a description of the beam tests and their results regarding optics and other line parameters, including the experience gained with beam instrumentation, the control system and the machine protection equipment

The ATLAS Inner Detector commissioning and calibration

CERN Document Server

Aad, G.; Abdallah, J.; Abdelalim, A.A.; Abdesselam, A.; Abdinov, O.; Abi, B.; Abolins, M.; Abramowicz, H.; Abreu, H.; Acharya, B.S.; Adams, D.L.; Addy, T.N.; Adelman, J.; Adorisio, C.; Adragna, P.; Adye, T.; Aefsky, S.; Aguilar-Saavedra, J.A.; Aharrouche, M.; Ahlen, S.P.; Ahles, F.; Ahmad, A.; Ahsan, M.; Aielli, G.; Akdogan, T.; Akesson, T.P.A.; Akimoto, G.; Akimov, A.V.; Aktas, A.; Alam, M.S.; Alam, M.A.; Albert, J.; Albrand, S.; Aleksa, M.; Aleksandrov, I.N.; Alexa, C.; Alexander, G.; Alexandre, G.; Alexopoulos, T.; Alhroob, M.; Aliev, M.; Alimonti, G.; Alison, J.; Aliyev, M.; Allport, P.P.; Allwood-Spiers, S.E.; Almond, J.; Aloisio, A.; Alon, R.; Alonso, A.; Alviggi, M.G.; Amako, K.; Amelung, C.; Amorim, A.; Amoros, G.; Amram, N.; Anastopoulos, C.; Andeen, T.; Anders, C.F.; Anderson, K.J.; Andreazza, A.; Andrei, V.; Anduaga, X.S.; Angerami, A.; Anghinolfi, F.; Anjos, N.; Annovi, A.; Antonaki, A.; Antonelli, M.; Antonelli, S.; Antos, J.; Antunovic, B.; Anulli, F.; Aoun, S.; Arabidze, G.; Aracena, I.; Arai, Y.; Arce, A.T.H.; Archambault, J.P.; Arfaoui, S.; Arguin, J-F.; Argyropoulos, T.; Arik, M.; Armbruster, A.J.; Arnaez, O.; Arnault, C.; Artamonov, A.; Arutinov, D.; Asai, M.; Asai, S.; Asfandiyarov, R.; Ask, S.; Asman, B.; Asner, D.; Asquith, L.; Assamagan, K.; Astbury, A.; Astvatsatourov, A.; Atoian, G.; Auerbach, B.; Augsten, K.; Aurousseau, M.; Austin, N.; Avolio, G.; Avramidou, R.; Axen, D.; Ay, C.; Azuelos, G.; Azuma, Y.; Baak, M.A.; Bach, A.M.; Bachacou, H.; Bachas, K.; Backes, M.; Badescu, E.; Bagnaia, P.; Bai, Y.; Bain, T.; Baines, J.T.; Baker, O.K.; Baker, M.D.; Baker, S.; Baltasar Dos, F.Santos Pedrosa; Banas, E.; Banerjee, P.; Banerjee, S.; Banfi, D.; Bangert, A.; Bansal, V.; Baranov, S.P.; Baranov, S.; Barashkou, A.; Barber, T.; Barberio, E.L.; Barberis, D.; Barbero, M.; Bardin, D.Y.; Barillari, T.; Barisonzi, M.; Barklow, T.; Barlow, N.; Barnett, B.M.; Barnett, R.M.; Baroncelli, A.; Barr, A.J.; Barreiro, F.; Guimara, J.Barreiro; Barrillon, P.; Bartoldus, R.; Bartsch, D.; Bates, R.L.; Batkova, L.; Batley, J.R.; Battaglia, A.; Battistin, M.; Bauer, F.; Bawa, H.S.; Bazalova, M.; Beare, B.; Beau, T.; Beauchemin, P.H.; Beccherle, R.; Bechtle, P.; Beck, G.A.; Beck, H.P.; Beckingham, M.; Becks, K.H.; Beddall, A.J.; Beddall, A.; Bednyakov, V.A.; Bee, C.; Begel, M.; Behar Harpaz, S.; Behera, P.K.; Beimforde, M.; Belanger-Champagne, C.; Bell, P.J.; Bell, W.H.; Bella, G.; Bellagamba, L.; Bellina, F.; Bellomo, M.; Belloni, A.; Belotskiy, K.; Beltramello, O.; Ben Ami, S.; Benary, O.; Benchekroun, D.; Bendel, M.; Benedict, B.H.; Benekos, N.; Benhammou, Y.; Benincasa, G.P.; Benjamin, D.P.; Benoit, M.; Bensinger, J.R.; Benslama, K.; Bentvelsen, S.; Beretta, M.; Berge, D.; Bergeaas Kuutmann, E.; Berger, N.; Berghaus, F.; Berglund, E.; Beringer, J.; Bernat, P.; Bernhard, R.; Bernius, C.; Berry, T.; Bertin, A.; Besana, M.I.; Besson, N.; Bethke, S.; Bianchi, R.M.; Bianco, M.; Biebel, O.; Biesiada, J.; Biglietti, M.; Bilokon, H.; Bindi, M.; Binet, S.; Bingul, A.; Bini, C.; Biscarat, C.; Bitenc, U.; Black, K.M.; Blair, R.E.; Blanchard, J-B.; Blanchot, G.; Blocker, C.; Blondel, A.; Blum, W.; Blumenschein, U.; Bobbink, G.J.; Bocci, A.; Boehler, M.; Boek, J.; Boelaert, N.; Boser, S.; Bogaerts, J.A.; Bohm, C.; Bohm, J.; Boisvert, V.; Bold, T.; Boldea, V.; Bondarenko, V.G.; Bondioli, M.; Boonekamp, M.; Bordoni, S.; Borer, C.; Borisov, A.; Borissov, G.; Borjanovic, I.; Borroni, S.; Bos, K.; Boscherini, D.; Bosman, M.; Boterenbrood, H.; Bouchami, J.; Boudreau, J.; Bouhova-Thacker, E.V.; Boulahouache, C.; Bourdarios, C.; Boveia, A.; Boyd, J.; Boyko, I.R.; Bozovic-Jelisavcic, I.; Bracinik, J.; Braem, A.; Branchini, P.; Brandenburg, G.W.; Brandt, A.; Brandt, G.; Brandt, O.; Bratzler, U.; Brau, B.; Brau, J.E.; Braun, H.M.; Brelier, B.; Bremer, J.; Brenner, R.; Bressler, S.; Britton, D.; Brochu, F.M.; Brock, I.; Brock, R.; Brodet, E.; Bromberg, C.; Brooijmans, G.; Brooks, W.K.; Brown, G.; Bruckman de Renstrom, P.A.; Bruncko, D.; Bruneliere, R.; Brunet, S.; Bruni, A.; Bruni, G.; Bruschi, M.; Bucci, F.; Buchanan, J.; Buchholz, P.; Buckley, A.G.; Budagov, I.A.; Budick, B.; Buscher, V.; Bugge, L.; Bulekov, O.; Bunse, M.; Buran, T.; Burckhart, H.; Burdin, S.; Burgess, T.; Burke, S.; Busato, E.; Bussey, P.; Buszello, C.P.; Butin, F.; Butler, B.; Butler, J.M.; Buttar, C.M.; Butterworth, J.M.; Byatt, T.; Caballero, J.; Urban, S.Cabrera; Caforio, D.; Cakir, O.; Calafiura, P.; Calderini, G.; Calfayan, P.; Calkins, R.; Caloba, L.P.; Calvet, D.; Camarri, P.; Cameron, D.; Campana, S.; Campanelli, M.; Canale, V.; Canelli, F.; Canepa, A.; Cantero, J.; Capasso, L.; Capeans Garrido, M.D.M.; Caprini, I.; Caprini, M.; Capua, M.; Caputo, R.; Caramarcu, C.; Cardarelli, R.; Carli, T.; Carlino, G.; Carminati, L.; Caron, B.; Caron, S.; Carrillo Montoya, G.D.; Carron Montero, S.; Carter, A.A.; Carter, J.R.; Carvalho, J.; Casadei, D.; Casado, M.P.; Cascella, M.; Castaneda Hernadez, A.M.; Castaneda-Miranda, E.; Castillo Gimenez, V.; Castro, N.F.; Cataldi, G.; Catinaccio, A.; Catmore, J.R.; Cattai, A.; Cattani, G.; Caughron, S.; Cauz, D.; Cavalleri, P.; Cavalli, D.; Cavalli-Sforza, M.; Cavasinni, V.; Ceradini, F.; Cerqueira, A.S.; Cerri, A.; Cerrito, L.; Cerutti, F.; Cetin, S.A.; Chafaq, A.; Chakraborty, D.; Chan, K.; Chapman, J.D.; Chapman, J.W.; Chareyre, E.; Charlton, D.G.; Chavda, V.; Cheatham, S.; Chekanov, S.; Chekulaev, S.V.; Chelkov, G.A.; Chen, H.; Chen, S.; Chen, X.; Cheplakov, A.; Chepurnov, V.F.; Cherkaoui El, R.Moursli; Tcherniatine, V.; Chesneanu, D.; Cheu, E.; Cheung, S.L.; Chevalier, L.; Chevallier, F.; Chiarella, V.; Chiefari, G.; Chikovani, L.; Childers, J.T.; Chilingarov, A.; Chiodini, G.; Chizhov, V.; Choudalakis, G.; Chouridou, S.; Christidi, I.A.; Christov, A.; Chromek-Burckhart, D.; Chu, M.L.; Chudoba, J.; Ciapetti, G.; Ciftci, A.K.; Ciftci, R.; Cinca, D.; Cindro, V.; Ciobotaru, M.D.; Ciocca, C.; Ciocio, A.; Cirilli, M.; Citterio, M.; Clark, A.; Clark, P.J.; Cleland, W.; Clemens, J.C.; Clement, B.; Clement, C.; Coadou, Y.; Cobal, M.; Coccaro, A.; Cochran, J.; Coggeshall, J.; Cogneras, E.; Colijn, A.P.; Collard, C.; Collins, N.J.; Collins-Tooth, C.; Collot, J.; Colon, G.; Muino, P.Conde; Coniavitis, E.; Conidi, M.C.; Consonni, M.; Constantinescu, S.; Conta, C.; Conventi, F.; Cooke, M.; Cooper, B.D.; Cooper-Sarkar, A.M.; Cooper-Smith, N.J.; Copic, K.; Cornelissen, T.; Corradi, M.; Corriveau, F.; Corso-Radu, A.; Cortes-Gonzalez, A.; Cortiana, G.; Costa, G.; Costa, M.J.; Costanzo, D.; Costin, T.; Cote, D.; Coura Torres, R.; Courneyea, L.; Cowan, G.; Cowden, C.; Cox, B.E.; Cranmer, K.; Cranshaw, J.; Cristinziani, M.; Crosetti, G.; Crupi, R.; Crepe-Renaudin, S.; Cuenca Almenar, C.; Cuhadar Donszelmann, T.; Curatolo, M.; Curtis, C.J.; Cwetanski, P.; Czyczula, Z.; D'Auria, S.; D'Onofrio, M.; D'Orazio, A.; Da Via, C.; Dabrowski, W.; Dai, T.; Dallapiccola, C.; Dam, M.; Danielsson, H.O.; Dannheim, D.; Dao, V.; Darbo, G.; Darlea, G.L.; Davey, W.; Davidek, T.; Davidson, N.; Davidson, R.; Davies, M.; Davison, A.R.; Dawson, I.; Daya, R.K.; De, K.; de Asmundis, R.; De Castro, S.; De Castro, P.E.Faria Salgado; De Cecco, S.; de Graat, J.; De Groot, N.; de Jong, P.; De Mora, L.; De Oliveira, M.Branco; De Pedis, D.; De Salvo, A.; De Sanctis, U.; De Santo, A.; De Vivie De Regie, J.B.; De Zorzi, G.; Dean, S.; Dedovich, D.V.; Degenhardt, J.; Dehchar, M.; Del Papa, C.; Del Peso, J.; Del Prete, T.; Dell'Acqua, A.; Dell'Asta, L.; Della Pietra, M.; della Volpe, D.; Delmastro, M.; Delsart, P.A.; Deluca, C.; Demers, S.; Demichev, M.; Demirkoz, B.; Deng, J.; Deng, W.; Denisov, S.P.; Derkaoui, J.E.; Derue, F.; Dervan, P.; Desch, K.; Deviveiros, P.O.; Dewhurst, A.; DeWilde, B.; Dhaliwal, S.; Dhullipudi, R.; Di Ciaccio, A.; Di Ciaccio, L.; Di Domenico, A.; Di Girolamo, A.; Di Girolamo, B.; Di Luise, S.; Di Mattia, A.; Di Nardo, R.; Di Simone, A.; Di Sipio, R.; Diaz, M.A.; Diblen, F.; Diehl, E.B.; Dietrich, J.; Dietzsch, T.A.; Diglio, S.; Dindar Yagci, K.; Dingfelder, D.J.; Dionisi, C.; Dita, P.; Dita, S.; Dittus, F.; Djama, F.; Djilkibaev, R.; Djobava, T.; Vale, M.A.B.do; Do Valle, A.Wemans; Doan, T.K.O.; Dobos, D.; Dobson, E.; Dobson, M.; Doglioni, C.; Doherty, T.; Dolejsi, J.; Dolenc, I.; Dolezal, Z.; Dolgoshein, B.A.; Dohmae, T.; Donega, M.; Donini, J.; Dopke, J.; Doria, A.; Dos Anjos, A.; Dotti, A.; Dova, M.T.; Doxiadis, A.; Doyle, A.T.; Drasal, Z.; Dris, M.; Dubbert, J.; Duchovni, E.; Duckeck, G.; Dudarev, A.; Dudziak, F.; Duhrssen, M.; Duflot, L.; Dufour, M-A.; Dunford, M.; Duran Yildiz, H.; Dushkin, A.; Duxfield, R.; Dwuznik, M.; Duren, M.; Ebenstein, W.L.; Ebke, J.; Eckweiler, S.; Edmonds, K.; Edwards, C.A.; Egorov, K.; Ehrenfeld, W.; Ehrich, T.; Eifert, T.; Eigen, G.; Einsweiler, K.; Eisenhandler, E.; Ekelof, T.; El Kacimi, M.; Ellert, M.; Elles, S.; Ellinghaus, F.; Ellis, K.; Ellis, N.; Elmsheuser, J.; Elsing, M.; Emeliyanov, D.; Engelmann, R.; Engl, A.; Epp, B.; Eppig, A.; Erdmann, J.; Ereditato, A.; Eriksson, D.; Ermoline, I.; Ernst, J.; Ernst, M.; Ernwein, J.; Errede, D.; Errede, S.; Ertel, E.; Escalier, M.; Escobar, C.; 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Okuyama, T.; Olchevski, A.G.; Oliveira, M.; Oliveira Damazio, D.; Oliver, J.; Oliver Garcia, E.; Olivito, D.; Olszewski, A.; Olszowska, J.; Omachi, C.; Onofre, A.; Onyisi, P.U.E.; Oram, C.J.; Oreglia, M.J.; Oren, Y.; Orestano, D.; Orlov, I.; Oropeza Barrera, C.; Orr, R.S.; Ortega, E.O.; Osculati, B.; Ospanov, R.; Osuna, C.; Ottersbach, J.P.; Ould-Saada, F.; Ouraou, A.; Ouyang, Q.; Owen, M.; Owen, S.; Oyarzun, A.; Ozcan, V.E.; Ozone, K.; Ozturk, N.; Pacheco Pages, A.; Padilla Aranda, C.; Paganis, E.; Pahl, C.; Paige, F.; Pajchel, K.; Palestini, S.; Pallin, D.; Palma, A.; Palmer, J.D.; Pan, Y.B.; Panagiotopoulou, E.; Panes, B.; Panikashvili, N.; Panitkin, S.; Pantea, D.; Panuskova, M.; Paolone, V.; Papadopoulou, Th.D.; Park, S.J.; Park, W.; Parker, M.A.; Parker, S.I.; Parodi, F.; Parsons, J.A.; Parzefall, U.; Pasqualucci, E.; Passeri, A.; Pastore, F.; Pastore, Fr.; Pasztor, G.; Pataraia, S.; Pater, J.R.; Patricelli, S.; Patwa, A.; Pauly, T.; Peak, L.S.; Pecsy, M.; Pedraza Morales, M.I.; Peleganchuk, S.V.; Peng, H.; Penson, A.; Penwell, J.; Perantoni, M.; Perez, K.; Perez Codina, E.; Perez Garcia-Estan, M.T.; Perez Reale, V.; Perini, L.; Pernegger, H.; Perrino, R.; Persembe, S.; Perus, P.; Peshekhonov, V.D.; Petersen, B.A.; Petersen, T.C.; Petit, E.; Petridou, C.; Petrolo, E.; Petrucci, F.; Petschull, D.; Petteni, M.; Pezoa, R.; Phan, A.; Phillips, A.W.; Piacquadio, G.; Piccinini, M.; Piegaia, R.; Pilcher, J.E.; Pilkington, A.D.; Pina, J.; Pinamonti, M.; Pinfold, J.L.; Pinto, B.; Pizio, C.; Placakyte, R.; Plamondon, M.; Pleier, M.A.; Poblaguev, A.; Poddar, S.; Podlyski, F.; Poffenberger, P.; Poggioli, L.; Pohl, M.; Polci, F.; Polesello, G.; Policicchio, A.; Polini, A.; Poll, J.; Polychronakos, V.; Pomeroy, D.; Pommes, K.; Pontecorvo, L.; Pope, B.G.; Popovic, D.S.; Poppleton, A.; Popule, J.; Portell Bueso, X.; Porter, R.; Pospelov, G.E.; Pospisil, S.; Potekhin, M.; Potrap, I.N.; Potter, C.J.; Potter, C.T.; Potter, K.P.; Poulard, G.; Poveda, J.; Prabhu, R.; Pralavorio, P.; Prasad, S.; Pravahan, R.; Pribyl, L.; Price, D.; Price, L.E.; Prichard, P.M.; Prieur, D.; Primavera, M.; Prokofiev, K.; Prokoshin, F.; Protopopescu, S.; Proudfoot, J.; Prudent, X.; Przysiezniak, H.; Psoroulas, S.; Ptacek, E.; Puigdengoles, C.; Purdham, J.; Purohit, M.; Puzo, P.; Pylypchenko, Y.; Qi, M.; Qian, J.; Qian, W.; Qin, Z.; Quadt, A.; Quarrie, D.R.; Quayle, W.B.; Quinonez, F.; Raas, M.; Radeka, V.; Radescu, V.; Radics, B.; Rador, T.; Ragusa, F.; Rahal, G.; Rahimi, A.M.; Rajagopalan, S.; Rammensee, M.; Rammes, M.; Rauscher, F.; Rauter, E.; Raymond, M.; Read, A.L.; Rebuzzi, D.M.; Redelbach, A.; Redlinger, G.; Reece, R.; Reeves, K.; Reinherz-Aronis, E.; Reinsch, A.; Reisinger, I.; Reljic, D.; Rembser, C.; Ren, Z.L.; Renkel, P.; Rescia, S.; Rescigno, M.; Resconi, S.; Resende, B.; Reznicek, P.; Rezvani, R.; Richards, A.; Richards, R.A.; Richter, R.; Richter-Was, E.; Ridel, M.; Rijpstra, M.; Rijssenbeek, M.; Rimoldi, A.; Rinaldi, L.; Rios, R.R.; Riu, I.; Rizatdinova, F.; Rizvi, E.; Roa Romero, D.A.; Robertson, S.H.; Robichaud-Veronneau, A.; Robinson, D.; Robinson, J.E.M.; Robinson, M.; Robson, A.; Rocha de Lima, J.G.; Roda, C.; Roda Dos, D.Santos; Rodriguez, D.; Rodriguez Garcia, Y.; Roe, S.; Rohne, O.; Rojo, V.; Rolli, S.; Romaniouk, A.; Romanov, V.M.; Romeo, G.; Romero Maltrana, D.; Roos, L.; Ros, E.; Rosati, S.; Rosenbaum, G.A.; Rosselet, L.; Rossetti, V.; Rossi, L.P.; Rotaru, M.; Rothberg, J.; Rousseau, D.; Royon, C.R.; Rozanov, A.; Rozen, Y.; Ruan, X.; Ruckert, B.; Ruckstuhl, N.; Rud, V.I.; Rudolph, G.; Ruhr, F.; Ruggieri, F.; Ruiz-Martinez, A.; Rumyantsev, L.; Rurikova, Z.; Rusakovich, N.A.; Rutherfoord, J.P.; Ruwiedel, C.; Ruzicka, P.; Ryabov, Y.F.; Ryan, P.; Rybkin, G.; Rzaeva, S.; Saavedra, A.F.; Sadrozinski, H.F-W.; Sadykov, R.; Safai Tehrani, F.; Sakamoto, H.; Salamanna, G.; Salamon, A.; Saleem, M.S.; Salihagic, D.; Salnikov, A.; Salt, J.; Salvachua Ferrando, B.M.; Salvatore, D.; Salvatore, F.; Salvucci, A.; Salzburger, A.; Sampsonidis, D.; Samset, B.H.; Sanchis Lozano, M.A.; Sandaker, H.; Sander, H.G.; Sanders, M.P.; Sandhoff, M.; Sandhu, P.; Sandstroem, R.; Sandvoss, S.; Sankey, D.P.C.; Sanny, B.; Sansoni, A.; Santamarina Rios, C.; Santoni, C.; Santonico, R.; Saraiva, J.G.; Sarangi, T.; Sarkisyan-Grinbaum, E.; Sarri, F.; Sasaki, O.; Sasao, N.; Satsounkevitch, I.; Sauvage, G.; Savard, P.; Savine, A.Y.; Savinov, V.; Sawyer, L.; Saxon, D.H.; Says, L.P.; Sbarra, C.; Sbrizzi, A.; Scannicchio, D.A.; Schaarschmidt, J.; Schacht, P.; Schafer, U.; Schaetzel, S.; Schaffer, A.C.; Schaile, D.; Schamberger, R.D.; Schamov, A.G.; Scharf, V.; Schegelsky, V.A.; Scheirich, D.; Schernau, M.; Scherzer, M.I.; Schiavi, C.; Schieck, J.; Schioppa, M.; Schlenker, S.; Schmidt, E.S.; Schmieden, K.; Schmitt, C.; Schmitz, M.; Schonig, A.; Schott, M.; Schouten, D.; Schovancova, J.; Schram, M.; Schreiner, A.; Schroeder, C.; Schroer, N.; Schroers, M.; Schultes, J.; Schultz-Coulon, H.C.; Schumacher, J.W.; Schumacher, M.; Schumm, B.A.; Schune, Ph.; Schwanenberger, C.; Schwartzman, A.; Schwemling, Ph.; Schwienhorst, R.; Schwierz, R.; Schwindling, J.; Scott, W.G.; Searcy, J.; Sedykh, E.; Segura, E.; Seidel, S.C.; Seiden, A.; Seifert, F.; Seixas, J.M.; Sekhniaidze, G.; Seliverstov, D.M.; Sellden, B.; Semprini-Cesari, N.; Serfon, C.; Serin, L.; Seuster, R.; Severini, H.; Sevior, M.E.; Sfyrla, A.; Shabalina, E.; Shamim, M.; Shan, L.Y.; Shank, J.T.; Shao, Q.T.; Shapiro, M.; Shatalov, P.B.; Shaw, K.; Sherman, D.; Sherwood, P.; Shibata, A.; Shimojima, M.; Shin, T.; Shmeleva, A.; Shochet, M.J.; Shupe, M.A.; Sicho, P.; Sidoti, A.; Siegert, F.; Siegrist, J.; Sijacki, Dj.; Silbert, O.; Silva, J.; Silver, Y.; Silverstein, D.; Silverstein, S.B.; Simak, V.; Simic, Lj.; Simion, S.; Simmons, B.; Simonyan, M.; Sinervo, P.; Sinev, N.B.; Sipica, V.; Siragusa, G.; Sisakyan, A.N.; Sivoklokov, S.Yu.; Sjoelin, J.; Sjursen, T.B.; Skovpen, K.; Skubic, P.; Slater, M.; Slavicek, T.; Sliwa, K.; Sloper, J.; Sluka, T.; Smakhtin, V.; Smirnov, S.Yu.; Smirnov, Y.; Smirnova, L.N.; Smirnova, O.; Smith, B.C.; Smith, D.; Smith, K.M.; Smizanska, M.; Smolek, K.; Snesarev, A.A.; Snow, S.W.; Snow, J.; Snuverink, J.; Snyder, S.; Soares, M.; Sobie, R.; Sodomka, J.; Soffer, A.; Solans, C.A.; Solar, M.; Solc, J.; Solfaroli Camillocci, E.; Solodkov, A.A.; Solovyanov, O.V.; Soluk, R.; Sondericker, J.; Sopko, V.; Sopko, B.; Sosebee, M.; Soukharev, A.; Spagnolo, S.; Spano, F.; Spencer, E.; Spighi, R.; Spigo, G.; Spila, F.; Spiwoks, R.; Spousta, M.; Spreitzer, T.; Spurlock, B.; Denis, R.D.St.; Stahl, T.; Stahlman, J.; Stamen, R.; Stancu, S.N.; Stanecka, E.; Stanek, R.W.; Stanescu, C.; Stapnes, S.; Starchenko, E.A.; Stark, J.; Staroba, P.; Starovoitov, P.; Stastny, J.; Stavina, P.; Steele, G.; Steinbach, P.; Steinberg, P.; Stekl, I.; Stelzer, B.; Stelzer, H.J.; Stelzer-Chilton, O.; Stenzel, H.; Stevenson, K.; Stewart, G.; Stockton, M.C.; Stoerig, K.; Stoicea, G.; Stonjek, S.; Strachota, P.; Stradling, A.R.; Straessner, A.; Strandberg, J.; Strandberg, S.; Strandlie, A.; Strauss, M.; Strizenec, P.; Strohmer, R.; Strom, D.M.; Stroynowski, R.; Strube, J.; Stugu, B.; Sturm, P.; Soh, D.A.; Su, D.; Sugaya, Y.; Sugimoto, T.; Suhr, C.; Suk, M.; Sulin, V.V.; Sultansoy, S.; Sumida, T.; Sun, X.H.; Sundermann, J.E.; Suruliz, K.; Sushkov, S.; Susinno, G.; Sutton, M.R.; Suzuki, T.; Suzuki, Y.; Sykora, I.; Sykora, T.; Szymocha, T.; Sanchez, J.; Ta, D.; Tackmann, K.; Taffard, A.; Tafirout, R.; Taga, A.; Takahashi, Y.; Takai, H.; Takashima, R.; Takeda, H.; Takeshita, T.; Talby, M.; Talyshev, A.; Tamsett, M.C.; Tanaka, J.; Tanaka, R.; Tanaka, S.; Tanaka, S.; Tapprogge, S.; Tardif, D.; Tarem, S.; Tarrade, F.; Tartarelli, G.F.; Tas, P.; Tasevsky, M.; Tassi, E.; Tatarkhanov, M.; Taylor, C.; Taylor, F.E.; Taylor, G.N.; Taylor, R.P.; Taylor, W.; Teixeira-Dias, P.; Ten Kate, H.; Teng, P.K.; Tennenbaum-Katan, Y.D.; Terada, S.; Terashi, K.; Terron, J.; Terwort, M.; Testa, M.; Teuscher, R.J.; Therhaag, J.; Thioye, M.; Thoma, S.; Thomas, J.P.; Thompson, E.N.; Thompson, P.D.; Thompson, P.D.; Thompson, R.J.; Thompson, A.S.; Thomson, E.; Thun, R.P.; Tic, T.; Tikhomirov, V.O.; Tikhonov, Y.A.; Tipton, P.; Tique Aires, F.J.Viegas; Tisserant, S.; Toczek, B.; Todorov, T.; Todorova-Nova, S.; Toggerson, B.; Tojo, J.; Tokar, S.; Tokushuku, K.; Tollefson, K.; Tomasek, L.; Tomasek, M.; Tomoto, M.; Tompkins, L.; Toms, K.; Tonoyan, A.; Topfel, C.; Topilin, N.D.; Torchiani, I.; Torrence, E.; Pastor, E.Torro; Toth, J.; Touchard, F.; Tovey, D.R.; Trefzger, T.; Tremblet, L.; Tricoli, A.; Trigger, I.M.; Trincaz-Duvoid, S.; Trinh, T.N.; Tripiana, M.F.; Triplett, N.; Trischuk, W.; Trivedi, A.; Trocme, B.; Troncon, C.; Trzupek, A.; Tsarouchas, C.; Tseng, J.C-L.; Tsiakiris, M.; Tsiareshka, P.V.; Tsionou, D.; Tsipolitis, G.; Tsiskaridze, V.; Tskhadadze, E.G.; Tsukerman, I.I.; Tsulaia, V.; Tsung, J.W.; Tsuno, S.; Tsybychev, D.; Tuggle, J.M.; Turecek, D.; Turk Cakir, I.; Turlay, E.; Tuts, P.M.; Twomey, M.S.; Tylmad, M.; Tyndel, M.; Uchida, K.; Ueda, I.; Ueno, R.; Ugland, M.; Uhlenbrock, M.; Uhrmacher, M.; Ukegawa, F.; Unal, G.; Undrus, A.; Unel, G.; Unno, Y.; Urbaniec, D.; Urkovsky, E.; Urquijo, P.; Urrejola, P.; Usai, G.; Uslenghi, M.; Vacavant, L.; Vacek, V.; Vachon, B.; Vahsen, S.; Valente, P.; Valentinetti, S.; Valkar, S.; Valladolid Gallego, E.; Vallecorsa, S.; Valls Ferrer, J.A.; Van Berg, R.; van der Graaf, H.; van der Kraaij, E.; van der Poel, E.; van der Ster, D.; van Eldik, N.; van Gemmeren, P.; van Kesteren, Z.; van Vulpen, I.; Vandelli, W.; Vaniachine, A.; Vankov, P.; Vannucci, F.; Vari, R.; Varnes, E.W.; Varouchas, D.; Vartapetian, A.; Varvell, K.E.; Vasilyeva, L.; Vassilakopoulos, V.I.; Vazeille, F.; Vellidis, C.; Veloso, F.; Veneziano, S.; Ventura, A.; Ventura, D.; Venturi, M.; Venturi, N.; Vercesi, V.; Verducci, M.; Verkerke, W.; Vermeulen, J.C.; Vetterli, M.C.; Vichou, I.; Vickey, T.; Viehhauser, G.H.A.; Villa, M.; Villani, E.G.; Villaplana Perez, M.; Vilucchi, E.; Vincter, M.G.; Vinek, E.; Vinogradov, V.B.; Viret, S.; Virzi, J.; Vitale, A.; Vitells, O.; Vivarelli, I.; Vives Vaque, F.; Vlachos, S.; Vlasak, M.; Vlasov, N.; Vogel, A.; Vokac, P.; Volpi, M.; von der Schmitt, H.; von Loeben, J.; von Radziewski, H.; von Toerne, E.; Vorobel, V.; Vorwerk, V.; Vos, M.; Voss, R.; Voss, T.T.; Vossebeld, J.H.; Vranjes, N.; Vranjes Milosavljevic, M.; Vrba, V.; Vreeswijk, M.; Vu Anh, T.; Vudragovic, D.; Vuillermet, R.; Vukotic, I.; Wagner, P.; Walbersloh, J.; Walder, J.; Walker, R.; Walkowiak, W.; Wall, R.; Wang, C.; Wang, H.; Wang, J.; Wang, S.M.; Warburton, A.; Ward, C.P.; Warsinsky, M.; Wastie, R.; Watkins, P.M.; Watson, A.T.; Watson, M.F.; Watts, G.; Watts, S.; Waugh, A.T.; Waugh, B.M.; Weber, M.D.; Weber, M.; Weber, M.S.; Weber, P.; Weidberg, A.R.; Weingarten, J.; Weiser, C.; Wellenstein, H.; Wells, P.S.; Wen, M.; Wenaus, T.; Wendler, S.; Wengler, T.; Wenig, S.; Wermes, N.; Werner, M.; Werner, P.; Werth, M.; Werthenbach, U.; Wessels, M.; Whalen, K.; White, A.; White, M.J.; White, S.; Whitehead, S.R.; Whiteson, D.; Whittington, D.; Wicek, F.; Wicke, D.; Wickens, F.J.; Wiedenmann, W.; Wielers, M.; Wienemann, P.; Wiglesworth, C.; Wiik, L.A.M.; Wildauer, A.; Wildt, M.A.; Wilkens, H.G.; Williams, E.; Williams, H.H.; Willocq, S.; Wilson, J.A.; Wilson, M.G.; Wilson, A.; Wingerter-Seez, I.; Winklmeier, F.; Wittgen, M.; Wolter, M.W.; Wolters, H.; Wosiek, B.K.; Wotschack, J.; Woudstra, M.J.; Wraight, K.; Wright, C.; Wright, D.; Wrona, B.; Wu, S.L.; Wu, X.; Wulf, E.; Wynne, B.M.; Xaplanteris, L.; Xella, S.; Xie, S.; Xu, D.; Xu, N.; Yamada, M.; Yamamoto, A.; Yamamoto, K.; Yamamoto, S.; Yamamura, T.; Yamaoka, J.; Yamazaki, T.; Yamazaki, Y.; Yan, Z.; Yang, H.; Yang, U.K.; Yang, Z.; Yao, W-M.; Yao, Y.; Yasu, Y.; Ye, J.; Ye, S.; Yilmaz, M.; Yoosoofmiya, R.; Yorita, K.; Yoshida, R.; Young, C.; Youssef, S.P.; Yu, D.; Yu, J.; Yuan, L.; Yurkewicz, A.; Zaidan, R.; Zaitsev, A.M.; Zajacova, Z.; Zambrano, V.; Zanello, L.; Zaytsev, A.; Zeitnitz, C.; Zeller, M.; Zemla, A.; Zendler, C.; Zenin, O.; Zenis, T.; Zenonos, Z.; Zenz, S.; Zerwas, D.; della Porta, G.Zevi; Zhan, Z.; Zhang, H.; Zhang, J.; Zhang, Q.; Zhang, X.; Zhao, L.; Zhao, T.; Zhao, Z.; Zhemchugov, A.; Zhong, J.; Zhou, B.; Zhou, N.; Zhou, Y.; Zhu, C.G.; Zhu, H.; Zhu, Y.; Zhuang, X.; Zhuravlov, V.; Zimmermann, R.; Zimmermann, S.; Zimmermann, S.; Ziolkowski, M.; Zivkovic, L.; Zobernig, G.; Zoccoli, A.; zur Nedden, M.

2010-01-01

The ATLAS Inner Detector is a composite tracking system consisting of silicon pixels, silicon strips and straw tubes in a 2 T magnetic field. Its installation was completed in August 2008 and the detector took part in data- taking with single LHC beams and cosmic rays. The initial detector operation, hardware commissioning and in-situ calibrations are described. Tracking performance has been measured with 7.6 million cosmic-ray events, collected using a tracking trigger and reconstructed with modular pattern-recognition and fitting software. The intrinsic hit efficiency and tracking trigger efficiencies are close to 100%. Lorentz angle measurements for both electrons and holes, specific energy-loss calibration and transition radiation turn-on measurements have been performed. Different alignment techniques have been used to reconstruct the detector geometry. After the initial alignment, a transverse impact parameter resolution of 22.1+/-0.9 {\\mu}m and a relative momentum resolution {\\sigma}p/p = (4.83+/-0.16)...

Commissioning of the Silicon Strip Detector (SSD) of ALICE

NARCIS (Netherlands)

Christakoglou, P.; Botje, M.A.J.; Mischke, A.; van Leeuwen, M.

2009-01-01

The latest results from the commissioning of the SSD with cosmics are presented in this paper. The hardware status of the detector, the front-end electronics, cooling, data acquisition and issues related to the on-line monitoring are shown. In addition, the procedures implemented and followed to

Event-driven processing for hardware-efficient neural spike sorting

Science.gov (United States)

Liu, Yan; Pereira, João L.; Constandinou, Timothy G.

2018-02-01

Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

Automatic Analysis at the Commissioning of the LHC Superconducting Electrical Circuits

CERN Document Server

Reymond, H; Charrondiere, C; Rijllart, A; Zerlauth, M

2011-01-01

Since the beginning of 2010 the LHC has been operating in a routinely manner, starting with a commissioning phase and then an operation for physics phase. The commissioning of the superconducting electrical circuits requires rigorous test procedures before entering into operation. To maximize the beam operation time of the LHC, these tests should be done as fast as procedures allow. A full commissioning need 12000 tests and is required after circuits have been warmed above liquid nitrogen temperature. Below this temperature, after an end of year break of two months, commissioning needs about 6000 tests. As the manual analysis of the tests takes a major part of the commissioning time, we automated existing analysis tools. We present here how these LabVIEW™ applications were automated, the evaluation of the gain in commissioning time and reduction of experts on night shift observed during the LHC hardware commissioning campaign of 2011 compared to 2010. We end with an outlook at what can be further optimized.

Automatic analysis at the commissioning of the LHC superconducting electrical circuits

International Nuclear Information System (INIS)

Reymond, H.; Andreassen, O.O.; Charrondiere, C.; Rijllart, A.; Zerlauth, M.

2012-01-01

Since the beginning of 2010 the LHC has been operating in a routinely manner, starting with a commissioning phase and then an operation for physics phase. The commissioning of the superconducting electrical circuits requires rigorous test procedures before entering into operation. To maximize the beam operation time of the LHC, these tests should be done as fast as procedures allow. A full commissioning need 12000 tests and is required after circuits have been warmed above liquid nitrogen temperature. Below this temperature, after an end of year break of two months, commissioning needs about 6000 tests. As the manual analysis of the tests takes a major part of the commissioning time, we automated existing analysis tools. We present here how these LabVIEW TM applications were automated, the evaluation of the gain in commissioning time and reduction of experts on night shift observed during the LHC hardware commissioning campaign of 2011 compared to 2010. We end with an outlook at what can be further optimized. (authors)

COMMISSIONING AND DETECTOR PERFORMANCE GROUPS

CERN Multimedia

T. Camporesi

The central commissioning activities have concentrated mostly in the Service cavern. Since early February the central DAQ has been ready to accept connections from FEDs from the various partitions. This has triggered a campaign from all subdetectors to install their readout crates in USC55. Systematic tests of the connections between FEDs and Central DAQ have been scheduled and to date more than 70% of all FED connections have been successfully tested from almost all subdetectors. In March the Level 1 trigger team started deployment of their hardware followed by a campaign of testing the connections between Trigger primitive generators and the corresponding LV1 hardware (Regional Calorimeter Trigger and Global Muon Trigger). The functionality tests are continuing to date by pattern tests of increasing complexity. In April the central DAQ was ready to start FED system tests, which amounts to testing the data reading and trans¬fer-ability from the FEDs to the Filter Units (with or without an actual ...

Virtual commissioning of automated micro-optical assembly

Science.gov (United States)

Schlette, Christian; Losch, Daniel; Haag, Sebastian; Zontar, Daniel; Roßmann, Jürgen; Brecher, Christian

2015-02-01

In this contribution, we present a novel approach to enable virtual commissioning for process developers in micro-optical assembly. Our approach aims at supporting micro-optics experts to effectively develop assisted or fully automated assembly solutions without detailed prior experience in programming while at the same time enabling them to easily implement their own libraries of expert schemes and algorithms for handling optical components. Virtual commissioning is enabled by a 3D simulation and visualization system in which the functionalities and properties of automated systems are modeled, simulated and controlled based on multi-agent systems. For process development, our approach supports event-, state- and time-based visual programming techniques for the agents and allows for their kinematic motion simulation in combination with looped-in simulation results for the optical components. First results have been achieved for simply switching the agents to command the real hardware setup after successful process implementation and validation in the virtual environment. We evaluated and adapted our system to meet the requirements set by industrial partners-- laser manufacturers as well as hardware suppliers of assembly platforms. The concept is applied to the automated assembly of optical components for optically pumped semiconductor lasers and positioning of optical components for beam-shaping

Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

DEFF Research Database (Denmark)

Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

1998-01-01

as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search.......This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...

A Scalable Approach for Hardware Semiformal Verification

OpenAIRE

Grimm, Tomas; Lettnin, Djones; Hübner, Michael

2018-01-01

The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation and FPGA prototyping. However, none is able to verify a complete architecture. Furthermore, hybrid approaches aiming at complete verification use techniques that lower the overall complexity by increasing the abstraction level. This work focuses on the verification of complex systems at the RT level to handle the hardware peculiarities. Our r...

Automated Execution and Tracking of the LHC Commissioning Tests

CERN Document Server

Fuchsberger, K; Galetzka, M; Gorbonosov, R; Pojer, M; Solfaroli Camillocci, M; Zerlauth, M

2012-01-01

To ensure the correct operation and prevent system failures, which can lead to equipment damage in the worst case, all critical systems in the Large Hadron Collider (LHC), among them the superconducting circuits, have to be tested thoroughly during dedicated commissioning phases after each intervention. In view of the around 7,000 individual tests to be performed each year after a Christmas stop, a lot of effort was already put into the automation of these tests at the beginning of LHC hardware commissioning in 2005, to assure the dependable execution and analysis of these tests. To further increase the productivity during the commissioning campaigns and to enforce a more consistent workflow, the development of a dedicated testing framework was launched. This new framework is designed to schedule and track the automated tests for all systems of the LHC and will also be extendable, e.g., to beam commissioning tests. This is achieved by re-using different, already existing execution frameworks. In this paper, w...

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

Science.gov (United States)

Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

Hardware for soft computing and soft computing for hardware

CERN Document Server

Nedjah, Nadia

2014-01-01

Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

International Nuclear Information System (INIS)

Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

Energy Technology Data Exchange (ETDEWEB)

Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

Digital Hardware Design Teaching: An Alternative Approach

Science.gov (United States)

Benkrid, Khaled; Clayton, Thomas

2012-01-01

This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

LHC Report: finalizing the shutdown activities

CERN Multimedia

CERN Bulletin

2011-01-01

The maintenance work and other activities scheduled for the LHC technical stop have now been completed and the electrical, quality assurance and powering tests are in full swing.   These hardware tests, or hardware re-commissioning as it is known in the CERN Control Centre, are complete for Sectors 5-6 and 6-7. The re-commissioning process is almost complete in Sectors 7-8 and 8-1, but a problem with the emergency stop safety system last week, and the failure of a turbine in the cryogenic plant at Point 8, mean that the final part of the re-commissioning for these two sectors has been delayed and will be completed this week. Preparations for the re-commissioning in the other 4 sectors are going well, and everything is on schedule for the LHC to restart with beam as planned on 18 February. At the SPS, all the technical stop work and magnet changes have been completed and the machine has been handed over to the Operations Group for the usual set of hardware tests and preparations for beam operation. ...

The NUCLARR databank: Human reliability and hardware failure data for the nuclear power industry

International Nuclear Information System (INIS)

Reece, W.J.

1993-01-01

Under the sponsorship of the US Nuclear Regulatory Commission (NRC), the Nuclear Computerized Library for Assessing Reactor Reliability (NUCLARR) was developed to provide human reliability and hardware failure data to analysts in the nuclear power industry. This IBM-compatible databank is contained on a set of floppy diskettes which include data files and a menu-driven system for locating, reviewing, sorting, and retrieving the data. NUCLARR contains over 2500 individual data records, drawn from more, than 60 sources. The system is upgraded annually, to include additional human error and hardware component failure data and programming enhancements (i.e., increased user-friendliness). NUCLARR is available from the NRC through project staff at the INEL

SPS completes LS1 activities

CERN Multimedia

Katarina Anthony

2014-01-01

On 27 June, the SPS closed its doors to the LS1 engineers, bringing to an end almost 17 months of activities. The machine now enters the hardware-testing phase in preparation for an October restart.   Photo 1: The SPS transfer tunnel, TT10, reinforced with steal beams. Having completed their LS1 activities right on schedule (to the day!), the SPS team is now preparing the machine for its restart. Over the next eight weeks, hardware tests of the SPS dipole and quadrupole power converters will be underway, led by the TE-EPC (Electrical Power Converters) team. "OP start-up test activities will also be running in parallel, utilising the off hours when EPC is not using the machine," says David McFarlane, the SPS technical coordinator from the Engineering Department. "The primary beam testing phase will start at the beginning of September, once hardware tests and DSO safety tests have been completed." It has been a long journey to this point, with several major...

Introduction to Hardware Security

Directory of Open Access Journals (Sweden)

Yier Jin

2015-10-01

Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

Computer hardware for radiologists: Part I

International Nuclear Information System (INIS)

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium ® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration

Computer hardware for radiologists: Part I

Directory of Open Access Journals (Sweden)

Indrajit I

2010-01-01

Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

PCI hardware support in LIA-2 control system

International Nuclear Information System (INIS)

Bolkhovityanov, D.; Cheblakov, P.

2012-01-01

The control system of the LIA-2 accelerator is built on cPCI crates with *86- compatible processor boards running Linux. Slow electronics is connected via CAN-bus, while fast electronics (4 MHz and 200 MHz fast ADCs and 200 MHz timers) are implemented as cPCI/PMC modules. Several ways to drive PCI control electronics in Linux were examined. Finally a user-space drivers approach was chosen. These drivers communicate with hardware via a small kernel module, which provides access to PCI BARs and to interrupt handling. This module was named USPCI (User-Space PCI access). This approach dramatically simplifies creation of drivers, as opposed to kernel drivers, and provides high reliability (because only a tiny and thoroughly-debugged piece of code runs in kernel). LIA-2 accelerator was successfully commissioned, and the solution chosen has proven adequate and very easy to use. Besides, USPCI turned out to be a handy tool for examination and debugging of PCI devices direct from command-line. In this paper available approaches to work with PCI control hardware in Linux are considered, and USPCI architecture is described. (authors)

78 FR 13887 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2013-03-01

... Washington State Parks and Recreation Commission at the address below by April 1, 2013. ADDRESSES: Alicia... contact Alicia Woods, Washington State Parks and Recreation Commission, PO Box 42650, Olympia, WA 98504...

78 FR 44594 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2013-07-24

..., 2013. ADDRESSES: Alicia Woods, Washington State Parks and Recreation Commission, PO Box 42650, Olympia, WA 98504-2650, telephone (360) 902- 0939, email Alicia[email protected] . SUPPLEMENTARY INFORMATION... to Alicia Woods, Washington State Parks and Recreation Commission, PO Box 42650, Olympia, WA 98504...

Hardware-in-the-loop environment for the design and test of regulators in the refrigeration technology; Hardware-in-the-Loop Umgebung fuer den Entwurf und Test von kaeltetechnischen Reglern

Energy Technology Data Exchange (ETDEWEB)

Koeberle, Thomas; Becker, Martin [Hochschule Biberach (Germany). Inst. fuer Gebaeude- und Energiesysteme

2012-07-01

In its Directive on energy efficiency, The European Commission has specified a target value for saving primary energy by 20 % up the year 2020. According to current projections, the target will be failed by half. This is why significantly more efforts are needed. The energy consumption of the technical supply of coldness amounts nearly 14 % of the total consumption of electrical power in Germany. The Research Council Coldness specifies that the potential for energy conservation in the refrigeration engineering amounts up to 40 %. Thus, more effort must be made in the refrigeration engineering in order to reach the energy saving targets of the European Commission. Thereby, the major portion of the potential of energy saving consists of the establishment of the requirements in regard to system concepts and components as well as the control. The control of refrigeration systems provides a simple possibility of intervention to optimize the energy efficiency. The optimization of control parameters is usually achieved only with great experience and knowledge. There are any tools which facilitate an objective comparison of optimization measures of control concepts, strategies and settings. In order to facilitate the evaluation and comparison of refrigeration controls, a hardware-in-the-loop test environment was set up at the University of Applied Sciences in Biberach (Federal Republic of Germany). The test environment facilitates an implementation of a controller in a simulation environment so that the controller drives the simulation model of the chiller. Due to this procedure, tests are possible under standardized and reproducible conditions. The impact of modified control parameters, disturbances and modifications in the regulatory approach can be investigated by means of the possibility of a targeted impacting of individual disturbances. The test rig was designed, built and tested at the University of Applied Sciences in Biberach. Simulation models were adapted to the

Hardware description languages

Science.gov (United States)

Tucker, Jerry H.

1994-01-01

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

A Hardware Lab Anywhere At Any Time

Directory of Open Access Journals (Sweden)

Tobias Schubert

2004-12-01

Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

Preparation and procedures of pre-commissioning on DECY-13 cyclotron

International Nuclear Information System (INIS)

Silakhuddin

2016-01-01

A preparation and procedures for pre-commissioning of DECY-13 Cyclotron have been discussed and the steps for these have been arranged. Pre-commissioning is a testing stage of individual subsystems when all subsystems have been integrated into a cyclotron system. The discussion was taken from references, the next the readiness of devices was studied and then the preparation and procedures of the pre-commissioning were arranged. The results of the discussion are that for doing the pre-commissioning of the cyclotron DECY-13 still requires the completion of RF-dee subsystem and some components for testing are still to be completed. (author)

A hardware overview of the RHIC LLRF platform

International Nuclear Information System (INIS)

Hayes, T.; Smith, K.S.

2011-01-01

The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Directory of Open Access Journals (Sweden)

Manuel Saldaña

2009-01-01

Full Text Available High-performance reconfigurable computers (HPRCs provide a mix of standard processors and FPGAs to collectively accelerate applications. This introduces new design challenges, such as the need for portable programming models across HPRCs and system-level verification tools. To address the need for cosimulating a complete heterogeneous application using both software and hardware in an HPRC, we have created a tool called the Message-passing Simulation Framework (MSF. We have used it to simulate and develop an interface enabling an MPI-based approach to exchange data between X86 processors and hardware engines inside FPGAs. The MSF can also be used as an application development tool that enables multiple FPGAs in simulation to exchange messages amongst themselves and with X86 processors. As an example, we simulate a LINPACK benchmark hardware core using an Intel-FSB-Xilinx-FPGA platform to quickly prototype the hardware, to test the communications. and to verify the benchmark results.

IDEAS and App Development Internship in Hardware and Software Design

Science.gov (United States)

Alrayes, Rabab D.

2016-01-01

In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

Using EPICS enabled industrial hardware for upgrading control systems

International Nuclear Information System (INIS)

Bjorkland, Eric A.; Veeramani, Arun; Debelle, Thierry

2009-01-01

Los Alamos National Laboratory has been working with National Instruments (NI) and Cosy lab to implement EPICS Input Output Controller (IOC) software that runs directly on NI CompactRIO Real Time Controller (RTC) and communicates with NI LabVIEW through a shared memory interface. In this presentation, we will discuss our current progress in upgrading the control system at the Los Alamos Neutron Science Centre (LANSCE) and what we have learned about integrating CompactRIO into large experimental physics facilities. We will also discuss the implications of using Channel Access Server for LabVIEW which will enable more commercial hardware platforms to be used in upgrading existing facilities or in commissioning new ones.

Foundations of hardware IP protection

CERN Document Server

Torres, Lionel

2017-01-01

This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

Open hardware for open science

CERN Multimedia

CERN Bulletin

2011-01-01

Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

Open Hardware Business Models

OpenAIRE

Edy Ferreira

2008-01-01

In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

Open Hardware Business Models

Directory of Open Access Journals (Sweden)

Edy Ferreira

2008-04-01

Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

Startup and commissioning of pressurized water reactors

International Nuclear Information System (INIS)

Albert, L.J.; Gilbert, C.F.

1983-05-01

A critical phase of plant development is the test, startup, and commissioning period. The effort expended prior to commissioning has a definite effect on the reliability and continuing availability of the plant during its life. This paper describes a test, startup, and commissioning program for a pressurized water reactor (PWR) plant. This program commences with the completion of construction and continues through the turnover of equipment/systems to the owner's startup/ commissioning group. The paper addresses the organization of the test/startup group, planning and scheduling, test procedures and initial testing, staffing and certification of the test group, training of operators, and turnover to the owner

Fast image processing on parallel hardware

International Nuclear Information System (INIS)

Bittner, U.

1988-01-01

Current digital imaging modalities in the medical field incorporate parallel hardware which is heavily used in the stage of image formation like the CT/MR image reconstruction or in the DSA real time subtraction. In order to image post-processing as efficient as image acquisition, new software approaches have to be found which take full advantage of the parallel hardware architecture. This paper describes the implementation of two-dimensional median filter which can serve as an example for the development of such an algorithm. The algorithm is analyzed by viewing it as a complete parallel sort of the k pixel values in the chosen window which leads to a generalization to rank order operators and other closely related filters reported in literature. A section about the theoretical base of the algorithm gives hints for how to characterize operations suitable for implementations on pipeline processors and the way to find the appropriate algorithms. Finally some results that computation time and usefulness of medial filtering in radiographic imaging are given

Curriculum for Commissioning Energy Efficient Buildings

Energy Technology Data Exchange (ETDEWEB)

Webster, Lia [Portland Energy Conservation, Inc., OR (United States)

2012-12-27

In July 2010, the U.S. Department of Energy (DOE) awarded funding to PECI to develop training curriculum in commercial energy auditing and building commissioning. This program was created in response to the high demand for auditing and commissioning services in the U.S. commercial buildings market and to bridge gaps and barriers in existing training programs. Obstacles addressed included: lack of focus on entry level candidates; prohibitive cost and time required for training; lack of hands-on training; trainings that focus on certifications & process overviews; and lack of comprehensive training. PECI organized several other industry players to create a co-funded project sponsored by DOE, PECI, New York State Energy and Research Development Authority (NYSERDA), California Energy Commission (CEC), Northwest Energy Efficiency Alliance (NEEA) and California Commissioning Collaborative (CCC). After awarded, PECI teamed with another DOE awardee, New Jersey Institute of Technology (NJIT), to work collaboratively to create one comprehensive program featuring two training tracks. NJIT’s Center for Building Knowledge is a research and training institute affiliated with the College of Architecture and Design, and provided e-learning and video enhancements. This project designed and developed two training programs with a comprehensive, energy-focused curriculum to prepare new entrants to become energy auditors or commissioning authorities (CxAs). The following are the key elements of the developed trainings, which is depicted graphically in Figure 1: • Online classes are self-paced, and can be completed anywhere, any time • Commissioning Authority track includes 3 online modules made up of 24 courses delivered in 104 individual lessons, followed by a 40 hour hands-on lab. Total time required is between 75 and 100 hours, depending on the pace of the independent learner. • Energy Auditor track includes 3 online modules made up of 18 courses delivered in 72 individual

Tools for a simulation supported commissioning of the automation of HVAC plants. Hardware-in-the-loop in building automation; Werkzeuge fuer eine simulationsgestuetzte Inbetriebnahme der Automation von RLT- Anlagen. Hardware-in-the-Loop in der Gebaeudeautomation

Energy Technology Data Exchange (ETDEWEB)

Richter, Andreas; Sokollik, Frank [Hochschule Merseburg (Germany). Fachbereich Informatik und Kommunikationssysteme

2012-07-01

Hardware-in-the-loop (HiL) is a method for testing and validating technical automation solutions based on virtual processes in a simulation environment. Applied to the automation of the interior air supply systems, preceded commissioning tests of the controller at a simulated system can be performed. These tests can be used for example to find logic errors in the program development, or to adjust the parameters of a controller. The adjustment of the parameters can be performed independent of the seasons by modifying the ambient climatic conditions. The parameters of the plants can be tested under dynamic conditions. The control mode can be visualized by starting up of load conditions at dynamic HVAC components and optimized if necessary. Within BMBF funded projects, a HiL solution was developed in a.NET environment. The coupling of simulation and control takes place via the bus systems CAN and BACnet. The elements of the simulation of air conditioners are implemented object-oriented in the programming language C, and are based on the solution of dynamic mass and energy balances. The features of HIL are implemented in a multi-client architecture. This includes primarily the simulation and communication. Other feature are implemented: import of virtual systems from a CAE system, adjustment of parameters of the simulation using structured sets of parameters, features for a distributed simulation of complex systems in the network, a tool for the dimensioning of controllers, chart and visualization features.

Open Hardware at CERN

CERN Multimedia

CERN Knowledge Transfer Group

2015-01-01

CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

NSLS-II injector commissioning and initial operation

Energy Technology Data Exchange (ETDEWEB)

Bacha, B.; Blum, E.; Bassi, B.; Bengtsson, J.; Blednykh, A.; Buda, S.; Cheng, W.; Choi, J.; Cuppolo, J.; D Alsace, R.; Davidsaver, M.; DeLong, J.; Doom, L.; Durfee, d.; fliller, R.; Fulkerson, M.; Ganetis, G.; Gao, F.; Gardner, C.; Guo, W.; Heese, R.; Hidaka, Y.; Hu, Y.; Johanson, M.; Kosciuk, B.; Kowalski, S.; Dramer, S.; Krinsky, S.; Li, Y.; Louie, W.; Maggipinto, M.; Marino, P.; Mead, J.; Oliva, G.; Padrazo, D.; Pedersen, K.; Podobedov, B.; Rainer, R.; Rose, J.; Santana, M.; Seletskiy, S.; Shaftan, T.; Singh, O.; Singh, P.; Smalyuk, V.; Smith, R.; Summers, T.; Tagger, J.; Tian, Y.; Wahl, W.; Wang, G.; Weiner, G.; Willeke, F.; Yang, L.; Yang, X.; Zeitler, E.; Zitvogel, E.; Zuhoski, P.

2015-05-03

The injector for the National Synchrotron Light Source II (NSLS-II) storage ring consists of a 3 GeV booster synchrotron and a 200 MeV S-band linac. The linac was designed to produce either a single bunch with a charge of 0.5 nC of electrons or a train of bunches up to 300 ns long containing a total charge of 15 nC. The booster was designed to accelerate up to 15 nC each cycle in a train of bunches up to 300 ns long. Linac commissioning was completed in April 2012. Booster commissioning was started in November 2013 and completed in March 2014. All of the significant design goals were satisfied including beam emittance, energy spread, and transport efficiency. While the maximum booster charge accelerated was only 10 nC, this has proven to be more than sufficient for storage ring commissioning and operation. The injector has operated reliably during storage ring operation since then. Results will be presented showing measurements of linac and booster operating parameters achieved during commissioning and initial operation. Operating experience and reliability during the first year of NSLS-II operation will be discussed.

BROOKHAVEN: Booster commissioned

Energy Technology Data Exchange (ETDEWEB)

Bleser, Ed

1992-03-15

The construction and first commissioning phase of the Booster synchrotron to inject into Brookhaven's veteran Alternating Gradient Synchrotron (AGS) were completed last year. Scheduled to come into operation this year, the new Booster will extend the research capabilities AGS, and with its ability to accelerate partially stripped heavy ions will play an essential role in the chain of accelerators serving the Relativistic Heavy Ion Collider (RHIC)

Hardware protection through obfuscation

CERN Document Server

Bhunia, Swarup; Tehranipoor, Mark

2017-01-01

This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

International Nuclear Information System (INIS)

Williamson, D.A.

1991-01-01

Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas ampersand Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States' utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste

Commissioning and Validation of the ATLAS Level-1 Topological Trigger in Run 2

CERN Document Server

Zheng, Daniel; The ATLAS collaboration

2017-01-01

The ATLAS experiment has introduced and recently commissioned a completely new hardware sub-system of its first-level trigger: the topological processor (L1Topo). L1Topo consist of two AdvancedTCA blades mounting state-of-the-art FPGA processors, providing high input bandwidth (up to 4 Gb/s) and low latency data processing (200 ns). L1Topo is able to select collision events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Results from data recorded using the L1Topo trigger will be presented. These results demonstrate a significantly improved background event rejection, thus allowing for rate reduction with minimal efficiency loss. This improvement has been shown for several physics processes leading to low-$p_T$ leptons, including $H\\rightarrow\\tau \\tau$ and $J/\\psi \\rightarrow \\mu \\mu$. In addition to describing the L1Topo trigger system, we will discuss the use of an accurate L1Topo simulation as a pow...

Hardware Support for Embedded Java

DEFF Research Database (Denmark)

Schoeberl, Martin

2012-01-01

The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

Results from Commissioning of the Energy Extraction Facilities of the LHC Machine

CERN Document Server

Coelingh, G J; Mess, K H

2008-01-01

The risk of damage to the superconducting magnets, bus bars and current leads of the LHC machine in case of a resistive transition (quench) is being minimized by adequate protection. The protection is based on early quench detection, bypassing the quenching magnets by cold diodes, energy density dilution in the quenching magnets using heaters and, eventually, energy extraction. For two hundred and twenty-six LHC circuits (600 A and 13 kA) extraction of the stored magnetic energy to external dump resistors was required. All these systems are now installed in the machine and the final hardware commissioning has been undertaken. After a short description of the topology and definitive features, layouts and parameters of these systems the paper will focus on the results from their successful commissioning and an analysis of the system performance.

Development of a hardware-in-loop attitude control simulator for a CubeSat satellite

Science.gov (United States)

Tapsawat, Wittawat; Sangpet, Teerawat; Kuntanapreeda, Suwat

2018-01-01

Attitude control is an important part in satellite on-orbit operation. It greatly affects the performance of satellites. Testing of an attitude determination and control subsystem (ADCS) is very challenging since it might require attitude dynamics and space environment in the orbit. This paper develops a low-cost hardware-in-loop (HIL) simulator for testing an ADCS of a CubeSat satellite. The simulator consists of a numerical simulation part, a hardware part, and a HIL interface hardware unit. The numerical simulation part includes orbital dynamics, attitude dynamics and Earth’s magnetic field. The hardware part is the real ADCS board of the satellite. The simulation part outputs satellite’s angular velocity and geomagnetic field information to the HIL interface hardware. Then, based on this information, the HIL interface hardware generates I2C signals mimicking the signals of the on-board rate-gyros and magnetometers and consequently outputs the signals to the ADCS board. The ADCS board reads the rate-gyro and magnetometer signals, calculates control signals, and drives the attitude actuators which are three magnetic torquers (MTQs). The responses of the MTQs sensed by a separated magnetometer are feedback to the numerical simulation part completing the HIL simulation loop. Experimental studies are conducted to demonstrate the feasibility and effectiveness of the simulator.

HARDWARE TROJAN IDENTIFICATION AND DETECTION

OpenAIRE

Samer Moein; Fayez Gebali; T. Aaron Gulliver; Abdulrahman Alkandari

2017-01-01

ABSTRACT The majority of techniques developed to detect hardware trojans are based on specific attributes. Further, the ad hoc approaches employed to design methods for trojan detection are largely ineffective. Hardware trojans have a number of attributes which can be used to systematically develop detection techniques. Based on this concept, a detailed examination of current trojan detection techniques and the characteristics of existing hardware trojans is presented. This is used to dev...

Hunting for hardware changes in data centres

International Nuclear Information System (INIS)

Coelho dos Santos, M; Steers, I; Szebenyi, I; Xafi, A; Barring, O; Bonfillou, E

2012-01-01

With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

Open-source hardware for medical devices.

Science.gov (United States)

Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

2016-04-01

Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

Horizontal mergers and weak and strong competition commissions

Directory of Open Access Journals (Sweden)

Ristić Bojan

2014-01-01

Full Text Available In this paper we analyse the horizontal merger of companies in an already concentrated industry. The participants in mergers are obliged to submit notification to the Competition Commission but they also have the option of rejecting the merger. At the time of the notification submission the participants do not know whether the Commission is strong or weak, and they can complain to the Court if the Commission prohibits the merger. We model the strategic interaction between Participants and Commission in a dynamic game of incomplete information and determine weak perfect Bayesian equilibria. The main finding of our paper is that Participants will base their decision to submit notification on their belief in a weak Commission decision and will almost completely ignore the possibility of a strong Commission decision. We also provide a detailed examination of one case from Serbian regulatory practice, which coincides with the results of our game theoretical model.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Science.gov (United States)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Directory of Open Access Journals (Sweden)

David R. W. Barr

2009-01-01

Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

An evaluation of Skylab habitability hardware

Science.gov (United States)

Stokes, J.

1974-01-01

For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

Commissioning the Linac Coherent Light Source injector

Directory of Open Access Journals (Sweden)

R. Akre

2008-03-01

Full Text Available The Linac Coherent Light Source is a SASE x-ray free-electron laser (FEL project presently under construction at SLAC [J. Arthur et al., SLAC-R-593, 2002.]. The injector section, from drive laser and rf photocathode gun through first bunch compressor chicane, was installed in the fall of 2006. The initial system commissioning with an electron beam was completed in August of 2007, with the goal of a 1.2-micron emittance in a 1-nC bunch demonstrated. The second phase of commissioning, including second bunch compressor and full linac, is planned for 2008, with FEL commissioning in 2009. We report experimental results and experience gained in the first phase of commissioning, including the photocathode drive laser, rf gun, photocathode, S-band and X-band rf systems, first bunch compressor, and the various beam diagnostics.

Is Hardware Removal Recommended after Ankle Fracture Repair?

Directory of Open Access Journals (Sweden)

Hong-Geun Jung

2016-01-01

Full Text Available The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients’ daily activities. This study was conducted on 80 consecutive cases (78 patients treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6 and decreased to 1.3 (range 0 to 6 after removal. 58 (72.5% patients experienced improved ankle stiffness and 65 (81.3% less discomfort while walking on uneven ground and 63 (80.8% patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

Door Hardware and Installations; Carpentry: 901894.

Science.gov (United States)

Dade County Public Schools, Miami, FL.

The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

OpenMM 4: A Reusable, Extensible, Hardware Independent Library for High Performance Molecular Simulation.

Science.gov (United States)

Eastman, Peter; Friedrichs, Mark S; Chodera, John D; Radmer, Randall J; Bruns, Christopher M; Ku, Joy P; Beauchamp, Kyle A; Lane, Thomas J; Wang, Lee-Ping; Shukla, Diwakar; Tye, Tony; Houston, Mike; Stich, Timo; Klein, Christoph; Shirts, Michael R; Pande, Vijay S

2013-01-08

OpenMM is a software toolkit for performing molecular simulations on a range of high performance computing architectures. It is based on a layered architecture: the lower layers function as a reusable library that can be invoked by any application, while the upper layers form a complete environment for running molecular simulations. The library API hides all hardware-specific dependencies and optimizations from the users and developers of simulation programs: they can be run without modification on any hardware on which the API has been implemented. The current implementations of OpenMM include support for graphics processing units using the OpenCL and CUDA frameworks. In addition, OpenMM was designed to be extensible, so new hardware architectures can be accommodated and new functionality (e.g., energy terms and integrators) can be easily added.

COMMISSIONING AND DETECTOR PERFORMANCE GROUPS

CERN Multimedia

D. Acosta

The global commissioning campaign begins this year with a series of weekly two-day global runs of limited participation until mid-March. The aim of these runs varies week-to-week, but includes the commissioning the calorimeter triggers, the muon track-finder triggers in the DT/CSC overlap, the PLL locking ranges, and generally accumulating data either for HCAL noise characterization or detector studies with cosmic muons. In mid-March a full Global Run is scheduled with all components participating, followed in April by a Cosmic Run with the aim of collecting statistics over a couple weeks with the installed Tracker and other subsystems. The ultimate milestone is the Cosmic Run At Four Tesla (CRAFT), with a completed CMS closed and the solenoid energized for data-taking during June. The Detector Performance Groups start the year with the focus to prepare for LHC collisions, and the associated challenges (CSA08) and global commissioning exercises (CRAFT) along the way. New this year is the addition of the Tri...

77 FR 61782 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2012-10-11

... Washington State Parks and Recreation Commission at the address below by November 13, 2012. ADDRESSES: Alicia... affiliated with the human remains should contact Alicia Woods, Washington State Parks and Recreation...

Digital Hardware Realization of Forward and Inverse Kinematics for a Five-Axis Articulated Robot Arm

Directory of Open Access Journals (Sweden)

Bui Thi Hai Linh

2015-01-01

Full Text Available When robot arm performs a motion control, it needs to calculate a complicated algorithm of forward and inverse kinematics which consumes much CPU time and certainty slows down the motion speed of robot arm. Therefore, to solve this issue, the development of a hardware realization of forward and inverse kinematics for an articulated robot arm is investigated. In this paper, the formulation of the forward and inverse kinematics for a five-axis articulated robot arm is derived firstly. Then, the computations algorithm and its hardware implementation are described. Further, very high speed integrated circuits hardware description language (VHDL is applied to describe the overall hardware behavior of forward and inverse kinematics. Additionally, finite state machine (FSM is applied for reducing the hardware resource usage. Finally, for verifying the correctness of forward and inverse kinematics for the five-axis articulated robot arm, a cosimulation work is constructed by ModelSim and Simulink. The hardware of the forward and inverse kinematics is run by ModelSim and a test bench which generates stimulus to ModelSim and displays the output response is taken in Simulink. Under this design, the forward and inverse kinematics algorithms can be completed within one microsecond.

From Open Source Software to Open Source Hardware

OpenAIRE

Viseur , Robert

2012-01-01

Part 2: Lightning Talks; International audience; The open source software principles progressively give rise to new initiatives for culture (free culture), data (open data) or hardware (open hardware). The open hardware is experiencing a significant growth but the business models and legal aspects are not well known. This paper is dedicated to the economics of open hardware. We define the open hardware concept and determine intellectual property tools we can apply to open hardware, with a str...

Preparation of physics commissioning of Mochovce units 3 and 4

International Nuclear Information System (INIS)

Sedlacek, M.; Chrapciak, V.

2010-01-01

The Project 'Mochovce Units 3 and 4 Completion' started in 2009 and it will be finished in 2013. VUJE, Inc. is one of the five main Project contractors for the Nuclear Island and it is responsible, inter alia, for Mochovce Units 3 and 4 commissioning. The commissioning of Units 3 and 4 includes the stages of Physics Commissioning and Power Commissioning. This paper deals with the preparation of Mochovce Units 3 and 4 Physics Commissioning. In the paper there is presented a preparation of some commissioning documents, e.g. 'Quality Assurance Programme', 'Commissioning Programme', 'Stage Programme for Physics Commissioning', 'Test working programmes', 'Neutron-physics characteristics for Physics and Power Commissioning', etc. The scope of Physics Commissioning is presented by list of tests. For assessment of tests results so-called three-level acceptance criteria will be applied: realization, design and safety criteria. In the paper there are also presented computer codes, which will be used for neutron-physics characteristics calculation and the fuel loading scheme for the reactor core of Mochovce Unit 3. (Authors)

A leading-edge hardware family for diagnostics applications and low-level RF in CERN's ELENA ring

CERN Document Server

Angoletta, M E; Jaussi, M; Leiononen, P; Levens, T E; Molendijk, J C; Sanchez-Quesada, J; Simonin, J

2013-01-01

The CERN Extra Low ENergy Antiproton (ELENA) Ring is a new synchrotron that will be commissioned in 2016 to further decelerate the antiprotons transferred from the CERN’s Antiproton Decelerator (AD). The requirements for the acquisition and treatment of signals for longitudinal diagnostics are very demanding, owing to the revolution frequency swing as well as to the digital signal processing required. The requirements for the Low-Level Radio-Frequency (LLRF) system are very demanding as well, especially in terms of revolution frequency swing, dynamic range and low noise required by the cavity voltage control and digital signal processing to be performed. Both sets of requirements will be satisfied by using a leading-edge hardware family, developed to cover the LLRF needs of all synchrotrons in the Meyrin site; it will be first deployed in 2014 in the CERN’s PSB and in the medical machine MedAustron. This paper gives an overview of the main building blocks of the hardware family and of th...

PROMOTER COMMISSION LEGISLATIVE AND EXTERNAL REPRESENTATIVE OF THE UNION

Directory of Open Access Journals (Sweden)

Nely Militaru

2014-11-01

Full Text Available Commission was established by the Treaty establishing the Economic Community of Coal and Osel – signed in Paris in 1951, entered into force next year –as the High Authority supranational institution with discretionary decisionmaking powers in optics of this treaty. Also known as “guardian of the treaties” Commission by its member, who exercise their functions in complete independence, is an institution that promotes the general interest of the Union (art. 17 par.TEU. Commission oversees therefore application of Union law. In this capacity, especially in terms of the competence of the legislative proposal, the Commission by calling upon specialists and experts from EU Member States harmonize with the national interest.

Commissioning the SNO+ Detector

Science.gov (United States)

Caden, E.; Coulter, I.; SNO+ Collaboration

2017-09-01

SNO+ is a multipurpose liquid scintillator neutrino experiment based at SNOLAB in Sudbury, Ontario, Canada. The experiment’s main physics goal is a search for neutrinoless double beta decay in Tellurium-130, but SNO+ will also study low energy solar neutrinos, geo- and reactor-antineutrinos, among other topics. We are reusing much of the hardware from the original SNO experiment, but significant work has taken place to transform the heavy water detector into a liquid scintillator detector. We present upgrades and improvements to the read-out electronics and trigger system to handle the higher data rates expected by a scintillator experiment. We show the successful installation and testing of a hold-down rope net for the acrylic vessel to counter-act the buoyancy of organic liquid scintillator. We also describe the new scintillator process plant and cover gas systems that have been constructed to achieve the purification necessary to meet our physics goals. We are currently commissioning the experiment with ultra-pure water in preparation for filling with scintillator in early 2017 and present the current status of this work.

77 FR 48535 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2012-08-14

...: Alicia Woods, Washington State Parks and Recreation Commission, P.O. Box 42650, Olympia, WA 98504-2650... it satisfies the criteria in 43 CFR 10.11(c)(1) should contact Alicia Woods, Washington State Parks...

ZEUS hardware control system

Science.gov (United States)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-12-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

ZEUS hardware control system

International Nuclear Information System (INIS)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-01-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users. (orig.)

Studies for the Commissioning of the CERN CMS Silicon Strip Tracker

CERN Document Server

Bloch, Christoph; Abbaneo, Duccio; Fabjan, Christian Wolfgang

2008-01-01

In 2008 the Large Hadron Collider (LHC) at CERN will start producing proton-proton collisions of unprecedented energy. One of its main experiments is the Compact Muon Solenoid (CMS), a general purpose detector, optimized for the search of the Higgs boson and super symmetric particles. The discovery potential of the CMS detector relies on a high precision tracking system, made of a pixel detector and the largest silicon strip Tracker ever built. In order to operate successfully a device as complex as the CMS silicon strip Tracker, and to fully exploit its potential, the properties of the hardware need to be characterized as precisely as possible, and the reconstruction software needs to be commissioned with physics signals. A number of issues were identified and studied to commission the detector, some of which concern the entire Tracker, while some are specific to the Tracker Outer Barrel (TOB): - the time evolution of the signals in the readout electronics need to be precisely measured and correctly simulate...

NDAS Hardware Translation Layer Development

Science.gov (United States)

Nazaretian, Ryan N.; Holladay, Wendy T.

2011-01-01

The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

Hardware standardization for embedded systems

International Nuclear Information System (INIS)

Sharma, M.K.; Kalra, Mohit; Patil, M.B.; Mohanty, Ashutos; Ganesh, G.; Biswas, B.B.

2010-01-01

Reactor Control Division (RCnD) has been one of the main designers of safety and safety related systems for power reactors. These systems have been built using in-house developed hardware. Since the present set of hardware was designed long ago, a need was felt to design a new family of hardware boards. A Working Group on Electronics Hardware Standardization (WG-EHS) was formed with an objective to develop a family of boards, which is general purpose enough to meet the requirements of the system designers/end users. RCnD undertook the responsibility of design, fabrication and testing of boards for embedded systems. VME and a proprietary I/O bus were selected as the two system buses. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented on FPGA/CPLD using VHDL. This paper outlines the various boards that have been developed with a brief description. (author)

Hardware for dynamic quantum computing.

Science.gov (United States)

Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

2017-10-01

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

Commissioning (Phases 4, 4A, 4B)

National Research Council Canada - National Science Library

Schofield, Andrew

1997-01-01

Phase 4 marked the completion of ANS&A's commitments under the BAA, as the new large centrifuge at the Waterways Experiment Station was commissioned and a series of research experiments were undertaken to demonstrate the breadth of new...

Construction and Commissioning of PAL-XFEL Facility

Directory of Open Access Journals (Sweden)

In Soo Ko

2017-05-01

Full Text Available The construction of Pohang Accelerator Laboratory X-ray Free-Electron Laser (PAL-XFEL, a 0.1-nm hard X-ray free-electron laser (FEL facility based on a 10-GeV S-band linear accelerator (LINAC, is achieved in Pohang, Korea by the end of 2016. The construction of the 1.11 km-long building was completed by the end of 2014, and the installation of the 10-GeV LINAC and undulators started in January 2015. The installation of the 10-GeV LINAC, together with the undulators and beamlines, was completed by the end of 2015. The commissioning began in April 2016, and the first lasing of the hard X-ray FEL line was achieved on 14 June 2016. The progress of the PAL-XFEL construction and its commission are reported here.

Hardware device binding and mutual authentication

Science.gov (United States)

Hamlet, Jason R; Pierson, Lyndon G

2014-03-04

Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

PLASMA ELECTRODE POCKELS CELL SUBSYSTEM PERFORMANCE IN THE NATIONAL IGNITION FACILITY

International Nuclear Information System (INIS)

Barbosa, F; Arnold, P; Hinz, A; Zacharias, R; Ollis, C; Fulkerson, E; Mchale, B; Runtal, A; Bishop, C

2007-01-01

The Plasma Electrode Pockels Cell (PEPC) subsystem is a key component of the National Ignition Facility, enabling the laser to employ an efficient four-pass main amplifier architecture. PEPC relies on a pulsed power technology to initiate and maintain plasma within the cells and to provide the necessary high voltage bias to the cells nonlinear crystals. Ultimately, nearly 300 high-voltage, high-current pulse generators will be deployed in the NIF in support of PEPC. Production of solid-state plasma pulse generators and thyratron-switched pulse generators is now complete, with the majority of the hardware deployed in the facility. An entire cluster (one-fourth of a complete NIF) has been commissioned and is operating on a routine basis, supporting laser shot operations. Another cluster has been deployed, awaiting final commissioning. Activation and commissioning of new hardware continues to progress in parallel, driving toward a goal of completing the PEPC subsystem in late 2007

Secure coupling of hardware components

NARCIS (Netherlands)

Hoepman, J.H.; Joosten, H.J.M.; Knobbe, J.W.

2011-01-01

A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and,

The work of the international commission on radiological protection

International Nuclear Information System (INIS)

Clarke, R.H.

1996-01-01

ICRP was established in 1928 as the International X-ray and Radium Protection Committee. In 1950 the name was changed to reflect the wider scope of radiological protection. The present membership of the Main Commission and its four committees was established in July 1993 for the period 1993-1997. Their programmes of work are now nearing completion with the Committees having met four times and their progress is summarised. The Main Commission meets in November 1996, when one of the main topics will be the election of the new Commission and members of the four Committees for the period 1997-2001

Hardware-in-the-loop simulation of the EAST PF converter for PF control system upgrade

Energy Technology Data Exchange (ETDEWEB)

Chen, Xiaojiao, E-mail: chenxj@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Science (ASIPP), P.O. Box 1126, Hefei, Anhui Province 230031 (China); Chinese University of Science and Technology, Hefei, Anhui Province 230022 (China); Fu, Peng [Institute of Plasma Physics, Chinese Academy of Science (ASIPP), P.O. Box 1126, Hefei, Anhui Province 230031 (China); Chinese University of Science and Technology, Hefei, Anhui Province 230022 (China); Huang, Liansheng, E-mail: huangls@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Science (ASIPP), P.O. Box 1126, Hefei, Anhui Province 230031 (China); Gao, Ge; He, Shiying [Institute of Plasma Physics, Chinese Academy of Science (ASIPP), P.O. Box 1126, Hefei, Anhui Province 230031 (China)

2016-11-15

Highlights: • The hardware in the loop simulation of the EAST PF system is presented. • The control functions and the protection logic have been tested and verified. • The major faults could be avoided and commissioning time could be saved on site. - Abstract: The EAST poloidal field (PF) control system was upgraded in 2015 and the new system has been in use for the 2015 EAST campaign. This paper presents the implementation of a hardware-in-the-loop (HIL) simulation platform of the EAST PF converter system based on the RT-LAB simulation environment, which was used to improve and evaluate the performance of the real controller. The EAST PF power supply system and its operational modes are presented in this paper. The experiments on HIL simulation platform show that the control algorithms and the over current protection of the controller meet the design requirements well. In addition, the effectiveness of the designed control system has been verified by actual application during the EAST campaign at 2015 for six months.

Hardware-in-the-loop simulation of the EAST PF converter for PF control system upgrade

International Nuclear Information System (INIS)

Chen, Xiaojiao; Fu, Peng; Huang, Liansheng; Gao, Ge; He, Shiying

2016-01-01

Highlights: • The hardware in the loop simulation of the EAST PF system is presented. • The control functions and the protection logic have been tested and verified. • The major faults could be avoided and commissioning time could be saved on site. - Abstract: The EAST poloidal field (PF) control system was upgraded in 2015 and the new system has been in use for the 2015 EAST campaign. This paper presents the implementation of a hardware-in-the-loop (HIL) simulation platform of the EAST PF converter system based on the RT-LAB simulation environment, which was used to improve and evaluate the performance of the real controller. The EAST PF power supply system and its operational modes are presented in this paper. The experiments on HIL simulation platform show that the control algorithms and the over current protection of the controller meet the design requirements well. In addition, the effectiveness of the designed control system has been verified by actual application during the EAST campaign at 2015 for six months.

LHC: Construction and Commissioning Status

CERN Document Server

Evans, Lyndon R

2007-01-01

The installation of the Large Hadron Collider at CERN is now approaching completion. All magnets are installed with the exception of a few inner triplet quadrupoles. The first of the eight machine sectors is cold and power tests are proceeding. Two other sectors are ready for cool down and interconnect work is proceeding at a satisfactory pace in the other five sectors. In view of a number of accumulated delays, the original plan for partial commissioning of the machine and a low energy pilot run at the end of 2007 will now have to be abandoned. Instead, the full commissioning of the machine to top energy in a single step will start once the injector chain becomes available in spring 2008.

The CMS Trigger Supervisor: Control and Hardware Monitoring System of the CMS Level-1 Trigger at CERN

CERN Document Server

Ildefons Magrans de Abril

2008-01-01

The experiments CMS (Compact Muon Solenoid) and ATLAS (A Toroidal LHC ApparatuS) at the LargeHadron Collider (LHC) are the greatest exponents of the rising complexity in High Energy Physics (HEP) datahandling instrumentation. Tens of millions of readout channels, tens of thousands of hardware boards and thesame order of connections are figures of merit. However, the hardware volume is not the only complexitydimension, the unprecedented large number of research institutes and scientists that form the internationalcollaborations, and the long design, development, commissioning and operational phases are additional factorsthat must be taken into account.The Level-1 (L1) trigger decision loop is an excellent example of these difficulties. This system is based on apipelined logic destined to analyze without deadtime the data from each LHC bunch crossing occurring every25_ns, using special coarsely segmented trigger data from the detectors. The L1 trigger is responsible forreducing the rate of accepted crossings to...

NSLS-II commissioning and operation

Energy Technology Data Exchange (ETDEWEB)

Wang, G., E-mail: gwang@bnl.gov; Shaftan, T.; Bassi, G.; Bengtsson, J.; Blednykh, A.; Blum, E.; Cheng, W.; Choi, J.; Davidsaver, M.; Doom, L.; Fliller, R.; Ganetis, G.; Guo, W.; Hidaka, Y.; Kramer, S.; Li, Y.; Podobedov, B.; Qian, K.; Rose, J.; Seletskiy, S. [Brookhaven National Laboratory, Upton, NY 11973 (United States); and others

2016-07-27

The National Synchrotron Light Source II at Brookhaven National Lab is a third-generation synchrotron radiation facility that has been commissioned in 2014. The facility is based on a 3 GeV electron storage ring, which will circulate 500 mA of beam current at 1 nm rad horizontal emittance. The storage ring is 792 meters in circumference and will accommodate more than 60 beamlines in the final built-out. The beamline sources range from insertion-devices located in straight sections, bending magnets or three-pole-wigglers configured in multiple branches. The NSLS-II storage ring commissioning was successfully completed in July 2014 and the facility delivered the first user light on October 23, 2014. Currently the storage ring reached 300 mA beam current and achieved 1 nm rad of horizontal emittance with 3 sets of Damping Wigglers. At this point six NSLS-II project beamlines are routinely taking photons with beam current at 150 mA. This paper reviews the NSLS-II accelerator design and commissioning experience.

HiCAT Software Infrastructure: Safe hardware control with object oriented Python

Science.gov (United States)

Moriarty, Christopher; Brooks, Keira; Soummer, Remi

2018-01-01

High contrast imaging for Complex Aperture Telescopes (HiCAT) is a testbed designed to demonstrate coronagraphy and wavefront control for segmented on-axis space telescopes such as envisioned for LUVOIR. To limit the air movements in the testbed room, software interfaces for several different hardware components were developed to completely automate operations. When developing software interfaces for many different pieces of hardware, unhandled errors are commonplace and can prevent the software from properly closing a hardware resource. Some fragile components (e.g. deformable mirrors) can be permanently damaged because of this. We present an object oriented Python-based infrastructure to safely automate hardware control and optical experiments. Specifically, conducting high-contrast imaging experiments while monitoring humidity and power status along with graceful shutdown processes even for unexpected errors. Python contains a construct called a “context manager” that allows you define code to run when a resource is opened or closed. Context managers ensure that a resource is properly closed, even when unhandled errors occur. Harnessing the context manager design, we also use Python’s multiprocessing library to monitor humidity and power status without interrupting the experiment. Upon detecting a safety problem, the master process sends an event to the child process that triggers the context managers to gracefully close any open resources. This infrastructure allows us to queue up several experiments and safely operate the testbed without a human in the loop.

The Impact of Flight Hardware Scavenging on Space Logistics

Science.gov (United States)

Oeftering, Richard C.

2011-01-01

For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

Constructing Hardware in a Scale Embedded Language

Energy Technology Data Exchange (ETDEWEB)

2014-08-21

Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

Hardware Objects for Java

DEFF Research Database (Denmark)

Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan

2008-01-01

Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

Gentilly 2: design, construction and commissioning

International Nuclear Information System (INIS)

Amyot, Paul; Michel, Benoit.

1982-06-01

Construction of the Gentilly 2 power station is essentially complete, and commissioning is proceeding. The main activities during the 1981-82 period have been the completion of the construction and overall testing of the major systems. One cause of delay in the project in 1981 was the discovery of damage to the tubesheet of a steam generator. An internal manhole cover support in the steam generator head had become loose and had caused damage to the tube-to-tubesheet welds. Repairs to the welds were completed in Feb. 1982 after an extensive development program to qualify the welding procedure. Overall project life will be slightly more than 9 years

78 FR 50099 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2013-08-16

... at the address in this notice by September 16, 2013. ADDRESSES: Alicia Woods, Washington State Parks... Alicia[email protected] . SUPPLEMENTARY INFORMATION: Notice is here given in accordance with the Native... request Alicia Woods, Washington State Parks and Recreation Commission, PO Box 42650, Olympia, WA 98504...

78 FR 44593 - Notice of Inventory Completion: Washington State Parks and Recreation Commission, Olympia, WA

Science.gov (United States)

2013-07-24

...: Alicia Woods, Washington State Parks and Recreation Commission, PO Box 42650, Olympia, WA 98504-2650, telephone (360) 902- 0939, email Alicia[email protected] . SUPPLEMENTARY INFORMATION: Notice is here given... written request with information in support of the request to Alicia Woods, Washington State Parks and...

VEG-01: Veggie Hardware Verification Testing

Science.gov (United States)

Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

2013-01-01

The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

TH-AB-201-10: Portal Dosimetry with Elekta IViewDose:Performance of the Simplified Commissioning Approach Versus Full Commissioning

Energy Technology Data Exchange (ETDEWEB)

Kydonieos, M; Folgueras, A; Florescu, L; Cybulski, T; Marinos, N; Thompson, G; Sayeed, A [Elekta Limited, Crawley, West Sussex (United Kingdom); Rozendaal, R; Olaciregui-Ruiz, I [Netherlands Cancer Institute - Antoni van Leeuwenhoek, Amsterdam, Noord-Holland (Netherlands); Subiel, A; Patallo, I Silvestre [National Physical Laboratory, London (United Kingdom)

2016-06-15

Purpose: Elekta recently developed a solution for in-vivo EPID dosimetry (iViewDose, Elekta AB, Stockholm, Sweden) in conjunction with the Netherlands Cancer Institute (NKI). This uses a simplified commissioning approach via Template Commissioning Models (TCMs), consisting of a subset of linac-independent pre-defined parameters. This work compares the performance of iViewDose using a TCM commissioning approach with that corresponding to full commissioning. Additionally, the dose reconstruction based on the simplified commissioning approach is validated via independent dose measurements. Methods: Measurements were performed at the NKI on a VersaHD™ (Elekta AB, Stockholm, Sweden). Treatment plans were generated with Pinnacle 9.8 (Philips Medical Systems, Eindhoven, The Netherlands). A farmer chamber dose measurement and two EPID images were used to create a linac-specific commissioning model based on a TCM. A complete set of commissioning measurements was collected and a full commissioning model was created.The performance of iViewDose based on the two commissioning approaches was compared via a series of set-to-work tests in a slab phantom. In these tests, iViewDose reconstructs and compares EPID to TPS dose for square fields, IMRT and VMAT plans via global gamma analysis and isocentre dose difference. A clinical VMAT plan was delivered to a homogeneous Octavius 4D phantom (PTW, Freiburg, Germany). Dose was measured with the Octavius 1500 array and VeriSoft software was used for 3D dose reconstruction. EPID images were acquired. TCM-based iViewDose and 3D Octavius dose distributions were compared against the TPS. Results: For both the TCM-based and the full commissioning approaches, the pass rate, mean γ and dose difference were >97%, <0.5 and <2.5%, respectively. Equivalent gamma analysis results were obtained for iViewDose (TCM approach) and Octavius for a VMAT plan. Conclusion: iViewDose produces similar results with the simplified and full commissioning

Implementation of Hardware Accelerators on Zynq

DEFF Research Database (Denmark)

Toft, Jakob Kenn

of the ARM Cortex-9 processor featured on the Zynq SoC, with regard to execution time, power dissipation and energy consumption. The implementation of the hardware accelerators were successful. Use of the Monte Carlo processor resulted in a significant increase in performance. The Telco hardware accelerator......In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose...... processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented on a Xilinx Zynq SoC platform mounted on the ZedBoard platform. The two accelerators are based on two different...

Status of the MIT-Bates South Hall Ring commissioning

International Nuclear Information System (INIS)

Flanz, J.B.; Jacobs, K.D.; McAllister, B.; Averill, R.; Bradley, S.; Carter, A.; Dow, K.; Farkondeh, M.; Ihloff, E.; Kowalski, S.

1993-01-01

The MIT-Bates South Hall Ring construction project is now nearly complete. At this time the Energy Compression System, the SHR Injection Line and the South Hall Ring itself are complete. The SHR Extraction Line is complete but has not been connected to the ring. Commissioning with beam of the completed beam lines has been started. The MIT-Bates South Hall Ring (SHR) is an electron storage ring used with the 1 GeV Bates electron accelerator to increase the effective duty factor and luminosity. A beam can be stored for use with an internal target, thus allowing for high duty factor, high luminosity experiments. External beams with high duty factor can be obtained using resonant extraction. The new systems associated with the SHR include the Energy Compression System (ECS), the Injection line, and the Extraction line. The authors have commissioned the ECS, the new injection line and the SHR without RF. This includes transporting beam, measuring beam phase space parameters using critical injection elements including a high voltage electrostatic septum, a fast beam kicker, and storing a beam in the SHR

Computer hardware fault administration

Science.gov (United States)

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

2010-09-14

Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

Combining high productivity with high performance on commodity hardware

DEFF Research Database (Denmark)

Skovhede, Kenneth

-like compiler for translating CIL bytecode on the CELL-BE. I then introduce a bytecode converter that transforms simple loops in Java bytecode to GPGPU capable code. I then introduce the numeric library for the Common Intermediate Language, NumCIL. I can then utilizing the vector programming model from Num......CIL and map this to the Bohrium framework. The result is a complete system that gives the user a choice of high-level languages with no explicit parallelism, yet seamlessly performs efficient execution on a number of hardware setups....

Hardware interface unit for control of shuttle RMS vibrations

Science.gov (United States)

Lindsay, Thomas S.; Hansen, Joseph M.; Manouchehri, Davoud; Forouhar, Kamran

1994-01-01

Vibration of the Shuttle Remote Manipulator System (RMS) increases the time for task completion and reduces task safety for manipulator-assisted operations. If the dynamics of the manipulator and the payload can be physically isolated, performance should improve. Rockwell has developed a self contained hardware unit which interfaces between a manipulator arm and payload. The End Point Control Unit (EPCU) is built and is being tested at Rockwell and at the Langley/Marshall Coupled, Multibody Spacecraft Control Research Facility in NASA's Marshall Space Flight Center in Huntsville, Alabama.

LISA Pathfinder: hardware tests and their input to the mission

Science.gov (United States)

Audley, Heather

The Laser Interferometer Space Antenna (LISA) is a joint ESA-NASA mission for the first space-borne gravitational wave detector. LISA aims to detect sources in the 0.1mHz to 1Hz range, which include supermassive black holes and galactic binary stars. Core technologies required for the LISA mission, including drag-free test mass control, picometre interferometry and micro-Newton thrusters, cannot be tested on-ground. Therefore, a precursor satellite, LISA Pathfinder, has been developed as a technology demonstration mission. The preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on system level. The results and test procedures of these campaigns will be utilised directly in the ground-based flight hardware tests, and subsequently within in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MatLab based LTP data analysis toolbox. This contribution presents an overview of the test campaigns calibration, control and perfor-mance results, focusing on the implications for the Experimental Master Plan which provides the basis for the in-flight operations and procedures.

17 CFR 300.302 - Mechanics of closeout or completion.

Science.gov (United States)

2010-04-01

... 17 Commodity and Securities Exchanges 3 2010-04-01 2010-04-01 false Mechanics of closeout or completion. 300.302 Section 300.302 Commodity and Securities Exchanges SECURITIES AND EXCHANGE COMMISSION... Completion of Open Contractual Commitments § 300.302 Mechanics of closeout or completion. (a) The closeout or...

Non-fuel bearing hardware melting technology

International Nuclear Information System (INIS)

Newman, D.F.

1993-01-01

Battelle has developed a portable hardware melter concept that would allow spent fuel rod consolidation operations at commercial nuclear power plants to provide significantly more storage space for other spent fuel assemblies in existing pool racks at lower cost. Using low pressure compaction, the non-fuel bearing hardware (NFBH) left over from the removal of spent fuel rods from the stainless steel end fittings and the Zircaloy guide tubes and grid spacers still occupies 1/3 to 2/5 of the volume of the consolidated fuel rod assemblies. Melting the non-fuel bearing hardware reduces its volume by a factor 4 from that achievable with low-pressure compaction. This paper describes: (1) the configuration and design features of Battelle's hardware melter system that permit its portability, (2) the system's throughput capacity, (3) the bases for capital and operating estimates, and (4) the status of NFBH melter demonstration to reduce technical risks for implementation of the concept. Since all NFBH handling and processing operations would be conducted at the reactor site, costs for shipping radioactive hardware to and from a stationary processing facility for volume reduction are avoided. Initial licensing, testing, and installation in the field would follow the successful pattern achieved with rod consolidation technology

Commissioning and Operational Experience in Power Reactor Fuel Reprocessing Plant

Energy Technology Data Exchange (ETDEWEB)

Pradhan, S., E-mail: spradhan@barctara.gov.in [Tarapur Based Reprocessing Plant, Bhabha Atomic Research Centre, Tarapur (India)

2014-10-15

After completing design, construction, commissioning, operation and maintenance experience of the reprocessing plants at Tarapur, Mumbai and Kalpakkam a new reprocessing plant is commissioned and put into operation at BARC, Tarapur since 2011. Subsequent to construction clearance, commissioning of the plant is taken in many steps with simultaneous review by design and safety committees. In spite of vast experience, all the staff was retrained in various aspects of process and utility operations and in operation of innovative changes incorporated in the design. Operating personnel are licensed through an elaborate procedure consisting of various check lists followed by personnel interview. Commissioning systems were divided in sub-systems. Sub-systems were commissioned independently and later integrated testing was carried out. For commissioning, extreme operating conditions were identified in consultation with designers and detailed commissioning procedures were made accordingly. Commissioning was done in different conditions to ensure safety, smooth operation and maintainability. Few modifications were carried out based on commissioning experience. Technical specifications for operation of the plant are made in consultation with designers and reviewed by safety committees. Operation of the plant was carried out after successful commissioning trials with Deep Depleted Uranium (DDU). Emergency operating procedures for each design basis accident were made. Performance of various systems, subsystems are quite satisfactory and the plant has given very good capacity factor. (author)

A Practical Introduction to HardwareSoftware Codesign

CERN Document Server

Schaumont, Patrick R

2013-01-01

This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

Comparative Modal Analysis of Sieve Hardware Designs

Science.gov (United States)

Thompson, Nathaniel

2012-01-01

The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

Science.gov (United States)

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

Cleanup Verification Package for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault

International Nuclear Information System (INIS)

Appel, M.J.

2006-01-01

This cleanup verification package documents completion of remedial action for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault. The site consisted of an inactive solid waste storage vault used for temporary storage of slightly contaminated reactor parts that could be recovered and reused for the 100-F Area reactor operations

Cleanup Verification Package for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault

Energy Technology Data Exchange (ETDEWEB)

M. J. Appel

2006-11-02

This cleanup verification package documents completion of remedial action for the 118-F-7, 100-F Miscellaneous Hardware Storage Vault. The site consisted of an inactive solid waste storage vault used for temporary storage of slightly contaminated reactor parts that could be recovered and reused for the 100-F Area reactor operations.

Remote hardware-reconfigurable robotic camera

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

Identification of single-shell tank in-tank hardware obstructions to retrieval at Hanford Site Tank Farms

International Nuclear Information System (INIS)

Ballou, R.A.

1994-10-01

Two retrieval technologies, one of which uses robot-deployed end effectors, will be demonstrated on the first single-shell tank (SST) waste to be retrieved at the Hanford Site. A significant impediment to the success of this technology in completing the Hanford retrieval mission is the presence of unique tank contents called in-tank hardware (ITH). In-tank hardware includes installed and discarded equipment and various other materials introduced into the tank. This paper identifies those items of ITH that will most influence retrieval operations in the arm-based demonstration project and in follow-on tank operations within the SST farms

Appalachian Regional Commission: 1982 Annual Report.

Science.gov (United States)

Appalachian Regional Commission, Washington, DC.

Fiscal year 1982 was transitional for the Appalachian Regional Commission (ARC), as it was the last year of the broad economic development program and a year of reduced funding and new limits on programs. In 1981, Congress had requested that ARC prepare a plan for completion of the Appalachian highway system and for a 3 to 5 year ARC finish-up…

Spaceflight hardware for conducting plant growth experiments in space: the early years 1960-2000

Science.gov (United States)

Porterfield, D. M.; Neichitailo, G. S.; Mashinski, A. L.; Musgrave, M. E.

2003-01-01

The best strategy for supporting long-duration space missions is believed to be bioregenerative life support systems (BLSS). An integral part of a BLSS is a chamber supporting the growth of higher plants that would provide food, water, and atmosphere regeneration for the human crew. Such a chamber will have to be a complete plant growth system, capable of providing lighting, water, and nutrients to plants in microgravity. Other capabilities include temperature, humidity, and atmospheric gas composition controls. Many spaceflight experiments to date have utilized incomplete growth systems (typically having a hydration system but lacking lighting) to study tropic and metabolic changes in germinating seedlings and young plants. American, European, and Russian scientists have also developed a number of small complete plant growth systems for use in spaceflight research. Currently we are entering a new era of experimentation and hardware development as a result of long-term spaceflight opportunities available on the International Space Station. This is already impacting development of plant growth hardware. To take full advantage of these new opportunities and construct innovative systems, we must understand the results of past spaceflight experiments and the basic capabilities of the diverse plant growth systems that were used to conduct these experiments. The objective of this paper is to describe the most influential pieces of plant growth hardware that have been used for the purpose of conducting scientific experiments during the first 40 years of research. c2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

Commissioning and First Operation of the Low-Beta Triplets and Their Electrical Feed Boxes at the Large Hadron Collider

CERN Document Server

Darve, C; Casas-Cubillos, J; Claudet, S; Feher, S; Ferlin, G; Kerby, J; Metral, L; Perin, A; Peterson, T; Prin, H; Rabehl, R; Vauthier, N; Wagner, U; van Weelderen, R

2010-01-01

The insertion regions located around the four interaction points of the Large Hadron Collider (LHC) are mainly composed of the low-b triplets, the separation dipoles and their respective electrical feed-boxes (DFBX). The low-b triplets are Nb-Ti superconductor quadrupole magnets, which operate at 215 T/m in superfluid helium at a temperature of 1.9 K. The commissioning and the first operation of these components have been performed. The thermo-mechanical behavior of the low-b triplets and DFBX were studied. Cooling and control systems were tuned to optimize the cryogenic operation of the insertion regions. Hardware commissioning also permitted to test the system response. This paper summarizes the performance results and the lessons learned.

Transmission delays in hardware clock synchronization

Science.gov (United States)

Shin, Kang G.; Ramanathan, P.

1988-01-01

Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in a system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been studied extensively in the communication area in the absence of malicious or Byzantine faults. The authors show that it is easy to incorporate the ideas from the communication area into the existing hardware clock synchronization algorithms to take into account the presence of both malicious faults and nonzero transmission delays.

Computer hardware description languages - A tutorial

Science.gov (United States)

Shiva, S. G.

1979-01-01

The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

Support for NUMA hardware in HelenOS

OpenAIRE

Horký, Vojtěch

2011-01-01

The goal of this master thesis is to extend HelenOS operating system with the support for ccNUMA hardware. The text of the thesis contains a brief introduction to ccNUMA hardware, an overview of NUMA features and relevant features of HelenOS (memory management, scheduling, etc.). The thesis analyses various design decisions of the implementation of NUMA support -- introducing the hardware topology into the kernel data structures, propagating this information to user space, thread affinity to ...

Sterilization of space hardware.

Science.gov (United States)

Pflug, I. J.

1971-01-01

Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

Software for Managing Inventory of Flight Hardware

Science.gov (United States)

Salisbury, John; Savage, Scott; Thomas, Shirman

2003-01-01

The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

Co-operation Agreement relating to LHC Commissioning

CERN Multimedia

2005-01-01

CERN Director-General Robert Aymar and Ryszard Tadeusiewicz, the Rector of the AGH University of Science and Technology in Cracow, after signing the agreement. On 29 July, the Rector of the AGH University of Science and Technology in Cracow, Ryszard Tadeusiewicz, and CERN Director-General Robert Aymar signed a collaboration agreement relating to the commissioning of the instrumentation and monitoring equipment for the LHC cryogenic system. Under the agreement, a team consisting of a dozen physicists, engineers and technicians from the AGH University in Cracow will lend a helping hand to the teams at CERN for the commissioning of the cryogenic system in the tunnel. This is the first in what will be a series of agreements relating to the commissioning of the LHC's various systems. From the end of this year until the summer of 2007, CERN will require reinforcements of physicists, engineers and technicians in order to complete the many tasks associated with the start-up of the accelerator. CERN is therefore pre...

Targeting multiple heterogeneous hardware platforms with OpenCL

Science.gov (United States)

Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

2014-06-01

The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

Improvement of nuclear ship engineering simulation system. Hardware renewal and interface improvement of the integral type reactor

Energy Technology Data Exchange (ETDEWEB)

Takahashi, Hiroki; Kyoya, Masahiko; Shimazaki, Junya [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment; Kano, Tadashi [KCS, Co., Mito, Ibaraki (Japan); Takahashi, Teruo [Energis, Co., Kobe, Hyogo (Japan)

2001-10-01

JAERI had carried out the design study about a lightweight and compact integral type reactor (an advanced marine reactor) with passive safety equipment as a power source for the future nuclear ships, and completed an engineering design. We have developed the simulator for the integral type reactor to confirm the design and operation performance and to utilize the study of automation of the reactor operation. The simulator can be used also for future research and development of a compact reactor. However, the improvement in a performance of hardware and a human machine interface of software of the simulator were needed for future research and development. Therefore, renewal of hardware and improvement of software have been conducted. The operability of the integral-reactor simulator has been improved. Furthermore, this improvement with the hardware and software on the market brought about better versatility, maintainability, extendibility and transfer of the system. This report mainly focuses on contents of the enhancement in a human machine interface, and describes hardware renewal and the interface improvement of the integral type reactor simulator. (author)

78 FR 76218 - Rural Call Completion

Science.gov (United States)

2013-12-17

... calls to rural areas, and enforce restrictions against blocking, choking, reducing, or restricting calls... to alert the Commission of systemic problems receiving calls from a particular originating long... associated with completing calls to rural areas. These rules will also enhance our ability to enforce...

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

Science.gov (United States)

Abutaleb, M. M.

2018-04-01

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

An Open Hardware seismic data recorder - a solid basis for citizen science

Science.gov (United States)

Mertl, Stefan

2015-04-01

"Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

Improvement of hardware basic testing : Identification and development of a scripted automation tool that will support hardware basic testing

OpenAIRE

Rask, Ulf; Mannestig, Pontus

2002-01-01

In the ever-increasing development pace, circuits and hardware are no exception. Hardware designs grow and circuits gets more complex at the same time as the market pressure lowers the expected time-to-market. In this rush, verification methods often lag behind. Hardware manufacturers must be aware of the importance of total verification if they want to avoid quality flaws and broken deadlines which in the long run will lead to delayed time-to-market, bad publicity and a decreasing market sha...

Statement from the 1987 Como meeting of the international commission on radiological protection

International Nuclear Information System (INIS)

Anon.

1988-01-01

The Commission is presently revising its basic recommendations which were presented in ICRP Publication 26 in 1977 and in a number of subsequent statements and amendments as well as in other ICRP reports. The revised recommendations are expected to be completed by 1990 after preparatory work by the Commission's four expert committees and a number of ad hoc task groups. This work included a review and re-assessment of the complete system of dose limitation, including the values of the dose limits. In this article certain dose limit problems are discussed

Hardware design of a submerged buoy system based on electromagnetic inductive coupling

Directory of Open Access Journals (Sweden)

Song Dalei

2016-01-01

Full Text Available This paper mainly introduces the hardware design of a new type of ocean buoy for multi-scale marine dynamic process. The buoy system can collect a number of real-time marine environment data and then transmit all the data back to the landing site through wireless module. The authors mainly designed the hardware circuit of the buoy system, including data collection system, data communication system, data storage system. Due to the buoy system will complete the marine observation work continuously for at least a month, so we add the low power consumption function which can realize the intermittent work for the data collection system. This paper also introduces the electromagnetic induction coupling technology of underwater sensors, the sea surface communication network technology, etc. The system can also extends to the ecological regional anomaly monitoring and the early warning of disaster weather.

Technical management on commissioning test of nuclear heating reactor

International Nuclear Information System (INIS)

Zhang Yajun; Su Qingshan

1999-01-01

The commissioning is the last construction stage of a nuclear heating project. The commissioning quality will directly affect on the safe operation and availability of the heating reactor. The author presents the whole test process until the completion of the test report from the point of test documents, including the preparation and execution of the test, the management of the various unexpected events during the test. And it will be emphatically discussed that the managing procedures of the various unexpected events during the test, including temporary control change, setpoint change, unexpected events and design change

State Energy Commission of Western Australia. 1985 annual report

Energy Technology Data Exchange (ETDEWEB)

1985-01-01

The report reviews the operations and achievements of the Commission during 1984/85, and also outlines plans aimed at providing reliable and cost-effective energy supplies in Western Australia in the future. The Commission completed the 1984/85 financial year with an operating surplus of 4.3 m dollars. This compared with a surplus of 4.4 m dollars for the previous year. A full set of financial statements, certified by the Auditor General of Western Australia as being properly drawn up and fairly presented, appears in the back of the report.

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

Directory of Open Access Journals (Sweden)

Ikbel Belaid

2011-01-01

Full Text Available Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

COMPUTER HARDWARE MARKING

CERN Multimedia

Groupe de protection des biens

2000-01-01

As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

GOSH! A roadmap for open-source science hardware

CERN Multimedia

Stefania Pandolfi

2016-01-01

The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

Hardware Accelerated Simulated Radiography

International Nuclear Information System (INIS)

Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

2005-01-01

We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists

Hardware for dynamic quantum computing experiments: Part I

Science.gov (United States)

Johnson, Blake; Ryan, Colm; Riste, Diego; Donovan, Brian; Ohki, Thomas

Static, pre-defined control sequences routinely achieve high-fidelity operation on superconducting quantum processors. Efforts toward dynamic experiments depending on real-time information have mostly proceeded through hardware duplication and triggers, requiring a combinatorial explosion in the number of channels. We provide a hardware efficient solution to dynamic control with a complete platform of specialized FPGA-based control and readout electronics; these components enable arbitrary control flow, low-latency feedback and/or feedforward, and scale far beyond single-qubit control and measurement. We will introduce the BBN Arbitrary Pulse Sequencer 2 (APS2) control system and the X6 QDSP readout platform. The BBN APS2 features: a sequencer built around implementing short quantum gates, a sequence cache to allow long sequences with branching structures, subroutines for code re-use, and a trigger distribution module to capture and distribute steering information. The X6 QDSP features a single-stage DSP pipeline that combines demodulation with arbitrary integration kernels, and multiple taps to inspect data flow for debugging and calibration. We will show system performance when putting it all together, including a latency budget for feedforward operations. This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), through the Army Research Office Contract No. W911NF-10-1-0324.

Nuclear Regulatory Commission Information Digest: 1993 edition

International Nuclear Information System (INIS)

1993-03-01

The Nuclear Regulatory Commission Information Digest (digest) provides a summary of information about the U.S. Nuclear Regulatory Commission (NRC), NRC's regulatory responsibilities, the activities NRC licenses, and general information on domestic and worldwide nuclear energy. The digest, published annually, is a compilation of nuclear- and NRC-related data and is designed to provide a quick reference to major facts about the agency and the industry it regulates. In general, the data cover 1975 through 1992, with exceptions noted. Information on generating capacity and average capacity factor for operating U.S. commercial nuclear power reactors is obtained from monthly operating reports that are submitted directly to the NRC by the licensee. This information is reviewed by the NRC for consistency only and no independent validation and/or verification is performed. Comments and/or suggestions on the data presented are welcomed and should be directed to Karen Olive, United States Nuclear Regulatory Commission, Office of the Controller, Division of Budget and Analysis, Washington, D.C. 20555. For detailed and complete information about tables and figures, refer to the source publications

Reliable software for unreliable hardware a cross layer perspective

CERN Document Server

Rehman, Semeen; Henkel, Jörg

2016-01-01

This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

Hardware device to physical structure binding and authentication

Science.gov (United States)

Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

2013-08-20

Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

Raspberry Pi hardware projects 1

CERN Document Server

Robinson, Andrew

2013-01-01

Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

A Hardware Abstraction Layer in Java

DEFF Research Database (Denmark)

Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

2011-01-01

Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

Designing Secure Systems on Reconfigurable Hardware

OpenAIRE

Huffmire, Ted; Brotherton, Brett; Callegari, Nick; Valamehr, Jonathan; White, Jeff; Kastner, Ryan; Sherwood, Ted

2008-01-01

The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers often have no choice but to use soft IP cores obtained from third parties, the cores operate at different trust levels, resulting in mixed trust designs. The goal of this project is to evaluate recently proposed security primitives for reconfigurab...

Hardware-Accelerated Simulated Radiography

International Nuclear Information System (INIS)

Laney, D; Callahan, S; Max, N; Silva, C; Langer, S.; Frank, R

2005-01-01

We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester

Speed test results and hardware/software study of computational speed problem, appendix D

Science.gov (United States)

1984-01-01

The HP9845C is a desktop computer which is tested and evaluated for processing speed. A study was made to determine the availability and approximate cost of computers and/or hardware accessories necessary to meet the 20 ms sample period speed requirements. Additional requirements were that the control algorithm could be programmed in a high language and that the machine have sufficient storage to store the data from a complete experiment.

Hardware descriptions of the I and C systems for NPP

International Nuclear Information System (INIS)

Lee, Cheol Kwon; Oh, In Suk; Park, Joo Hyun; Kim, Dong Hoon; Han, Jae Bok; Shin, Jae Whal; Kim, Young Bak

2003-09-01

The hardware specifications for I and C Systems of SNPP(Standard Nuclear Power Plant) are reviewed in order to acquire the hardware requirement and specification of KNICS (Korea Nuclear Instrumentation and Control System). In the study, we investigated hardware requirements, hardware configuration, hardware specifications, man-machine hardware requirements, interface requirements with the other system, and data communication requirements that are applicable to SNP. We reviewed those things of control systems, protection systems, monitoring systems, information systems, and process instrumentation systems. Through the study, we described the requirements and specifications of digital systems focusing on a microprocessor and a communication interface, and repeated it for analog systems focusing on the manufacturing companies. It is expected that the experience acquired from this research will provide vital input for the development of the KNICS

Scintillator tiles with SiPM readout for calorimetry and fast timing in SuperKEKB commissioning

Energy Technology Data Exchange (ETDEWEB)

Windel, Hendrik [Max-Planck-Institute for Physics (Germany); Collaboration: CALICE-D-Collaboration

2016-07-01

The CALICE collaboration is studying plastic scintillators coupled to silicon photomultipliers as sensors for calorimeters for future linear colliders like ILC and CLIC. Current detector concepts foresee up to ten million channels for the hadronic calorimeter. A larger number of different types of SiPMs and scintillator materials exist and their properties have to be investigated to provide best results. For these purposes a dedicated laboratory setup has been developed to provide high resolution scanning of the scintillator tiles with a radioactive source. The data acquisition of this setup as well as a fast online analysis has been implemented in LABVIEW. A modified version of this setup, together with hardware previously used for measuring timing properties of hardronic showers, will be used in the commissioning phase of the SuperKEKB accelerator. This contribution discusses results from detailed investigations of different scintillator tiles, including the study of different materials. Key performance criteria for their application in calorimetry and in background measurements with high time resolution at SuperKEKB are also presented. The CALICE collaboration is studying plastic scintillators coupled to silicon photomultipliers as sensors for calorimeters for future linear colliders like ILC and CLIC. Current detector concepts foresee up two ten million channels for the hadronic calorimeter. In the real detector several thousands of these plastic scintillators will be used. To provide comparability between each of them, investigations of homogeneity for different packaging types and scintillating materials are needed as well as different attempts in tile arrangement to take inter tile crosstalk into account. A larger number of different types of SiPMs and scintillator materials exist and their properties have to be investigated to provide best results. For these purposes a dedicated LABVIEW based setup consistent of data acquisition system (DAQ) and analysis

Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

Directory of Open Access Journals (Sweden)

Huang Chun-Hsian

2008-01-01

Full Text Available Abstract We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.

Test system design for Hardware-in-Loop evaluation of PEM fuel cells and auxiliaries

Energy Technology Data Exchange (ETDEWEB)

Randolf, Guenter; Moore, Robert M. [Hawaii Natural Energy Institute, University of Hawaii, Honolulu, HI (United States)

2006-07-14

In order to evaluate the dynamic behavior of proton exchange membrane (PEM) fuel cells and their auxiliaries, the dynamic capability of the test system must exceed the dynamics of the fastest component within the fuel cell or auxiliary component under test. This criterion is even more critical when a simulated component of the fuel cell system (e.g., the fuel cell stack) is replaced by hardware and Hardware-in-Loop (HiL) methodology is employed. This paper describes the design of a very fast dynamic test system for fuel cell transient research and HiL evaluation. The integration of the real time target (which runs the simulation), the test stand PC (that controls the operation of the test stand), and the programmable logic controller (PLC), for safety and low-level control tasks, into one single integrated unit is successfully completed. (author)

1990 Recommendations of the International Commission on Radiological Protection adopted by the Commission in November 1990

International Nuclear Information System (INIS)

1991-01-01

This publication represents a completely new set of basic recommendations, outdating ICRP Publication 26. They aim to: a) take account of new biological information and of trends in setting safety standards; b) improve the presentation of the recommendations: c) maintain as much stability in the recommendations as is consistent with the new information. The recommendations cover quantities, biological aspects, the conceptual framework of radiological protection, proposed and continuing practices (occupational, medical and public exposure) and implementation of the Commission's Recommendations. (UK)

SSCL Commissioning and Operations

International Nuclear Information System (INIS)

1992-01-01

The SSC, with an energy of 20 TeV/Beam, requires a sequence of individual accelerators of increasing energy in the injector chain. These are the Linac, Low Energy Booster, Medium Energy Booster, and High Energy Booster. Each accelerator system must be completed in sequence in order to provide beam to the next higher energy accelerator. The collider itself is comprised of ten sectors, each of which in terms of superconducting magnet bending strength, is equivalent to two HEB injectors. The completion of all injectors and collider sectors is required before stored beams can circulate in preparation for colliding beam operation. Four experimental halls are planned for the detector systems. Each major detector will be assembled in one of the halls by a world-wide collaboration of scientists. In addition, above ground facilities provide shops and test facilities for accelerator technical systems, superconducting magnet and materials research and development, and for detector assembly and operations. The purpose of this report is to present a plan for the sequential commissioning and operation of these individual accelerators and other technical facilities of the SSC. A central objective of this plan is to describe the activities at the SSCL that are not included as part of the construction project TPC, even though they occur during the overall project construction time-frame. Examples of such activities include the operation of general laboratory facilities and services not specifically related to construction, the operating costs for the individual accelerators in the injector chain once these facilities have been commissioned, and the costs of SSCL physics research groups. The Department of Energy has provided the following decision with regard to these operations categories for the SSCL

Application of the ATLAS DAQ and Monitoring System for MDT and RPC Commissioning

CERN Document Server

Pasqualucci, E

2007-01-01

The ATLAS DAQ and monitoring software are currently commonly used to test detectors during the commissioning phase. In this paper, their usage in MDT and RPC commissioning is described, both at the surface pre-commissioning and commissioning stations and in the ATLAS pit. Two main components are heavily used for detector tests. The ROD Crate DAQ software is based on the ATLAS Readout application. Based on the plug-in mechanism, it provides a complete environment to interface any kind of detector or trigger electronics to the ATLAS DAQ system. All the possible flavours of this application are used to test and run the MDT and RPC detectors at the pre-commissioning and commissioning sites. Ad-hoc plug-ins have been developed to implement data readout via VME, both with ROD prototypes and emulating final electronics to read out data with temporary solutions, and to provide trigger distribution and busy management in a multi-crate environment. Data driven event building functionality is also used to combine data f...

Generation of Embedded Hardware/Software from SystemC

Directory of Open Access Journals (Sweden)

Dominique Houzet

2006-08-01

Full Text Available Designers increasingly rely on reusing intellectual property (IP and on raising the level of abstraction to respect system-on-chip (SoC market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propose a design flow intended to reduce the SoC design cost. This design flow unifies hardware and software using a single high-level language. It integrates hardware/software (HW/SW generation tools and an automatic interface synthesis through a custom library of adapters. We have validated our interface synthesis approach on a hardware producer/consumer case study and on the design of a given software radiocommunication application.

Generation of Embedded Hardware/Software from SystemC

Directory of Open Access Journals (Sweden)

Ouadjaout Salim

2006-01-01

Full Text Available Designers increasingly rely on reusing intellectual property (IP and on raising the level of abstraction to respect system-on-chip (SoC market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propose a design flow intended to reduce the SoC design cost. This design flow unifies hardware and software using a single high-level language. It integrates hardware/software (HW/SW generation tools and an automatic interface synthesis through a custom library of adapters. We have validated our interface synthesis approach on a hardware producer/consumer case study and on the design of a given software radiocommunication application.

Cooperative communications hardware, channel and PHY

CERN Document Server

Dohler, Mischa

2010-01-01

Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

IDD Archival Hardware Architecture and Workflow

Energy Technology Data Exchange (ETDEWEB)

Mendonsa, D; Nekoogar, F; Martz, H

2008-10-09

This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

Aspects of system modelling in Hardware/Software partitioning

DEFF Research Database (Denmark)

Knudsen, Peter Voigt; Madsen, Jan

1996-01-01

This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...... the importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

Hardware Acceleration of Adaptive Neural Algorithms.

Energy Technology Data Exchange (ETDEWEB)

James, Conrad D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2017-11-01

As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

Installation and commissioning of Scandiflash-450 flash X-ray generator at BARC, Visakhapatnam

International Nuclear Information System (INIS)

Banerjee, P.; Verma, R.; Shukla, R.; Sharma, S.K.; Das, B.; Prabaharan, T.; Deb, P.; Das, R.; Adhikary, B.; Meena, M.; Sagar, K.; Shyam, A.

2014-08-01

Energetics and Electromagnetics Division, BARC, Visakhapatnam has possessed a Flash X-ray radiography (FXR) system, make: Scandiflash, Sweden. This installation and commissioning of the system has been done by ourselves. Few problems have been detected during installation and commissioning. The troubleshooting of the system has been done. Somewhere we needed to replace the original components by indigenously made one. The complete installation and commissioning has been reportedly as far as detailed possible. Presently the system is working with satisfaction. The installed facility is being used as one of the primary means of diagnostics in many of the ongoing experiments. (author)

Hardware/software virtualization for the reconfigurable multicore platform.

NARCIS (Netherlands)

Ferger, M.; Al Kadi, M.; Hübner, M.; Koedam, M.L.P.J.; Sinha, S.S.; Goossens, K.G.W.; Marchesan Almeida, Gabriel; Rodrigo Azambuja, J.; Becker, Juergen

2012-01-01

This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a

PERANCANGAN APLIKASI SISTEM PAKAR DIAGNOSA KERUSAKAN HARDWARE KOMPUTER METODE FORWARD CHAINING

Directory of Open Access Journals (Sweden)

Ali Akbar Rismayadi

2016-09-01

Full Text Available Abstract Damage to computer hardware, not a big disaster, because not all damage to computer hardware can not be repaired, nearly all computer users, whether public or institutions often suffer various kinds of damage that occurred in the computer hardware it has, and the damage can be caused by various factors that are basically as the user does not know the cause of what makes the computer hardware used damaged. Therefore, it is necessary to build an application that can help users to mendiganosa damage to computer hardware. So that everyone can diagnose the type of hardware damage his computer. Development of expert system diagnosis of damage to computer hardware uses forward chaining method by promoting alisisis descriptive of various damage data obtained from several experts and other sources of literature to reach a conclusion on the diagnosis of damage. As well as using the waterfall model as a model system development, starting from the analysis stage to stage software needs support. This application is built using a programming language tools Eclipse ADT as well as SQLite as its database. diagnosis expert system damage computer hardware is expected to be used as a tool to help find the causes of damage to computer hardware independently without the help of a computer technician.

Increased risk for complications following removal of hardware in patients with liver disease, pilon or pelvic fractures: A regression analysis.

Science.gov (United States)

Brown, Bryan D; Steinert, Justin N; Stelzer, John W; Yoon, Richard S; Langford, Joshua R; Koval, Kenneth J

2017-12-01

Indications for removing orthopedic hardware on an elective basis varies widely. Although viewed as a relatively benign procedure, there is a lack of data regarding overall complication rates after fracture fixation. The purpose of this study is to determine the overall short-term complication rate for elective removal of orthopedic hardware after fracture fixation and to identify associated risk factors. Adult patients indicated for elective hardware removal after fracture fixation between July 2012 and July 2016 were screened for inclusion. Inclusion criteria included patients with hardware related pain and/or impaired cosmesis with complete medical and radiographic records and at least 3-month follow-up. Exclusion criteria were those patients indicated for hardware removal for a diagnosis of malunion, non-union, and/or infection. Data collected included patient age, gender, anatomic location of hardware removed, body mass index, ASA score, and comorbidities. Overall complications, as well as complications requiring revision surgery were recorded. Statistical analysis was performed with SPSS 20.0, and included univariate and multivariate regression analysis. 391 patients (418 procedures) were included for analysis. Overall complication rates were 8.4%, with a 3.6% revision surgery rate. Univariate regression analysis revealed that patients who had liver disease were at significant risk for complication (p=0.001) and revision surgery (p=0.036). Multivariate regression analysis showed that: 1) patients who had liver disease were at significant risk of overall complication (p=0.001) and revision surgery (p=0.039); 2) Removal of hardware following fixation for a pilon had significantly increased risk for complication (p=0.012), but not revision surgery (p=0.43); and 3) Removal of hardware for pelvic fixation had a significantly increased risk for revision surgery (p=0.017). Removal of hardware following fracture fixation is not a risk-free procedure. Patients with

Distally based saphenous neurocutaneous perforator flap combined with vac therapy for soft tissue reconstruction and hardware salvage in the lower extremities.

Science.gov (United States)

Wen, Gen; Wang, Chun-Yang; Chai, Yi-Min; Cheng, Liang; Chen, Ming; Yi-Min, L V

2013-11-01

The complex wound with the exposed hardware and infection is one of the common complications after the internal fixation of the tibia fracture. The salvage of hardware and reconstruction of soft tissue defect remain challenging. In this report, we presented our experience on the use of the distally based saphenous neurocutaneous perforator flap combined with vacuum-assisted closure (VAC) therapy for the coverage of the soft tissue defect and the exposed hardware in the lower extremity with fracture. Between January 2008 and July 2010, seven patients underwent the VAC therapy followed by transferring a reversed saphenous neurocutaneous perforator flap for reconstruction of the wound with exposed hardware around the distal tibia. The sizes of the flaps ranged from 6 × 3 cm to 15 × 6 cm. Six flaps survived completely. Partial necrosis occurred in one patient. There were no other complications of repair and donor sites. Bone healing was achieved in all patients. In conclusion, the reversed saphenous neurocutaneous perfortor flaps combined with the VAC therapy might be one of the options to cover the complex wound with exposed hardware in the lower extremities. © 2013 Wiley Periodicals, Inc.

Flight Hardware Virtualization for On-Board Science Data Processing

Data.gov (United States)

National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

Speed challenge: a case for hardware implementation in soft-computing

Science.gov (United States)

Daud, T.; Stoica, A.; Duong, T.; Keymeulen, D.; Zebulum, R.; Thomas, T.; Thakoor, A.

2000-01-01

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

The initial criticality and nuclear commissioning test program at HANARO

Energy Technology Data Exchange (ETDEWEB)

Lee, Choong-Sung; Seo, Chul-Gyo; Jun, Byung-Jin [Korea Atomic Energy Research Institute, Dukjin-Dong 150, Yusung-Ku, Taejon, 305-353 (Korea, Republic of)

1995-07-01

The construction of the Korea Multipurpose Research Reactor - HANARO of 3MW, developed by Korea Atomic Energy Research Institute, was completed at the beginning of this year. The first fuel loading began on February 2 1995, and initial criticality was achieved on February 8, when the core had four 18-element assemblies and thirteen 36-element assemblies. The critical control rod position was 600.8 mm which represents excess reactivity of 0.71 $. Currently the nuclear commissioning test is on going under the zero power range. This paper describes the initial criticality approach of the HANARO, and its nuclear commissioning test program. (author)

Complete Neuron-Astrocyte Interaction Model: Digital Multiplierless Design and Networking Mechanism.

Science.gov (United States)

Haghiri, Saeed; Ahmadi, Arash; Saif, Mehrdad

2017-02-01

Glial cells, also known as neuroglia or glia, are non-neuronal cells providing support and protection for neurons in the central nervous system (CNS). They also act as supportive cells in the brain. Among a variety of glial cells, the star-shaped glial cells, i.e., astrocytes, are the largest cell population in the brain. The important role of astrocyte such as neuronal synchronization, synaptic information regulation, feedback to neural activity and extracellular regulation make the astrocytes play a vital role in brain disease. This paper presents a modified complete neuron-astrocyte interaction model that is more suitable for efficient and large scale biological neural network realization on digital platforms. Simulation results show that the modified complete interaction model can reproduce biological-like behavior of the original neuron-astrocyte mechanism. The modified interaction model is investigated in terms of digital realization feasibility and cost targeting a low cost hardware implementation. Networking behavior of this interaction is investigated and compared between two cases: i) the neuron spiking mechanism without astrocyte effects, and ii) the effect of astrocyte in regulating the neurons behavior and synaptic transmission via controlling the LTP and LTD processes. Hardware implementation on FPGA shows that the modified model mimics the main mechanism of neuron-astrocyte communication with higher performance and considerably lower hardware overhead cost compared with the original interaction model.

Hardware malware

CERN Document Server

Krieg, Christian

2013-01-01

In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

15 MW HArdware-in-the-loop Grid Simulation Project

Energy Technology Data Exchange (ETDEWEB)

Rigas, Nikolaos [Clemson Univ., SC (United States); Fox, John Curtiss [Clemson Univ., SC (United States); Collins, Randy [Clemson Univ., SC (United States); Tuten, James [Clemson Univ., SC (United States); Salem, Thomas [Clemson Univ., SC (United States); McKinney, Mark [Clemson Univ., SC (United States); Hadidi, Ramtin [Clemson Univ., SC (United States); Gislason, Benjamin [Clemson Univ., SC (United States); Boessneck, Eric [Clemson Univ., SC (United States); Leonard, Jesse [Clemson Univ., SC (United States)

2014-10-31

The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA

Commission on Legal Matters

CERN Multimedia

Staff Association

2016-01-01

What is a commission within the Staff Association (SA)? A commission is a working group of the CERN Staff Council, led by a staff representative. The commission is composed mainly of staff representatives, but interested members of the SA can apply to participate in the work of a commission. What is the commission on legal matters? The commission on legal matters works on texts governing the employment conditions of staff (Employed Members of Personnel and Associated Members of Personnel). This covers legal documents such as the Staff Rules and Regulations, administrative and operational circulars, as well as any other document relating to employment conditions. How is the work organised in this commission? The revision process of the text is generally done along following lines: The HR department, and its legal experts, proposes new texts or modifications to existing texts. A schedule for the study of these texts is established each year and this calendar by the commission to plan its work. The new or modi...

Commissioning MMS

Science.gov (United States)

Wood, Paul; Gramling, Cheryl; Stone, John; Smith, Patrick; Reiter, Jenifer

2016-01-01

This paper discusses commissioning of NASAs Magnetospheric MultiScale (MMS) Mission. The mission includes four identical spacecraft with a large, complex set of instrumentation. The planning for and execution of commissioning for this mission is described. The paper concludes by discussing lessons learned.

Hardware Accelerated Sequence Alignment with Traceback

Directory of Open Access Journals (Sweden)

Scott Lloyd

2009-01-01

in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

Operation and Monitoring of the CMS Regional Calorimeter Trigger Hardware

CERN Document Server

Klabbers, P

2008-01-01

The electronics for the Regional Calorimeter Trigger (RCT) of the Compact Muon Solenoid Experiment (CMS) have been produced, tested, and installed. The RCT hardware consists of one clock distribution crate and 18 double-sided crates containing custom boards, ASICs, and backplanes. The RCT receives 8-bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the CMS Global Calorimeter Trigger (GCT) after processing. Integration tests with the TPG and GCT subsystems have been successful. Installation is complete and the RCT is integrated into the Level-1 Trigger chain. Data taking has begun using detector noise, cosmic rays, proton-beam debris, and beamhalo muons. The operation and configuration of the RCT is a completely automated process. The tools to monitor, operate, and debug the RCT are mature and will be described in detail, as well as the results from data taking with the RCT.

Hardware-in-the-Loop Testing

Data.gov (United States)

Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

Audit of the Federal Energy Regulatory Commission`s Office of Chief Accountant

Energy Technology Data Exchange (ETDEWEB)

NONE

1995-04-07

The Federal Energy Regulatory Commission`s (Commission) mission is to oversee America`s natural gas and oil pipeline transportation, electric utility, and hydroelectric power industries to ensure that consumers receive adequate energy supplies at just and reasonable rates. To carry out this mission, the Commission issues regulations covering the accounting, reporting, and rate-making requirements of the regulated utility companies. The Commission`s Office of Chief Accountant performs financial related audits at companies to ensure compliance with these regulations. The purpose of this audit was to evaluate the office of Chief Accountant`s audit performance. Specifically, the objectives were to determine if the most appropriate audit approach was used and if a quality assurance process was in place to ensure reports were accurate and supported by the working papers.

Learning Machines Implemented on Non-Deterministic Hardware

OpenAIRE

Gupta, Suyog; Sindhwani, Vikas; Gopalakrishnan, Kailash

2014-01-01

This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementations. The hardware/software co-design methodology advocated here hinges on the deployment of compute-intensive machine learning kernels onto compute platforms that trade-off deter...

Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

Directory of Open Access Journals (Sweden)

Ali Akbar Zarezadeh

2012-01-01

Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

Science.gov (United States)

Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

2012-06-01

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

RF control hardware design for CYCIAE-100 cyclotron

Energy Technology Data Exchange (ETDEWEB)

Yin, Zhiguo, E-mail: bitbearAT@hotmail.com; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

2015-11-21

The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

Biometric Identifiers and Border Security: 9/11 Commission Recommendations and Related Issues

National Research Council Canada - National Science Library

Morgan, Daniel; Krouse, William

2005-01-01

In its final report, the 9/11 Commission concluded that funding and completing a "biometric entry-exit screening system" for travelers to and from the United States is essential to U.S. national security...

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

OpenAIRE

Drzevitzky, Stephanie; Kastens, Uwe; Platzner, Marco

2010-01-01

Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes ...

Collaboration and Coordination to Improve Adult College Completion Efforts. Policy Exchanges

Science.gov (United States)

Lane, Patrick

2015-01-01

The Adult College Completion Network--funded by Lumina Foundation and facilitated by the Western Interstate Commission for Higher Education (WICHE)--brings together and supports entities working to increase college and certificate completion by adults with prior postsecondary credits but no degree. The network was founded in part on the premise…

European antitrust policy 1957-2004: an analysis of Commission decisions

NARCIS (Netherlands)

Carree, M.; Günster, A.; Schinkel, M.P.

2010-01-01

This paper provides a survey of European antitrust law enforcement since its foundation in the Treaty of Rome of 1957 up to and including 2004. We present a complete overview and statistical analysis of all 538 formal Commission decisions under Articles 81, 82, and 86 of the European Community

Nuclear Regulatory Commission Information Digest, 1991 edition

International Nuclear Information System (INIS)

Olive, K.L.

1991-03-01

The Nuclear Regulatory Commission Information Digest provides a summary of information about the US Nuclear Regulatory Commission (NRC), NRC's regulatory responsibilities, and the areas NRC licenses. This digest is a compilation of NRC-related data and is designed to provide a quick reference to major facts about the agency and the industry it regulates. In general, the data cover 1975 through 1990, with exceptions noted. For operating US commercial nuclear power reactors, information on generating capacity and average capacity factor is obtained from Monthly Operating Reports submitted to the NRC directly by the licensee. This information is reviewed for consistency only. No independent validation and/or verification is performed by the NRC. For detailed and complete information about tables and figures, refer to the source publications. This digest is published annually for the general use of the NRC staff and is available to the public. 30 figs., 12 tabs

The VMTG Hardware Description

CERN Document Server

Puccio, B

1998-01-01

The document describes the hardware features of the CERN Master Timing Generator. This board is the common platform for the transmission of General Timing Machine required by the CERN accelerators. In addition, the paper shows the various jumper options to customise the card which is compliant to the VMEbus standard.

Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

DEFF Research Database (Denmark)

Esposito, A.; Lomuscio, A.; Nunzio, L. Di

2016-01-01

In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors......, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. The proposed architecture provides excellent flexibility with respect to the different audio applications implemented, high quality audio, and an energy efficient solution....

Hardware Approach for Real Time Machine Stereo Vision

Directory of Open Access Journals (Sweden)

Michael Tornow

2006-02-01

Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

Hardware implementation of a GFSR pseudo-random number generator

Science.gov (United States)

Aiello, G. R.; Budinich, M.; Milotti, E.

1989-12-01

We describe the hardware implementation of a pseudo-random number generator of the "Generalized Feedback Shift Register" (GFSR) type. After brief theoretical considerations we describe two versions of the hardware, the tests done and the performances achieved.

First results from the commissioning of the BGO-OD experiment at ELSA

Science.gov (United States)

Bella, Andreas

2014-11-01

The BGO-OD experiment at the ELSA accelerator facility in Bonn combines the highly segmented BGO calorimeter with a particle tracking magnetic spectrometer at forward angles. An extensive physics program using an energy tagged Bremsstrahlung photon beam is planned. The commissioning phase of the experiment is recently complete, enhancements for the BGO-OD experiment are nevertheless in development. Recent results from the analysis of the commissioning data, which includes particle track reconstruction in the forward spectrometer and momentum reconstruction with the BGO calorimeter are presented.

CEBAF Cryomodule Commissioning in the South Linac

International Nuclear Information System (INIS)

M. Drury; H. Lankford; T. Lee; J. Marshall; J. Preble; Q. Saulter; W. Schneider; Michael Spata; Mark Wiseman

1993-01-01

When complete, the Continuous Electron Beam Accelerator Facility will house a 4 GeV recirculating linear accelerator containing 42 1/4 cryomodules arrayed in two antiparallel linacs and an injector. Currently, 38 1/4 cryomodules have been installed. Each cryomodule contains eight superconducting niobium 5-cell rf cavities that operate at 1.497 GHz[1]. A cryomodule must provide an energy gain of 20 MeV to the 200 mu-A beam[2]. The resultant dynamic heat load must be less than 45 W. The cavity parameters that are measured during the commissioning process include the external Q's (Q(sub ext)) of the cavity ports, the unloaded Q (Q(sub 0)) of the cavity as a function of accelerating gradient, and the maximum operating gradient of the cavity[3]. Finally, the mechanical tuners are cycled and characterized. A portable test stand allows local control of the rf system and provides automated data acquisition. During the period from April 1993 through September 1993, 16 of the 20 cryomodules installed in the South Linac were commissioned. All cryomodules tested in the South Linac meet or exceed the CEBAF specifications. This paper describes the results of the commissioning of the first 10 cryomodules in the South Linac

Hardware Realization of Chaos Based Symmetric Image Encryption

KAUST Repository

Barakat, Mohamed L.

2012-06-01

This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

Desenvolvimento de hardware reconfigurável de criptografia assimétrica

Directory of Open Access Journals (Sweden)

Otávio Souza Martins Gomes

2015-01-01

Full Text Available Este artigo apresenta o resultado parcial do desenvolvimento de uma interface de hardware reconfigurável para criptografia assimétrica que permite a troca segura de dados. Hardwares reconfiguráveis permitem o desenvolvimento deste tipo de dispositivo com segurança e flexibilidade e possibilitam a mudança de características no projeto com baixo custo e de forma rápida.Palavras-chave: Criptografia. Hardware. ElGamal. FPGA. Segurança. Development of an asymmetric cryptography reconfigurable harwadre ABSTRACTThis paper presents some conclusions and choices about the development of an asymmetric cryptography reconfigurable hardware interface to allow a safe data communication. Reconfigurable hardwares allows the development of this kind of device with safety and flexibility, and offer the possibility to change some features with low cost and in a fast way.Keywords: Cryptography. Hardware. ElGamal. FPGAs. Security.

Testing and commissioning the multinode ECRH realtime control system on the FTU tokamak

International Nuclear Information System (INIS)

Galperti, C.; Boncagni, L.; Alessi, E.; Sozzi, C.; Nowak, S.; Granucci, G.; Minelli, D.; Marchetto, C.

2014-01-01

Highlights: • We conceived, developed and commissioned a distributed multinode control hardware with proven real-time performances. • The adopted hardware solution is modular and reconfigurable. • The adopted software solution is able to host many experimental scenarios and is totally remotely programmable, configurable and testable. • Effective results in on-line MHD instability detection are presented. - Abstract: In tokamak machines, the ECRH heating system is crucial for plasma heating and for stability control. To be reliable, an ECRH control system should be deeply integrated into the supervision and control systems of the machine, and must be interconnected to the diagnostic instruments and the power actuators of the plant. Moreover, several ECRH experiments are under investigation by the community. So, for the sake of efficiency, it should be possible to reprogram a control system on the fly and possibly from remote locations, even during experiment campaigns. This paper presents the new ECRH control system under development at the FTU tokamak. This system consists of multiple units that acquire and process data and are linked through Ethernet and dedicated fiber-optic data links, under a Linux/MARTe framework. This paper also presents open-loop operative results, both about performances of the control system and about signal processing of the diagnostics relevant to MHD control

Testing and commissioning the multinode ECRH realtime control system on the FTU tokamak

Energy Technology Data Exchange (ETDEWEB)

Galperti, C., E-mail: galperti@ifp.cnr.it [EURATOM – ENEA – CNR Fusion Association, CNR-IFP, via R. Cozzi 53, 20125 Milan (Italy); Boncagni, L., E-mail: luca.boncagni@enea.it [EURATOM – ENEA – CNR Fusion Association, Frascati Research Center, Division of Fusion Physics, Rome, Frascati (Italy); Alessi, E.; Sozzi, C.; Nowak, S.; Granucci, G.; Minelli, D.; Marchetto, C. [EURATOM – ENEA – CNR Fusion Association, CNR-IFP, via R. Cozzi 53, 20125 Milan (Italy)

2014-03-15

Highlights: • We conceived, developed and commissioned a distributed multinode control hardware with proven real-time performances. • The adopted hardware solution is modular and reconfigurable. • The adopted software solution is able to host many experimental scenarios and is totally remotely programmable, configurable and testable. • Effective results in on-line MHD instability detection are presented. - Abstract: In tokamak machines, the ECRH heating system is crucial for plasma heating and for stability control. To be reliable, an ECRH control system should be deeply integrated into the supervision and control systems of the machine, and must be interconnected to the diagnostic instruments and the power actuators of the plant. Moreover, several ECRH experiments are under investigation by the community. So, for the sake of efficiency, it should be possible to reprogram a control system on the fly and possibly from remote locations, even during experiment campaigns. This paper presents the new ECRH control system under development at the FTU tokamak. This system consists of multiple units that acquire and process data and are linked through Ethernet and dedicated fiber-optic data links, under a Linux/MARTe framework. This paper also presents open-loop operative results, both about performances of the control system and about signal processing of the diagnostics relevant to MHD control.

MRI monitoring of focused ultrasound sonications near metallic hardware.

Science.gov (United States)

Weber, Hans; Ghanouni, Pejman; Pascal-Tenorio, Aurea; Pauly, Kim Butts; Hargreaves, Brian A

2018-07-01

To explore the temperature-induced signal change in two-dimensional multi-spectral imaging (2DMSI) for fast thermometry near metallic hardware to enable MR-guided focused ultrasound surgery (MRgFUS) in patients with implanted metallic hardware. 2DMSI was optimized for temperature sensitivity and applied to monitor focus ultrasound surgery (FUS) sonications near metallic hardware in phantoms and ex vivo porcine muscle tissue. Further, we evaluated its temperature sensitivity for in vivo muscle in patients without metallic hardware. In addition, we performed a comparison of temperature sensitivity between 2DMSI and conventional proton-resonance-frequency-shift (PRFS) thermometry at different distances from metal devices and different signal-to-noise ratios (SNR). 2DMSI thermometry enabled visualization of short ultrasound sonications near metallic hardware. Calibration using in vivo muscle yielded a constant temperature sensitivity for temperatures below 43 °C. For an off-resonance coverage of ± 6 kHz, we achieved a temperature sensitivity of 1.45%/K, resulting in a minimum detectable temperature change of ∼2.5 K for an SNR of 100 with a temporal resolution of 6 s per frame. The proposed 2DMSI thermometry has the potential to allow MR-guided FUS treatments of patients with metallic hardware and therefore expand its reach to a larger patient population. Magn Reson Med 80:259-271, 2018. © 2017 International Society for Magnetic Resonance in Medicine. © 2017 International Society for Magnetic Resonance in Medicine.

European antitrust policy 1957-2004: An analysis of Commission decisions

NARCIS (Netherlands)

Carree, M.; Günster, A.; Schinkel, M.P.

2008-01-01

This paper provides a survey of European antitrust law enforcement since its foundation in the Treaty of Rome of 1957. We present a complete overview and statistical analysis of all 538 formal Commission decisions adopted up to 2004 under Articles 81, 82 and 86 of the European Community Treaty. We

75 FR 11166 - Joint Meeting of the Nuclear Regulatory Commission and the Federal Energy Regulatory Commission...

Science.gov (United States)

2010-03-10

... the Nuclear Regulatory Commission and the Federal Energy Regulatory Commission; Notice of Joint Meeting of the Nuclear Regulatory Commission and the Federal Energy Regulatory Commission March 2, 2010. The Federal Energy Regulatory Commission (FERC) and the Nuclear Regulatory Commission (NRC) will hold...

The hardware track finder processor in CMS at CERN

International Nuclear Information System (INIS)

Kluge, A.

1997-07-01

The work covers the design of the Track Finder Processor in the high energy experiment CMS at CERN/Geneva. The task of this processor is to identify muons and to measure their transverse momentum. The Track Finder makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data analysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and to measure their transverse momentum. Each 25 ns a new data set is generated. Measurement of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC. The classical method in high energy physics experiments is to employ a pattern comparison method. The predefined patterns are compared to the found patterns. The high number of data channels and the complex requirements to the spatial detector resolution do not permit to employ a pattern comparison method. A so called track following algorithm was designed, which is able to assemble complete tracks through the whole detector starting from single track segments. Instead of storing a high number of track patterns the problem is brought back to the algorithm level. Comprehensive simulations, employing the hardware simulation language VHDL, were conducted in order to optimize the algorithm and its hardware implementation. A FPGA (field program able gate array)-prototype was designed. A feasibility study to implement the track finder processor employing ASICs was conducted. (author)

Trends in computer hardware and software.

Science.gov (United States)

Frankenfeld, F M

1993-04-01

Previously identified and current trends in the development of computer systems and in the use of computers for health care applications are reviewed. Trends identified in a 1982 article were increasing miniaturization and archival ability, increasing software costs, increasing software independence, user empowerment through new software technologies, shorter computer-system life cycles, and more rapid development and support of pharmaceutical services. Most of these trends continue today. Current trends in hardware and software include the increasing use of reduced instruction-set computing, migration to the UNIX operating system, the development of large software libraries, microprocessor-based smart terminals that allow remote validation of data, speech synthesis and recognition, application generators, fourth-generation languages, computer-aided software engineering, object-oriented technologies, and artificial intelligence. Current trends specific to pharmacy and hospitals are the withdrawal of vendors of hospital information systems from the pharmacy market, improved linkage of information systems within hospitals, and increased regulation by government. The computer industry and its products continue to undergo dynamic change. Software development continues to lag behind hardware, and its high cost is offsetting the savings provided by hardware.

Beam commissioning of the 3-GeV rapid cycling synchrotron of the Japan Proton Accelerator Research Complex

Directory of Open Access Journals (Sweden)

H. Hotchi

2009-04-01

Full Text Available The 3-GeV rapid cycling synchrotron (RCS of the Japan Proton Accelerator Research Complex (J-PARC was commissioned in October 2007, and successfully accomplished 3 GeV acceleration on October 31. Six run cycles through February 2008 were dedicated to commissioning the RCS, for which the initial machine parameter tuning and various underlying beam studies were completed. Then since May 2008 the RCS beam has been delivered to the downstream facilities for their beam commissioning. In this paper we describe beam tuning and study results following our beam commissioning scenario and a beam performance and operational experience obtained in the first commissioning phase through June 2008.

CERN Neutrino Platform Hardware

CERN Document Server

Nelson, Kevin

2017-01-01

My summer research was broadly in CERN's neutrino platform hardware efforts. This project had two main components: detector assembly and data analysis work for ICARUS. Specifically, I worked on assembly for the ProtoDUNE project and monitored the safety of ICARUS as it was transported to Fermilab by analyzing the accelerometer data from its move.

Human Centered Hardware Modeling and Collaboration

Science.gov (United States)

Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

2013-01-01

In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

Analysis for Parallel Execution without Performing Hardware/Software Co-simulation

OpenAIRE

Muhammad Rashid

2014-01-01

Hardware/software co-simulation improves the performance of embedded applications by executing the applications on a virtual platform before the actual hardware is available in silicon. However, the virtual platform of the target architecture is often not available during early stages of the embedded design flow. Consequently, analysis for parallel execution without performing hardware/software co-simulation is required. This article presents an analysis methodology for parallel execution of ...

Nuclear Computerized Library for Assessing Reactor Reliability (NUCLARR): Data manual. Part 3: Hardware component failure data; Volume 5, Revision 4

International Nuclear Information System (INIS)

Reece, W.J.; Gilbert, B.G.; Richards, R.E.

1994-09-01

This data manual contains a hard copy of the information in the Nuclear Computerized Library for Assessing Reactor Reliability (NUCLARR) Version 3.5 database, which is sponsored by the US Nuclear Regulatory Commission. NUCLARR was designed as a tool for risk analysis. Many of the nuclear reactors in the US and several outside the US are represented in the NUCLARR database. NUCLARR includes both human error probability estimates for workers at the plants and hardware failure data for nuclear reactor equipment. Aggregations of these data yield valuable reliability estimates for probabilistic risk assessments and human reliability analyses. The data manual is organized to permit manual searches of the information if the computerized version is not available. Originally, the manual was published in three parts. In this revision the introductory material located in the original Part 1 has been incorporated into the text of Parts 2 and 3. The user can now find introductory material either in the original Part 1, or in Parts 2 and 3 as revised. Part 2 contains the human error probability data, and Part 3, the hardware component reliability data

Software error masking effect on hardware faults

International Nuclear Information System (INIS)

Choi, Jong Gyun; Seong, Poong Hyun

1999-01-01

Based on the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), in this work, a simulation model for fault injection is developed to estimate the dependability of the digital system in operational phase. We investigated the software masking effect on hardware faults through the single bit-flip and stuck-at-x fault injection into the internal registers of the processor and memory cells. The fault location reaches all registers and memory cells. Fault distribution over locations is randomly chosen based on a uniform probability distribution. Using this model, we have predicted the reliability and masking effect of an application software in a digital system-Interposing Logic System (ILS) in a nuclear power plant. We have considered four the software operational profiles. From the results it was found that the software masking effect on hardware faults should be properly considered for predicting the system dependability accurately in operation phase. It is because the masking effect was formed to have different values according to the operational profile

Instrument hardware and software upgrades at IPNS

International Nuclear Information System (INIS)

Worlton, Thomas; Hammonds, John; Mikkelson, D.; Mikkelson, Ruth; Porter, Rodney; Tao, Julian; Chatterjee, Alok

2006-01-01

IPNS is in the process of upgrading their time-of-flight neutron scattering instruments with improved hardware and software. The hardware upgrades include replacing old VAX Qbus and Multibus-based data acquisition systems with new systems based on VXI and VME. Hardware upgrades also include expanded detector banks and new detector electronics. Old VAX Fortran-based data acquisition and analysis software is being replaced with new software as part of the ISAW project. ISAW is written in Java for ease of development and portability, and is now used routinely for data visualization, reduction, and analysis on all upgraded instruments. ISAW provides the ability to process and visualize the data from thousands of detector pixels, each having thousands of time channels. These operations can be done interactively through a familiar graphical user interface or automatically through simple scripts. Scripts and operators provided by end users are automatically included in the ISAW menu structure, along with those distributed with ISAW, when the application is started

MFTF supervisory control and diagnostics system hardware

International Nuclear Information System (INIS)

Butner, D.N.

1979-01-01

The Supervisory Control and Diagnostics System (SCDS) for the Mirror Fusion Test Facility (MFTF) is a multiprocessor minicomputer system designed so that for most single-point failures, the hardware may be quickly reconfigured to provide continued operation of the experiment. The system is made up of nine Perkin-Elmer computers - a mixture of 8/32's and 7/32's. Each computer has ports on a shared memory system consisting of two independent shared memory modules. Each processor can signal other processors through hardware external to the shared memory. The system communicates with the Local Control and Instrumentation System, which consists of approximately 65 microprocessors. Each of the six system processors has facilities for communicating with a group of microprocessors; the groups consist of from four to 24 microprocessors. There are hardware switches so that if an SCDS processor communicating with a group of microprocessors fails, another SCDS processor takes over the communication

Flight Hardware Virtualization for On-Board Science Data Processing Project

Data.gov (United States)

National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

Real-Time Processing Library for Open-Source Hardware Biomedical Sensors.

Science.gov (United States)

Molina-Cantero, Alberto J; Castro-García, Juan A; Lebrato-Vázquez, Clara; Gómez-González, Isabel M; Merino-Monge, Manuel

2018-03-29

Applications involving data acquisition from sensors need samples at a preset frequency rate, the filtering out of noise and/or analysis of certain frequency components. We propose a novel software architecture based on open-software hardware platforms which allows programmers to create data streams from input channels and easily implement filters and frequency analysis objects. The performances of the different classes given in the size of memory allocated and execution time (number of clock cycles) were analyzed in the low-cost platform Arduino Genuino. In addition, 11 people took part in an experiment in which they had to implement several exercises and complete a usability test. Sampling rates under 250 Hz (typical for many biomedical applications) makes it feasible to implement filters, sliding windows and Fourier analysis, operating in real time. Participants rated software usability at 70.2 out of 100 and the ease of use when implementing several signal processing applications was rated at just over 4.4 out of 5. Participants showed their intention of using this software because it was percieved as useful and very easy to use. The performances of the library showed that it may be appropriate for implementing small biomedical real-time applications or for human movement monitoring, even in a simple open-source hardware device like Arduino Genuino. The general perception about this library is that it is easy to use and intuitive.

Guidelines for residential commissioning

Energy Technology Data Exchange (ETDEWEB)

Wray, Craig P.; Walker, Iain S.; Sherman, Max H.

2003-01-31

Currently, houses do not perform optimally or even as many codes and forecasts predict, largely because they are field assembled and there is no consistent process to identify problems or to correct them. Residential commissioning is a solution to this problem. This guide is the culmination of a 30-month project that began in September 1999. The ultimate objective of the project is to increase the number of houses that undergo commissioning, which will improve the quality, comfort, and safety of homes for California citizens. The project goal is to lay the groundwork for a residential commissioning industry in California focused on end-use energy and non-energy issues. As such, we intend this guide to be a beginning and not an end. Our intent is that the guide will lead to the programmatic integration of commissioning with other building industry processes, which in turn will provide more value to a single site visit for people such as home energy auditors and raters, home inspectors, and building performance contractors. Project work to support the development of this guide includes: a literature review and annotated bibliography, which facilitates access to 469 documents related to residential commissioning published over the past 20 years (Wray et al. 2000), an analysis of the potential benefits one can realistically expect from commissioning new and existing California houses (Matson et al. 2002), and an assessment of 107 diagnostic tools for evaluating residential commissioning metrics (Wray et al. 2002). In this guide, we describe the issues that non-experts should consider in developing a commissioning program to achieve the benefits we have identified. We do this by providing specific recommendations about: how to structure the commissioning process, which diagnostics to use, and how to use them to commission new and existing houses. Using examples, we also demonstrate the potential benefits of applying the recommended whole-house commissioning approach to

Compiling quantum circuits to realistic hardware architectures using temporal planners

Science.gov (United States)

Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

2018-04-01

To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

A low power biomedical signal processor ASIC based on hardware software codesign.

Science.gov (United States)

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

Fuel cell hardware-in-loop

Energy Technology Data Exchange (ETDEWEB)

Moore, R.M.; Randolf, G.; Virji, M. [University of Hawaii, Hawaii Natural Energy Institute (United States); Hauer, K.H. [Xcellvision (Germany)

2006-11-08

Hardware-in-loop (HiL) methodology is well established in the automotive industry. One typical application is the development and validation of control algorithms for drive systems by simulating the vehicle plus the vehicle environment in combination with specific control hardware as the HiL component. This paper introduces the use of a fuel cell HiL methodology for fuel cell and fuel cell system design and evaluation-where the fuel cell (or stack) is the unique HiL component that requires evaluation and development within the context of a fuel cell system designed for a specific application (e.g., a fuel cell vehicle) in a typical use pattern (e.g., a standard drive cycle). Initial experimental results are presented for the example of a fuel cell within a fuel cell vehicle simulation under a dynamic drive cycle. (author)

Commissioning and Performance of the LHCb Silicon Tracker

CERN Multimedia

van Tilburg, J; Buechler, A; Bursche , A; Chiapolini, N; Elsaesser, C; Hangartner, V; Salzmann, C; Steiner, S; Steinkamp, O; Staumann, U; Tobin, M; Vollhardt, A; Bay, A; Bettler, M O; Blanc, F; Bressieux, J; Conti, G; Fave, V; Frei, R; Gauvin, N; Gonzalez, R; Haefeli, G; Hicheur, A; Keune, A; Luisier, J; Muresan, R; Nakada, T; Needham, M; Nicolas, L; Knecht, M; Perrin, A; Potterat, C; Schneider, O; Tran, M; Aquines Gutierrez, O; Bauer, C; Britsch, M; Hofmann, W; Maciuc, F; Schmelling, M; Voss, H; Adeva, B; Esperante, D; Fungueiriño Pazos, J; Gallas, A; Pazos-Alvarez, A; Pérez-Trigo, E; Pló Casasús, M; Rogríguez Pérez, P; Saborido, J; Vázquez, P; Iakovenko, V; Okhrimenko, O; Pugatch, V

2010-01-01

The LHCb Silicon Tracker is a silicon micro-strip detector with a sensitive area of 12 m$^2$ and a total of 272k readout channels. The Silicon Tracker consists of two parts that use different detector modules. The detector installation was completed by early summer 2008 and the commissioning without beam has reached its finals stage, successfully overcoming most of the encountered problems. Currently, the detector has more than 99% of the channels fully functioning. Commissioning with particles has started using beam-induced events from the LHC injection tests in 2008 and 2009. These events allowed initial studies of the detector performance. Especially, the detector modules could be aligned with an accuracy of about 20 $\\mu$m. Furthermore, with the first beam collisions that took place end of 2009 we could further study the performance and improve the alignment of the detector.

Flexible hardware design for RSA and Elliptic Curve Cryptosystems

NARCIS (Netherlands)

Batina, L.; Bruin - Muurling, G.; Örs, S.B.; Okamoto, T.

2004-01-01

This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless

Sharing open hardware through ROP, the robotic open platform

NARCIS (Netherlands)

Lunenburg, J.; Soetens, R.P.T.; Schoenmakers, F.; Metsemakers, P.M.G.; van de Molengraft, M.J.G.; Steinbuch, M.; Behnke, S.; Veloso, M.; Visser, A.; Xiong, R.

2014-01-01

The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

Sharing open hardware through ROP, the Robotic Open Platform

NARCIS (Netherlands)

Lunenburg, J.J.M.; Soetens, R.P.T.; Schoenmakers, Ferry; Metsemakers, P.M.G.; Molengraft, van de M.J.G.; Steinbuch, M.

2013-01-01

The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

DEFF Research Database (Denmark)

Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

2015-01-01

The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware speci...

Fast DRR splat rendering using common consumer graphics hardware

International Nuclear Information System (INIS)

Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

2007-01-01

Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2x10 6 voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine

78 FR 32295 - Commission Meeting

Science.gov (United States)

2013-05-29

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... business meeting are contained in the Supplementary Information section of this notice. DATES: June 20...

77 FR 10599 - Commission Meeting

Science.gov (United States)

2012-02-22

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... business meeting are contained in the Supplementary Information section of this notice. DATES: March 15...

78 FR 12412 - Commission Meeting

Science.gov (United States)

2013-02-22

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... business meeting are contained in the Supplementary Information section of this notice. DATES: March 21...

78 FR 52601 - Commission Meeting

Science.gov (United States)

2013-08-23

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... meeting are contained in the Supplementary Information section of this notice. DATES: September 19, 2013...

77 FR 70204 - Commission Meeting

Science.gov (United States)

2012-11-23

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... meeting are contained in the SUPPLEMENTARY INFORMATION section of this notice. DATES: December 14, 2012...

78 FR 69517 - Commission Meeting

Science.gov (United States)

2013-11-19

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... meeting are contained in the Supplementary Information section of this notice. DATES: December 12, 2013...

77 FR 52106 - Commission Meeting

Science.gov (United States)

2012-08-28

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... business meeting are contained in the Supplementary Information section of this notice. DATES: September 20...

Geothermal drilling and completion technology development program. Quarterly progress report, January-March 1980

Energy Technology Data Exchange (ETDEWEB)

Varnado, S.G. (ed.)

1980-04-01

The progress, status, and results of ongoing Research and Development (R and D) within the Geothermal Drilling and Completion Technology Development Program are described. The program emphasizes the development of geothermal drilling hardware, drilling fluids, completion technology, and lost circulation control methods. Advanced drilling systems are also under development. The goals of the program are to develop the technology required to reduce well costs by 25% by 1983 and by 50% by 1987.

Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project.

Science.gov (United States)

Antonopoulos, Christos; Asimogloy, Katerina; Chiti, Sarah; D'Onofrio, Luca; Gianfranceschi, Simone; He, Danping; Iodice, Antonio; Koubias, Stavros; Koulamas, Christos; Lavagno, Luciano; Lazarescu, Mihai T; Mujica, Gabriel; Papadopoulos, George; Portilla, Jorge; Redondo, Luis; Riccio, Daniele; Riesgo, Teresa; Rodriguez, Daniel; Ruello, Giuseppe; Samoladas, Vasilis; Stoyanova, Tsenka; Touliatos, Gerasimos; Valvo, Angela; Vlahoy, Georgia

2016-06-02

In this article we present the main results obtained in the ARTEMIS-JU WSN-DPCM project between October 2011 and September 2015. The first objective of the project was the development of an integrated toolset for Wireless sensor networks (WSN) application planning, development, commissioning and maintenance, which aims to support application domain experts, with limited WSN expertise, to efficiently develop WSN applications from planning to lifetime maintenance. The toolset is made of three main tools: one for planning, one for application development and simulation (which can include hardware nodes), and one for network commissioning and lifetime maintenance. The tools are integrated in a single platform which promotes software reuse by automatically selecting suitable library components for application synthesis and the abstraction of the underlying architecture through the use of a middleware layer. The second objective of the project was to test the effectiveness of the toolset for the development of two case studies in different domains, one for detecting the occupancy state of parking lots and one for monitoring air concentration of harmful gasses near an industrial site.

Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project

Directory of Open Access Journals (Sweden)

Christos Antonopoulos

2016-06-01

Full Text Available In this article we present the main results obtained in the ARTEMIS-JU WSN-DPCM project between October 2011 and September 2015. The first objective of the project was the development of an integrated toolset for Wireless sensor networks (WSN application planning, development, commissioning and maintenance, which aims to support application domain experts, with limited WSN expertise, to efficiently develop WSN applications from planning to lifetime maintenance. The toolset is made of three main tools: one for planning, one for application development and simulation (which can include hardware nodes, and one for network commissioning and lifetime maintenance. The tools are integrated in a single platform which promotes software reuse by automatically selecting suitable library components for application synthesis and the abstraction of the underlying architecture through the use of a middleware layer. The second objective of the project was to test the effectiveness of the toolset for the development of two case studies in different domains, one for detecting the occupancy state of parking lots and one for monitoring air concentration of harmful gasses near an industrial site.

Design and commissioning of a timestamp-based data acquisition system for the DRAGON recoil mass separator

International Nuclear Information System (INIS)

Christian, G.; Fallis, J.; Hutcheon, D.; Olchanski, K.; Ruiz, C.; Akers, C.; Connolly, D.

2014-01-01

The DRAGON recoil mass separator at TRIUMF exists to study radiative proton and alpha capture reactions, which are important in a variety of astrophysical scenarios. DRAGON experiments require a data acquisition system that can be triggered on either reaction product (γ-ray or heavy ion), with the additional requirement of being able to promptly recognize coincidence events in an online environment. To this end, we have designed and implemented a new data acquisition system for DRAGON, which consists of two independently triggered readouts. Events from both systems are recorded with timestamps from a 20 MHz clock that are used to tag coincidences in the earliest possible stage of the data analysis. Here we report on the design, implementation, and commissioning of the new DRAGON data acquisition system, including the hardware, trigger logic, coincidence reconstruction algorithm, and live time considerations. We also discuss the results of an experiment commissioning the new system, which measured the strength of the E c.m. = 1113 keV resonance in the 20 Ne(p, γ) 21 Na radiative proton capture reaction. (orig.)

Development of the practical application of the recommendations of the international commission on radiological protection

International Nuclear Information System (INIS)

Dunster, H.J.

1998-01-01

The International Commission on Radiological Protection grew out of the International X-ray and Radium Protection Commission set up in 1928. Its Recommendations have developed from simple prescriptive rules for protecting the medical staff using x rays and radium to a complete System of Protection for all human activities that involve exposure to ionizing radiation. The Commission is satisfied that some of the health effects of radiation are caused, albeit with small probabilities, by small doses. Its System of Protection is therefore risk-based. It is no longer prescriptive and has to be applied with judgement. The basis of that judgement and the framework for its application are set out in ICRP Publication 60, the 1990 Recommendations of the Commission

77 FR 28420 - Commission Meeting

Science.gov (United States)

2012-05-14

... SUSQUEHANNA RIVER BASIN COMMISSION Commission Meeting AGENCY: Susquehanna River Basin Commission. ACTION: Notice. SUMMARY: The Susquehanna River Basin Commission will hold its regular business meeting on... meeting are contained in the Supplementary Information section of this notice. DATES: June 7, 2012, at 9...

Generation of Efficient High-Level Hardware Code from Dataflow Programs

OpenAIRE

Siret , Nicolas; Wipliez , Matthieu; Nezan , Jean François; Palumbo , Francesca

2012-01-01

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code, due to the difficulties of compiling input imperative languages into efficient hardware code. Moreover the hardware code generated by the HLS tools is usually target-dependant and at a low level of abstraction (i.e. gate-level...

Commissioning and validation of the ATLAS Level-1 topological trigger

CERN Document Server

AUTHOR|(SzGeCERN)788741; The ATLAS collaboration; Hong, Tae Min

2017-01-01

The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-$P_{T}$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach ...

Hardware and software status of QCDOC

International Nuclear Information System (INIS)

Boyle, P.A.; Chen, D.; Christ, N.H.; Clark, M.; Cohen, S.D.; Cristian, C.; Dong, Z.; Gara, A.; Joo, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R.D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-01-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation

Real-Time Fabric Defect Detection Using Accelerated Small-Scale Over-Completed Dictionary of Sparse Coding

Directory of Open Access Journals (Sweden)

Tianpeng Feng

2016-01-01

Full Text Available An auto fabric defect detection system via computer vision is used to replace manual inspection. In this paper, we propose a hardware accelerated algorithm based on a small-scale over-completed dictionary (SSOCD via sparse coding (SC method, which is realized on a parallel hardware platform (TMS320C6678. In order to reduce computation, the image patches projections in the training SSOCD are taken as features and the proposed features are more robust, and exhibit obvious advantages in detection results and computational cost. Furthermore, we introduce detection ratio and false ratio in order to measure the performance and reliability of the hardware accelerated algorithm. The experiments show that the proposed algorithm can run with high parallel efficiency and that the detection speed meets the real-time requirements of industrial inspection.

77 FR 76367 - Availability of E-Tag Information to Commission Staff

Science.gov (United States)

2012-12-28

...-Tag Access to MMUs, RTOs and ISOs........ 43 1. E-Tag NOPR 43 2. Comments 44 3. Commission... requires that Regional Transmission Organizations (RTOs), Independent System Operators (ISOs) and their... MMUs for RTOs and ISOs to have access to complete e-Tag information, including access to e-Tags for...

Quantum neuromorphic hardware for quantum artificial intelligence

Science.gov (United States)

Prati, Enrico

2017-08-01

The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

Introduction to co-simulation of software and hardware in embedded processor systems

Energy Technology Data Exchange (ETDEWEB)

Dreike, P.L.; McCoy, J.A.

1996-09-01

From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

RRFC hardware operation manual

International Nuclear Information System (INIS)

Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

1996-05-01

The Research Reactor Fuel Counter (RRFC) system was developed to assay the 235 U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the 235 U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics

Removal of symptomatic craniofacial titanium hardware following craniotomy: Case series and review

Directory of Open Access Journals (Sweden)

Sheri K. Palejwala

2015-06-01

Full Text Available Titanium craniofacial hardware has become commonplace for reconstruction and bone flap fixation following craniotomy. Complications of titanium hardware include palpability, visibility, infection, exposure, pain, and hardware malfunction, which can necessitate hardware removal. We describe three patients who underwent craniofacial reconstruction following craniotomies for trauma with post-operative courses complicated by medically intractable facial pain. All three patients subsequently underwent removal of the symptomatic craniofacial titanium hardware and experienced rapid resolution of their painful parasthesias. Symptomatic plates were found in the region of the frontozygomatic suture or MacCarty keyhole, or in close proximity with the supraorbital nerve. Titanium plates, though relatively safe and low profile, can cause local nerve irritation or neuropathy. Surgeons should be cognizant of the potential complications of titanium craniofacial hardware and locations that are at higher risk for becoming symptomatic necessitating a second surgery for removal.

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Liberalism, authority, and bioethics commissions.

Science.gov (United States)

MacDougall, D Robert

2013-12-01

Bioethicists working on national ethics commissions frequently think of themselves as advisors to the government, but distance themselves from any claims to actual authority. Governments however may find it beneficial to appear to defer to the authority of these commissions when designing laws and policies, and might appoint such commissions for exactly this reason. Where does the authority for setting laws and policies come from? This question is best answered from within a normative political philosophy. This paper explains the locus of moral authority as understood within one family of normative political theories--liberal political theories--and argues that most major "liberal" commentators have understood both the source and scope of ethics commissions' authority in a manner at odds with liberalism, rightly interpreted. The author argues that reexamining the implications of liberalism for bioethics commissions would mean changing what are considered valid criticisms of such commissions and also changing the content of national bioethics commission mandates. The author concludes that bioethicists who participate in such commissions ought to carefully examine their own views about the normative limits of governmental authority because such limits have important implications for the contribution that bioethicists can legitimately make to government commissions.

Hardware support for collecting performance counters directly to memory

Science.gov (United States)

Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

2012-09-25

Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

Why Open Source Hardware matters and why you should care

OpenAIRE

Gürkaynak, Frank K.

2017-01-01

Open source hardware is currently where open source software was about 30 years ago. The idea is well received by enthusiasts, there is interest and the open source hardware has gained visible momentum recently, with several well-known universities including UC Berkeley, Cambridge and ETH Zürich actively working on large projects involving open source hardware, attracting the attention of companies big and small. But it is still not quite there yet. In this talk, based on my experience on the...

Acceleration of Meshfree Radial Point Interpolation Method on Graphics Hardware

International Nuclear Information System (INIS)

Nakata, Susumu

2008-01-01

This article describes a parallel computational technique to accelerate radial point interpolation method (RPIM)-based meshfree method using graphics hardware. RPIM is one of the meshfree partial differential equation solvers that do not require the mesh structure of the analysis targets. In this paper, a technique for accelerating RPIM using graphics hardware is presented. In the method, the computation process is divided into small processes suitable for processing on the parallel architecture of the graphics hardware in a single instruction multiple data manner.

No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

Science.gov (United States)

Zaghloul, A. R. M.; Zaghloul, Y. A.

2014-06-01

We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

Performance of the Main Dipole Magnet Circuits of the LHC during Commissioning

CERN Document Server

Verweij, A; Ballarino, A; Bellesia, B; Bordry, Frederick; Cantone, A; Casas Lino, M; Castaneda Serra, A; Castillo Trello, C; Catalan-Lasheras, N; Charifoulline, Z; Coelingh, G; Dahlerup-Petersen, K; D'Angelo, G; Denz, R; Fehér, S; Flora, R; Gruwé, M; Kain, V; Khomenko, B; Kirby, G; MacPherson, A; Marqueta Barbero, A; Mess, K H; Modena, M; Mompo, R; Montabonnet, V; le Naour, S; Nisbet, D; Parma, V; Pojer, M; Ponce, L; Raimondo, A; Redaelli, S; Reymond, H; Richter, D; de Rijk, G; Rijllart, A; Romera Ramirez, I; Saban, R; Sanfilippo, S; Schmidt, R; Siemko, A; Solfaroli Camillocci, M; Thurel, Y; Thiessen, H; Venturini-Delsolaro, W; Vergara Fernandez, A; Wolf, R; Zerlauth, M

2008-01-01

During hardware commissioning of the Large Hadron Collider (LHC), 8 main dipole circuits are tested at 1.9 K and up to their nominal current. Each dipole circuit contains 154 magnets of 15 m length, and has a total stored energy of up to 1.3 GJ. All magnets are wound from Nb-Ti superconducting Rutherford cables, and contain heaters to quickly force the transition to the normal conducting state in case of a quench, and hence reduce the hot spot temperature. In this paper the performance of the first three of these circuits is presented, focussing on quench detection, heater performance, operation of the cold bypass diodes, and magnet-to-magnet quench propagation. The results as measured on the entire circuits will be compared to the test results obtained during the reception tests of the individual magnets.

Power for southern Italy: hvdc Sardinia to mainland 200 MW scheme now commissioned

Energy Technology Data Exchange (ETDEWEB)

1967-02-16

Transmission of the maximum rated power of 200 MW over the hvdc system which now links Sardinia with the Italian Mainland marks the successful completion of a notable British Export contract by English Electric. The link was commissioned on February 1. The Sardinia scheme is the seventh hvdc scheme to be completed in the world and is the first to be engineered by submarine cable.

TRIGGER

CERN Multimedia

W. Smith from contributions of C. Leonidopoulos, I. Mikulec, J. Varela and C. Wulz.

Level-1 Trigger Hardware and Software Over the past few months, the Level-1 trigger has successfully recorded data with cosmic rays over long continuous stretches as well as LHC splash events, beam halo, and collision events. The L1 trigger hardware, firmware, synchronization, performance and readiness for beam operation were reviewed in October. All L1 trigger hardware is now installed at Point 5, and most of it is completely commissioned. While the barrel ECAL Trigger Concentrator Cards are fully operational, the recently delivered endcap ECAL TCC system is still being commissioned. For most systems there is a sufficient number of spares available, but for a few systems additional reserve modules are needed. It was decided to increase the overall L1 latency by three bunch crossings to increase the safety margin for trigger timing adjustments. In order for CMS to continue data taking during LHC frequency ramps, the clock distribution tree needs to be reset. The procedures for this have been tested. A repl...

TreeBASIS Feature Descriptor and Its Hardware Implementation

Directory of Open Access Journals (Sweden)

Spencer Fowers

2014-01-01

Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Science.gov (United States)

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-01-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation. PMID:24189331

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Directory of Open Access Journals (Sweden)

Sheng-Ying Lai

2013-11-01

Full Text Available This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA and fuzzy C-means (FCM algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA. It is embedded in a System-on-Chip (SOC platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Parallel asynchronous hardware implementation of image processing algorithms

Science.gov (United States)

Coon, Darryl D.; Perera, A. G. U.

1990-01-01

Research is being carried out on hardware for a new approach to focal plane processing. The hardware involves silicon injection mode devices. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuron-like asynchronous pulse-coded form through the laminar processor. No multiplexing, digitization, or serial processing would occur in the preprocessing state. High performance is expected, based on pulse coding of input currents down to one picoampere with noise referred to input of about 10 femtoamperes. Linear pulse coding has been observed for input currents ranging up to seven orders of magnitude. Low power requirements suggest utility in space and in conjunction with very large arrays. Very low dark current and multispectral capability are possible because of hardware compatibility with the cryogenic environment of high performance detector arrays. The aforementioned hardware development effort is aimed at systems which would integrate image acquisition and image processing.

Treatment of hardware infection after osteosynthesis of lower leg using negative pressure wound therapy and transforming powder dressing.

Science.gov (United States)

Marinović, Marin; Ivandcić, Aldo; Spanjol, Josip; Pina, Maja; Bakota, Bore; Bandalović, Ante; Cukeljs, Fabijan

2014-12-01

Fractures of the distal part of the lower leg are more common in everyday practice and traumatology. In young and active patients these injuries are mainly caused by high energy trauma. They are treated with external fixator in first step, and in second step, after sanation of the soft tissue, with open reduction and internal fixation (ORIF). It is very safe and effective method of treatment. Treatment of the infections that occur in the early postoperative period after open reduction and internal fixation represents a great problem and challenge for surgeons. It is widely accepted that the presence of deep infection can't be cured in the presence of hardware. However, removal of hardware in the presence of unhealed fractures significantly complicates sanation of infection and fracture itself We have decided to present a 35-years-old patient with a hardware infection with present chronic wound with hardware exposed eight months after the first operation and six months after second operation. The wound measured one centimeter in diameter with cell detritus and bad granulations tissue inside the wound. Hardwre was exposed in the depth of the wound.The secretion was minimal. Negative Pressure Wound Therapy (NPWT) was applicated after debridemet and lavage performed in ambulatory conditions. The starting therapy was continuously -125 mm Hg of vacuum. After five days of NPWT the defect was partially filled with granula- tion tissue. For another five days we continue with NPWT with the same values of-125 mm Hg pressure but in the inter- mitent mode. After that period we used transforming powder dressing for covering and protection of the wound with was filled with granulation tissue. Five days later, wound was completely healed with epithelisation. After four months of patient follow-up, we found the wound is completely repaired. The patient denies pain and has continued orderly flow of fracture healing, with no signs of infection.

A Hybrid Hardware and Software Component Architecture for Embedded System Design

Science.gov (United States)

Marcondes, Hugo; Fröhlich, Antônio Augusto

Embedded systems are increasing in complexity, while several metrics such as time-to-market, reliability, safety and performance should be considered during the design of such systems. A component-based design which enables the migration of its components between hardware and software can cope to achieve such metrics. To enable that, we define hybrid hardware and software components as a development artifact that can be deployed by different combinations of hardware and software elements. In this paper, we present an architecture for developing such components in order to construct a repository of components that can migrate between the hardware and software domains to meet the design system requirements.

BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

DEFF Research Database (Denmark)

2010-01-01

Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...... language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one...... or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has...

Travel Software using GPU Hardware

CERN Document Server

Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

2015-01-01

Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

The principles of computer hardware

CERN Document Server

Clements, Alan

2000-01-01

Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

Some Main Results of Commissioning of the Dalat Research Reactor with Low Enriched Fuel

International Nuclear Information System (INIS)

Nguyen Nhi Dien; Luong Ba Vien; Pham Van Lam; Le Vinh Vinh; Huynh Ton Nghiem

2014-01-01

After completion of design calculation of the Dalat Nuclear Research Reactor (DNRR) for conversion from high-enriched uranium fuel (HEU) to low-enriched uranium (LEU) fuel, the commissioning programme for DNRR with entire core loaded with LEU fuel was successfully carried out from 24 November 2011 to 13 January 2012. The experimental results obtained during the implementation of commissioning programme showed a good agreement with design calculations and affirmed that the DNRR with LEU core have met all safety and exploiting requirements. (author)

Geothermal drilling and completion technology development program. Annual progress report, October 1979-September 1980

Energy Technology Data Exchange (ETDEWEB)

Varnado, S.G. (ed.)

1980-11-01

The progress, status, and results of ongoing research and development (R and D) within the Geothermal Drilling and Completion Technology Development Program are described. The program emphasizes the development of geothermal drilling hardware, drilling fluids, completion technology, and lost circulation control methods. Advanced drilling systems are also under development. The goals of the program are to develop the technology required to reduce well costs by 25% by 1983 and by 50% by 1987.

Hardware and software for image acquisition in nuclear medicine

International Nuclear Information System (INIS)

Fideles, E.L.; Vilar, G.; Silva, H.S.

1992-01-01

A system for image acquisition and processing in nuclear medicine is presented, including the hardware and software referring to acquisition. The hardware is consisted of an analog-digital conversion card, developed in wire-wape. Its function is digitate the analogic signs provided by gamma camera. The acquisitions are made in list or frame mode. (C.G.C.)

Commissioning of the Fresno, California, Retrofit Unoccupied Test House

Energy Technology Data Exchange (ETDEWEB)

Stecher, D. [IBACOS, Inc., Pittsburgh, PA (United States); Imm, C. [IBACOS, Inc., Pittsburgh, PA (United States)

2013-06-01

Commissioning of instrumentation and limited short-term testing have been completed on a retrofit unoccupied test house in Fresno, California. This house is intended to be used as a laboratory in which several different methods of space conditioning distribution will be evaluated. This report provides background on the project, including specifications of the house and models used in its development, along with models to be evaluated through its operation.

Commission Conditions d'emploi

CERN Multimedia

Staff Association

2017-01-01

Au CERN, nous avons la formidable possibilité d’imaginer nos CONDITIONS D’EMPLOIS. Rendez-vous compte ! Nous avons le pouvoir de proposer des idées et de les défendre pour avoir des conditions d’emplois qui soient les plus attractives possibles pour le personnel en place et à venir. ---------------- L’Association du personnel du CERN, tout le monde connait ou en a entendu parler. Ce qui est moins connu, ce sont les diverses commissions internes qui traitent des sujets propres à défendre les intérêts du personnel. Les publications dans notre journal, l’Echo, sont un des moyens à notre disposition pour vous faire découvrir chacune des commissions internes de l’Association du personnel (voir Echo n°242 sur la commission juridique, et Echo n°255 sur la commission des cas particuliers). Commission Conditions d&...

Hardware Realization of Chaos-based Symmetric Video Encryption

KAUST Repository

Ibrahim, Mohamad A.

2013-05-01

This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

Safe LHC beam commissioning

International Nuclear Information System (INIS)

Uythoven, J.; Schmidt, R.

2007-01-01

Due to the large amount of energy stored in magnets and beams, safety operation of the LHC is essential. The commissioning of the LHC machine protection system will be an integral part of the general LHC commissioning program. A brief overview of the LHC Machine Protection System will be given, identifying the main components: the Beam Interlock System, the Beam Dumping System, the Collimation System, the Beam Loss Monitoring System and the Quench Protection System. An outline is given of the commissioning strategy of these systems during the different commissioning phases of the LHC: without beam, injection and the different phases with stored beam depending on beam intensity and energy. (author)

Commissioning of NSLS-II

Energy Technology Data Exchange (ETDEWEB)

Willeke, F.

2015-05-03

NSLS-II, the new 3rd generation light source at BNL was designed for a brightness of 10²² photons s^-1mm^-2mrad^-2 (0.1%BW)^-1. It was constructed between 2009 and 2014. The storage ring was commissioned in April 2014 which was followed by insertion device and beamline commissioning in the fall of 2014. All ambitious design parameters of the facility have already been achieved except for commissioning the full beam intensity of 500mA which requires more RF installation. This paper reports on the results of commissioning.

Analog Exercise Hardware to Implement a High Intensity Exercise Program During Bed Rest

Science.gov (United States)

Loerch, Linda; Newby, Nate; Ploutz-Snyder, Lori

2012-01-01

Background: In order to evaluate novel countermeasure protocols in a space flight analog prior to validation on the International Space Station (ISS), NASA's Human Research Program (HRP) is sponsoring a multi-investigator bedrest campaign that utilizes a combination of commercial and custom-made exercise training hardware to conduct daily resistive and aerobic exercise protocols. This paper will describe these pieces of hardware and how they are used to support current bedrest studies at NASA's Flight Analog Research Unit in Galveston, TX. Discussion: To implement candidate exercise countermeasure studies during extended bed rest studies the following analog hardware are being utilized: Stand alone Zero-Gravity Locomotion Simulator (sZLS) -- a custom built device by NASA, the sZLS allows bedrest subjects to remain supine as they run on a vertically-oriented treadmill (0-15 miles/hour). The treadmill includes a pneumatic subject loading device to provide variable body loading (0-100%) and a harness to keep the subject in contact with the motorized treadmill to provide a ground reaction force at their feet that is quantified by a Kistler Force Plate. Supine Cycle Ergometer -- a commercially available supine cycle ergometer (Lode, Groningen, Netherlands) is used for all cycle ergometer sessions. The ergometer has adjustable shoulder supports and handgrips to help stabilize the subject during exercise. Horizontal Squat Device (HSD) -- a custom built device by Quantum Fitness Corp (Stafford, TX), the HSD allows for squat exercises to be performed while lying in a supine position. The HSD can provide 0 to 600 pounds of force in selectable 5 lb increments, and allows hip translation in both the vertical and horizontal planes. Prone Leg Curl -- a commercially available prone leg curl machine (Cybex International Inc., Medway, MA) is used to complete leg curl exercises. Horizontal Leg Press -- a commercially available horizontal leg press (Quantum Fitness Corporation) is

Unit Commissioning of “Belene” NPP (Bulgaria)

International Nuclear Information System (INIS)

2009-01-01

This presentations gives detailed information about the following topics about commissioning: principles of NPP commissioning; phases of NPP commissioning; organization of commissioning activities; duties and responsibilities of the parties for carrying out unit commissioning activities; responsibility and obligations of the sides during commissioning of power unit; documentation required for power unit commissioning; quality assurance for commissioning activities

Systematic development of industrial control systems using Software/Hardware Engineering

NARCIS (Netherlands)

Voeten, J.P.M.; van der Putten, P.H.A.; Stevens, M.P.J.; Milligan, P.; Corr, P.

1997-01-01

SHE (Software/Hardware Engineering) is a new object-oriented analysis, specification and design method for complex reactive hardware/software systems. SHE is based on the formal specification language POOSL and a design framework guiding analysis and design activities. This paper reports on the

A Virtual Commissioning Learning Platform

DEFF Research Database (Denmark)

Mortensen, Steffen; Madsen, Ole

2018-01-01

The introduction of reconfigurable manufacturing systems (RMS), Industry 4.0 and the associated technologies requires the establishment of new competencies. Towards that goal, Aalborg University (AAU) has developed an Industry 4.0 learning factory, the AAU Smart Production Lab. The AAU Smart...... Production Lab integrates a number of Industry 4.0 technologies for learning and research purposes. One of the many techniques is virtual commissioning. Virtual commissioning uses a virtual plant model and real controllers (PLCs) enabling a full emulation of the manufacturing system for verification. Virtual...... commissioning can lower the commissioning time up to 63%, allowing faster time to market. However, virtual commission is still missing industrial impact one of the reasons being lack of competencies and integration experiences. The paper presents the setup of the virtual commissioning learning platform...

CT image reconstruction system based on hardware implementation

International Nuclear Information System (INIS)

Silva, Hamilton P. da; Evseev, Ivan; Schelin, Hugo R.; Paschuk, Sergei A.; Milhoretto, Edney; Setti, Joao A.P.; Zibetti, Marcelo; Hormaza, Joel M.; Lopes, Ricardo T.

2009-01-01

Full text: The timing factor is very important for medical imaging systems, which can nowadays be synchronized by vital human signals, like heartbeats or breath. The use of hardware implemented devices in such a system has advantages considering the high speed of information treatment combined with arbitrary low cost on the market. This article refers to a hardware system which is based on electronic programmable logic called FPGA, model Cyclone II from ALTERA Corporation. The hardware was implemented on the UP3 ALTERA Kit. A partially connected neural network with unitary weights was programmed. The system was tested with 60 topographic projections, 100 points in each, of the Shepp and Logan phantom created by MATLAB. The main restriction was found to be the memory size available on the device: the dynamic range of reconstructed image was limited to 0 65535. Also, the normalization factor must be observed in order to do not saturate the image during the reconstruction and filtering process. The test shows a principal possibility to build CT image reconstruction systems for any reasonable amount of input data by arranging the parallel work of the hardware units like we have tested. However, further studies are necessary for better understanding of the error propagation from topographic projections to reconstructed image within the implemented method. (author)

Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

Directory of Open Access Journals (Sweden)

Amar Dawod

2013-04-01

Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

Performance comparison between ISCSI and other hardware and software solutions

CERN Document Server

Gug, M

2003-01-01

We report on our investigations on some technologies that can be used to build disk servers and networks of disk servers using commodity hardware and software solutions. It focuses on the performance that can be achieved by these systems and gives measured figures for different configurations. It is divided into two parts : iSCSI and other technologies and hardware and software RAID solutions. The first part studies different technologies that can be used by clients to access disk servers using a gigabit ethernet network. It covers block access technologies (iSCSI, hyperSCSI, ENBD). Experimental figures are given for different numbers of clients and servers. The second part compares a system based on 3ware hardware RAID controllers, a system using linux software RAID and IDE cards and a system mixing both hardware RAID and software RAID. Performance measurements for reading and writing are given for different RAID levels.

Hardware based redundant multi-threading inside a GPU for improved reliability

Science.gov (United States)

Sridharan, Vilas; Gurumurthi, Sudhanva

2015-05-05

A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.

DAQ INSTALLATION IN USC COMPLETED

CERN Multimedia

A. Racz

After one year of work at P5 in the underground control rooms (USC55-S1&S2), the DAQ installation in USC55 is completed. The first half of 2006 was dedicated to the DAQ infrastructures installation (private cable trays, rack equipment for a very dense cabling, connection to services i.e. water, power, network). The second half has been spent to install the custom made electronics (FRLs and FMMs) and place all the inter-rack cables/fibers connecting all sub-systems to central DAQ (more details are given in the internal pages). The installation has been carried out by DAQ group members, coming from the hardware and software side as well. The pictures show the very nice team spirit !

n_TOF New target commissioning and beam characterization

CERN Multimedia

Igashira, M

A full characterization of the neutron beam and experimental conditions for measurement with the new spallation target installed at the n_TOF facility is proposed. In a first step, the behavior the target assembly under the proton beam irradiation will be investigated, in order to complete the target commissioning. Subsequently the neutron beam parameters required to analyze the physics measurements, i.e. neutron fluence, beam profile, energy resolution function and beam related backgrounds as a function of the neutron energy, will be determined.

Basics of spectroscopic instruments. Hardware of NMR spectrometer

International Nuclear Information System (INIS)

Sato, Hajime

2009-01-01

NMR is a powerful tool for structure analysis of small molecules, natural products, biological macromolecules, synthesized polymers, samples from material science and so on. Magnetic Resonance Imaging (MRI) is applicable to plants and animals Because most of NMR experiments can be done by an automation mode, one can forget hardware of NMR spectrometers. It would be good to understand features and performance of NMR spectrometers. Here I present hardware of a modern NMR spectrometer which is fully equipped with digital technology. (author)

Integrated circuit authentication hardware Trojans and counterfeit detection

CERN Document Server

Tehranipoor, Mohammad; Zhang, Xuehui

2013-01-01

This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

ATLAS Level-1 Topological Trigger : Commissioning and Validation in Run 2

CERN Document Server

AUTHOR|(SzGeCERN)788741; The ATLAS collaboration; Hong, Tae Min

2017-01-01

The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-$P_{T}$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach ...

Hardware controls for the STAR experiment at RHIC

International Nuclear Information System (INIS)

Reichhold, D.; Bieser, F.; Bordua, M.; Cherney, M.; Chrin, J.; Dunlop, J.C.; Ferguson, M.I.; Ghazikhanian, V.; Gross, J.; Harper, G.; Howe, M.; Jacobson, S.; Klein, S.R.; Kravtsov, P.; Lewis, S.; Lin, J.; Lionberger, C.; LoCurto, G.; McParland, C.; McShane, T.; Meier, J.; Sakrejda, I.; Sandler, Z.; Schambach, J.; Shi, Y.; Willson, R.; Yamamoto, E.; Zhang, W.

2003-01-01

The STAR detector sits in a high radiation area when operating normally; therefore it was necessary to develop a robust system to remotely control all hardware. The STAR hardware controls system monitors and controls approximately 14,000 parameters in the STAR detector. Voltages, currents, temperatures, and other parameters are monitored. Effort has been minimized by the adoption of experiment-wide standards and the use of pre-packaged software tools. The system is based on the Experimental Physics and Industrial Control System (EPICS) . VME processors communicate with subsystem-based sensors over a variety of field busses, with High-level Data Link Control (HDLC) being the most prevalent. Other features of the system include interfaces to accelerator and magnet control systems, a web-based archiver, and C++-based communication between STAR online, run control and hardware controls and their associated databases. The system has been designed for easy expansion as new detector elements are installed in STAR

Motion compensation in digital subtraction angiography using graphics hardware.

Science.gov (United States)

Deuerling-Zheng, Yu; Lell, Michael; Galant, Adam; Hornegger, Joachim

2006-07-01

An inherent disadvantage of digital subtraction angiography (DSA) is its sensitivity to patient motion which causes artifacts in the subtraction images. These artifacts could often reduce the diagnostic value of this technique. Automated, fast and accurate motion compensation is therefore required. To cope with this requirement, we first examine a method explicitly designed to detect local motions in DSA. Then, we implement a motion compensation algorithm by means of block matching on modern graphics hardware. Both methods search for maximal local similarity by evaluating a histogram-based measure. In this context, we are the first who have mapped an optimizing search strategy on graphics hardware while paralleling block matching. Moreover, we provide an innovative method for creating histograms on graphics hardware with vertex texturing and frame buffer blending. It turns out that both methods can effectively correct the artifacts in most case, as the hardware implementation of block matching performs much faster: the displacements of two 1024 x 1024 images can be calculated at 3 frames/s with integer precision or 2 frames/s with sub-pixel precision. Preliminary clinical evaluation indicates that the computation with integer precision could already be sufficient.

Model Commissioning Plan and Guide Specifications

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The objectives of Model Commissioning Plan and Guide Specifications are to ensure that the design team applies commissioning concepts to the design and prepares commissioning specifications and a commission plan for inclusion in the bid construction documents.

Hardware packet pacing using a DMA in a parallel computer

Science.gov (United States)

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

2013-08-13

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

The priority queue as an example of hardware/software codesign

DEFF Research Database (Denmark)

Høeg, Flemming; Mellergaard, Niels; Staunstrup, Jørgen

1994-01-01

The paper identifies a number of issues that are believed to be important for hardware/software codesign. The issues are illustrated by a small comprehensible example: a priority queue. Based on simulations of a real application, we suggest a combined hardware/software realization of the priority...

Complete distributed computing environment for a HEP experiment: experience with ARC-connected infrastructure for ATLAS

International Nuclear Information System (INIS)

Read, A; Taga, A; O-Saada, F; Pajchel, K; Samset, B H; Cameron, D

2008-01-01

Computing and storage resources connected by the Nordugrid ARC middleware in the Nordic countries, Switzerland and Slovenia are a part of the ATLAS computing Grid. This infrastructure is being commissioned with the ongoing ATLAS Monte Carlo simulation production in preparation for the commencement of data taking in 2008. The unique non-intrusive architecture of ARC, its straightforward interplay with the ATLAS Production System via the Dulcinea executor, and its performance during the commissioning exercise is described. ARC support for flexible and powerful end-user analysis within the GANGA distributed analysis framework is also shown. Whereas the storage solution for this Grid was earlier based on a large, distributed collection of GridFTP-servers, the ATLAS computing design includes a structured SRM-based system with a limited number of storage endpoints. The characteristics, integration and performance of the old and new storage solutions are presented. Although the hardware resources in this Grid are quite modest, it has provided more than double the agreed contribution to the ATLAS production with an efficiency above 95% during long periods of stable operation

Complete distributed computing environment for a HEP experiment: experience with ARC-connected infrastructure for ATLAS

Energy Technology Data Exchange (ETDEWEB)

Read, A; Taga, A; O-Saada, F; Pajchel, K; Samset, B H; Cameron, D [Department of Physics, University of Oslo, P.b. 1048 Blindern, N-0316 Oslo (Norway)], E-mail: a.l.read@fys.uio.no

2008-07-15

Computing and storage resources connected by the Nordugrid ARC middleware in the Nordic countries, Switzerland and Slovenia are a part of the ATLAS computing Grid. This infrastructure is being commissioned with the ongoing ATLAS Monte Carlo simulation production in preparation for the commencement of data taking in 2008. The unique non-intrusive architecture of ARC, its straightforward interplay with the ATLAS Production System via the Dulcinea executor, and its performance during the commissioning exercise is described. ARC support for flexible and powerful end-user analysis within the GANGA distributed analysis framework is also shown. Whereas the storage solution for this Grid was earlier based on a large, distributed collection of GridFTP-servers, the ATLAS computing design includes a structured SRM-based system with a limited number of storage endpoints. The characteristics, integration and performance of the old and new storage solutions are presented. Although the hardware resources in this Grid are quite modest, it has provided more than double the agreed contribution to the ATLAS production with an efficiency above 95% during long periods of stable operation.

On Strong Standard Completeness in Some MTL-Delta Expansions

Czech Academy of Sciences Publication Activity Database

Vidal, Amanda; Bou, F.; Esteva, F.; Godo, L.

2017-01-01

Roč. 21, č. 1 (2017), s. 125-147 ISSN 1432-7643 R&D Projects: GA ČR(CZ) GF15-34650L Grant - others:Austrian Science Fund(AT) I1897-N25 Institutional support: RVO:67985807 Keywords : mathematical fuzzy logic * left-continuous t-norms * monoidal t-norm logic * infinitary rules * standard completeness Subject RIV: BA - General Mathematics OBOR OECD: Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8) Impact factor: 2.472, year: 2016

Complexities and Challenges of Researching Student Completion and Non-Completion of HE Programmes in Europe: A Comparative Analysis between England and Norway

Science.gov (United States)

Thomas, Liz; Hovdhaugen, Elisabeth

2014-01-01

There is a growing interest in policy research on student completion and non-continuation and bodies such as the European Commission and OECD are focusing on the subject. There is also increasing national interest in the issue in many countries and they are looking to each other for input on effective policies. However, there are significant…

Commissioning of the CMS Experiment and the Cosmic Run at Four Tesla

CERN Document Server

Chatrchyan, S; Sirunyan, A M; Adam, W; Arnold, B; Bergauer, H; Bergauer, T; Dragicevic, M; Eichberger, M; Erö, J; Friedl, M; Frühwirth, R; Ghete, V M; Hammer, J; Hänsel, S; Hoch, M; Hörmann, N; Hrubec, J; Jeitler, M; Kasieczka, G; Kastner, K; Krammer, M; Liko, D; Magrans de Abril, I; Mikulec, I; Mittermayr, F; Neuherz, B; Oberegger, M; Padrta, M; Pernicka, M; Rohringer, H; Schmid, S; Schöfbeck, R; Schreiner, T; Stark, R; Steininger, H; Strauss, J; Taurok, A; Teischinger, F; Themel, T; Uhl, D; Wagner, P; Waltenberger, W; Walzel, G; Widl, E; Wulz, C E; Chekhovsky, V; Dvornikov, O; Emeliantchik, I; Litomin, A; Makarenko, V; Marfin, I; Mossolov, V; Shumeiko, N; Solin, A; Stefanovitch, R; Suarez Gonzalez, J; Tikhonov, A; Fedorov, A; Karneyeu, A; Korzhik, M; Panov, V; Zuyeuski, R; Kuchinsky, P; Beaumont, W; Benucci, L; Cardaci, M; De Wolf, E A; Delmeire, E; Druzhkin, D; Hashemi, M; Janssen, X; Maes, T; Mucibello, L; Ochesanu, S; Rougny, R; Selvaggi, M; Van Haevermaet, H; Van Mechelen, P; Van Remortel, N; Adler, V; Beauceron, S; Blyweert, S; D'Hondt, J; De Weirdt, S; Devroede, O; Heyninck, J; Kalogeropoulos, A; Maes, J; Maes, M; Mozer, M U; Tavernier, S; Van Doninck, W; Van Mulders, P; Villella, I; Bouhali, O; Chabert, E C; Charaf, O; Clerbaux, B; De Lentdecker, G; Dero, V; Elgammal, S; Gay, A P R; Hammad, G H; Marage, P E; Rugovac, S; Vander Velde, C; Vanlaer, P; Wickens, J; Grunewald, M; Klein, B; Marinov, A; Ryckbosch, D; Thyssen, F; Tytgat, M; Vanelderen, L; Verwilligen, P; Basegmez, S; Bruno, G; Caudron, J; Delaere, C; Demin, P; Favart, D; Giammanco, A; Grégoire, G; Lemaitre, V; Militaru, O; Ovyn, S; Piotrzkowski, K; Quertenmont, L; Schul, N; Beliy, N; Daubie, E; Alves, G A; Pol, M E; Souza, M H G; Carvalho, W; De Jesus Damiao, D; De Oliveira Martins, C; Fonseca De Souza, S; Mundim, L; Oguri, V; Santoro, A; Silva Do Amaral, S M; Sznajder, A; Fernandez Perez Tomei, T R; Ferreira Dias, M A; Gregores, E M; Novaes, S F; Abadjiev, K; Anguelov, T; Damgov, J; Darmenov, N; Dimitrov, L; Genchev, V; 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Perez, E; Perinic, G; Pernot, J F; Petagna, P; Petiot, P; Petrilli, A; Pfeiffer, A; Pierini, M; Pimiä, M; Pintus, R; Pirollet, B; Postema, H; Racz, A; Ravat, S; Rew, S B; Rodrigues Antunes, J; Rolandi, G; Rovere, M; Ryjov, V; Sakulin, H; Samyn, D; Sauce, H; Schäfer, C; Schlatter, W D; Schröder, M; Schwick, C; Sciaba, A; Segoni, I; Sharma, A; Siegrist, N; Siegrist, P; Sinanis, N; Sobrier, T; Sphicas, P; Spiga, D; Spiropulu, M; Stöckli, F; Traczyk, P; Tropea, P; Troska, J; Tsirou, A; Veillet, L; Veres, G I; Voutilainen, M; Wertelaers, P; Zanetti, M; Bertl, W; Deiters, K; Erdmann, W; Gabathuler, K; Horisberger, R; Ingram, Q; Kaestli, H C; König, S; Kotlinski, D; Langenegger, U; Meier, F; Renker, D; Rohe, T; Sibille, J; Starodumov, A; Betev, B; Caminada, L; Chen, Z; Cittolin, S; Da Silva Di Calafiori, D R; Dambach, S; Dissertori, G; Dittmar, M; Eggel, C; Eugster, J; Faber, G; Freudenreich, K; Grab, C; Hervé, A; Hintz, W; Lecomte, P; Luckey, P D; Lustermann, W; Marchica, C; Milenovic, P; Moortgat, F; Nardulli, A; Nessi-Tedaldi, F; Pape, L; Pauss, F; Punz, T; Rizzi, A; Ronga, F J; Sala, L; Sanchez, A K; Sawley, M C; Sordini, V; Stieger, B; Tauscher, L; Thea, A; Theofilatos, K; Treille, D; Trüb, P; Weber, M; Wehrli, L; Weng, J; Zelepoukine, S; Amsler, C; Chiochia, V; De Visscher, S; Regenfus, C; Robmann, P; Rommerskirchen, T; Schmidt, A; Tsirigkas, D; Wilke, L; Chang, Y H; Chen, E A; Chen, W T; Go, A; Kuo, C M; Li, S W; Lin, W; Bartalini, P; Chang, P; Chao, Y; Chen, K F; Hou, W S; Hsiung, Y; Lei, Y J; Lin, S W; Lu, R S; Schümann, J; Shiu, J G; Tzeng, Y M; Ueno, K; Velikzhanin, Y; Wang, C C; Wang, M; Adiguzel, A; Ayhan, A; Azman Gokce, A; Bakirci, M N; Cerci, S; Dumanoglu, I; Eskut, E; Girgis, S; Gurpinar, E; Hos, I; Karaman, T; Kayis Topaksu, A; Kurt, P; Önengüt, G; Önengüt Gökbulut, G; Ozdemir, K; Ozturk, S; Polatöz, A; Sogut, K; Tali, B; Topakli, H; Uzun, D; Vergili, L N; Vergili, M; Akin, I V; Aliev, T; Bilmis, S; Deniz, M; Gamsizkan, H; Guler, A M; Öcalan, K; Serin, M; Sever, R; Surat, U E; Zeyrek, M; Deliomeroglu, M; Demir, D; Gülmez, E; Halu, A; Isildak, B; Kaya, M; Kaya, O; Ozkorucuklu, S; Sonmez, N; Levchuk, L; Lukyanenko, S; Soroka, D; Zub, S; Bostock, F; Brooke, J J; Cheng, T L; Cussans, D; Frazier, R; Goldstein, J; Grant, N; Hansen, M; Heath, G P; Heath, H F; Hill, C; Huckvale, B; Jackson, J; Mackay, C K; Metson, S; Newbold, D M; Nirunpong, K; Smith, V J; Velthuis, J; Walton, R; Bell, K W; Brew, C; Brown, R M; Camanzi, B; Cockerill, D J A; Coughlan, J A; Geddes, N I; Harder, K; Harper, S; Kennedy, B W; Murray, P; Shepherd-Themistocleous, C H; Tomalin, I R; Williams, J H; Womersley, W J; Worm, S D; Bainbridge, R; Ball, G; Ballin, J; Beuselinck, R; Buchmuller, O; Colling, D; Cripps, N; Davies, G; Della Negra, M; Foudas, C; Fulcher, J; Futyan, D; Hall, G; Hays, J; Iles, G; Karapostoli, G; MacEvoy, B C; Magnan, A M; Marrouche, J; Nash, J; Nikitenko, A; Papageorgiou, A; Pesaresi, M; Petridis, K; Pioppi, M; Raymond, D M; Rompotis, N; Rose, A; Ryan, M J; Seez, C; Sharp, P; Sidiropoulos, G; Stettler, M; Stoye, M; Takahashi, M; Tapper, A; Timlin, C; Tourneur, S; Vazquez Acosta, M; Virdee, T; Wakefield, S; Wardrope, D; Whyntie, T; Wingham, M; Cole, J E; Goitom, I; Hobson, P R; Khan, A; Kyberd, P; Leslie, D; Munro, C; Reid, I D; Siamitros, C; Taylor, R; Teodorescu, L; Yaselli, I; Bose, T; Carleton, M; Hazen, E; Heering, A H; Heister, A; John, J St; Lawson, P; Lazic, D; Osborne, D; Rohlf, J; Sulak, L; Wu, S; Andrea, J; Avetisyan, A; Bhattacharya, S; Chou, J P; Cutts, D; Esen, S; Kukartsev, G; Landsberg, G; Narain, M; Nguyen, D; Speer, T; Tsang, K V; Breedon, R; Calderon De La Barca Sanchez, M; Case, M; Cebra, D; Chertok, M; Conway, J; Cox, P T; Dolen, J; Erbacher, R; Friis, E; Ko, W; Kopecky, A; Lander, R; Lister, A; Liu, H; Maruyama, S; Miceli, T; Nikolic, M; Pellett, D; Robles, J; Searle, M; Smith, J; Squires, M; Stilley, J; Tripathi, M; Vasquez Sierra, R; Veelken, C; Andreev, V; Arisaka, K; Cline, D; Cousins, R; Erhan, S; Hauser, J; Ignatenko, M; Jarvis, C; Mumford, J; Plager, C; Rakness, G; Schlein, P; Tucker, J; Valuev, V; Wallny, R; Yang, X; Babb, J; Bose, M; Chandra, A; Clare, R; Ellison, J A; Gary, J W; Hanson, G; Jeng, G Y; Kao, S C; Liu, F; Liu, H; Luthra, A; Nguyen, H; Pasztor, G; Satpathy, A; Shen, B C; Stringer, R; Sturdy, J; Sytnik, V; Wilken, R; Wimpenny, S; Branson, J G; Dusinberre, E; Evans, D; Golf, F; Kelley, R; Lebourgeois, M; Letts, J; Lipeles, E; Mangano, B; Muelmenstaedt, J; Norman, M; Padhi, S; Petrucci, A; Pi, H; Pieri, M; Ranieri, R; Sani, M; Sharma, V; Simon, S; Würthwein, F; Yagil, A; Campagnari, C; D'Alfonso, M; Danielson, T; Garberson, J; Incandela, J; Justus, C; Kalavase, P; Koay, S A; Kovalskyi, D; Krutelyov, V; Lamb, J; Lowette, S; Pavlunin, V; Rebassoo, F; Ribnik, J; Richman, J; Rossin, R; Stuart, D; To, W; Vlimant, J R; Witherell, M; Apresyan, A; Bornheim, A; Bunn, J; Chiorboli, M; Gataullin, M; Kcira, D; Litvine, V; Ma, Y; Newman, H B; Rogan, C; Timciuc, V; Veverka, J; Wilkinson, R; Yang, Y; Zhang, L; Zhu, K; Zhu, R Y; Akgun, B; Carroll, R; Ferguson, T; Jang, D W; Jun, S Y; Paulini, M; Russ, J; Terentyev, N; Vogel, H; Vorobiev, I; Cumalat, J P; Dinardo, M E; Drell, B R; Ford, W T; Heyburn, B; Luiggi Lopez, E; Nauenberg, U; Stenson, K; Ulmer, K; Wagner, S R; Zang, S L; Agostino, L; Alexander, J; Blekman, F; Cassel, D; Chatterjee, A; Das, S; Gibbons, L K; Heltsley, B; Hopkins, W; Khukhunaishvili, A; Kreis, B; Kuznetsov, V; Patterson, J R; Puigh, D; Ryd, A; Shi, X; Stroiney, S; Sun, W; Teo, W D; Thom, J; Vaughan, J; Weng, Y; Wittich, P; Beetz, C P; Cirino, G; Sanzeni, C; Winn, D; Abdullin, S; Afaq, M A; Albrow, M; Ananthan, B; Apollinari, G; Atac, M; Badgett, W; Bagby, L; Bakken, J A; Baldin, B; Banerjee, S; Banicz, K; Bauerdick, L A T; Beretvas, A; Berryhill, J; Bhat, P C; Biery, K; Binkley, M; Bloch, I; Borcherding, F; Brett, A M; Burkett, K; Butler, J N; Chetluru, V; Cheung, H W K; Chlebana, F; Churin, I; Cihangir, S; Crawford, M; Dagenhart, W; Demarteau, M; Derylo, G; Dykstra, D; Eartly, D P; Elias, J E; Elvira, V D; Evans, D; Feng, L; Fischler, M; Fisk, I; Foulkes, S; Freeman, J; Gartung, P; Gottschalk, E; Grassi, T; Green, D; Guo, Y; Gutsche, O; Hahn, A; Hanlon, J; Harris, R M; Holzman, B; Howell, J; Hufnagel, D; James, E; Jensen, H; Johnson, M; Jones, C D; Joshi, U; Juska, E; Kaiser, J; Klima, B; Kossiakov, S; Kousouris, K; Kwan, S; Lei, C M; Limon, P; Lopez Perez, J A; Los, S; Lueking, L; Lukhanin, G; Lusin, S; Lykken, J; Maeshima, K; Marraffino, J M; Mason, D; McBride, P; Miao, T; Mishra, K; Moccia, S; Mommsen, R; Mrenna, S; Muhammad, A S; Newman-Holmes, C; Noeding, C; O'Dell, V; Prokofyev, O; Rivera, R; Rivetta, C H; Ronzhin, A; Rossman, P; Ryu, S; Sekhri, V; Sexton-Kennedy, E; Sfiligoi, I; Sharma, S; Shaw, T M; Shpakov, D; Skup, E; Smith, R P; Soha, A; Spalding, W J; Spiegel, L; Suzuki, I; Tan, P; Tanenbaum, W; Tkaczyk, S; Trentadue, R; Uplegger, L; Vaandering, E W; Vidal, R; Whitmore, J; Wicklund, E; Wu, W; Yarba, J; Yumiceva, F; Yun, J C; Acosta, D; Avery, P; Barashko, V; Bourilkov, D; Chen, M; Di Giovanni, G P; Dobur, D; Drozdetskiy, A; Field, R D; Fu, Y; Furic, I K; Gartner, J; Holmes, D; Kim, B; Klimenko, S; Konigsberg, J; Korytov, A; Kotov, K; Kropivnitskaya, A; Kypreos, T; Madorsky, A; Matchev, K; Mitselmakher, G; Pakhotin, Y; Piedra Gomez, J; Prescott, C; Rapsevicius, V; Remington, R; Schmitt, M; Scurlock, B; Wang, D; Yelton, J; Ceron, C; Gaultney, V; Kramer, L; Lebolo, L M; Linn, S; Markowitz, P; Martinez, G; Rodriguez, J L; Adams, T; Askew, A; Baer, H; Bertoldi, M; Chen, J; Dharmaratna, W G D; Gleyzer, S V; Haas, J; Hagopian, S; Hagopian, V; Jenkins, M; Johnson, K F; Prettner, E; Prosper, H; Sekmen, S; Baarmand, M M; Guragain, S; Hohlmann, M; Kalakhety, H; Mermerkaya, H; Ralich, R; Vodopiyanov, I; Abelev, B; Adams, M R; Anghel, I M; Apanasevich, L; Bazterra, V E; Betts, R R; Callner, J; Castro, M A; Cavanaugh, R; Dragoiu, C; Garcia-Solis, E J; Gerber, C E; Hofman, D J; Khalatian, S; Mironov, C; Shabalina, E; Smoron, A; Varelas, N; Akgun, U; Albayrak, E A; Ayan, A S; Bilki, B; Briggs, R; Cankocak, K; Chung, K; Clarida, W; Debbins, P; Duru, F; Ingram, F D; Lae, C K; McCliment, E; Merlo, J P; Mestvirishvili, A; Miller, M J; Moeller, A; Nachtman, J; Newsom, C R; Norbeck, E; Olson, J; Onel, Y; Ozok, F; Parsons, J; Schmidt, I; Sen, S; Wetzel, J; Yetkin, T; Yi, K; Barnett, B A; Blumenfeld, B; Bonato, A; Chien, C Y; Fehling, D; Giurgiu, G; Gritsan, A V; Guo, Z J; Maksimovic, P; Rappoccio, S; Swartz, M; Tran, N V; Zhang, Y; Baringer, P; Bean, A; Grachov, O; Murray, M; Radicci, V; Sanders, S; Wood, J S; Zhukova, V; Bandurin, D; Bolton, T; Kaadze, K; Liu, A; Maravin, Y; Onoprienko, D; Svintradze, I; Wan, Z; Gronberg, J; Hollar, J; Lange, D; Wright, D; Baden, D; Bard, R; Boutemeur, M; Eno, S C; Ferencek, D; Hadley, N J; Kellogg, R G; Kirn, M; Kunori, S; Rossato, K; Rumerio, P; Santanastasio, F; Skuja, A; Temple, J; Tonjes, M B; Tonwar, S C; Toole, T; Twedt, E; Alver, B; Bauer, G; Bendavid, J; Busza, W; Butz, E; Cali, I A; Chan, M; D'Enterria, D; Everaerts, P; Gomez Ceballos, G; Hahn, K A; Harris, P; Jaditz, S; Kim, Y; Klute, M; Lee, Y J; Li, W; Loizides, C; Ma, T; Miller, M; Nahn, S; Paus, C; Roland, C; Roland, G; Rudolph, M; Stephans, G; Sumorok, K; Sung, K; Vaurynovich, S; Wenger, E A; Wyslouch, B; Xie, S; Yilmaz, Y; Yoon, A S; Bailleux, D; Cooper, S I; Cushman, P; Dahmes, B; De Benedetti, A; Dolgopolov, A; Dudero, P R; Egeland, R; Franzoni, G; Haupt, J; Inyakin, A; Klapoetke, K; Kubota, Y; Mans, J; Mirman, N; Petyt, D; Rekovic, V; Rusack, R; Schroeder, M; Singovsky, A; Zhang, J; Cremaldi, L M; Godang, R; Kroeger, R; Perera, L; Rahmat, R; Sanders, D A; Sonnek, P; Summers, D; Bloom, K; Bockelman, B; Bose, S; Butt, J; Claes, D R; Dominguez, A; Eads, M; Keller, J; Kelly, T; Kravchenko, I; Lazo-Flores, J; Lundstedt, C; Malbouisson, H; Malik, S; Snow, G R; Baur, U; Iashvili, I; Kharchilava, A; Kumar, A; Smith, K; Strang, M; Alverson, G; Barberis, E; Boeriu, O; Eulisse, G; Govi, G; McCauley, T; Musienko, Y; Muzaffar, S; Osborne, I; Paul, T; Reucroft, S; Swain, J; Taylor, L; Tuura, L; Anastassov, A; Gobbi, B; Kubik, A; Ofierzynski, R A; Pozdnyakov, A; Schmitt, M; Stoynev, S; Velasco, M; Won, S; Antonelli, L; Berry, D; Hildreth, M; Jessop, C; Karmgard, D J; Kolberg, T; Lannon, K; Lynch, S; Marinelli, N; Morse, D M; Ruchti, R; Slaunwhite, J; Warchol, J; Wayne, M; Bylsma, B; Durkin, L S; Gilmore, J; Gu, J; Killewald, P; Ling, T Y; Williams, G; Adam, N; Berry, E; Elmer, P; Garmash, A; Gerbaudo, D; Halyo, V; Hunt, A; Jones, J; Laird, E; Marlow, D; Medvedeva, T; Mooney, M; Olsen, J; Piroué, P; Stickland, D; Tully, C; Werner, J S; Wildish, T; Xie, Z; Zuranski, A; Acosta, J G; Bonnett Del Alamo, M; Huang, X T; Lopez, A; Mendez, H; Oliveros, S; Ramirez Vargas, J E; Santacruz, N; Zatzerklyany, A; Alagoz, E; Antillon, E; Barnes, V E; Bolla, G; Bortoletto, D; Everett, A; Garfinkel, A F; Gecse, Z; Gutay, L; Ippolito, N; Jones, M; Koybasi, O; Laasanen, A T; Leonardo, N; Liu, C; Maroussov, V; Merkel, P; Miller, D H; Neumeister, N; Sedov, A; Shipsey, I; Yoo, H D; Zheng, Y; Jindal, P; Parashar, N; Cuplov, V; Ecklund, K M; Geurts, F J M; Liu, J H; Maronde, D; Matveev, M; Padley, B P; Redjimi, R; Roberts, J; Sabbatini, L; Tumanov, A; Betchart, B; Bodek, A; Budd, H; Chung, Y S; de Barbaro, P; Demina, R; Flacher, H; Gotra, Y; Harel, A; Korjenevski, S; Miner, D C; Orbaker, D; Petrillo, G; Vishnevskiy, D; Zielinski, M; Bhatti, A; Demortier, L; Goulianos, K; Hatakeyama, K; Lungu, G; Mesropian, C; Yan, M; Atramentov, O; Bartz, E; Gershtein, Y; Halkiadakis, E; Hits, D; Lath, A; Rose, K; Schnetzer, S; Somalwar, S; Stone, R; Thomas, S; Watts, T L; Cerizza, G; Hollingsworth, M; Spanier, S; Yang, Z C; York, A; Asaadi, J; Aurisano, A; Eusebi, R; Golyash, A; Gurrola, A; Kamon, T; Nguyen, C N; Pivarski, J; Safonov, A; Sengupta, S; Toback, D; Weinberger, M; Akchurin, N; Berntzon, L; Gumus, K; Jeong, C; Kim, H; Lee, S W; Popescu, S; Roh, Y; Sill, A; Volobouev, I; Washington, E; Wigmans, R; Yazgan, E; Engh, D; Florez, C; Johns, W; Pathak, S; Sheldon, P; Andelin, D; Arenton, M W; Balazs, M; Boutle, S; Buehler, M; Conetti, S; Cox, B; Hirosky, R; Ledovskoy, A; Neu, C; Phillips II, D; Ronquest, M; Yohay, R; Gollapinni, S; Gunthoti, K; Harr, R; Karchin, P E; Mattson, M; Sakharov, A; Anderson, M; Bachtis, M; Bellinger, J N; Carlsmith, D; Crotty, I; Dasu, S; Dutta, S; Efron, J; Feyzi, F; Flood, K; Gray, L; Grogg, K S; Grothe, M; Hall-Wilton, R; Jaworski, M; Klabbers, P; Klukas, J; Lanaro, A; Lazaridis, C; Leonard, J; Loveless, R; Magrans de Abril, M; Mohapatra, A; Ott, G; Polese, G; Reeder, D; Savin, A; Smith, W H; Sourkov, A; Swanson, J; Weinberg, M; Wenman, D; Wensveen, M; White, A

2010-01-01

The CMS Collaboration conducted a month-long data-taking exercise known as the Cosmic Run At Four Tesla in late 2008 in order to complete the commissioning of the experiment for extended operation. The operational lessons resulting from this exercise were addressed in the subsequent shutdown to better prepare CMS for LHC beams in 2009. The cosmic data collected have been invaluable to study the performance of the detectors, to commission the alignment and calibration techniques, and to make several cosmic ray measurements. The experimental setup, conditions, and principal achievements from this data-taking exercise are described along with a review of the preceding integration activities.

Commissioning of the CMS experiment and the cosmic run at four tesla

International Nuclear Information System (INIS)

2010-01-01

The CMS Collaboration conducted a month-long data-taking exercise known as the Cosmic Run At Four Tesla in late 2008 in order to complete the commissioning of the experiment for extended operation. The operational lessons resulting from this exercise were addressed in the subsequent shutdown to better prepare CMS for LHC beams in 2009. The cosmic data collected have been invaluable to study the performance of the detectors, to commission the alignment and calibration techniques, and to make several cosmic ray measurements. The experimental setup, conditions, and principal achievements from this data-taking exercise are described along with a review of the preceding integration activities.

Hardware characteristic and application

International Nuclear Information System (INIS)

Gu, Dong Hyeon

1990-03-01

The contents of this book are system board on memory, performance, system timer system click and specification, coprocessor such as programing interface and hardware interface, power supply on input and output, protection for DC output, Power Good signal, explanation on 84 keyboard and 101/102 keyboard,BIOS system, 80286 instruction set and 80287 coprocessor, characters, keystrokes and colors, communication and compatibility of IBM personal computer on application direction, multitasking and code for distinction of system.

Evaluation of Various Cleaning Methods to Remove Bacillus Spores from Spacecraft Hardware Materials

Science.gov (United States)

Venkateswaran, Kasthuri; Chung, Shirley; Allton, Judith; Kern, Roger

2004-09-01

A detailed study was made of the biological cleaning effectiveness, defined in terms of the ability to remove bacterial spores, of a number of methods used to clean hardware surfaces. Aluminum (Al 6061) and titanium (Ti 6Al-4V) were chosen for the study as they were deemed the two materials most likely to be used in spacecraft extraterrestrial sampler construction. Metal coupons (1 cm × 2.5 cm) were precleaned and inoculated with 5.8 × 103 cultivable Bacillus subtilis spores, which are commonly found on spacecraft surfaces and in the assembly environments. The inoculated coupons were subsequently cleaned using: (1) 70% isopropyl alcohol wipe; (2) water wipe; (3) multiple-solvent flight-hardware cleaning procedures used at the Jet Propulsion Laboratory (JPL); (4) Johnson Space Center-developed ultrapure water rinse; and (5) a commercial, semi-aqueous, multiple-solvent (SAMS) cleaning process. The biological cleaning effectiveness was measured by agar plate assay, sterility test (growing in liquid media), and epifluorescent microscopy. None of the cleaning protocols tested completely removed viable spores from the surface of the aluminum. In contrast, titanium was capable of being cleaned to sterility by two methods, the JPL standard and the commercial SAMS cleaning process. Further investigation showed that the passivation step employed in the JPL standard method is an effective surface sterilant on both metals but not compatible with aluminum. It is recommended that titanium (Ti 6Al-4V) be considered superior to aluminum (Al 6061) for use in spacecraft sampling hardware, both for its potential to be cleaned to sterilization and for its ability to withstand the most effective cleaning protocols.

Hardware architecture design of image restoration based on time-frequency domain computation

Science.gov (United States)

Wen, Bo; Zhang, Jing; Jiao, Zipeng

2013-10-01

The image restoration algorithms based on time-frequency domain computation is high maturity and applied widely in engineering. To solve the high-speed implementation of these algorithms, the TFDC hardware architecture is proposed. Firstly, the main module is designed, by analyzing the common processing and numerical calculation. Then, to improve the commonality, the iteration control module is planed for iterative algorithms. In addition, to reduce the computational cost and memory requirements, the necessary optimizations are suggested for the time-consuming module, which include two-dimensional FFT/IFFT and the plural calculation. Eventually, the TFDC hardware architecture is adopted for hardware design of real-time image restoration system. The result proves that, the TFDC hardware architecture and its optimizations can be applied to image restoration algorithms based on TFDC, with good algorithm commonality, hardware realizability and high efficiency.

Automating an EXAFS facility: hardware and software considerations

International Nuclear Information System (INIS)

Georgopoulos, P.; Sayers, D.E.; Bunker, B.; Elam, T.; Grote, W.A.

1981-01-01

The basic design considerations for computer hardware and software, applicable not only to laboratory EXAFS facilities, but also to synchrotron installations, are reviewed. Uniformity and standardization of both hardware configurations and program packages for data collection and analysis are heavily emphasized. Specific recommendations are made with respect to choice of computers, peripherals, and interfaces, and guidelines for the development of software packages are set forth. A description of two working computer-interfaced EXAFS facilities is presented which can serve as prototypes for future developments. 3 figures

Nuclear Regulatory Commission information digest

International Nuclear Information System (INIS)

1990-03-01

The Nuclear Regulatory Commission information digest provides summary information regarding the US Nuclear Regulatory Commission, its regulatory responsibilities, and areas licensed by the commission. This is an annual publication for the general use of the NRC Staff and is available to the public. The digest is divided into two parts: the first presents an overview of the US Nuclear Regulatory Commission and the second provides data on NRC commercial nuclear reactor licensees and commercial nuclear power reactors worldwide

A Guide to Building Commissioning

Energy Technology Data Exchange (ETDEWEB)

Baechler, Michael C.

2011-09-01

Commissioning is the process of verifying that a building's heating, ventilation, and air conditioning (HVAC) and lighting systems perform correctly and efficiently. Without commissioning, system and equipment problems can result in higher than necessary utility bills and unexpected and costly equipment repairs. This report reviews the benefits of commissioning, why it is a requirement for Leadership in Energy and Environmental Design (LEED) certification, and why building codes are gradually adopting commissioning activities into code.

Federal Energy Regulatory Commission`s fiscal year 1996 financial statement audit

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-02-14

This report presents the results of the independent certified public accountants` audit of the Federal Energy Regulatory Commission`s (FERC) financial statements as of September 30, 1996. The auditors have expressed an unqualified opinion on the 1996 statement of financial position and the related statements of operations and changes in net position.

Power Hardware-in-the-Loop-Based Anti-Islanding Evaluation and Demonstration

Energy Technology Data Exchange (ETDEWEB)

Schoder, Karl [Florida State Univ., Tallahassee, FL (United States). Ceter for Advanced Power Systems (CAPS); Langston, James [Florida State Univ., Tallahassee, FL (United States). Ceter for Advanced Power Systems (CAPS); Hauer, John [Florida State Univ., Tallahassee, FL (United States). Ceter for Advanced Power Systems (CAPS); Bogdan, Ferenc [Florida State Univ., Tallahassee, FL (United States). Ceter for Advanced Power Systems (CAPS); Steurer, Michael [Florida State Univ., Tallahassee, FL (United States). Ceter for Advanced Power Systems (CAPS); Mather, Barry [National Renewable Energy Lab. (NREL), Golden, CO (United States)

2015-10-01

The National Renewable Energy Laboratory (NREL) teamed with Southern California Edison (SCE), Clean Power Research (CPR), Quanta Technology (QT), and Electrical Distribution Design (EDD) to conduct a U.S. Department of Energy (DOE) and California Public Utility Commission (CPUC) California Solar Initiative (CSI)-funded research project investigating the impacts of integrating high-penetration levels of photovoltaics (PV) onto the California distribution grid. One topic researched in the context of high-penetration PV integration onto the distribution system is the ability of PV inverters to (1) detect islanding conditions (i.e., when the distribution system to which the PV inverter is connected becomes disconnected from the utility power connection) and (2) disconnect from the islanded system within the time specified in the performance specifications outlined in IEEE Standard 1547. This condition may cause damage to other connected equipment due to insufficient power quality (e.g., over-and under-voltages) and may also be a safety hazard to personnel that may be working on feeder sections to restore service. NREL teamed with the Florida State University (FSU) Center for Advanced Power Systems (CAPS) to investigate a new way of testing PV inverters for IEEE Standard 1547 unintentional islanding performance specifications using power hardware-in-loop (PHIL) laboratory testing techniques.

A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications.

Science.gov (United States)

Raghunathan, Shriram; Gupta, Sumeet K; Markandeya, Himanshu S; Roy, Kaushik; Irazoqui, Pedro P

2010-10-30

Implantable neural prostheses that deliver focal electrical stimulation upon demand are rapidly emerging as an alternate therapy for roughly a third of the epileptic patient population that is medically refractory. Seizure detection algorithms enable feedback mechanisms to provide focally and temporally specific intervention. Real-time feasibility and computational complexity often limit most reported detection algorithms to implementations using computers for bedside monitoring or external devices communicating with the implanted electrodes. A comparison of algorithms based on detection efficacy does not present a complete picture of the feasibility of the algorithm with limited computational power, as is the case with most battery-powered applications. We present a two-dimensional design optimization approach that takes into account both detection efficacy and hardware cost in evaluating algorithms for their feasibility in an implantable application. Detection features are first compared for their ability to detect electrographic seizures from micro-electrode data recorded from kainate-treated rats. Circuit models are then used to estimate the dynamic and leakage power consumption of the compared features. A score is assigned based on detection efficacy and the hardware cost for each of the features, then plotted on a two-dimensional design space. An optimal combination of compared features is used to construct an algorithm that provides maximal detection efficacy per unit hardware cost. The methods presented in this paper would facilitate the development of a common platform to benchmark seizure detection algorithms for comparison and feasibility analysis in the next generation of implantable neuroprosthetic devices to treat epilepsy. Copyright © 2010 Elsevier B.V. All rights reserved.

Commodity hardware and software summary

International Nuclear Information System (INIS)

Wolbers, S.

1997-04-01

A review is given of the talks and papers presented in the Commodity Hardware and Software Session at the CHEP97 conference. An examination of the trends leading to the consideration of PC's for HEP is given, and a status of the work that is being done at various HEP labs and Universities is given

Power Hardware-in-the-Loop Evaluation of PV Inverter Grid Support on Hawaiian Electric Feeders

Energy Technology Data Exchange (ETDEWEB)

Nelson, Austin A [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Prabakar, Kumaraguru [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Nagarajan, Adarsh [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Nepal, Shaili [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Hoke, Anderson F [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Asano, Marc [Hawaiian Electric Company; Ueda, Reid [Hawaiian Electric Company; Ifuku, Earle [Hawaiian Electric Company

2017-10-03

As more grid-connected photovoltaic (PV) inverters become compliant with evolving interconnections requirements, there is increased interest from utilities in understanding how to best deploy advanced grid-support functions (GSF) in the field. One efficient and cost-effective method to examine such deployment options is to leverage power hardware-in-the-loop (PHIL) testing methods, which combine the fidelity of hardware tests with the flexibility of computer simulation. This paper summarizes a study wherein two Hawaiian Electric feeder models were converted to real-time models using an OPAL-RT real-time digital testing platform, and integrated with models of GSF capable PV inverters based on characterization test data. The integrated model was subsequently used in PHIL testing to evaluate the effects of different fixed power factor and volt-watt control settings on voltage regulation of the selected feeders using physical inverters. Selected results are presented in this paper, and complete results of this study were provided as inputs for field deployment and technical interconnection requirements for grid-connected PV inverters on the Hawaiian Islands.

Monitoring Based Commissioning: Benchmarking Analysis of 24 UC/CSU/IOU Projects

Energy Technology Data Exchange (ETDEWEB)

Mills, Evan; Mathew, Paul

2009-04-01

Buildings rarely perform as intended, resulting in energy use that is higher than anticipated. Building commissioning has emerged as a strategy for remedying this problem in non-residential buildings. Complementing traditional hardware-based energy savings strategies, commissioning is a 'soft' process of verifying performance and design intent and correcting deficiencies. Through an evaluation of a series of field projects, this report explores the efficacy of an emerging refinement of this practice, known as monitoring-based commissioning (MBCx). MBCx can also be thought of as monitoring-enhanced building operation that incorporates three components: (1) Permanent energy information systems (EIS) and diagnostic tools at the whole-building and sub-system level; (2) Retro-commissioning based on the information from these tools and savings accounting emphasizing measurement as opposed to estimation or assumptions; and (3) On-going commissioning to ensure efficient building operations and measurement-based savings accounting. MBCx is thus a measurement-based paradigm which affords improved risk-management by identifying problems and opportunities that are missed with periodic commissioning. The analysis presented in this report is based on in-depth benchmarking of a portfolio of MBCx energy savings for 24 buildings located throughout the University of California and California State University systems. In the course of the analysis, we developed a quality-control/quality-assurance process for gathering and evaluating raw data from project sites and then selected a number of metrics to use for project benchmarking and evaluation, including appropriate normalizations for weather and climate, accounting for variations in central plant performance, and consideration of differences in building types. We performed a cost-benefit analysis of the resulting dataset, and provided comparisons to projects from a larger commissioning 'Meta-analysis' database. A

Commissioning of the ATLAS electromagnetic calorimeter and Z' → e+e- discovery potential in the first LHC data

International Nuclear Information System (INIS)

Mangeard, P.S.

2009-07-01

After about fifteen years of development, the ATLAS detector is ready to operate and it recorded, in 2008, several millions of cosmic events as well as first LHC data. This achievement is based on the long experience of beam tests and on the large effort towards the detector in situ commissioning undertaken by the ATLAS collaboration. This promises fast ability to perform searches for evidence of the Higgs boson and new physics. I heavily contributed to the in situ commissioning of the electromagnetic calorimeter. To verify its performance, I studied the first cosmic data taken in 2006 which allowed the first in situ analysis of dead channels, energy reconstruction and detector response uniformity. This participation to the commissioning has continued with the study of the single beam data recorded during the first week of LHC operation (Sept. 2008). Expanding on my expertise of the electromagnetic calorimeter, I focused my physics analysis, prepared with simulation, on the promising discovery potential of new physics at LHC via the di-electron/di-photon decay of new heavy gauge boson in the early LHC data (the first 100 pb -1 ). Possible limitations coming from early hardware problems or imperfect electron energy calibration in first data have been estimated. According to the new schedule of LHC operation, this analysis will be possible with 10 TeV pp collisions data in 2010. (author)

Surface moisture measurement system hardware acceptance test report

Energy Technology Data Exchange (ETDEWEB)

Ritter, G.A., Westinghouse Hanford

1996-05-28

This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

Computer organization and design the hardware/software interface

CERN Document Server

Hennessy, John L

1994-01-01

Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

The role of the visual hardware system in rugby performance ...

African Journals Online (AJOL)

This study explores the importance of the 'hardware' factors of the visual system in the game of rugby. A group of professional and club rugby players were tested and the results compared. The results were also compared with the established norms for elite athletes. The findings indicate no significant difference in hardware ...

OER Approach for Specific Student Groups in Hardware-Based Courses

Science.gov (United States)

Ackovska, Nevena; Ristov, Sasko

2014-01-01

Hardware-based courses in computer science studies require much effort from both students and teachers. The most important part of students' learning is attending in person and actively working on laboratory exercises on hardware equipment. This paper deals with a specific group of students, those who are marginalized by not being able to…

49 CFR 238.105 - Train electronic hardware and software safety.

Science.gov (United States)

2010-10-01

... and software system safety as part of the pre-revenue service testing of the equipment. (d)(1... safely by initiating a full service brake application in the event of a hardware or software failure that... 49 Transportation 4 2010-10-01 2010-10-01 false Train electronic hardware and software safety. 238...

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

Science.gov (United States)

Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

2011-11-01

Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

2D to 3D conversion implemented in different hardware

Science.gov (United States)

Ramos-Diaz, Eduardo; Gonzalez-Huitron, Victor; Ponomaryov, Volodymyr I.; Hernandez-Fragoso, Araceli

2015-02-01

Conversion of available 2D data for release in 3D content is a hot topic for providers and for success of the 3D applications, in general. It naturally completely relies on virtual view synthesis of a second view given by original 2D video. Disparity map (DM) estimation is a central task in 3D generation but still follows a very difficult problem for rendering novel images precisely. There exist different approaches in DM reconstruction, among them manually and semiautomatic methods that can produce high quality DMs but they demonstrate hard time consuming and are computationally expensive. In this paper, several hardware implementations of designed frameworks for an automatic 3D color video generation based on 2D real video sequence are proposed. The novel framework includes simultaneous processing of stereo pairs using the following blocks: CIE L*a*b* color space conversions, stereo matching via pyramidal scheme, color segmentation by k-means on an a*b* color plane, and adaptive post-filtering, DM estimation using stereo matching between left and right images (or neighboring frames in a video), adaptive post-filtering, and finally, the anaglyph 3D scene generation. Novel technique has been implemented on DSP TMS320DM648, Matlab's Simulink module over a PC with Windows 7, and using graphic card (NVIDIA Quadro K2000) demonstrating that the proposed approach can be applied in real-time processing mode. The time values needed, mean Similarity Structural Index Measure (SSIM) and Bad Matching Pixels (B) values for different hardware implementations (GPU, Single CPU, and DSP) are exposed in this paper.

47 CFR 1.1528 - Commission review.

Science.gov (United States)

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false Commission review. 1.1528 Section 1.1528... Commission review. Either the applicant or Bureau counsel may seek Commission review of the initial decision on the application, or the Commission may decide to review the decision on its own initiative, in...

A Framework for Hardware-Accelerated Services Using Partially Reconfigurable SoCs

Directory of Open Access Journals (Sweden)

MACHIDON, O. M.

2016-05-01

Full Text Available The current trend towards ?Everything as a Service? fosters a new approach on reconfigurable hardware resources. This innovative, service-oriented approach has the potential of bringing a series of benefits for both reconfigurable and distributed computing fields by favoring a hardware-based acceleration of web services and increasing service performance. This paper proposes a framework for accelerating web services by offloading the compute-intensive tasks to reconfigurable System-on-Chip (SoC devices, as integrated IP (Intellectual Property cores. The framework provides a scalable, dynamic management of the tasks and hardware processing cores, based on dynamic partial reconfiguration of the SoC. We have enhanced security of the entire system by making use of the built-in detection features of the hardware device and also by implementing active counter-measures that protect the sensitive data.

Outline of a Hardware Reconfiguration Framework for Modular Industrial Mobile Manipulators

DEFF Research Database (Denmark)

Schou, Casper; Bøgh, Simon; Madsen, Ole

2014-01-01

This paper presents concepts and ideas of a hard- ware reconfiguration framework for modular industrial mobile manipulators. Mobile manipulators pose a highly flexible pro- duction resource due to their ability to autonomously navigate between workstations. However, due to this high flexibility new...... approaches to the operation of the robots are needed. Reconfig- uring the robot to a new task should be carried out by shop floor operators and, thus, be both quick and intuitive. Late research has already proposed a method for intuitive robot programming. However, this relies on a predetermined hardware...... configuration. Finding a single multi-purpose hardware configuration suited to all tasks is considered unrealistic. As a result, the need for reconfiguration of the hardware is inevitable. In this paper an outline of a framework for making hardware reconfiguration quick and intuitive is presented. Two main...

Optimized hardware design for the divertor remote handling control system

Energy Technology Data Exchange (ETDEWEB)

Saarinen, Hannu [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland)], E-mail: hannu.saarinen@tut.fi; Tiitinen, Juha; Aha, Liisa; Muhammad, Ali; Mattila, Jouni; Siuko, Mikko; Vilenius, Matti [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland); Jaervenpaeae, Jorma [VTT Systems Engineering, Tekniikankatu 1, 33720 Tampere (Finland); Irving, Mike; Damiani, Carlo; Semeraro, Luigi [Fusion for Energy, Josep Pla 2, Torres Diagonal Litoral B3, 08019 Barcelona (Spain)

2009-06-15

A key ITER maintenance activity is the exchange of the divertor cassettes. One of the major focuses of the EU Remote Handling (RH) programme has been the study and development of the remote handling equipment necessary for divertor exchange. The current major step in this programme involves the construction of a full scale physical test facility, namely DTP2 (Divertor Test Platform 2), in which to demonstrate and refine the RH equipment designs for ITER using prototypes. The major objective of the DTP2 project is the proof of concept studies of various RH devices, but is also important to define principles for standardizing control hardware and methods around the ITER maintenance equipment. This paper focuses on describing the control system hardware design optimization that is taking place at DTP2. Here there will be two RH movers, namely the Cassette Multifuctional Mover (CMM), Cassette Toroidal Mover (CTM) and assisting water hydraulic force feedback manipulators (WHMAN) located aboard each Mover. The idea here is to use common Real Time Operating Systems (RTOS), measurement and control IO-cards etc. for all maintenance devices and to standardize sensors and control components as much as possible. In this paper, new optimized DTP2 control system hardware design and some initial experimentation with the new DTP2 RH control system platform are presented. The proposed new approach is able to fulfil the functional requirements for both Mover and Manipulator control systems. Since the new control system hardware design has reduced architecture there are a number of benefits compared to the old approach. The simplified hardware solution enables the use of a single software development environment and a single communication protocol. This will result in easier maintainability of the software and hardware, less dependence on trained personnel, easier training of operators and hence reduced the development costs of ITER RH.

Atomic Energy Commission Act, 1963

International Nuclear Information System (INIS)

1963-01-01

Promulgated in 1963, the Atomic Energy Commission Act (204) established and vested in the Ghana Atomic Energy Commission the sole responsibility for all matters relating to the peaceful uses of atomic energy in the country. Embodied in the Act are provisions relating to the powers, duties, rights and liabilities of the Commission. (EAA)

Commissioning the GTA accelerator

International Nuclear Information System (INIS)

Sander, O.R.; Atkins, W.H.; Bolme, G.O.; Bowling, S.; Brown, S.; Cole, R.; Gilpatrick, J.D.; Garnett, R.; Guy, F.W.; Ingalls, W.B.; Johnson, K.F.; Kerstiens, D.; Little, C.; Lohsen, R.A.; Lloyd, S.; Lysenko, W.P.; Mottershead, C.T.; Neuschaefer, G.; Power, J.; Rusthoi, D.P.; Sandoval, D.P.; Stevens, R.R.; Vaughn, G.; Wadlinger, E.A.; Connolly, R.; Weiss, R.; Saadatmand, K.

1992-01-01

The Ground Test Accelerator (GTA) is being used to resolve the physics and engineering issues related to accelerating, focusing, and steering a high-brightness, high-current H - beam and then neutralizing it. The goal is to produce a 24 MeV, 50 mA device with a 2% duty factor. Specific features of the GTA -- injector, beam optics, rf linac structures, diagnostics, control and rf power systems are described. The first four steps in commissioning have been completed. The RFQ predicted and measured performances are in good agreement; however, the transmission is lower than specifications. Input emittance is larger than design specifications and increases the effects of image charge and multipoles. Displacement of steering magnets in either the horizontal or vertical plane caused beam displacements in both planes. It is suspected that quadrupole rotation is the cause of the coupled motion. 9 figs., 5 tabs., 11 refs

Security challenges and opportunities in adaptive and reconfigurable hardware

OpenAIRE

Costan, Victor Marius; Devadas, Srinivas

2011-01-01

We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two pa...

Review of Maxillofacial Hardware Complications and Indications for Salvage

OpenAIRE

Hernandez Rosa, Jonatan; Villanueva, Nathaniel L.; Sanati-Mehrizy, Paymon; Factor, Stephanie H.; Taub, Peter J.

2015-01-01

From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances w...

System-level protection and hardware Trojan detection using weighted voting.

Science.gov (United States)

Amin, Hany A M; Alkabani, Yousra; Selim, Gamal M I

2014-07-01

The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

System-level protection and hardware Trojan detection using weighted voting

Directory of Open Access Journals (Sweden)

Hany A.M. Amin

2014-07-01

Full Text Available The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

Commissioning of the iGp Feedback System at DAΦNE

International Nuclear Information System (INIS)

Drago, A.; Fox, J.D.; Teytelman, D.; Tobiyama, M.

2011-01-01

The iGp (Integrated Gigasample Processor) is an innovative digital bunch-by-bunch feedback system developed by a KEK / SLAC / INFN-LNF joint collaboration. The processing unit can sample at 500 MHz and compute the bunch-by-bunch output signal for up to ∼5000 bunches. The feedback gateware code is implemented inside just one FPGA (Field Programmable Gate Array) chip, a Xilinx Virtex-II. The FPGA implements two banks of 16-tap FIR (Finite Impulse Response) filters. Each filter is realtime programmable through the operator interface. At DAΦNE, the Frascati Φ-Factory, two iGp units have been commissioned in the April 2007. The iGp systems have substituted the previous betatron feedback systems. This insertion has been very fast and has shown no problems involving just a substitution of the old, less flexible, digital systems, letting unchanged the baseband analog frontend and backend. The commissioning has been very simple, due to the complete and powerful EPICS operator interface, working well in local and remote operations. The software includes also tools for analyzing post processor data. A description of the commissioning with the operations done is reported.

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

Science.gov (United States)

Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

2015-01-01

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

Role of the team of scientific and technical commissioning support (TSTCS) during Mochovce NPP unit 3 and 4 commissioning

International Nuclear Information System (INIS)

Hermansky, J.; Prachar, M.; Sedlacek, M.; Petenyi, V.

2011-01-01

The Team of Scientific and Technical Commissioning Support (TSTCS) shall provide an independent support for the Mochovce NPP 3 and 4 Commissioning Department during Mochovce Units 3 and 4 commissioning. This independent support will be in line with the Mochovce NPP 3 and 4 Directive 'Non-active tests and commissioning' and it will be carried out in form of professional and expert works focusing on supervision of fulfilment of requirements for nuclear safety observance. The TSTCS duty to provide for such services during NPP commissioning is specified by Slovak Regulatory Body legislation. The independent TSTCS will supervise; - fulfilment of requirements for nuclear safety during preparation and implementation of commissioning tests; -scientific and technical level of commissioning programmes, and reflection on nuclear safety requirements in commissioning programmes,- commissioning process and test results. Main standpoints of the Team activities for individual unit commissioning stages will be; - assesment of the selected programs of functional tests in installations having an impact on nuclear safety and evaluation of the results of these tests; - assesment of the programs of physics and power commissioning, - assesment of the unit preparedness before fuel loading start; - assesment of the unit preparedness for performing initial criticality and low power commissioning and power commissioning stages; - evaluation of the results of physics and power commissioning stages and sub-stages; - final evaluation of the results from implementing the physics and power commissioning stages. The paper also presents a short description of the Team scope activities, the Team organisation, and a procedure for issuing of standpoints to individual unit commissioning stages. (Authors)

The commissioning of the BRISOL facility

Energy Technology Data Exchange (ETDEWEB)

Tang, B., E-mail: tangb364@126.com; Cui, B.; Chen, L.; Huang, Q.; Ma, R.; Ma, Y.; Ma, X.; Zhang, T.; Jiang, W.

2016-06-01

The Beijing Radioactive ion beam facility Isotope Separator On-Line (BRISOL) is a radioactive ion beam facility based on a 100 MeV cyclotron providing 100 μA proton beam bombarding a thick target to produce radioactive nuclei, which are transferred into an ion source to produce a singly-charged ion beam. The construction and installation of BRISOL was completed in March 2014. The commissioning of the BRISOL facility with stable beams has been carried out in the last year. The ion source, the separator and the beam-line were tested with a {sup 39}K{sup +} stable beam. The tests and the current status of the BRISOL facility will be presented in this paper.

Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

Science.gov (United States)

Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

2015-01-01

Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

WE-AB-201-00: Treatment Planning System Commissioning and QA

International Nuclear Information System (INIS)

2015-01-01

Treatment planning systems (TPS) are a cornerstone of modern radiation therapy. Errors in their commissioning or use can have a devastating impact on many patients. To support safe and high quality care, medical physicists must conduct efficient and proper commissioning, good clinical integration, and ongoing quality assurance (QA) of the TPS. AAPM Task Group 53 and related publications have served as seminal benchmarks for TPS commissioning and QA over the past two decades. Over the same time, continuing innovations have made the TPS even more complex and more central to the clinical process. Medical goals are now expressed in terms of the dose and margins around organs and tissues that are delineated from multiple imaging modalities (CT, MR and PET); and even temporally resolved (i.e., 4D) imaging. This information is passed on to optimization algorithms to establish accelerator movements that are programmed directly for IMRT, VMAT and stereotactic treatments. These advances have made commissioning and QA of the TPS much more challenging. This education session reviews up-to-date experience and guidance on this subject; including the recently published AAPM Medical Physics Practice Guideline (MPPG) #5 “Commissioning and QA of Treatment Planning Dose Calculations: Megavoltage Photon and Electron Beams”. Treatment Planning System Commissioning and QA: Challenges and Opportunities (Greg Salomons) This session will provide some key background and review publications describing prominent incidents relating to TPS commissioning and QA. Traditional approaches have been hardware and feature oriented. They aim to establish a functional configuration and establish specifications for regular testing of features (like dose calculation) to assure stable operation and detect failures. With the advent of more complex systems, more patient-specific testing has also been adopted. A number of actual TPS defects will be presented along with heuristics for identifying similar

WE-AB-201-00: Treatment Planning System Commissioning and QA

Energy Technology Data Exchange (ETDEWEB)

NONE

2015-06-15

Treatment planning systems (TPS) are a cornerstone of modern radiation therapy. Errors in their commissioning or use can have a devastating impact on many patients. To support safe and high quality care, medical physicists must conduct efficient and proper commissioning, good clinical integration, and ongoing quality assurance (QA) of the TPS. AAPM Task Group 53 and related publications have served as seminal benchmarks for TPS commissioning and QA over the past two decades. Over the same time, continuing innovations have made the TPS even more complex and more central to the clinical process. Medical goals are now expressed in terms of the dose and margins around organs and tissues that are delineated from multiple imaging modalities (CT, MR and PET); and even temporally resolved (i.e., 4D) imaging. This information is passed on to optimization algorithms to establish accelerator movements that are programmed directly for IMRT, VMAT and stereotactic treatments. These advances have made commissioning and QA of the TPS much more challenging. This education session reviews up-to-date experience and guidance on this subject; including the recently published AAPM Medical Physics Practice Guideline (MPPG) #5 “Commissioning and QA of Treatment Planning Dose Calculations: Megavoltage Photon and Electron Beams”. Treatment Planning System Commissioning and QA: Challenges and Opportunities (Greg Salomons) This session will provide some key background and review publications describing prominent incidents relating to TPS commissioning and QA. Traditional approaches have been hardware and feature oriented. They aim to establish a functional configuration and establish specifications for regular testing of features (like dose calculation) to assure stable operation and detect failures. With the advent of more complex systems, more patient-specific testing has also been adopted. A number of actual TPS defects will be presented along with heuristics for identifying similar

Hardware and layout aspects affecting maintainability

International Nuclear Information System (INIS)

Jayaraman, V.N.; Surendar, Ch.

1977-01-01

It has been found from maintenance experience at the Rajasthan Atomic Power Station that proper hardware and instrumentation layout can reduce maintenance and down-time on the related equipment. The problems faced in this connection and how they were solved is narrated. (M.G.B.)

Building Correlators with Many-Core Hardware

NARCIS (Netherlands)

van Nieuwpoort, R.V.

2010-01-01

Radio telescopes typically consist of multiple receivers whose signals are cross-correlated to filter out noise. A recent trend is to correlate in software instead of custom-built hardware, taking advantage of the flexibility that software solutions offer. Examples include e-VLBI and LOFAR. However,

Hardware and software maintenance strategies for upgrading vintage computers

International Nuclear Information System (INIS)

Wang, B.C.; Buijs, W.J.; Banting, R.D.

1992-01-01

The paper focuses on the maintenance of the computer hardware and software for digital control computers (DCC). Specific design and problems related to various maintenance strategies are reviewed. A foundation was required for a reliable computer maintenance and upgrading program to provide operation of the DCC with high availability and reliability for 40 years. This involved a carefully planned and executed maintenance and upgrading program, involving complementary hardware and software strategies. The computer system was designed on a modular basis, with large sections easily replaceable, to facilitate maintenance and improve availability of the system. Advances in computer hardware have made it possible to replace DCC peripheral devices with reliable, inexpensive, and widely available components from PC-based systems (PC = personal computer). By providing a high speed link from the DCC to a PC, it is now possible to use many commercial software packages to process data from the plant. 1 fig

GeMS: Gemini Mcao System: current status and commissioning plans

Science.gov (United States)

Boccas, Maxime; Rigaut, François; Gratadour, Damien; d'Orgeville, Céline; Bec, Matthieu; Daruich, Felipe; Perez, Gabriel; Arriagada, Gustavo; Bombino, Stacy; Carter, Chris; Cavedoni, Chas; Collao, Fabian; Collins, Paul; Diaz, Pablo; Ebbers, Angelic; Galvez, Ramon; Gausachs, Gaston; Hardash, Steve; James, Eric; Karewicz, Stan; Lazo, Manuel; Maltes, Diego; Mouser, Ron; Rogers, Rolando; Rojas, Roberto; Sheehan, Michael; Trancho, Gelys; Vergara, Vicente; Vucina, Tomislav

2008-07-01

The Gemini Multi-Conjugate Adaptive Optics project was launched in April 1999 to become the Gemini South AO facility in Chile. The system includes 5 laser guide stars, 3 natural guide stars and 3 deformable mirrors optically conjugated at 0, 4.5 and 9km to achieve near-uniform atmospheric compensation over a 1 arc minute square field of view. Sub-contracted systems with vendors were started as early as October 2001 and were all delivered by July 2007, but for the 50W laser (due around September 2008). The in-house development began in January 2006, and is expected to be completed by the end of 2008 to continue with integration and testing (I&T) on the telescope. The on-sky commissioning phase is scheduled to start during the first half of 2009. In this general overview, we will first describe the status of each subsystem with their major requirements, risk areas and achieved performance. Next we will present our plan to complete the project by reviewing the remaining steps through I&T and commissioning on the telescope, both during day-time and at night-time. Finally, we will summarize some management activities like schedules, resources and conclude with some lessons learned.

The completed Management Information System for the Monterey Navy Flying Club.

OpenAIRE

Graham, James M.

1987-01-01

Approved for public release; distribution in unlimited. This thesis provides a completed Management Information System for the Monterey Navy Flying Club. The software package was designed to operate upon an IBM PC-XT or PC-AT or 100% compatible microcomputer wjiich has 384K of main memory. Specific hardware requirements are discussed in chapter one. This software package supplies the necessary tools for the club manager to maintain all club records and generate required a...

The Danish Welfare Commission

DEFF Research Database (Denmark)

Gjerding, Allan Næs

2006-01-01

on public services, and install economic incentives for the behaviour of private households. The paper then digs into the proposals of the commission that are broadly grouped into five policy target areas con-cerning (1) the ageing of the population, (2) the incentives for labour market participation, (3......The paper deals with the main report of the Danish Welfare Commission and the one-hundred-and-nine proposals on the structure of the future Danish welfare state that the com-mission has put forward. Following upon a brief review of the discussion on the work of the Danish Welfare Commission......) competitiveness in the global economy, (4) behavioural regulation of the use of public bene-fits and services, and (5) management within tight budgets of an increasing demand on health and care. Finally, the concluding section sums up the discussion and elaborates on the debate on the Welfare Commission’s work...

Perceptions and misconceptions regarding the Joint Commission's view of quality monitoring.

Science.gov (United States)

Patterson, C H

1989-10-01

The Joint Commission recently has revised its hospital standards for infection control to reflect more accurately current state-of-the-art practices. In addition, the Joint Commission's Agenda for Change initiatives include the development of clinical indicators; one of the topics that will be included in those clinical indicator sets will be infection control. How the hospital chooses to organize itself to conduct the historically required monitoring and evaluation of clinical patient care currently required by the standards of the Joint Commission is at the option of the hospital. How the hospital will organize and collect data specific to infection control indicators yet to be developed by the Joint Commission has not been determined and will not be defined until specific research and development projects are completed. The hospital is expected to have in place infection prevention, surveillance, and control programs; it also is expected to have in place a quality assurance program that focuses not only on solving identified problems but also on the improvement of patient care quality. How the hospitals organize and/or integrate these activities is also at its option. It is expected that qualified professionals will direct and enforce infection prevention, surveillance, and control practices; indicators for infection control can provide data that will help assess the relative success of those practices and activities. The Joint Commission is not developing the capability to judge, on its own part, the actual quality of care provided by an organization seeking accreditation. Rather, the Joint Commission is committed to developing more accurate means to evaluate the structures, processes, and outcomes of diagnosis and treatment activities, as well as their interrelationships. Clinical excellence is supported by quality in the organizational environment and the managerial and leadership contexts within which patient care is delivered. Both clinical and

Open source hardware and software platform for robotics and artificial intelligence applications

Science.gov (United States)

Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

2016-02-01

Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

Open source hardware and software platform for robotics and artificial intelligence applications

International Nuclear Information System (INIS)

Liang, S Ng; Tan, K O; Clement, T H Lai; Ng, S K; Mohammed, A H Ali; Mailah, Musa; Yussof, Wan Azhar; Hamedon, Zamzuri; Yussof, Zulkifli

2016-01-01

Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots. (paper)

X-Window for process control in a mixed hardware environment

International Nuclear Information System (INIS)

Clausen, M.; Rehlich, K.

1992-01-01

X-Window is a common standard for display purposes on the current workstations. The possibility to create more than one window on a single screen enables the operators to gain more information about the process. Multiple windows from different control systems using mixed hardware is one of the problems this paper will describe. The experience shows that X-Window is a standard per definition, but not in any case. But it is an excellent tool to separate data-acquisition and display from each other over long distances using different types of hardware and software for communications and display. Our experience with X-Window displays for the cryogenic control system and the vacuum control system at HERA on DEC and SUN hardware will be described. (author)

Plutonium Protection System (PPS). Volume 2. Hardware description. Final report

International Nuclear Information System (INIS)

Miyoshi, D.S.

1979-05-01

The Plutonium Protection System (PPS) is an integrated safeguards system developed by Sandia Laboratories for the Department of Energy, Office of Safeguards and Security. The system is designed to demonstrate and test concepts for the improved safeguarding of plutonium. Volume 2 of the PPS final report describes the hardware elements of the system. The major areas containing hardware elements are the vault, where plutonium is stored, the packaging room, where plutonium is packaged into Container Modules, the Security Operations Center, which controls movement of personnel, the Material Accountability Center, which maintains the system data base, and the Material Operations Center, which monitors the operating procedures in the system. References are made to documents in which details of the hardware items can be found

Current trends in hardware and software for brain-computer interfaces (BCIs).

Science.gov (United States)

Brunner, P; Bianchi, L; Guger, C; Cincotti, F; Schalk, G

2011-04-01

A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

Current trends in hardware and software for brain-computer interfaces (BCIs)

Science.gov (United States)

Brunner, P.; Bianchi, L.; Guger, C.; Cincotti, F.; Schalk, G.

2011-04-01

A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

Tomographic image reconstruction and rendering with texture-mapping hardware

International Nuclear Information System (INIS)

Azevedo, S.G.; Cabral, B.K.; Foran, J.

1994-07-01

The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in numerous applications in medicine and industry. The most common algorithm used in these cases is filtered backprojection (FBP), which, while a simple procedure, is time-consuming for large images on any type of computational engine. Specially-designed, dedicated parallel processors are commonly used in medical CT scanners, whose results are then passed to graphics workstation for rendering and analysis. However, a fast direct FBP algorithm can be implemented on modern texture-mapping hardware in current high-end workstation platforms. This is done by casting the FBP algorithm as an image warping operation with summing. Texture-mapping hardware, such as that on the Silicon Graphics Reality Engine (TM), shows around 600 times speedup of backprojection over a CPU-based implementation (a 100 Mhz R4400 in this case). This technique has the further advantages of flexibility and rapid programming. In addition, the same hardware can be used for both image reconstruction and for volumetric rendering. The techniques can also be used to accelerate iterative reconstruction algorithms. The hardware architecture also allows more complex operations than straight-ray backprojection if they are required, including fan-beam, cone-beam, and curved ray paths, with little or no speed penalties

Hardware realization of an SVM algorithm implemented in FPGAs

Science.gov (United States)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Directory of Open Access Journals (Sweden)

Christos Ttofis

2012-01-01

Full Text Available Stereo correspondence is a popular algorithm for the extraction of depth information from a pair of rectified 2D images. Hence, it has been used in many computer vision applications that require knowledge about depth. However, stereo correspondence is a computationally intensive algorithm and requires high-end hardware resources in order to achieve real-time processing speed in embedded computer vision systems. This paper presents an overview of the use of edge information as a means to accelerate hardware implementations of stereo correspondence algorithms. The presented approach restricts the stereo correspondence algorithm only to the edges of the input images rather than to all image points, thus resulting in a considerable reduction of the search space. The paper highlights the benefits of the edge-directed approach by applying it to two stereo correspondence algorithms: an SAD-based fixed-support algorithm and a more complex adaptive support weight algorithm. Furthermore, we present design considerations about the implementation of these algorithms on reconfigurable hardware and also discuss issues related to the memory structures needed, the amount of parallelism that can be exploited, the organization of the processing blocks, and so forth. The two architectures (fixed-support based versus adaptive-support weight based are compared in terms of processing speed, disparity map accuracy, and hardware overheads, when both are implemented on a Virtex-5 FPGA platform.

11 CFR 116.7 - Debt settlement plans filed by terminating committees; Commission review.

Science.gov (United States)

2010-01-01

... description of the terms under which the creditor has extended credit to nonpolitical debtors of similar risk... settlement plan after the creditors included in the debt settlement plan have agreed to the settlement or... payments to the creditors included in the debt settlement plan until completion of Commission review. The...

Introduction to Hardware Security and Trust

CERN Document Server

Wang, Cliff

2012-01-01

The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

Atomic Energy Commission (Amendment) Law, 1993

International Nuclear Information System (INIS)

1993-02-01

The Atomic Energy Commission (Amendment) Law, 1993 (P.N.D.C.L. 308) seeks to amend the Atomic Energy Commission Act of 1963 (Act 204) so as to provide for the establishment of a Radiation Protection Board and other institutes under the Ghana Atomic Energy Commission. The Law further repeats the Atomic Energy Commission (Amendment) Law of 1982 (P.N.D.C.L. 37). (EAA)

First results with the immediate reconstructive strategy for internal hardware exposure in non-united fractures of the distal third of the leg: case series and literature review

Directory of Open Access Journals (Sweden)

Vaienti Luca

2012-08-01

Full Text Available Abstract Background Fractures of the distal third of the leg are increasingly common and are often handled by open reduction and internal fixation. Exposure and infection of internal hardware could occur, especially after high energy traumas, requiring hardware removal and delayed soft tissue reconstruction. Nevertheless immediate soft tissue reconstruction without internal hardware removal is still possible in selected patients. In this study the effectiveness and the complications of immediate soft tissue reconstruction without internal hardware removal is analyzed. Methods 13 patients, affected by internal hardware exposure in the distal leg, treated with immediate soft tissue reconstruction with pedicled flaps and hardware retention, are retrospectively analyzed, with special regard to flap survival and wound infection. Results Wound infection was observed in 10 cases before surgery and in 5 cases surgical debridement was necessary before reconstruction which was performed in a separate operative session. After reconstruction, wound dehiscence and infection occurred in 5 cases, and in 3 cases removal of internal hardware was necessary in order to achieve the complete healing of dehiscence. In one case the previous flap failed but prompt reconstruction with a sural fasciocutaneous flap was performed without hardware removal and without complications. Pre-operative infection and late reconstructive surgery are predictive for higher rates of post-operative complications (respectively p 0.018 and p 0.028. Conclusion Our approach achieved full recovery in 53.8% of the treated cases after one-step surgery, therefore reducing hospitalization and allowing early mobilization. Controlled trials are needed to confirm the effectiveness of this strategy, although the present case series shows encouraging results.

Utilizing IXP1200 hardware and software for packet filtering

OpenAIRE

Lindholm, Jeffery L.

2004-01-01

As network processors have advanced in speed and efficiency they have become more and more complex in both hardware and software configurations. Intel's IXP1200 is one of these new network processors that has been given to different universities worldwide to conduct research on. The goal of this thesis is to take the first step in starting that research by providing a stable system that can provide a reliable platform for further research. This thesis introduces the fundamental hardware of In...

The hardware control system for WEAVE at the William Herschel telescope

NARCIS (Netherlands)

Delgado Hernandez, Jose M.; Rodríguez-Ramos, Luis F.; Cano Infantes, Diego; Martin, Carlos; Bevil, Craige; Picó, Sergio; Dee, Kevin M.; Abrams, Don Carlos; Lewis, Ian J.; Pragt, Johan; Stuik, Remko; Tromp, Niels; Dalton, Gavin; L. Aguerri, J. Alfonso; Bonifacio, Piercarlo; Middleton, Kevin F.; Trager, Scott C.

This work describes the hardware control system of the Prime Focus Corrector (PFC) and the Spectrograph, two of the main parts of WEAVE, a multi-object fiber spectrograph for the WHT Telescope. The PFC and Spectrograph control system hardware is based on the Allen Bradley's Programmable Automation

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.

Science.gov (United States)

Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

2009-01-01

Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

Science.gov (United States)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

Bioethics commission to review gene patenting

Energy Technology Data Exchange (ETDEWEB)

Rothenburg, L.

1995-12-01

In October, in an unexpected development, U.S. President Bill Clinton created a national ethics advisory board, the National Bioethics Advisory Commission (NBAC, Washington, DC), to study both research ethics and the management and use of genetic information. Of particular interest to biotechnology companies and researchers is the fact that the commission`s brief encompasses issues about human gene patenting, a subject not contained in earlier proposals for the commission.

Complete BWR--EM LOCA analysis using the WRAP--EM system

International Nuclear Information System (INIS)

Beckmeyer, R.R.; Gregory, M.V.; Buckner, M.R.

1979-01-01

The Water Reactor Analysis Package, Evaluation Model (WRAP--EM), provides a complete analysis of postulated loss-of-coolant accidents (LOCA's) in light--water nuclear power reactors. The system is being developed at the Savannah River Laboratory (SRL) for use by the Nuclear Regulatory Commission (NRC) to interpret and evaluate reactor vendor, evaluation model (EM) analyses. The initial version of the WRAP--EM system for analysis of boiling water reactors (BWR's) is operational. To demonstrate the complete capability of the WRAP--BWR--EM system, a LOCA analysis has been performed for the Hope Creek Plant

Benchmarking Model Variants in Development of a Hardware-in-the-Loop Simulation System

Science.gov (United States)

Aretskin-Hariton, Eliot D.; Zinnecker, Alicia M.; Kratz, Jonathan L.; Culley, Dennis E.; Thomas, George L.

2016-01-01

Distributed engine control architecture presents a significant increase in complexity over traditional implementations when viewed from the perspective of system simulation and hardware design and test. Even if the overall function of the control scheme remains the same, the hardware implementation can have a significant effect on the overall system performance due to differences in the creation and flow of data between control elements. A Hardware-in-the-Loop (HIL) simulation system is under development at NASA Glenn Research Center that enables the exploration of these hardware dependent issues. The system is based on, but not limited to, the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k). This paper describes the step-by-step conversion from the self-contained baseline model to the hardware in the loop model, and the validation of each step. As the control model hardware fidelity was improved during HIL system development, benchmarking simulations were performed to verify that engine system performance characteristics remained the same. The results demonstrate the goal of the effort; the new HIL configurations have similar functionality and performance compared to the baseline C-MAPSS40k system.

Finishing and Commissioning the New Arecibo HF Facility

Science.gov (United States)

Sulzer, M. P.; Gonzalez, S. A.

2011-12-01

The imminent completion of the major tasks in the construction of the New Arecibo HF facility means that we must verify that the components are working as intended. The antenna system and the transmitters must be separately commissioned before they can be connected together so that we an be sure it will provide 83 dbW at 8.175 MHz, and 80 dbW at 5.1 MHz. The antenna system will be ready for initial testing in September. It Illuminates the 305 meter dish using dipoles near the surface of the dish transmitting upward to a wire mesh sub-reflector. There are three crossed dipoles for each of the two frequencies. The dipoles are supported on towers mounted on concrete pads underneath the dish. Each dipole element is connected to a transmitter through a three inch coax line. The tower foundations are nearly complete, and the towers will be erected in early September, and we expect to have at least one crossed dipole in place for initial testing by the end of September. We will need to make some measurements on the antenna system to ensure that it meets our requirements. One requirement is to match the antenna impedance to the transmission line and the transmitter closely enough to meet the transmitter specifications, the closer, the better. We have additional requirements; for example, it is necessary for efficient use of the facility that the polarization be close to circular. In most experiments, we want O mode excitation. If we were to transmit linear only half the power would reach the reflection height. The symmetry of the system assures that most of the conditions for achieving accurate circular polarization are met, but one condition is not: that exciting the transmitters driving the orthogonal elements at 90 degrees assures 90 degree separation in the corresponding antenna currents. One of the dipoles of each pair points toward the center of the array. If we think of the three crossed dipoles as consisting of a reference and two that are excited relative to it

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system

Directory of Open Access Journals (Sweden)

Daniel Brüderle

2009-06-01

Full Text Available Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Enabling Open Hardware through FOSS tools

CERN Multimedia

CERN. Geneva

2016-01-01

Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

Integrated conception of hardware/software mixed systems used in nuclear instrumentation

International Nuclear Information System (INIS)

Dias, Ailton F.; Sorel, Yves; Akil, Mohamed

2002-01-01

Hardware/software codesign carries out the design of systems composed by a hardware portion, with specific components, and a software portion, with microprocessor based architecture. This paper describes the Algorithm Architecture Adequation (AAA) design methodology - originally oriented to programmable multicomponent architectures, its extension to reconfigurable circuits and its application to design and development of nuclear instrumentation systems composed by programmable and configurable circuits. AAA methodology uses an unified model to describe algorithm, architecture and implementation, based on graph theory. The great advantage of AAA methodology is the utilization of a same model from the specification to the implementation of hardware/software systems, reducing the complexity and design time. (author)

The Lhc beam commissioning

International Nuclear Information System (INIS)

Redarelli, S.; Bailey, R.

2008-01-01

The plans for the Lhc proton beam commissioning are presented. A staged commissioning approach is proposed to satisfy the request of the Lhc experiments while minimizing the machine complexity in early commissioning phases. Machine protection and collimation aspects will be tackled progressively as the performance will be pushed to higher beam intensities. The key parameters are the number of bunches, k b , the proton intensity pe bunch, N, and the β in the various interaction points. All together these parameters determine the total beam power and the complexity of the machine. We will present the proposed trade off between the evolution of these parameters and the Lhc luminosity performance.

Development of a hardware-in-the-loop testbed to demonstrate multiple spacecraft operations in proximity

Science.gov (United States)

Eun, Youngho; Park, Sang-Young; Kim, Geuk-Nam

2018-06-01

This paper presents a new state-of-the-art ground-based hardware-in-the-loop test facility, which was developed to verify and demonstrate autonomous guidance, navigation, and control algorithms for space proximity operations and formation flying maneuvers. The test facility consists of two complete spaceflight simulators, an aluminum-based operational arena, and a set of infrared motion tracking cameras; thus, the testbed is capable of representing space activities under circumstances prevailing on the ground. The spaceflight simulators have a maximum of five-degree-of-freedom in a quasi-momentum-free environment, which is produced by a set of linear/hemispherical air-bearings and a horizontally leveled operational arena. The tracking system measures the real-time three-dimensional position and attitude to provide state variables to the agents. The design of the testbed is illustrated in detail for every element throughout the paper. The practical hardware characteristics of the active/passive measurement units and internal actuators are identified in detail from various perspectives. These experimental results support the successful development of the entire facility and enable us to implement and verify the spacecraft proximity operation strategy in the near future.

Patterns of Participation and Motivation in Folding@home: The Contribution of Hardware Enthusiasts and Overclockers

Directory of Open Access Journals (Sweden)

Vickie Curtis

2018-04-01

Full Text Available Folding@home is a distributed computing project in which participants run protein folding simulations on their computers. Participants complete work units and are awarded points for their contribution. An investigation into motivations to participate and patterns of participation revealed the significant contribution of a sub-community composed of individuals who custom-build computers to maximise their processing power. These individuals, known as “overclockers” or “hardware enthusiasts,” use distributed computing projects such as Folding@home to benchmark their modified computers and to compete with one another to see who can process the greatest number of project work units. Many are initially drawn to the project to learn about computer hardware from other overclockers and to compete for points. However, once they learn more about the scientific outputs of Folding@home, some participants become more motivated by the desire to contribute to scientific research. Overclockers form numerous online communities where members collaborate and help each other maximise their computing output. They invest heavily in their computers and process the majority of Folding@home’s simulations, thus providing an invaluable (and free resource.

Calculator: A Hardware Design, Math and Software Programming Project Base Learning

Directory of Open Access Journals (Sweden)

F. Criado

2015-03-01

Full Text Available This paper presents the implementation by the students of a complex calculator in hardware. This project meets hardware design goals, and also highly motivates them to use competences learned in others subjects. The learning process, associated to System Design, is hard enough because the students have to deal with parallel execution, signal delay, synchronization … Then, to strengthen the knowledge of hardware design a methodology as project based learning (PBL is proposed. Moreover, it is also used to reinforce cross subjects like math and software programming. This methodology creates a course dynamics that is closer to a professional environment where they will work with software and mathematics to resolve the hardware design problems. The students design from zero the functionality of the calculator. They are who make the decisions about the math operations that it is able to resolve it, and also the operands format or how to introduce a complex equation into the calculator. This will increase the student intrinsic motivation. In addition, since the choices may have consequences on the reliability of the calculator, students are encouraged to program in software the decisions about how implement the selected mathematical algorithm. Although math and hardware design are two tough subjects for students, the perception that they get at the end of the course is quite positive.

Commissioning of the ion beam buncher and cooler for LEBIT

Energy Technology Data Exchange (ETDEWEB)

Sun, T.; Bollen, G.; Ringle, R.; Schury, P. [Michigan State University, NSCL, East Lansing, MI (United States); Michigan State University, Department of Physics and Astronomy, East Lansing, MI (United States); Schwarz, S.; Lawton, D. [Michigan State University, NSCL, East Lansing, MI (United States)

2005-09-01

A radiofrequency-quadrupole ion accumulator and buncher has been set-up for the low-energy-beam and ion-trap (LEBIT) facility, which is in its final commissioning phase at the NSCL/MSU. The buncher is a cryogenic system with separated cooling and accumulation stages, optimized for excellent beam quality and high performance. The completed set-up of the LEBIT ion buncher is presented as well as first experimental results on pulse forming and beam properties. (orig.)

Commissioning of the ion beam buncher and cooler for LEBIT

International Nuclear Information System (INIS)

Sun, T.; Bollen, G.; Ringle, R.; Schury, P.; Schwarz, S.; Lawton, D.

2005-01-01

A radiofrequency-quadrupole ion accumulator and buncher has been set-up for the low-energy-beam and ion-trap (LEBIT) facility, which is in its final commissioning phase at the NSCL/MSU. The buncher is a cryogenic system with separated cooling and accumulation stages, optimized for excellent beam quality and high performance. The completed set-up of the LEBIT ion buncher is presented as well as first experimental results on pulse forming and beam properties. (orig.)

MORPION: a fast hardware processor for straight line finding in MWPC

International Nuclear Information System (INIS)

Mur, M.

1980-02-01

A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

77 FR 22573 - Information Collections Being Reviewed by the Federal Communications Commission Under Delegated...

Science.gov (United States)

2012-04-16

.... Privacy Impact Assessment(s): No impact(s). Nature and Extent of Confidentiality: There is no need for... to notify the Commission in writing when the station commences operation. Such notification shall be... time to complete construction of the station and commence operation shall request an extension of time...

Commission of economical affairs, environment and territory. Report no. 51; Commission des affaires economiques, de l'environnement et du territoire. Compte rendu no. 51

Energy Technology Data Exchange (ETDEWEB)

NONE

2004-05-01

The aim of this report is to present to the French deputies the comments made by the commission of economic affairs, environment and territory about the project of energy trend law. This law aims at defining in its first article the goals and trends of the French energy policy, and then at completing the existing energy dispositions in order to more efficiently implement these trends. The first title of the law is devoted to the mastery of energy demand and foresee the implementation of a system of energy saving certificates, the reinforcement of the thermal building codes law and a better information of consumers. The second title aims at promoting the development of renewable energy sources. The first part of this report summarizes the general comments made by the commission while the second part makes a detailed examination of each article of the law project. (J.S.)

Environmental Control System Software & Hardware Development

Science.gov (United States)

Vargas, Daniel Eduardo

2017-01-01

ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

Total knee arthroplasty using patient-specific blocks after prior femoral fracture without hardware removal

Directory of Open Access Journals (Sweden)

Raju Vaishya

2018-01-01

Full Text Available Background: The options to perform total knee arthroplasty (TKA with retained hardware in femur are mainly – removal of hardware, use of extramedullary guide, or computer-assisted surgery. Patient-specific blocks (PSBs have been introduced with many potential advantages, but their use in retained hardware has not been adequately explored. The purpose of the present study was to outline and assess the usefulness of the PSBs in performing TKA in patients with retained femoral hardware. Materials and Materials and Methods: Nine patients with retained femoral hardware underwent TKA using PSBs. All the surgeries were performed by the same surgeon using same implants. Nine cases (7 males and 2 females out of total of 120 primary TKA had retained hardware. The average age of the patients was 60.55 years. The retained hardware were 6 patients with nails, 2 with plates and one patient had screws. Out of the nine cases, only one patient needed removal of a screw which was hindering placement of pin for the PSB. Results: All the patients had significant improvement in their Knee Society Score (KSS which improved from 47.0 to postoperative KSS of 86.77 (P < 0.00. The mechanical axis was significantly improved (P < 0.03 after surgery. No patient required blood transfusion and the average tourniquet time was 41 min. Conclusion: TKA using PSBs is useful and can be used in patients with retained hardware with good functional and radiological outcome.

Event management for large scale event-driven digital hardware spiking neural networks.

Science.gov (United States)

Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

2013-09-01

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

Hardware-assisted software clock synchronization for homogeneous distributed systems

Science.gov (United States)

Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

1990-01-01

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Review report: safety and reliability issues on digital instrumentation and control systems in nuclear power plants and United States Nuclear Regulatory Commission`s dispositions

Energy Technology Data Exchange (ETDEWEB)

Watanabe, Norio; Suzudo, Tomoaki [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment

1998-09-01

Recently, digital instrumentation and control (I and C) systems have been applied to nuclear power plants (NPPs) in various countries. Introduction of digital I and C systems, however, raises special issues on design, implementation, safety and licensing. Since FY 1997, the Japan Atomic Energy Research Institute (JAERI) has been carrying out a project, Study on Reliability of Digital I and C Systems, which includes extensive reviews of design approaches, technical standards, regulatory processes, especially, in the United States. This report summarizes the results from the study of National Research Council (NRC) and the U.S. Nuclear Regulatory Commission`s (USNRC`s) responses to the recommendations made by the NRC`s study. That study identified six technical key issues (system aspects of digital I and C technology, software quality assurance, common-mode software failure potential, safety and reliability assessment methods, human factors and man-machine interface, dedication of commercial off-the-shelf hardware and software) and two strategic key issues (case-by-case licensing process, adequacy of technical infrastructure) that arise from the introduction of digital I and C technology and then, made recommendations to the USNRC for coping with digital I and C applications. The USNRC responded to each recommendation and showed their own dispositions in which the USNRC agreed with most of the recommendations. In Japan, it is expected that introduction of digital I and C technology is inevitable in NPPs because the vendors are gradually discontinuing support and stocking of analog components. To cope with such situations, there is a need to develop and update the standards and guidelines applicable to digital I and C technology. The key issues and the USNRC`s dispositions provided in this report is believed to be useful for developing and updating them. (J.P.N.)

Compact Modbus TCP/IP protocol for data acquisition systems based on limited hardware resources

Science.gov (United States)

Bai, Q.; Jin, B.; Wang, D.; Wang, Y.; Liu, X.

2018-04-01

The Modbus TCP/IP has been a standard industry communication protocol and widely utilized for establishing sensor-cloud platforms on the Internet. However, numerous existing data acquisition systems built on traditional single-chip microcontrollers without sufficient resources cannot support it, because the complete Modbus TCP/IP protocol always works dependent on a full operating system which occupies abundant hardware resources. Hence, a compact Modbus TCP/IP protocol is proposed in this work to make it run efficiently and stably even on a resource-limited hardware platform. Firstly, the Modbus TCP/IP protocol stack is analyzed and the refined protocol suite is rebuilt by streamlining the typical TCP/IP suite. Then, specific implementation of every hierarchical layer is respectively presented in detail according to the protocol structure. Besides, the compact protocol is implemented in a traditional microprocessor to validate the feasibility of the scheme. Finally, the performance of the proposed scenario is assessed. The experimental results demonstrate that message packets match the frame format of Modbus TCP/IP protocol and the average bandwidth reaches to 1.15 Mbps. The compact protocol operates stably even based on a traditional microcontroller with only 4-kB RAM and 12-MHz system clock, and no communication congestion or frequent packet loss occurs.

Nuclear Regulatory Commission 1989 Information Digest

International Nuclear Information System (INIS)

1989-03-01

The Nuclear Regulatory Commission 1989 Information Digest provides summary information regarding the US Nuclear Regulatory Commission, its regulatory responsibilities, and areas licensed by the Commission. This is the first of an annual publication for the general use of the NRC staff and is available to the public. The Digest is divided into two parts: the first presents an overview of the US Nuclear Regulatory Commission and the second provides data on NRC commercial nuclear reactor licensees and commercial nuclear power reactors worldwide

Hardware availability calculations and results of the IFMIF accelerator facility

International Nuclear Information System (INIS)

Bargalló, Enric; Arroyo, Jose Manuel; Abal, Javier; Beauvais, Pierre-Yves; Gobin, Raphael; Orsini, Fabienne; Weber, Moisés; Podadera, Ivan; Grespan, Francesco; Fagotti, Enrico; De Blas, Alfredo; Dies, Javier; Tapia, Carlos; Mollá, Joaquín; Ibarra, Ángel

2014-01-01

Highlights: • IFMIF accelerator facility hardware availability analyses methodology is described. • Results of the individual hardware availability analyses are shown for the reference design. • Accelerator design improvements are proposed for each system. • Availability results are evaluated and compared with the requirements. - Abstract: Hardware availability calculations have been done individually for each system of the deuteron accelerators of the International Fusion Materials Irradiation Facility (IFMIF). The principal goal of these analyses is to estimate the availability of the systems, compare it with the challenging IFMIF requirements and find new paths to improve availability performances. Major unavailability contributors are highlighted and possible design changes are proposed in order to achieve the hardware availability requirements established for each system. In this paper, such possible improvements are implemented in fault tree models and the availability results are evaluated. The parallel activity on the design and construction of the linear IFMIF prototype accelerator (LIPAc) provides detailed design information for the RAMI (reliability, availability, maintainability and inspectability) analyses and allows finding out the improvements that the final accelerator could have. Because of the R and D behavior of the LIPAc, RAMI improvements could be the major differences between the prototype and the IFMIF accelerator design

Hardware availability calculations and results of the IFMIF accelerator facility

Energy Technology Data Exchange (ETDEWEB)

Bargalló, Enric, E-mail: enric.bargallo-font@upc.edu [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Arroyo, Jose Manuel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Abal, Javier [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Beauvais, Pierre-Yves; Gobin, Raphael; Orsini, Fabienne [Commissariat à l’Energie Atomique, Saclay (France); Weber, Moisés; Podadera, Ivan [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Grespan, Francesco; Fagotti, Enrico [Istituto Nazionale di Fisica Nucleare, Legnaro (Italy); De Blas, Alfredo; Dies, Javier; Tapia, Carlos [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Mollá, Joaquín; Ibarra, Ángel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain)

2014-10-15

Highlights: • IFMIF accelerator facility hardware availability analyses methodology is described. • Results of the individual hardware availability analyses are shown for the reference design. • Accelerator design improvements are proposed for each system. • Availability results are evaluated and compared with the requirements. - Abstract: Hardware availability calculations have been done individually for each system of the deuteron accelerators of the International Fusion Materials Irradiation Facility (IFMIF). The principal goal of these analyses is to estimate the availability of the systems, compare it with the challenging IFMIF requirements and find new paths to improve availability performances. Major unavailability contributors are highlighted and possible design changes are proposed in order to achieve the hardware availability requirements established for each system. In this paper, such possible improvements are implemented in fault tree models and the availability results are evaluated. The parallel activity on the design and construction of the linear IFMIF prototype accelerator (LIPAc) provides detailed design information for the RAMI (reliability, availability, maintainability and inspectability) analyses and allows finding out the improvements that the final accelerator could have. Because of the R and D behavior of the LIPAc, RAMI improvements could be the major differences between the prototype and the IFMIF accelerator design.

Advanced hardware design for error correcting codes

CERN Document Server

Coussy, Philippe

2015-01-01

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

Computer hardware for radiologists: Part 2

International Nuclear Information System (INIS)

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future

Computer hardware for radiologists: Part 2

Directory of Open Access Journals (Sweden)

Indrajit I

2010-01-01

Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

Hardwares e sistemas multiagente: um estudo sobre arquiteturas híbridas

Directory of Open Access Journals (Sweden)

Rafhael Rodrigues Cunha

2015-05-01

Full Text Available Este artigo apresenta três estudos de caso sobre a aplicabilidade de arquiteturas de hardware reconfiguráveis, como FPGA, voltadas à utilização em sistemas multiagentes. Feita uma análise visando à elucidação dos resultados e das contribuições que os estudos proporcionaram aos autores, observa-se que o desenvolvimento de sistemas inteligentes depende cada vez mais de uma programação que explore o hardware ao máximo. Esse desfecho torna o uso de hardwares reconfiguráveis o mais aconselhável quando problemas computacionais complexos demandam respostas rápidas e eficientes, como nos casos estudados.

Readiness evaluation report -- High-exposure rate hardware removal resumption of activities

International Nuclear Information System (INIS)

Volkman, C.L.

1996-11-01

In August 1996, N Basin Project Management proactively ceased activities in the N Basin after noting several radiological control anomalies occurring during the performance of the high exposure rate hardware removal activity. The HERH is one of several activities that will be accomplished to complete deactivation of N Basin. Three project critiques were performed to identify causes and several corrective actions were identified. To ensure the true causes of the events were identified the N Basin Project Manager requested that a root cause analysis be performed for the events covered by the three critiques. The intent was to identify recurring events and evaluate the effectiveness of corrective action implementation. These three review elements were used by the project to develop a corrective action plan (CAP) which consisted of both project unique and programmatic items. The N Basin Project is using this BHI Readiness Evaluation (RE) process as a mechanism to independently verify that corrective actions identified from the CAP have been completed and that no changes have been made during the stand down that affect the resumption of the HERH activities. A readiness evaluation (RE) plan (Attachment 3) was prepared. The completed Readiness Evaluation Records which documents the results of the team member evaluations are in attachment 1. The independent readiness evaluation team identified 5 deficiencies of which two are post startup and three are pre startup. All deficiencies are in the area of training. These findings are explained in detail in Attachment 2

Accelerator Technology: Injection and Extraction Related Hardware: Kickers and Septa

CERN Document Server

Barnes, M J; Mertens, V

2013-01-01

This document is part of Subvolume C 'Accelerators and Colliders' of Volume 21 'Elementary Particles' of Landolt-Börnstein - Group I 'Elementary Particles, Nuclei and Atoms'. It contains the the Section '8.7 Injection and Extraction Related Hardware: Kickers and Septa' of the Chapter '8 Accelerator Technology' with the content: 8.7 Injection and Extraction Related Hardware: Kickers and Septa 8.7.1 Fast Pulsed Systems (Kickers) 8.7.2 Electrostatic and Magnetic Septa

Testing Microgravity Flight Hardware Concepts on the NASA KC-135

Science.gov (United States)

Motil, Susan M.; Harrivel, Angela R.; Zimmerli, Gregory A.

2001-01-01

This paper provides an overview of utilizing the NASA KC-135 Reduced Gravity Aircraft for the Foam Optics and Mechanics (FOAM) microgravity flight project. The FOAM science requirements are summarized, and the KC-135 test-rig used to test hardware concepts designed to meet the requirements are described. Preliminary results regarding foam dispensing, foam/surface slip tests, and dynamic light scattering data are discussed in support of the flight hardware development for the FOAM experiment.

Hardware control system using modular software under RSX-11D

International Nuclear Information System (INIS)

Kittell, R.S.; Helland, J.A.

1978-01-01

A modular software system used to control extensive hardware is described. The development, operation, and experience with this software are discussed. Included are the methods employed to implement this system while taking advantage of the Real-Time features of RSX-11D. Comparisons are made between this system and an earlier nonmodular system. The controlled hardware includes magnet power supplies, stepping motors, DVM's, and multiplexors, and is interfaced through CAMAC. 4 figures

ARM assembly language with hardware experiments

CERN Document Server

Elahi, Ata

2015-01-01

This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

Science.gov (United States)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

77 FR 36178 - Carriage of Digital Television Broadcast Signals: Amendment to the Commission's Rules

Science.gov (United States)

2012-06-18

...-0432 (TTY). I. Introduction 1. With this Fifth Report and Order (Fifth R&O) in the DTV cable carriage... time after completion of the DTV transition.\\8\\ Some operators may choose to deliver programming in... certain percentage of their analog channel's programming on their DTV channel), and the Commission decided...

Secure Hardware Performance Analysis in Virtualized Cloud Environment

Directory of Open Access Journals (Sweden)

Chee-Heng Tan

2013-01-01

Full Text Available The main obstacle in mass adoption of cloud computing for database operations is the data security issue. In this paper, it is shown that IT services particularly in hardware performance evaluation in virtual machine can be accomplished effectively without IT personnel gaining access to real data for diagnostic and remediation purposes. The proposed mechanisms utilized TPC-H benchmark to achieve 2 objectives. First, the underlying hardware performance and consistency is supervised via a control system, which is constructed using a combination of TPC-H queries, linear regression, and machine learning techniques. Second, linear programming techniques are employed to provide input to the algorithms that construct stress-testing scenarios in the virtual machine, using the combination of TPC-H queries. These stress-testing scenarios serve 2 purposes. They provide the boundary resource threshold verification to the first control system, so that periodic training of the synthetic data sets for performance evaluation is not constrained by hardware inadequacy, particularly when the resources in the virtual machine are scaled up or down which results in the change of the utilization threshold. Secondly, they provide a platform for response time verification on critical transactions, so that the expected Quality of Service (QoS from these transactions is assured.

Hardware design of the median filter based on window structure and batcher′s oddeven sort network

Directory of Open Access Journals (Sweden)

SUN Kaimin

2013-06-01

Full Text Available Area and speed are two important factors to be considered in designing Median Filter with digital circuits.Area consideration requires the use of logical resources as little as possible,while speed consideration requires the system capable of working on higher clock frequencies,with as few clock cycles as possible to complete a frame filtering or real time filtering.This paper gives a new design of Median Filter,the hardware structure of which is a 3×3 window structure with two buffers.The filter function module is based on Batcher′s Odd-Even Sort network theory.Structural design is implemented in FPGA,verified by ModelSim software and realizes video image filtering.The experimental analysis shows that this new structure of Median Filter effectively decreases logical resources (merely using 741 Logic Elements,and accelerates the pixel processing speed up to 27MHz.This filter achieves realtime processing of video images of 30 frames/s.This design not only has a certain practicality,but also provides a reference for the hardware structure design ideas in digital image processing.

2D neural hardware versus 3D biological ones

Energy Technology Data Exchange (ETDEWEB)

Beiu, V.

1998-12-31

This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

Commissioning of the LHC Cryogenic System Subsystems Cold Commissioning in Preparation of Full Sector Tests

CERN Document Server

Serio, L; Ferlin, G; Gilbert, N; Gruehagen, Henning; Knoops, S; Parente, C; Sanmartí, M

2006-01-01

The cryogenic system for the Large Hadron Collider accelerator is presently in its final phase of installation and commissioning at nominal operating temperatures. The refrigeration capacity for the LHC will be produced using eight large cryogenic plants installed on five technical sites and distributed around the 26.7-km circumference ring located in a deep underground tunnel. The status of the cryogenic system commissioning is presented together with the experience gained in operating and commissioning it.

Performance/price estimates for cortex-scale hardware: a design space exploration.

Science.gov (United States)

Zaveri, Mazad S; Hammerstrom, Dan

2011-04-01

In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering. Copyright © 2010 Elsevier Ltd. All rights reserved.

Commissioning plans for SSC linac

International Nuclear Information System (INIS)

Hurd, J.W.; Aprile, R.L.; Chang, C.R.; Crist, C.E.; Cutler, R.I.; Funk, L.W.; Guy, F.W.; Leifeste, G.T.; Raparia, D.; Saadatmand, K.; Sethi, R.C.; Swenson, D.A.; Tooker, J.; Yao, C.G.

1992-01-01

Presented are the general description of the SSC linac and the plans for commissioning. Sections of the linac are installed, tested, and beam commissioned in a serial approach. A specialized set of diagnostics is used to characterize the beam through each section. In addition to the standard diagnostic set, plans call for the use of a bunch shape monitor and x-ray spectrometer. Streak camera and digital imaging diagnostics will be developed. The commissioning plan is folded into the general linac project schedule to show the relation between delivery, staging, installation, conditioning, and actual commissioning with beam. These plans form the basis for coordination between the various organizations responsible for different elements of the linac including the technical components, infrastructure, and temporary staging and operation facilities. (Author) 2 figs., 17 refs

Design of a Hardware-Implemented Phase Calculating System for Feedback Control in the LHCD Experiments on EAST

International Nuclear Information System (INIS)

Liu Qiang; Liang Hao; Zhou Yongzhao

2009-01-01

A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array (FPGA) chips with embedded digital signal processing (DSP) cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave (LHW) system on EAST. (fusion engineering)

17 CFR 201.57 - Commission review.

Science.gov (United States)

2010-04-01

... 17 Commodity and Securities Exchanges 2 2010-04-01 2010-04-01 false Commission review. 201.57... Regulations Pertaining to the Equal Access to Justice Act § 201.57 Commission review. In accordance with the... Division of the Commission may seek review of the initial decision on the fee application, or the...

A photovoltaic source I/U model suitable for hardware in the loop application

Directory of Open Access Journals (Sweden)

Stala Robert

2017-12-01

Full Text Available This paper presents a novel, low-complexity method of simulating PV source characteristics suitable for real-time modeling and hardware implementation. The application of the suitable model of the PV source as well as the model of all the PV system components in a real-time hardware gives a safe, fast and low cost method of testing PV systems. The paper demonstrates the concept of the PV array model and the hardware implementation in FPGAs of the system which combines two PV arrays. The obtained results confirm that the proposed model is of low complexity and can be suitable for hardware in the loop (HIL tests of the complex PV system control, with various arrays operating under different conditions.

Commissioning of ATLAS

CERN Document Server

Thomas, J

2008-01-01

The status of the commissioning of the ATLAS experiment as of May 2008 is presented. The subdetector integration in recent milestone weeks is described, especially the cosmic commissioning in milestone week M6, focussing on combined running and track analysis of the muon detector and inner detector. The liquid argon and tile calorimeters have achieved near-full operation, and are integrated with the calorimeter trigger. The High-Level-Trigger infrastructure is installed and algorithms tested in technical runs. Problems with the inner detector cooling compressors are being fixed.

ATF2 Commissioning

Energy Technology Data Exchange (ETDEWEB)

Seryi, A.; /SLAC; Christian, G.; /KLTE-ATOMKI; Parker, B.; /BNL; Schulte, D.; Delahaye, J.-P.; Tomas, R.; Zimmermann, F.; /CERN; Wolski, A.; Elsen, E.; /Cockcroft Inst. /DESY; Sanuki, T.; /Tohoku U.; Gianfelice-Wendt, E.; Ross, M.; Wendt, M.; /Fermilab; Takahashi, T.; /Hiroshima U.; Bai, S.; Gao, J.; /Beijing, Inst. High Energy Phys.; Bolzon, B.; Geffroy, N.; Jeremie, A.; /Annecy, LAPP; Apsimon, R.; Burrows, P.; /Oxford U., JAI /Kyoto U., Inst. Chem. Res. /Kyungpook Natl. U. /Orsay, LAL /Phang Accelerator Lab /Royal Holloway, U. of London /SLAC /Daresbury /University Coll. London /Manchester U. /Univ. of Tokyo U.

2009-10-30

ATF2 is a final-focus test beam line that aims to focus the low-emittance beam from the ATF damping ring to a beam size of about 37 nm, and at the same time to demonstrate nm beam stability, using numerous advanced beam diagnostics and feedback tools. The construction has been finished at the end of 2008 and the beam commissioning of ATF2 has started in December of 2008. ATF2 is constructed and commissioned by ATF international collaborations with strong US, Asian and European participation.

ATF2 COMMISSIONING

CERN Document Server

Seryi, A; Parker, B; Schulte, D; Delahaye, J P; Tomas, R; Zimmermann, F; Wolski, A; Elsen, E; Sanuki, T; Gianfelice-Wendt, E; Ross, M; Wendt, M; Takahashi, T; Bai, S; Gao, J; Bolzon, B; Geffroy, N; Jeremie, A; Apsimon, R; Burrows, P; Constance, B; Perry, C; Resta-Lopez, J; Swinson, C; Araki, S; Aryshev, A; Hayano, H; Honda, Y; Kubo, K; Kume, T; Kuroda, S; Masuzawa, M; Naito, T; Okugi, T; Sugahara, R; Tauchi, T; Terunuma, N; Urakawa, J; Yokoya, K; Iwashita, Y; Sugimoto, T; Heo, A Y; Kim, E S; Kim, H S; Bambade, P; Renier, Y; Rimbault, C; Huang, J Y; Kim, S H; Park, Y J; Hwang, W H; Blair, G; Boogert, S; Karataev, P; Molloy, S; Amann, J; Bellomo, P; Lam, B; McCormick, D; Nelson, J; Paterson, E; Pivi, M; Raubenheimer, T; Spencer, C; Wang, M H; White, G; Wittmer, W; Woodley, M; Yan, Y; Zhou, F; Angal-Kalinin, D; Jones, J; Lyapin, A; Scarfe, A; Kamiya, Y; Komamiya, S; Oroku, M; Suehara, T; Yamanaka, T

2010-01-01

ATF2 is a final-focus test beam line that aims to focus the low-emittance beam from the ATF damping ring to a beam size of about 37 nm, and at the same time to demonstrate nm beam stability, using numerous advanced beam diagnostics and feedback tools. The construction has been finished at the end of 2008 and the beam commissioning of ATF2 has started in December of 2008. ATF2 is constructed and commissioned by ATF international collaborations with strong US, Asian and European participation.

Joint Commission

Science.gov (United States)

... for the latest publication of The Joint Commission Journal on Quality and Patient Safety (JQPS). . How We Work Process improvement program breeds quality culture, empowers staff An article in Quality Progress, June ...

The status of recommendations of the President's Commission on the accident at Three Mile Island: A ten-year review

International Nuclear Information System (INIS)

1989-03-01

This report summarizes the status of actions taken by the US Nuclear Regulatory Commission (NRC) in response to recommendations made by the Presidential Commission on the Accident at Three Mile Island in the 10 years since the accident occurred in March 1979. It also updates NRC's initial response to the Presidential Commission's recommendations contained in ''NRC Views and Analysis of the Recommendations of the President's Commission of the Accident at Three Mile Island'' (NUREG-0632), issued in November 1979. The status of ongoing initiatives for actions not yet complete is also reported for reference purposes. On the basis of its analysis of NRC and the industry, the Presidential Commission found many then-current practices inadequate and in need of improvement. As a result of its recommendations and of guidance from other studies, substantial changes have been made in the 10 years since the accident. This report reflects how, based on Presidential Commission recommendations and continued work, revised practices and standards are now being implemented by NRC and throughout the industry

Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

Science.gov (United States)

Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

2013-01-01

This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

Hardware detection and parameter tuning method for speed control system of PMSM

Science.gov (United States)

Song, Zhengqiang; Yang, Huiling

2018-03-01

In this paper, the development of permanent magnet synchronous motor AC speed control system is taken as an example, aiming to expound the principle and parameter setting method of the system hardware, and puts forward the method of using software or hardware to eliminate the problem.

National Bioethics Commissions as Educators.

Science.gov (United States)

Lee, Lisa M

2017-05-01

As has become tradition, executive directors of United States' presidential bioethics committees offer reflections about their experience shortly after the orderly shutdown of the commission staff. After the records are filed according to government records regulations; after all the staff members, who are hired into temporary positions that must be renewed every two years, have secured permanent employment; after preparations are made to ensure that the next commission staff (should there be one) has a budget and standard operating procedures in order to begin its work in a timely manner; after the lights are turned out for the last time, the executive director makes the final climb up the stairs into the sunlight and reflects on the whirlwind. There is much about my work with the Presidential Commission for the Study of Bioethical Issues that deserves comment, but one aspect of the commission that has been especially valuable to me is its work to educate the nation on bioethical issues. This is, moreover, a contribution in which the commission staff was central, and it is one that, as an ethics educator myself, I will cherish deeply. © 2017 The Hastings Center.

Open Source Hardware for DIY Environmental Sensing

Science.gov (United States)

Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

2014-12-01

The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

Successful Completion of the Top-off Upgrade of the Advanced Light Source

International Nuclear Information System (INIS)

Steier, C.; Bailey, B.; Baptiste, K.; Barry, W.; Biocca, A.; Byrne, W.; Casey, P.; Chin, M.; Donahue, R.; Duarte, R.; Fahmie, M.; Gath, B.; Jacobson, S.; Julian, J.; Jung, J.Y.; Kritscher, M.; Kwiatkowski, S.; Marks, S.; McKean, P.; Mueller, R.; Nishimura, H.; ONeill, J.; Portmann, G.; Prestemon, S.; Robin, D.; Rossi, S.; Sannibale, F.; Scarvie, T.; Schlueter, R.; Shuman, D.; Smith-Baumann, A.; Stover, G.; Timossi, C.; Wan, W.; Warwick, T.; Wells, R.; Weber, J.; Williams, E.

2010-01-01

An upgrade of the Advanced Light Source to enable top-off operation has been completed during the last four years. The final work centered around radiation safety aspects, culminating in a systematic proof that top-off operation is equally safe as decaying beam operation. Commissioning and transition to full user operations happened in late 2008 and early 2009. Top-off operation at the ALS provides a very large increase in time-averaged brightness (by about a factor of 10) as well as improvements in beam stability. The following sections provide an overview of the radiation safety rationale, commissioning results, as well as experience in user operations.

Commissioning of the nuclear power plant

International Nuclear Information System (INIS)

Furtado, P.M.; Rolf, F.

1984-01-01

Nuclear Power Plant Angra 2, located at Itaorna Beach-Angra dos Reis is the first plant of the Brazilian-German Agreement to be commissioned. The Nuclear Power Plant is a pressurized water reactor rated at 3765 Mw thermal/1325 Mw electrical. For commissioning purpose the plant is divided into 110 systems. Plant commissioning objective is to demonstrate the safe and correct operation of each plan component, system and of the whole plant in agreement with design conditions, licensing requirements and contractual obligations. This work gives a description of plant commissioning objectives, activities their time sequence, and documentation. (Author) [pt

Molr - A delegation framework for accelerator commissioning

CERN Document Server

Valliappan, Nachiappan

2017-01-01

Accelerator commissioning is the process of preparing an accelerator for beam operations. A typical commissioning period at CERN involves running thousands of tests on many complex systems and machinery to ensure smooth beam operations and correct functioning of the machine protection systems. AccTesting is a software framework which helps orchestrate the commissioning of CERN’s accelerators and it’s equipment systems. This involves running and managing tests provided by various commissioning tools and analyzing their outcomes. Currently, AccTesting only supports a specific set of commissioning tools. In this project, we aim to widen the spectrum of commissioning tools supported by AccTesting by developing a generic and programmable integration framework called Molr, which would enable the integration of more commissioning tools with AccTesting. In this report, we summarize the work done during the summer student project and lay out a brief overview of the current status and next steps for Molr.

Design of hardware accelerators for demanding applications.

NARCIS (Netherlands)

Jozwiak, L.; Jan, Y.

2010-01-01

This paper focuses on mastering the architecture development of hardware accelerators. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for modern demanding applications, when using as an example the accelerator design for LDPC decoding

Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

CERN Document Server

Simpson, Robert J

1987-01-01

Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

CAMAC high energy physics electronics hardware

International Nuclear Information System (INIS)

Kolpakov, I.F.

1977-01-01

CAMAC hardware for high energy physics large spectrometers and control systems is reviewed as is the development of CAMAC modules at the High Energy Laboratory, JINR (Dubna). The total number of crates used at the Laboratory is 179. The number of CAMAC modules of 120 different types exceeds 1700. The principles of organization and the structure of developed CAMAC systems are described. (author)

The Industry Commission inquiry into charitable organisations.

Science.gov (United States)

Suter, K

1996-01-01

The Industry Commission has carried out Australia's largest inquiry into charities. It was, from the point of view of charities, an unsatisfactory operation, all the more so since it was not clear why the task had been given to the commission. This article examines the commission's work in three ways: the overall relationship between government and charities; the commission's proposed major reforms; and the minor reforms.

Measurement and evaluation systems for NPP commissioning

International Nuclear Information System (INIS)

Elko, Marek

2006-01-01

Standard core monitoring and information systems are designed with an emphasis on normal operation of nuclear power plant. Their purpose is to provide necessary support for reactor operators and other operating personnel during the fuel cycle. After each fuel reloading, and to the larger extent during the plant commissioning, a variety of start-up tests need to be carried out and evaluated. Sampling periods, accuracy and communication delays of standard systems are not always suitable for test performance and evaluation. For technical and safety reasons, the access to standard monitoring and information systems is very limited. Non-Standard Measurement and Evaluation Systems are highly specialized devices designed with an emphasis on start-up tests performance and evaluation. They are capable of high frequency sampling, processing and communication of hundreds of technological signals with required accuracy and low communication delay. All technological signals needed for the test performance and evaluation are collected from various systems, concentrated in one system and fully accessible to a test leader, a reactor physicist or other users. In addition, Non-Standard Measurement and Evaluation Systems can perform other tasks like data storing and presentation, data distribution to other systems or external computers via network, reactivity calculations, etc. Structure of such systems can vary, but generally it is a mixture of two basic concepts: a mobile system and a stationary system. A basic description of hardware structure and software equipment of Non-Standard Measurement and Evaluation Systems is given in the paper (Authors)

Nuclear Regulatory Commission issuances, October 1993

International Nuclear Information System (INIS)

1993-10-01

This document contains a Commission issuance in which the Commission denies the petitioners' motion to quash or modify a subpoena issued by the NRC staff in the course of an investigation to determine if the petitioners' have violated NRC regulations and to determine if safety-related problems exist at NRC-licensed facilities. The pertinent regulations and the Commission's Memorandum and Order are included

Commission 1

African Journals Online (AJOL)

state" to provide the Commission with information on the measures that they have ...... policies and identify the gaps in ensuring the full realisation of socio- economic .... Boulle L, Harris Band Hoexter C Constitutional and Administrative Law.

Hardware Realization of Chaos Based Symmetric Image Encryption

KAUST Repository

Barakat, Mohamed L.

2012-01-01

This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations

Commissioning results of the APS storage ring rf beam position monitors

International Nuclear Information System (INIS)

Kahana, E.; Chung, Y.

1996-01-01

The commissioning of the 360 rf beam position monitors (BPMs) in the Advanced Photon Source (APS) storage ring (SR) is nearing completion. After using the single-turn capability of the BPM electronics in the early ring commissioning phase, resolution measurements versus current and bandwidth were successfully performed. In the standard Sr vacuum chamber geometry, the resolution was measured with beam as 0.16 micromA/√(Hz). For the insertion device vacuum chamber geometry, the resolution was measured to be 0.1 micromA/√(Hz). Since the photon beam stability requirement for the users is only 4.5 microns rms in the vertical direction, investigations of rf BPM offset versus current and bunch pattern have also been initiated. Both single bunch and multibunch beam patterns with varying intensity were used to determine offset stability for both the global and the local orbit feedback applications

Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

KAUST Repository

Javed, Sidrah; Amin, Osama; Ikki, Salama S.; Alouini, Mohamed-Slim

2017-01-01

This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

Directory of Open Access Journals (Sweden)

Liang Ying-Chang

2005-01-01

Full Text Available This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP -based communication systems, including orthogonal frequency-division multiplexing (OFDM, single-carrier cyclic-prefix (SCCP system, multicarrier (MC code-division multiple access (MC-CDMA, MC direct-sequence CDMA (MC-DS-CDMA, CP-based CDMA (CP-CDMA, and CP-based direct-sequence CDMA (CP-DS-CDMA. A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

KAUST Repository

Javed, Sidrah

2017-02-22

This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

Qualification of software and hardware

International Nuclear Information System (INIS)

Gossner, S.; Schueller, H.; Gloee, G.

1987-01-01

The qualification of on-line process control equipment is subdivided into three areas: 1) materials and structural elements; 2) on-line process-control components and devices; 3) electrical systems (reactor protection and confinement system). Microprocessor-aided process-control equipment are difficult to verify for failure-free function owing to the complexity of the functional structures of the hardware and to the variety of the software feasible for microprocessors. Hence, qualification will make great demands on the inspecting expert. (DG) [de

Hardware dependencies of GPU-accelerated beamformer performances for microwave breast cancer detection

Directory of Open Access Journals (Sweden)

Salomon Christoph J.

2016-09-01

Full Text Available UWB microwave imaging has proven to be a promising technique for early-stage breast cancer detection. The extensive image reconstruction time can be accelerated by parallelizing the execution of the underlying beamforming algorithms. However, the efficiency of the parallelization will most likely depend on the grade of parallelism of the imaging algorithm and of the utilized hardware. This paper investigates the dependencies of two different beamforming algorithms on multiple hardware specification of several graphics boards. The parallel implementation is realized by using NVIDIA’s CUDA. Three conclusions are drawn about the behavior of the parallel implementation and how to efficiently use the accessible hardware.

Automation Hardware & Software for the STELLA Robotic Telescope

Science.gov (United States)

Weber, M.; Granzer, Th.; Strassmeier, K. G.

The STELLA telescope (a joint project of the AIP, Hamburger Sternwarte and the IAC) is to operate in fully robotic mode, with no human interaction necessary for regular operation. Thus, the hardware must be kept as simple as possible to avoid unnecessary failures, and the environmental conditions must be monitored accurately to protect the telescope in case of bad weather. All computers are standard PCs running Linux, and communication with specialized hardware is done via a RS232/RS485 bus system. The high level (java based) control software consists of independent modules to ease bug-tracking and to allow the system to be extended without changing existing modules. Any command cycle consists of three messages, the actual command sent from the central node to the operating device, an immediate acknowledge, and a final done message, both sent back from the receiving device to the central node. This reply-splitting allows a direct distinction between communication problems (no acknowledge message) and hardware problems (no or a delayed done message). To avoid bug-prone packing of all the sensor-analyzing software into a single package, each sensor-reading and interaction with other sensors is done within a self-contained thread. Weather-decision making is therefore totally decoupled from the core control software to avoid dead-locks in the core module.

Rupture hardware minimization in pressurized water reactor piping

International Nuclear Information System (INIS)

Mukherjee, S.K.; Ski, J.J.; Chexal, V.; Norris, D.M.; Goldstein, N.A.; Beaudoin, B.F.; Quinones, D.F.; Server, W.L.

1989-01-01

For much of the high-energy piping in light reactor systems, fracture mechanics calculations can be used to assure pipe failure resistance, thus allowing the elimination of excessive rupture restraint hardware both inside and outside containment. These calculations use the concept of leak-before-break (LBB) and include part-through-wall flaw fatigue crack propagation, through-wall flaw detectable leakage, and through-wall flaw stability analyses. Performing these analyses not only reduces initial construction, future maintenance, and radiation exposure costs, but also improves the overall safety and integrity of the plant since much more is known about the piping and its capabilities than would be the case had the analyses not been performed. This paper presents the LBB methodology applied a Beaver Valley Power Station- Unit 2 (BVPS-2); the application for two specific lines, one inside containment (stainless steel) and the other outside containment (ferrutic steel), is shown in a generic sense using a simple parametric matrix. The overall results for BVPS-2 indicate that pipe rupture hardware is not necessary for stainless steel lines inside containment greater than or equal to 6-in. (152-mm) nominal pipe size that have passed a screening criteria designed to eliminate potential problem systems (such as the feedwater system). Similarly, some ferritic steel line as small as 3-in. (76-mm) diameter (outside containment) can qualify for pipe rupture hardware elemination

arXiv Medical Physics Commissioning

CERN Document Server

Meer, David

The medical commissioning is an important step to bring a particle gantry into clinical operation for tumour treatments. This involves the parametrization and characterization of all relevant systems including the beam delivery, the patient table, the imaging systems and the connection to all required software components. This article is limited to necessary tasks for the beam delivery system of a pencil beam scanning system. Usually the commissioning starts with the characterization of the unscanned beam and the calibration of the beam energy. The following steps are the parametrization of the scanning system, the commissioning of the beam position monitoring system and characterization of the spot size, all requiring precisions better than 1 mm. The commissioning effort for these tasks depends also on the gantry topology. Finally, the calibration of the dose measurement system ensures that any dose distribution can be delivered with an absolute precision better than 1%.

Atomic Energy Commission Act, 2000 (Act 588)

International Nuclear Information System (INIS)

2000-01-01

Act 588 of the Republic of Ghana entitled, Atomic Energy Commission Act, 2000, amends and consolidates the Atomic Energy Commission Act, 204 of 1963 relating to the establishment of the Atomic Energy Commission. Act 588 makes provision for the Ghana Atomic Energy Commission to establish more institutes for the purpose of research in furtherance of its functions and also promote the commercialization of its research and development results. (E.A.A.)

Multi-loop PWR modeling and hardware-in-the-loop testing using ACSL

International Nuclear Information System (INIS)

Thomas, V.M.; Heibel, M.D.; Catullo, W.J.

1989-01-01

Westinghouse has developed an Advanced Digital Feedwater Control System (ADFCS) which is aimed at reducing feedwater related reactor trips through improved control performance for pressurized water reactor (PWR) power plants. To support control system setpoint studies and functional design efforts for the ADFCS, an ACSL based model of the nuclear steam supply system (NSSS) of a Westinghouse (PWR) was generated. Use of this plant model has been extended from system design to system testing through integration of the model into a Hardware-in-Loop test environment for the ADFCS. This integration includes appropriate interfacing between a Gould SEL 32/87 computer, upon which the plant model executes in real time, and the Westinghouse Distributed Processing family (WDPF) test hardware. A development program has been undertaken to expand the existing ACSL model to include capability to explicitly model multiple plant loops, steam generators, and corresponding feedwater systems. Furthermore, the program expands the ADFCS Hardware-in-Loop testing to include the multi-loop plant model. This paper provides an overview of the testing approach utilized for the ADFCS with focus on the role of Hardware-in-Loop testing. Background on the plant model, methodology and test environment is also provided. Finally, an overview is presented of the program to expand the model and associated Hardware-in-Loop test environment to handle multiple loops

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

Science.gov (United States)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

A Cost-Effective Approach to Hardware-in-the-Loop Simulation

DEFF Research Database (Denmark)

Pedersen, Mikkel Melters; Hansen, M. R.; Ballebye, M.

2012-01-01

This paper presents an approach for developing cost effective hardware-in-the- loop (HIL) simulation platforms for the use in controller software test and development. The approach is aimed at the many smaller manufacturers of e.g. mobile hydraulic machinery, which often do not have very advanced...... testing facilities at their disposal. A case study is presented where a HIL simulation platform is developed for the controller of a truck mounted loader crane. The total expenses in hardware and software is less than 10.000$....

Electrical, electronics, and digital hardware essentials for scientists and engineers

CERN Document Server

Lipiansky, Ed

2012-01-01

A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

Energy Technology Data Exchange (ETDEWEB)

Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

1993-01-01

Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

Energy Technology Data Exchange (ETDEWEB)

Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

1993-05-01

Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

Internet-based hardware/software co-design framework for embedded 3D graphics applications

Directory of Open Access Journals (Sweden)

Wong Weng-Fai

2011-01-01

Full Text Available Abstract Advances in technology are making it possible to run three-dimensional (3D graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API, device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC accelerator using transaction-level modeling (TLM. This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

Summary of multi-core hardware and programming model investigations

Energy Technology Data Exchange (ETDEWEB)

Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

2008-05-01

This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

Hardware Realization of Chaos-based Symmetric Video Encryption

KAUST Repository

Ibrahim, Mohamad A.

2013-01-01

This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally

Control/interlock/display system for EBT-P using commercially-available hardware and firmware

International Nuclear Information System (INIS)

Schmitt, R.J.

1983-01-01

For the EBT-P project, alternative commercially-available hardware, software and firmware have been employed for control, interlock and data display functions. This paper describes the criteria and rationale used to select that commercial equipment and discusses the important features of the equipment chosen, especially programmable controllers. Additional discussion is centered on interface problems which are encountered upon attempts to integrate equipment from several vendors. Some solutions to these problems are discussed. Details of software and hardware performance during tests are presented. The extent to which the EBT-P hardware and software configuration addresses and resolves various issues is discussed. Several areas have been uncovered in which relatively slight improvements/modifications of commercial programmable controller firmware would significantly improve the capability of this type of hardware in fusion control applications. These improvements are discussed in detail

78 FR 44165 - Nuclear Regulatory Commission Enforcement Policy

Science.gov (United States)

2013-07-23

... NUCLEAR REGULATORY COMMISSION [NRC-2013-0159] Nuclear Regulatory Commission Enforcement Policy AGENCY: Nuclear Regulatory Commission. ACTION: Enforcement policy; request for comment. SUMMARY: The U.S... Policy. In SRM-SECY-12-0047, ``Revisions to the Nuclear Regulatory Commission Enforcement Policy,'' dated...

Instrumented home energy rating and commissioning

Energy Technology Data Exchange (ETDEWEB)

Wray, Craig P.; Walker, Iain S.; Sherman, Max H.

2003-05-01

Currently, houses do not perform optimally or even as many codes and forecasts predict, largely because they are field assembled and there is no consistent process to identify deficiencies or to correct them. Solving this problem requires field performance evaluations using appropriate and agreed upon procedures in the form of a new process called residential commissioning. The purpose of this project is to develop and document these procedures and to demonstrate the value that applying them could provide in both new and existing California houses. This project has four specific objectives: to develop metrics and diagnostics for assessing house performance, to provide information on the potential benefits of commissioning using a whole-house approach, to develop programmatic guidelines for commissioning, and to conduct outreach efforts to transfer project results to industry stakeholders. The primary outcomes from this project are the development of residential commissioning guidelines and the analytical confirmation that there are significant potential benefits associated with commissioning California houses, particularly existing ones. In addition, we have made substantial advances in understanding the accuracy and usability of diagnostics for commissioning houses. In some cases, we have been able to work with equipment manufacturers to improve these aspects of their diagnostic tools. These outcomes provide a solid foundation on which to build a residential commissioning program in California. We expect that a concerted effort will be necessary to integrate such a program with existing building industry efforts and to demonstrate its use in the field.

Nuclear Regulatory Commission Issuances

International Nuclear Information System (INIS)

1992-01-01

This is the thirty-sixth volume of issuances (1-396) of the Nuclear Regulatory Commission and its Atomic Safety and Licensing Boards, Administrative Law Judges, and Office Directors. It covers the period from July 1, 1992-December 31, 1992. Atomic Safety and Licensing Boards are authorized by Section 191 of the Atomic Energy Act of 1954. These Boards, comprised of three members conduct adjudicatory hearings on applications to construct and operate nuclear power plants and related facilities and issue initial decisions which, subject to internal review and appellate procedures, become the final Commission action with respect to those applications. Boards are drawn from the Atomic Safety and Licensing Board Panel, comprised of lawyers, nuclear physicists and engineers, environmentalists, chemists, and economists. The Atomic Energy Commission first established Licensing Boards in 1962 and the Panel in 1967

17 CFR 171.28 - Participation by Commission staff.

Science.gov (United States)

2010-04-01

... staff. 171.28 Section 171.28 Commodity and Securities Exchanges COMMODITY FUTURES TRADING COMMISSION..., Membership Denial and Registration Actions § 171.28 Participation by Commission staff. The Division of.... The Commission shall by order establish a supplementary briefing schedule for the Commission staff and...

Point Lepreau G.S. commissioning management experience

International Nuclear Information System (INIS)

Alikhan, S.; Walker, W.J.

1983-05-01

This paper shares the experience gained by New Brunswick Power in commissioning its first nuclear plant, with particular emphasis on the management techniques that were developed. Some of the areas discussed include: organization of Nuclear Operations Group responsible for commissioning and its interface with construction; outline and scope of documentation required to define, execute and report commissioning to satisfy the licensing requirements, management techniques developed to implement commissioning; and a summary of lessons learned and recommendations for the future

Evaluating the scalability of HEP software and multi-core hardware

CERN Document Server

Jarp, S; Leduc, J; Nowak, A

2011-01-01

As researchers have reached the practical limits of processor performance improvements by frequency scaling, it is clear that the future of computing lies in the effective utilization of parallel and multi-core architectures. Since this significant change in computing is well underway, it is vital for HEP programmers to understand the scalability of their software on modern hardware and the opportunities for potential improvements. This work aims to quantify the benefit of new mainstream architectures to the HEP community through practical benchmarking on recent hardware solutions, including the usage of parallelized HEP applications.

Water system hardware and management rehabilitation: Qualitative evidence from Ghana, Kenya, and Zambia.

Science.gov (United States)

Klug, Tori; Shields, Katherine F; Cronk, Ryan; Kelly, Emma; Behnke, Nikki; Lee, Kristen; Bartram, Jamie

2017-05-01

Sufficient, safe, continuously available drinking water is important for human health and development, yet one in three handpumps in sub-Saharan Africa are non-functional at any given time. Community management, coupled with access to external technical expertise and spare parts, is a widely promoted model for rural water supply management. However, there is limited evidence describing how community management can address common hardware and management failures of rural water systems in sub-Saharan Africa. We identified hardware and management rehabilitation pathways using qualitative data from 267 interviews and 57 focus group discussions in Ghana, Kenya, and Zambia. Study participants were water committee members, community members, and local leaders in 18 communities (six in each study country) with water systems managed by a water committee and supported by World Vision (WV), an international non-governmental organization (NGO). Government, WV or private sector employees engaged in supporting the water systems were also interviewed. Inductive analysis was used to allow for pathways to emerge from the data, based on the perspectives and experiences of study participants. Four hardware rehabilitation pathways were identified, based on the types of support used in rehabilitation. Types of support were differentiated as community or external. External support includes financial and/or technical support from government or WV employees. Community actor understanding of who to contact when a hardware breakdown occurs and easy access to technical experts were consistent reasons for rapid rehabilitation for all hardware rehabilitation pathways. Three management rehabilitation pathways were identified. All require the involvement of community leaders and were best carried out when the action was participatory. The rehabilitation pathways show how available resources can be leveraged to restore hardware breakdowns and management failures for rural water systems in sub

Trainable hardware for dynamical computing using error backpropagation through physical media.

Science.gov (United States)

Hermans, Michiel; Burm, Michaël; Van Vaerenbergh, Thomas; Dambre, Joni; Bienstman, Peter

2015-03-24

Neural networks are currently implemented on digital Von Neumann machines, which do not fully leverage their intrinsic parallelism. We demonstrate how to use a novel class of reconfigurable dynamical systems for analogue information processing, mitigating this problem. Our generic hardware platform for dynamic, analogue computing consists of a reciprocal linear dynamical system with nonlinear feedback. Thanks to reciprocity, a ubiquitous property of many physical phenomena like the propagation of light and sound, the error backpropagation-a crucial step for tuning such systems towards a specific task-can happen in hardware. This can potentially speed up the optimization process significantly, offering important benefits for the scalability of neuro-inspired hardware. In this paper, we show, using one experimentally validated and one conceptual example, that such systems may provide a straightforward mechanism for constructing highly scalable, fully dynamical analogue computers.

19 CFR 213.5 - Access to Commission resources.

Science.gov (United States)

2010-04-01

... 19 Customs Duties 3 2010-04-01 2010-04-01 false Access to Commission resources. 213.5 Section 213.5 Customs Duties UNITED STATES INTERNATIONAL TRADE COMMISSION INVESTIGATIONS OF UNFAIR PRACTICES IN IMPORT TRADE TRADE REMEDY ASSISTANCE § 213.5 Access to Commission resources. Commission resources, in...

Alaska Public Offices Commission, Department of Administration, State of

Science.gov (United States)

Visiting Alaska State Employees State of Alaska Department of Administration Alaska Public Offices Commission Alaska Department of Administration, Alaska Public Offices Commission APOC Home Commission Filer ; AO's Contact Us Administration > Alaska Public Offices Commission Alaska Public Offices Commission

47 CFR 0.420 - Other Commission publications.

Science.gov (United States)

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false Other Commission publications. 0.420 Section 0... Information Printed Publications § 0.420 Other Commission publications. The following additional Commission publications may be purchased from the Superintendent of Documents: (a) Statistics of Communications Common...

National Capital Planning Commission Meeting Transcripts

Data.gov (United States)

National Capital Planning Commission — Transcripts of the monthly (with the exception of August) National Capital Planning Commission meeting transcripts are provided for research to confirm actions taken...

29 CFR 2200.92 - Review by the Commission.

Science.gov (United States)

2010-07-01

... Regulations Relating to Labor (Continued) OCCUPATIONAL SAFETY AND HEALTH REVIEW COMMISSION RULES OF PROCEDURE Posthearing Procedures § 2200.92 Review by the Commission. (a) Jurisdiction of the Commission; issues on... Commission to review the entire case. The issues to be decided on review are within the discretion of the...

48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

Science.gov (United States)

2010-10-01

... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title III...

Completion of the Heysham 2 peripheral manipulator

International Nuclear Information System (INIS)

Shipp, R.; Ewen, R.O.

1996-01-01

The in-service inspection strategy for the AGR power station at Heysham 2 envisaged a suite of five manipulators to be used for inserting TRIUMPH television cameras into the reactor vessel. Prior to power raising, four of the five had been successfully commissioned and have been in regular use during the subsequent statutory outages. The final device, the Peripheral Manipulator (PM), was eventually completed prior to the 1994 outage and has been successfully deployed on reactor for both the 1994 and 1995 outages. The paper describes the design of the manipulator, its operation and scope of use in the Heysham 2 reactors. (Author)

National Capital Planning Commission Library contents

Data.gov (United States)

National Capital Planning Commission — The National Capital Planning Commission library catalog is a compilation of titles, authors, years of publication and topics of books, reports and NCPC publications.

Growth in spaceflight hardware results in alterations to the transcriptome and proteome

Science.gov (United States)

Basu, Proma; Kruse, Colin P. S.; Luesse, Darron R.; Wyatt, Sarah E.

2017-11-01

The Biological Research in Canisters (BRIC) hardware has been used to house many biology experiments on both the Space Transport System (STS, commonly known as the space shuttle) and the International Space Station (ISS). However, microscopic examination of Arabidopsis seedlings by Johnson et al. (2015) indicated the hardware itself may affect cell morphology. The experiment herein was designed to assess the effects of the BRIC-Petri Dish Fixation Units (BRIC-PDFU) hardware on the transcriptome and proteome of Arabidopsis seedlings. To our knowledge, this is the first transcriptomic and proteomic comparison of Arabidopsis seedlings grown with and without hardware. Arabidopsis thaliana wild-type Columbia (Col-0) seeds were sterilized and bulk plated on forty-four 60 mm Petri plates, of which 22 were integrated into the BRIC-PDFU hardware and 22 were maintained in closed containers at Ohio University. Seedlings were grown for approximately 3 days, fixed with RNAlater® and stored at -80 °C prior to RNA and protein extraction, with proteins separated into membrane and soluble fractions prior to analysis. The RNAseq analysis identified 1651 differentially expressed genes; MS/MS analysis identified 598 soluble and 589 membrane proteins differentially abundant both at p < .05. Fold enrichment analysis of gene ontology terms related to differentially expressed transcripts and proteins highlighted a variety of stress responses. Some of these genes and proteins have been previously identified in spaceflight experiments, indicating that these genes and proteins may be perturbed by both conditions.

45 CFR 702.12 - Contempt of the Commission.

Science.gov (United States)

2010-10-01

... 45 Public Welfare 3 2010-10-01 2010-10-01 false Contempt of the Commission. 702.12 Section 702.12 Public Welfare Regulations Relating to Public Welfare (Continued) COMMISSION ON CIVIL RIGHTS RULES ON HEARINGS, REPORTS, AND MEETINGS OF THE COMMISSION Hearings and Reports § 702.12 Contempt of the Commission...

Particle Transport Simulation on Heterogeneous Hardware

CERN Multimedia

CERN. Geneva

2014-01-01

CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

High exposure rate hardware ALARA plan

International Nuclear Information System (INIS)

Nellesen, A.L.

1996-10-01

This as low as reasonably achievable review provides a description of the engineering and administrative controls used to manage personnel exposure and to control contamination levels and airborne radioactivity concentrations. HERH waste is hardware found in the N-Fuel Storage Basin, which has a contact dose rate greater than 1 R/hr and used filters. This waste will be collected in the fuel baskets at various locations in the basins

Hardware-in-the-Loop Simulation for the Automatic Power Control System of Research Reactors

International Nuclear Information System (INIS)

Fikry, R.M.; Shehata, S.A.; Elaraby, S.M.; Mahmoud, M.I.; Elbardini, M.M.

2009-01-01

Designing and testing digital control system for any nuclear research reactor can be costly and time consuming. In this paper, a rapid, low-cost proto typing and testing procedure for digital controller design is proposed using the concept of Hardware-In- The-Loop (HIL). Some of the control loop components are real hardware components and thc others are simulated. First, the whole system is modeled and tested by Real- Time Simulation (RTS) using conventional simulation techniques such as MATLAB / SIMULINK. Second the Hardware-in-the-Ioop simulation is tested using Real-Time Windows Target in MATLAB and Visual C++. The control parts are included as hardware components which are the reactor control rod and its drivers. Two kinds of controllers are studied, Proportional derivative (PD) and Fuzzy controller, An experimental setup for the hardware used in HIL concept for the control of the nuclear research reactor has been realized. Experimental results are obtained and compared with the simulation results. The experimental results indicate the validation of HIL method in this domain

United States Nuclear Regulatory Commission staff practice and procedure digest

International Nuclear Information System (INIS)

1991-02-01

This Revision 9 of the fifth edition of the NRC Staff Practice and Procedure Digest contains a digest of a number of Commission, Atomic Safety and Licensing Appeal Board, and Atomic Safety and Licensing Board decisions issued during the period from July 1, 1972 to September 30, 1990 interpreting the NRC's Rules of Practice in 10 CFR Part 2. This Revision 9 replaces in part earlier editions and revisions and includes appropriate changes reflecting the amendments to the Rules of Practice effective through September 30, 1990. This edition of the Digest was prepared by attorneys from Aspen Systems Corporation pursuant to Contract number 18-89-346. Persons using this Digest are placed on notice that it may not be used as an authoritative citation in support of any position before the Commission or any of its adjudicatory tribunals. Persons using this Digest are also placed on notice that it is intended for use only as an initial research tool, that it may, and likely does, contain errors, including errors in analysis and interpretation of decisions, and that the user should not rely on the Digest analyses and interpretations but must read, analyze and rely on the user's own analysis of the actual Commission, Appeal Board and Licensing Board decisions cited. Further, neither the United States, the Nuclear Regulatory Commission, Aspen Systems Corporation, nor any of their employees makes any expressed or implied warranty or assumes liability or responsibility for the accuracy, completeness or usefulness of any material presented in the Digest. The Digest is roughly structured in accordance with the chronological sequence of the nuclear facility licensing process as set forth in Appendix A to 10 CFR Part 2. Those decisions which did not fit into that structure are dealt with in a section on general matters. Where appropriate, particular decisions are indexed under more than one heading. (JF)

Hardware accuracy counters for application precision and quality feedback

Science.gov (United States)

de Paula Rosa Piga, Leonardo; Majumdar, Abhinandan; Paul, Indrani; Huang, Wei; Arora, Manish; Greathouse, Joseph L.

2018-06-05

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

Fast and Reliable Mouse Picking Using Graphics Hardware

Directory of Open Access Journals (Sweden)

Hanli Zhao

2009-01-01

Full Text Available Mouse picking is the most commonly used intuitive operation to interact with 3D scenes in a variety of 3D graphics applications. High performance for such operation is necessary in order to provide users with fast responses. This paper proposes a fast and reliable mouse picking algorithm using graphics hardware for 3D triangular scenes. Our approach uses a multi-layer rendering algorithm to perform the picking operation in linear time complexity. The objectspace based ray-triangle intersection test is implemented in a highly parallelized geometry shader. After applying the hardware-supported occlusion queries, only a small number of objects (or sub-objects are rendered in subsequent layers, which accelerates the picking efficiency. Experimental results demonstrate the high performance of our novel approach. Due to its simplicity, our algorithm can be easily integrated into existing real-time rendering systems.

Advances in neuromorphic hardware exploiting emerging nanoscale devices

CERN Document Server

2017-01-01

This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

Web tools to monitor and debug DAQ hardware

International Nuclear Information System (INIS)

Desavouret, Eugene; Nogiec, Jerzy M.

2003-01-01

A web-based toolkit to monitor and diagnose data acquisition hardware has been developed. It allows for remote testing, monitoring, and control of VxWorks data acquisition computers and associated instrumentation using the HTTP protocol and a web browser. This solution provides concurrent and platform independent access, supplementary to the standard single-user rlogin mechanism. The toolkit is based on a specialized web server, and allows remote access and execution of select system commands and tasks, execution of test procedures, and provides remote monitoring of computer system resources and connected hardware. Various DAQ components such as multiplexers, digital I/O boards, analog to digital converters, or current sources can be accessed and diagnosed remotely in a uniform and well-organized manner. Additionally, the toolkit application supports user authentication and is able to enforce specified access restrictions

A Hardware Framework for on-Chip FPGA Acceleration

DEFF Research Database (Denmark)

Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

2016-01-01

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

Commissioning and start-up of RA-8 critical assembly

International Nuclear Information System (INIS)

Lorenzo, N. de; Diaz, C.; Facchini, G.; Fernandez, C.; Fittipaldi, A.; Juracich, R.; Levanon, I.; Manceda, J.; Martinez, J.; Mogdan, R.; Perez, J.; Scarnichia, E.; Blaumann, H.; Gennuso, G.; Scotti, G.

1999-01-01

The RA-8 critical assembly was designed as one of the experimental facilities for the CAREM Reactor Project. This paper describes the activities developed during the cold and hot commissioning, pointing out the difficulties and the solutions applied (some of them original ones). Moreover, this paper will show the main features of the newest nuclear installation of CNEA making a brief description of its characteristics. Among the special circumstances related to the commissioning that are described in the paper we can mention the following: 1. The facility shares the building with the Thermohydraulic Assay Laboratory (L.E.T.), another experimental facility of CAREM, and thus some shared systems have already been working for many years before this start up. Special procedures for these systems were designed to verify the proper functioning under the new requirements. 2. A new driving mechanism, based in hydraulic cylinders, was used to move the control rods. The criteria for acceptance and a validation of the procedure completeness have been carried out. 3. The implementation of a power measurement system based in neutron noise. 4. Measurement of Power Distribution using direct gamma counting from the fuel elements. 5. The commissioning was interrupted for a ten-month period because the personnel involved had to carry out the commissioning of the Egyptian Research Reactor 2. Also, the common activities during a commissioning are described, pointing out the major steps carried out and the results obtained. The following are examples of these activities: 1. Environmental dose survey (before fuel loading and during other stages). 2. Test of equipment and systems isolated from the rest of the plant. 3. Integrated system test (two or more systems working at the same time). 4. Start-up and power operation simulations before fuel loading. 5. Fuel loading strategy during the approximation to criticality by mass. 6. Modification of systems' components to improve the