Use of the Graded Prognostic Assessment (GPA) score in patients with brain metastases from primary tumours not represented in the diagnosis-specific GPA studies

Energy Technology Data Exchange (ETDEWEB)

Nieder, C. [Nordland Hospital, Bodoe (Norway). Dept. of Oncology and Palliative Medicine; Tromsoe Univ. (Norway). Inst. of Clinical Medicine; Andratschke, N.H. [University Hospital Rostock (Germany). Dept. of Radiation Oncology; Geinitz, H. [Klinikum rechts der Isar der Technischen Univ. Muenchen (Germany). Dept. of Radiation Oncology; Grosu, A.L. [University Hospital Freiburg (Germany). Dept. of Radiation Oncology

2012-08-15

Background and purpose: Assessment of prognostic factors might influence treatment decisions in patients with brain metastases. Based on large studies, the diagnosis-specific graded prognostic assessment (GPA) score is a useful tool. However, patients with unknown or rare primary tumours are not represented in this model. A pragmatic approach might be use of the first GPA version which is not limited to specific primary tumours. Patients and methods: This retrospective analysis examines for the first time whether the GPA is a valid score in patients not eligible for the diagnosis-specific GPA. It includes 71 patients with unknown primary tumour, bladder cancer, ovarian cancer, thyroid cancer or other uncommon primaries. Survival was evaluated in uni- and multivariate tests. Results: The GPA significantly predicted survival. Moreover, improved survival was seen in patients treated with surgical resection or radiosurgery (SRS) for brain metastases. The older recursive partitioning analysis (RPA) score was significant in univariate analysis. However, the multivariate model with RPA, GPA and surgery or SRS versus none showed that only GPA and type of treatment were independent predictors of survival. Conclusion: Ideally, cooperative research efforts would lead to development of diagnosis-specific scores also for patients with rare or unknown primary tumours. In the meantime, a pragmatic approach of using the general GPA score appears reasonable. (orig.)

Use of the Graded Prognostic Assessment (GPA) score in patients with brain metastases from primary tumours not represented in the diagnosis-specific GPA studies

International Nuclear Information System (INIS)

Nieder, C.; Tromsoe Univ.; Andratschke, N.H.; Geinitz, H.; Grosu, A.L.

2012-01-01

Background and purpose: Assessment of prognostic factors might influence treatment decisions in patients with brain metastases. Based on large studies, the diagnosis-specific graded prognostic assessment (GPA) score is a useful tool. However, patients with unknown or rare primary tumours are not represented in this model. A pragmatic approach might be use of the first GPA version which is not limited to specific primary tumours. Patients and methods: This retrospective analysis examines for the first time whether the GPA is a valid score in patients not eligible for the diagnosis-specific GPA. It includes 71 patients with unknown primary tumour, bladder cancer, ovarian cancer, thyroid cancer or other uncommon primaries. Survival was evaluated in uni- and multivariate tests. Results: The GPA significantly predicted survival. Moreover, improved survival was seen in patients treated with surgical resection or radiosurgery (SRS) for brain metastases. The older recursive partitioning analysis (RPA) score was significant in univariate analysis. However, the multivariate model with RPA, GPA and surgery or SRS versus none showed that only GPA and type of treatment were independent predictors of survival. Conclusion: Ideally, cooperative research efforts would lead to development of diagnosis-specific scores also for patients with rare or unknown primary tumours. In the meantime, a pragmatic approach of using the general GPA score appears reasonable. (orig.)

Array processor architecture

Science.gov (United States)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

Science.gov (United States)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Biological Water Processor and Forward Osmosis Secondary Treatment

Science.gov (United States)

Shull, Sarah; Meyer, Caitlin

2014-01-01

The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

Probabilistic programmable quantum processors

International Nuclear Information System (INIS)

Buzek, V.; Ziman, M.; Hillery, M.

2004-01-01

We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

OpenAIRE

Abdul Kareem PARCHUR; Ram Asaray SINGH

2012-01-01

High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

Compression of glycolide-h4 to 6GPa

DEFF Research Database (Denmark)

Hutchison, Ian B.; Bull, Craig L.; Marshall, William G.

2017-01-01

This study details the structural characterization of glycolide-h4 as a function of pressure to 6GPa using neutron powder diffraction on the PEARL instrument at ISIS Neutron and Muon source. Glycolide-h4, rather than its deuterated isotopologue, was used in this study due to the difficulty...... of deuteration. The low background afforded by zirconia-toughened alumina anvils nevertheless enabled the collection of data suitable for structural analysis to be obtained to a pressure of 5GPa. Glycolide-h4 undergoes a reconstructive phase transition at 0.15GPa to a previously identified form (II), which...

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2012-08-01

Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

Simulation of a parallel processor on a serial processor: The neutron diffusion equation

International Nuclear Information System (INIS)

Honeck, H.C.

1981-01-01

Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

HTGR core seismic analysis using an array processor

International Nuclear Information System (INIS)

Shatoff, H.; Charman, C.M.

1983-01-01

A Floating Point Systems array processor performs nonlinear dynamic analysis of the high-temperature gas-cooled reactor (HTGR) core with significant time and cost savings. The graphite HTGR core consists of approximately 8000 blocks of various shapes which are subject to motion and impact during a seismic event. Two-dimensional computer programs (CRUNCH2D, MCOCO) can perform explicit step-by-step dynamic analyses of up to 600 blocks for time-history motions. However, use of two-dimensional codes was limited by the large cost and run times required. Three-dimensional analysis of the entire core, or even a large part of it, had been considered totally impractical. Because of the needs of the HTGR core seismic program, a Floating Point Systems array processor was used to enhance computer performance of the two-dimensional core seismic computer programs, MCOCO and CRUNCH2D. This effort began by converting the computational algorithms used in the codes to a form which takes maximum advantage of the parallel and pipeline processors offered by the architecture of the Floating Point Systems array processor. The subsequent conversion of the vectorized FORTRAN coding to the array processor required a significant programming effort to make the system work on the General Atomic (GA) UNIVAC 1100/82 host. These efforts were quite rewarding, however, since the cost of running the codes has been reduced approximately 50-fold and the time threefold. The core seismic analysis with large two-dimensional models has now become routine and extension to three-dimensional analysis is feasible. These codes simulate the one-fifth-scale full-array HTGR core model. This paper compares the analysis with the test results for sine-sweep motion

Functional unit for a processor

NARCIS (Netherlands)

Rohani, A.; Kerkhoff, Hans G.

2013-01-01

The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

Managing gas plant margins through the financial commodities market

International Nuclear Information System (INIS)

Peters, D.; Lafferty, L.

1995-01-01

Gas processors invest capital in gas plants to condition raw natural gas for market. They also attempt to upgrade the value of natural gas streams by removing gas liquids contained in these streams and selling them for a profit. Unfortunately, this is not always possible. Gas processing profit margins swing up and down in line with the volatility of the natural gas and gas liquids markets. Consequently the return on gas processors invested capital also swings up and down through ''good years'' and ''bad years''. Until recently, gas processors have had to bear the risk associated with these swings in margins. While an efficient market exists for products like crude oil on the New York Mercantile Exchange, no similar market has been available for gas liquids. The NYMEX propane contract has not developed sufficient liquidity for year round hedging of propane, much less the other gas liquids. Processors in regions without access to the Belvieu market encounter an even more difficult task attempting to use the NYMEX contract to hedge. Today this inability to manage risk is beginning to change. The natural gas markets have led the way since their deregulation with an actively traded over-the-counter forwards market firmly established. An over-the-counter forwards market for gas liquids has also started to emerge. It is through these new and emerging markets that a gas plant's profitability can be hedged

Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

Energy Technology Data Exchange (ETDEWEB)

Nuvera Fuel Cells

2005-04-15

The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

Adaptive signal processor

Energy Technology Data Exchange (ETDEWEB)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

Adaptive signal processor

International Nuclear Information System (INIS)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

Recovery of hexagonal Si-IV nanowires from extreme GPa pressure

Energy Technology Data Exchange (ETDEWEB)

Smith, Bennett E. [Department of Chemistry, University of Washington, Seattle, Washington 98195 (United States); Zhou, Xuezhe; Roder, Paden B. [Department of Materials Science and Engineering, University of Washington, Seattle, Washington 98195 (United States); Abramson, Evan H. [Department of Earth and Space Sciences, University of Washington, Seattle, Washington 98195 (United States); Pauzauskie, Peter J., E-mail: peterpz@uw.edu [Department of Materials Science and Engineering, University of Washington, Seattle, Washington 98195 (United States); Fundamental and Computational Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352 (United States)

2016-05-14

We use Raman spectroscopy in tandem with transmission electron microscopy and density functional theory simulations to show that extreme (GPa) pressure converts the phase of silicon nanowires from cubic (Si-I) to hexagonal (Si-IV) while preserving the nanowire's cylindrical morphology. In situ Raman scattering of the longitudinal transverse optical (LTO) mode demonstrates the high-pressure Si-I to Si-II phase transition near 9 GPa. Raman signal of the LTO phonon shows a decrease in intensity in the range of 9–14 GPa. Then, at 17 GPa, it is no longer detectable, indicating a second phase change (Si-II to Si-V) in the 14–17 GPa range. Recovery of exotic phases in individual silicon nanowires from diamond anvil cell experiments reaching 17 GPa is also shown. Raman measurements indicate Si-IV as the dominant phase in pressurized nanowires after decompression. Transmission electron microscopy and electron diffraction confirm crystalline Si-IV domains in individual nanowires. Computational electromagnetic simulations suggest that heating from the Raman laser probe is negligible and that near-hydrostatic pressure is the primary driving force for the formation of hexagonal silicon nanowires.

Alternative Water Processor Test Development

Science.gov (United States)

Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

2012-01-01

The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

Multithreading in vector processors

Science.gov (United States)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

2018-01-16

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Working under the PJVA gas processing agreement

International Nuclear Information System (INIS)

Collins, S.

1996-01-01

The trend in the natural gas industry is towards custom processing. New gas reserves tend to be smaller and in tighter reservoirs than in the past. This has resulted in plants having processing and transportation capacity available to be leased to third parties. Major plant operators and owners are finding themselves in the business of custom processing in a more focused way. Operators recognize that the dilution of operating costs can result in significant benefits to the plant owners as well as the third party processor. The relationship between the gas processor and the gas producer as they relate to the Petroleum Joint Venture Association (PJVA) Gas Processing Agreement were discussed. Details of the standard agreement that clearly defines the responsibilities of the third party producer and the processor were explained. In addition to outlining obligations of the parties, it also provides a framework for fee negotiation. It was concluded that third party processing can lower facility operating costs, extend facility life, and keep Canadian gas more competitive in holding its own in North American gas markets

Dual-core Itanium Processor

CERN Multimedia

2006-01-01

Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

3081/E processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.

1984-04-01

The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

Investigating the Utility of a GPA Institutional Adjustment Index

Science.gov (United States)

Didier, Thomas; Kreiter, Clarence D.; Buri, Russell; Solow, Catherine

2006-01-01

Background: Grading standards vary widely across undergraduate institutions. If, during the medical school admissions process, GPA is considered without reference to the institution attended, it will disadvantage applicants from undergraduate institutions employing rigorous grading standards. Method: A regression-based GPA institutional equating…

The Why, What, and Impact of GPA at Oxford Brookes University

Science.gov (United States)

Andrews, Matthew

2016-01-01

This paper examines the introduction at Oxford Brookes University of a Grade Point Average (GPA) scheme alongside the traditional honours degree classification. It considers the reasons for the introduction of GPA, the way in which the scheme was implemented, and offers an insight into the impact of GPA at Brookes. Finally, the paper considers…

Methanol fuel processor and PEM fuel cell modeling for mobile application

Energy Technology Data Exchange (ETDEWEB)

Chrenko, Daniela [ISAT, University of Burgundy, Rue Mlle Bourgoise, 58000 Nevers (France); Gao, Fei; Blunier, Benjamin; Bouquain, David; Miraoui, Abdellatif [Transport and Systems Laboratory (SeT) - EA 3317/UTBM, Fuel cell Laboratory (FCLAB), University of Technology of Belfort-Montbeliard, Rue Thierry Mieg 90010, Belfort Cedex (France)

2010-07-15

The use of hydrocarbon fed fuel cell systems including a fuel processor can be an entry market for this emerging technology avoiding the problem of hydrogen infrastructure. This article presents a 1 kW low temperature PEM fuel cell system with fuel processor, the system is fueled by a mixture of methanol and water that is converted into hydrogen rich gas using a steam reformer. A complete system model including a fluidic fuel processor model containing evaporation, steam reformer, hydrogen filter, combustion, as well as a multi-domain fuel cell model is introduced. Experiments are performed with an IDATECH FCS1200 trademark fuel cell system. The results of modeling and experimentation show good results, namely with regard to fuel cell current and voltage as well as hydrogen production and pressure. The system is auto sufficient and shows an efficiency of 25.12%. The presented work is a step towards a complete system model, needed to develop a well adapted system control assuring optimized system efficiency. (author)

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

Science.gov (United States)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

The Hugoniot and chemistry of ablator plastic below 100 GPa

Energy Technology Data Exchange (ETDEWEB)

Akin, M. C., E-mail: akin1@llnl.gov; Fratanduono, D. E.; Chau, R. [Lawrence Livermore National Laboratory, Livermore, California 94550 (United States)

2016-01-28

The equation of state of glow discharge polymer (GDP) was measured to high precision using the two-stage light gas gun at Lawrence Livermore National Laboratory at pressures up to 70 GPa. Both absolute measurements and impedance matching techniques were used to determine the principal and secondary Hugoniots. GDP likely reacts at about 30 GPa, demonstrated by specific emission at 450 nm coupled with changes to the Hugoniot and reshock points. As a result of these reactions, the shock pressure in GDP evolves in time, leading to a possible decrease in pressure as compression increases, or negative compressibility, and causing complex pressure profiles within the plastic. Velocity wave profile variation was observed as a function of position on each shot, suggesting some internal variation of GDP may be present, which would be consistent with previous observations. The complex temporal and possibly structural evolution of GDP under shock compression suggests that calculations of compression and pressure based upon bulk or mean measurements may lead to artificially low pressures and high compressions. Evidence for this includes a large shift in calculating reshock pressures based on the reflected Hugoniot. These changes also suggest other degradation mechanisms for inertial confinement fusion implosions.

The Molen Polymorphic Media Processor

NARCIS (Netherlands)

Kuzmanov, G.K.

2004-01-01

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

Challenging the 3.0 GPA Eligibility Standard for Public Relations Internships.

Science.gov (United States)

Maynard, Michael L.

1999-01-01

Analyzes the appropriateness of a 3.0 GPA standard for public relations internship eligibility at one university. Seeks to determine at what GPA cutoff faculty can feel confident that the student will gain from the internship without damaging the program's reputation. Finds students with a 2.7 GPA did as well as students with GPAs ranging from 3.0…

A light hydrocarbon fuel processor producing high-purity hydrogen

Science.gov (United States)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

Simulation of a 250 kW diesel fuel processor/PEM fuel cell system

Science.gov (United States)

Amphlett, J. C.; Mann, R. F.; Peppley, B. A.; Roberge, P. R.; Rodrigues, A.; Salvador, J. P.

Polymer-electrolyte membrane (PEM) fuel cell systems offer a potential power source for utility and mobile applications. Practical fuel cell systems use fuel processors for the production of hydrogen-rich gas. Liquid fuels, such as diesel or other related fuels, are attractive options as feeds to a fuel processor. The generation of hydrogen gas for fuel cells, in most cases, becomes the crucial design issue with respect to weight and volume in these applications. Furthermore, these systems will require a gas clean-up system to insure that the fuel quality meets the demands of the cell anode. The endothermic nature of the reformer will have a significant affect on the overall system efficiency. The gas clean-up system may also significantly effect the overall heat balance. To optimize the performance of this integrated system, therefore, waste heat must be used effectively. Previously, we have concentrated on catalytic methanol-steam reforming. A model of a methanol steam reformer has been previously developed and has been used as the basis for a new, higher temperature model for liquid hydrocarbon fuels. Similarly, our fuel cell evaluation program previously led to the development of a steady-state electrochemical fuel cell model (SSEM). The hydrocarbon fuel processor model and the SSEM have now been incorporated in the development of a process simulation of a 250 kW diesel-fueled reformer/fuel cell system using a process simulator. The performance of this system has been investigated for a variety of operating conditions and a preliminary assessment of thermal integration issues has been carried out. This study demonstrates the application of a process simulation model as a design analysis tool for the development of a 250 kW fuel cell system.

JPP: A Java Pre-Processor

OpenAIRE

Kiniry, Joseph R.; Cheong, Elaine

1998-01-01

The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

48 CFR 25.504-2 - WTO GPA/Caribbean Basin Trade Initiative/FTAs.

Science.gov (United States)

2010-10-01

... 48 Federal Acquisition Regulations System 1 2010-10-01 2010-10-01 false WTO GPA/Caribbean Basin... 25.504-2 WTO GPA/Caribbean Basin Trade Initiative/FTAs. Example 1. Offer A 304,000 U.S.-made end... the acquisition is covered by the WTO GPA and there is an offer of a U.S.-made or an eligible product...

X-ray Diffraction Study of Molybdenum Diselenide to 35.9 GPa

International Nuclear Information System (INIS)

Aksoy, R.; Selvi, E.; Ma, Y.

2008-01-01

In situ high-pressure angle dispersive synchrotron X-ray diffraction studies of molybdenum diselenide (MoSe2) were carried out in a diamond-anvil cell to 35.9 GPa. No evidence of a phase transformation was observed in the pressure range. By fitting the pressure-volume data to the third-order Birch-Murnaghan equation of state, the bulk modulus, K0T, was determined to be 45.7±0.3 GPa with its pressure derivative, K'0T, being 11.6±0.1. It was found that the c-axis decreased linearly with pressure at a slope of -0.1593 when pressures were lower than 10 GPa. It showed different linear decrease with the slope of a -0.0236 at pressures higher than 10 GPa.

Producing chopped firewood with firewood processors

International Nuclear Information System (INIS)

Kaerhae, K.; Jouhiaho, A.

2009-01-01

The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

Optical Associative Processors For Visual Perception"

Science.gov (United States)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

AMD's 64-bit Opteron processor

CERN Multimedia

CERN. Geneva

2003-01-01

This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

Composable processor virtualization for embedded systems

NARCIS (Netherlands)

Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

2010-01-01

Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

Deterministic chaos in the processor load

International Nuclear Information System (INIS)

Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

2007-01-01

In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

Opportunities and Best Practices to Support Sustainable Production for Small Growers and Post-Harvest Processors in Southern California

Science.gov (United States)

Fissore, Cinzia; Duran, Daniel F.; Russell, Robert

2015-01-01

This article describes current practices and needs associated with water and gas conservation among Southern California greenhouse growers, Post-Harvest Processors (PHPs), and agricultural associations. Two communication forums were held with the goal of educating the local gas company and small growers and PHPs on the most compelling needs and…

Compression of Single-Crystal Orthopyroxene to 60GPa

Science.gov (United States)

Finkelstein, G. J.; Dera, P. K.; Holl, C. M.; Dorfman, S. M.; Duffy, T. S.

2010-12-01

Orthopyroxene ((Mg,Fe)SiO3) is one of the dominant phases in Earth’s upper mantle - it makes up ~20% of the upper mantle by volume. At high pressures and temperatures, this phase undergoes several well-characterized phase transitions. However, when compressed at low temperature and high-pressure, orthopyroxene is predicted to exhibit metastable behavior(1). Previous researchers have found orthoenstatite (Mg endmember of orthopyroxene) persists up to ~10 GPa, and diffraction(2-3), Raman(4), and elasticity(5) experiments suggest a phase transition above this pressure to an as-yet unidentified structure. While earlier diffraction data has surprisingly only been evaluated for structural information to ~9 GPa(2), changes in high-pressure Raman spectra to ~70 GPa indicate that several more high-pressure phase transitions in orthopyroxene are likely, including at least one change in Si-coordination(6). We have recently conducted exploratory experiments to further elucidate the high-pressure behavior of orthopyroxene. Compressing a single crystal of Fe-rich orthopyroxene (Fe0.66Mg0.24Ca0.05SiO3) using a diamond anvil cell, we observe phase transitions at ~10, 14, and 30 GPa, with the new phases having monoclinic, orthorhombic, and orthorhombic symmetries, respectively. While the first two transitions do not show a significant change in volume, the phase transition at ~30 GPa shows a large decrease in volume, which is consistent with a change in Si coordination number to mixed 4- and 6-fold coordination. References: [1] S. Jahn, American Mineralogist 93, 528-532 (2008). [2] R. J. Angel, J. M. Jackson, American Mineralogist 87, 558-561 (2002). [3] R. J. Angel, D. A. Hugh-Jones, Journal of Geophysical Research-Solid Earth 99, 19,777-19,783 (1994). [4] G. Serghiou, Journal of Raman Spectroscopy 34, 587-590 (2003). [5] J. Kung et al., Physics of the Earth and Planetary Interiors 147, 27-44 (2004). [6] G. Serghiou, A. Chopelas, R. Boehler, Journal of Physics: Condensed Matter

Caffeine Consumption among Medical Interns and Association with GPA in Makkah Region

Directory of Open Access Journals (Sweden)

Alsharif Mohammed H

2016-12-01

Full Text Available The Vagarious amount of caffeine may become harmful in frequent use, it increased among medical interns in Makkah region. The caffeine becomes a daily routine for medical interns without attention for their side harmful effect. The purpose of our study was to evaluate the educational level of awareness of the harmful effect of caffeine consumption. This was a cross-sectional study from August to October 2016. A total number 437 of participants with GPA groups, Group I (GPA 1.5-2, Group II (GPA 2.1- 3 and Group III (GPA 3.1- 3.5. The higher percentages were the group II and female consumed caffeine frequently more than male.

Phase stability of iron germanate, FeGeO3, to 127 GPa

Science.gov (United States)

Dutta, R.; Tracy, S. J.; Stan, C. V.; Prakapenka, V. B.; Cava, R. J.; Duffy, T. S.

2018-04-01

The high-pressure behavior of germanates is of interest as these compounds serve as analogs for silicates of the deep Earth. Current theoretical and experimental studies of iron germanate, FeGeO3, are limited. Here, we have examined the behavior of FeGeO3 to 127 GPa using the laser-heated diamond anvil cell combined with in situ synchrotron X-ray diffraction. Upon compression at room temperature, the ambient-pressure clinopyroxene phase transforms to a disordered triclinic phase [FeGeO3 (II)] at 18 GPa in agreement with earlier studies. An additional phase transition to FeGeO3 (III) occurs above 54 GPa at room temperature. Laser-heating experiments ( 1200-2200 K) were conducted at three pressures (33, 54, and 123 GPa) chosen to cover the stability regions of different GeO2 polymorphs. In all cases, we observe that FeGeO3 dissociates into GeO2 + FeO at high pressure and temperature conditions. Neither the perovskite nor the post-perovskite phase was observed up to 127 GPa at ambient or high temperatures. The results are consistent with the behavior of FeSiO3, which also dissociates into a mixture of the oxides (FeO + SiO2) at least up to 149 GPa.

X-ray-diffraction study of californium metal to 16 GPa

International Nuclear Information System (INIS)

Peterson, J.R.; Benedict, U.; Dufour, C.; Birkel, I.; Haire, R.G.

1983-01-01

The first series of measurements to determine the structural behavior of californium (Cf) metal under pressure has been carried out. The initial dhcp structure transformed sluggishly with increasing pressure to a fcc structure. A bulk modulus of 50(5) GPa was derived for dhcp Cf metal from the relative volume (V/V 0 ) data to 10 GPa

Neurovision processor for designing intelligent sensors

Science.gov (United States)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

VIRTUS: a multi-processor system in FASTBUS

International Nuclear Information System (INIS)

Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

1986-01-01

VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

A lock circuit for a multi-core processor

DEFF Research Database (Denmark)

2015-01-01

An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

Downstream gas processing opportunities arising from the 1990's quest for a quality environment

International Nuclear Information System (INIS)

Geren, P.M.

1992-01-01

Over the last several years the former wart on your favorite daughter's nose (gas liquids processing) has become a most cherished body part, to paraphrase 1991 remarks of a U.S. gas processing leader. The dramatic recent spreads between liquids prices and the cost of feedstock natural gas have provided spectacular performance for processors. However, market prices for liquids will probably track petroleum. One day soon natural gas's inherent value will rise to parity with petroleum on a heating value basis. As petroleum demands will probably be flat in the foreseeable term, and natural gas prices will rise, something must be done to preserve gas processors' margins. Radical change in the formulation of U.S. gasoline presents many opportunities for gas processor to diversify into synthesis of upgraded derivatives of natural gas and liquids, which derivatives have high value-added characteristics. Issues relating to the selection of derivatives, the required technology, and capital project considerations are discussed in this paper

Analysis of factors influencing China's accession to the GPA

OpenAIRE

Meng, Ye

2008-01-01

China, with a huge market in government procurement, submitted an application to join the WTO GPA and formally began the negotiating process with the other signatories to the Agreement while the current parties were revising the 1994 GPA. International trade is not simply the outcome of market forces, of relative supply and demand. Rather, it is the result of a complex and interlocking network of bargains that are partly economic and partly political. This article discusses the main factors i...

Sensitometric control of roentgen film processors

International Nuclear Information System (INIS)

Forsberg, H.; Karolinska Sjukhuset, Stockholm

1987-01-01

Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

Special purpose processors for high energy physics applications

International Nuclear Information System (INIS)

Verkerk, C.

1978-01-01

The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

The Central Trigger Processor (CTP)

CERN Multimedia

Franchini, Matteo

2016-01-01

The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

X-ray absorption spectroscopy of GeO2 glass to 64 GPa

International Nuclear Information System (INIS)

Hong, Xinguo; Newville, Matthew; Sutton, Stephen R; Rivers, Mark L; Duffy, Thomas S

2014-01-01

The structural behavior of GeO 2 glass has been investigated up to 64 GPa using results from x-ray absorption spectroscopy in a diamond anvil cell combined with previously reported density measurements. The difference between the nearest Ge–O distances of glassy and rutile-type GeO 2 disappears at the Ge–O distance maximum at 20 GPa, indicating completion of the tetrahedral–octahedral transition in GeO 2 glass. The mean-square displacement σ 2 of the Ge–O distance in the first Ge–O shell increases progressively to a maximum at 10 GPa, followed by a substantial reduction at higher pressures. The octahedral glass is, as expected, less dense and has a higher compressibility than the corresponding crystalline phase, but the differences in Ge–O distance and density between the glass and the crystals are gradually eliminated over the 20–40 GPa pressure range. Above 40 GPa, GeO 2 forms a dense octahedral glass with a compressibility similar to that of the corresponding crystalline phase (α-PbO 2 type). The EXAFS and XANES spectra show evidence for subtle changes in the dense glass continuing to occur at these high pressures. The Ge–O bond distance shows little change between 45–64 GPa, and this may reflect a balance between bond shortening and a gradual coordination number increase with compression. The density of the glass is similar to that of the α–PbO 2 -type phase, but the Ge–O distance is longer and is close to that in the higher-coordination pyrite-type phase which is stable above ∼60 GPa. The density data provide evidence for a possible discontinuity and change in compressibility at 40–45 GPa, but there are no major changes in the corresponding EXAFS spectra. A pyrite-type local structural model for the glass can provide a reasonable fitting to the XAFS spectra at 64 GPa. (paper)

Phase transitions to 120 GPa for shock-compressed pyrolytic and hot-pressed boron nitride

International Nuclear Information System (INIS)

Gust, W.H.; Young, D.A.

1977-01-01

Shock-compression characteristics of two types of hexagonal graphitelike boron nitride have been investigated. Highly oriented very pure pyrolytic boron nitride exhibits shock-velocity versus particle-velocity discontinuities that appear to be manifestations of the initiation of a sluggish phase transition. This transition begins at 20 GPa and is driven to completion (melting) at 75 GPa. Discontinuities in the plot for impure hot-pressed boron nitride indicate initiation at 10 GPa and completion at 20 GPa. The (U/sub s/, U/sub p/) plots follow essentially the same paths for 4.0 < U/sub p/ < 5.2 km/sec. No evidence for a transition to a metalliclike state was seen. Temperature calculations indicate that the material is liquid above approx.80 GPa

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

Science.gov (United States)

Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junmin; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

2017-08-01

The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC), KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1) updating the pure Message Passing Interface (MPI) parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2) fully employing the 512 bit wide vector processing units (VPUs) on the KNL platform; (3) reducing unnecessary memory access to improve cache efficiency; (4) reducing the thread local storage (TLS) in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5) changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined performance and energy

Compression of ThC to 50 GPa

International Nuclear Information System (INIS)

Gerward, L.; Staun Olsen, J.; Benedict, U.; Luo, H.

1990-01-01

Thorium monocarbide crystallizes in the NaCl type structure (space group Fmanti 3m) at room temperature and atmospheric pressure. Very little has been published on the structural high-pressure behaviour of this compound. In a previous study ThC was compressed to 36 GPa and the bulk modulus B 0 was determined. No phase transformation was observed in contrast to the case of the corresponding uranium compound UC, which transforms to an orthorhombic structure at about 27 GPa. It has been suggested that the B 0 value might be too low, considering the bulk modulus scaling with specific volume for thorium and uranium compounds. Thus it should be useful to confirm the B 0 value for ThC and to look for structural phase transformations in an extended pressure range. (orig.)

Experimental testing of the noise-canceling processor.

Science.gov (United States)

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

New directions in gas processing

International Nuclear Information System (INIS)

Anon.

1996-01-01

Papers presented at the Insight conference held on January 30, 1996 in Calgary, Alberta, were contained in this volume. The conference was devoted to a discussion of new directions in the gas processing business, the changing business environment, new processing technologies, and means by which current facilities agreements can be adapted to the new commercial reality. High operating costs which have resulted in the downsizing and restructuring of the industry, and partnering with a third party in the gathering and processing operations, with apparently beneficial result both to plant owners, as well to third party processors, received the most attention. The relationship between the gas processor and the gas producer as they relate to the Petroleum Joint Venture Association (PJVA) Gas Processing Agreement, which defines the obligations of third parties, was the center of discussion. Regulatory changes and the industry's response to the changes was also on the agenda. Refs., tabs., figs

Thermoelectric power of YBa2Cu3Osub(7-δ) under pressure upto 9GPa

International Nuclear Information System (INIS)

Ramasesha, S.K.; Singh, A.K.

1991-01-01

Thermoelectric power (TEP) of two YBa 2 Cu 3 Osub(7-δ) compounds (with δ=0.17 and 0.21) was measured as a function of quasi-hydrostatic pressure up to 9GPa at 300 K on samples with low porosity. In both cases TEP decreases with increasing pressure, at a rate ∼0.8μVK -1 /GPa. The data obtained under hydrostatic pressure up to 3 GPa are in good agreement with those under quasi-hydrostatic pressure. The TEP of both compositions is found to decrease linearly at a rate 0.8 μVK -1 /GPa above 1.5 GPA. (author). 17 refs

Development of a highly reliable CRT processor

International Nuclear Information System (INIS)

Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

1996-01-01

Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

Computer Generated Inputs for NMIS Processor Verification

International Nuclear Information System (INIS)

J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

2001-01-01

Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

3081//sub E/ processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

1983-03-01

Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

Multimode power processor

Science.gov (United States)

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

PixonVision real-time video processor

Science.gov (United States)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

Processors and systems (picture processing)

Energy Technology Data Exchange (ETDEWEB)

Gemmar, P

1983-01-01

Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

Compact gasoline fuel processor for passenger vehicle APU

Science.gov (United States)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

High-pressure EXAFS study of vitreous GeO2 up to 44 GPa

International Nuclear Information System (INIS)

Baldini, M.; Aquilanti, G.; Mao, H-k.; Yang, W.; Shen, G.; Pascarelli, S.; Mao, W. L.

2010-01-01

High-pressure extended x-ray absorption fine-structure measurements were performed on amorphous GeO 2 over increasing and decreasing pressure cycles at pressures up to 44 GPa. Several structural models based on crystalline phases with fourfold, fivefold, and sixfold coordination were used to fit the Ge-O first shell. The Ge-O bond lengths gradually increased up to 30 GPa. Three different pressure regimes were identified in the pressure evolution of the Ge-O bond distances. Below 13 GPa, the local structure was well described by a fourfold 'quartzlike' model whereas a disordered region formed by a mixture of four- and five-coordinated germanium-centered polyhedra was observed in the intermediate pressure range between 13 and 30 GPa. Above 30 GPa the structural transition to the maximum coordination could be considered complete. The present results shed light on the GeO 2 densification process and on the nature of the amorphous-amorphous transition, suggesting that the transition is more gradual and continuous than what has been previously reported.

Special processor for in-core control systems

International Nuclear Information System (INIS)

Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

1978-01-01

The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

Functional Verification of Enhanced RISC Processor

OpenAIRE

SHANKER NILANGI; SOWMYA L

2013-01-01

This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

Effect of processor temperature on film dosimetry

International Nuclear Information System (INIS)

Srivastava, Shiv P.; Das, Indra J.

2012-01-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

The world economy: Its impact on the gas processing industry

International Nuclear Information System (INIS)

Teleki, A.

1994-01-01

Gas processors are in the business of extracting C 2-7 hydrocarbons from natural gas streams and converting them to commercial grade gas liquids, valued at or slightly below oil product prices. If the margin of oil prices over gas prices is higher, the gas processing business is more profitable. An approximate index of profitability is the ratio of the price of a bbl of oil divided by the price of a million Btu of gas (the oil-gas ratio). Since the mid-1980s, by which time both the oil and gas markets had been largely deregulated, the oil-gas ratio fluctuated in the 10-12 range then peaked to over 15 in 1990-91. The recent fall in oil prices has driven the ratio to historically low levels of 6-7, which leads to gas processors curtailing ethane recovery. Various aspects of the world economy and the growth of oil consumption are discussed to forecast their effect on gas processors. It is expected that oil demand should grow at least 4% annually over 1994-98, due to factors including world economic growth and low energy prices. Oil prices are forecast to bottom out in late 1995 and rise thereafter to the mid-20 dollar range by the end of the 1990s. A close supply-demand balance could send short-term prices much higher. Some widening of the gas-oil ratio should occur, providing room for domestic natural gas prices to rise, but with a lag. 8 figs

Shock wave response of ammonium perchlorate single crystals to 6 GPa

International Nuclear Information System (INIS)

Yuan, G.; Feng, R.; Gupta, Y. M.; Zimmerman, K.

2000-01-01

Plane shock wave experiments were carried out on ammonium perchlorate single crystals compressed along [210] and [001] orientations to peak stresses ranging from 1.2 to 6.2 GPa. Quartz gauge and velocity interferometer techniques were used to measure the elastic and plastic shock wave velocities, and stress and particle velocity histories in the shocked samples. The measured Hugoniot elastic limit (HEL) was 0.48±0.09 GPa. Above the HEL and up to about 6 GPa, the data show a clear two-wave structure, indicating an elastic-plastic response. Time-dependent elastic precursor decay and plastic wave ramping are discernable and orientation dependent in the low stress data. However, the orientation dependence of the peak state response is small. Hence, data for both orientations were summarized into a single isotropic, elastic-plastic-stress relaxation model. Reasonable agreement was obtained between the numerical simulations using this model and the measured wave profiles. At a shock stress of about 6 GPa and for the time duration and crystal orientations examined, we did not observe any features that may be identified as a sustained chemical reaction or a phase transformation. (c) 2000 American Institute of Physics

Bank switched memory interface for an image processor

International Nuclear Information System (INIS)

Barron, M.; Downward, J.

1980-09-01

A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

VON WISPR Family Processors: Volume 1

National Research Council Canada - National Science Library

Wagstaff, Ronald

1997-01-01

...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

Solid-state phase transitions in CuCl under hydrostatic pressures to 12.8 GPa

International Nuclear Information System (INIS)

Liebenberg, D.H.; Mills, R.L.; Huang, C.Y.; Olsen, C.; Schmidt, L.C.

1981-01-01

The phase transitions in solid CuCl under hydrostatic conditions at pressures to 12.8 GPa are examined. The transition at 4.4 GPa from zinc-blende to tetragonal is observed. Our negative observations for the upper transition at 8.2 GPa and for the formation of an opaque phase due to the disproportionation reaction support the contention that pressure gradients are important in affecting the behavior of pure CuCl

Many - body simulations using an array processor

International Nuclear Information System (INIS)

Rapaport, D.C.

1985-01-01

Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS on Intel Xeon Phi processors

Directory of Open Access Journals (Sweden)

H. Wang

2017-08-01

Full Text Available The Global Nested Air Quality Prediction Modeling System (GNAQPMS is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS, which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL. Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC, KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1 updating the pure Message Passing Interface (MPI parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2 fully employing the 512 bit wide vector processing units (VPUs on the KNL platform; (3 reducing unnecessary memory access to improve cache efficiency; (4 reducing the thread local storage (TLS in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5 changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined

Multi-processor network implementations in Multibus II and VME

International Nuclear Information System (INIS)

Briegel, C.

1992-01-01

ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

Structural transformation of compressed solid Ar: An x-ray diffraction study to 114 GPa

International Nuclear Information System (INIS)

Errandonea, D.; Boehler, R.; Japel, S.; Mezouar, M.; Benedetti, L. R.

2006-01-01

Room temperature angle-dispersive x-ray diffraction measurements on solid Ar up to 114 GPa reveal evidence of a structural phase transformation after stress relaxation by laser heating. Beyond 49.6 GPa, Ar exhibits the coexistence of fcc and hcp phases with an increasing hcp/fcc ratio, similar to the observation made recently on krypton and xenon. From the present results, we estimate the fcc-to-hcp transition to be completed at 300 GPa

Evaluation of the Intel Sandy Bridge-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2012-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

Array processors based on Gaussian fraction-free method

Energy Technology Data Exchange (ETDEWEB)

Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

1998-03-01

The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

Multiple Embedded Processors for Fault-Tolerant Computing

Science.gov (United States)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Online track processor for the CDF upgrade

International Nuclear Information System (INIS)

Thomson, E. J.

2002-01-01

A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

Design Principles for Synthesizable Processor Cores

DEFF Research Database (Denmark)

Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

2012-01-01

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

A High-Pressure Study of Manganese Metal and its Reactions with CO2 at 6, 23, and 44 GPa

Science.gov (United States)

Sawchuk, K. L. S.; McGuire, C. P.; Greenburg, A.; Makhluf, A.; Kavner, A.

2017-12-01

The free energies of formation of oxides and carbonates at the extreme pressures and temperatures of Earth's interior provides some of the thermodynamic constrains for models of mantle/core formation and subsequent chemical evolution. The broad goal of our research program is to measure the pressure- and temperature-dependence of free energies of formation of transition metal oxides and carbonates. This requires measurements of the phase stability, density, and thermoelastic properties of metals, oxides, and carbonates at deep-Earth and planetary conditions. Manganese is of interest because it is one of the most abundant transition metal geochemical tracers, it readily forms a carbonate at ambient pressure, and its high-pressure carbonate and oxide densities and equation of state parameters are relatively unknown. Here we report new data on the pressure/volume equation of state and structure of manganese metal as well as its reactions with CO2. These measurements were made using a laser heated diamond anvil cell in conjunction with synchrotron-based X-ray diffraction at beamline 12.2.2 at the Advanced Light Source. Three samples of manganese metal were gas-loaded in a CO2 pressure medium and pressurized to 6, 23, and 44 GPa. Upon laser heating, the CO2 reacted with the Mn metal generating new phases. To analyze the diffraction patterns, we we use a python-based program developed in-house for extracting high resolution 2-dimensional diffraction peak position and intensity information from two-dimensional X-ray diffraction patterns. At each pressure step, the structure and density of the quenched Mn metal phase was determined. At 6 GPa, Mn metal adopts a BCC structure, and at 23 GPa a tetragonal distortion is observed in the lattice. The measured equation of state is in good agreement with an existing meaurement by Fujihisa and Takemura (1995). MnCO3 rhodochrosite is observed in the sample quenched after heating at 6 GPa. Additional high pressure phases are evident

Data register and processor for multiwire chambers

International Nuclear Information System (INIS)

Karpukhin, V.V.

1985-01-01

A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

Calculated Phase Relations in the System KFMASH Between 6 and 16 GPa

Science.gov (United States)

Massonne, H.; Brandelik, A.

2005-12-01

To better understand the modal compositions of deeply buried metagranitoids and metapelites, phase relations in the model system K2O-FeO-MgO-Al2O3-SiO2-H2O (KFMASH) with SiO2 in excess were calculated applying thermodynamic principles. We used the software package PTGIBBS, published data, and thermodynamic data (e.g. for phase egg (AlSiO3OH), K-hollandite (KAlSi3O8)) newly derived on the basis of former high-pressure (HP) experiments. Non-ideal mixing was considered for the solid solution series of garnet (components: pyrope, majorite, almandine) and potassic white mica (components: muscovite, MgAl-celadonite, FeAl-celadonite). For phases such as HP-clinoenstatite ((Mg,Fe)SiO3), Si-spinel ((Fe,Mg)2SiO4), and beta phase ((Mg,Fe)2SiO4) only binary solid solutions, assuming ideal mixing, were taken into account. On the basis of the above data, we constructed petrogenetic grids mainly for the P-T range 6 to 16 GPa and 600 to 1600 ° C. Typical features of these grids are, for instance, the disappearance of K-cymrite (KAlSi3O8 H2O) with rising pressure close to 10 GPa and the occurrence of phase egg above 12 GPa. In KMASH potassic white mica reacts with OH-topaz at about 11 GPa (1000-1200 ° C) to form pyrope + K-hollandite. The content of majorite component in pyrope is less than 1 mol% which is systematically so for all garnets coexisting with an Al-silicate at least up to 16 GPa. Potassic white mica, which is virtually pure MgAl-celadonite, finally breaks down at pressures close to 12 GPa. Decomposition assemblages are K-hollandite + HP-clinoenstatite + H2O (T free) garnet + Al-silicate. The latter phase is either OH-topaz (Al2SiO4(OH)2) or phase egg or kyanite also depending on the availability of H2O. Metagranitoids should be composed of shishovite + K-hollandite + majorite-bearing garnet + (enstatite-rich) clinopyroxene. Si-spinel is an important additional phase in this assemblage. This phase shows increasing amounts by approaching to 16 GPa.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

International Nuclear Information System (INIS)

Clark, D.L.

1983-01-01

The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

Embedded Processor Laboratory

Data.gov (United States)

Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

Science.gov (United States)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Architectural design and analysis of a programmable image processor

International Nuclear Information System (INIS)

Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

2003-01-01

In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

Analytical Bounds on the Threads in IXP1200 Network Processor

OpenAIRE

Ramakrishna, STGS; Jamadagni, HS

2003-01-01

Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

A UNIX-based prototype biomedical virtual image processor

International Nuclear Information System (INIS)

Fahy, J.B.; Kim, Y.

1987-01-01

The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

The communication processor of TUMULT-64

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Jansen, P.G.

1988-01-01

Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

Accuracies Of Optical Processors For Adaptive Optics

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1992-01-01

Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

Making CSB + -Trees Processor Conscious

DEFF Research Database (Denmark)

Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

2005-01-01

of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

Lipsi: Probably the Smallest Processor in the World

DEFF Research Database (Denmark)

Schoeberl, Martin

2018-01-01

While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

Recommending the heterogeneous cluster type multi-processor system computing

International Nuclear Information System (INIS)

Iijima, Nobukazu

2010-01-01

Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

Shock-wave compression of lithium niobate from 2.4 to 44 GPa

International Nuclear Information System (INIS)

Stanton, P.L.; Graham, R.A.

1979-01-01

Shock compression of lithium niobate above the Hugoniot elastic limit (about 2.5 GPa) reveals a succession of unusual features. Just above the Hugoniot elastic limit, the shock velocity is observed to be well below the bulk sound speed, indicative of a drastic reduction of shear strength. The shock velocity is observed to increase with particle velocity at an unusually large rate due to the reduction of strength in a very stiff material and an anomalously large pressure derivative of the bulk modulus. This later behavior may be due to the effects of localized shock heating resulting from heterogeneous shear deformation in ferroelectrics like lithium niobate and lithium tantalate in which increases in temperature are shown to have a strong effect on bulk modulus. A shock-induced polymorphic phase transition occurs at 13.9 GPa. Above the transition point the slope of the Hugoniot curve relating shock velocity and particle velocity is unusually low, indicative of a broad mixed phase region of undetermined extent. Limited work is reported on the isomorphous crystal, lithium tantalate, which exhibits features similar to lithium niobate with a Hugoniot elastic limit of 4 GPa and a phase transition in the vicinity of 19 GPa

First level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

First-level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

A digital retina-like low-level vision processor.

Science.gov (United States)

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

High pressure in situ X-ray diffraction study of MnO to 137 GPa and comparison with shock compression experiment

Science.gov (United States)

Yagi, T.; Kondo, T.; Syono, Y.

1998-07-01

In order to clarify the nature of the phase transformation in MnO observed at around 90 GPa by shock compression experiment, high pressure in situ X-ray observations were carried out up to 137 GPa. Powdered sample was directly compressed in Mao-Bell type diamond anvil cell and X-ray experiments were carried out using angle dispersive technique by combining synchrotron radiation and imaging plate detector. Distortion of the B1 structured phase was observed above about 40 GPa, which continues to increase up to 90 GPa. Two discontinuous changes of the diffraction profiles were observed at around 90 GPa and 120 GPa. The nature of the intermediate phase between 90 GPa and 120 GPa is not clear yet. It is neither cesium chloride (B2) nor nickel arsenide (B8) structure. On the other hand, the diffraction profile above 120 GPa can be reasonably well explained by the B8 structure. High pressure phases above 90 GPa have metallic luster and all the transformations are reversible on release of pressure.

Median and Morphological Specialized Processors for a Real-Time Image Data Processing

Directory of Open Access Journals (Sweden)

Kazimierz Wiatr

2002-01-01

Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

Java Processor Optimized for RTSJ

Directory of Open Access Journals (Sweden)

Tu Shiliang

2007-01-01

Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

Stability range and decomposition of potassic richterite and phlogopite end members at 5-15 GPa

International Nuclear Information System (INIS)

Troennes, R.G.

2002-01-01

The phase relations of K-richterite, KNaCaMg 5 Si 8 O 22 (OH) 2 , and phlogopite, K 3 Mg 6 Al 2 Si O20 (OH) 2 , have been investigated at pressures of 5-15 GPa and temperatures of 1000-1500 o C. K-richterite is stable to about 1450 o C at 9-10 GPa, where the dp/dT-slope of the decomposition curve changes from positive to negative. At 1000 o C the alkali-rich, low-Al amphibole is stable to more than 14 GPa. Phlogopite has a more limited stability range with a maximum thermal stability limit of 1350 o C at 4-5 GPa and a pressure stability limit of 9-10 GPa at 1000 o C. The high-pressure decomposition reactions for both of the phases produce relatively small amounts of highly alkaline water-dominated fluids, in combination with mineral assemblages that are relatively close to the decomposing hydrous phase in bulk composition. In contrast, the incongruent melting of K-richterite and phlogopite in the 1-3 GPa range involves a larger proportion of hydrous silicate melts. The K-richterite breakdown produces high-Ca pyroxene and orthoenstatite or clinoenstatite at all pressures above 4 GPa. At higher pressures additional phases are: wadeite-structured K 2 Si VI Si IV 3 O 9 at 10 GPa and 1500 o C, wadeite-structured K 2 Si VI Si IV 3 O 9 and phase X at 15 GPa and 1500 o C, and stishovite at 15 GPa and 1100 o C. The solid breakdown phases of phlogopite are dominated by pyrope and forsterite. At 9-10 GPa and 1100-1400 o C phase X is an additional phase, partly accompanied by clinoenstatite close to the decomposition curve. Phase X has variable composition. In the KCMSH-system (K 2 CaMg 5 Si 8 O 22 (OH) 2 ) investigated by Inoue et al. (1998) and in the KMASH-system investigated in this report the compositions are approximately K 4 Mg 8 Si 8 O 25 (OH) 2 and K 3.7 Mg 7.4 Al 0.6 Si 8.0 O 25 (OH) 2 , respectively. Observations from natural compositions and from the phlogopite-diopside system indicate that phlogopite-clinopyroxene assemblages are stable along common geothermal

Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

International Nuclear Information System (INIS)

Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

1983-01-01

This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

The cyst nematode SPRYSEC protein RBP-1 elicits Gpa2- and RanGAP2-dependent plant cell death.

Directory of Open Access Journals (Sweden)

Melanie Ann Sacco

2009-08-01

Full Text Available Plant NB-LRR proteins confer robust protection against microbes and metazoan parasites by recognizing pathogen-derived avirulence (Avr proteins that are delivered to the host cytoplasm. Microbial Avr proteins usually function as virulence factors in compatible interactions; however, little is known about the types of metazoan proteins recognized by NB-LRR proteins and their relationship with virulence. In this report, we demonstrate that the secreted protein RBP-1 from the potato cyst nematode Globodera pallida elicits defense responses, including cell death typical of a hypersensitive response (HR, through the NB-LRR protein Gpa2. Gp-Rbp-1 variants from G. pallida populations both virulent and avirulent to Gpa2 demonstrated a high degree of polymorphism, with positive selection detected at numerous sites. All Gp-RBP-1 protein variants from an avirulent population were recognized by Gpa2, whereas virulent populations possessed Gp-RBP-1 protein variants both recognized and non-recognized by Gpa2. Recognition of Gp-RBP-1 by Gpa2 correlated to a single amino acid polymorphism at position 187 in the Gp-RBP-1 SPRY domain. Gp-RBP-1 expressed from Potato virus X elicited Gpa2-mediated defenses that required Ran GTPase-activating protein 2 (RanGAP2, a protein known to interact with the Gpa2 N terminus. Tethering RanGAP2 and Gp-RBP-1 variants via fusion proteins resulted in an enhancement of Gpa2-mediated responses. However, activation of Gpa2 was still dependent on the recognition specificity conferred by amino acid 187 and the Gpa2 LRR domain. These results suggest a two-tiered process wherein RanGAP2 mediates an initial interaction with pathogen-delivered Gp-RBP-1 proteins but where the Gpa2 LRR determines which of these interactions will be productive.

New development for low energy electron beam processor

International Nuclear Information System (INIS)

Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

2003-01-01

Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

GPA and Attribute Framing Effects: Are Better Students More Sensitive or More Susceptible?

Science.gov (United States)

Dunegan, Ken

2010-01-01

Data from 2 studies show students differ in terms of how attribute framing alters perceptions and reactions in a decision-making episode. Using student GPA as a moderator, results from a role-play-decision-making exercise (Experiment 1) show perceptions and intended actions of higher GPA students were more strongly affected by attribute framing…

Laser driven single shock compression of fluid deuterium from 45 to 220 GPa

Energy Technology Data Exchange (ETDEWEB)

Hicks, D; Boehly, T; Celliers, P; Eggert, J; Moon, S; Meyerhofer, D; Collins, G

2008-03-23

The compression {eta} of liquid deuterium between 45 and 220 GPa under laser-driven shock loading has been measured using impedance matching to an aluminum (Al) standard. An Al impedance match model derived from a best fit to absolute Hugoniot data has been used to quantify and minimize the systematic errors caused by uncertainties in the high-pressure Al equation of state. In deuterium below 100 GPa results show that {eta} {approx_equal} 4.2, in agreement with previous impedance match data from magnetically-driven flyer and convergent-explosive shock wave experiments; between 100 and 220 GPa {eta} reaches a maximum of {approx}5.0, less than the 6-fold compression observed on the earliest laser-shock experiments but greater than expected from simple extrapolations of lower pressure data. Previous laser-driven double-shock results are found to be in good agreement with these single-shock measurements over the entire range under study. Both sets of laser-shock data indicate that deuterium undergoes an abrupt increase in compression at around 110 GPa.

Water solubility of synthetic pyrope at high temperature and pressure up to 12GPa

Science.gov (United States)

Huang, S.; Chen, J.

2012-12-01

Water can be incorporated into normally anhydrous minerals as OH- defects and transported into the mantle. Its existence in the mantle may affect property of minerals, such as elasticity, electrical conductivity and rheological properties. As the secondary mineral in the mantle, garnet has not been extensively studied for its water solubility and there is discrepancies among the existing experiments on the water solubility in the garnet change at pressures and temperatures. Geiger et al., 1991 investigated water content in synthetic pyrope and concluded 0.02wt% to 0.07wt% OH- substitution. Lu et al., 1997 found 198ppm water in the Dora Miara pyrope at 100Kbar and 1000°C. Withers et al., 1998 claimed that water solubility in pyrope reached 1000ppm at 5GPa and then decreased as pressure increasing; above 7GPa, no water was detected. Mookherjee et al., 2009 also explored pyrope-rich garnet, which contains water up to 0.1%wt at 5-9GPa and temperatures 1373K-1473K. Here we report a study of water solubility of synthetic single crystal pyrope at pressures 4-12GPa and temperature 1000°C. Single crystals of pyrope were synthesized using multi-anvil press and water contents in these samples were measured using FTIR. We have observed OH- peak at 3650 cm-1 along this pressure range, although Withers, 1998 reported water contents decrease to undetectable level above 7GPa. Water solubility in pyrope will be reported as a function of pressure up to 12 GPa at 1000°C.

A data base processor semantics specification package

Science.gov (United States)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

Globe hosts launch of new processor

CERN Multimedia

2006-01-01

Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

XL-100S microprogrammable processor

International Nuclear Information System (INIS)

Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

1983-01-01

The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

Science.gov (United States)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Simulation of a processor switching circuit with APLSV

International Nuclear Information System (INIS)

Dilcher, H.

1979-01-01

The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

Accuracy Limitations in Optical Linear Algebra Processors

Science.gov (United States)

Batsell, Stephen Gordon

1990-01-01

One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

International Nuclear Information System (INIS)

Maenner, R.; Deluigi, B.

1981-01-01

The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

A dedicated line-processor as used at the SHF

International Nuclear Information System (INIS)

Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

1985-01-01

A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

Saturation curve of SiO2 component in rutile-type GeO2: A recoverable high-temperature pressure standard from 3 GPa to 10 GPa

International Nuclear Information System (INIS)

Leinenweber, Kurt; Gullikson, Amber L.; Stoyanov, Emil; Malik, Abds-Sami

2015-01-01

The accuracy and precision of pressure measurements and the pursuit of reliable and readily available pressure scales at simultaneous high temperatures and pressures are still topics in development in high pressure research despite many years of work. In situ pressure scales based on x-ray diffraction are widely used but require x-ray access, which is lacking outside of x-ray beam lines. Other methods such as fixed points require several experiments to bracket a pressure calibration point. In this study, a recoverable high-temperature pressure gauge for pressures ranging from 3 GPa to 10 GPa is presented. The gauge is based on the pressure-dependent solubility of an SiO 2 component in the rutile-structured phase of GeO 2 (argutite), and is valid when the argutite solid solution coexists with coesite. The solid solution varies strongly in composition, mainly in pressure but also somewhat in temperature, and the compositional variations are easily detected by x-ray diffraction of the recovered products because of significant changes in the lattice parameters. The solid solution is measured here on two isotherms, one at 1200 °C and the other at 1500 °C, and is developed as a pressure gauge by calibrating it against three fixed points for each temperature and against the lattice parameter of MgO measured in situ at a total of three additional points. A somewhat detailed thermodynamic analysis is then presented that allows the pressure gauge to be used at other temperatures. This provides a way to accurately and reproducibly evaluate the pressure in high pressure experiments and applications in this pressure-temperature range, and could potentially be used as a benchmark to compare various other pressure scales under high temperature conditions. - Graphical abstract: The saturation curve of SiO 2 in TiO 2 shows a strong pressure dependence and a strong dependence of unit cell volume on composition. This provides an opportunity to use this saturation curve as a

Embedded processor extensions for image processing

Science.gov (United States)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

Strike Four! Do-Over Policies Institutionalize GPA Distortion

Science.gov (United States)

Marx, Jonathan; Meeler, David

2013-01-01

Purpose: The aim of this paper is to illustrate how universities play an institutional role in inflating student grade point averages (GPA) by modifying academic polices such as course withdraw, repeats, and satisfactory/unsatisfactory grade options. Design/methodology/approach: Three research strategies are employed: an examination of eight…

Sojourn time tails in processor-sharing systems

NARCIS (Netherlands)

Egorova, R.R.

2009-01-01

The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

An interactive parallel processor for data analysis

International Nuclear Information System (INIS)

Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

1984-01-01

A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

Optical Array Processor: Laboratory Results

Science.gov (United States)

Casasent, David; Jackson, James; Vaerewyck, Gerard

1987-01-01

A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

OpenAIRE

Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

2016-01-01

International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

Hardware trigger processor for the MDT system

CERN Document Server

AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

2017-01-01

We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

High pressure studies up to 50 GPa of Bi-based high-Tc superconductors

International Nuclear Information System (INIS)

Staun Olsen, J.; Steenstrup, S.; Gerward, L.; Sundqvist, B.

1991-01-01

The high-T c superconductor with nominal composition BiSrCaCu 2 O x has been studied at high pressure, i.e. up to 50 GPa. A tetragonal structure was compatible with the measurements at all pressures, and no phase change was observed. The bulk modulus, B o =62.5 GPa, obtained has a somewhat smaller value than the one estimated earier. (orig.)

Towards a Process Algebra for Shared Processors

DEFF Research Database (Denmark)

Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

2002-01-01

We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

High-speed packet filtering utilizing stream processors

Science.gov (United States)

Hummel, Richard J.; Fulp, Errin W.

2009-04-01

Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

Contaminant Permeation in the Ionomer-Membrane Water Processor (IWP) System

Science.gov (United States)

Kelsey, Laura K.; Finger, Barry W.; Pasadilla, Patrick; Perry, Jay

2016-01-01

The Ionomer-membrane Water Processor (IWP) is a patented membrane-distillation based urine brine water recovery system. The unique properties of the IWP membrane pair limit contaminant permeation from the brine to the recovered water and purge gas. A paper study was conducted to predict volatile trace contaminant permeation in the IWP system. Testing of a large-scale IWP Engineering Development Unit (EDU) with urine brine pretreated with the International Space Station (ISS) pretreatment formulation was then conducted to collect air and water samples for quality analysis. Distillate water quality and purge air GC-MS results are presented and compared to predictions, along with implications for the IWP brine processing system.

High-pressure X-ray diffraction studies on ThS up to 40 GPa using synchrotron radiation

International Nuclear Information System (INIS)

Benedict, U.; Spirlet, J.C.; Gerward, L.; Olsen, J.S.

1983-12-01

High-pressure X-ray diffraction studies have been performed on ThS up to 40 GPa using synchrotron radiation and a diamond anvil cell. The measured value of the bulk modulus B 0 =145 GPa is in disagreement with a previous measurement. The high-pressure behaviour indicates a phase transformation to ThS II starting at 15 to 20 GPa. The transformation is of second order nature, the resulting structure can be described as distorted fcc. (orig.)

High pressure X-ray diffraction studies on ThS up to 40 GPa using synchrotron radiation

International Nuclear Information System (INIS)

Benedict, U.; Spirlet, J.C.; Gerward, L.; Olsen, J.S.

1984-01-01

High pressure X-ray diffraction studies (up to 40 GPa) were performed on ThS using synchrotron radiation and a diamond anvil cell. The measured value of 145 GPa for the bulk modulus B 0 disagrees with a previous measurement. The high pressure behaviour indicates a phase transformation to ThS II starting at 15 - 20 GPa. The transformation is of the second-order type, and the resulting structure can be described as distorted f.c.c. (Auth.)

The pressure-induced structural response of rare earth hafnate and stannate pyrochlore from 0.1-50 GPa

Science.gov (United States)

Turner, K. M.; Rittman, D.; Heymach, R.; Turner, M.; Tracy, C.; Mao, W. L.; Ewing, R. C.

2017-12-01

Complex oxides with the pyrochlore (A2B2O7) and defect-fluorite ((A,B)4O7) structure-types undergo structural transformations under high-pressure. These compounds are under consideration for applications including as a proposed waste-form for actinides generated in the nuclear fuel cycle. High-pressure transformations in rare earth hafnates (A2Hf2O7, A=Sm, Eu, Gd, Dy, Y, Yb) and stannates (A2Sn2O7, A=Nd, Gd, Er) were investigated to 50 GPa by in situ Raman spectroscopy and synchrotron x-ray diffraction (XRD). Rare-earth hafnates form the pyrochlore structure for A=La-Tb and the defect-fluorite structure for A=Dy-Lu. Lanthanide stannates form the pyrochlore structure. Raman spectra revealed that at ambient pressure all compositions have pyrochlore-type short-range order. Stannate compositions show a larger degree of pyrochlore-type short-range ordering relative to hafnates. In situ high-pressure synchrotron XRD showed that rare earth hafnates and stannates underwent a pressure-induced phase transition to a cotunnite-like (Pnma) structure that begins between 18-25 GPa in hafnates and between 30-33 GPa in stannates. The phase transition is not complete at 50 GPa, and upon decompression, XRD indicates that all compositions transform to defect-fluorite with an amorphous component. In situ Raman spectroscopy showed that disordering in stannates and hafnates occurs gradually upon compression. Pyrochlore-structured hafnates retain short-range order to a higher pressure (30 GPa vs. <10 GPa) than defect-fluorite-structured hafnates. Hafnates and stannates decompressed from 50 GPa show Raman spectra consistent with weberite-type structures, also reported in irradiated stannates. The second-order Birch-Murnaghan equation of state fit gives a bulk modulus of 250 GPa for hafnate compositions with the pyrochlore structure, and 400 GPa for hafnate compositions with the defect-fluorite structure. Stannates have a lower bulk modulus relative to hafnates (between 80-150 GPa

Fast processor for dilepton triggers

International Nuclear Information System (INIS)

Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

1983-01-01

We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

Design of RISC Processor Using VHDL and Cadence

Science.gov (United States)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Real time processor for array speckle interferometry

Science.gov (United States)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Parallelization of simulation code for liquid-gas model of lattice-gas fluid

International Nuclear Information System (INIS)

Kawai, Wataru; Ebihara, Kenichi; Kume, Etsuo; Watanabe, Tadashi

2000-03-01

A simulation code for hydrodynamical phenomena which is based on the liquid-gas model of lattice-gas fluid is parallelized by using MPI (Message Passing Interface) library. The parallelized code can be applied to the larger size of the simulations than the non-parallelized code. The calculation times of the parallelized code on VPP500 (Vector-Parallel super computer with dispersed memory units), AP3000 (Scalar-parallel server with dispersed memory units), and a workstation cluster decreased in inverse proportion to the number of processors. (author)

Vector and parallel processors in computational science

International Nuclear Information System (INIS)

Duff, I.S.; Reid, J.K.

1985-01-01

These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

Radial X-ray diffraction study of the static strength and equation of state of MoB2 to 85 GPa

International Nuclear Information System (INIS)

Xiong, Lun; Liu, Jing; Zhang, Xinxin; Tao, Qiang; Zhu, Pinwen

2015-01-01

Highlights: • α-MoB 2 powder synthesized under high pressure–temperature condition. • We have firstly investigated the equation of state of α-MoB 2 under uniaxial compression up to 85 GPa. • The complete elastic constant tensor of α-MoB 2 at high pressures up to 100 GPa are firstly calculated from density-functional theory (DFT). • We have investigated the strength of α-MoB 2 under uniaxial compression up to 85 GPa. - Abstract: Investigations of strength and equation of state of α-MoB 2 have been performed under nonhydrostatic compression up to 85 GPa using an angle-dispersive radial X-ray diffraction (RXD) techniques together with the lattice strain theory in a 2-fold panoramic diamond anvil cell at ambient temperature. The RXD data yields a bulk modulus and its pressure derivative as K 0 = 323(6) GPa with K 0 ′ = 4.59(27). The ratio of t/G is found to remain constant above ∼44 GPa, indicating that the α-MoB 2 started to experience yield with plastic deformation at this pressure. Together with theoretical results on high-pressure shear modulus, our results here show that molybdenum diborides sample could support a differential stress of ∼18 GPa when it started to yield with plastic deformation at ∼44 GPa under uniaxial compression. A maximum differential stress, as high as ∼25 GPa can be supported by molybdenum diborides at the high pressure of ∼85 GPa

MPC Related Computational Capabilities of ARMv7A Processors

DEFF Research Database (Denmark)

Frison, Gianluca; Jørgensen, John Bagterp

2015-01-01

In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

Air-Lubricated Thermal Processor For Dry Silver Film

Science.gov (United States)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

40 CFR 80.217 - How does a refiner or importer apply for the GPA standards?

Science.gov (United States)

2010-07-01

... annual average sulfur standard for gasoline produced for use in the GPA for the 2004 through 2006 annual... for gasoline produced for use in the GPA. (d) If EPA finds that a refiner or importer provided false... (CONTINUED) AIR PROGRAMS (CONTINUED) REGULATION OF FUELS AND FUEL ADDITIVES Gasoline Sulfur Geographic Phase...

Real time monitoring of electron processors

International Nuclear Information System (INIS)

Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

1995-01-01

A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

Fast track trigger processor for the OPAL detector at LEP

Energy Technology Data Exchange (ETDEWEB)

Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

1986-09-20

A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

Carbon nanohorns under cold compression to 40 GPa: Raman scattering and X-ray diffraction experiments

Science.gov (United States)

Li, Bo; Nan, Yanli; Zhao, Xiang; Song, Xiaolong; Li, Haining; Wu, Jie; Su, Lei

2017-11-01

We report a high-pressure behavior of carbon nanohorns (CNHs) to 40 GPa at ambient temperature by in situ Raman spectroscopy and synchrotron radiation x-ray diffraction (XRD) in a diamond anvil cell. In Raman measurement, multiple structural transitions are observed. In particular, an additional band at ˜1540 cm-1 indicative of sp3 bonding is shown above 35 GPa, but it reverses upon releasing pressure, implying the formation of a metastable carbon phase having both sp2 and sp3 bonds. Raman frequencies of all bands (G, 2D, D + G, and 2D') are dependent upon pressure with respective pressure coefficients, among which the value for the G band is as small as ˜2.65 cm-1 GPa-1 above 10 GPa, showing a superior high-pressure structural stability. Analysis based on mode Grüneisen parameter demonstrates the similarity of high-pressure behavior between CNHs and single-walled carbon nanotubes. Furthermore, the bulk modulus and Grüneisen parameter for the G band of CNHs are calculated to be ˜33.3 GPa and 0.1, respectively. In addition, XRD data demonstrate that the structure of post-graphite phase derives from surface nanohorns. Based on topological defects within conical graphene lattice, a reasonable transformation route from nanohorns to the post-graphite phase is proposed.

Multi-processor data acquisition and monitoring systems for particle physics

International Nuclear Information System (INIS)

White, V.; Burch, B.; Eng, K.; Heinicke, P.; Pyatetsky, M.; Ritchie, D.

1983-01-01

A high speed distributed processing system, using PDP-11 and VAX processors, is being developed at Fermilab. The acquisition of data is done using one or more PDP-11s. Additional processors are connected to provide either data logging or extra data analysis capabilities. Within this framework, functional interchangeability of PDP-11 and VAX processors and of the PDP-11 operating systems, RT-11 and RSX-11M, has been maintained. Inter-processor connections have been implemented in a general way using the 5 megabit DR11-W hardware currently selected for the purpose. Using this approach the authors have been able to make use of several existing data acquisition and analysis packages, such as RT/MULTI, in a multi-processor system

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

Science.gov (United States)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Optical backplane interconnect switch for data processors and computers

Science.gov (United States)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

Science.gov (United States)

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Fast digital processor for event selection according to particle number difference

International Nuclear Information System (INIS)

Basiladze, S.G.; Gus'kov, B.N.; Li Van Sun; Maksimov, A.N.; Parfenov, A.N.

1978-01-01

A fast digital processor for a magnetic spectrometer is described. It is used in experimental searches for charmed particles. The basic purpose of the processor is discriminating events in the difference of numbers of particles passing through two proportional chambers (PC). The processor consists of three units for detecting signals with PC, and a binary coder. The number of inputs of the processor is 32 for the first PC and 64 for the second. The difference in the number of particles discriminated is from 0 to 8. The resolution time is 180 ns. The processor is built in the CAMAC standard

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

Abscisic Acid–Responsive Guard Cell Metabolomes of Arabidopsis Wild-Type and gpa1 G-Protein Mutants[C][W

Science.gov (United States)

Jin, Xiaofen; Wang, Rui-Sheng; Zhu, Mengmeng; Jeon, Byeong Wook; Albert, Reka; Chen, Sixue; Assmann, Sarah M.

2013-01-01

Individual metabolites have been implicated in abscisic acid (ABA) signaling in guard cells, but a metabolite profile of this specialized cell type is lacking. We used liquid chromatography–multiple reaction monitoring mass spectrometry for targeted analysis of 85 signaling-related metabolites in Arabidopsis thaliana guard cell protoplasts over a time course of ABA treatment. The analysis utilized ∼350 million guard cell protoplasts from ∼30,000 plants of the Arabidopsis Columbia accession (Col) wild type and the heterotrimeric G-protein α subunit mutant, gpa1, which has ABA-hyposensitive stomata. These metabolomes revealed coordinated regulation of signaling metabolites in unrelated biochemical pathways. Metabolites clustered into different temporal modules in Col versus gpa1, with fewer metabolites showing ABA-altered profiles in gpa1. Ca2+-mobilizing agents sphingosine-1-phosphate and cyclic adenosine diphosphate ribose exhibited weaker ABA-stimulated increases in gpa1. Hormone metabolites were responsive to ABA, with generally greater responsiveness in Col than in gpa1. Most hormones also showed different ABA responses in guard cell versus mesophyll cell metabolomes. These findings suggest that ABA functions upstream to regulate other hormones, and are also consistent with G proteins modulating multiple hormonal signaling pathways. In particular, indole-3-acetic acid levels declined after ABA treatment in Col but not gpa1 guard cells. Consistent with this observation, the auxin antagonist α-(phenyl ethyl-2-one)-indole-3-acetic acid enhanced ABA-regulated stomatal movement and restored partial ABA sensitivity to gpa1. PMID:24368793

Development of multi-frequency ESR system for high-pressure measurements up to 2.5 GPa

Science.gov (United States)

Sakurai, T.; Fujimoto, K.; Matsui, R.; Kawasaki, K.; Okubo, S.; Ohta, H.; Matsubayashi, K.; Uwatoko, Y.; Tanaka, H.

2015-10-01

A new piston-cylinder pressure cell for electron spin resonance (ESR) has been developed. The pressure cell consists of a double-layer hybrid-type cylinder with internal components made of the ZrO2-based ceramics. It can generate a pressure of 2 GPa repeatedly and reaches a maximum pressure of around 2.5 GPa. A high-pressure ESR system using a cryogen-free superconducting magnet up 10 T has also been developed for this hybrid-type pressure cell. The frequency region is from 50 GHz to 400 GHz. This is the first time a pressure above 2 GPa has been achieved in multi-frequency ESR system using a piston-cylinder pressure cell. We demonstrate its potential by showing the results of the high-pressure ESR of the S = 1 system with the single ion anisotropy NiSnCl6 · 6H2O and the S = 1 / 2 quantum spin system CsCuCl3. We performed ESR measurements of these systems above 2 GPa successfully.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Science.gov (United States)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Directory of Open Access Journals (Sweden)

David R. W. Barr

2009-01-01

Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Phase diagram of antimony up to 31 GPa and 835 K

Science.gov (United States)

Coleman, A. L.; Stevenson, M.; McMahon, M. I.; Macleod, S. G.

2018-04-01

X-ray powder diffraction experiments using resistively heated diamond anvil cells have been conducted in order to establish the phase behavior of antimony up to 31 GPa and 835 K. The dip in the melting curve at 5.7 GPa and 840 K is identified as the triple point between the Sb-I, incommensurate Sb-II, and liquid phases. No evidence of the previously reported simple cubic phase was observed. Determination of the phase boundary between Sb-II and Sb-III suggests the existence of a second triple point in the region of 13 GPa and 1200 K. The incommensurate composite structure of Sb-II was found to remain ordered to the highest temperatures studies—no evidence of disordering of the guest-atom chains was observed. Indeed, the modulation reflections that arise from interactions between the host and guest subsystems were found to be present to the highest temperatures, suggesting such interactions remain relatively strong in Sb even in the presence of increased thermal motion. Finally, we show that the incommensurately modulated structure recently reported as giving an improved fit to diffraction data from incommensurate Ba-IV can be rejected as the structure of Sb-II using a simple density argument.

Control structures for high speed processors

Science.gov (United States)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Interpreting the Relationships between TOEFL iBT Scores and GPA: Language Proficiency, Policy, and Profiles

Science.gov (United States)

Ginther, April; Yan, Xun

2018-01-01

This study examines the predictive validity of the TOEFL iBT with respect to academic achievement as measured by the first-year grade point average (GPA) of Chinese students at Purdue University, a large, public, Research I institution in Indiana, USA. Correlations between GPA, TOEFL iBT total and subsection scores were examined on 1990 mainland…

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1989-10-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

High performance graphics processors for medical imaging applications

International Nuclear Information System (INIS)

Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

1989-01-01

This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

Evaluation of the Intel Westmere-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

Keystone Business Models for Network Security Processors

OpenAIRE

Arthur Low; Steven Muegge

2013-01-01

Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

Development of level 2 processor for the readout of TMC

International Nuclear Information System (INIS)

Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

1995-01-01

We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

Renegotiating ethane contracts from producer/processor perspectives

International Nuclear Information System (INIS)

Hawkins, D. J.

1997-01-01

An overview of commercial practices relating to ethane sup ply and other collateral issues, including the variety of technologies used in the recovery of ethane and the manufacture of ethylene was provided. Ethane supply and demand balances, the Alberta ethane supply, the justifications for ethane recovery, the need for renegotiating ethane contracts in view of the changing Alberta market, the major price components , producers and processors' objectives in ethane sales, the nature of ethane contracts, and ethane pricing mechanisms were reviewed. The 'Alberta Advantage' based on gas price, large-scale ethane recovery, proximity to the largest market in the world, efficient transportation and fractionation facilities, further enhanced by deregulation and reduced regulatory barriers, was described. It was suggested that the enhanced competition and increase in market diversity demands a transparency in pricing that may well be realized as additional players enter the petrochemical business, and as competing transportation, processing and fractionation options become available to ethane suppliers and purchasers.1 tab

Phase transformation in nanocrystalline α-quartz GeO2 up to 51.5 GPa

International Nuclear Information System (INIS)

Wang, H; Liu, J F; Wu, H P; He, Y; Chen, W; Wang, Y; Zeng, Y W; Wang, Y W; Luo, C J; Liu, J; Hu, T D; Stahl, K; Jiang, J Z

2006-01-01

The high-pressure behaviour of nanocrystalline α-quartz GeO 2 (q-GeO 2 ) with average crystallite sizes of 40 and 260 nm has been studied by in situ high-pressure synchrotron radiation x-ray diffraction measurements up to about 51.5 GPa at ambient temperature. Two phase transformations, q-GeO 2 to amorphous GeO 2 and amorphous GeO 2 to monoclinic GeO 2 , are detected. The onset and end of the transition pressures for the q-GeO 2 -to-amorphous GeO 2 phase transition are found to be approximately 10.8 and 14.9 GPa for the 40 nm q-GeO 2 sample, and 9.5 and 12.4 GPa for the 260 nm q-GeO 2 sample, respectively. The mixture of amorphous and monoclinic GeO 2 phases remains up to 51.5 GPa during compression and even after pressure release. This result strongly suggests that the difference of free energy between the amorphous phase and the monoclinic phase might be small. Consequently, defects in the starting material, which alter the free energies of the amorphous phase and the monoclinic phase, may play a key role for the phase transformation of q-GeO 2

Dynamics anomaly in high-density amorphous ice between 0.7 and 1.1 GPa

Science.gov (United States)

Handle, Philip H.; Loerting, Thomas

2016-02-01

We studied high-density amorphous ices between 0.004 and 1.6 GPa by isobaric in situ volumetry and by subsequent ex situ x-ray diffraction and differential scanning calorimetry at 1 bar. Our observations indicate two processes, namely, relaxation in the amorphous matrix and crystallization, taking place at well-separated time scales. For this reason, we are able to report rate constants of crystallization kX and glass-transition temperatures Tg in an unprecedented pressure range. Tg's agree within ±3 K with earlier work in the small pressure range where there is overlap. Both Tg and kX show a pressure anomaly between 0.7 and 1.1 GPa, namely, a kX minimum and a Tg maximum. This anomalous pressure dependence suggests a continuous phase transition from high- (HDA) to very-high-density amorphous ice (VHDA) and faster hydrogen bond dynamics in VHDA. We speculate this phenomenology can be rationalized by invoking the crossing of a Widom line between 0.7 and 1.1 GPa emanating from a low-lying HDA-VHDA critical point. Furthermore, we interpret the volumetric relaxation of the amorphous matrix to be accompanied by viscosity change to explain the findings such that the liquid state can be accessed prior to the crystallization temperature TX at 0.8 GPa.

Review of trigger and on-line processors at SLAC

International Nuclear Information System (INIS)

Lankford, A.J.

1984-07-01

The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

A technique for precise electrical-transport measurements under pressure above 10 GPa

Energy Technology Data Exchange (ETDEWEB)

Ohashi, M [Division of Civil and Enviromental Engineering, Kanazawa University, Kakuma-machi, Kanazawa 920-1192 (Japan)], E-mail: ohashi@t.kanazawa-u.ac.jp

2008-07-15

We report a technique for the precise measurement of electrical resistivity at high pressures up to 15 GPa by using Bridgman anvils. The relatively large size of the pressure chamber (1.0 mm in diameter) allows the use of large specimens and simple experimental procedures rather than using a standard diamond anvil cell. A SUS310 gasket is pressed by two tungsten carbide anvils. A sample with typical dimensions of approximately 0.5x0.2x0.1mm{sup 3} is placed in a small hole of the gasket. In order to obtain a quasi-hydrostatic pressure, the pressure chamber is filled with a 1:1 mixture of Fluorinert FC70 and FC77 as the pressure transmitting medium. Electrical leads are introduced through shallow grooves milled into the anvil. The grooves are filled with a mixture of alumina powder for insulation. Accurate data of the resistance values of Bi and Fe at room temperature are available. We observe sharp transitions for Bi at 2.55, 2.7 and 7.7 GPa. The electrical resistance of Fe shows a sudden increase due to a structural transition near 14 GPa.

Software-defined reconfigurable microwave photonics processor.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Designing a dataflow processor using CλaSH

NARCIS (Netherlands)

Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

2010-01-01

In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

Researching, building a soft-processor and Ethernet interface circuit using EDK

International Nuclear Information System (INIS)

Tuong Thi Thu Huong; Pham Ngoc Tuan; Truong Van Dat, Dang Lanh; Chau Thi Nhu Quynh

2014-01-01

The processor is an indispensable component in the measurement and automatic control systems. This report describes the fabrication of a soft-processor (32-bits, on-chip block RAM 64K, 50M clock, internal and peripheral bus) for receiving, sending and processing of data Ethernet packets. This processor is fabricated using the XPS component from EDK (Xilinx) software toolkit. After that, it is configured on the FPGA named Spartan XC3S500E circuit. A firmware of a processor for controlling the interface between processor and Ethernet port is written in C language and can play a role of a HOST (station) which has its own IP to connect to Ethernet network. Besides, there are some needed parts as follows: an Ethernet interfacing controller chip, a suitable cable providing a speed up to 100 Mbs and an application program running under Window XP environment written in LabView to communicate with soft-processor. (author)

A high-accuracy optical linear algebra processor for finite element applications

Science.gov (United States)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Self-diffusion of protons in H{sub 2}O ice VII at high pressures: Anomaly around 10 GPa

Energy Technology Data Exchange (ETDEWEB)

Noguchi, Naoki, E-mail: noguchi-n@okayama-u.ac.jp; Okuchi, Takuo [Institute for Planetary Materials, Okayama University, Misasa, Tottori 682-0193 (Japan)

2016-06-21

The self-diffusion of ice VII in the pressure range of 5.5–17 GPa and temperature range of 400–425 K was studied using micro Raman spectroscopy and a diamond anvil cell. The diffusion was monitored by observing the distribution of isotope tracers: D{sub 2}O and H{sub 2}{sup 18}O. The diffusion coefficient of hydrogen reached a maximum value around 10 GPa. It was two orders of magnitude greater at 10 GPa than at 6 GPa. Hydrogen diffusion was much faster than oxygen diffusion, which indicates that protonic diffusion is the dominant mechanism for the diffusion of hydrogen in ice VII. This mechanism is in remarkable contrast to the self-diffusion in ice I{sub h} that is dominated by an interstitial mechanism for the whole water molecule. An anomaly around 10 GPa in ice VII indicates that the rate-determining process for the proton diffusion changes from the diffusion of ionic defects to the diffusion of rotational defects, which was suggested by proton conductivity measurements and molecular dynamics simulations.

Low voltage 80 KV to 125 KV electron processors

International Nuclear Information System (INIS)

Lauppi, U.V.

1999-01-01

The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

A fast track trigger processor for the OPAL detector at LEP

International Nuclear Information System (INIS)

Carter, A.A.; Jaroslawski, S.; Wagner, A.

1986-01-01

A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented. (orig.)

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

Science.gov (United States)

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Satellite on-board real-time SAR processor prototype

Science.gov (United States)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

Particle simulation on a distributed memory highly parallel processor

International Nuclear Information System (INIS)

Sato, Hiroyuki; Ikesaka, Morio

1990-01-01

This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

Code compression for VLIW embedded processors

Science.gov (United States)

Piccinelli, Emiliano; Sannino, Roberto

2004-04-01

The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

Recursive Matrix Inverse Update On An Optical Processor

Science.gov (United States)

Casasent, David P.; Baranoski, Edward J.

1988-02-01

A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

Evaluation of the Intel Nehalem-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

Graphical user interface for TOUGH/TOUGH2 - development of database, pre-processor, and post-processor

Energy Technology Data Exchange (ETDEWEB)

Sato, Tatsuya; Okabe, Takashi; Osato, Kazumi [Geothermal Energy Research and Development Co., Ltd., Tokyo (Japan)

1995-03-01

One of the advantages of the TOUGH/TOUGH2 (Pruess, 1987 and 1991) is the modeling using {open_quotes}free shape{close_quotes} polygonal blocks. However, the treatment of three-dimensional information, particularly for TOUGH/TOUGH2 is not easy because of the {open_quotes}free shape{close_quotes} polygonal blocks. Therefore, we have developed a database named {open_quotes}GEOBASE{close_quotes} and a pre/post-processor named {open_quotes}GEOGRAPH{close_quotes} for TOUGH/TOUGH2 on engineering work station (EWS). {open_quotes}GEOGRAPH{close_quotes} is based on the ORACLE{sup *1} relational database manager system to access data sets of surface exploration (geology, geophysics, geochemistry, etc.), drilling (well trajectory, geological column, logging, etc.), well testing (production test, injection test, interference test, tracer test, etc.) and production/injection history.{open_quotes}GEOGRAPH{close_quotes} consists of {open_quotes}Pre-processor{close_quotes} that can construct the three-dimensional free shape reservoir modeling by mouse operation on X-window and {open_quotes}Post-processor{close_quotes} that can display several kinds of two/three-dimensional maps and X-Y plots to compile data on {open_quotes}GEOBASE{close_quotes} and result of TOUGH/TOUGH2 calculation. This paper shows concept of the systems and examples of utilization.

Relationship between mutation frequency of GPA locus and cumulative dose among medical diagnostic X-ray workers

International Nuclear Information System (INIS)

Wang Jixian; Yu Wenru; Li Benxiao; Fan Tiqiang; Li Zhen; Gao Zhiwei; Chen Zhenjun; Zhao Yongcheng

2000-01-01

Objective: To explore the feasibility of using GPA locus mutation assay as a bio-dosimeter for occupational exposure to ionizing radiation. Methods: An improved technique of GPA locus mutation assay was used in th study. The frequencies of mutant RBC in peripheral blood of 55 medical X-ray workers and 50 controls employed in different calendar-year periods were detected. The relationship between mutation frequencies (MFs) and period of entry, working years and cumulative doses were analyzed. Results: The MFs were significantly elevated among X-ray workers employed before 1970. This finding is similar to the result of cancer epidemiological study among medical X-ray workers , in which the cancer risk was significantly increased only X-ray workers employed before 1970. The MFs of GPA increased with increasing cumulative dose. The dose-effect relationship of Nφ MF with cumulative dose was closer than that of NN MF. Conclusion: There are many problems to be solved for using GPA MF assay as a bio-dosimeter such as individual variation, specificity and calibration curve of dose-effect relationship

X-ray diffraction measurements on CuGeO3 under high pressures to 81 GPa using synchrotron radiation and imaging plates

International Nuclear Information System (INIS)

Ming, L C; Eto, T; Takeda, K; Kobayashi, Y; Suzuki, E; Endo, S; Sharma, S K; Jayaraman, A; Kikegawa, T

2002-01-01

Angle-dispersive x-ray diffraction measurements using CuGeO 3 (I) and CuGeO 3 (III) as the starting materials were carried out to 81 and 31 GPa, respectively, at room temperature. Data for phase (I) show that phase transitions occur at ∼7, ∼14, and ∼22 GPa, respectively, corresponding to (I) → (II), (II) → (II'), and (II') → (VI) transitions, as reported previously. The tetragonal phase (VI) was found to be stable up to 81 GPa, the highest pressure determined in this study. The volume changes at the transition pressures are estimated to be of ∼5%, ∼0%, and ∼14% for (I) → (II), (II) → (II'), and (II') → (VI) transitions, respectively. Data from measurements where phase (III) was the starting material show that phase (III) first changes to phase (IV) at ∼7 GPa and then to (IV') at 13.5 GPa, and finally to phase (V) at ∼18 GPa, with volume changes of 1.5%, 0%, and 20%, respectively, at the transition pressure. The volume change of 20% at 18 GPa is consistent with the pyroxene-perovskite transition

Biomass is beginning to threaten the wood-processors

International Nuclear Information System (INIS)

Beer, G.; Sobinkovic, B.

2004-01-01

In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

Reconfigurable signal processor designs for advanced digital array radar systems

Science.gov (United States)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Parallel processor for fast event analysis

International Nuclear Information System (INIS)

Hensley, D.C.

1983-01-01

Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

Asymmetrical floating point array processors, their application to exploration and exploitation

Energy Technology Data Exchange (ETDEWEB)

Geriepy, B L

1983-01-01

An asymmetrical floating point array processor is a special-purpose scientific computer which operates under asymmetrical control of a host computer. Although an array processor can receive fixed point input and produce fixed point output, its primary mode of operation is floating point. The first generation of array processors was oriented towards time series information. The next generation of array processors has proved much more versatile and their applicability ranges from petroleum reservoir simulation to speech syntheses. Array processors are becoming commonplace in mining, the primary usage being construction of grids-by usual methods or by kriging. The Australian mining community is among the world's leaders in regard to computer-assisted exploration and exploitation systems. Part of this leadership role must be providing guidance to computer vendors in regard to current and future requirements.

On the effective parallel programming of multi-core processors

NARCIS (Netherlands)

Varbanescu, A.L.

2010-01-01

Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

Sound velocity of tantalum under shock compression in the 18–142 GPa range

Energy Technology Data Exchange (ETDEWEB)

Xi, Feng, E-mail: xifeng@caep.cn; Jin, Ke; Cai, Lingcang, E-mail: cai-lingcang@aliyun.com; Geng, Huayun; Tan, Ye; Li, Jun [National Key Laboratory of Shock Waves and Detonation Physics, Institute of Fluid Physics, CAEP, P.O. Box 919-102 Mianyang, Sichuan 621999 (China)

2015-05-14

Dynamic compression experiments of tantalum (Ta) within a shock pressure range from 18–142 GPa were conducted driven by explosive, a two-stage light gas gun, and a powder gun, respectively. The time-resolved Ta/LiF (lithium fluoride) interface velocity profiles were recorded with a displacement interferometer system for any reflector. Sound velocities of Ta were obtained from the peak state time duration measurements with the step-sample technique and the direct-reverse impact technique. The uncertainty of measured sound velocities were analyzed carefully, which suggests that the symmetrical impact method with step-samples is more accurate for sound velocity measurement, and the most important parameter in this type experiment is the accurate sample/window particle velocity profile, especially the accurate peak state time duration. From these carefully analyzed sound velocity data, no evidence of a phase transition was found up to the shock melting pressure of Ta.

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Baird, S.A.; Biddulph, P.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

Benchmarking NWP Kernels on Multi- and Many-core Processors

Science.gov (United States)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

Science.gov (United States)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Excellent durability of DLC film on carburized steel (JIS-SCr420) under a stress of 3.0 GPa

International Nuclear Information System (INIS)

Yakabe, F; Kumagai, M; Kuwahara, H; Ochiai, S; Jinbo, Y; Horiuchi, T

2008-01-01

To improve durability of transmission gears, Diamond Like Carbon (DLC) film coated on roller was estimated as well as TiN film. These films were coated on JIS-SCr420 steel, which was carburized, quenched, and tempered. DLC and TiN films were deposited by PCVD and PVD process, respectively. These surface modified rollers were estimated by usual metallurgical methods (observation of microstructure by optical microscope, SEM, and TEM, measurement of hardness by Vickers hardness tester and nano-indentator), measurement of friction coefficient by ball-on-disk in dry atmosphere, analysis of carbon by Raman spectroscopy and hydrogen by EDRA, and lifetime of pitting by the roller-pitting test. The hardness values were 21 GPa and 26 GPa, the elasticity coefficients were 192 GPa and 336 GPa, the friction coefficients were 0.1∼0.15 and 0.5∼0.6 for DLC and TiN films, respectively. The present DLC was a typical DLC called as hydrogenated amorphous carbon (a-C: H). The hydrogen content was about 20%. The surface fatigue resistance of DLC-coated specimen had 100 times longer life than that the carburized and quenched one even under Hertzian contact stress of 3.0 GPa. TiN coated specimen was failed at 3.0 GPa by 5.17·10 5 cycles despite that the strength of the surface of the substrate was reduced due to the exposure at higher temperature in the coating process than the temperature for tempering

ACP/R3000 processors in data acquisition systems

International Nuclear Information System (INIS)

Deppe, J.; Areti, H.; Atac, R.

1989-02-01

We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

GA103: A microprogrammable processor for online filtering

International Nuclear Information System (INIS)

Calzas, A.; Danon, G.; Bouquet, B.

1981-01-01

GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)

Real-time trajectory optimization on parallel processors

Science.gov (United States)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

Deep Trek Re-configurable Processor for Data Acquisition (RPDA)

Energy Technology Data Exchange (ETDEWEB)

Bruce Ohme; Michael Johnson

2009-06-30

This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop a high-temperature Re-configurable Processor for Data Acquisition (RPDA). The RPDA development has incorporated multiple high-temperature (225C) electronic components within a compact co-fired ceramic Multi-Chip-Module (MCM) package. This assembly is suitable for use in down-hole oil and gas applications. The RPDA module is programmable to support a wide range of functionality. Specifically this project has demonstrated functional integrity of the RPDA package and internal components, as well as functional integrity of the RPDA configured to operate as a Multi-Channel Data Acquisition Controller. This report reviews the design considerations, electrical hardware design, MCM package design, considerations for manufacturing assembly, test and screening, and results from prototype assembly and characterization testing.

The ATLAS Level-1 Central Trigger Processor (CTP)

CERN Document Server

Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

2005-01-01

The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

A Processor-Sharing Scheduling Strategy for NFV Nodes

Directory of Open Access Journals (Sweden)

Giuseppe Faraci

2016-01-01

Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.

Processor farming method for multi-scale analysis of masonry structures

Science.gov (United States)

Krejčí, Tomáš; Koudelka, Tomáš

2017-07-01

This paper describes a processor farming method for a coupled heat and moisture transport in masonry using a two-level approach. The motivation for the two-level description comes from difficulties connected with masonry structures, where the size of stone blocks is much larger than the size of mortar layers and very fine finite element mesh has to be used. The two-level approach is suitable for parallel computing because nearly all computations can be performed independently with little synchronization. This approach is called processor farming. The master processor is dealing with the macro-scale level - the structure and the slave processors are dealing with a homogenization procedure on the meso-scale level which is represented by an appropriate representative volume element.

[Improving speech comprehension using a new cochlear implant speech processor].

Science.gov (United States)

Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

2009-06-01

The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

High Pressure In Situ X-ray Diffraction Study of MnO to 120 GPa and Comparison with Shock Compression Experiment

Science.gov (United States)

Yagi, Takehiko; Kondo, Tadashi; Syono, Yasuhiko

1997-07-01

In order to clarify the nature of the phase transformation in MnO observed at around 90 GPa by shock compression experiment (Syono et al., this symposium), high pressure in situ x-ray experiments were carried out up to 120 GPa. Powdered sample was directly compressed in Mao-Bell type diamond anvil and x-ray experiments were carried out using angle dispersive technique by combining synchrotron radiation and imaging plate detector. Distortion of the B1 structured phase into hexagonal unit cell was observed from 25-40 GPa, which continues to increase up to 90 GPa. At around 90 GPa, discontinuous change of the diffraction was observed. This new phase cannot be explained by a simple B2 structure and the analysis of this phase is in progress. This high pressure phase has metallic appearance, which reverses to transparent MnO on release of pressure.

Hardware processor for tracking particles in an alternating-gradient synchrotron

International Nuclear Information System (INIS)

Johnson, M.; Avilez, C.

1987-01-01

We discuss the design and performance of special-purpose processors for tracking particles through an alternating-gradient synchrotron. We present block diagram designs for two hardware processors. Both processors use algorithms based on the 'kick' approximation, i.e., transport matrices are used for dipoles and quadrupoles, and the thin-lens approximation is used for all higher multipoles. The faster processor makes extensive use of memory look-up tables for evaluating functions. For the case of magnets with multipoles up to pole 30 and using one kick per magnet, this processor can track 19 particles through an accelerator at a rate that is only 220 times slower than the time it takes real particles to travel around the machine. For a model consisting of only thin lenses, it is only 150 times slower than real particles. An additional factor of 2 can be obtained with chips now becoming available. The number of magnets in the accelerator is limited only by the amount of memory available for storing magnet parameters. (author) 20 refs., 7 figs., 2 tabs

Changes in structure and preferential cage occupancy of ethane hydrate and ethane-methane mixed gas hydrate under high pressure

International Nuclear Information System (INIS)

Hirai, H; Takahara, N; Kawamura, T; Yamamoto, Y; Yagi, T

2010-01-01

Structural changes and preferential cage occupancies were examined for ethane hydrate and ethane-methane mixed gas hydrates with five compositions in a pressure range of 0.2 to 2.8 GPa at room temperature. X-ray diffractometry and Raman spectroscopy showed the following structural changes. The initial structure, structure I (sI), of ethane hydrate was retained up to 2.1 GPa without any structural change. For the mixed hydrates, sI was widely distributed throughout the region examined except for the methane-rich and lower pressure regions, where sII and sH appeared. Above 2.1 GPa ethane hydrate and all of the mixed hydrates decomposed into ice VI and ethane fluid or methane-ethane fluid, respectively. The Raman study revealed that occupation of the small cages by ethane molecules occurred above 0.1 GPa in ethane hydrate and continued up to decomposition at 2.1 GPa, although it was thought that ethane molecules were contained only in the large cage.

High-speed special-purpose processor for event selection by number of direct tracks

International Nuclear Information System (INIS)

Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.

1986-01-01

A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits

Multibus-based parallel processor for simulation

Science.gov (United States)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Monitoring the performance of off-site processors

International Nuclear Information System (INIS)

Miller, C.C.

1995-01-01

Commercial nuclear power plants have been able to utilize the latest technologies and achieve large volume reduction by obtaining off-site waste processor services. Although the use of such services reduce the burden of waste processing it also reduces the utility's control over the process. Monitoring the performance of off-site processors is important so that the utility is cognizant of the waste disposition for required regulatory reporting. In addition to obtaining data for Reg Guide 1.21 reporting, Performance monitoring is important to determine which vendor and which services to utilize. Off-site processor services were initially offered for the decontamination of metallic waste. Since that time the list of services has expanded to include supercompaction, survey for release, incineration and metal melting. The number of vendors offering off-site services has increased and the services they offer vary. processing rates vary between vendors and have different charge bases. Determining which vendor to use for what service can be complicated and confusing

Performance evaluation and comparison of fuel processors integrated with PEM fuel cell based on steam or autothermal reforming and on CO preferential oxidation or selective methanation

International Nuclear Information System (INIS)

Ercolino, Giuliana; Ashraf, Muhammad A.; Specchia, Vito; Specchia, Stefania

2015-01-01

Highlights: • Modeling of different fuel processors integrated with PEM fuel cell stack. • Steam or autothermal reforming + CO selective methanation or preferential oxidation. • Reforming of different hydrocarbons: gasoline, light diesel oil, natural gas. • 5 kW e net systems comparison via energy efficiency and primary fuel rate consumed. • Highest net efficiency: steam reformer + CO selective methanation based system. - Abstract: The performances of four different auxiliary power unit (APU) schemes, based on a 5 kW e net proton exchange membrane fuel cell (PEM-FC) stack, are evaluated and compared. The fuel processor section of each APU is characterized by a reformer (autothermal ATR or steam SR), a non-isothermal water gas shift (NI-WGS) reactor and a final syngas catalytic clean-up step: the CO preferential oxidation (PROX) reactor or the CO selective methanation (SMET) one. Furthermore, three hydrocarbon fuels, the most commonly found in service stations (gasoline, light diesel oil and natural gas) are considered as primary fuels. The comparison is carried out examining the results obtained by a series of steady-state system simulations in Aspen Plus® of the four different APU schemes by varying the fed fuel. From the calculated data, the performance of CO-PROX is not very different compared to that of the CO-SMET, but the performance of the SR based APUs is higher than the scheme of the ATR based APUs. The most promising APU scheme with respect to an overall performance target is the scheme fed with natural gas and characterized by a fuel processor chain consisting of SR, NI-WGS and CO-SMET reactors. This processing reactors scheme together with the fuel cell section, notwithstanding having practically the same energy efficiency of the scheme with SR, NI-WGS and CO-PROX reactors, ensures a less complex scheme, higher hydrogen concentration in the syngas, lower air mass rate consumption, the absence of nitrogen in the syngas and higher potential

Digital Signal Processor System for AC Power Drivers

Directory of Open Access Journals (Sweden)

Ovidiu Neamtu

2009-10-01

Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

Non-hydrostatic behavior of KBr as a pressure medium in diamond anvil cells up to 5.63 GPa

International Nuclear Information System (INIS)

Zhao, Jing; Ross, Nancy L

2015-01-01

Non-hydrostatic stresses of KBr acting as a pressure–transmitting medium have been investigated by examining their effect on a single crystal of quartz in a diamond anvil cell (DAC). The lattice strains or distortions were measured by single-crystal x-ray diffraction methods, and the non-hydrostatic deviatoric stresses for KBr were determined up to 5.63(2) GPa. The experimental results show that differences between axial stress components in the direction normal to the DAC culet face and the radial stress components in directions parallel to the DAC culet face are about 0.063(24) GPa at pressures below 2.14 GPa, and the pressure-transmitting medium can therefore be considered as quasi-hydrostatic up to this pressure. However above 2.14 GPa, after the phase transition pressure of KBr during which it converts from the B1 phase to the B2 phase, the deviatoric stresses constantly increase with increasing pressure. At the maximum pressure of this study, 5.63(2) GPa, the difference between axial stress and radial stress components reaches 0.93(9) GPa. Different variations in the non-hydrostatic deviatoric stresses were observed during both compression and decompression of the DAC, and are mainly ascribed to the phase-transition-induced volume change of KBr. (paper)

Early experience with the cochlear ESPrit ear-level speech processor in children.

Science.gov (United States)

Totten, C; Cope, Y; McCormick, B

2000-12-01

The ESPrit ear-level speech processor has recently become available in the United Kingdom for use with the Nucleus CI24M multichannel cochlear implant. We report on the use of this ear-level processor with 6 children, ages 8 to 15 years. In this study, all patients were initially fitted with the SPrint body-worn processor, this being a prerequisite for programming the ESPrit. Five of the children were fitted successfully with the ESPrit and are using their devices consistently. The results show that patient experience with the ESPrit has been favorable, although there have been some device and programming difficulties. Aided threshold measures show that the ESPrit processor performs at least as well as the SPrint processor, with a trend toward improved aided thresholds for the ESPrit processor compared with the SPrint processor. Further study of the functional benefit of both of these devices may confirm these potential gains. The ESPrit device currently has a disadvantage for children in that it does not support FM radio hearing aid use. Finally, caution is advised in the fitting of the ESPrit in very young children or inexperienced listeners, because of difficulties in monitoring device function.

Survey of cochlear implant user satisfaction with the Neptune™ waterproof sound processor

Directory of Open Access Journals (Sweden)

Jeroen J. Briaire

2016-04-01

Full Text Available A multi-center self-assessment survey was conducted to evaluate patient satisfaction with the Advanced Bionics Neptune™ waterproof sound processor used with the AquaMic™ totally submersible microphone. Subjective satisfaction with the different Neptune™ wearing options, comfort, ease of use, sound quality and use of the processor in a range of active and water related situations were assessed for 23 adults and 73 children, using an online and paper based questionnaire. Upgraded subjects compared their previous processor to the Neptune™. The Neptune™ was most popular for use in general sports and in the pool. Subjects were satisfied with the sound quality of the sound processor outside and under water and following submersion. Seventyeight percent of subjects rated waterproofness as being very useful and 83% of the newly implanted subjects selected waterproofness as one of the reasons why they chose the Neptune™ processor. Providing a waterproof sound processor is considered by cochlear implant recipients to be useful and important and is a factor in their processor choice. Subjects reported that they were satisfied with the Neptune™ sound quality, ease of use and different wearing options.

A word processor optimized for preparing journal articles and student papers.

Science.gov (United States)

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

Predicting Success Study Using Students GPA Category

Directory of Open Access Journals (Sweden)

Awan Setiawan

2015-07-01

Full Text Available Abstract. Maintaining student graduation rates are the main tasks of a University. High rates of student graduation and the quality of graduates is a success indicator of a university, which will have an impact on public confidence as stakeholders of higher education and the National Accreditation Board as a regulator (government. Making predictions of student graduation and determine the factors that hinders will be a valuable input for University. Data mining system facilitates the University to create the segmentation of students’ performance and prediction of their graduation. Segmentation of student by their performance can be classified in a quadrant chart is divided into 4 segments based on grade point average and the growth rate of students performance index per semester. Standard methodology in data mining i.e CRISP-DM (Cross Industry Standard Procedure for Data Mining will be implemented in this research. Making predictions, graduation can be done through the modeling process by utilizing the college database. Some algorithms such as C5, C & R Tree, CHAID, and Logistic Regression tested in order to find the best model. This research utilizes student performance data for several classes. Parameters used in addition to GPA also included the master's students data are expected to build the student profile data. The outcome of the study is the student category based on their study performance and prediction of graduation. Based on this prediction, the  university may recommend actions to be taken to improve the student  achievement index and graduation rates.Keywords: graduation, segmentation, quadrant GPA, data mining, modeling algorithms

Predicting Success Study Using Students GPA Category

Directory of Open Access Journals (Sweden)

Awan Setiawan

2015-06-01

Full Text Available Abstract. Maintaining student graduation rates are the main tasks of a University. High rates of student graduation and the quality of graduates is a success indicator of a university, which will have an impact on public confidence as stakeholders of higher education and the National Accreditation Board as a regulator (government. Making predictions of student graduation and determine the factors that hinders will be a valuable input for University. Data mining system facilitates the University to create the segmentation of students’ performance and prediction of their graduation. Segmentation of student by their performance can be classified in a quadrant chart is divided into 4 segments based on grade point average and the growth rate of students performance index per semester. Standard methodology in data mining i.e CRISP-DM (Cross Industry Standard Procedure for Data Mining will be implemented in this research. Making predictions, graduation can be done through the modeling process by utilizing the college database. Some algorithms such as C5, C & R Tree, CHAID, and Logistic Regression tested in order to find the best model. This research utilizes student performance data for several classes. Parameters used in addition to GPA also included the master's students data are expected to build the student profile data. The outcome of the study is the student category based on their study performance and prediction of graduation. Based on this prediction, the university may recommend actions to be taken to improve the student achievement index and graduation rates. Keywords: graduation, segmentation, quadrant GPA, data mining, modeling algorithms

Developing an equitable fee structure for gas processing services: JP-90 and beyond

International Nuclear Information System (INIS)

Kingsbury, J.D.; Moller, I.

1996-01-01

The Joint Industry Gas Processing Fee Task Force Report, JP-90, was designed to promote negotiation of gas processing fees that are based on principles of equity and fairness for both natural gas producers and processors. Another purpose of the JP-90 was to develop an effective dispute resolution process for use in those cases where negotiations have failed. At its inception, JP-90 was the only guideline for unregulated fee practices in the oil and gas sector in North America. Today PJVA-95, the revised version of JP-90, is in its final draft. It addresses the changing focus of the gas processing business, and changing regulatory roles in Alberta and British Columbia. A number of other fee mechanisms also have been described, such as the jumping pound formula, fixed fees, fees based on price, wellhead purchases, and others. These mechanisms developed over time to allow the processor and the producer to share the price risk. The changing role of regulatory agencies in fee dispute resolution was also discussed briefly

An Implementation of ARM 920T Processor-based Ultrasonic Spirometer and Improvement of Its Sensitivity

International Nuclear Information System (INIS)

Lee, Cheul Won; Kim, Young Kil

2005-01-01

The spirometer is a medical device that measures the instantaneous velocity of the respiratory gas flow capacity. It is used for testing the condition of the lung and patient monitoring. It measures the absolute capacity difference that includes the flow capacity signal. In this paper, by using an ultrasound sensor that reduce+ the error caused by the inertia and pressure it has improved the transmission and receiving signal. This has enabled patients with weak respiratory to use the spirometer. Also, by using the ARM 920T Processor, a precise and prompt detection system was implemented

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

Science.gov (United States)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Synthetic lead bromapatite: X-ray structure at ambient pressure and compressibility up to about 20 GPa

Science.gov (United States)

Liu, Xi; Fleet, Michael E.; Shieh, Sean R.; He, Qiang

2011-05-01

Lead bromapatite [Pb10(PO4)6Br2] has been synthesized via solid-state reaction at pressures up to 1.0 GPa, and its structure determined by single-crystal X-ray diffraction at ambient temperature and pressure. The large bromide anion is accommodated in the c-axis channel by lateral displacements of structural elements, particularly of Pb2 cations and PO4 tetrahedra. The compressibility of bromapatite was also investigated up to about 20.7 GPa at ambient temperature, using a diamond-anvil cell and synchrotron X-ray radiation. The compressibility of lead bromapatite is significantly different from that of lead fluorapatite. The pressure-volume data of lead bromapatite ( P < 10 GPa) fitted to the third-order Birch-Murnaghan equation yield an isothermal bulk modulus ( K T ) of 49.8(16) GPa and first pressure derivative ( KT^' } ) of 10.1(10). If KT^' } is fixed at 4, the derived K T is 60.8(11) GPa. The relative difference of the bulk moduli of these two lead apatites is thus about 12%, which is about two times the relative difference of the bulk moduli (~5%) of the calcium apatites fluorapatite [Ca10(PO4)6F2], chlorapatite [Ca10(PO4)6Cl2] and hydroxylapatite [Ca10(PO4)6(OH)2]. Another interesting feature apparently related to the replacement of F by Br in lead apatite is the switch in the principle axes of the strain ellipsoid: the c-axis is less compressible than the a-axis in lead bromapatite but more compressible in lead fluorapatite.

First Results of an “Artificial Retina” Processor Prototype

International Nuclear Information System (INIS)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

2016-01-01

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

Melting relations in the MgO-MgSiO3 system up to 70 GPa

Science.gov (United States)

Ohnishi, Satoka; Kuwayama, Yasuhiro; Inoue, Toru

2017-06-01

Melting experiments in a binary system MgO-MgSiO3 were performed up to 70 GPa using a CO2 laser heated diamond anvil cell. The quenched samples were polished and analyzed by a dualbeam focused ion beam (FIB) and a field emission scanning electron microscope (FE-SEM), respectively. The liquidus phase and the eutectic composition were determined on the basis of textual and chemical analyses of sample cross sections. Our experimental results show that the eutectic composition is the Si/Mg molar ratio of 0.76 at 35 GPa and it decreases with increasing pressure. Above 45 GPa, it becomes relatively constant at about 0.64-0.65 Si/Mg molar ratio. Using our experimental data collected at a wide pressure range up to 70 GPa together with previous experimental data, we have constructed a thermodynamic model of the eutectic composition of the MgO-MgSiO3 system. The eutectic composition extrapolated to the pressure and temperature conditions at the base of the mantle is about 0.64 Si/Mg molar ratio. The modeled eutectic composition is quite consistent with a previous prediction from ab initio calculations (de Koker et al. in Earth Planet Sci Lett 361:58-63, 2013), suggesting that the simple assumption of a non-ideal regular solution model can well describe the melting relation of the MgO-MgSiO3 system at high pressure. Our results show that the liquidus phase changes from MgO-periclase to MgSiO3-bridgmanite at 35 GPa for the simplified pyrolite composition ( 0.7 Si/Mg molar ratio), while MgSiO3-bridgmanite is the liquidus phase at the entire lower mantle conditions for the chondritic composition ( 0.84 Si/Mg molar ratio).

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

Science.gov (United States)

Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

2018-02-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

M7--a high speed digital processor for second level trigger selections

International Nuclear Information System (INIS)

Droege, T.F.; Gaines, I.; Turner, K.J.

1978-01-01

A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

Discussion paper for a highly parallel array processor-based machine

International Nuclear Information System (INIS)

Hagstrom, R.; Bolotin, G.; Dawson, J.

1984-01-01

The architectural plant for a quickly realizable implementation of a highly parallel special-purpose computer system with peak performance in the range of 6 billion floating point operations per second is discussed. The architecture is suitable to Lattice Gauge theoretical computations of fundamental physics interest and may be applicable to a range of other problems which deal with numerically intensive computational problems. The plan is quickly realizable because it employs a maximum of commercially available hardware subsystems and because the architecture is software-transparent to the individual processors, allowing straightforward re-use of whatever commercially available operating-systems and support software that is suitable to run on the commercially-produced processors. A tiny prototype instrument, designed along this architecture has already operated. A few elementary examples of programs which can run efficiently are presented. The large machine which the authors would propose to build would be based upon a highly competent array-processor, the ST-100 Array Processor, and specific design possibilities are discussed. The first step toward realizing this plan practically is to install a single ST-100 to allow algorithm development to proceed while a demonstration unit is built using two of the ST-100 Array Processors

SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

Science.gov (United States)

Moyer, Ruth A.

Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

OpenAIRE

Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

2010-01-01

As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

Directory of Open Access Journals (Sweden)

Hristov Ivan

2018-01-01

Full Text Available We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP” in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL. The results show 2 times better performance on KNL processor.

A single chip pulse processor for nuclear spectroscopy

International Nuclear Information System (INIS)

Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

1985-01-01

A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

The hardware track finder processor in CMS at CERN

CERN Document Server

Kluge, A

1997-01-01

The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

UA1 upgrade first-level calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

1989-01-01

A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

Application of the Computer Capacity to the Analysis of Processors Evolution

OpenAIRE

Ryabko, Boris; Rakitskiy, Anton

2017-01-01

The notion of computer capacity was proposed in 2012, and this quantity has been estimated for computers of different kinds. In this paper we show that, when designing new processors, the manufacturers change the parameters that affect the computer capacity. This allows us to predict the values of parameters of future processors. As the main example we use Intel processors, due to the accessibility of detailed description of all their technical characteristics.

Optimal processor for malfunction detection in operating nuclear reactor

International Nuclear Information System (INIS)

Ciftcioglu, O.

1990-01-01

An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

An updated program-controlled analog processor, model AP-006, for semiconductor detector spectrometers

International Nuclear Information System (INIS)

Shkola, N.F.; Shevchenko, Yu.A.

1989-01-01

An analog processor, model AP-006, is reported. The processor is a development of a series of spectrometric units based on a shaper of the type 'DL dif +TVS+gated ideal integrator'. Structural and circuits design features are described. The results of testing the processor in a setup with a Si(Li) detecting unit over an input count-rate range of up to 5x10 5 cps are presented. Processor applications are illustrated. (orig.)

Intelligent trigger processor for the crystal box

International Nuclear Information System (INIS)

Sanders, G.H.; Butler, H.S.; Cooper, M.D.

1981-01-01

A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering

40 CFR 80.840 - What requirements apply to transmix processors?

Science.gov (United States)

2010-07-01

... PROGRAMS (CONTINUED) REGULATION OF FUELS AND FUEL ADDITIVES Gasoline Toxics Gasoline Toxics Performance Requirements § 80.840 What requirements apply to transmix processors? Any transmix processor who produces gasoline or gasoline blendstock from transmix, or recovers gasoline or gasoline blendstock from transmix...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

2014-01-01

The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

Safe and Efficient Support for Embeded Multi-Processors in ADA

Science.gov (United States)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

Hugoniot measurements in vanadium using the LNL two-stage light-gas gun

International Nuclear Information System (INIS)

Gathers, G.R.; Mitchell, A.C.; Holmes, N.C.

1983-01-01

Hugoniot measurements on vanadium have been made using the LLNL two-stage light-gas gun. The direct collision method with electrical pins and a tantalum flyer accelerated to 6.28 km/s was used. Alt'shuler, et. al., have reported Hugoniot measurements in vanadium using explosives and the impedance match method. They reported a kink in the U/sub s/ - U/sub p/ relationship at 183 GPa, and attribute it to electronic transitions. The upper portion of their curve is based on a single point at 339 GPa. The present work was performed to further investigate the equation-of-state in the high-pressure range

7 CFR 1215.14 - Processor.

Science.gov (United States)

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

Hydrostatic pressure (8 GPa) dependence of electrical resistivity of BaCo{sub 2}As{sub 2} single crystal

Energy Technology Data Exchange (ETDEWEB)

Ganguli, Chandreyee; Matsubayashi, Kazuyuki; Ohgushi, Kenya [Institute for Solid State Physics, The University of Tokyo, Kashiwanoha, Kashiwa, Chiba 277-8581 (Japan); Uwatoko, Yoshiya, E-mail: uwatoko@issp.u-tokyo.ac.jp [Institute for Solid State Physics, The University of Tokyo, Kashiwanoha, Kashiwa, Chiba 277-8581 (Japan); Kanagaraj, Moorthi [Centre for High Pressure Research, School of Physics, Bharathidasan University, Tiruchirappalli 620024 (India); Arumugam, Sonachalam, E-mail: sarumugam1963@yahoo.com [Centre for High Pressure Research, School of Physics, Bharathidasan University, Tiruchirappalli 620024 (India)

2013-10-15

Graphical abstract: - Highlights: • Single crystals of BaCo{sub 2}As{sub 2} were grown by CoAs self-flux method. • We have studied pressure effects (8 GPa) on dc electrical resistivity of BaCo{sub 2}As{sub 2}. • On applied external pressure BaCo{sub 2}As{sub 2} remains a metallic state up to 8 GPa. • Superconductivity is absent in BaCo{sub 2}As{sub 2} because of its proximity to ferromagnetism. - Abstract: The pressure dependence of the electrical resistivity of BaCo{sub 2}As{sub 2} single crystal as a function of temperature was measured at ambient and high pressures up to 8 GPa for the first time using cubic anvil high pressure cell. It is observed that at room temperature the resistivity monotonically decreases with increasing pressure and it remains in the metallic state even at an applied pressure of 8 GPa. From the temperature dependence of the resistivity measurements under pressure, we found that superconductivity is absent up to 8 GPa. The value of the electron's scattering factor (A) is found to be large at ambient pressure and it decreases with the application of pressure, indicating that the substantial electron correlation effect of BaCo{sub 2}As{sub 2} is reduced under pressure, revealing a dramatic change of density of states at the Fermi energy.

Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2010-12-01

Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

40 CFR 80.219 - Designation and downstream requirements for GPA gasoline.

Science.gov (United States)

2010-07-01

... 40 Protection of Environment 16 2010-07-01 2010-07-01 false Designation and downstream requirements for GPA gasoline. 80.219 Section 80.219 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY... sold or dispensed for use in motor vehicles at a retail outlet or wholesale purchaser-consumer facility...

Photonics and Fiber Optics Processor Lab

Data.gov (United States)

Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

Slowdown in the $M/M/1$ discriminatory processor-sharing queue

NARCIS (Netherlands)

Cheung, S.K.; Kim, Bara; Kim, Jeongsim

2008-01-01

We consider a queue with multiple K job classes, Poisson arrivals, and exponentially distributed required service times in which a single processor serves according to the discriminatory processor-sharing (DPS) discipline. For this queue, we obtain the first and second moments of the slowdown, which

Online Fastbus processor for LEP

International Nuclear Information System (INIS)

Mueller, H.

1986-01-01

The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

Invasive tightly coupled processor arrays

CERN Document Server

LARI, VAHID

2016-01-01

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

Science.gov (United States)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

A survey of Tumult, a real-time multi-processor system

International Nuclear Information System (INIS)

Jansen, P.G.

1986-01-01

Tumult (Twente University MULTi processor system) is the name of an ongoing project aiming at the design and implementation of a modular extendible multiprocessor system. All memory is distributed and processors communicate in parallel via a fast and reliable local switching network instead of a shared bus. A distributed real-time operating system is being designed and implemented, consisting of a multi-tasking subsystem per processor. Processes can communicate via a message passing mechanism. Communication links and processes are dynamically created and disposed by the application. In this article a brief description of the system is given; communication aspects are emphasized. (Auth.)

Reaction-diffusion path planning in a hybrid chemical and cellular-automaton processor

International Nuclear Information System (INIS)

Adamatzky, Andrew; Lacy Costello, Benjamin de

2003-01-01

To find the shortest collision-free path in a room containing obstacles we designed a chemical processor and coupled it with a cellular-automaton processor. In the chemical processor obstacles are represented by sites of high concentration of potassium iodide and a planar substrate is saturated with palladium chloride. Potassium iodide diffuses into the substrate and reacts with palladium chloride. A dark coloured precipitate of palladium iodide is formed almost everywhere except sites where two or more diffusion wavefronts collide. The less coloured sites are situated at the furthest distance from obstacles. Thus, the chemical processor develops a repulsive field, generated by obstacles. A snapshot of the chemical processor is inputted to a cellular automaton. The automaton behaves like a discrete excitable media; also, every cell of the automaton is supplied with a pointer that shows an origin of the cell's excitation. The excitation spreads along the cells corresponding to precipitate depleted sites of the chemical processor. When the destination-site is excited, waves travel on the lattice and update the orientations of the pointers. Thus, the automaton constructs a spanning tree, made of pointers, that guides a traveler towards the destination point. Thus, the automaton medium generates an attractive field and combination of this attractive field with the repulsive field, generated by the chemical processor, provides us with a solution of the collision-free path problem

A VAX-FPS Loosely-Coupled Array of Processors

International Nuclear Information System (INIS)

Grosdidier, G.

1987-03-01

The main features of a VAX-FPS Loosely-Coupled Array of Processors (LCAP) set-up and the implementation of a High Energy Physics tracking program for off-line purposes will be described. This LCAP consists of a VAX 11/750 host and two FPS 64 bit attached processors. Before analyzing the performances of this LCAP, its characteristics will be outlined, especially from a user's point of vue, and will be briefly compared to those of the IBM-FPS LCAP

Reducing Competitive Cache Misses in Modern Processor Architectures

OpenAIRE

Prisagjanec, Milcho; Mitrevski, Pece

2017-01-01

The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This tec...

16-Bit RISC Processor Design for Convolution Application

OpenAIRE

Anand Nandakumar Shardul

2013-01-01

In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

An integrated processor for photonic quantum states using a broadband light–matter interface

International Nuclear Information System (INIS)

Saglamyurek, E; Sinclair, N; Slater, J A; Heshami, K; Oblak, D; Tittel, W

2014-01-01

Faithful storage and coherent manipulation of quantum optical pulses are key for long distance quantum communications and quantum computing. Combining these functions in a light–matter interface that can be integrated on-chip with other photonic quantum technologies, e.g. sources of entangled photons, is an important step towards these applications. To date there have only been a few demonstrations of coherent pulse manipulation utilizing optical storage devices compatible with quantum states, and that only in atomic gas media (making integration difficult) and with limited capabilities. Here we describe how a broadband waveguide quantum memory based on the atomic frequency comb (AFC) protocol can be used as a programmable processor for essentially arbitrary spectral and temporal manipulations of individual quantum optical pulses. Using weak coherent optical pulses at the few photon level, we experimentally demonstrate sequencing, time-to-frequency multiplexing and demultiplexing, splitting, interfering, temporal and spectral filtering, compressing and stretching as well as selective delaying. Our integrated light–matter interface offers high-rate, robust and easily configurable manipulation of quantum optical pulses and brings fully practical optical quantum devices one step closer to reality. Furthermore, as the AFC protocol is suitable for storage of intense light pulses, our processor may also find applications in classical communications. (paper)

Modal Processor Effects Inspired by Hammond Tonewheel Organs

Directory of Open Access Journals (Sweden)

Kurt James Werner

2016-06-01

Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

Safety-critical Java on a time-predictable processor

DEFF Research Database (Denmark)

Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

2015-01-01

For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

Stepping motor control processor reference manual. Volume I

International Nuclear Information System (INIS)

Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.

1980-01-01

This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained

The Interface Between Redundant Processor Modules Of Safety Grade PLC Using Mass Storage DPRAM

International Nuclear Information System (INIS)

Hwang, Sung Jae; Song, Seong Hwan; No, Young Hun; Yun, Dong Hwa; Park, Gang Min; Kim, Min Gyu; Choi, Kyung Chul; Lee, Ui Taek

2010-01-01

Processor module of safety grade PLC (hereinafter called as POSAFE-Q) developed by POSCO ICT provides high reliability and safety. However, POSAFEQ would have suffered a malfunction when we think taking place of abnormal operation by exceptional environmental. POSAFE-Q would not able to conduct its function normally in such case. To prevent these situations, the necessity of redundant processor module has been raised. Therefore, redundant processor module, NCPU-2Q, has been developed which has not only functions of single processor module with high reliability and safety but also functions of redundant processor

The performances of coffee processors and coffee market in the Republic of Serbia

Directory of Open Access Journals (Sweden)

Nuševa Daniela

2017-01-01

Full Text Available The main aim of this paper is to investigate the performances of coffee processors and coffee market in Serbia based on the market concentration analysis, profitability analysis, and profitability determinants analysis. The research was based on the sample of 40 observations of coffee processing companies divided into two groups: large and small coffee processors. The results indicate that two large coffee processors have dominant market share. Even though the Serbian coffee market is an oligopolistic, profitability analysis indicates that small coffee processors have a significant better profitability ratio than large coffee processors. Furthermore, results show that profitability ratio is positively related to the inventory turnover and negatively related to the market share.

Hardware Synchronization for Embedded Multi-Core Processors

DEFF Research Database (Denmark)

Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

2011-01-01

Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi......Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper...

The microelectronic and photonic test bed RISC processor and DRAM memory stack experiments

International Nuclear Information System (INIS)

Clark, K.A.; Meehan, T.J.

1999-01-01

This paper reports on the on-orbit data obtained from the MPTB RISC Processor Experiment, containing three Integrated Device Technologies R3081 processors. During operations, nine SEUs were observed in the processors, and four SEUs were observed in the memory and/or support circuitry. (authors)

Digital image processing software system using an array processor

International Nuclear Information System (INIS)

Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.

1981-01-01

A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

CERN Document Server

AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

2016-01-01

The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

CERN Document Server

Tang, Shaochun; The ATLAS collaboration

2015-01-01

The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

Scientific programming on massively parallel processor CP-PACS

International Nuclear Information System (INIS)

Boku, Taisuke

1998-01-01

The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

Investigation of Large Scale Cortical Models on Clustered Multi-Core Processors

Science.gov (United States)

2013-02-01

Playstation 3 with 6 available SPU cores outperforms the Intel Xeon processor (with 4 cores) by about 1.9 times for the HTM model and by 2.4 times...runtime breakdowns of the HTM and Dean models respectively on the Cell processor (on the Playstation 3) and the Intel Xeon processor ( 4 thread...YOUR FORM TO THE ABOVE ORGANIZATION. 1. REPORT DATE (DD-MM-YYYY) 2. REPORT TYPE 3. DATES COVERED (From - To) 4 . TITLE AND SUBTITLE 5a. CONTRACT NUMBER

Automation of ORIGEN2 calculations for the transuranic waste baseline inventory database using a pre-processor and a post-processor

International Nuclear Information System (INIS)

Liscum-Powell, J.

1997-06-01

The purpose of the work described in this report was to automate ORIGEN2 calculations for the Waste Isolation Pilot Plant (WIPP) Transuranic Waste Baseline Inventory Database (WTWBID); this was done by developing a pre-processor to generate ORIGEN2 input files from WWBID inventory files and a post-processor to remove excess information from the ORIGEN2 output files. The calculations performed with ORIGEN2 estimate the radioactive decay and buildup of various radionuclides in the waste streams identified in the WTWBID. The resulting radionuclide inventories are needed for performance assessment calculations for the WIPP site. The work resulted in the development of PreORG, which requires interaction with the user to generate ORIGEN2 input files on a site-by-site basis, and PostORG, which processes ORIGEN2 output into more manageable files. Both programs are written in the FORTRAN 77 computer language. After running PreORG, the user will run ORIGEN2 to generate the desired data; upon completion of ORIGEN2 calculations, the user can run PostORG to process the output to make it more manageable. All the programs run on a 386 PC or higher with a math co-processor or a computer platform running under VMS operating system. The pre- and post-processors for ORIGEN2 were generated for use with Rev. 1 data of the WTWBID and can also be used with Rev. 2 and 3 data of the TWBID (Transuranic Waste Baseline Inventory Database)

A design of a computer complex including vector processors

International Nuclear Information System (INIS)

Asai, Kiyoshi

1982-12-01

We, members of the Computing Center, Japan Atomic Energy Research Institute have been engaged for these six years in the research of adaptability of vector processing to large-scale nuclear codes. The research has been done in collaboration with researchers and engineers of JAERI and a computer manufacturer. In this research, forty large-scale nuclear codes were investigated from the viewpoint of vectorization. Among them, twenty-six codes were actually vectorized and executed. As the results of the investigation, it is now estimated that about seventy percents of nuclear codes and seventy percents of our total amount of CPU time of JAERI are highly vectorizable. Based on the data obtained by the investigation, (1)currently vectorizable CPU time, (2)necessary number of vector processors, (3)necessary manpower for vectorization of nuclear codes, (4)computing speed, memory size, number of parallel 1/0 paths, size and speed of 1/0 buffer of vector processor suitable for our applications, (5)necessary software and operational policy for use of vector processors are discussed, and finally (6)a computer complex including vector processors is presented in this report. (author)

Parallel computation for distributed parameter system-from vector processors to Adena computer

Energy Technology Data Exchange (ETDEWEB)

Nogi, T

1983-04-01

Research on advanced parallel hardware and software architectures for very high-speed computation deserves and needs more support and attention to fulfil its promise. Novel architectures for parallel processing are being made ready. Architectures for parallel processing can be roughly divided into two groups. One is a vector processor in which a single central processing unit involves multiple vector-arithmetic registers. The other is a processor array in which slave processors are connected to a host processor to perform parallel computation. In this review, the concept and data structure of the Adena (alternating-direction edition nexus array) architecture, which is conformable to distributed-parameter simulation algorithms, are described. 5 references.

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

Magnetic susceptibility measurement of solid oxygen at pressures up to 3.3 GPa

Energy Technology Data Exchange (ETDEWEB)

Mito, M., E-mail: mitoh@tobata.isc.kyutech.ac.jp; Yamaguchi, S.; Tsuruda, H.; Deguchi, H. [Faculty of Engineering, Kyushu Institute of Technology, Kitakyushu 804-8550 (Japan); Ishizuka, M. [Renovation Center of Instruments for Science Education and Technology, Osaka University, Toyonaka 560-8531 (Japan)

2014-01-07

The magnetic susceptibility of solid oxygen had long been observed only in the restricted pressure region below 0.8 GPa. We succeeded in extending the pressure region up to 3.3 GPa by clamping condensed oxygen in the sample chamber of a miniature diamond anvil cell and measuring the dc magnetic susceptibility using a superconducting quantum interference device magnetometer. In this experiment, the well-known α–β and β–γ transitions are observed in the phase diagram, suggesting consistency with the previous results of X-ray and Raman studies. In addition, a new magnetic anomaly is observed in the β phase.

Infrared spectrum and compressibility of Ti3GeC2 to 51 GPa

International Nuclear Information System (INIS)

Manoun, Bouchaib; Yang, H.; Saxena, S.K.; Ganguly, A.; Barsoum, M.W.; El Bali, B.; Liu, Z.X.; Lachkar, M.

2007-01-01

Using a synchrotron radiation source and a diamond anvil cell, we measured the pressure dependence of the lattice parameters of a polycrystalline Ti 3 GeC 2 sample up to a pressure of 51 GPa. No phase transformations were observed. Like Ti 3 SiC 2 , and most other compounds belonging to the same family of ternary carbides and nitrides, the so-called MAX phases, the compressibility of Ti 3 GeC 2 along the c axis is greater than that along the a axis. The bulk modulus is 197 ± 4 GPa, with a pressure derivative of 3.4 ± 0.1. We also characterized Ti 3 GeC 2 by infrared spectroscopy; four of the five expected infrared modes were observed for this material

Treecode with a Special-Purpose Processor

Science.gov (United States)

Makino, Junichiro

1991-08-01

We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

Token-Aware Completion Functions for Elastic Processor Verification

Directory of Open Access Journals (Sweden)

Sudarshan K. Srinivasan

2009-01-01

Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

Time-resolved light emission of a, c, and r-cut sapphires shock-compressed to 65 GPa

Science.gov (United States)

Liu, Q. C.; Zhou, X. M.

2018-04-01

To investigate light emission and dynamic deformation behaviors, sapphire (single crystal Al2O3) samples with three crystallographic orientations (a, c, and r-cut) were shock-compressed by the planar impact method, with final stress ranges from 47 to 65 GPa. Emission radiance and velocity versus time profiles were simultaneously measured with a fast pyrometer and a Doppler pin system in each experiment. Wave profile results show anisotropic elastic-plastic transitions, which confirm the literature observations. Under final shock stress of about 52 GPa, lower emission intensity is observed in the r-cut sample, in agreement with the previous report in the literature. When final shock stress increases to 57 GPa and 65 GPa, spectral radiance histories of the r-cut show two stages of distinct features. In the first stage, the emission intensity of r-cut is lower than those of the other two, which agrees with the previous report in the literature. In the second stage, spectral radiance of r-cut increases with time at much higher rate and it finally peaks over those of the a and c-cut. These observations (conversion of intensified emission in the r-cut) may indicate activation of a second slip system and formation of shear bands which are discussed with the resolved shear stress calculations for the slip systems in each of the three cuts under shock compression.

Soft-core dataflow processor architecture optimised for radar signal processing: Article

CSIR Research Space (South Africa)

Broich, R

2014-10-01

Full Text Available Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use...

Grade Point Average: Report of the GPA Pilot Project 2013-14

Science.gov (United States)

Higher Education Academy, 2015

2015-01-01

This report is published as the result of a range of investigations and debates involving many universities and colleges and a series of meetings, presentations, discussions and consultations. Interest in a grade point average (GPA) system was originally initiated by a group of interested universities, progressing to the systematic investigation…

Merged ozone profiles from four MIPAS processors

Science.gov (United States)

Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

2017-04-01

The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

Keystone Business Models for Network Security Processors

Directory of Open Access Journals (Sweden)

Arthur Low

2013-07-01

Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

Demonstration of two-qubit algorithms with a superconducting quantum processor.

Science.gov (United States)

DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

2009-07-09

Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

Science.gov (United States)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

OLYMPUS system and development of its pre-processor

International Nuclear Information System (INIS)

Okamoto, Masao; Takeda, Tatsuoki; Tanaka, Masatoshi; Asai, Kiyoshi; Nakano, Koh.

1977-08-01

The OLYMPUS SYSTEM developed by K. V. Roverts et al. was converted and introduced in computer system FACOM 230/75 of the JAERI Computing Center. A pre-processor was also developed for the OLYMPUS SYSTEM. The OLYMPUS SYSTEM is very useful for development, standardization and exchange of programs in thermonuclear fusion research and plasma physics. The pre-processor developed by the present authors is not only essential for the JAERI OLYMPUS SYSTEM, but also useful in manipulation, creation and correction of program files. (auth.)

A fast processor for di-lepton triggers

CERN Document Server

Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

1981-01-01

As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

Time Manager Software for a Flight Processor

Science.gov (United States)

Zoerne, Roger

2012-01-01

Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

Bulk-memory processor for data acquisition

International Nuclear Information System (INIS)

Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

1981-01-01

To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

RISC Processors and High Performance Computing

Science.gov (United States)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

Science.gov (United States)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Sensitometric Control of Automatic Processors in a Hospital Center : Retrospective Study

International Nuclear Information System (INIS)

Lobato Busto, R.; Pombar Camean, M.

1992-01-01

This paper analyses the results obtained between February (1990) and July (1991) of the sensitometric control of the seven automatic processors which are in Hospital General de Galicia-Clinico Universitario (Santiago de Compostela). The deviations with regard to the reference values of each processor, permitting the precocious detection of disturbances before being revealed by the image, were analysed. In this analysis, it was achieved that the days in which the automatic processors were out of standing only varied between 2.3% and 5% from the checked days. (author)

Development of a Next-Generation Membrane-Integrated Adsorption Processor for CO2 Removal and Compression for Closed-Loop Air Revitalization Systems

Science.gov (United States)

Mulloth, Lila; LeVan, Douglas

2002-01-01

The current CO2 removal technology of NASA is very energy intensive and contains many non-optimized subsystems. This paper discusses the concept of a next-generation, membrane integrated, adsorption processor for CO2 removal nd compression in closed-loop air revitalization systems. This processor will use many times less power than NASA's current CO2 removal technology and will be capable of maintaining a lower CO2 concentration in the cabin than that can be achieved by the existing CO2 removal systems. The compact, consolidated, configuration of gas dryer, CO2 separator, and CO2 compressor will allow continuous recycling of humid air in the cabin and supply of compressed CO2 to the reduction unit for oxygen recovery. The device has potential application to the International Space Station and future, long duration, transit, and planetary missions.

Rational calculation accuracy in acousto-optical matrix-vector processor

Science.gov (United States)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

Making (up) the grade? estimating the genetic and environmental influences of discrepancies between self-reported grades and official GPA scores.

Science.gov (United States)

Schwartz, Joseph A; Beaver, Kevin M

2015-05-01

Academic achievement has been found to have a pervasive and substantial impact on a wide range of developmental outcomes and has also been implicated in the critical transition from adolescence into early adulthood. Previous research has revealed that self-reported grades tend to diverge from official transcript grade point average (GPA) scores, with students being more likely to report inflated scores. Making use of a sample of monozygotic twin (N = 282 pairs), dizygotic twin (N = 441 pairs), and full sibling (N = 1,757 pairs) pairs from the National Longitudinal Study of Adolescent Health (Add Health; 65 % White; 50 % male; mean age = 16.14), the current study is the first to investigate the role that genetic and environmental factors play in misreporting grade information. A comparison between self-reported GPA (mean score of 2.86) and official transcript GPA scores (mean score of 2.44) revealed that self-reported scores were approximately one-half letter grade greater than official scores. Liability threshold models revealed that additive genetic influences explained between 40 and 63 % of the variance in reporting inflated grades and correctly reporting GPA, with the remaining variance explained by the nonshared environment. Conversely, 100 % of the variance in reporting deflated grade information was explained by nonshared environmental influences. In an effort to identify specific nonshared environmental influences on reporting accuracy, multivariate models that adequately control for genetic influences were estimated and revealed that siblings with lower transcript GPA scores were significantly less likely to correctly report their GPA and significantly more likely to report inflated GPA scores. Additional analyses revealed that verbal IQ and self-control were not significantly associated with self-reported GPA accuracy after controlling for genetic influences. These findings indicate that previous studies that implicate verbal IQ and self

Post-silicon and runtime verification for modern processors

CERN Document Server

Wagner, Ilya

2010-01-01

The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

Ring-array processor distribution topology for optical interconnects

Science.gov (United States)

Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

1992-01-01

The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

Reconfigurable lattice mesh designs for programmable photonic processors.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

2016-05-30

We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

Interactive high-resolution isosurface ray casting on multicore processors.

Science.gov (United States)

Wang, Qin; JaJa, Joseph

2008-01-01

We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

Science.gov (United States)

2012-01-03

... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

New technological developments in gas processing

International Nuclear Information System (INIS)

Draper, R.C.

1996-01-01

The changes that the natural gas industry has undergone over the last few years was discussed. Low natural gas prices forced companies to react to their high reserves replacements costs. They were forced to downsize and undergo major restructuring because they were losing money due to high operating costs; the future for natural gas prices looked pessimistic. The changes have led to a new kind of business practice, namely 'partnering with third party processor', mid-stream companies known as aggregators, to build and operate facilities as part of a move towards cost effective improvements for gas producers. Besides reducing capital and operating costs, the producer under this arrangements can dedicate his capital to finding new gas which is the basis of growth. Recent technological changes in the gas processing industry were also touched upon. These included enhanced technologies such as increased liquid hydrocarbon recovery, segregation of C3+ and C5+, installation of gas separation membrane systems, small sulphur plants, acid gas injection and selective or mixed solvents. Details of some of these technologies were described. 2 refs., 2 figs

Monte Carlo photon transport on shared memory and distributed memory parallel processors

International Nuclear Information System (INIS)

Martin, W.R.; Wan, T.C.; Abdel-Rahman, T.S.; Mudge, T.N.; Miura, K.

1987-01-01

Parallelized Monte Carlo algorithms for analyzing photon transport in an inertially confined fusion (ICF) plasma are considered. Algorithms were developed for shared memory (vector and scalar) and distributed memory (scalar) parallel processors. The shared memory algorithm was implemented on the IBM 3090/400, and timing results are presented for dedicated runs with two, three, and four processors. Two alternative distributed memory algorithms (replication and dispatching) were implemented on a hypercube parallel processor (1 through 64 nodes). The replication algorithm yields essentially full efficiency for all cube sizes; with the 64-node configuration, the absolute performance is nearly the same as with the CRAY X-MP. The dispatching algorithm also yields efficiencies above 80% in a large simulation for the 64-processor configuration

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

User manual Dieka PreProcessor

NARCIS (Netherlands)

Valkering, Kasper

2000-01-01

This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

High-Pressure and High-Temperature in situ X-Ray Diffraction Study of FeP2 up to 70 GPa

International Nuclear Information System (INIS)

Gu Ting-Ting; Wu Xiang; Qin Shan; Liu Jing; Li Yan-Chun; Zhang Yu-Feng

2012-01-01

The high-pressure and high-temperature structural behavior of FeP 2 is investigated by means of synchrotron x-ray powder diffraction combined with a laser heating technique up to 70 GPa and at least 1800 K. No phase transition of FeP 2 occurs up to 68 GPa at room temperature. While a new phase of FeP 2 assigned to the CuAl 2 -type structure (I4/mcm, Z = 4) is observed at 70 GPa after laser-heating. This new phase presents a quenchable property on decompression to ambient conditions. Our results update previous experimental data and are consistent with theoretical studies. (condensed matter: structure, mechanical and thermal properties)

In situ XRD study of C60 polymerisation above pressures of 9 GPa and temperatures up to 830K

International Nuclear Information System (INIS)

Talyzin, A.V.; Jansson, U.; Dubrovinsky, L.S.; Oden, M.; Le Bihan, T.

2002-01-01

The C60 polymerization was studied by X-ray diffraction in situ in the pressure range 13-18 GPa and at temperatures up to 830 K. The results of the high pressure high temperature treatment are strongly dependent from the history of the sample and stress. At certain conditions no elliptical diffraction patterns were observed at 13 GPa and 830K. Samples with a relatively low internal stress showed a transformation to new phase. It is suggested that this phase is three-dimensional polymer with each C60 molecule bonded to eight neighbors. This phase showed an increased hardness (about 37 GPa) and a Raman spectrum distinctly different from previously known polymeric phases

Effect of material strength on the relationship between the principal Hugoniot and quasi-isentrope of beryllium and 6061-T6 aluminum below 35 GPa

International Nuclear Information System (INIS)

Moss, W.C.

1985-01-01

Quasi-isentropic (QI) compression can be achieved by loading a specimen with a low strain rate, long rise time uniaxial strain wave. Recent experimental data show that the quasi-isentrope of 6061-T6 aluminum lies a few percent above the principal Hugoniot, that is, at a given specific volume, the QI stress exceeds the principal Hugoniot stress. It has been suggested that this effect is due to material strength. Using Hugoniot data, shock-reshock, and shock-unload data for beryllium and 6061-T6 aluminum, we have constructed the quasi-isentropes as functions of specific volume. Our results show that the QI stress exceeds the principal Hugoniot stress above a Hugoniot stress of 8.4 GPa in beryllium, and between Hugoniot stresses of 3.8 and 21.4 GPa in aluminum. The effect is due to strength and implies that the QI yield strength can be large. Our calculations show that the QI yield strength is 0.9 GPa in aluminum at a QI stress of 9 GPa, and 5.2 GPa in beryllium at a QI stress of 35 GPa

Evaluation of the Intel Westmere-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2011-01-01

One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

3081/E processor and its on-line use

International Nuclear Information System (INIS)

Rankin, P.; Bricaud, B.; Gravina, M.

1985-05-01

The 3081/E is a second generation emulator of a mainframe IBM. One of it's applications will be to form part of the data acquisition system of the upgraded Mark II detector for data taking at the SLAC linear collider. Since the processor does not have direct connections to I/O devices a FASTBUS interface will be provided to allow communication with both SLAC Scanner Processors (which are responsible for the accumulation of data at a crate level) and the experiment's VAX 8600 mainframe. The 3081/E's will supply a significant amount of on-line computing power to the experiment (a single 3081/E is equivalent to 4 to 5 VAX 11/780's). A major advantage of the 3081/E is that program development can be done on an IBM mainframe (such as the one used for off-line analysis) which gives the programmer access to a full range of debugging tools. The processor's performance can be continually monitored by comparison of the results obtained using it to those given when the same program is run on an IBM computer. 9 refs

40 CFR 80.220 - What are the downstream standards for GPA gasoline?

Science.gov (United States)

2010-07-01

... 40 Protection of Environment 16 2010-07-01 2010-07-01 false What are the downstream standards for GPA gasoline? 80.220 Section 80.220 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY... downstream location other than at a retail outlet or wholesale purchaser-consumer facility, and during the...

An intercomparison of Canadian external dosimetry processors for radiation protection

International Nuclear Information System (INIS)

1989-10-01

The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations

A high-speed analog neural processor

NARCIS (Netherlands)

Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

1994-01-01

Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

Processor farming in two-level analysis of historical bridge

Science.gov (United States)

Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

2017-11-01

This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

Array processors: an introduction to their architecture, software, and applications in nuclear medicine

International Nuclear Information System (INIS)

King, M.A.; Doherty, P.W.; Rosenberg, R.J.; Cool, S.L.

1983-01-01

Array processors are ''number crunchers'' that dramatically enhance the processing power of nuclear medicine computer systems for applicatons dealing with the repetitive operations involved in digital image processing of large segments of data. The general architecture and the programming of array processors are introduced, along with some applications of array processors to the reconstruction of emission tomographic images, digital image enhancement, and functional image formation

Compaction of Ceramic Microspheres, Spherical Molybdenum Powder and Other Materials to 3 GPa

International Nuclear Information System (INIS)

Carlson, S R; Bonner, B P; Ryerson, F J; Hart, M M

2006-01-01

Pressure-volume relationships were measured at room temperature for eight granular materials and one specimen of epoxy foam. The granular materials included hollow ceramic microspheres, spherical molybdenum powder, Ottawa sand, aluminum, copper, titanium and silicon carbide powders and glassy carbon spheres. Measurements were made to 0.9 GPa in a liquid medium press for all of the granular materials and to 3 GPa in a solid medium press for the ceramic microspheres and molybdenum powder. A single specimen of epoxy foam was compressed to 30 MPa in the liquid medium press. Bulk moduli were calculated as a function of pressure for the ceramic microspheres, the molybdenum powder and three other granular materials. The energy expended in compacting the granular materials was determined by numerically integrating pressure-volume curves. More energy was expended per unit volume in compacting the molybdenum powder to 1 GPa than for the other materials, but compaction of the ceramic microspheres required more energy per gram due to their very low initial density. The merge pressure, the pressure at which all porosity is removed, was estimated for each material by plotting porosity against pressure on a semi-log plot. The pressure-volume curves were then extrapolated to the predicted merge pressures and numerically integrated to estimate the energy required to reach full density for each material. The results suggest that the glassy carbon spheres and the ceramic microspheres would require more energy than the other materials to attain full density

The Danish real-time SAR processor: first results

DEFF Research Database (Denmark)

Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders

1993-01-01

A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

Science.gov (United States)

Manolakos, Elias S.

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

Science.gov (United States)

Sharma, Anuj; Manolakos, Elias S

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

Lattice strains in gold and rhenium under nonhydrostatic compression to 37 GPa

International Nuclear Information System (INIS)

Duffy, Thomas S.; Shen, Guoyin; Heinz, Dion L.; Shu, Jinfu; Ma, Yanzhang; Mao, Ho-Kwang; Hemley, Russell J.; Singh, Anil K.

1999-01-01

Using energy-dispersive x-ray diffraction techniques together with the theory describing lattice strains under nonhydrostatic compression, the behavior of a layered sample of gold and rhenium has been studied at pressures of 14-37 GPa. For gold, the uniaxial stress component t is consistent with earlier studies and can be described by t=0.06+0.015P where P is the pressure in GPa. The estimated single-crystal elastic moduli are in reasonable agreement with trends based on extrapolated low-pressure data. The degree of elastic anisotropy increases as α, the parameter which characterizes stress-strain continuity across grain boundaries, is reduced from 1.0 to 0.5. For rhenium, the apparent equation of state has been shown to be strongly influenced by nonhydrostatic compression, as evidenced by its dependence on the angle ψ between the diffracting plane normal and the stress axis. The bulk modulus obtained by inversion of nonhydrostatic compression data can differ by nearly a factor of 2 at angles of 0 degree sign and 90 degree sign . On the other hand, by a proper choice of ψ, d spacings corresponding to quasihydrostatic compression can be obtained from data obtained under highly nonhydrostatic conditions. The uniaxial stress in rhenium over the pressure range from 14-37 GPa can be described by t=2.5+0.09P. The large discrepancy between x-ray elastic moduli and ultrasonic data and theoretical calculations indicates that additional factors such as texturing or orientation dependence of t need to be incorporated to more fully describe the strain distribution in hexagonal-close-packed metals. (c) 1999 The American Physical Society

Case study of a gas plant alliance at Zama Lake

International Nuclear Information System (INIS)

Clark, S.

1998-01-01

The definition of gas processing effectiveness varies according to whether a producer emphasizes maximized production, or the greatest wellhead netback, or the greatest return on investment. The producer's vision and objectives can change over time, depending on his financial needs, changes in the investment market, shareholder perceptions, or management motivation. This article describes how a third party processor like Novagas Canada Limited (NCL) can help a producer achieve his objectives. The case of NCL's Zama Lake investment and alliance with Phillips Petroleum is used to illustrate the process. Based on this example, a third party processor can provide important midstream services such as raw gas gathering, field compression, gas processing, sales gas transmission, natural gas liquids recovery, transportation and fractionation. In addition, they can provide access to associated energy industries such as oil and electricity, or any combination of the above, by structuring their services to suit the individual needs of each producer. A third party producer can also reduce risk and cost, provide increased reliability, add new processing capacity, and increased netback. Details of how the alliance between NCL and Phillips Petroleum came about and the advantages that each partner derived from the partnership are described. By entering into an alliance with NCL, Phillips Petroleum gained value by divesting risk and acquiring low cost midstream services, while NCL gained by increasing its presence and by adding economies of scale and greater flexibility in its investment decisions

ARM Processor Based Embedded System for Remote Data Acquisition

OpenAIRE

Raj Kumar Tiwari; Santosh Kumar Agrahari

2014-01-01

The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

Application of Advanced Multi-Core Processor Technologies to Oceanographic Research

Science.gov (United States)

2013-09-30

1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Application of Advanced Multi-Core Processor Technologies...STM32 NXP LPC series No Proprietary Microchip PIC32/DSPIC No > 500 mW; < 5 W ARM Cortex TI OMAP TI Sitara Broadcom BCM2835 Varies FPGA...state-of-the-art information processing architectures. OBJECTIVES Next-generation processor architectures (multi-core, multi-threaded) hold the

Hardware processors for pattern recognition tasks in experiments with wire chambers

International Nuclear Information System (INIS)

Verkerk, C.

1975-01-01

Hardware processors for pattern recognition tasks in experiments with multiwire proportional chambers or drift chambers are described. They vary from simple ones used for deciding in real time if particle trajectories are straight to complex ones for recognition of curved tracks. Schematics and block-diagrams of different processors are shown

Structure of Mg2SiO4 glass up to 140 GPa

Science.gov (United States)

Prescher, C.; Prakapenka, V.; Wang, Y.; Skinner, L. B.

2014-12-01

The physical properties of melts at temperature and pressure conditions of the Earth's mantle have a fundamental influence on the chemical and thermal evolution of the Earth. However, direct investigations of melt structures at these conditions are experimentally very difficult or even impossible with current capabilities. In order to still be able to obtain an estimate of the structural behavior of melts at high pressures and temperatures, amorphous materials have been widely used as analogue materials. In particular the investigation of sound wave velocities of amorphous SiO2 and MgSiO3 as analogues for silicate melts indicate structural changes at about ~30-40 GPa and ~130-140 GPa [1]. The transition pressures are lower for MgSiO3 than for SiO2 indicating that these transitions are affected by the degree of polymerization of the SiO2 network of the glasses. Nevertheless, these measurements only give a hint about the occurrence of structural transitions but lack information on the actual structural changes accompanied by the sound wave velocity discontinuities. The pressure of the second structural transition at ~130-140 GPa is of vital importance for geophysics. If it causes silicate melts to become denser than the surrounding solid material, it would result in negatively buoyant melts close to the core-mantle boundary, which could be a major factor affecting the chemical stratification of the Earth's mantle during an early magma ocean after the moon forming impact. In order to resolve the structural transition and estimate the effect of a different degree of polymerization further, we studied the structural behavior of Mg2SiO4 glass up to 140 GPa using X-ray total scattering and pair distribution function analysis. The measurements were performed at the GSECARS 13-IDD beamline at the APS employing the newly developed multichannel collimator (MCC) setup. The MCC effectively removes unwanted Compton scattering of the diamond anvils and enables easy extraction of

Thermal Dissipation Efficiency in a Micro-Processor Using Carbon Nanotubes Based Composite

Science.gov (United States)

Thang, Bui Hung; Van Quang, Cao; Nghia, Van Trong; Hong, Phan Ngoc; Van Chuc, Nguyen; Tam, Ngo Thi Thanh; Quang, Le Dinh; Khang, Dao Duc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

Modern electronic and optoelectronic devices such as μ-processor, light emitting diode, semiconductor laser issued a challenge in the thermal dissipation problem. Finding an effective way for thermal dissipation therefore becomes a very important issue. It is known that carbon nanotubes (CNTs) is one of the most valuable materials with high thermal conductivity (2000 W/m.K compared to thermal conductivity of Ag 419 W/m.K). This suggested an approach in applying the CNTs as an essential component for thermal dissipation media to improve the performance of computer processor and other high power electronic devices. In this work multi walled carbon nanotubes (MWCNTs) based composites were utilized as the thermal dissipation media in a micro processor of a personal computer. The MWCNTs of different concentrations were added into polyaniline, commercial silicon thermal paste and commercial silver thermal paste by mechanical methods. A personal computer with configuration: Intel Pentium IV 3.066 GHz, 512 MB of RAM and Windows XP Service Pack 2 Operating System was employed. The thermal dissipation efficiency of the system was evaluated by directly measure the temperature of the μ-processor during the operation of the computer in different CPU speeds. The measured results showed that the CNTs based composite could reduce the temperature of the u-processor more than 5° C, and the time for increasing the temperature of the μ-processor was three times longer than that when using commercial thermal paste.

Video frame processor

International Nuclear Information System (INIS)

Joshi, V.M.; Agashe, Alok; Bairi, B.R.

1993-01-01

This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

Correlation Between Ability on Playing Tetris and GPA

Directory of Open Access Journals (Sweden)

Aprilia Ratna Christanti

2014-10-01

Full Text Available The goal of this study is to determine the correlation between ability on playing Tetris and GPA of Soegijapranata Catholic University, Department of Information System students against the dexterity in playing Tetris. The research has been done using experiment method on ten Information System students who have various grade points. They played Tetris, 30 minutes each, for three consecutive days. The results showed that: First, eight out of the ten students improved their agility. It can be seen from the increasing scores and levels; Second, the coefficient correlation between student grade point and dexterity in playing Tetris is by 62%. Keywords Ability, grade point average, Tetris

High-power selfshielded electron processors and their application to stack gas treatment

International Nuclear Information System (INIS)

Hiley, J.; Frutiger, W.A.; Nablo, S.V.

1987-01-01

The increasing industrial demands for large width (approximately 2 m), high dose rate (1 Mrad at 1500 m/min) electron beam machinery has led to a relatively rapid improvement in this field over the past several years. Selfshielded machinery capable of up to 1000 mA of current at 300 kV is now in commercial use, and the essential features of these designs are presented. A variety of product handling geometries for use with these accelerators has been developed for processes involving flexible web, rigid sheet, and three-dimensional objects in both the polymerization and sterilization applications. One of the major power-intensive processes to which these machines are currently applied is that of the reduction of pollutants (NO x , SO 2 , etc.) in the flue gas from fuel combustion - particularly those fossil fuels used in power production. The preferred technique utilizes the treatment of the ammoniated gas at modest dose levels (0.5-2.0 Mrads) to enhance the formation of ammonium salts which are then removed from the gas stream by conventional filtration. Some results from a 180 kWx300 kV pilot installation in Karlsruhe, Federal Republic of Germany are presented. (orig.)

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Simulation of Particulate Flows Multi-Processor Machines with Distributed Memory

Energy Technology Data Exchange (ETDEWEB)

Uhlmann, M.

2004-07-01

We presented a method for the parallelization of an immersed boundary algorithm for particulate flows using the MPI standard of communication. The treatment of the fluid phase used the domain decomposition technique over a Cartesian processor grid. The solution of the Helmholtz problem is approximately factorized an relies upon apparel tri-diagonal solver the Poisson problem is solved by means of a parallel multi-grid technique similar to MUDPACK. for the solid phase we employ a master-slaves technique where one processor handles all the particles contained in its Eulerian fluid sub-domain and zero or more neighbor processors collaborate in the computation of particle-related quantities whenever a particle position over laps the boundary of a sub-domain. the parallel efficiency for some preliminary computations is presented. (Author) 9 refs.

Effects of Gas-Phase Adsorption air purification on passengers and cabin crew in simulated 11-hour flights

DEFF Research Database (Denmark)

Strøm-Tejsen, Peter; Zukowska, Daria; Fang, Lei

2006-01-01

In a 3-row, 21-seat section of a simulated aircraft cabin that had been installed in a climate chamber, 4 groups of 17 subjects, acting as passengers and crew, took part in simulated 11-hour flights. Each group experienced 4 conditions in balanced order, defined by two outside air supply rates (2.......4 and 3.3 L/s per person), with and without a Gas-Phase Adsorption (GPA) unit in the re-circulated air system. Objective physical and physiological measurements and subjective human assessments of symptom intensity were obtained. The GPA unit provided advantages with no apparent disadvantages....

MORPION: a fast hardware processor for straight line finding in MWPC

International Nuclear Information System (INIS)

Mur, M.

1980-02-01

A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

First-principles simulation of Raman spectra and structural properties of quartz up to 5 GPa

International Nuclear Information System (INIS)

Liu Lei; Lv Chao-Jia; Yi Li; Liu Hong; Du Jian-Guo; Zhuang Chun-Qiang

2015-01-01

The crystal structure and Raman spectra of quartz are calculated by using first-principles method in a pressure range from 0 to 5 GPa. The results show that the lattice constants (a, c, and V) decrease with increasing pressure and the a-axis is more compressible than the c axis. The Si–O bond distance decreases with increasing pressure, which is in contrast to experimental results reported by Hazen et al. [Hazen R M, Finger L W, Hemley R J and Mao H K 1989 Solid State Communications 725 507–511], and Glinnemann et al. [Glinnemann J, King H E Jr, Schulz H, Hahn T, La Placa S J and Dacol F 1992 Z. Kristallogr. 198 177–212]. The most striking changes are of inter-tetrahedral O–O distances and Si–O–Si angles. The volume of the tetrahedron decreased by 0.9% (from 0 to 5 GPa), which suggests that it is relatively rigid. Vibrational models of the quartz modes are identified by visualizing the associated atomic motions. Raman vibrations are mainly controlled by the deformation of the tetrahedron and the changes in the Si–O–Si bonds. Vibrational directions and intensities of atoms in all Raman modes just show little deviations when pressure increases from 0 to 5 GPa. The pressure derivatives (dν i /dP) of the 12 Raman frequencies are obtained at 0 GPa–5 GPa. The calculated results show that first-principles methods can well describe the high-pressure structural properties and Raman spectra of quartz. The combination of first-principles simulations of the Raman frequencies of minerals and Raman spectroscopy experiments is a useful tool for exploring the stress conditions within the Earth. (paper)

3D Seismic Imaging through Reverse-Time Migration on Homogeneous and Heterogeneous Multi-Core Processors

Directory of Open Access Journals (Sweden)

Mauricio Araya-Polo

2009-01-01

Full Text Available Reverse-Time Migration (RTM is a state-of-the-art technique in seismic acoustic imaging, because of the quality and integrity of the images it provides. Oil and gas companies trust RTM with crucial decisions on multi-million-dollar drilling investments. But RTM requires vastly more computational power than its predecessor techniques, and this has somewhat hindered its practical success. On the other hand, despite multi-core architectures promise to deliver unprecedented computational power, little attention has been devoted to mapping efficiently RTM to multi-cores. In this paper, we present a mapping of the RTM computational kernel to the IBM Cell/B.E. processor that reaches close-to-optimal performance. The kernel proves to be memory-bound and it achieves a 98% utilization of the peak memory bandwidth. Our Cell/B.E. implementation outperforms a traditional processor (PowerPC 970MP in terms of performance (with an 15.0× speedup and energy-efficiency (with a 10.0× increase in the GFlops/W delivered. Also, it is the fastest RTM implementation available to the best of our knowledge. These results increase the practical usability of RTM. Also, the RTM-Cell/B.E. combination proves to be a strong competitor in the seismic arena.

Graphics processor efficiency for realization of rapid tabular computations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.

2016-01-01

Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions

FASTBUS Standard Routines implementation for Fermilab embedded processor boards

International Nuclear Information System (INIS)

Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

1992-10-01

In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

Statistical analysis of quality control of automatic processor

International Nuclear Information System (INIS)

Niu Yantao; Zhao Lei; Zhang Wei; Yan Shulin

2002-01-01

Objective: To strengthen the scientific management of automatic processor and promote QC, based on analyzing QC management chart for automatic processor by statistical method, evaluating and interpreting the data and trend of the chart. Method: Speed, contrast, minimum density of step wedge of film strip were measured everyday and recorded on the QC chart. Mean (x-bar), standard deviation (s) and range (R) were calculated. The data and the working trend were evaluated and interpreted for management decisions. Results: Using relative frequency distribution curve constructed by measured data, the authors can judge whether it is a symmetric bell-shaped curve or not. If not, it indicates a few extremes overstepping control limits possibly are pulling the curve to the left or right. If it is a normal distribution, standard deviation (s) is observed. When x-bar +- 2s lies in upper and lower control limits of relative performance indexes, it indicates the processor works in stable status in this period. Conclusion: Guided by statistical method, QC work becomes more scientific and quantified. The authors can deepen understanding and application of the trend chart, and improve the quality management to a new step

Broadband set-top box using MAP-CA processor

Science.gov (United States)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

Structural stability of boron carbide under pressure proven by spectroscopic studies up to 73 GPa

Energy Technology Data Exchange (ETDEWEB)

Chuvashova, Irina [Material Physics and Technology at Extreme Conditions, Laboratory of Crystallography, University of Bayreuth (Germany); Bayerisches Geoinstitut, University of Bayreuth (Germany); Gasharova, Biliana; Mathis, Yves-Laurent [IBPT, Karlsruhe Institute of Technology, Karlsruhe (Germany); Dubrovinsky, Leonid [Bayerisches Geoinstitut, University of Bayreuth (Germany); Dubrovinskaia, Natalia [Material Physics and Technology at Extreme Conditions, Laboratory of Crystallography, University of Bayreuth (Germany)

2017-11-17

Being a material of choice for lightweight armor applications, boron carbide has been intensively studied. Its behavior under pressure was investigated using both theoretical and experimental methods, such as powder X-ray diffraction and vibrational spectroscopy. As there is a discrepancy in experimental observations, in the presented work we studied vibrational properties of commercially available, ''nearly stoichiometric'' B{sub 4}C using IR and Raman spectroscopy up to 73 GPa. No phase transitions were found in the entire pressure range. Our results are at odds with the recent report of a phase transition in B{sub 4.3}C at about 40 GPa. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

Use of a track and vertex processor in a fixed-target charm experiment

International Nuclear Information System (INIS)

Schub, M.H.; Carey, T.A.; Hsiung, Y.B.; Kaplan, D.M.; Lee, C.; Miller, G.; Sa, J.; Teng, P.K.

1996-01-01

We have constructed and operated a high-speed parallel-pipelined track and vertex processor and used it to trigger data acquisition in a high-rate charm and beauty experiment at Fermilab. The processor uses information from hodoscopes and wire chambers to reconstruct tracks in the bend view of a magnetic spectrometer, and uses these tracks to find the corresponding tracks in a set of silicon-strip detectors. The processor then forms vertices and triggers the experiment if at least one vertex is downstream of the target. Under typical charm running conditions, with an interaction rate of ∼5 MHz, the processor rejects 80-90% of lower-level triggers while maintaining efficiency of ∼70% for two-prong D-meson decays. (orig.)

Simplifying cochlear implant speech processor fitting

NARCIS (Netherlands)

Willeboer, C.

2008-01-01

Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

A prediction method for job runtimes on shared processors: Survey, statistical analysis and new avenues

NARCIS (Netherlands)

Dobber, A.M.; van der Mei, R.D.; Koole, G.M.

2007-01-01

Grid computing is an emerging technology by which huge numbers of processors over the world create a global source of processing power. Their collaboration makes it possible to perform computations that are too extensive to perform on a single processor. On a grid, processors may connect and

Design of Processors with Reconfigurable Microarchitecture

Directory of Open Access Journals (Sweden)

Andrey Mokhov

2014-01-01

Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

Coordinated Energy Management in Heterogeneous Processors

Directory of Open Access Journals (Sweden)

Indrani Paul

2014-01-01

Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

A Bayesian sequential processor approach to spectroscopic portal system decisions

Energy Technology Data Exchange (ETDEWEB)

Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

2007-07-31

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

Parallelising a molecular dynamics algorithm on a multi-processor workstation

Science.gov (United States)

Müller-Plathe, Florian

1990-12-01

The Verlet neighbour-list algorithm is parallelised for a multi-processor Hewlett-Packard/Apollo DN10000 workstation. The implementation makes use of memory shared between the processors. It is a genuine master-slave approach by which most of the computational tasks are kept in the master process and the slaves are only called to do part of the nonbonded forces calculation. The implementation features elements of both fine-grain and coarse-grain parallelism. Apart from three calls to library routines, two of which are standard UNIX calls, and two machine-specific language extensions, the whole code is written in standard Fortran 77. Hence, it may be expected that this parallelisation concept can be transfered in parts or as a whole to other multi-processor shared-memory computers. The parallel code is routinely used in production work.

Real time processor for array speckle interferometry

International Nuclear Information System (INIS)

Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

1989-01-01

With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

UNIBUS processor interface for a FASTBUS data acquisition system

International Nuclear Information System (INIS)

Larwill, M.; Lagerlund, T.D.; Barsotti, E.; Taff, L.M.; Franzen, J.

1981-01-01

Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS ''event builder'' (i.e., data acquisition processor). Primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. Some possible FASTBUS data acquisition system architectures employing the UPI are discussed along with some detailed specifications of the UPI itself

The UA1 trigger processor

International Nuclear Information System (INIS)

Grayer, G.H.

1981-01-01

Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

High-precision measurements of the compressibility of chalcogenide glasses at a hydrostatic pressure up to 9 GPa

Energy Technology Data Exchange (ETDEWEB)

Brazhkin, V. V., E-mail: brazhkin@hppi.troitsk.ru [Vereshchagin Institute of High-Pressure Physics (Russian Federation); Bychkov, E. [Universite du Littoral, LPCA, UMR 8101 CNRS (France); Tsiok, O. B. [Vereshchagin Institute of High-Pressure Physics (Russian Federation)

2016-08-15

The volumes of glassy germanium chalcogenides GeSe{sub 2}, GeS{sub 2}, Ge{sub 17}Se{sub 83}, and Ge{sub 8}Se{sub 92} are precisely measured at a hydrostatic pressure up to 8.5 GPa. The stoichiometric GeSe{sub 2} and GeS{sub 2} glasses exhibit elastic behavior in the pressure range up to 3 GPa, and their bulk modulus decreases at pressures higher than 2–2.5 GPa. At higher pressures, inelastic relaxation processes begin and their intensity is proportional to the logarithm of time. The relaxation rate for the GeSe{sub 2} glasses has a pronounced maximum at 3.5–4.5 GPa, which indicates the existence of several parallel structural transformation mechanisms. The nonstoichiometric glasses exhibit a diffuse transformation and inelastic behavior at pressures above 1–2 GPa. The maximum relaxation rate in these glasses is significantly lower than that in the stoichiometric GeSe{sub 2} glasses. All glasses are characterized by the “loss of memory” of history: after relaxation at a fixed pressure, the further increase in the pressure returns the volume to the compression curve obtained without a stop for relaxation. After pressure release, the residual densification in the stoichiometric glasses is about 7% and that in the Ge{sub 17}Se{sub 83} glasses is 1.5%. The volume of the Ge{sub 8}Se{sub 92} glass returns to its initial value within the limits of experimental error. As the pressure decreases, the effective bulk moduli of the Ge{sub 17}Se{sub 83} and Ge{sub 8}Se{sub 92} glasses coincide with the moduli after isobaric relaxation at the stage of increasing pressure, and the bulk modulus of the stoichiometric GeSe{sub 2} glass upon decreasing pressure noticeably exceeds the bulk modulus after isobaric relaxation at the stage of increasing pressure. Along with the reported data, our results can be used to draw conclusions regarding the diffuse transformations in glassy germanium chalcogenides during compression.

Suboptimal processor for anomaly detection for system surveillance and diagnosis

Energy Technology Data Exchange (ETDEWEB)

Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van

1989-06-01

Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.

A Trade Study of Two Membrane-Aerated Biological Water Processors

Science.gov (United States)

Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

2011-01-01

Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

The equation of state of PbTiO sub 3 up to 37 GPa: a synchrotron x-ray powder diffraction study

CERN Document Server

Sani, A; Levy, D

2002-01-01

High-pressure synchrotron x-ray powder diffraction patterns were collected using ID09 of ESRF (Grenoble, France) for a powder sample of PbTiO sub 3 , placed in a diamond anvil cell. The patterns were collected at room temperature using nitrogen (up to 37 GPa) and methanol-ethanol solution (up to 7 GPa) as pressure-transmitting media. The bulk moduli were calculated for the first time using the Vinet equation of state and they were compared to those of isostructural compounds. The trend of the spontaneous polarization as a function of pressure confirms that the ferroelectric-paraelectric phase transition at 11.2 GPa possesses a second-order character.

A sensitive pressure sensor for diamond anvil cell experiments up to 2 GPa: FluoSpheres[reg

International Nuclear Information System (INIS)

Picard, Aude; Oger, Phil M.; Daniel, Isabelle; Cardon, Herve; Montagnac, Gilles; Chervin, Jean-Claude

2006-01-01

We present an optical pressure sensor suitable for experiments in diamond anvil cell in the 0.1 MPa-2 GPa pressure range, for temperatures between ambient and 323 K. It is based on the pressure-dependent fluorescence spectrum of FluoSpheres[reg], which are commercially available fluorescent microspheres commonly used to measure blood flow in experimental biology. The fluorescence of microspheres is excited by the 514.5 nm line of an Ar + laser, and the resulting spectrum displays three very intense broad bands at 534, 558, and 598 nm, respectively. The reference wavelength and pressure gauge is that of the first inflection point of the spectrum, located at 525.6±0.2 nm at ambient pressure. It is characterized by an instantaneous and large linear pressure shift of 9.93(±0.08) nm/GPa. The fluorescence of the FluoSpheres[reg] has been investigated as a function of pressure (0.1-4 GPa), temperature (295-343 K), pH (3-12), salinity, and pressure transmitting medium. These measurements show that, for pressures comprised between 0.1 MPa and 2 GPa, at temperatures not exceeding 323 K, at any pH, in aqueous pressure transmitting media, pressure can be calculated from the wavelength shift of two to three beads, according to the relation P=0.100 (±0.001) Δλ i (P) with Δλ i (P)=λ i (P)-λ i (0) and λ i (P) as the wavelength of the first inflection point of the spectrum at the pressure P. This pressure sensor is approximately thirty times more sensitive than the ruby scale and responds instantaneously to pressure variations

Sound velocities of skiagite-iron-majorite solid solution to 56 GPa probed by nuclear inelastic scattering

Science.gov (United States)

Vasiukov, D. M.; Ismailova, L.; Kupenko, I.; Cerantola, V.; Sinmyo, R.; Glazyrin, K.; McCammon, C.; Chumakov, A. I.; Dubrovinsky, L.; Dubrovinskaia, N.

2018-05-01

High-pressure experimental data on sound velocities of garnets are used for interpretation of seismological data related to the Earth's upper mantle and the mantle transition zone. We have carried out a Nuclear Inelastic Scattering study of iron-silicate garnet with skiagite (77 mol%)-iron-majorite composition in a diamond anvil cell up to 56 GPa at room temperature. The determined sound velocities are considerably lower than sound velocities of a number of silicate garnet end-members, such as grossular, pyrope, Mg-majorite, andradite, and almandine. The obtained sound velocities have the following pressure dependencies: V p [km/s] = 7.43(9) + 0.039(4) × P [GPa] and V s [km/s] = 3.56(12) + 0.012(6) × P [GPa]. We estimated sound velocities of pure skiagite and khoharite, and conclude that the presence of the iron-majorite component in skiagite strongly decreases V s . We analysed the influence of Fe3+ on sound velocities of garnet solid solution relevant to the mantle transition zone and consider that it may reduce sound velocities up to 1% relative to compositions with only Fe2+ in the cubic site.

The Principal Hugoniot of Forsterite to 950 GPa

Science.gov (United States)

Root, Seth; Townsend, Joshua P.; Davies, Erik; Lemke, Raymond W.; Bliss, David E.; Fratanduono, Dayne E.; Kraus, Richard G.; Millot, Marius; Spaulding, Dylan K.; Shulenburger, Luke; Stewart, Sarah T.; Jacobsen, Stein B.

2018-05-01

Forsterite (Mg2SiO4) single crystals were shock compressed to pressures between 200 and 950 GPa using independent plate-impact steady shocks and laser-driven decaying shock compression experiments. Additionally, we performed density functional theory-based molecular dynamics to aid interpretation of the experimental data and to investigate possible phase transformations and phase separations along the Hugoniot. We show that the experimentally obtained Hugoniot cannot distinguish between a pure liquid Mg2SiO4 and an assemblage of solid MgO plus liquid magnesium silicate. The measured reflectivity is nonzero and increases with pressure, which implies that the liquid is a poor electrical conductor at low pressures and that the conductivity increases with pressure.

Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

Science.gov (United States)

Casasent, D.; Jackson, J.

1986-01-01

A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

The Square Kilometre Array Science Data Processor. Preliminary compute platform design

International Nuclear Information System (INIS)

Broekema, P.C.; Nieuwpoort, R.V. van; Bal, H.E.

2015-01-01

The Square Kilometre Array is a next-generation radio-telescope, to be built in South Africa and Western Australia. It is currently in its detailed design phase, with procurement and construction scheduled to start in 2017. The SKA Science Data Processor is the high-performance computing element of the instrument, responsible for producing science-ready data. This is a major IT project, with the Science Data Processor expected to challenge the computing state-of-the art even in 2020. In this paper we introduce the preliminary Science Data Processor design and the principles that guide the design process, as well as the constraints to the design. We introduce a highly scalable and flexible system architecture capable of handling the SDP workload

An enhanced Ada run-time system for real-time embedded processors

Science.gov (United States)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

Science.gov (United States)

Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

2016-04-01

In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

The valence state of Yb metal under high pressure determined by XANES measurement up to 34.6 GPa

International Nuclear Information System (INIS)

Fuse, Akinori; Nakamoto, Go; Kurisu, Makio; Ishimatsu, Naoki; Tanida, Hajime

2004-01-01

The purpose of this study was to accurately determine the valency of Yb at high pressure and room temperature and to clarify the relation between the valence state and the crystal structure of Yb metal. L III -edge X-ray absorption near-edge structure (XANES) spectra were measured to determine the valence state of Yb metal in the pressure range from 0 to 34.6 GPa at room temperature, using a diamond anvil cell (DAC) and synchrotron radiation at SPring-8. In the fcc phase, Yb metal exhibits mixed valence (the mean valence ν-bar >2.1). At the fcc-to-bcc phase transition, a 0.1 jump is found in ν-bar. In the bcc phase, ν-bar(P) is an increasing function of pressure with downward curvature, reaching only 2.55 at 26 GPa. The ν-bar is only 2.65 in the hcp phase at 34.6 GPa. A tendency for saturation in ν-bar(P) to values smaller than 3.0 is found

Initial explorations of ARM processors for scientific computing

International Nuclear Information System (INIS)

Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad

2014-01-01

Power efficiency is becoming an ever more important metric for both high performance and high throughput computing. Over the course of next decade it is expected that flops/watt will be a major driver for the evolution of computer architecture. Servers with large numbers of ARM processors, already ubiquitous in mobile computing, are a promising alternative to traditional x86-64 computing. We present the results of our initial investigations into the use of ARM processors for scientific computing applications. In particular we report the results from our work with a current generation ARMv7 development board to explore ARM-specific issues regarding the software development environment, operating system, performance benchmarks and issues for porting High Energy Physics software

SPP: A data base processor data communications protocol

Science.gov (United States)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

A further step toward H2 in automobile : development of an efficient bi-functional catalyst for single stage water gas shift

NARCIS (Netherlands)

Azzam, K.G.H.

2008-01-01

The suitability of polymer electrolyte fuel (PEM) cells for stationary and vehicular applications initiated research in all areas of fuel processor (i.e. reformer, water-gas-shift, preferential oxidation of CO (PROX)) catalysts for hydrogen generation. Water gas shift (WGS) reaction is an essential

A discussion of tools and techniques for distributed processor based control systems using CAMAC

International Nuclear Information System (INIS)

Tippie, J.W.; Scandora, A.E.

1985-01-01

This paper describes and analyzes various distributed processor architectures using commercially available CAMAC components. The general orientation is toward distributed control systems using Digital Equipment Corporation LSI11 processors in a CAMAC environment. The paper describes in detail software tools available to simplify the development of applications software and to provide a high-level runtime environment both at the host and the remote processors. Discussion focuses on techniques for downloading of operating systems from a large host and applications tasks written in high-level languages. It also discusses software tools which enable tasks in the remote processors to exchange messages and data with tasks in the host in a simple and elegant way

Expert System Constant False Alarm Rate (CFAR) Processor

National Research Council Canada - National Science Library

Wicks, Michael C

2006-01-01

An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...

40 CFR 80.540 - How may a refiner be approved to produce gasoline under the GPA gasoline sulfur standards in 2007...

Science.gov (United States)

2010-07-01

... produce gasoline under the GPA gasoline sulfur standards in 2007 and 2008? 80.540 Section 80.540... Marine Fuel Geographic Phase-in Provisions § 80.540 How may a refiner be approved to produce gasoline under the GPA gasoline sulfur standards in 2007 and 2008? (a) A refiner that has been approved by EPA...

Choosing processor array configuration by performance modeling for a highly parallel linear algebra algorithm

International Nuclear Information System (INIS)

Littlefield, R.J.; Maschhoff, K.J.

1991-04-01

Many linear algebra algorithms utilize an array of processors across which matrices are distributed. Given a particular matrix size and a maximum number of processors, what configuration of processors, i.e., what size and shape array, will execute the fastest? The answer to this question depends on tradeoffs between load balancing, communication startup and transfer costs, and computational overhead. In this paper we analyze in detail one algorithm: the blocked factored Jacobi method for solving dense eigensystems. A performance model is developed to predict execution time as a function of the processor array and matrix sizes, plus the basic computation and communication speeds of the underlying computer system. In experiments on a large hypercube (up to 512 processors), this model has been found to be highly accurate (mean error ∼ 2%) over a wide range of matrix sizes (10 x 10 through 200 x 200) and processor counts (1 to 512). The model reveals, and direct experiment confirms, that the tradeoffs mentioned above can be surprisingly complex and counterintuitive. We propose decision procedures based directly on the performance model to choose configurations for fastest execution. The model-based decision procedures are compared to a heuristic strategy and shown to be significantly better. 7 refs., 8 figs., 1 tab

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

Science.gov (United States)

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

Beeldverwerking met de Micron Automatic Processor

OpenAIRE

Goyens, Frank

2017-01-01

Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

OpenAIRE

Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

2016-01-01

Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

Using of opportunities of graphic processors for acceleration of scientific and technical calculations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Sereda, T.M.; Us, S.A.; Shestakov, M.V.

2009-01-01

The new opportunities of modern graphic processors (GPU) for acceleration of the scientific and technical calculations with the help of paralleling of a calculating task between the central processor and GPU are described. The description of using the technology NVIDIA CUDA for connection of parallel computing opportunities of GPU within the programme of the some intensive mathematical tasks is resulted. The examples of comparison of parameters of productivity in the process of these tasks' calculation without application of GPU and with use of opportunities NVIDIA CUDA for graphic processor GeForce 8800 are resulted

Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

NARCIS (Netherlands)

Anjam, F.

2013-01-01

In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

Trigger and decision processors

International Nuclear Information System (INIS)

Franke, G.

1980-11-01

In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

Optical Finite Element Processor

Science.gov (United States)

Casasent, David; Taylor, Bradley K.

1986-01-01

A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

Radiation Tolerant Software Defined Video Processor, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

Demographic and Psychological Predictors of Grade Point Average (GPA) in North-Norway: A Particular Analysis of Cognitive/School-Related and Literacy Problems

Science.gov (United States)

Saele, Rannveig Grøm; Sørlie, Tore; Nergård-Nilssen, Trude; Ottosen, Karl-Ottar; Goll, Charlotte Bjørnskov; Friborg, Oddgeir

2016-01-01

Approximately 30% of students drop out from Norwegian upper secondary schools. Academic achievement, as indexed by grade point average (GPA), is one of the strongest predictors of dropout. The present study aimed to examine the role of cognitive, school-related and affective/psychological predictors of GPA. In addition, we examined the…

The fast tracker processor for hadronic collider triggers

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

2000-01-01

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

Digital implementation of the preloaded filter pulse processor

International Nuclear Information System (INIS)

Westphal, G.P.; Cadek, G.R.; Keroe, N.; Sauter, TH.; Thorwartl, P.C.

1995-01-01

Adapting it's processing time to the respective pulse intervals, the Preloaded Filter (PLF) pulse processor offers optimum resolution together with highest possible throughput rates. The PLF algorithm could be formulated in a recursive manner which made possible it's implementation by means of a large field-programmable gate array, as a fast, pipe-lined digital processor with 10 MHz maximum throughput rate. While pre-filter digitization by an ADC with 12 bit resolution and 10M Hz sampling rate resulted in a poorer resolution than that of an analog filter, a digital PLF based on an ADC with 14 bit resolution and 10 MHz sampling rate, surpassed high-quality analog filters in resolution, throughput rate and long-term stability. (author) 6 refs.; 7 figs

Debye temperature, thermal expansion, and heat capacity of TcC up to 100 GPa

Energy Technology Data Exchange (ETDEWEB)

Song, T., E-mail: songting@mail.lzjtu.cn [School of Mathematics and Physics, Lanzhou Jiaotong University, Lanzhou 730070 (China); School of Material Science and Engineering, Lanzhou University of Technology, Lanzhou 730050 (China); Ma, Q. [School of Material Science and Engineering, Lanzhou University of Technology, Lanzhou 730050 (China); Tian, J.H. [School of Mathematics and Physics, Lanzhou Jiaotong University, Lanzhou 730070 (China); Liu, X.B. [School of Physics and Information Science, Tianshui Normal University, Tianshui 741000 (China); Ouyang, Y.H.; Zhang, C.L.; Su, W.F. [School of Mathematics and Physics, Lanzhou Jiaotong University, Lanzhou 730070 (China)

2015-01-15

Highlights: • A number of thermodynamic properties of rocksalt TcC are investigated for the first time. • The quasi-harmonic Debye model is applied to take into account the thermal effect. • The pressure and temperature up to about 100 GPa and 3000 K, respectively. - Abstract: Debye temperature, thermal expansion coefficient, and heat capacity of ideal stoichiometric TcC in the rocksalt structure have been studied systematically by using ab initio plane-wave pseudopotential density functional theory method within the generalized gradient approximation. Through the quasi-harmonic Debye model, in which the phononic effects are considered, the dependences of Debye temperature, thermal expansion coefficient, constant-volume heat capacity, and constant-pressure heat capacity on pressure and temperature are successfully predicted. All the thermodynamic properties of TcC with rocksalt phase have been predicted in the entire temperature range from 300 to 3000 K and pressure up to 100 GPa.

学科GPA を利用した学生の学修意欲を把握する指標

OpenAIRE

岸上, 明生

2016-01-01

GPA（Grade Point Average）制度は，岐阜女子大学に平成24 年度より導入された。健康栄養学科の国試対策室は，専門科目の成績を用いたGPA（学科GPA）を算出し，学科GPA と国家試験結果の相関を検討した結果，累積GPA を学生指導に用いる方法を提案している。厳密な運用が困難な累積GPA は，別の指標で補完することで利用範囲が広がる可能性がある。新しい指標の候補として，学科GPA より近似一次関数の傾き（Slope）を算出し，その特徴を評価した。Slope が学修意欲を反映する可能性が示唆され，累積GPA の利用を補助することが期待される。...

Dual shear plate power processor packaging design. [for Solar Electric Propulsion spacecraft

Science.gov (United States)

Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.

1975-01-01

The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.

Parallel processor programs in the Federal Government

Science.gov (United States)

Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.

1985-01-01

In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

OpenAIRE

Hristov Ivan; Goranov Goran; Hristova Radoslava

2018-01-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP”) in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL). The results show 2 times better per...

Global synchronization of parallel processors using clock pulse width modulation

Science.gov (United States)

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Pathway Processor 2.0: a web resource for pathway-based analysis of high-throughput data.

Science.gov (United States)

Beltrame, Luca; Bianco, Luca; Fontana, Paolo; Cavalieri, Duccio

2013-07-15

Pathway Processor 2.0 is a web application designed to analyze high-throughput datasets, including but not limited to microarray and next-generation sequencing, using a pathway centric logic. In addition to well-established methods such as the Fisher's test and impact analysis, Pathway Processor 2.0 offers innovative methods that convert gene expression into pathway expression, leading to the identification of differentially regulated pathways in a dataset of choice. Pathway Processor 2.0 is available as a web service at http://compbiotoolbox.fmach.it/pathwayProcessor/. Sample datasets to test the functionality can be used directly from the application. duccio.cavalieri@fmach.it Supplementary data are available at Bioinformatics online.

Space Station Water Processor Process Pump

Science.gov (United States)

Parker, David

1995-01-01

This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

Performance evaluation of the HEP, ELXSI and CRAY X-MP parallel processors on hydrocode test problems

International Nuclear Information System (INIS)

Liebrock, L.M.; McGrath, J.F.; Hicks, D.L.

1986-01-01

Parallel programming promises improved processing speeds for hydrocodes, magnetohydrocodes, multiphase flow codes, thermal-hydraulics codes, wavecodes and other continuum dynamics codes. This paper presents the results of some investigations of parallel algorithms on three parallel processors: the CRAY X-MP, ELXSI and the HEP computers. Introduction and Background: We report the results of investigations of parallel algorithms for computational continuum dynamics. These programs (hydrocodes, wavecodes, etc.) produce simulations of the solutions to problems arising in the motion of continua: solid dynamics, liquid dynamics, gas dynamics, plasma dynamics, multiphase flow dynamics, thermal-hydraulic dynamics and multimaterial flow dynamics. This report restricts its scope to one-dimensional algorithms such as the von Neumann-Richtmyer (1950) scheme

Canadian conventional gas at a crossroads : a Ziff Energy white paper

International Nuclear Information System (INIS)

Ziff, P.

2010-01-01

The current low price of natural gas may have a significant and lasting impact on Canada's natural gas industry. This paper discussed the future of Canada's conventional gas industry and presented recommendations for ensuring a competitive and successful industry. Canada's oil and gas producers are increasingly shifting drilling activity towards oil production. The ratio of proven gas reserves to current production is now less than 8 years. As the conventional gas drilling reserve base shrinks, investment levels will also decline. Gas production in the Western Canadian Sedimentary Basin (WCSB) is expected to decline a further 15 per cent by 2020. The strong Canadian dollar has resulted in extensive monetary losses to Canadian gas producers. Service costs to the industry are also high. Recommendations included increased government involvement, new royalty rates, investment in unconventional gas, and regulatory reviews, and low gas production costs. Industry approaches will require involvement from operators, service companies, mid-stream processors, and transporters. 15 figs.

Modcomp MAX IV System Processors reference guide

Energy Technology Data Exchange (ETDEWEB)

Cummings, J.

1990-10-01

A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

A pre- and post-processor for the ICOOL muon transport code

International Nuclear Information System (INIS)

Fawley, W.M.

2001-01-01

ICOOL[1] is a Fortran77 macroparticle transport code widely used by researchers to study the front end of a neutrino factory/muon collider[2]. In part due to the desire that ICOOL be usable over multiple computer platforms and operating systems, the code uses simple text files for input/output services. This choice together with user-driven requests for greater and greater choice of lattice element type and configuration has led to ICOOL input decks becoming rather difficult to compose and modify easily. Moreover, the lack of a standard graphical post-processor has prevented many ICOOL users from extracting all but the most simple results from the output files. Here I present two attempts to improve this situation: First, a simple but quite general graphical pre-processor (NIME) written in the Tcl/TK[3] to permit users to write and maintain ASCII-formatted input files by use of simple macro definitions and expansions. Second, an interactive post-processor written in Fortran90 and NCAR graphics, which allows users to define, extract, and then examine the behavior of various particle subsets. In this paper I show some examples of use of both the pre- and post-processor for a standard ICOOL run

Making the black box signal processor transparent explains the contradictions in x-ray spectroscopy

International Nuclear Information System (INIS)

Papp, T.; Maxwell, J.A.; Papp, A.T.

2008-01-01

Full text: There are significant differences in the experimental data needed in the analysis of x-ray spectra, and many of the results contradict basic conservation laws and simple arithmetic. We have identified that the main source of the unexplainable results is rooted in the signal processing electronics. We have developed a line of fully digital signal processors that have yielded improved resolution, line shape, tailing and pile up recognition. The signal processor is a time variant, non-paralyzable signal processor. The signal processor accounts for and registers all events, sorting them into two spectra, one spectrum for the desirable or accepted events, and one spectrum for the rejected events. Although the information on the rejected events is always necessary, we recently realized its additional benefits in high rate, (10 5 -10 6 cps) analytical measurements. Having all information available we were surprised to see how different conclusions and level of understandings are possible in detector characterization, detector efficiency, spectrum evaluation methodology, and that it explains many of the contradictions. We will demonstrate how the Coster-Kronig transition measurements often do not even comply with arithmetic, and why is it difficult to interpret the spectra with other processors. It will be presented that for different spectra in origin, like radioisotope measurements, x-ray fluorescence, and particle induced x-ray emission, the primary signal from the preamplifier is so different, that the signal processor is facing very different challenges, and different metrological approaches are necessary in data processing. This data processing methodology cannot be established on the partial and fractional information offered by other approaches. However, the maximum information utilization approach offered by our processor's rejected spectrum supplements the accepted spectrum to allow the development of straight forward and accurate metrology. All the

Tinuso: A processor architecture for a multi-core hardware simulation platform

DEFF Research Database (Denmark)

Schleuniger, Pascal; Karlsson, Sven

2010-01-01

Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

Directory of Open Access Journals (Sweden)

R. Maheswari

2012-04-01

Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

Bounds on achievable accuracy in analog optical linear-algebra processors

Science.gov (United States)

Batsell, Stephen G.; Walkup, John F.; Krile, Thomas F.

1990-07-01

Upper arid lower bounds on the number of bits of accuracy achievable are determined by applying a seconth-ortler statistical model to the linear algebra processor. The use of bounds was found necessary due to the strong signal-dependence of the noise at the output of the optical linear algebra processor (OLAP). 1 1. ACCURACY BOUNDS One of the limiting factors in applying OLAPs to real world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication ard addition operations spatial variations across arrays and crosstalk. We have previously examined these noise sources and determined a general model for the output noise mean and variance. The model demonstrates a strony signaldependency in the noise at the output of the processor which has been confirmed by our experiments. 1 We define accuracy similar to its definition for an analog signal input to an analog-to-digital (ND) converter. The number of bits of accuracy achievable is related to the log (base 2) of the number of separable levels at the P/D converter output. The number of separable levels is fouri by dividing the dynamic range by m times the standard deviation of the signal a. 2 Here m determines the error rate in the P/D conversion. The dynamic range can be expressed as the

Parallel Processor for 3D Recovery from Optical Flow

Directory of Open Access Journals (Sweden)

Jose Hugo Barron-Zambrano

2009-01-01

Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

Cassava processors' awareness of occupational and environmental ...

African Journals Online (AJOL)

A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

The application of charge-coupled device processors in automatic-control systems

Science.gov (United States)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

Very wide register : an asymmetric register file organization for low power embedded processors.

NARCIS (Netherlands)

Raghavan, P.; Lambrechts, A.; Jayapala, M.; Catthoor, F.; Verkest, D.T.M.L.; Corporaal, H.

2007-01-01

In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Science.gov (United States)

2010-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2010-01-01 2010-01-01 false Processors and processing of all classes of certified...

Homogeneity corrections in the Anger camera with micro-Z processor

International Nuclear Information System (INIS)

Knoop, B.; Jordan, K.

1979-01-01

Series of measurements largely covering the area of clinical use of the Anger camera were carried out to investigate the mode of action of inhomogeneity correction by the micro-Z processor. The variation of boundary conditions of measurements when measuring in patients is simulated as closely as possible by selecting suitable measuring arrangements. The measured results confirm both the concepts outlined above on the causes of inhomogeneity of the Anger camera and the suitability for inhomogeneity correction under clinical conditions of the methods applied in the micro-Z processor. (orig./HP) [de

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

Science.gov (United States)

Downie, John D.

1990-01-01

A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.

21 CFR 864.3875 - Automated tissue processor.

Science.gov (United States)

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automated tissue processor. 864.3875 Section 864.3875 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES HEMATOLOGY AND PATHOLOGY DEVICES Pathology Instrumentation and Accessories § 864.3875...

Interleaved Subtask Scheduling on Multi Processor SOC

NARCIS (Netherlands)

Zhe, M.

2006-01-01

The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

Operation of the upgraded ATLAS Central Trigger Processor during the LHC Run 2

DEFF Research Database (Denmark)

Bertelsen, H.; Montoya, G. Carrillo; Deviveiros, P. O.

2016-01-01

The ATLAS Central Trigger Processor (CTP) is responsible for forming the Level-1 trigger decision based on the information from the calorimeter and muon trigger processors. In order to cope with the increase of luminosity and physics cross-sections in Run 2, several components of this system have...

The fast tracker processor for hadron collider triggers

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

2001-01-01

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

Energy Technology Data Exchange (ETDEWEB)

Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

International Nuclear Information System (INIS)

Barhen, Jacob; Kerekes, Ryan A.; St Charles, Jesse Lee; Buckner, Mark A.

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

Discovery of new nanomolar inhibitors of GPa: Extension of 2-oxo-1,2-dihydropyridinyl-3-yl amide-based GPa inhibitors.

Science.gov (United States)

Loughlin, Wendy A; Jenkins, Ian D; Karis, N David; Healy, Peter C

2017-02-15

Glycogen Phosphorylase (GP) is a functionally active dimeric enzyme, which is a target for inhibition of the conversion of glycogen to glucose-1-phosphate. In this study we report the design and synthesis of 14 new pyridone derivatives, and seek to extend the SAR analysis of these compounds. The SAR revealed the minor influence of the amide group, importance of the pyridone ring both spatially around the pyridine ring and for possible π-stacking, and confirmed a preference for inclusion of 3,4-dichlorobenzyl moieties, as bookends to the pyridone scaffold. Upon exploring a dimer strategy as part of the SAR analysis, the first extended 2-oxo-dihydropyridinyl-3-yl amide nanomolar based inhibitors of GPa (IC 50  = 230 and 260 nM) were identified. Copyright © 2017 Elsevier Masson SAS. All rights reserved.

Differential role of gpaB and sidA gene expressions in relation to virulence in Aspergillus species from patients with invasive aspergillosis.

Science.gov (United States)

Ghods, Nayereh; Falahati, Mehraban; Roudbary, Maryam; Farahyar, Shirin; Shamaei, Masoud; Pourabdollah, Mahin; Seif, Farhad

2018-02-03

The virulence genes in invasive aspergillosis (IA) have not been analyzed adequately. The present study was designed to evaluate the expression of gpaB and sidA genes, which are important virulence genes in Aspergillus spp. from bronchoalveolar lavage (BAL) samples. Direct examination and culture on Czapek Agar and Sabouraud Dextrose Agar media were performed for 600 BAL specimens isolated from patients with possible aspergillosis. A Galactomannan ELISA assay was also carried out. The expression levels of the gpaB and sidA genes in isolates were analyzed using quantitative real-time PCR (qRT-PCR). We identified 2 species, including Aspergillus flavus (A. flavus) and Aspergillus fumigatus (A. fumigatus) in 25 positive samples for invasive aspergillosis as validated using GM-ELISA. A. flavus is the main pathogen threatening transplant recipients and cancer patients worldwide. In this study, A. flavus had low levels of the gpaB gene expression compared to A. fumigatus (p=0.006). The highest sidA expression was detected in transplant recipients (p=0.05). There was no significant correlation between sidA expression and underlying disease (p=0.15). The sidA and gpaB gene expression patterns may provide evidence that these virulence genes play important roles in the pathogenicity of Aspergillus isolates; however, there are several regulatory genes responsible for the unexpressed sidA and gpaB genes in the isolates. Copyright © 2018 Sociedade Brasileira de Microbiologia. Published by Elsevier Editora Ltda. All rights reserved.

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Directory of Open Access Journals (Sweden)

Hiroki Iwaizumi

2013-01-01

Full Text Available A processor design for singular value decomposition (SVD and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs and arithmetic instructions specialized in complex matrix operations.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Scalable architecture for a room temperature solid-state quantum information processor.

Science.gov (United States)

Yao, N Y; Jiang, L; Gorshkov, A V; Maurer, P C; Giedke, G; Cirac, J I; Lukin, M D

2012-04-24

The realization of a scalable quantum information processor has emerged over the past decade as one of the central challenges at the interface of fundamental science and engineering. Here we propose and analyse an architecture for a scalable, solid-state quantum information processor capable of operating at room temperature. Our approach is based on recent experimental advances involving nitrogen-vacancy colour centres in diamond. In particular, we demonstrate that the multiple challenges associated with operation at ambient temperature, individual addressing at the nanoscale, strong qubit coupling, robustness against disorder and low decoherence rates can be simultaneously achieved under realistic, experimentally relevant conditions. The architecture uses a novel approach to quantum information transfer and includes a hierarchy of control at successive length scales. Moreover, it alleviates the stringent constraints currently limiting the realization of scalable quantum processors and will provide fundamental insights into the physics of non-equilibrium many-body quantum systems.

Electricity in lieu of nautral gas and oil for industrial thermal energy: a preliminary survey

Energy Technology Data Exchange (ETDEWEB)

Tallackson, J. R.

1979-02-01

In 1974, industrial processors accounted for nearly 50% of the nation's natural gas consumption and nearly 20% of its consumption of petroleum. This report is a preliminary assessment of the potential capability of the process industries to substitute utility-generated electricity for these scarce fuels. It is tacitly assumed that virtually all public utilities will soon be relying on coal or nuclear fission for primary energy. It was concluded that the existing technology will permit substitution of electricity for approximately 75% of the natural gas and petroleum now being consumed by industrial processors, which is equivalent to an annual usage of 800 million barrels of oil and 9 trillion cubic feet of gas at 1974 levels. Process steam generation, used throughout industry and representing 40% of its energy usage, offers the best near-term potential for conversion to electricity. Electric boilers and energy costs for steam are briefly discussed. Electrically driven heat pumps are considered as a possible method to save additional low-grade energy. Electrical reheating at high temperatures in the primary metals sector will be an effective way to conserve gas and oil. A wholesale shift by industry to electricity to replace gas and oil will produce impacts on the public utilities and, perhaps, those of a more general socio-economic nature. The principal bar to large-scale electrical substitution is economics, not technology. 174 references.

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

Science.gov (United States)

Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

2008-04-01

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

'Iconic' tracking algorithms for high energy physics using the TRAX-I massively parallel processor

International Nuclear Information System (INIS)

Vesztergombi, G.

1989-01-01

TRAX-I, a cost-effective parallel microcomputer, applying associative string processor (ASP) architecture with 16 K parallel processing elements, is being built by Aspex Microsystems Ltd. (UK). When applied to the tracking problem of very complex events with several hundred tracks, the large number of processors allows one to dedicate one or more processors to each wire (in MWPC), each pixel (in digitized images from streamer chambers or other visual detectors), or each pad (in TPC) to perform very efficient pattern recognition. Some linear tracking algorithms based on this ''ionic'' representation are presented. (orig.)

'Iconic' tracking algorithms for high energy physics using the TRAX-I massively parallel processor

International Nuclear Information System (INIS)

Vestergombi, G.

1989-11-01

TRAX-I, a cost-effective parallel microcomputer, applying Associative String Processor (ASP) architecture with 16 K parallel processing elements, is being built by Aspex Microsystems Ltd. (UK). When applied to the tracking problem of very complex events with several hundred tracks, the large number of processors allows one to dedicate one or more processors to each wire (in MWPC), each pixel (in digitized images from streamer chambers or other visual detectors), or each pad (in TPC) to perform very efficient pattern recognition. Some linear tracking algorithms based on this 'iconic' representation are presented. (orig.)

Noise limitations in optical linear algebra processors.

Science.gov (United States)

Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

1990-05-10

A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

Sojourn time asymptotics in processor-sharing queues

NARCIS (Netherlands)

Borst, S.C.; Núñez Queija, R.; Zwart, B.

2006-01-01

Over the past few decades, the Processor-Sharing (PS) discipline has attracted a great deal of attention in the queueing literature. While the PS paradigm emerged in the sixties as an idealization of round-robin scheduling in time-shared computer systems, it has recently captured renewed interest as

A Real-Time Sound Field Rendering Processor

Directory of Open Access Journals (Sweden)

Tan Yiyu

2017-12-01

Full Text Available Real-time sound field renderings are computationally intensive and memory-intensive. Traditional rendering systems based on computer simulations suffer from memory bandwidth and arithmetic units. The computation is time-consuming, and the sample rate of the output sound is low because of the long computation time at each time step. In this work, a processor with a hybrid architecture is proposed to speed up computation and improve the sample rate of the output sound, and an interface is developed for system scalability through simply cascading many chips to enlarge the simulated area. To render a three-minute Beethoven wave sound in a small shoe-box room with dimensions of 1.28 m × 1.28 m × 0.64 m, the field programming gate array (FPGA-based prototype machine with the proposed architecture carries out the sound rendering at run-time while the software simulation with the OpenMP parallelization takes about 12.70 min on a personal computer (PC with 32 GB random access memory (RAM and an Intel i7-6800K six-core processor running at 3.4 GHz. The throughput in the software simulation is about 194 M grids/s while it is 51.2 G grids/s in the prototype machine even if the clock frequency of the prototype machine is much lower than that of the PC. The rendering processor with a processing element (PE and interfaces consumes about 238,515 gates after fabricated by the 0.18 µm processing technology from the ROHM semiconductor Co., Ltd. (Kyoto Japan, and the power consumption is about 143.8 mW.

A Time-Composable Operating System for the Patmos Processor

DEFF Research Database (Denmark)

Ziccardi, Marco; Schoeberl, Martin; Vardanega, Tullio

2015-01-01

-composable operating system, on top of a time-composable processor, facilitates incremental development, which is highly desirable for industry. This paper makes a twofold contribution. First, we present enhancements to the Patmos processor to allow achieving time composability at the operating system level. Second......, we extend an existing time-composable operating system, TiCOS, to make best use of advanced Patmos hardware features in the pursuit of time composability.......In the last couple of decades we have witnessed a steady growth in the complexity and widespread of real-time systems. In order to master the rising complexity in the timing behaviour of those systems, rightful attention has been given to the development of time-predictable computer architectures...

A Geometric Algebra Co-Processor for Color Edge Detection

Directory of Open Access Journals (Sweden)

Biswajit Mishra

2015-01-01

Full Text Available This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA co-processor implemented on an Application Specific Integrated Circuit (ASIC. GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

The Influence of the Silicon Component in the Paste for Processor Cooling

Directory of Open Access Journals (Sweden)

Antun Koren

2003-12-01

Full Text Available The development of computer coolers foreseen for the processors keeps step with the processors for PC platform. There are still working and development areas where one could find new technologies and the kinds of the alternative cooling which give better results that the existing classical methods. There are several kinds of alternative cooling, from cooling with the mixture of water and methanol to the usage of freon and liquid nitrogen as the cooling media. The purpose of this work is to point at some new alternative cooling methods and to compare them with the classical ones as well as to stress the problems in classical - mechanically treated cooler and additives of chemically prepared pastes for better heat conductivity from the core surface of the processor.

Supertracker: A Programmable Parallel Pipeline Arithmetic Processor For Auto-Cueing Target Processing

Science.gov (United States)

Mack, Harold; Reddi, S. S.

1980-04-01

Supertracker represents a programmable parallel pipeline computer architecture that has been designed to meet the real time image processing requirements of auto-cueing target data processing. The prototype bread-board currently under development will be designed to perform input video preprocessing and processing for 525-line and 875-line TV formats FLIR video, automatic display gain and contrast control, and automatic target cueing, classification, and tracking. The video preprocessor is capable of performing operations full frames of video data in real time, e.g., frame integration, storage, 3 x 3 convolution, and neighborhood processing. The processor architecture is being implemented using bit-slice microprogrammable arithmetic processors, operating in parallel. Each processor is capable of up to 20 million operations per second. Multiple frame memories are used for additional flexibility.

The associative memory system for the FTK processor at ATLAS

CERN Document Server

Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

2014-01-01

In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

Low-Latency Embedded Vision Processor (LLEVS)

Science.gov (United States)

2016-03-01

algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system

50 CFR 648.6 - Dealer/processor permits.

Science.gov (United States)

2010-10-01

... of incorporation if the business is a corporation, and a copy of the partnership agreement and the names and addresses of all partners, if the business is a partnership, name of at-sea processor vessel... the fishing year to an applicant, unless the applicant fails to submit a completed application. An...

Event analysis using a massively parallel processor

International Nuclear Information System (INIS)

Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.

1990-01-01

This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable

Fast Parallel Computation of Polynomials Using Few Processors

DEFF Research Database (Denmark)

Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.

1983-01-01

It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

Huffman-based code compression techniques for embedded processors

KAUST Repository

Bonny, Mohamed Talal; Henkel, Jö rg

2010-01-01

% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.

Academic Self-Efficacy, Emotional Intelligence, GPA and Academic Procrastination in Higher Education

Directory of Open Access Journals (Sweden)

Meirav Hen

2014-05-01

Full Text Available Academic procrastination has been seen as an impediment to students' academic success because it decreases the quality and quantity of learning while increasing the severity of negative outcomes in students’ lives. Research findings suggest that academic procrastination is closely related to motivation variables such as self-efficacy and self-regulated learning, and with higher levels of anxiety, stress, and illness. Emotional Intelligence is the ability to assess, regulate, and utilize emotions. It has been found to be associated with academic self-efficacy and a variety of better outcomes, including academic performance. The purpose of the present study was to explore and provide an initial understanding to the relationships between emotional intelligence, academic procrastination and GPA, as mediated by academic selfefficacy. A convenience sampling of 287 college students was collected. Structural equation modeling analysis using AMOS was conducted to examine the mediation role of academic selfefficacy between emotional intelligence, procrastination and GPA. Findings indicated that Emotional intelligence has a negative indirect effect on academic procrastination and a positive indirect effect on academic performance. Further research is needed to explore the effect of emotional intelligence on academic procrastination and performance, and to further understand its implications for academic settings.

Efficacy of Code Optimization on Cache-Based Processors

Science.gov (United States)

VanderWijngaart, Rob F.; Saphir, William C.; Chancellor, Marisa K. (Technical Monitor)

1997-01-01

In this paper a number of techniques for improving the cache performance of a representative piece of numerical software is presented. Target machines are popular processors from several vendors: MIPS R5000 (SGI Indy), MIPS R8000 (SGI PowerChallenge), MIPS R10000 (SGI Origin), DEC Alpha EV4 + EV5 (Cray T3D & T3E), IBM RS6000 (SP Wide-node), Intel PentiumPro (Ames' Whitney), Sun UltraSparc (NERSC's NOW). The optimizations all attempt to increase the locality of memory accesses. But they meet with rather varied and often counterintuitive success on the different computing platforms. We conclude that it may be genuinely impossible to obtain portable performance on the current generation of cache-based machines. At the least, it appears that the performance of modern commodity processors cannot be described with parameters defining the cache alone.

From TEMPO+ to OPUS 2: what can music tests tell us about processor upgrades?

Science.gov (United States)

van Besouw, R M; Grasmeder, M L

2011-08-01

Tests for quantifying the music perception abilities of cochlear implant users are currently being developed and trialled at the South of England Cochlear Implant Centre. In addition to measures of speech perception, tests of rhythm, and pitch have been administered to MED-EL C40+ implant users before and after upgrading from the TEMPO+ processor with continuous interleaved sampling strategy to the OPUS 2 processor with fine structure processing strategy, with the aims of comparing device performance and evaluating the potential of music perception tests for informing processor upgrades and tuning. Eight experienced adult C40+ implant recipients performed tests of rhythm and pitch discrimination using the TEMPO+ processor and, after a minimum of 6 weeks acclimatization, using the OPUS 2 processor. Stimuli included piano and sine tones in two note ranges for the pitch tasks, and drum beats for the rhythm task. Rhythm, pitch, and speech perception scores were comparable for both processors. An effect of note range was observed (z = -2.52, p = 0.008 (two-tailed), r = -0.63), which indicated that the higher range of notes used for the pitch tasks was easier for participants than the lower range. Measures of pitch discrimination in different frequency ranges further informed changes made to one participant's map, resulting in improved pitch discrimination and speech perception scores. The outcomes of this study demonstrate that music perception tests can provide important additional measures for tuning cochlear implant parameters and assessing the impact of changes to device type and processing strategy.

The hardware implementation of the CERN SPS ultrafast feedback processor demonstrator

CERN Document Server

Dusakto, J E; Fox, J D; Olsen, J; Rivetta, C H; Höfle, W

2013-01-01

An ultrafast 4GSa/s transverse feedback processor has been developed for proof-of-concept studies of feedback control of e-cloud driven and transverse mode coupled intra-bunch instabilities in the CERN SPS. This system consists of a high-speed ADC on the front end and equally fast DAC on the back end. All control and signal processing is implemented in FPGA logic. This system is capable of taking up to 16 sample slices across a single SPS bunch and processing each slice individually within a reconfigurable signal processor. This demonstrator system is a rapidly developed prototype, consisting of both commercial and custom-design components. It can stabilize the motion of a single particle bunch using closed loop feedback. The system can also run open loop as a high-speed arbitrary waveform generator and contains diagnostic features including a special ADC snapshot capture memory. This paper describes the overall system, the feedback processor and focuses on the hardware architecture, design ...

The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Silverstein, S

2010-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Silverstein, S; The ATLAS collaboration

2009-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

Density-driven structural transformations in network forming glasses: a high-pressure neutron diffraction study of GeO2 glass up to 17.5 GPa

International Nuclear Information System (INIS)

Salmon, Philip S; Drewitt, James W E; Whittaker, Dean A J; Zeidler, Anita; Wezka, Kamil; Bull, Craig L; Tucker, Matthew G; Wilding, Martin C; Guthrie, Malcolm; Marrocchelli, Dario

2012-01-01

The structure of GeO 2 glass was investigated at pressures up to 17.5(5) GPa using in situ time-of-flight neutron diffraction with a Paris-Edinburgh press employing sintered diamond anvils. A new methodology and data correction procedure were developed, enabling a reliable measurement of structure factors that are largely free from diamond Bragg peaks. Calibration curves, which are important for neutron diffraction work on disordered materials, were constructed for pressure as a function of applied load for both single and double toroid anvil geometries. The diffraction data are compared to new molecular-dynamics simulations made using transferrable interaction potentials that include dipole-polarization effects. The results, when taken together with those from other experimental methods, are consistent with four densification mechanisms. The first, at pressures up to ≃ 5 GPa, is associated with a reorganization of GeO 4 units. The second, extending over the range from ≃ 5 to 10 GPa, corresponds to a regime where GeO 4 units are replaced predominantly by GeO 5 units. In the third, as the pressure increases beyond ∼10 GPa, appreciable concentrations of GeO 6 units begin to form and there is a decrease in the rate of change of the intermediate-range order as measured by the pressure dependence of the position of the first sharp diffraction peak. In the fourth, at about 30 GPa, the transformation to a predominantly octahedral glass is achieved and further densification proceeds via compression of the Ge-O bonds. The observed changes in the measured diffraction patterns for GeO 2 occur at similar dimensionless number densities to those found for SiO 2 , indicating similar densification mechanisms for both glasses. This implies a regime from about 15 to 24 GPa where SiO 4 units are replaced predominantly by SiO 5 units, and a regime beyond ∼24 GPa where appreciable concentrations of SiO 6 units begin to form.

Robust zero resistance in a superconducting high-entropy alloy at pressures up to 190 GPa

Science.gov (United States)

Guo, Jing; Wang, Honghong; von Rohr, Fabian; Wang, Zhe; Cai, Shu; Zhou, Yazhou; Yang, Ke; Li, Aiguo; Jiang, Sheng; Wu, Qi; Cava, Robert J.; Sun, Liling

2017-12-01

We report the observation of extraordinarily robust zero-resistance superconductivity in the pressurized (TaNb)0.67(HfZrTi)0.33 high-entropy alloy--a material with a body-centered-cubic crystal structure made from five randomly distributed transition-metal elements. The transition to superconductivity (TC) increases from an initial temperature of 7.7 K at ambient pressure to 10 K at ˜60 GPa, and then slowly decreases to 9 K by 190.6 GPa, a pressure that falls within that of the outer core of the earth. We infer that the continuous existence of the zero-resistance superconductivity from 1 atm up to such a high pressure requires a special combination of electronic and mechanical characteristics. This high-entropy alloy superconductor thus may have a bright future for applications under extreme conditions, and also poses a challenge for understanding the underlying quantum physics.

Fast parallel computation of polynomials using few processors

DEFF Research Database (Denmark)

Valiant, Leslie; Skyum, Sven

1981-01-01

It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

Study of an analog/logic processor for the design of an auto patch hybrid computer

International Nuclear Information System (INIS)

Koched, Hassen

1976-01-01

This paper presents the experimental study of an analog multiprocessor designed at SES/CEN-Saclay. An application of such a device as a basic component of an auto-patch hybrid computer is presented. First, the description of the processor, and a presentation of the theoretical concepts which governed the design of the processor are given. Experiments on an hybrid computer are then presented. Finally, different systems of automatic patching are presented, and conveniently modified, for the use of such a processor. (author) [fr

SAPIENS: Spreading Activation Processor for Information Encoded in Network Structures. Technical Report No. 296.

Science.gov (United States)

Ortony, Andrew; Radin, Dean I.

The product of researchers' efforts to develop a computer processor which distinguishes between relevant and irrelevant information in the database, Spreading Activation Processor for Information Encoded in Network Structures (SAPIENS) exhibits (1) context sensitivity, (2) efficiency, (3) decreasing activation over time, (4) summation of…

Feasibility analysis of real-time physical modeling using WaveCore processor technology on FPGA

NARCIS (Netherlands)

Verstraelen, Martinus Johannes Wilhelmina; Pfeifle, Florian; Bader, Rolf

2015-01-01

WaveCore is a scalable many-core processor technology. This technology is specifically developed and optimized for real-time acoustical modeling applications. The programmable WaveCore soft-core processor is silicon-technology independent and hence can be targeted to ASIC or FPGA technologies. The

Standardized Testing Placement and High School GPA as Predictors of Success in Remedial Math

Science.gov (United States)

Burrow, Susan C.

2013-01-01

The purpose of this quantitative study was to determine if a relationship existed between success in elementary algebra and a set of predictor variables including COMPASS score and high school GPA. Relationships for intermediate algebra and college credit accumulation over three semesters were also examined with COMPASS score and high school GPA…

Assessment of directionality performances: comparison between Freedom and CP810 sound processors.

Science.gov (United States)

Razza, Sergio; Albanese, Greta; Ermoli, Lucilla; Zaccone, Monica; Cristofari, Eliana

2013-10-01

To compare speech recognition in noise for the Nucleus Freedom and CP810 sound processors using different directional settings among those available in the SmartSound portfolio. Single-subject, repeated measures study. Tertiary care referral center. Thirty-one monoaurally and binaurally implanted subjects (24 children and 7 adults) were enrolled. They were all experienced Nucleus Freedom sound processor users and achieved a 100% open set word recognition score in quiet listening conditions. Each patient was fitted with the Freedom and the CP810 processor. The program setting incorporated Adaptive Dynamic Range Optimization (ADRO) and adopted the directional algorithm BEAM (both devices) and ZOOM (only on CP810). Speech reception threshold (SRT) was assessed in a free-field layout, with disyllabic word list and interfering multilevel babble noise in the 3 different pre-processing configurations. On average, CP810 improved significantly patients' SRTs as compared to Freedom SP after 1 hour of use. Instead, no significant difference was observed in patients' SRT between the BEAM and the ZOOM algorithm fitted in the CP810 processor. The results suggest that hardware developments achieved in the design of CP810 allow an immediate and relevant directional advantage as compared to the previous-generation Freedom device.

In-Network Adaptation of Video Streams Using Network Processors

Directory of Open Access Journals (Sweden)

Mohammad Shorfuzzaman

2009-01-01

problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

Optical chirp z-transform processor with a simplified architecture.

Science.gov (United States)

Ngo, Nam Quoc

2014-12-29

Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

Computations on the massively parallel processor at the Goddard Space Flight Center

Science.gov (United States)

Strong, James P.

1991-01-01

Described are four significant algorithms implemented on the massively parallel processor (MPP) at the Goddard Space Flight Center. Two are in the area of image analysis. Of the other two, one is a mathematical simulation experiment and the other deals with the efficient transfer of data between distantly separated processors in the MPP array. The first algorithm presented is the automatic determination of elevations from stereo pairs. The second algorithm solves mathematical logistic equations capable of producing both ordered and chaotic (or random) solutions. This work can potentially lead to the simulation of artificial life processes. The third algorithm is the automatic segmentation of images into reasonable regions based on some similarity criterion, while the fourth is an implementation of a bitonic sort of data which significantly overcomes the nearest neighbor interconnection constraints on the MPP for transferring data between distant processors.

Power estimation on functional level for programmable processors

Directory of Open Access Journals (Sweden)

M. Schneider

2004-01-01

Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

Power estimation on functional level for programmable processors

Science.gov (United States)

Schneider, M.; Blume, H.; Noll, T. G.

2004-05-01

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input

Study on the management of the Boohung X-Dol 90 developer and fixing solution for automatic X-ray film processor

International Nuclear Information System (INIS)

Hyan, Yong Sil; Kim, Heung Tae; Kwon, Dal Gwan; Choi, Myung Joon; Cheung, Hwan

1986-01-01

Recently, Demands of Automatic X-ray film Processors are increasing more and more at University Hospitals and general Hospitals and Private clinics, but various troubles because of incorrect control were found out. Authors have researched to find out the function and Activity of Automatic X-ray film processor for 2 weeks Kodak RPX-OMAT Processor and Sakura GX3000 Processor and Doosan parka 2000 Processor and results obtained were as follows: 1. Automatic X-ray film processor have an advantage to conduct the rapid treatment of X-ray film processing but incorrect handling of developing and fixing agents were brought about a great change in Contrast and Optical density of X-ray film pictures. 2. About 300 X-ray film could be finished by same developing and fixing solution without exchanging any other solutions in each Automatic X-ray film processor

Reconfigurable VLIW Processor for Software Defined Radio, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

Vector and parallel processors in computational science

International Nuclear Information System (INIS)

Duff, I.S.; Reid, J.K.

1985-01-01

This book presents the papers given at a conference which reviewed the new developments in parallel and vector processing. Topics considered at the conference included hardware (array processors, supercomputers), programming languages, software aids, numerical methods (e.g., Monte Carlo algorithms, iterative methods, finite elements, optimization), and applications (e.g., neutron transport theory, meteorology, image processing)

Dual Credit Enrollment and GPA by Ethnicity and Gender at Texas 2-Year Colleges

Science.gov (United States)

Young, Robert D., Jr.

2013-01-01

Purpose: The purpose of this investigation was to determine the extent to which differences were present in dual credit course enrollment. Specifically examined were whether differences were present in the first semester GPA and at the end of the first two semesters for students who enrolled in dual credit courses while in high school from…

The impact of reneging in processor sharing queues

NARCIS (Netherlands)

Gromoll, H.C.; Robert, Ph.; Zwart, B.; Bakker, R.F.

2006-01-01

We investigate an overloaded processor sharing queue with renewal arrivals and generally distributed service times. Impatient customers may abandon the queue, or renege, before completing service. The random time representing a customer’s patience has a general distribution and may be dependent on

Color sensor and neural processor on one chip

Science.gov (United States)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

Nested dissection on a mesh-connected processor array

International Nuclear Information System (INIS)

Worley, P.H.; Schreiber, R.

1986-01-01

The authors present a parallel implementation of Gaussian elimination without pivoting using the nested dissection ordering for solving Ax=b where A is an N x N symmetric positive definite matrix. If the graph of A is a √N x √N finite element mesh then a parallel complexity of O(√N) can be achieved for Gaussian elimination with the nested dissection ordering. The authors' implementation achieves this parallel complexity on a two dimensional MIMD processor array with N processors and nearest neighbors interconnections. Thus nested dissection is a near optimal algorithm for this problem on this interconnection topology. The parallel implementation on this architecture requires 158√N + O(log/sub 2/(√N)) parallel floating point multiplications. It is faster than a Kung-Leiserson systolic array for banded matrices for N≥961, and faster than a serial implementation for N as small as 9

Matrix preconditioning: a robust operation for optical linear algebra processors.

Science.gov (United States)

Ghosh, A; Paparao, P

1987-07-15

Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

Upgrade of the PreProcessor System for the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Khomich, A

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5\\,us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

Upgrade of the PreProcessor System for the ATLAS LVL1 Calorimeter Trigger

CERN Document Server

Khomich, A; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serializers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

Embedded SoPC Design with Nios II Processor and Verilog Examples

CERN Document Server

Chu, Pong P

2012-01-01

Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

Formulation of consumables management models: Mission planning processor payload interface definition

Science.gov (United States)

Torian, J. G.

1977-01-01

Consumables models required for the mission planning and scheduling function are formulated. The relation of the models to prelaunch, onboard, ground support, and postmission functions for the space transportation systems is established. Analytical models consisting of an orbiter planning processor with consumables data base is developed. A method of recognizing potential constraint violations in both the planning and flight operations functions, and a flight data file storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights is presented.

Experimental investigation of dynamic compression and spallation of Cerium at pressures up to 6 GPa

Science.gov (United States)

Zubareva, A. N.; Kolesnikov, S. A.; Utkin, A. V.

2014-05-01

In this study the experiments on one-dimensional dynamic compression of Cerium (Ce) samples to pressures of 0.5 to 6 GPa using various types of explosively driven generators were conducted. VISAR laser velocimeter was used to obtain Ce free surface velocity profiles. The isentropic compression wave was registered for γ-phase of Ce at pressures lower than 0.76 GPa that corresponds to γ-α phase transition pressure in Ce. Shock rarefaction waves were also registered in several experiments. Both observations were the result of the anomalous compressibility of γ-phase of Ce. On the basis of our experimental results the compression isentrope of Ce γ-phase was constructed. Its comparison with volumetric compression curves allowed to estimate the magnitude of shear stress at dynamic compression conditions for Ce. Spall strength measurements were also conducted for several samples. They showed a strong dependence of the spall strength of Ce on the strain rate.

Experimental investigation of dynamic compression and spallation of cerium at pressures up to 6 GPa

International Nuclear Information System (INIS)

Zubareva, A N; Kolesnikov, S A; Utkin, A V

2014-01-01

In this study the experiments on one-dimensional dynamic compression of Cerium (Ce) samples to pressures of 0.5 to 6 GPa using various types of explosively driven generators were conducted. VISAR laser velocimeter was used to obtain Ce free surface velocity profiles. The isentropic compression wave was registered for γ-phase of Ce at pressures lower than 0.76 GPa that corresponds to γ-α phase transition pressure in Ce. Shock rarefaction waves were also registered in several experiments. Both observations were the result of the anomalous compressibility of γ-phase of Ce. On the basis of our experimental results the compression isentrope of Ce γ-phase was constructed. Its comparison with volumetric compression curves allowed to estimate the magnitude of shear stress at dynamic compression conditions for Ce. Spall strength measurements were also conducted for several samples. They showed a strong dependence of the spall strength of Ce on the strain rate.

A fast inner product processor based on equal alignments

Energy Technology Data Exchange (ETDEWEB)

Smith, S.P.; Torng, H.C.

1985-11-01

Inner product computation is an important operation, invoked repeatedly in matrix multiplications. A high-speed inner product processor can be very useful (among many possible applications) in real-time signal processing. This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost. The inner product processor is implemented with a tree of carry-propagate or carry-save adders; this structure is obtained with the incorporation of three innovations in the conventional multiply/add tree: The leaf-multipliers are expanded into adder subtrees, thus achieving an O(log Nb) latency, where N denotes the number of elements in a vector and b the number of bits in each element. The partial products, to be summed in producing an inner product, are reordered according to their ''minimum alignments.'' This reordering brings approximately a 20% savings in hardware-including adders and data paths. The reduction in adder widths also yields savings in carry propagation time for carry-propagate adders. For trees implemented with carry-save adders, the partial product reordering also serves to truncate the carry propagation chain in the final propagation stage by 2 log b - 1 positions, thus significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.

A post-processor for the PEST code

International Nuclear Information System (INIS)

Priesche, S.; Manickam, J.; Johnson, J.L.

1992-01-01

A new post-processor has been developed for use with output from the PEST tokamak stability code. It allows us to use quantities calculated by PEST and take better advantage of the physical picture of the plasma instability which they can provide. This will improve comparison with experimentally measured quantities as well as facilitate understanding of theoretical studies

2009 Survey of Gulf of Mexico Dockside Seafood Processors

Data.gov (United States)

National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

Fuel processor integrated H{sub 2}S catalytic partial oxidation technology for sulfur removal in fuel cell power plants

Energy Technology Data Exchange (ETDEWEB)

Gardner, T.H.; Berry, D.A.; Lyons, K.D.; Beer, S.K.; Freed, A.D. [U.S. Department of Energy, Morgantown, WV (USA). National Energy Technology Laboratory

2002-12-01

H{sub 2}S catalytic partial oxidation technology with an activated carbon catalyst was found to be a promising method for the removal of hydrogen sulfide from fuel cell hydrocarbon feedstocks. Three different fuel cell feedstocks were considered for analysis: sour natural gas, sour effluent from a liquid middle distillate fuel processor and a Texaco O{sub 2}-blown coal-derived synthesis gas. The H{sub 2}S catalytic partial oxidation reaction, its integratability into fuel cell power plants with different hydrocarbon feedstocks and its salient features are discussed. Experimental results indicate that H{sub 2}S concentration can be removed down to the part-per-million level in these plants. Additionally, a power law rate expression was developed and reaction kinetics compared to prior literature. The activation energy for this reaction was determined to be 34.4 kJ/g mol with the reaction being first order in H{sub 2}S and 0.3 order in O{sub 2}. 18 refs., 14 figs., 3 tabs.