Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

Science.gov (United States)

Zargham, Meysam; Gulak, P Glenn

2015-04-01

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

CERN Document Server

Wang, T.

2017-01-01

The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

Electronically Tunable Fully Integrated Fractional-Order Resonator

KAUST Repository

Tsirimokou, Georgia

2017-03-20

A fully integrated implementation of a parallel fractional-order resonator which employs together a fractional order capacitor and a fractional-order inductor is proposed in this paper. The design utilizes current-controlled Operational Transconductance Amplifiers as building blocks, designed and fabricated in AMS 0:35m CMOS process, and based on a second-order approximation of a fractional-order differentiator/ integrator magnitude optimized in the range 10Hz–700Hz. An attractive benefit of the proposed scheme is its electronic tuning capability.

Electronically Tunable Fully Integrated Fractional-Order Resonator

KAUST Repository

Tsirimokou, Georgia; Psychalinos, Costas; Elwakil, Ahmed S.; Salama, Khaled N.

2017-01-01

A fully integrated implementation of a parallel fractional-order resonator which employs together a fractional order capacitor and a fractional-order inductor is proposed in this paper. The design utilizes current-controlled Operational Transconductance Amplifiers as building blocks, designed and fabricated in AMS 0:35m CMOS process, and based on a second-order approximation of a fractional-order differentiator/ integrator magnitude optimized in the range 10Hz–700Hz. An attractive benefit of the proposed scheme is its electronic tuning capability.

1.5V fully programmable CMOS Membership Function Generator Circuit with proportional DC-voltage control

Directory of Open Access Journals (Sweden)

C. Muñiz-Montero

2013-06-01

Full Text Available A Membership Function Generator Circuit (MFGC with bias supply of 1.5 Volts and independent DC-voltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal output waveforms. HSPICE simulation results of the proposed circuit using the parameters of a double-poly, three metal layers, 0.5 μm CMOS technology validate the functionality of the proposed architecture, which exhibits a maximum deviation of the linearity in the programmability of 7 %.

High-Voltage-Input Level Translator Using Standard CMOS

Science.gov (United States)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

CERN Document Server

Ghafar-Zadeh, Ebrahim

2010-01-01

The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

Science.gov (United States)

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

Science.gov (United States)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

International Nuclear Information System (INIS)

Obermann, Theresa

2017-06-01

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n + -implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e - to 3000 e - while the noise is 30 e - due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10 14 neutrons/cm 2 the performance suffers from the radiation damage leading to a signal of 1000 e - and a higher noise of 60 e - due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10 14 particles/cm 2 . Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10 14 particles/cm 2 ). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget

CMOS dot matrix microdisplay

Science.gov (United States)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

Science.gov (United States)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Nanometer CMOS ICs from basics to ASICs

CERN Document Server

J M Veendrick, Harry

2017-01-01

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

Directory of Open Access Journals (Sweden)

M. Jamal Deen

2013-08-01

Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Depleted CMOS pixels for LHC proton–proton experiments

International Nuclear Information System (INIS)

Wermes, N.

2016-01-01

While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

Science.gov (United States)

Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

Voltage-to-frequency converters CMOS design and implementation

CERN Document Server

Azcona Murillo, Cristina; Pueyo, Santiago Celma

2013-01-01

This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

CERN Document Server

Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

2012-01-01

CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Obermann, Theresa

2017-06-15

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n{sup +}-implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e{sup -} to 3000 e{sup -} while the noise is 30 e{sup -} due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10{sup 14} neutrons/cm{sup 2} the performance suffers from the radiation damage leading to a signal of 1000 e{sup -} and a higher noise of 60 e{sup -} due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10{sup 14} particles/cm{sup 2}. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10{sup 14} particles/cm{sup 2}). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

International Nuclear Information System (INIS)

Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan

2009-01-01

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm 2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

Energy Technology Data Exchange (ETDEWEB)

Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-01-15

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

Small Pixel Hybrid CMOS X-ray Detectors

Science.gov (United States)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

A CMOS transconductance-C filter technique for very high frequencies

NARCIS (Netherlands)

Nauta, Bram

1992-01-01

CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

Fully differential cross sections for heavy particle impact ionization

Energy Technology Data Exchange (ETDEWEB)

McGovern, M; Walters, H R J [Department of Applied Mathematics and Theoretical Physics, Queen' s University, Belfast BT7 1NN (United Kingdom); Assafrao, D; Mohallem, J R [Laboratorio de Atomos e Moleculas Especiais, Departamento de Fisica, ICEx, Universidade Federal de Minas Gerais, P.O Box 702, 30123-970 Belo Horizonte, MG (Brazil); Whelan, Colm T, E-mail: mmcgovern06@qub.ac.u [Department of Physics, Old Dominion University, Norfolk, VA 23529-0116 (United States)

2009-11-15

We describe a procedure for extracting fully differential ionization cross sections from an impact parameter coupled pseudostate treatment of the collision. Some examples from antiproton impact ionization of atomic Hydrogen are given.

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

Science.gov (United States)

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

Merits of CMOS/SIMOX technology for low-voltage SRAM macros

CERN Document Server

Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

1999-01-01

A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

Energy Technology Data Exchange (ETDEWEB)

Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

2010-12-15

A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

Wideband pulse amplifier with 8 GHz GBW product in a 0.35 μm CMOS technology for the integrated camera of the Cherenkov Telescope Array

International Nuclear Information System (INIS)

Gascon, D; Sanuy, A; Ribo, M; Delagnes, E; Glicenstein, J-F; Sieiro, X; Feinstein, F; Vorobiov, S; Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P

2010-01-01

A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35μm CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

Science.gov (United States)

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

International Nuclear Information System (INIS)

Li Shoucheng; Wang Xin'an; Lin Ke; Shen Jinpeng; Zhang Jinhai

2014-01-01

A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm 2 . Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of −13.5 dBm (semiconductor integrated circuits)

Backward stochastic differential equations from linear to fully nonlinear theory

CERN Document Server

Zhang, Jianfeng

2017-01-01

This book provides a systematic and accessible approach to stochastic differential equations, backward stochastic differential equations, and their connection with partial differential equations, as well as the recent development of the fully nonlinear theory, including nonlinear expectation, second order backward stochastic differential equations, and path dependent partial differential equations. Their main applications and numerical algorithms, as well as many exercises, are included. The book focuses on ideas and clarity, with most results having been solved from scratch and most theories being motivated from applications. It can be considered a starting point for junior researchers in the field, and can serve as a textbook for a two-semester graduate course in probability theory and stochastic analysis. It is also accessible for graduate students majoring in financial engineering.

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

OpenAIRE

Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

2011-01-01

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

A scalable neural chip with synaptic electronics using CMOS integrated memristors

International Nuclear Information System (INIS)

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-01-01

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

Science.gov (United States)

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Programmable differential capacitance-to-voltage converter for MEMS accelerometers

Science.gov (United States)

Royo, G.; Sánchez-Azqueta, C.; Gimeno, C.; Aldea, C.; Celma, S.

2017-05-01

Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.

Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback

DEFF Research Database (Denmark)

Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre

A fully differential rail-to-rail Operational Transconductance Amplifier (OTA) with improved DC-gain and reduced power consumption is proposed in this paper. By using the adaptive biasing circuit and two differential inputs, a low stand-by current can be obtained together with reduced power...... consumption. The DC-gain of the proposed OTA is improved by adding a partial feedback loop. A Common-Mode Feedback (CMFB) circuit is required for fully differential rail-to-rail operation. Simulations show that the OTA topology has a low stand-by power consumption of 96μW and a high FoM of 3.84 [(V...

A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 {mu}m CMOS process

Energy Technology Data Exchange (ETDEWEB)

Wang Jingchao; Zhang Chun; Wang Zhihua, E-mail: wangjc@gmail.co [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

2010-08-15

A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 {mu}m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm{sup 2} including pads. (semiconductor integrated circuits)

A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

International Nuclear Information System (INIS)

Wang Jingchao; Zhang Chun; Wang Zhihua

2010-01-01

A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm 2 including pads. (semiconductor integrated circuits)

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Directory of Open Access Journals (Sweden)

Fangming Deng

2014-05-01

Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Fully Digital Chaotic Differential Equation-based Systems And Methods

KAUST Repository

Radwan, Ahmed Gomaa Ahmed; Zidan, Mohammed A.; Salama, Khaled N.

2012-01-01

Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Fully Digital Chaotic Differential Equation-based Systems And Methods

KAUST Repository

Radwan, Ahmed Gomaa Ahmed

2012-09-06

Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

Science.gov (United States)

Rimoldi, M.

2017-12-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

Anelastic Models of Fully-Convective Stars: Differential Rotation, Meridional Circulation and Residual Entropy

Science.gov (United States)

Sainsbury-Martinez, Felix; Browning, Matthew; Miesch, Mark; Featherstone, Nicholas A.

2018-01-01

Low-Mass stars are typically fully convective, and as such their dynamics may differ significantly from sun-like stars. Here we present a series of 3D anelastic HD and MHD simulations of fully convective stars, designed to investigate how the meridional circulation, the differential rotation, and residual entropy are affected by both varying stellar parameters, such as the luminosity or the rotation rate, and by the presence of a magnetic field. We also investigate, more specifically, a theoretical model in which isorotation contours and residual entropy (σ‧ = σ ‑ σ(r)) are intrinsically linked via the thermal wind equation (as proposed in the Solar context by Balbus in 2009). We have selected our simulation parameters in such as way as to span the transition between Solar-like differential rotation (fast equator + slow poles) and ‘anti-Solar’ differential rotation (slow equator + fast poles), as characterised by the convective Rossby number and △Ω. We illustrate the transition from single-celled to multi-celled MC profiles, and from positive to negative latitudinal entropy gradients. We show that an extrapolation involving both TWB and the σ‧/Ω link provides a reasonable estimate for the interior profile of our fully convective stars. Finally, we also present a selection of MHD simulations which exhibit an almost unsuppressed differential rotation profile, with energy balances remaining dominated by kinetic components.

A BiCMOS Binary Hysteresis Chaos Generator

Science.gov (United States)

Ahmadi, S.; Newcomb, R. W.

A previous op-amp RC circuit which was proven to give chaotic signals is converted to a BiCMOS design more suitable to integrated circuit realization. The structure results from a degree two differential equation which includes binary hysteresis as its nonlinearity. The circuit is realized by differential (voltage to current) pairs feeding two capacitors, which carry the dynamics, with the key component being a (voltage to current) binary hysteresis circuit due to Linares.

Low-voltage CMOS operational amplifiers theory, design and implementation

CERN Document Server

Sakurai, Satoshi

1995-01-01

Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

Multi-target electrochemical biosensing enabled by integrated CMOS electronics

International Nuclear Information System (INIS)

Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

2011-01-01

An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

Energy Technology Data Exchange (ETDEWEB)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-11-15

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

International Nuclear Information System (INIS)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

2012-01-01

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

Renormalization-group improved fully differential cross sections for top pair production

International Nuclear Information System (INIS)

Broggio, A.; Papanastasiou, A.S.; Signer, A.; Zuerich Univ.

2014-07-01

We extend approximate next-to-next-to-leading order results for top-pair production to include the semi-leptonic decays of top quarks in the narrow-width approximation. The new hard-scattering kernels are implemented in a fully differential parton-level Monte Carlo that allows for the study of any IR-safe observable constructed from the momenta of the decay products of the top. Our best predictions are given by approximate NNLO corrections in the production matched to a fixed order calculation with NLO corrections in both the production and decay subprocesses. Being fully differential enables us to make comparisons between approximate results derived via different (PIM and 1PI) kinematics for arbitrary distributions. These comparisons reveal that the renormalization-group framework, from which the approximate results are derived, is rather robust in the sense that applying a realistic error estimate allows us to obtain a reliable prediction with a reduced theoretical error for generic observables and analysis cuts.

Simple BiCMOS CCCTA design and resistorless analog function realization.

Science.gov (United States)

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

Directory of Open Access Journals (Sweden)

Worapong Tangsrirat

2014-01-01

Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

Science.gov (United States)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

Characterization of a fully resonant, 1-MHz, 25-watt, DC/DC converter fabricated in a rad-hard BiCMOS/high-voltage process

International Nuclear Information System (INIS)

Titus, J.L.; Gehlhausen, M.A.; Desko, J.C. Jr.; Nguyen, T.T.; Roberts, D.J.; Shibib, M.A.; Hollenbach, K.E.

1995-01-01

This paper presents the characterization of a DC/DC converter prototype when its power integrated circuit (PIC) chip is exposed to total dose, dose rate, neutron, and heavy ion environments. This fully resonant, 1-MHZ, 25-Watt, DC/DC converter is composed of a brassboard, populated with input/output filters, isolation transformers, output rectifier, capacitors, resistors, and PIC chip, integrating the primary-side control circuitry, secondary-side control circuitry, power switch, gate-drive circuitry, and voltage references. The brassboard is built using commercial off-the-shelf components; and the PIC chip is fabricated using AT and T's rad-hard, bipolar complementary metal-oxide semiconductor (BiCMOS)/high-voltage process. The intent of this paper is to demonstrate that the PIC chip is fabricated with a radiation-hardened process and to demonstrate that various analog, digital, and power functions can be effectively integrated

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Science.gov (United States)

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology

NARCIS (Netherlands)

Radovanovic, S.; Annema, Anne J.; Nauta, Bram

2003-01-01

The influence of different geometries (layouts) and structures of high-speed photodiodes in fully standard 0.18 μm CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. Three photodiode structures are studied: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. The

High efficiency grating couplers based on shared process with CMOS MOSFETs

International Nuclear Information System (INIS)

Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

2013-01-01

Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

Science.gov (United States)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

Fully integrated CMOS pixel detector for high energy particles

International Nuclear Information System (INIS)

Vanstraelen, G.; Debusschere, I.; Claeys, C.; Declerck, G.

1989-01-01

A novel type of position and energy sensitive, monolithic pixel array with integrated readout electronics is proposed. Special features of the design are a reduction of the number of output channels and of the amount of output data, and the use of transistors on the high resistivity silicon. The number of output channels for the detector array is reduced by handling in parallel a number of pixels, chosen as a function of the time resolution required for the system, and by the use of an address decoder. A further reduction of data is achieved by reading out only those pixels which have been activated. The pixel detector circuit will be realized in a 3 μm p-well CMOS process, which is optimized for the full integration of readout electronics and detector diodes on high resistivity Si. A retrograde well is formed by means of a high energy implantation, followed by the appropriate temperature steps. The optimization of the well shape takes into account the high substrate bias applied during the detector operation. The design is largely based on the use of MOS transistors on the high resistivity silicon itself. These have proven to perform as well as transistors on standard doped substrate. The basic building elements as well as the design strategy of the integrated pixel detector are presented in detail. (orig.)

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

A fully integrated 16 channel digitally trimmed pulse shaping amplifier

International Nuclear Information System (INIS)

Hearn, W.E.; Wright, M.E.

1993-11-01

A fully integrated CMOS pulse shaping amplifier has been developed at LBL. All frequency dependent networks are included on the chip. Provision is made for tuning to compensate for process variations. The overall architecture and details of the circuitry are discussed. Test results are presented

A 0.18 μm CMOS LDO Regulator for an On-Chip Sensor Array Impedance Measurement System.

Science.gov (United States)

Pérez-Bailón, Jorge; Márquez, Alejandro; Calvo, Belén; Medrano, Nicolás

2018-05-02

This paper presents a fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator specifically designed to meet the stringent requirements of a battery-operated impedance spectrometry multichannel CMOS micro-instrument. The proposed LDO provides a regulated 1.8 V voltage from a 3.6 V to 1.94 V battery voltage over a −40 °C to 100 °C temperature range, with a compact topology (sensors.

Design and characterization of a fully differential MEMS accelerometer fabricated using MetalMUMPs technology.

Science.gov (United States)

Qu, Peng; Qu, Hongwei

2013-05-02

This paper presents a fully differential single-axis accelerometer fabricated using the MetalMUMPs process. The unique structural configuration and common-centriod wiring of the metal electrodes enables a fully differential sensing scheme with robust metal sensing structures. CoventorWare is used in structural and electrical design and simulation of the fully differential accelerometer. The MUMPs foundry fabrication process of the sensor allows for high yield, good process consistency and provides 20 μm structural thickness of the sensing element, which makes the capacitive sensing eligible. In device characterization, surface profile of the fabricated device is measured using a Veeco surface profilometer; and mean and gradient residual stress in the nickel structure are calculated as approximately 94.7 MPa and -5.27 MPa/μm, respectively. Dynamic characterization of the sensor is performed using a vibration shaker with a high-end commercial calibrating accelerometer as reference. The sensitivity of the sensor is measured as 0.52 mV/g prior to off-chip amplification. Temperature dependence of the sensing capacitance is also characterized. A -0.021fF/°C is observed. The findings in the presented work will provide useful information for design of sensors and actuators such as accelerometers, gyroscopes and electrothermal actuators that are to be fabricated using MetalMUMPs technology.

Matching fully differential NNLO calculations and parton showers

International Nuclear Information System (INIS)

Alioli, Simone; Bauer, Christian W.; Berggren, Calvin; Walsh, Jonathan R.; Zuberi, Saba

2013-11-01

We present a general method to match fully differential next-to-next-to-leading (NNLO) calculations to parton shower programs. We discuss in detail the perturbative accuracy criteria a complete NNLO+PS matching has to satisfy. Our method is based on consistently improving a given NNLO calculation with the leading-logarithmic (LL) resummation in a chosen jet resolution variable. The resulting NNLO+LL calculation is cast in the form of an event generator for physical events that can be directly interfaced with a parton shower routine, and we give an explicit construction of the input ''Monte Carlo cross sections'' satisfying all required criteria. We also show how other proposed approaches naturally arise as special cases in our method.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

Science.gov (United States)

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

A passive CMOS pixel sensor for the high luminosity LHC

Energy Technology Data Exchange (ETDEWEB)

Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

2016-07-01

The high luminosity upgrade for the Large Hadron Collider at CERN requires a new inner tracking detector for the ATLAS experiment. About 200 m{sup 2} of silicon detectors are needed demanding new, low cost hybridization- and sensor technologies. One promising approach is to use commercial CMOS technologies to produce the passive sensor for a hybrid pixel detector design. In this talk a fully functional prototype of a 300 μm thick, backside biased CMOS pixel sensor in 150 nm LFoundry technology is presented. The sensor is bump bonded to the ATLAS FE-I4 with AC and DC coupled pixels. Results like leakage current, noise performance, and charge collection efficiency are presented and compared to the actual ATLAS pixel sensor design.

Some design aspects of a two-stage rail-to-rail CMOS op amp

NARCIS (Netherlands)

Gierkink, Sander L.J.; Holzmann, Peter J.; Wiegerink, Remco J.; Wassenaar, R.F.

1999-01-01

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

Science.gov (United States)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

Science.gov (United States)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

Energy Technology Data Exchange (ETDEWEB)

Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

2010-03-15

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

Matching fully differential NNLO calculations and parton showers

Energy Technology Data Exchange (ETDEWEB)

Alioli, Simone; Bauer, Christian W.; Berggren, Calvin; Walsh, Jonathan R.; Zuberi, Saba [California Univ., Berkeley, CA (United States). Ernest Orlando Lawrence Berkeley National Laboratory; Tackmann, Frank J. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

2013-11-15

We present a general method to match fully differential next-to-next-to-leading (NNLO) calculations to parton shower programs. We discuss in detail the perturbative accuracy criteria a complete NNLO+PS matching has to satisfy. Our method is based on consistently improving a given NNLO calculation with the leading-logarithmic (LL) resummation in a chosen jet resolution variable. The resulting NNLO+LL calculation is cast in the form of an event generator for physical events that can be directly interfaced with a parton shower routine, and we give an explicit construction of the input ''Monte Carlo cross sections'' satisfying all required criteria. We also show how other proposed approaches naturally arise as special cases in our method.

A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

International Nuclear Information System (INIS)

Kuang Lixue; Chi Baoyong; Chen Lei; Wang Zhihua; Jia Wen

2014-01-01

A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD) and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is −97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 mW, including all the buffers. (semiconductor integrated circuits)

A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

Science.gov (United States)

Lixue, Kuang; Baoyong, Chi; Lei, Chen; Wen, Jia; Zhihua, Wang

2014-12-01

A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD) and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is -97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 mW, including all the buffers.

Design and Characterization of a Fully Differential MEMS Accelerometer Fabricated Using MetalMUMPs Technology

Directory of Open Access Journals (Sweden)

Hongwei Qu

2013-05-01

Full Text Available This paper presents a fully differential single-axis accelerometer fabricated using the MetalMUMPs process. The unique structural configuration and common-centriod wiring of the metal electrodes enables a fully differential sensing scheme with robust metal sensing structures. CoventorWare is used in structural and electrical design and simulation of the fully differential accelerometer. The MUMPs foundry fabrication process of the sensor allows for high yield, good process consistency and provides 20 μm structural thickness of the sensing element, which makes the capacitive sensing eligible. In device characterization, surface profile of the fabricated device is measured using a Veeco surface profilometer; and mean and gradient residual stress in the nickel structure are calculated as approximately 94.7 MPa and −5.27 MPa/μm, respectively. Dynamic characterization of the sensor is performed using a vibration shaker with a high-end commercial calibrating accelerometer as reference. The sensitivity of the sensor is measured as 0.52 mV/g prior to off-chip amplification. Temperature dependence of the sensing capacitance is also characterized. A −0.021fF/°C is observed. The findings in the presented work will provide useful information for design of sensors and actuators such as accelerometers, gyroscopes and electrothermal actuators that are to be fabricated using MetalMUMPs technology.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

Science.gov (United States)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

International Nuclear Information System (INIS)

Liu Nan; Chen Guoping; Hong Zhiliang

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm 2 and consumes 37 mW.

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor.

Science.gov (United States)

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2016-02-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

Energy Technology Data Exchange (ETDEWEB)

Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

2009-06-01

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

International Nuclear Information System (INIS)

Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

2009-01-01

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

A low-voltage fully balanced CMFF transconductor with improved linearity

Science.gov (United States)

Calvo, B.; Celma, S.; Alegre, J. P.; Sanz, M. T.

2007-05-01

This paper presents a new low-voltage pseudo-differential continuous-time CMOS transconductor for wideband applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Simulation results for a 0.35 μm CMOS design show a 1:2 G m tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 200 μA p-p differential output. The proposed cell consumes less than 1.2 mW from a single 2.0 V supply.

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

International Nuclear Information System (INIS)

Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

2011-01-01

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

Science.gov (United States)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

Advanced CMOS device technologies for 45 nm node and below

Directory of Open Access Journals (Sweden)

A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

2007-01-01

Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

Energy Technology Data Exchange (ETDEWEB)

Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

2016-07-11

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

Science.gov (United States)

Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

2016-07-01

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

International Nuclear Information System (INIS)

Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

2016-01-01

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

International Nuclear Information System (INIS)

Han Ye; Li Quanliang; Shi Cong; Wu Nanjian

2013-01-01

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm 2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. (semiconductor integrated circuits)

A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps

Science.gov (United States)

Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

2010-06-01

Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

2012-01-01

. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

The 128-channel fully differential digital integrated neural recording and stimulation interface.

Science.gov (United States)

Shahrokhi, Farzaneh; Abdelhalim, Karim; Serletis, Demitre; Carlen, Peter L; Genov, Roman

2010-06-01

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg(2+)/high-K(+) epileptic seizure model in an intact hippocampus of a mouse.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

International Nuclear Information System (INIS)

Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

2005-01-01

This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

A new memory effect (MSD) in fully depleted SOI MOSFETs

Science.gov (United States)

Bawedin, M.; Cristoloveanu, S.; Yun, J. G.; Flandre, D.

2005-09-01

We demonstrate that the transconductance and drain current of fully depleted MOSFETs can display an interesting time-dependent hysteresis. This new memory effect, called meta-stable dip (MSD), is mainly due to the long carrier generation lifetime in the silicon film. Our parametric analysis shows that the memory window can be adjusted in view of practical applications. Various measurement conditions and devices with different doping, front oxide and silicon film thicknesses are systematically explored. The MSD effect can be generalized to several fully depleted CMOS technologies. The MSD mechanism is discussed and validated by two-dimensional simulations results.

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

NARCIS (Netherlands)

Babaie, M.; Kuo, F.W.; Chen, H; Cho, L.C.; Jou, C.P.; Hsueh, F.L.; Shahmohammadi, M.; Staszewski, R.B.

2016-01-01

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply

Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

KAUST Repository

Shaikh, Sohail F.

2017-01-17

The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

International Nuclear Information System (INIS)

Contopanagos, Harry

2005-01-01

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

Energy Technology Data Exchange (ETDEWEB)

Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

2005-01-01

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

Microelectronic test structures for CMOS technology

CERN Document Server

Ketchen, Mark B

2011-01-01

Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback

DEFF Research Database (Denmark)

Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre

consumption. The DC-gain of the proposed OTA is improved by adding a partial feedback loop. A Common-Mode Feedback (CMFB) circuit is required for fully differential rail-to-rail operation. Simulations show that the OTA topology has a low stand-by power consumption of 96μW and a high FoM of 3.84 [(V...

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

Science.gov (United States)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

CMOS Current-mode Operational Amplifier

OpenAIRE

Kaulberg, Thomas

1992-01-01

A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-r...

Large area CMOS image sensors

International Nuclear Information System (INIS)

Turchetta, R; Guerrini, N; Sedgwick, I

2011-01-01

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

Improvement to the signaling interface for CMOS pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Shi, Zhan, E-mail: sz1134@163.com [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Tang, Zhenan, E-mail: tangza@dlut.edu.cn [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Feng, Chong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Dalian Minzu University, No.18 Liaohe West Road, 116600 Dalian (China); Cai, Hong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China)

2016-10-01

The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

Global On-Chip Differential Interconnects with Optimally-Placed Twists

NARCIS (Netherlands)

Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

2005-01-01

Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects

Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

Science.gov (United States)

Vishnoi, U.; Noll, T. G.

2012-09-01

The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

International Nuclear Information System (INIS)

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-01-01

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12μm to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented

A 50–60 GHz mm-wave rectifier with bulk voltage bias in 65-nm CMOS

NARCIS (Netherlands)

Gao, H.; Matters-Kammerer, M.; Harpe, P.; Baltus, P.

2016-01-01

This letter presents a 50∼60 GHz fully integrated 3-stage rectifier with bulk voltage bias for threshold voltage modulation in a 65-nm CMOS technology, which can be integrated in a mm-wave hybrid rectifier structure as the main rectifier. In this letter, the new technique of bulk voltage bias is

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications

International Nuclear Information System (INIS)

Passeri, D; Placidi, P; Servoli, L; Meroli, S; Magalotti, D; Marras, A

2012-01-01

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

A CMOS pressure sensor with integrated interface for passive RFID applications

International Nuclear Information System (INIS)

Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

2014-01-01

This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18 μm CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2 fF kPa −1 . The sensor interface consumes only 1.1 µW of power at 0.5 V voltage supply, which is at least an order of magnitude better than state-of-the-art designs. (paper)

Optoelectronic circuits in nanometer CMOS technology

CERN Document Server

Atef, Mohamed

2016-01-01

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

CMOS test and evaluation a physical perspective

CERN Document Server

Bhushan, Manjul

2015-01-01

This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

Science.gov (United States)

Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

2016-12-21

One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Directory of Open Access Journals (Sweden)

Mauro Olivieri

2013-01-01

Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

Absorbed dose by a CMOS in radiotherapy

International Nuclear Information System (INIS)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

2011-10-01

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Neutron absorbed dose in a pacemaker CMOS

International Nuclear Information System (INIS)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

2012-01-01

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2012-06-15

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

Absorbed dose by a CMOS in radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-10-15

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Wideband CMOS receivers

CERN Document Server

Oliveira, Luis

2015-01-01

This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

Science.gov (United States)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

Science.gov (United States)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

A CMOS integrated timing discriminator circuit for fast scintillation counters

International Nuclear Information System (INIS)

Jochmann, M.W.

1998-01-01

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

CMOS sensors for atmospheric imaging

Science.gov (United States)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

Dysfunctions at human intestinal barrier by water-borne protozoan parasites: lessons from cultured human fully differentiated colon cancer cell lines.

Science.gov (United States)

Liévin-Le Moal, Vanessa

2013-06-01

Some water-borne protozoan parasites induce diseases through their membrane-associated functional structures and virulence factors that hijack the host cellular molecules and signalling pathways leading to structural and functional lesions in the intestinal barrier. In this Microreview we analyse the insights on the mechanisms of pathogenesis of Entamoeba intestinalis, Giardia and Cryptosporidium observed in the human colon carcinoma fully differentiated colon cancer cell lines, cell subpopulations and clones expressing the structural and functional characteristics of highly specialized fully differentiated epithelial cells lining the intestinal epithelium and mimicking structurally and functionally an intestinal barrier. © 2013 John Wiley & Sons Ltd.

Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

CERN Document Server

El-Khatib, Ziad; Mahmoud, Samy A

2012-01-01

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

Directory of Open Access Journals (Sweden)

Ler Chun Lee

2008-01-01

Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

Scalable production of sub-μm functional structures made of non-CMOS compatible materials on glass

Science.gov (United States)

Arens, Winfried

2014-03-01

Biophotonic and Life Science applications often require non-CMOS compatible materials to be patterned with sub μm resolution. Whilst the mass production of sub μm patterns is well established in the semiconductor industry, semiconductor fabs are limited to using CMOS compatible materials. IMT of Switzerland has implemented a fully automated manufacturing line that allows cost effective mass manufacturing of consumables for biophotonics in substrate materials like D263 glass or fused silica and layer/coating materials like Cr, SiO2, Cr2O5, Nb2O5, Ta2O5 and with some restrictions even gold with sub-μm patterns. The applied processes (lift-off and RIE) offer a high degree of freedom in the design of the consumable.

A CMOS Morlet Wavelet Generator

Directory of Open Access Journals (Sweden)

A. I. Bautista-Castillo

2017-04-01

Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

CMOS image sensors: State-of-the-art

Science.gov (United States)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

All-CMOS night vision viewer with integrated microdisplay

Science.gov (United States)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Beyond CMOS nanodevices 1

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

Beyond CMOS nanodevices 2

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

Variation-aware advanced CMOS devices and SRAM

CERN Document Server

Shin, Changhwan

2016-01-01

This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

Poly-SiGe for MEMS-above-CMOS sensors

CERN Document Server

Gonzalez Ruiz, Pilar; Witvrouw, Ann

2014-01-01

Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

Directory of Open Access Journals (Sweden)

Daehyeok Kim

2015-03-01

Full Text Available In order to increase the operating speed of a CMOS image sensor (CIS, a new technique of digital correlated double sampling (CDS is described. In general, the fixed pattern noise (FPN of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

Directory of Open Access Journals (Sweden)

Hongyi Mi

2017-03-01

Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

Science.gov (United States)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal

2012-06-01

In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

A Standard CMOS Humidity Sensor without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

Directory of Open Access Journals (Sweden)

Mohammad Reza Shokrani

2014-01-01

Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

Science.gov (United States)

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-11-15

The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

Energy Technology Data Exchange (ETDEWEB)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

2009-12-15

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

International Nuclear Information System (INIS)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

2009-01-01

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

CMOS-sensors for energy-resolved X-ray imaging

International Nuclear Information System (INIS)

Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

2016-01-01

Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

Science.gov (United States)

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

High-speed nonvolatile CMOS/MNOS RAM

International Nuclear Information System (INIS)

Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

1979-01-01

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

Science.gov (United States)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

JPL CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa

2017-11-23

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

Batch Processing of CMOS Compatible Feedthroughs

DEFF Research Database (Denmark)

Rasmussen, F.E.; Heschel, M.; Hansen, Ole

2003-01-01

. The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Carbon Nanotube Integration with a CMOS Process

Science.gov (United States)

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Single photon detection and localization accuracy with an ebCMOS camera

Energy Technology Data Exchange (ETDEWEB)

Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

2015-07-01

The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

CERN Document Server

Hehn, Thorsten

2014-01-01

This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

Broadband image sensor array based on graphene-CMOS integration

Science.gov (United States)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

CMOS Cell Sensors for Point-of-Care Diagnostics

Science.gov (United States)

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Fully differential cross sections for Li2+-impact ionization of Li(2s) and Li(2p)

Science.gov (United States)

Ghorbani, Omid; Ghanbari-Adivi, Ebrahim; Fabian Ciappina, Marcelo

2018-05-01

A semiclassical impact parameter version of the continuum distorted wave-Eikonal initial state theory is developed to study the differential ionization of Li atoms in collisions with Li2+ ions. Both post and prior forms of the transition amplitude are considered. The fully differential cross sections are calculated for the lithium targets in their ground and their first excited states and for the projectile ions at 16 MeV impact energy. The role of the inter-nuclear interaction as well as the significance of the post-prior discrepancy in the ejected electron spectra are investigated. The obtained results for ejection of the electron into the azimuthal plane are compared with the recent measurements and with their corresponding values obtained using a fully quantum mechanical version of the theory. In most of the cases, the consistency of the present approach with the experimental and the quantum theoretical data is reasonable. However, for 2p-state ionization, in the cases where no experimental data exist, there is a considerable difference between the two theoretical approaches. This difference is questionable and further experiments are needed to judge which theory makes a more accurate description of the collision dynamics.

CMOS optimization for radiation hardness

International Nuclear Information System (INIS)

Derbenwick, G.F.; Fossum, J.G.

1975-01-01

Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

CMOS MEMS capacitive absolute pressure sensor

International Nuclear Information System (INIS)

Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

2013-01-01

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

An auto-biased 0.5 um CMOS transconductor for very high frequency applications

OpenAIRE

Garrido, Nuno; Franca, José E.

1998-01-01

This paper describes a CMOS transconductance cell for the implementation of very high frequency current-mode gm-C filters. It features simple pseudo-differential circuitry employing small device size transistors and yielding a power dissipation of less than 1 mW/pole at nominal 3.0 V supply voltage. Self-biased common-mode voltage designed to minimize mismatch errors, improves noise and stability behavior. Short channel effects are analyzed and simulation results are presented.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

Energy Technology Data Exchange (ETDEWEB)

Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin' an, E-mail: wangxa@szpku.edu.c [Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen 518055 (China)

2009-06-01

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 mum{sup 2} without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

International Nuclear Information System (INIS)

Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

2009-01-01

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 μm 2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

International Nuclear Information System (INIS)

Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

2012-01-01

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

Self-calibrated humidity sensor in CMOS without post-processing.

Science.gov (United States)

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Self-Calibrated Humidity Sensor in CMOS without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Radiation-hardened bulk CMOS technology

International Nuclear Information System (INIS)

Dawes, W.R. Jr.; Habing, D.H.

1979-01-01

The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

CMOS/SOS processing

Science.gov (United States)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

Directory of Open Access Journals (Sweden)

Jose Luis Muñoz-Gamarra

2016-02-01

Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

Simulations of depleted CMOS sensors for high-radiation environments

CERN Document Server

Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

2017-01-01

After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

2018-01-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.

2018-02-27

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

Prevention of CMOS latch-up by gold doping

International Nuclear Information System (INIS)

Dawes, W.R.; Derbenwick, G.F.

1976-01-01

CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications

International Nuclear Information System (INIS)

Peters, Christian; Ortmanns, Maurits; Manoli, Yiannos; Spreemann, Dirk

2008-01-01

In this paper, a fully CMOS integrated active AC/DC converter for energy harvesting applications is presented. The rectifier is realized in a standard 0.35 µm CMOS process without special process options. It works as a full wave rectifier and can be separated into two stages—one passive and one active. The active part is powered from the storage capacitor and consumes about 600 nA at 2 V supply. The input voltage amplitude range is between 1.25 and 3.75 V, and the operating frequency range is from 1 Hz to as much as several 100 kHz. The series voltage drop over the rectifier is less than 20 mV. Measurements in combination with an electromagnetic harvester show a significant increase in the achievable output voltage and power compared to a common, discrete Schottky diode rectifier. The measured efficiency of the rectifier is over 95%. Measurements show a negligible temperature influence on the output voltage between −40 °C and +125 °C

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

Science.gov (United States)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

International Nuclear Information System (INIS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-01-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM

Design and simulation of Gaussian shaping amplifier made only with CMOS FET for FEE of particle detector

International Nuclear Information System (INIS)

Wembe Tafo Evariste; Su Hong; Qian Yi; Kong Jie; Wang Tongxi

2010-01-01

The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip, Si (Li), CdZnTe and CsI detectors, etc., which can be further integrated the whole system and adopted to develop CMOS-based application, specific integrated circuit for Front End Electronics (FEE) of read-out system of nuclear physics, particle physics and astrophysics research, etc. It's why we used only CMOS transistor to develop the entire system. A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC 4 filter, we perform shaping time in the range, 465 ns to 2.76μs with a low output resistance and the linearity almost good. (authors)

An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

International Nuclear Information System (INIS)

Gao Peijun; Min Hao; Oh, N J

2009-01-01

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative g m -cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply. (semiconductor integrated circuits)

Toward CMOS image sensor based glucose monitoring.

Science.gov (United States)

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

High-voltage CMOS detectors

International Nuclear Information System (INIS)

Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

2016-01-01

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High-voltage CMOS detectors

Energy Technology Data Exchange (ETDEWEB)

Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

2016-07-11

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

A Differential Electrochemical Readout ASIC With Heterogeneous Integration of Bio-Nano Sensors for Amperometric Sensing.

Science.gov (United States)

Ghoreishizadeh, Sara S; Taurino, Irene; De Micheli, Giovanni; Carrara, Sandro; Georgiou, Pantelis

2017-10-01

A monolithic biosensing platform is presented for miniaturized amperometric electrochemical sensing in CMOS. The system consists of a fully integrated current readout circuit for differential current measurement as well as on-die sensors developed by growing platinum nanostructures (Pt-nanoS) on top of electrodes implemented with the top metal layer. The circuit is based on the switch-capacitor technique and includes pseudodifferential integrators for concurrent sampling of the differential sensor currents. The circuit further includes a differential to single converter and a programmable gain amplifier prior to an ADC. The system is fabricated in [Formula: see text] technology and measures current within [Formula: see text] with minimum input-referred noise of [Formula: see text] and consumes [Formula: see text] from a [Formula: see text] supply. Differential sensing for nanostructured sensors is proposed to build highly sensitive and offset-free sensors for metabolite detection. This is successfully tested for bio-nano-sensors for the measurement of glucose in submilli molar concentrations with the proposed readout IC. The on-die electrodes are nanostructured and cyclic voltammetry run successfully through the readout IC to demonstrate detection of [Formula: see text].

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

Science.gov (United States)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

Large Format CMOS-based Detectors for Diffraction Studies

Science.gov (United States)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Large Format CMOS-based Detectors for Diffraction Studies

International Nuclear Information System (INIS)

Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

2013-01-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

A CMOS smart temperature and humidity sensor with combined readout.

Science.gov (United States)

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

NARCIS (Netherlands)

Dutta, Satadal

2017-01-01

Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

Directory of Open Access Journals (Sweden)

Haitao Li

2016-12-01

Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

E-Beam Effects on CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

2011-01-01

Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

Science.gov (United States)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

CMOS-compatible spintronic devices: a review

Science.gov (United States)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

A low-power and small-area column-level ADC for high frame-rate CMOS pixel sensor

Energy Technology Data Exchange (ETDEWEB)

Zhang, L., E-mail: liang.zhang@iphc.cnrs.fr [School of Physics, Key Laboratory of Particle Physics and Particle Irradiation, Shandong University, 250100 Jinan (China); Institut Pluridisciplinaire Hubert Curien, University of Strasbourg, CNRS/IN2P3/UDS, 23 rue du loess, BP 28, 67037 Strasbourg (France); Morel, F.; Hu-Guo, C.; Hu, Y. [Institut Pluridisciplinaire Hubert Curien, University of Strasbourg, CNRS/IN2P3/UDS, 23 rue du loess, BP 28, 67037 Strasbourg (France)

2014-07-01

CMOS pixel sensors (CPS) have demonstrated performances meeting the specifications of the International Linear Collider (ILC) vertex detector (VTX). This paper presents a low-power and small-area 4-bit column-level analog-to-digital converter (ADC) for CMOS pixel sensors. The ADC employs a self-timed trigger and completes the conversion by performing a multi-bit/step approximation. As in the outer layers of the ILC vertex detector hit density is of the order of a few per thousand, in order to reduce power consumption, the ADC is designed to work in two modes: active mode and idle mode. The ADC is fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. It is implemented with 48 columns in a sensor prototype. Each column ADC covers an area of 35 ×545 μm{sup 2}. The measured temporal noise and Fixed Pattern Noise (FPN) are 0.96 mV and 0.40 mV, respectively. The power consumption, for a 3 V supply and 6.25 MS/s sampling rate, is 486 μW during idle time, which is by far the most frequently employed one. This value rises to 714 μW in the case of the active mode. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.49/−0.28 LSB and 0.29/−0.20 LSB, respectively. - Highlights: • CMOS sensor integrated with column-level ADC is proposed for ILC VTX outer layers. • A low-power and small-area column-level ADC for high frame-rate CPS is presented. • The test results demonstrate the power and area efficiency. • The architecture is suitable for the outer layer CMOS sensors.

A low-power and small-area column-level ADC for high frame-rate CMOS pixel sensor

International Nuclear Information System (INIS)

Zhang, L.; Morel, F.; Hu-Guo, C.; Hu, Y.

2014-01-01

CMOS pixel sensors (CPS) have demonstrated performances meeting the specifications of the International Linear Collider (ILC) vertex detector (VTX). This paper presents a low-power and small-area 4-bit column-level analog-to-digital converter (ADC) for CMOS pixel sensors. The ADC employs a self-timed trigger and completes the conversion by performing a multi-bit/step approximation. As in the outer layers of the ILC vertex detector hit density is of the order of a few per thousand, in order to reduce power consumption, the ADC is designed to work in two modes: active mode and idle mode. The ADC is fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. It is implemented with 48 columns in a sensor prototype. Each column ADC covers an area of 35 ×545 μm 2 . The measured temporal noise and Fixed Pattern Noise (FPN) are 0.96 mV and 0.40 mV, respectively. The power consumption, for a 3 V supply and 6.25 MS/s sampling rate, is 486 μW during idle time, which is by far the most frequently employed one. This value rises to 714 μW in the case of the active mode. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.49/−0.28 LSB and 0.29/−0.20 LSB, respectively. - Highlights: • CMOS sensor integrated with column-level ADC is proposed for ILC VTX outer layers. • A low-power and small-area column-level ADC for high frame-rate CPS is presented. • The test results demonstrate the power and area efficiency. • The architecture is suitable for the outer layer CMOS sensors

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

Science.gov (United States)

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Theoretical calculation of fully differential cross sections for electron-impact ionization of hydrogen molecules

International Nuclear Information System (INIS)

Gao Junfang; Madison, D H; Peacher, J L

2006-01-01

We have recently proposed the orientation averaged molecular orbital (OAMO) approximation for calculating fully differential cross sections (FDCS) for electron-impact ionization of molecules averaged over all molecular orientations. Orientation averaged FDCS were calculated for electron-impact ionization of nitrogen molecules using the distorted wave impulse approximation (DWIA) and the molecular three-body distorted wave (M3DW) approximation. In this paper, we use the same methods to examine the FDCS for ionization of hydrogen molecules. It is found that the DWIA yields reasonable results for high-energy incident electrons. While the DWIA breaks down for low-energy electrons, the M3DW gives reasonable results down to incident-electron energies around 35 eV

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

2017-01-01

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

Data.gov (United States)

Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

CMOS Compressed Imaging by Random Convolution

OpenAIRE

Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

2009-01-01

We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

The challenge of sCMOS image sensor technology to EMCCD

Science.gov (United States)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Variationen und ihre Kompensation in CMOS Digitalschaltungen

OpenAIRE

Baumann, Thomas

2010-01-01

Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

CMOS Integrated Carbon Nanotube Sensor

International Nuclear Information System (INIS)

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

2009-01-01

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

Characterization of active CMOS sensors for capacitively coupled pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

2015-07-01

Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Long term ionization response of several BiCMOS VLSIC technologies

International Nuclear Information System (INIS)

Pease, R.L.; Combs, W.; Clark, S.

1992-01-01

BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

First principle leakage current reduction technique for CMOS devices

CSIR Research Space (South Africa)

Tsague, HD

2015-12-01

Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

RAPS: an innovative active pixel for particle detection integrated in CMOS technology

International Nuclear Information System (INIS)

Passeri, Daniele; Placidi, Pisana; Verducci, Leonardo; Ciampolini, Paolo; Matrella, Guido; Marras, Alessandro; Bilei, G.M.

2004-01-01

In this paper we discuss some design, implementation and test issues, with respect to the development of the RAPS01 chip in the framework of the Radiation Active Pixel Sensors (RAPS) INFN project. The project aimed at verifying feasibility of smart, high-resolution pixel arrays with a fully standard, submicron CMOS technology for particle detection purposes. Layout optimization of the pixel, including sensitive element and local read and amplification circuits has been carried out. Different basic pixel schemes and read-out options have been proposed and devised. Chip fabrication has been completed and test phase is now under way: to this purpose a suitable test environment has been devised and test strategies have been planned

Ion traps fabricated in a CMOS foundry

Energy Technology Data Exchange (ETDEWEB)

Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

CMOS front ends for millimeter wave wireless communication systems

CERN Document Server

Deferm, Noël

2015-01-01

This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

International Nuclear Information System (INIS)

Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

2006-01-01

Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

Science.gov (United States)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

NARCIS (Netherlands)

Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

2018-01-01

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

DEFF Research Database (Denmark)

Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

2008-01-01

This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

CMOS-compatible high-voltage integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Parpia, Z

1988-01-01

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

CMOS Image Sensors: Electronic Camera On A Chip

Science.gov (United States)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

CMOS image sensor-based immunodetection by refractive-index change.

Science.gov (United States)

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

International Nuclear Information System (INIS)

Luo Yanbin; Ma Chengyan; Gan Yebing; Qian Min; Ye Tianchun

2015-01-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm 2 . (paper)

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Photon detection with CMOS sensors for fast imaging

International Nuclear Information System (INIS)

Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

2009-01-01

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

Contact CMOS imaging of gaseous oxygen sensor array.

Science.gov (United States)

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Single-chip RF communications systems in CMOS

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

CMOS sigma-delta converters practical design guide

CERN Document Server

De la Rosa, Jose M

2013-01-01

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

Science.gov (United States)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

Advancement of CMOS Doping Technology in an External Development Framework

Science.gov (United States)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Science.gov (United States)

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Transient-induced latchup in CMOS integrated circuits

CERN Document Server

Ker, Ming-Dou

2009-01-01

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

Science.gov (United States)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

Science.gov (United States)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Development of a CMOS process using high energy ion implantation

International Nuclear Information System (INIS)

Stolmeijer, A.

1986-01-01

The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

Science.gov (United States)

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

National Research Council Canada - National Science Library

An, S

2001-01-01

.... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

Science.gov (United States)

Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

2017-06-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

International Nuclear Information System (INIS)

Pernegger, H.; Hoorne, J.W. van; Kugathasan, T.; Musa, L.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E.J.; Snoeys, W.; Bates, R.; Buttar, C.; Maneuski, D.; Dalla, M.; Sbarra, C.

2017-01-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 10"1"5 n _e_q/cm"2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

Electron capture to the continuum manifestation in fully differential cross sections for ion impact single ionization

Science.gov (United States)

Ciappina, M. F.; Fojón, O. A.; Rivarola, R. D.

2018-04-01

We present theoretical calculations of single ionization of He atoms by protons and multiply charged ions. The kinematical conditions are deliberately chosen in such a way that the ejected electron velocity matches the projectile impact velocity. The computed fully differential cross sections (FDCS) in the scattering plane using the continuum-distorted wave-eikonal initial state show a distinct peaked structure for a polar electron emission angle θ k = 0°. This element is absent when a first order theory is employed. Consequently, we can argue that this peak is a clear manifestation of a three-body effect, not observed before in FDCS. We discuss a possible interpretation of this new feature.

Nano-electromechanical switch-CMOS hybrid technology and its applications.

Science.gov (United States)

Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

2011-01-01

Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

Science.gov (United States)

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

A novel multi-actuation CMOS RF MEMS switch

Science.gov (United States)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Integrated 60GHz RF beamforming in CMOS

CERN Document Server

Yu, Yikun; van Roermund, Arthur H M

2011-01-01

""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

Challenges & Roadmap for Beyond CMOS Computing Simulation.

Energy Technology Data Exchange (ETDEWEB)

Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2017-12-01

Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Characterization of active CMOS pixel sensors on high resistive substrate

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

2016-07-01

Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

Science.gov (United States)

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

CERN Document Server

Nguyen, Cam

2017-01-01

This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Risti{c}, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Gaudiello, Andrea; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Recent developments with CMOS SSPM photodetectors

Energy Technology Data Exchange (ETDEWEB)

Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

2009-10-21

Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

Directory of Open Access Journals (Sweden)

Farès TOUNSI

2009-09-01

Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

CERN Document Server

Hervé, C

2002-01-01

This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

Spiral-Shaped Piezoelectric MEMS Cantilever Array for Fully Implantable Hearing Systems

Directory of Open Access Journals (Sweden)

Péter Udvardi

2017-10-01

Full Text Available Fully implantable, self-powered hearing aids with no external unit could significantly increase the life quality of patients suffering severe hearing loss. This highly demanding concept, however, requires a strongly miniaturized device which is fully implantable in the middle/inner ear and includes the following components: frequency selective microphone or accelerometer, energy harvesting device, speech processor, and cochlear multielectrode. Here we demonstrate a low volume, piezoelectric micro-electromechanical system (MEMS cantilever array which is sensitive, even in the lower part of the voice frequency range (300–700 Hz. The test array consisting of 16 cantilevers has been fabricated by standard bulk micromachining using a Si-on-Insulator (SOI wafer and aluminum nitride (AlN as a complementary metal-oxide-semiconductor (CMOS and biocompatible piezoelectric material. The low frequency and low device footprint are ensured by Archimedean spiral geometry and Si seismic mass. Experimentally detected resonance frequencies were validated by an analytical model. The generated open circuit voltage (3–10 mV is sufficient for the direct analog conversion of the signals for cochlear multielectrode implants.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

Science.gov (United States)

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

International Nuclear Information System (INIS)

Zheng Renliang; Ren Junyan; Li Wei; Li Ning

2009-01-01

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18 μm RF CMOS process with an area of 1.74 mm 2 and only consumes 32 mA current (at 1.8 V) including the test associated parts. (semiconductor integrated circuits)

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 {mu}m CMOS for OFDM-UWB

Energy Technology Data Exchange (ETDEWEB)

Zheng Renliang; Ren Junyan; Li Wei; Li Ning, E-mail: jyren@fudan.edu.c [Micro/Nano Science and Innovation Platform, State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-12-15

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18 {mu}m RF CMOS process with an area of 1.74 mm{sup 2} and only consumes 32 mA current (at 1.8 V) including the test associated parts. (semiconductor integrated circuits)

CMOS-based avalanche photodiodes for direct particle detection

International Nuclear Information System (INIS)

Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

2007-01-01

Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

The total dose effects on the 1/f noise of deep submicron CMOS transistors

International Nuclear Information System (INIS)

Hu Rongbin; Wang Yuxin; Lu Wu

2014-01-01

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

International Nuclear Information System (INIS)

Zheng Yongzheng; Xia Lingli; Li Weinan; Huang Yumei; Hong Zhiliang

2009-01-01

A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 x 1.8 mm 2 .

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

Energy Technology Data Exchange (ETDEWEB)

Zheng Yongzheng; Xia Lingli; Li Weinan; Huang Yumei; Hong Zhiliang, E-mail: yumeihuang@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-09-15

A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 {mu}m CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 x 1.8 mm{sup 2}.

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

KAUST Repository

Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

2016-01-01

. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

Application of CMOS Technology to Silicon Photomultiplier Sensors

Science.gov (United States)

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

Science.gov (United States)

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

CMOS SPDT switch for WLAN applications

International Nuclear Information System (INIS)

Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

2015-01-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

Cmos spdt switch for wlan applications

Science.gov (United States)

Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

2015-04-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process

International Nuclear Information System (INIS)

Ji Xu; Li Zhihong; Li Juan; Wang Yangyuan; Xi Jianzhong

2008-01-01

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Ristic, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

CMOS voltage references an analytical and practical perspective

CERN Document Server

Kok, Chi-Wah

2013-01-01

A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

Fully integrated low-loss band-pass filters for wireless applications

International Nuclear Information System (INIS)

Rais-Zadeh, M; Kapoor, A; Lavasani, H M; Ayazi, F

2009-01-01

Fully integrated low insertion loss micromachined band-pass filters are designed and fabricated on the silicon substrate (ρ = 10–20 Ω cm, ε r = 11.9) for UHF applications. Filters are made of silver, which has the highest conductivity of all metals, to minimize the ohmic loss. A detailed analysis for realizing low insertion loss and high out-of-band rejection filters using elliptic magnitude characteristics is presented, and a comprehensive model to take into account inductive parasitics of the interconnects is developed. Temperature characteristics of the filters are measured and show stable performance. The presented filters are different from the previously reported lumped element filters in that all filters are fully integrated on silicon substrate and occupy a remarkably smaller die area. Two filters are fabricated using the silver micromachining technique with center frequencies at 1.05 and 1.35 GHz. The filters have a constant 3 dB bandwidth of 300 MHz (28.6% and 22.2%) and an insertion loss of 1.4–1.7 dB. The low insertion loss and CMOS compatibility make the presented filters suitable candidates for radio frequency integrated circuits

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

Science.gov (United States)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

The review of radiation effects of γ total dose in CMOS circuits

International Nuclear Information System (INIS)

Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

1992-01-01

Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

Science.gov (United States)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

An Implantable CMOS Amplifier for Nerve Signals

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Lehmann, Torsten

2001-01-01

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

A novel CMOS SRAM feedback element for SEU environments

International Nuclear Information System (INIS)

Verghese, S.; Wortman, J.J.; Kerns, S.E.

1987-01-01

A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

Materials Characterization of CIGS solar cells on Top of CMOS chips

NARCIS (Netherlands)

Lu, J.; Liu, W.; Kovalgin, A.Y.; Sun, Y.; Schmitz, J.; Venkatasubramanian, R.; Radousky, H.; Liang, H.

2011-01-01

In the current work, we present a detailed study on the material properties of the CIGS layers, fabricated on top of the CMOS chips, and compare the results with the fabrication on standard glass substrates. Almost identical elemental composition on both glass and CMOS chips (within measurement

Radiation imaging detectors made by wafer post-processing of CMOS chips

NARCIS (Netherlands)

Blanco Carballo, V.M.

2009-01-01

In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

A CMOS pressure sensor tag chip for passive wireless applications.

Science.gov (United States)

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-03-23

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

Fully-differential spectrophotometry determination of trace thorium in uranium-containing waste water separated by CL-TBP levextrel resin

International Nuclear Information System (INIS)

You Jiannan

2000-01-01

A method for separation by CL-TBP levextrel resin and determination of trace thorium in uranium-containing waste water by fully-differential spectrophotometry is developed. In 4 mol/L HNO 3 medium, in presence of tartaric acid, CL-TBP levextrel resin is used for adsorption of thorium and separating from other elements. The thorium on the resin is stripped by 4 mol/L HCl, with oxalic acid and urea as screening agent, thorium forms red complex with arsenazo III. The maximum absorption of the complex is at 668 nm, and the molar absorptivity is 1.27 x 10 5 L/(mol·cm) . The complex can be steady for 2.5 h. By regulating micro-current of differential spectrophotometry, the method can realize determination with high precision. Sensitivity of this method increase 10 times than usual spectrophotometry. The relative standard deviation is better than +- 5% and recovery of thorium is 99%-107%

Two CMOS BGR using CM and DTMOST techniques

International Nuclear Information System (INIS)

Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

2009-06-01

Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

High Performance Wideband CMOS CCI and its Application in Inductance Simulator Design

Directory of Open Access Journals (Sweden)

ARSLAN, E.

2012-08-01

Full Text Available In this paper, a new, differential pair based, low-voltage, high performance and wideband CMOS first generation current conveyor (CCI is proposed. The proposed CCI has high voltage swings on ports X and Y and very low equivalent impedance on port X due to super source follower configuration. It also has high voltage swings (close to supply voltages on input and output ports and wideband current and voltage transfer ratios. Furthermore, two novel grounded inductance simulator circuits are proposed as application examples. Using HSpice, it is shown that the simulation results of the proposed CCI and also of the presented inductance simulators are in very good agreement with the expected ones.

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Analog filters in nanometer CMOS

CERN Document Server

Uhrmann, Heimo; Zimmermann, Horst

2014-01-01

Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

International Nuclear Information System (INIS)

Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

2011-01-01

The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

Latch-up in CMOS integrated circuits

International Nuclear Information System (INIS)

Estreich, D.B.; Dutton, R.W.

1978-04-01

An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

DEFF Research Database (Denmark)

Olesen, Ole

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

Design and fabrication of a CMOS-compatible MHP gas sensor

Directory of Open Access Journals (Sweden)

Ying Li

2014-03-01

Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

A high speed, low power consumption LVDS interface for CMOS pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Shi, Zhan, E-mail: sz1134@163.com [Dalian University of Technology, No. 2 Linggong Road, 116024 Dalian (China); Tang, Zhenan, E-mail: tangza@dlut.edu.cn [Dalian University of Technology, No. 2 Linggong Road, 116024 Dalian (China); Tian, Yong [Dalian University of Technology, No. 2 Linggong Road, 116024 Dalian (China); Pham, Hung; Valin, Isabelle; Jaaskelainen, Kimmo [IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

2015-01-01

The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-µm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW.

CMOS cassette for digital upgrade of film-based mammography systems

Science.gov (United States)

Baysal, Mehmet A.; Toker, Emre

2006-03-01

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Desenvolvimento de uma matriz de portas CMOS

OpenAIRE

Jose Geraldo Mendes Taveira

1991-01-01

Resumo: É apresentado o projeto de uma matriz deportas CMOS. O capítulo 11 descreve as etapas de projeto, incluindo desde a escolha da topologia das células internas e de interface, o projeto e a simulação elétrica, até a geração do lay-out. Ocaprtulo III apresenta o projeto dos circuitos de aplicação, incluídos para permitir a validação da matriz. Os circuitos de apl icação são : Oscilador em anel e comparador de códigos. A matriz foi difundida no Primeiro Projeto Multi-Usuário CMOS Brasile...

Ultralow-loss CMOS copper plasmonic waveguides

DEFF Research Database (Denmark)

Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

2016-01-01

with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

KAUST Repository

Ouda, Mahmoud H.

2013-04-17

A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

Directory of Open Access Journals (Sweden)

Milaim Zabeli

2017-11-01

Full Text Available The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.

Improved Space Object Orbit Determination Using CMOS Detectors

Science.gov (United States)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

International Nuclear Information System (INIS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

2016-01-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Science.gov (United States)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Energy Technology Data Exchange (ETDEWEB)

Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

2016-09-21

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

Science.gov (United States)

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Science.gov (United States)

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Above-CMOS a-Si and CIGS Solar Cells for Powering Autonomous Microsystems

NARCIS (Netherlands)

Lu, J.; Liu, W.; van der Werf, C.H.M.; Kovalgin, A.Y.; Sun, Y.; Schropp, R.E.I.; Schmitz, J.

2010-01-01

Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copperindium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

Directory of Open Access Journals (Sweden)

Nan Guo

2014-10-01

Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

Science.gov (United States)

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

Science.gov (United States)

Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

2017-05-01

In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

CERN Document Server

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

2014-01-01

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

A 205GHz Amplifier in 90nm CMOS Technology

Science.gov (United States)

2017-03-01

10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

An introduction to deep submicron CMOS for vertex applications

CERN Document Server

Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

2001-01-01

Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

Linear CMOS RF power amplifiers a complete design workflow

CERN Document Server

Ruiz, Hector Solar

2013-01-01

The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

Dielectric metasurfaces solve differential and integro-differential equations.

Science.gov (United States)

Abdollahramezani, Sajjad; Chizari, Ata; Dorche, Ali Eshaghian; Jamali, Mohammad Vahid; Salehi, Jawad A

2017-04-01

Leveraging subwavelength resonant nanostructures, plasmonic metasurfaces have recently attracted much attention as a breakthrough concept for engineering optical waves both spatially and spectrally. However, inherent ohmic losses concomitant with low coupling efficiencies pose fundamental impediments over their practical applications. Not only can all-dielectric metasurfaces tackle such substantial drawbacks, but also their CMOS-compatible configurations support both Mie resonances that are invariant to the incident angle. Here, we report on a transmittive metasurface comprising arrayed silicon nanodisks embedded in a homogeneous dielectric medium to manipulate phase and amplitude of incident light locally and almost independently. By taking advantage of the interplay between the electric/magnetic resonances and employing general concepts of spatial Fourier transformation, a highly efficient metadevice is proposed to perform mathematical operations including solution of ordinary differential and integro-differential equations with constant coefficients. Our findings further substantiate dielectric metasurfaces as promising candidates for miniaturized, two-dimensional, and planar optical analog computing systems that are much thinner than their conventional lens-based counterparts.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

Science.gov (United States)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

High-ratio voltage conversion in CMOS for efficient mains-connected standby

CERN Document Server

Meyvaert, Hans

2016-01-01

This book describes synergetic innovation opportunities offered by combining the field of power conversion with the field of integrated circuit (IC) design. The authors demonstrate how integrating circuits enables increased operation frequency, which can be exploited in power converters to reduce drastically the size of the discrete passive components. The authors introduce multiple power converter circuits, which are very compact as result of their high level of integration. First, the limits of high-power-density low-voltage monolithic switched-capacitor DC-DC conversion are investigated to enable on-chip power granularization. AC-DC conversion from the mains to a low voltage DC is discussed, enabling an efficient and compact, lower-power auxiliary power supply to take over the power delivery during the standby mode of mains-connected appliances, allowing the main power converter of these devices to be shut down fully. Discusses high-power-density monolithic switched-capacitor DC-DC conversion in bulk CMOS,...

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

Science.gov (United States)

Yijun, Song; Wenyuan, Li

2014-06-01

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which canperform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

International Nuclear Information System (INIS)

Song Yijun; Li Wenyuan

2014-01-01

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which canperform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW. (semiconductor integrated circuits)

Applications of Si/SiGe heterostructures to CMOS devices

International Nuclear Information System (INIS)

Sidek, R.M.

1999-03-01

For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

Research-grade CMOS image sensors for demanding space applications

Science.gov (United States)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2017-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Development of CMOS Imager Block for Capsule Endoscope

International Nuclear Information System (INIS)

Shafie, S; Fodzi, F A M; Tung, L Q; Lioe, D X; Halin, I A; Hasan, W Z W; Jaafar, H

2014-01-01

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5 V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5 V to 3.3 V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5 V to 3.3 V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

OpenAIRE

Hassan Jassim Motlak

2015-01-01

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

CMOS-compatible photonic devices for single-photon generation

Directory of Open Access Journals (Sweden)

Xiong Chunle

2016-09-01

Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

Science.gov (United States)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

Science.gov (United States)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

CMOS technology: a critical enabler for free-form electronics-based killer applications

Science.gov (United States)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

A Differential 4-Path Highly Linear Widely Tunable On-Chip Band-Pass Filter

NARCIS (Netherlands)

Ghaffari, A.; Klumperink, Eric A.M.; Nauta, Bram

2010-01-01

Abstract A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity

Analysis of the resistive network in a bio-inspired CMOS vision chip

Science.gov (United States)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

CMOS VHF transconductance-C lowpass filter

NARCIS (Netherlands)

Nauta, Bram

1990-01-01

Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

International Nuclear Information System (INIS)

Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N

2013-01-01

The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

International Nuclear Information System (INIS)

Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

2015-01-01

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

Science.gov (United States)

2012-12-14

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations, Modifications and Rulings AGENCY: U.S... United States after importation of certain CMOS image sensors and products containing the same based on...

Performance simulation and analysis of a CMOS/nano hybrid nanoprocessor system

International Nuclear Information System (INIS)

Cabe, Adam C; Das, Shamik

2009-01-01

This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for an FPNI implementation using 90 nm CMOS with 15 nm wide nanowire interconnects. Detailed simulations of this design illustrate that critical design choices and tradeoffs exist beyond those specified by the architecture. This includes the selection of the types of junction nanodevices, as well as the implementation of low-level circuits. In particular, the simulation results presented here show that only nanodevices with an 'on/off' current ratio of 200 or more are suitable to produce correct system-level behaviour. Furthermore, the design of the CMOS logic gates in the FPNI system must be customized to accommodate the resistances of both 'on'-state and 'off'-state nanodevices. Using these customized designs together with models of suitable nanodevices, additional simulations demonstrate that, relative to conventional 90 nm CMOS FPGA systems, performance gains can be obtained of up to 70% greater speed or up to a ninefold reduction in energy consumption.

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

Science.gov (United States)

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

Science.gov (United States)

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

A back-illuminated megapixel CMOS image sensor

Science.gov (United States)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

Science.gov (United States)

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor.

Science.gov (United States)

Dennis, John Ojur; Ahmad, Farooq; Khir, M Haris Bin Md; Bin Hamid, Nor Hisham

2015-07-27

Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

A Biologically Inspired CMOS Image Sensor

CERN Document Server

Sarkar, Mukul

2013-01-01

Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

Science.gov (United States)

Davidson, Bradley Darren

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

CMOS technology: a critical enabler for free-form electronics-based killer applications

KAUST Repository

Hussain, Muhammad Mustafa

2016-05-17

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

A 60-GHz energy harvesting module with on-chip antenna and switch for co-integration with ULP radios in 65-nm CMOS with fully wireless mm-wave power transfer measurement

NARCIS (Netherlands)

Gao, H.; Matters - Kammerer, M.; Harpe, P.J.A.; Milosevic, D.; Roermund, van A.H.M.; Linnartz, J.P.M.G.; Baltus, P.G.M.

2014-01-01

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve

Fully implicit kinetic modelling of collisional plasmas

International Nuclear Information System (INIS)

Mousseau, V.A.

1996-05-01

This dissertation describes a numerical technique, Matrix-Free Newton Krylov, for solving a simplified Vlasov-Fokker-Planck equation. This method is both deterministic and fully implicit, and may not have been a viable option before current developments in numerical methods. Results are presented that indicate the efficiency of the Matrix-Free Newton Krylov method for these fully-coupled, nonlinear integro-differential equations. The use and requirement for advanced differencing is also shown. To this end, implementations of Chang-Cooper differencing and flux limited Quadratic Upstream Interpolation for Convective Kinematics (QUICK) are presented. Results are given for a fully kinetic ion-electron problem with a self consistent electric field calculated from the ion and electron distribution functions. This numerical method, including advanced differencing, provides accurate solutions, which quickly converge on workstation class machines. It is demonstrated that efficient steady-state solutions can be achieved to the non-linear integro-differential equation, obtaining quadratic convergence, without incurring the large memory requirements of an integral operator. Model problems are presented which simulate plasma impinging on a plate with both high and low neutral particle recycling typical of a divertor in a Tokamak device. These model problems demonstrate the performance of the new solution method

Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

NARCIS (Netherlands)

Acar, M.

2011-01-01

In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

Nanocantilever based mass sensor integrated with cmos circuitry

DEFF Research Database (Denmark)

Davis, Zachary James; Abadal, G.; Campabadal, F.

2003-01-01

We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

Optimization Design Method for the CMOS-type Capacitive Micro-Machined Ultrasonic Transducer

Directory of Open Access Journals (Sweden)

D. Y. Chiou

2011-12-01

Full Text Available In this study, an integrated modeling technique for characterization and optimization design of the complementary metal-oxide-semiconductor (CMOS capacitive micro-arrayed ultrasonic transducer (pCMOS-CMUT is presented. Electromechanical finite element simulations are performed to investigate its operational characteristics, such as the collapse voltage and the resonant frequency. Both the numerical and experimental results are in good agreement. In order to simultaneously customize the resonant frequency and minimize the collapse voltage, the genetic algorithm (GA is applied to optimize dimensional parameters of the transducer. From the present results, it is concluded that the FE/GA coupling approach provides another efficient numerical tool for multi-objective design of the pCMOS-CMUT.

Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

Energy Technology Data Exchange (ETDEWEB)

Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

2015-07-01

CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

Science.gov (United States)

Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

2012-08-01

An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

Nanosecond-laser induced crosstalk of CMOS image sensor

Science.gov (United States)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

CERN Document Server

Aznar, Francisco; Calvo Lopez, Belén

2013-01-01

This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

From vertex detectors to inner trackers with CMOS pixel sensors

CERN Document Server

Besson, A.

2017-01-01

The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

Designing a robust high-speed CMOS-MEMS capacitive humidity sensor

International Nuclear Information System (INIS)

Lazarus, N; Fedder, G K

2012-01-01

In our previous work (Lazarus and Fedder 2011 J. Micromech. Microeng. 21 0650281), we demonstrated a CMOS-MEMS capacitive humidity sensor with a 72% improvement in sensitivity over the highest previously integrated on a CMOS die. This paper explores a series of methods for creating a faster and more manufacturable high-sensitivity capacitive humidity sensor. These techniques include adding oxide pillars to hold the plates apart, spin coating polymer to allow sensors to be fabricated more cheaply, adding a polysilicon heater and etching away excess polymer in the release holes. In most cases a tradeoff was found between sensitivity and other factors such as response time or robustness. A robust high-speed sensor was designed with a sensitivity of 0.21% change in capacitance per per cent relative humidity, while dropping the response time constant from 70 to 4s. Although less sensitive than our design, the sensor remains 17% more sensitive than the most sensitive interdigitated designs successfully integrated with CMOS. (paper)

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

Science.gov (United States)

Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

2011-05-01

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

Science.gov (United States)

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

Development of a lens-coupled CMOS detector for an X-ray inspection system

International Nuclear Information System (INIS)

Kim, Ho Kyung; Ahn, Jung Keun; Cho, Gyuseong

2005-01-01

A digital X-ray imaging detector based on a complementary metal-oxide-semiconductor (CMOS) image sensor has been developed for X-ray non-destructive inspection applications. This is a cost-effective solution because of the availability of cheap commercial standard CMOS image sensors. The detector configuration adopts an indirect X-ray detection method by using scintillation material and lens assembly. As a feasibility test of the developed lens-coupled CMOS detector as an X-ray inspection system, we have acquired X-ray projection images under a variety of imaging conditions. The results show that the projected image is reasonably acceptable in typical non-destructive testing (NDT). However, the developed detector may not be appropriate for laminography due to a low light-collection efficiency of lens assembly. In this paper, construction of the lens-coupled CMOS detector and its specifications are described, and the experimental results are presented. Using the analysis of quantum accounting diagram, inefficiency of the lens-coupling method is discussed

Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

NARCIS (Netherlands)

Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

Monolithic CMOS imaging x-ray spectrometers

Science.gov (United States)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

Science.gov (United States)

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-10-27

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

Directory of Open Access Journals (Sweden)

Haiyun Huang

2015-10-01

Full Text Available This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

CERN Document Server

Tsirimokou, Georgia; Elwakil, Ahmed

2017-01-01

This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

OpenAIRE

Tanaka, Masahiro; Omura, Ichiro

2012-01-01

Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables t...

Radiation effects of protons and 60Co γ rays on CMOS operational amplifier

International Nuclear Information System (INIS)

Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Yan Rongliang

1997-01-01

Radiation effects of 60 Co γ ray and 4,7 and 30 MeV protons on LF 7650 CMOS operational amplifier were investigated. The damage mechanism of LF7650 was discussed. It is indicated that the mobility reduction of major carrier caused by ionizing and displacement damage is the chief mechanism causing the failure of CMOS operational amplifier irradiated by protons, and that is why the degradation of LF 7650 caused by protons is much more serious than that caused by 60 Co γ ray. In addition, a comparison of proton radiation effects on CMOS operational amplifier and MOSFET showed a significant difference in mechanism

CAcTμS: High-Voltage CMOS Monolithic Active Pixel Sensor for tracking and time tagging of charged particles

CERN Document Server

Guilloux, F.; Degerli, Y.; Elhosni, M.; Guyot, C.; Hemperek, T.; Lachkar, M.; Meyer, JP.; Ouraou, A.; Schwemling, P.; Vandenbroucke, M.

2018-01-01

The increase of luminosity foreseen for the Phase-II HL-LHC upgrades calls for new solutions to fight against the expected pile-up effects. One approach is to measure very accurately the time of arrival of the particles with a resolution of a few tens of picoseconds. In addition, a spatial granularity better than a few millimeter will be needed to obtain a fake jet rejection rate acceptable for physics analysis. These goals could be achieved by using the intrinsic benefits of a standard High-Voltage CMOS technology – in conjunction with a high-resistivity detector material – leading to a fast, integrated, rad-hard, fully depleted monolithic active pixel sensor ASIC.

Wideband pulse amplifiers for the NECTAr chip

International Nuclear Information System (INIS)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J-F.; Naumann, C.L.; Nayman, P.; Ribó, M.

2012-01-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1–3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Wideband pulse amplifiers for the NECTAr chip

Science.gov (United States)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Fully differential Higgs boson pair production in association with a Z boson at next-to-next-to-leading order in QCD

Science.gov (United States)

Li, Hai Tao; Li, Chong Sheng; Wang, Jian

2018-04-01

We present a fully differential next-to-next-to-leading order QCD calculation of the Higgs pair production in association with a Z boson at hadron colliders, which is important for probing the trilinear Higgs self-coupling. The next-to-next-to-leading-order corrections enhance the next-to-leading order total cross sections by a factor of 1.2-1.5, depending on the collider energy, and change the shape of next-to-leading order kinematic distributions. We discuss how to determine the trilinear Higgs self-coupling using our results.

Micromachined high-performance RF passives in CMOS substrate

International Nuclear Information System (INIS)

Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

2016-01-01

This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

CMOS switched current phase-locked loop

NARCIS (Netherlands)

Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

1997-01-01

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

First result on biased CMOS MAPs-on-diamond devices

Energy Technology Data Exchange (ETDEWEB)

Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

2015-10-01

Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

Resistance calculation of un-fully developed two-phase flow through high differential pressure regulating valves

International Nuclear Information System (INIS)

Xu Mingyang; Wang Wenran; Wang Jiaying

1999-01-01

To reduce the flow velocity in the high differential pressure regulating valve with labyrinth. A type of complicated valve core structure were designed with tortuous flow path made from reversal double elbows. It is very difficult to calculate the pressure-drop of the un-fully developed two-phase flow under high temperature and pressure which flow through the valve core. A calculation method called 'constant (varing) pressure-drop progressing step by step design method' was developed. The complicated flow path was disintegrated into a series of independent resistance units and with the valve stem end progressing step by step the dimensions of the flow path were designed in accordance with the principle that in every position the total pressure-drop of the valve should amount to that required by the design goal curve. In the course of calculating the total pressure-drop, the valve flow path was also divided into a series of independent resistance units. The experiment results show that design flow characteristics are approximately consistent with the flow characteristics measured in the test

Geant4-based simulations of charge collection in CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Esposito, M.; Allinson, N.M.; Price, T.; Anaxagoras, T.

2017-01-01

Geant4 is an object-oriented toolkit for the simulation of the interaction of particles and radiation with matter. It provides a snapshot of the state of a simulated particle in time, as it travels through a specified geometry. One important area of application is the modelling of radiation detector systems. Here, we extend the abilities of such modelling to include charge transport and sharing in pixelated CMOS Active Pixel Sensors (APSs); though similar effects occur in other pixel detectors. The CMOS APSs discussed were developed in the framework of the PRaVDA consortium to assist the design of custom sensors to be used in an energy-range detector for proton Computed Tomography (pCT). The development of ad-hoc classes, providing a charge transport model for a CMOS APS and its integration into the standard Geant4 toolkit, is described. The proposed charge transport model includes, charge generation, diffusion, collection, and sharing across adjacent pixels, as well as the full electronic chain for a CMOS APS. The proposed model is validated against experimental data acquired with protons in an energy range relevant for pCT.

Custom high-reliability radiation-hard CMOS-LSI circuit design

International Nuclear Information System (INIS)

Barnard, W.J.

1981-01-01

Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Science.gov (United States)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

International Nuclear Information System (INIS)

Moreau, Y.; Gasiot, J.; Duzellier, S.

1995-01-01

Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined

Cloning mice and ES cells by nuclear transfer from somatic stem cells and fully differentiated cells.

Science.gov (United States)

Wang, Zhongde

2011-01-01

Cloning animals by nuclear transfer (NT) has been successful in several mammalian species. In addition to cloning live animals (reproductive cloning), this technique has also been used in several species to establish cloned embryonic stem (ntES) cell lines from somatic cells. It is the latter application of this technique that has been heralded as being the potential means to produce isogenic embryonic stem cells from patients for cell therapy (therapeutic cloning). These two types of cloning differ only in the steps after cloned embryos are produced: for reproductive cloning the cloned embryos are transferred to surrogate mothers to allow them to develop to full term and for therapeutic cloning the cloned embryos are used to derive ntES cells. In this chapter, a detailed NT protocol in mouse by using somatic stem cells (neuron and skin stem cells) and fully differentiated somatic cells (cumulus cells and fibroblast cells) as nuclear donors is described.

Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

International Nuclear Information System (INIS)

Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

2002-01-01

The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

A new method of preventing bulk-Si CMOS devices from latchup

International Nuclear Information System (INIS)

Xu Xianguo; Xu Xi

2004-01-01

A new method, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After we study the design of pseudo-latchup path method in detail, a practice and the corresponding simulation result by computer are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but it cannot be used to eliminate the dose rate upset of bulk-Si CMOS devices. (authors)

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

International Nuclear Information System (INIS)

Wang, Zujun; Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

2014-01-01

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10 8 n/cm 2 s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10 11 , 5 × 10 11 , and 1 × 10 12 n/cm 2 , respectively. The mean dark signal (K D ), dark signal spike, dark signal non-uniformity (DSNU), noise (V N ), saturation output signal voltage (V S ), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike

CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

International Nuclear Information System (INIS)

Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

2009-01-01

CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Science.gov (United States)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

Science.gov (United States)

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

International Nuclear Information System (INIS)

Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

1989-01-01

The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs

Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern

Directory of Open Access Journals (Sweden)

R. Geißler

2003-01-01

Full Text Available In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference

An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

DEFF Research Database (Denmark)

Shen, Ming; Mikkelsen, Jan H.

2013-01-01

This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

CMOS direct time interval measurement of long-lived luminescence lifetimes.

Science.gov (United States)

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

Implementation of large area CMOS image sensor module using the precision align inspection

International Nuclear Information System (INIS)

Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo; Lee, Kyung Yong; Kim, Jin Soo; Kim, Myung Soo; Cho, Gyu Seong

2014-01-01

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size

Implementation of large area CMOS image sensor module using the precision align inspection

Energy Technology Data Exchange (ETDEWEB)

Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo [Radiation Imaging Technology Center, JBTP, Iksan (Korea, Republic of); Lee, Kyung Yong; Kim, Jin Soo [Nano Sol-Tech INC., Iksan (Korea, Republic of); Kim, Myung Soo; Cho, Gyu Seong [Dept. of Nuclear and Quantum Engineering, KAIST, Daejeon (Korea, Republic of)

2014-12-15

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

CMOS technology and current-feedback op-amps

DEFF Research Database (Denmark)

Bruun, Erik

1993-01-01

Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

International Nuclear Information System (INIS)

Zhang, L.; Wang, M.; Fu, M.; Zhang, Y.; Yan, W.

2017-01-01

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm 2 .

A high performance 90 nm CMOS SAR ADC with hybrid architecture

International Nuclear Information System (INIS)

Tong Xingyuan; Zhu Zhangming; Yang Yintang; Chen Jianming

2010-01-01

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 x 214 μm 2 . The design results of this converter show that it is suitable for multi-supply embedded SoC applications. (semiconductor integrated circuits)

Structured Analog CMOS Design

CERN Document Server

Stefanovic, Danica

2008-01-01

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

Low swing differential logic for mixed signal applications

International Nuclear Information System (INIS)

Fischer, P.; Kraft, E.

2004-01-01

Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power

An ultra-low-power CMOS temperature sensor for RFID applications

Energy Technology Data Exchange (ETDEWEB)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao, E-mail: yanna@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-04-15

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-mum CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 muA and 1.8 V for continuous operation and achieves an accuracy of +-0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

An ultra-low-power CMOS temperature sensor for RFID applications

International Nuclear Information System (INIS)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao

2009-01-01

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA and 1.8 V for continuous operation and achieves an accuracy of ±0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

Directory of Open Access Journals (Sweden)

Ekavut Kritchanchai

2015-08-01

Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

A 24GHz Radar Receiver in CMOS

NARCIS (Netherlands)

Kwok, K.C.

2015-01-01

This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

CMOS circuits for electromagnetic vibration transducers interfaces for ultra-low voltage energy harvesting

CERN Document Server

Maurath, Dominic

2015-01-01

Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100µW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over...

A Multi-Modality CMOS Sensor Array for Cell-Based Assay and Drug Screening.

Science.gov (United States)

Chi, Taiyun; Park, Jong Seok; Butts, Jessica C; Hookway, Tracy A; Su, Amy; Zhu, Chengjie; Styczynski, Mark P; McDevitt, Todd C; Wang, Hua

2015-12-01

In this paper, we present a fully integrated multi-modality CMOS cellular sensor array with four sensing modalities to characterize different cell physiological responses, including extracellular voltage recording, cellular impedance mapping, optical detection with shadow imaging and bioluminescence sensing, and thermal monitoring. The sensor array consists of nine parallel pixel groups and nine corresponding signal conditioning blocks. Each pixel group comprises one temperature sensor and 16 tri-modality sensor pixels, while each tri-modality sensor pixel can be independently configured for extracellular voltage recording, cellular impedance measurement (voltage excitation/current sensing), and optical detection. This sensor array supports multi-modality cellular sensing at the pixel level, which enables holistic cell characterization and joint-modality physiological monitoring on the same cellular sample with a pixel resolution of 80 μm × 100 μm. Comprehensive biological experiments with different living cell samples demonstrate the functionality and benefit of the proposed multi-modality sensing in cell-based assay and drug screening.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

Science.gov (United States)

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

NARCIS (Netherlands)

Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

Directory of Open Access Journals (Sweden)

Chris R. Bowen

2011-05-01

Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

CMOS COLOUR SENSOR BASED pH MEASUREMENT FOR WATER QUALITY ANALYSIS

OpenAIRE

Sanjay Kumar; Arvind Singh

2016-01-01

A Real-Time pH measurement system using a novel design Programmable CMOS optical Colour light to frequency converter TCS230 is presented. The system uses Bogen’s universal indicator solution combined with a white light source and the Programmable CMOS colour sensor TCS230 to measure pH as a function of colour change in a sample. Bogen’s universal indicator solution causes a colour change in a sample according to the pH of the sample. The output frequency from the colour-sensitive CM...

Recent progress in the development of 3D deep n-well CMOS MAPS

International Nuclear Information System (INIS)

Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Manazza, A; Ratti, L; Zucca, S

2012-01-01

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel.

Science.gov (United States)

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-11-01

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

Science.gov (United States)

Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.

2016-03-01

This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.

SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

International Nuclear Information System (INIS)

Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

1993-01-01

A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

Photon imaging using post-processed CMOS chips

NARCIS (Netherlands)

Melai, J.

2010-01-01

This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

High-temperature complementary metal oxide semiconductors (CMOS)

International Nuclear Information System (INIS)

McBrayer, J.D.

1979-10-01

Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

A CMOS four-quadrant analog current multiplier

NARCIS (Netherlands)

Wiegerink, Remco J.

1991-01-01

A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

Science.gov (United States)

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

International Nuclear Information System (INIS)

Li Chen; Liao Huailin; Huang Ru; Wang Yangyuan

2008-01-01

In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

Science.gov (United States)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Gamma and Proton-Induced Dark Current Degradation of 5T CMOS Pinned Photodiode 0.18 mu{m} CMOS Image Sensors

Science.gov (United States)

Martin, E.; Nuns, T.; David, J.-P.; Gilard, O.; Vaillant, J.; Fereyre, P.; Prevost, V.; Boutillier, M.

2014-02-01

The radiation tolerance of a 0.18 μm technology CMOS commercial image sensor has been evaluated with Co60 and proton irradiations. The effects of protons on the hot pixels and dynamic bias and duty cycle conditions during gamma irradiations are studied.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

Science.gov (United States)

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

SiGe BiCMOS manufacturing platform for mmWave applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Chen Qu

2017-09-01

Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

CMOS digital integrated circuits a first course

CERN Document Server

Hawkins, Charles; Zarkesh-Ha, Payman

2016-01-01

This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

A Baseband Ultra-Low Noise SiGe:C BiCMOS 0.25 µm Amplifier And Its Application For An On-Chip Phase-Noise Measurement Circuit

OpenAIRE

Godet , Sylvain; Tournier , Éric; Llopis , Olivier; Cathelin , Andreia; Juyon , Julien

2009-01-01

4 pages; International audience; The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on-chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This ...

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

KAUST Repository

Chen, Min Cheng; Lin, Chia Yi; Li, Kai Hsin; Li, Lain-Jong; Chen, Chang Hsiao; Chuang, Cheng Hao; Lee, Ming Dao; Chen, Yi Ju; Hou, Yun Fang; Lin, Chang Hsien; Chen, Chun Chi; Wu, Bo Wei; Wu, Cheng San; Yang, Ivy; Lee, Yao Jen; Yeh, Wen Kuan; Wang, Tahui; Yang, Fu Liang; Hu, Chenming

2014-01-01

Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

KAUST Repository

Chen, Min Cheng

2014-12-01

Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

Science.gov (United States)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

International Nuclear Information System (INIS)

Walther, S.; Lenoble, D.; Lallement, F.; Grouillet, A.; Erokhin, Y.; Singh, V.; Testoni, A.

2005-01-01

For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5x higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p + /n ultra-shallow junctions formed with BF 3 plasma doping have superior X j /R s characteristics to beamline implants and yield up to 30% lower R s for 20 nm X j while using standard spike anneal with ramp-up rate of 75 deg. C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior V t roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving V t roll-off and I on -I off performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity

Overview of CMOS process and design options for image sensor dedicated to space applications

Science.gov (United States)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Wideband pulse amplifiers for the NECTAr chip

Energy Technology Data Exchange (ETDEWEB)

Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

2012-12-11

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

A 6.2 mW 0.024 mm2 fully-passive RF downconverter with 12 dB gain enhancement using MOS parametric amplification

DEFF Research Database (Denmark)

Custódio, J. R.; Bastos, I.; Oliveira, L. B.

2013-01-01

This paper describes a fully-passive discrete-time switched-capacitor RF downconverter with an on-chip oscillator, that combines quadrature mixing and harmonic rejection, designed in a 130 nm digital CMOS technology. By using MOS capacitors (varactors) to perform parametric amplification, it is p......, it is possible to achieve a measured gain enhancement of about 12 dB, together with 21 dB noise figure and more than 5 dBm IIP3. Operating in the VHF-III band, the downconverter core dissipates 6.2 mW and occupies 0.024 mm2....

TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

CERN Document Server

Buckland, Matthew Daniel

2016-01-01

The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

Inflation in a Fully-Euroised Economy: Could Inflation Differentials Threaten Competitiveness?

Directory of Open Access Journals (Sweden)

Mitrović-Mijatović Marijana

2017-05-01

Full Text Available This paper analyses inflation in Montenegro, a country which uses euro outside the euro area, and investigates the factors which contribute to price differentials in Montenegro relative to the euro area. Furthermore, the paper examines whether changes in the real effective exchange rates, which in Montenegro’s case follow the path of price differentials, may have any influence on country’s competitiveness.

A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

International Nuclear Information System (INIS)

He Wenwei; Meng Qiao; Zhang Yi; Tang Kai

2014-01-01

A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm 2 with the pad. It consumes 210 mW from a 1.2 V single supply. (semiconductor integrated circuits)

A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

International Nuclear Information System (INIS)

Wan Chuanchuan; Li Zhiqun; Hou Ningbing

2011-01-01

A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

Directory of Open Access Journals (Sweden)

N. B. ROMLI

2015-03-01

Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

CMOS Analog IC Design: Fundamentals

OpenAIRE

Bruun, Erik

2018-01-01

This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students directly from a basic level to a level where they can start working on simple analog IC design projects or continue their studies using more advanced textbooks in the field. A distinct feature of thi...

Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

Directory of Open Access Journals (Sweden)

Yasuhisa Omura

2014-01-01

Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

NARCIS (Netherlands)

Chen, Y.; Wang, X.; Mierop, A.J.; Theuwissen, A.J.P.

2009-01-01

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the

Development of a compact electronic dosemeter from CMOS sensor for radon measurement; Developpement d'un dosimetre electronique compact a base de capteurs CMOS pour la mesure du radon

Energy Technology Data Exchange (ETDEWEB)

Higueret, St

2007-12-15

Radon detection is a long-standing challenge in the field of radioprotection, and the IPHC Institute of Strasbourg has pushed for the development of a fully electronic device, portable and really standalone. Our first prototype of CMOS system-on-chip is presented, together with efficiency tests and the corresponding physics simulations (TRIM, GEANT IV). We describe several electronic boards which have been developed for various kinds of tests, firstly passive detection of {alpha}-particles from gaseous {sup 222}Rn in a large spectrum of activity concentrations. In a second stage, active collection of the daughter isotopes {sup 218}Po and {sup 214}Po was performed: these elements, appearing as attached on the aerosols present in air, are an important contribution to internal {alpha}-irradiation. The final electronic system, of only 10 cm size, includes four independent chips to ensure simultaneous detection of radon gas and its aerosols. An excellent linearity has been measured up to 80 kBq.m{sup -3} on the BACCARA bench of the IRSN at Saclay. A new generation chip is also studied. (author)

Comparison of analytical models and experimental results for single-event upset in CMOS SRAMs

International Nuclear Information System (INIS)

Mnich, T.M.; Diehl, S.E.; Shafer, B.D.

1983-01-01

In an effort to design fully radiation-hardened memories for satellite and deep-space applications, a 16K and a 2K CMOS static RAM were modeled for single-particle upset during the design stage. The modeling resulted in the addition of a hardening feedback resistor in the 16K remained tentatively unaltered. Subsequent experiments, using the Lawrence Berkeley Laboratories' 88-inch cyclotron to accelerate krypton and oxygen ions, established an upset threshold for the 2K and the 16K without resistance added, as well as a hardening threshold for the 16K with feedback resistance added. Results for the 16K showed it to be hardenable to the higher level than previously published data for other unhardened 16K RAMs. The data agreed fairly well with the modeling results; however, a close look suggests that modification of the simulation methodology is required to accurately predict the resistance necessary to harden the RAM cell

NV-CMOS HD camera for day/night imaging

Science.gov (United States)

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

A new CMOS Hall angular position sensor

Energy Technology Data Exchange (ETDEWEB)

Popovic, R.S.; Drljaca, P. [Swiss Federal Inst. of Tech., Lausanne (Switzerland); Schott, C.; Racz, R. [SENTRON AG, Zug (Switzerland)

2001-06-01

The new angular position sensor consists of a combination of a permanent magnet attached to a shaft and of a two-axis magnetic sensor. The permanent magnet produces a magnetic field parallel with the magnetic sensor plane. As the shaft rotates, the magnetic field also rotates. The magnetic sensor is an integrated combination of a CMOS Hall integrated circuit and a thin ferromagnetic disk. The CMOS part of the system contains two or more conventional Hall devices positioned under the periphery of the disk. The ferromagnetic disk converts locally a magnetic field parallel with the chip surface into a field perpendicular to the chip surface. Therefore, a conventional Hall element can detect an external magnetic field parallel with the chip surface. As the direction of the external magnetic field rotates in the chip plane, the output voltage of the Hall element varies as the cosine of the rotation angle. By placing the Hall elements at the appropriate places under the disk periphery, we may obtain the cosine signals shifted by 90 , 120 , or by any other angle. (orig.)

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

Science.gov (United States)

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

Science.gov (United States)

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

International Nuclear Information System (INIS)

Guo Rui; Zhang Haiying

2012-01-01

A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm 2 . The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply. (semiconductor integrated circuits)

Optimization of CMOS active pixels for high resolution digital radiography

International Nuclear Information System (INIS)

Kim, Young Soo

2007-02-01

CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n_d_i_f_f_u_s_i_o_n/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_s_u_b_s_t_r_a_t_e, n_d_i_f_f_u_s_i_o_n/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e) used in CMOS active pixels were fabricated

A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

International Nuclear Information System (INIS)

Ahmed, A.; Walkey, D.J.; Tarr, N.G.

1997-01-01

A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-microm conventional CMOS process with a sense capacitor area of 110 microm 2 . Tests carried out under vacuum conditions using a calibrated 241 Am alpha-particle source showed an output voltage swing of ≥2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles

Thermal-Diffusivity-Based Frequency References in Standard CMOS

NARCIS (Netherlands)

Kashmiri, S.M.

2012-01-01

In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

Future challenges in single event effects for advanced CMOS technologies

International Nuclear Information System (INIS)

Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

2010-01-01

SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

A Fully Symmetric and Completely Decoupled MEMS-SOI Gyroscope

Directory of Open Access Journals (Sweden)

Abdelhameed SHARAF

2011-04-01

Full Text Available This paper introduces a novel MEMS gyroscope that is capable of exciting the drive mode differentially. The structure also decouples the drive and sense modes via an intermediate mass and decoupling beams. Both drive and sense modes are fully differential enabling control over the zero-rate-output for the former and maximizing output sensitivity using a bridge circuit for the latter. Further, the structure is fully symmetric about the x- and y- axes which results in minimizing the temperature sensitivity problem. Complete analytical analysis based on the equations of motion was performed and verified using two commercially available finite element software packages. Results from both methods are in good agreement. The analysis of the sensor shows an electrical sensitivity of 1.14 (mV/(º/s. The gyroscope was fabricated using single mask and deep reactive ion etching. The measurement of the resonance frequency performed showing a good agreement with the analytical and numerical analysis.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

Science.gov (United States)

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

Application of CMOS charge-sensitive preamplifier in triple-GEM detector

International Nuclear Information System (INIS)

Lai Yongfang; Li Jin; Chinese Academy of Sciences, Beijing; Deng Zhi; Li Yulan; Liu Yinong; Li Yuanjing

2006-01-01

Among the various micro-pattern gas detectors (MPGD) that are available, the gas electron multiplier (GEM) detector is an attractive gas detector that has been used in particle physics experiments. However the GEM detector usually needs thousands of preamplifier units for its large number of micro-pattern readout strips or pads, which leads to considerable difficulties and complexities for front end electronics (FEE). Nowadays, by making use of complementary metal-oxide semiconductor (CMOS)-based application specific integrated circuit (ASIC), it is feasible to integrate hundreds of preamplifier units and other signal process circuits in a small-sized chip, which can be bound to the readout strips or pads of a micro-pattern particle detector (MPPD). Therefore, CMOS ASIC may provide an ideal solution to the readout problem of MPPD. In this article, a triple GEM detector is constructed and one of its readout strips is connected to a CMOS charge-sensitive preamplifier chip. The chip was exposed to an 55 Fe source of 5.9 kev X-ray, and the amplitude spectrum of the chip was tested, and it was found that the energy resolution was approximately 27%, which indicates that the chip can be used in triple GEM detectors. (authors)

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

Science.gov (United States)

2015-12-24

manufacturing today (namely, the 14nm FinFET silicon CMOS technology). The JPEG algorithm is selected as a motivational example since it is widely...TIFF images of a U.S. Air Force F-16 aircraft provided by the University of Southern California Signal and Image Processing Institute (SIPI) image...silicon CMOS technology currently in high volume manufac- turing today (the 14 nm FinFET silicon CMOS technology). The main contribution of this

Temperature Sensors Integrated into a CMOS Image Sensor

NARCIS (Netherlands)

Abarca Prouza, A.N.; Xie, S.; Markenhof, Jules; Theuwissen, A.J.P.

2017-01-01

In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

Energy Technology Data Exchange (ETDEWEB)

Rizzo, G., E-mail: rizzo@pi.infn.it [Università degli Studi di Pisa (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Comott, D. [Università degli Studi di Bergamo (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università degli Studi di Bergamo (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pavia (Italy); Fabbri, L.; Gabrielli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Giorgi, F.; Pellegrini, G.; Sbarra, C. [Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Berra, A.; Lietti, D.; Prest, M. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bevan, A. [School of Physics and Astronomy, Queen Mary, University of London, London E1 4NS (United Kingdom); Wilson, F. [STFC, Rutherford Appleton Laboratory, Harwell Oxford, Didcot OX11 0QX (United Kingdom); Beck, G. [School of Physics and Astronomy, Queen Mary, University of London, London E1 4NS (United Kingdom); and others

2013-08-01

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10–15μm in both coordinates, low material budget <1%X{sub 0}, and the ability to withstand a background hit rate of several tens of MHz/cm{sup 2}. Thanks to an intense R and D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Prospects for charge sensitive amplifiers in scaled CMOS

Science.gov (United States)

O'Connor, Paul; De Geronimo, Gianluigi

2002-03-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

Prospects for charge sensitive amplifiers in scaled CMOS

International Nuclear Information System (INIS)

O'Connor, Paul; De Geronimo, Gianluigi

2002-01-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

Science.gov (United States)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

International Nuclear Information System (INIS)

Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

2014-01-01

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

Directory of Open Access Journals (Sweden)

Kiyotaka Sasagawa

2010-12-01

Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

Energy Technology Data Exchange (ETDEWEB)

Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao, E-mail: tanxi@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2010-12-15

A two-stage differential linear power amplifier (PA) fabricated by 0.18 {mu}m CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm{sup 2}. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

International Nuclear Information System (INIS)

Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao

2010-01-01

A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm 2 . System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

On-Line High Dose-Rate Gamma Ray Irradiation Test of the CCD/CMOS Cameras

Energy Technology Data Exchange (ETDEWEB)

Cho, Jai Wan; Jeong, Kyung Min [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-05-15

In this paper, test results of gamma ray irradiation to CCD/CMOS cameras are described. From the CAMS (containment atmospheric monitoring system) data of Fukushima Dai-ichi nuclear power plant station, we found out that the gamma ray dose-rate when the hydrogen explosion occurred in nuclear reactors 1{approx}3 is about 160 Gy/h. If assumed that the emergency response robot for the management of severe accident of the nuclear power plant has been sent into the reactor area to grasp the inside situation of reactor building and to take precautionary measures against releasing radioactive materials, the CCD/CMOS cameras, which are loaded with the robot, serve as eye of the emergency response robot. In the case of the Japanese Quince robot system, which was sent to carry out investigating the unit 2 reactor building refueling floor situation, 7 CCD/CMOS cameras are used. 2 CCD cameras of Quince robot are used for the forward and backward monitoring of the surroundings during navigation. And 2 CCD (or CMOS) cameras are used for monitoring the status of front-end and back-end motion mechanics such as flippers and crawlers. A CCD camera with wide field of view optics is used for monitoring the status of the communication (VDSL) cable reel. And another 2 CCD cameras are assigned for reading the indication value of the radiation dosimeter and the instrument. In the preceding assumptions, a major problem which arises when dealing with CCD/CMOS cameras in the severe accident situations of the nuclear power plant is the presence of high dose-rate gamma irradiation fields. In the case of the DBA (design basis accident) situations of the nuclear power plant, in order to use a CCD/CMOS camera as an ad-hoc monitoring unit in the vicinity of high radioactivity structures and components of the nuclear reactor area, a robust survivability of this camera in such intense gamma-radiation fields therefore should be verified. The CCD/CMOS cameras of various types were gamma irradiated at a