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Sample records for fully differential cmos

  1. A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

    Institute of Scientific and Technical Information of China (English)

    Yu Changliang; Mao Luhong; Xiao Xindong; Xie Sheng; Zhang Shilin

    2009-01-01

    This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.

  2. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    Science.gov (United States)

    Xiaodong, Xu; Haigang, Yang; Tongqiang, Gao; Hongfeng, Zhang

    2013-07-01

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

  3. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2010-04-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  4. A Low-Voltage CMOS Buffer for RF Applications Based on a Fully-Differential Voltage-Combiner

    OpenAIRE

    Abdollahvand, S.; Santos-Tavares, R.; Goes, João

    2013-01-01

    Part 20: Electronics: RF Applications; International audience; This paper presents a new CMOS buffer circuit topology for radio-frequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source degeneration technique is used. The...

  5. Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    A fully differential complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) for 3.1-10.6 GHz ultra-wideband (UWB) communication systems is presented. The LNA adopts capacitive cross-coupling common-gate (CG) topology to achieve wideband input matching and low noise figure (NF). Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 μm CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an S11 of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point (IIP3) of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm2.

  6. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  7. Fully CMOS-compatible titanium nitride nanoantennas

    Science.gov (United States)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  8. Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

    Science.gov (United States)

    Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

    2008-11-01

    This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

  9. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  10. A novel fully differential telescopic operational transconductance amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Li Tianwang; Jiang Jinguang [Department of Integrated Circuits and Communication Software, International School of Software, Wuhan University, Wuhan 430079 (China); Ye Bo, E-mail: jgjiang95@yahoo.com.c [Faculty of Computer and Information Engineering, Shanghai University of Electric Power, Shanghai 200090 (China)

    2009-08-15

    A novel fully differential telescopic operational transconductance amplifier (OTA) is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18{mu}m CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced. (semiconductor integrated circuits)

  11. A 3μW fully-differential RF envelope detector for ultra-low power receivers

    NARCIS (Netherlands)

    Liempd, B.W.M. van; Vidojkovic, M.; Lont, M.; Zhou, C.; Harpe, P.; Milosevic, D.; Dolmans, G.

    2012-01-01

    A fully differential envelope detector (ED) operating at 2.4GHz is designed in 90nm CMOS technology. The new design uses the common-gate topology to deal with large common-mode input signals through first-order current cancellation. Thereby, a fully differential ultra-low power super-regenerative fr

  12. Fully Scaled 0.5 Micron CMOS Technology Using Variable Shaped Electron Beam Lithography

    Science.gov (United States)

    Coane, Philip; Rudeck, Paul; Wang, Li-Kong; Wilson, Alan; Hohn, Fritz

    1988-06-01

    Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpasssed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. In principle, variable shaped electron beam systems are capable of writing linewidths down to at least 0.1 micron. However, the successful application of sub-micron scaling principles to device fabrication involves an integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5 micron CMOS technology developed for VLSI appli-cations. Significant gains in both density and performance at reduced power supply levels are realized over previously reported 1.0 micron technology. The details of the integrated lithography strategy used to achieve these results are presented.

  13. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    Science.gov (United States)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  14. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  15. Two Stage Fully Differential Sample and Hold Circuit Using .18µm Technology

    Directory of Open Access Journals (Sweden)

    Dharmendra Dongardiye

    2014-05-01

    Full Text Available This paper presents a well-established Fully Differential sample & hold circuitry, implemented in 180-nm CMOS technology. In this two stage method the first stage give us very high gain and second stage gives large voltage swing. The proposed opamp provides 149MHz unity-gain bandwidth , 78 degree phase margin and a differential peak to peak output swing more than 2.4v. using the improved fully differential two stage operational amplifier of 76.7dB gain. Although the sample and hold circuit meets the requirements of SNR specifications.

  16. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

    Institute of Scientific and Technical Information of China (English)

    Liu Zhen; Jia Song; Wang Yuan; Ji Lijiu; Zhang Xing

    2009-01-01

    This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

  17. A fully integrated direct-conversion digital satellite tuner in 0.18μ m CMOS*

    Institute of Scientific and Technical Information of China (English)

    Chen Si; Yang Zengwang; Gu Mingliang

    2011-01-01

    A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz Lband, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 C integrated phase error.The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

  18. High Speed Boosted Cmos Differential Logic for Ripple Carry Adders

    Directory of Open Access Journals (Sweden)

    Meenu Roy,

    2014-01-01

    Full Text Available This paper describes a high speed boosted CMOS differential logic which is applicable in Ripple Carry Adders. The proposed logic operating with supply voltage approaching the MOS threshold voltage. The logic style improves switching speed by boosting the gate-source voltage of transistors along timing critical signal path. It allows a single boosting circuit to be shared by complementary outputs as a result the area overhead also minimizes. As compared to the conventional logic gates the EDP (energy delay product is improved. The test sets of logic gates and adders where designed in tsmc0.18μm of Mentor Graphics EDA tool. The experimental result for Ripple Carry Adders using the proposed logic style revealed that the addition time is reduced as compared with the conventional CMOS circuits.

  19. The fully differential top decay distribution

    Energy Technology Data Exchange (ETDEWEB)

    Aguilar-Saavedra, J.A. [Universidad de Granada, Departamento de Fisica Teorica y del Cosmos, Granada (Spain); Boudreau, J.; Mueller, J. [University of Pittsburgh, Department of Physics and Astronomy, Pittsburgh, PA (United States); Escobar, C. [CSIC-Universitat de Valencia, Instituto de Fisica Corpuscular, Paterna (Spain)

    2017-03-15

    We write down the four-dimensional fully differential decay distribution for the top quark decay t → Wb → lνb. We discuss how its eight physical parameters can be measured, either with a global fit or with the use of selected one-dimensional distributions and asymmetries. We give expressions for the top decay amplitudes for a general tbW interaction, and show how the untangled measurement of the two components of the fraction of longitudinal W bosons - those with b quark helicities of 1/2 and -1/2, respectively - could improve the precision of a global fit to the tbW vertex. (orig.)

  20. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

    Science.gov (United States)

    Yiqi, Mao; Tongqiang, Gao; Xiaodong, Xu; Haigang, Yang; Xinxia, Cai

    2016-09-01

    A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm2. It achieves a sensitivity of -80 dBm for 10-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW. Project supported by the National Basic Research Program of China (No. 2014CB744600) and the National Natural Science Foundation of China (No. 61474120).

  1. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    Directory of Open Access Journals (Sweden)

    Virgilio Valente

    2016-07-01

    Full Text Available This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR channels and four voltage-readout (VR channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis.

  2. An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

    Science.gov (United States)

    DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

    2016-01-01

    This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

  3. SEMICONDUCTOR INTEGRATED CIRCUITS: A novel fully differential telescopic operational transconductance amplifier

    Science.gov (United States)

    Tianwang, Li; Bo, Ye; Jinguang, Jiang

    2009-08-01

    A novel fully differential telescopic operational transconductance amplifier (OTA) is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.

  4. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    NARCIS (Netherlands)

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche ph

  5. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    NARCIS (Netherlands)

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche ph

  6. Biquadratic Filter Applications Using a Fully-Differential Active-Only Integrator

    Directory of Open Access Journals (Sweden)

    H. A. Yildiz

    2013-04-01

    Full Text Available A new class of active filters, real active-only filters is described and possible implementation issues of these filters are discussed. To remedy these issues, a fully-differential active-only integrator block built around current controlled current conveyors is presented. The integration frequency of the proposed circuit is adjustable over a wide frequency range. As an application, a real active-only filter based on the classical two-integrator loop topology is presented and designed. The feasibility of this filter in a 0.35µm CMOS process is verified through SPECTRE simulation program in the CADENCE design tool.

  7. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  8. Analysis of the high-speed polysilicon photodetector in fully standard CMOS technology

    NARCIS (Netherlands)

    Radovanović, S.; Annema, A.J.; Nauta, B.

    2003-01-01

    A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) b

  9. A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

    Energy Technology Data Exchange (ETDEWEB)

    Jin Boshi; Li Lewei; Wu Qun; Yang Guohui; Zhang Kuang, E-mail: boshijin@rdamicro.com [Department of Electronic and Communications Engineering, Harbin Institute of Technology, Harbin 150001 (China)

    2011-05-15

    A transformer-based CMOS power amplifier (PA) is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter. The third harmonic of the power stage and driver stage can be cancelled out in a specific power region. The two-stage PA fabricated in a standard 0.18-{mu}m CMOS process delivers 27.5 dBm with 27% PAE at the 1-dB compression point (P{sub 1dB}) and offers 21 dB gain. The PA achieves 5.5 % EVM and meets the spectrum mask at 20.5 dBm average power. Another conventional PA with a zero-cross-point of g{sub m3} bias is also fabricated and compared to prove its good linearity and efficiency. (semiconductor devices)

  10. Fully Integrated, Low Drop-Out Linear Voltage Regulator in 180 nm CMOS

    DEFF Research Database (Denmark)

    Yosef-Hay, Yoni; Larsen, Dennis Øland; Llimos Muntal, Pere

    2017-01-01

    . The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0-100 pF capacitive load. The design has been taped out in a 0.18 µm CMOS process. The proposed regulator has a low component count, area of 0.012 mm2 and is suitable for system-on-chip integration...

  11. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  12. Fully differential cross sections for heavy particle impact ionization

    Energy Technology Data Exchange (ETDEWEB)

    McGovern, M; Walters, H R J [Department of Applied Mathematics and Theoretical Physics, Queen' s University, Belfast BT7 1NN (United Kingdom); Assafrao, D; Mohallem, J R [Laboratorio de Atomos e Moleculas Especiais, Departamento de Fisica, ICEx, Universidade Federal de Minas Gerais, P.O Box 702, 30123-970 Belo Horizonte, MG (Brazil); Whelan, Colm T, E-mail: mmcgovern06@qub.ac.u [Department of Physics, Old Dominion University, Norfolk, VA 23529-0116 (United States)

    2009-11-15

    We describe a procedure for extracting fully differential ionization cross sections from an impact parameter coupled pseudostate treatment of the collision. Some examples from antiproton impact ionization of atomic Hydrogen are given.

  13. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  14. Active inductor based fully integrated CMOS transmit/ receive switch for 2.4 GHz RF transceiver

    Directory of Open Access Journals (Sweden)

    Mohammad A.S. Bhuiyan

    2016-06-01

    Full Text Available Modern Radio Frequency (RF transceivers cannot be imagined without high-performance (Transmit/Receive T/R switch. Available T/R switches suffer mainly due to the lack of good trade-off among the performance parameters, where high isolation and low insertion loss are very essential. In this study, a T/R switch with high isolation and low insertion loss performance has been designed by using Silterra 0.13µm CMOS process for 2.4GHz ISM band RF transceivers. Transistor aspect ratio optimization, proper gate bias resistance, resistive body floating and active inductor-based parallel resonance techniques have been implemented to achieve better trade-off. The proposed T/R switch exhibits 0.85dB insertion loss and 45.17dB isolation in both transmit and receive modes. Moreover, it shows very competitive values of power handling capability (P1dB and linearity (IIP3 which are 11.35dBm and 19.60dBm, respectively. Due to avoiding bulky inductor and capacitor, the proposed active inductor-based T/R switch became highly compact occupying only 0.003mm2 of silicon space; which will further trim down the total cost of the transceiver. Therefore, the proposed active inductor-based T/R switch in 0.13µm CMOS process will be highly useful for the electronic industries where low-power, high-performance and compactness of devices are the crucial concerns.

  15. Demonstration of a fully differential VGA chip with small THD for ECG acquisition system

    Science.gov (United States)

    Gongli, Xiao; Yuliang, Qin; Weilin, Xu; Baolin, Wei; Jihai, Duan; Xueming, Wei

    2015-10-01

    We present both a theoretical and experimental demonstration of a fully differential variable gain amplifier (VGA) with small total harmonic distortion (THD) for an electrocardiogram (ECG) acquisition system. Capacitive feedback technology is adopted to reduce the nonlinearity of VGA. The fully differential VGA has been fabricated in SMIC 0.18-μm CMOS process, and it only occupies 0.11 mm2. The measurements are in good agreement with simulation results. Experimental results show that the gain of VGA changes from 6.17 to 43.75 dB with a gain step of 3 dB. The high-pass corner frequency and low-pass corner frequency are around 0.22 Hz and 7.9 kHz, respectively. For each gain configuration, a maximal THD of 0.13% is obtained. The fully differential VGA has a low THD and its key performance parameters are well satisfied with the demands of ECG acquisition system application in the UWB wireless body area network. Project supported by the National Natural Science Foundation of China (Nos. 61264001, 61465004, 61161003, 61166004), the Guangxi Natural Science Foundation (Nos. 2013GXNSFAA019333, 2013GXNSFAA019338), the Science and Technology Research Key Project of Guangxi Department of Education (No. 2013ZD026), and the Innovation Project of GUET Graduate Education (No. GDYCSZ201457).

  16. A 9 MHz-2.4 GHz Fully Integrated Transceiver IC for a Microfluidic-CMOS Platform Dedicated to Miniaturized Dielectric Spectroscopy.

    Science.gov (United States)

    Bakhshiani, Mehran; Suster, Michael A; Mohseni, Pedram

    2015-12-01

    This paper presents a fully integrated transceiver IC as part of a self-sustained, microfluidic-CMOS platform for miniaturized dielectric spectroscopy (DS) from MHz to GHz. Fabricated in AMS 0.35 μm 2P/4M RF CMOS, the transmitter (TX) part of the IC generates a single-tone sinusoidal signal with frequency tunability in the range of ~ 9 MHz-2.4 GHz to excite a three-dimensional (3D), parallel-plate, capacitive sensor with a floating electrode and 9 μL microfluidic channel for sample delivery. With a material-under-test (MUT) loaded into the sensor, the receiver (RX) part of the IC employs broadband frequency response analysis (bFRA) methodology to measure the amplitude and phase of the RF excitation signal after transmission through the sensor. A one-time, 6-point sensor calibration algorithm then extracts both the real and imaginary parts of the MUT complex permittivity, ϵr, from IC measurements of the sensor transmission characteristics in the voltage domain. The "sensor + IC" is fully capable of differentiating among de-ionized (DI) water, phosphate-buffered saline (PBS), and alcoholic beverages in tests conducted at four excitation frequencies of ∼ 50 MHz , 500 MHz, 1.5 GHz, and 2.4 GHz generated by the TX. Moreover, permittivity readings of PBS by the sensor interfaced with the IC at six excitation frequencies in the range of ~ 50 MHz-2.4 GHz are in excellent agreement (rms error of 1.7% (real) and 7.2% (imaginary)) with those from bulk-solution reference measurements by commercial benchtop equipment. The total power consumption of the IC is with 1.5 V (analog) and 3.3 V (digital) supplies.

  17. The Fully-Differential Quark Beam Function at NNLO

    CERN Document Server

    Gaunt, Jonathan R

    2014-01-01

    We present the first calculation of a fully-unintegrated parton distribution (beam function) at next-to-next-to-leading order (NNLO). We obtain the fully-differential beam function for quark-initiated processes by matching it onto standard parton distribution functions (PDFs) at two loops. The fully-differential beam function is a universal ingredient in resummed predictions of observables probing both the virtuality as well as the transverse momentum of the incoming quark in addition to its usual longitudinal momentum fraction. For such double-differential observables our result is an important contribution to the resummation of large logarithms related to collinear initial-state radiation (ISR) through N3LL.

  18. A fully integrated W-band push-push CMOS VCO with low phase noise and wide tuning range.

    Science.gov (United States)

    Wang, To-Po

    2011-07-01

    A circuit topology suitable for a low-phase-noise wide-tuning-range push-push voltage-controlled oscillator (VCO) is proposed in this paper. By applying varactors connected between drain and source terminations of the cross-coupled pair, the tuning range is effectively increased and the phase noise is improved. Moreover, a small capacitor is inserted between the VCO core and testing buffer to reduce loading effects on the VCO core. Furthermore, the enhanced second-harmonic output signal is extracted at middle of the varactors, leading to the elimination of RF choke at VCO's second-harmonic output port and a reduced chip size. Based on the proposed architecture, this VCO fabricated in 0.18-μm CMOS exhibits a measured 6.35% tuning range. Operating at a supply voltage of 1.2 V, the VCO core consumes 7.5-mW dc power, and the measured phase noise is -75 dBc/Hz and -91.5 dBc/Hz at 100-kHz and 1-MHz offsets from the 77.8-GHz carrier, respectively. Compared with previously published silicon-based VCOs over 70 GHz, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power consumption, leading to a superior figure of merit (FOM), and better figure of merit considering the tuning range (FOM(T)). In addition, this fully integrated VCO also demonstrates the highest operation frequency among previously published 0.18-μm CMOS VCOs.

  19. Backward stochastic differential equations from linear to fully nonlinear theory

    CERN Document Server

    Zhang, Jianfeng

    2017-01-01

    This book provides a systematic and accessible approach to stochastic differential equations, backward stochastic differential equations, and their connection with partial differential equations, as well as the recent development of the fully nonlinear theory, including nonlinear expectation, second order backward stochastic differential equations, and path dependent partial differential equations. Their main applications and numerical algorithms, as well as many exercises, are included. The book focuses on ideas and clarity, with most results having been solved from scratch and most theories being motivated from applications. It can be considered a starting point for junior researchers in the field, and can serve as a textbook for a two-semester graduate course in probability theory and stochastic analysis. It is also accessible for graduate students majoring in financial engineering.

  20. A multi-channel fully differential programmable integrated circuit for neural recording application

    Science.gov (United States)

    Yun, Gui; Xu, Zhang; Yuan, Wang; Ming, Liu; Weihua, Pei; Kai, Liang; Suibiao, Huang; Bin, Li; Hongda, Chen

    2013-10-01

    A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.

  1. Design and noise analysis of a fully-differential charge pump for phase-locked loops

    Institute of Scientific and Technical Information of China (English)

    Gong Zhichao; Lu Lei; Liao Youchun; Tang Zhangwen

    2009-01-01

    A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1-2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 μm process. The measured output reference spur is -64 dBc to -69 dBc. The in-band and out-band phase noise is -95 dBc/Hz at 3 kHz frequency offset and -123 dBc/Hz at 1 MHz frequency offset respectively.

  2. Design and Analysis of Fully Integrated Differential VCOs

    Directory of Open Access Journals (Sweden)

    M. Prochaska

    2005-01-01

    Full Text Available Oscillators play a decisive role for electronic equipment in many fields - like communication, navigation or data processing. Especially oscillators are key building blocks in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper we present an analytic analysis of the steady state oscillation of integrated differential VCOs which is based on a nonlinear model of the oscillator. The outcomes of this are design formulas for the amplitude as well as the stability of the oscillator which take the nonlinearity of the circuit into account.

  3. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2013-08-01

    Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

  4. Fully Digital Chaotic Differential Equation-based Systems And Methods

    KAUST Repository

    Radwan, Ahmed Gomaa Ahmed

    2012-09-06

    Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

  5. Fully differential NLO predictions for the rare muon decay

    Science.gov (United States)

    Pruna, G. M.; Signer, A.; Ulrich, Y.

    2017-02-01

    Using the automation program GoSam, fully differential NLO corrections were obtained for the rare decay of the muon μ → eν ν bar ee. This process is an important Standard Model background to searches of the Mu3e Collaboration for lepton-flavor violation, as it becomes indistinguishable from the signal μ → 3 e if the neutrinos carry little energy. With our NLO program we are able to compute the branching ratio as well as custom-tailored observables for the experiment. With minor modifications, related decays of the tau can also be computed.

  6. Fully differential NLO predictions for the rare muon decay

    Directory of Open Access Journals (Sweden)

    G.M. Pruna

    2017-02-01

    Full Text Available Using the automation program GoSam, fully differential NLO corrections were obtained for the rare decay of the muon μ→eνν¯ee. This process is an important Standard Model background to searches of the Mu3e Collaboration for lepton-flavor violation, as it becomes indistinguishable from the signal μ→3e if the neutrinos carry little energy. With our NLO program we are able to compute the branching ratio as well as custom-tailored observables for the experiment. With minor modifications, related decays of the tau can also be computed.

  7. Differential Rotation and Magnetism in Simulations of Fully Convective Stars

    CERN Document Server

    Browning, Matthew

    2010-01-01

    Stars of sufficiently low mass are convective throughout their interiors, and so do not possess an internal boundary layer akin to the solar tachocline. Because that interface figures so prominently in many theories of the solar magnetic dynamo, a widespread expectation had been that fully convective stars would exhibit surface magnetic behavior very different from that realized in more massive stars. Here I describe how recent observations and theoretical models of dynamo action in low-mass stars are partly confirming, and partly confounding, this basic expectation. In particular, I present the results of 3--D MHD simulations of dynamo action by convection in rotating spherical shells that approximate the interiors of 0.3 solar-mass stars at a range of rotation rates. The simulated stars can establish latitudinal differential rotation at their surfaces which is solar-like at ``rapid'' rotation rates (defined within) and anti-solar at slower rotation rates; the differential rotation is greatly reduced by feed...

  8. Matching fully differential NNLO calculations and parton showers

    Energy Technology Data Exchange (ETDEWEB)

    Alioli, Simone; Bauer, Christian W.; Berggren, Calvin; Walsh, Jonathan R.; Zuberi, Saba [California Univ., Berkeley, CA (United States). Ernest Orlando Lawrence Berkeley National Laboratory; Tackmann, Frank J. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2013-11-15

    We present a general method to match fully differential next-to-next-to-leading (NNLO) calculations to parton shower programs. We discuss in detail the perturbative accuracy criteria a complete NNLO+PS matching has to satisfy. Our method is based on consistently improving a given NNLO calculation with the leading-logarithmic (LL) resummation in a chosen jet resolution variable. The resulting NNLO+LL calculation is cast in the form of an event generator for physical events that can be directly interfaced with a parton shower routine, and we give an explicit construction of the input ''Monte Carlo cross sections'' satisfying all required criteria. We also show how other proposed approaches naturally arise as special cases in our method.

  9. Matching Fully Differential NNLO Calculations and Parton Showers

    CERN Document Server

    Alioli, Simone; Berggren, Calvin; Tackmann, Frank J; Walsh, Jonathan R; Zuberi, Saba

    2013-01-01

    We present a general method to match fully differential next-to-next-to-leading (NNLO) calculations to parton shower programs. We discuss in detail the perturbative accuracy criteria a complete NNLO+PS matching has to satisfy. Our method is based on consistently improving a given NNLO calculation with the leading-logarithmic (LL) resummation in a chosen jet resolution variable. The resulting NNLO$+$LL calculation is cast in the form of an event generator for physical events that can be directly interfaced with a parton shower routine, and we give an explicit construction of the input "Monte Carlo cross sections" satisfying all required criteria. We also show how other proposed approaches naturally arise as special cases in our method.

  10. A Fully Differential Interface Circuit of Closed-loop Accelerometer with Force Feedback Linearization

    Institute of Scientific and Technical Information of China (English)

    HongLin Xu; HongNa Liu; Chong He; Liang Yin; XiaoWei Liu

    2014-01-01

    In this paper, a fifth-order fully differential interface circuit ( IC) is presented to improve the noise performance for micromechanical sigma-delta (Σ-Δ) accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling ( CDS) technique to decrease 1/f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range ( DR) . The layout of the IC is implemented in a standard 0�6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about -140 dBV/Hz1/2 at low frequency. The sensitivity is 2.5 V/g and the nonlinearity is 0�11%. The self-test function is achieved with 98�2 dB third-order harmonic distortion detection based on the electrostatic force feedback linearization.

  11. A Low Phase Noise Fully Monolithic 6 GHz Differential Coupled NMOS LC-VCO

    Science.gov (United States)

    Moalla, Dorra Mellouli; Cordeau, David; Mnif, Hassene; Paillot, Jean-Marie; Loulou, Mourad

    2016-01-01

    A fully monolithic 6 GHz low-phase noise Voltage-Controlled-Oscillator (VCO) is presented in this paper. It consists in two LC-NMOS differential VCOs coupled through a resistive network and is implemented on a 0.25 µm BiCMOS SiGe process. This proposed integrated VCO can be used also for phased-array applications to steer the beam over the entire spatial range. In this case, the radiation pattern of the phased antenna array is steered in a particular direction by establishing a constant phase progression in the oscillator chain which can be obtained by detuning the free-running frequencies of the two oscillators in the array. At 2.5 V power supply voltage and a power dissipation of 62.5 mW, the coupled VCO array features a measured worst case phase noise of -102.4 dBc/Hz and -125.64 dBc/Hz at 100 kHz and 1 MHz frequency offset respectively from a 6 GHz carrier. The tuning range is about 400 MHz, from 5.85 to 6.25 GHz, for a tuning voltage varying from 0 to 2.5 V.

  12. Novel Low Voltage CMOS Current Controlled Floating Resistor Using Differential Pair

    Directory of Open Access Journals (Sweden)

    S. A. Tekin

    2013-06-01

    Full Text Available In this paper, a low voltage CMOS current controlled floating resistor which is convenient for integrated circuit implementation is designed by using differential pair. The proposed resistor has a simple circuit structure and low power dissipation. This circuit is required ± 0.75 V as a power supply. The basic advantages of this circuit are wide tuning range of the resistance value, satisfied frequency performance and worthwhile dynamic range. As well as the proposed circuit has floating structure, it is able to be used both positive and negative resistor. The performances of the proposed circuit are simulated with SPICE to justify the presented theory.

  13. Design of 2.1 GHz CMOS Low Noise Amplifier

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

  14. A fully on-chip three-terminal switched-capacitor DC-DC converter for low-voltage CMOS LSIs

    Science.gov (United States)

    Kojima, Yuta; Hirose, Tetsuya; Tsubaki, Keishi; Ozaki, Toshihiro; Asano, Hiroki; Kuroki, Nobutaka; Numa, Masahiro

    2016-04-01

    In this paper, we present a fully on-chip switched-capacitor DC-DC converter for low-voltage CMOS LSIs. The converter has three terminals of input, ground, and output, by developing control circuits with fully on-chip configuration. We employ an ultra low-power nanoampere bias current and voltage reference circuit to achieve ultra low-power dissipation of control circuits. It enables us to realize a highly efficient power conversion circuit at light-load-current applications. The converter achieves highly efficient and robust voltage conversion using a pulse frequency modulation control circuit and a start-up/fail-safe circuit. Measurement results demonstrated that the converter can convert a 3.0 V input into 1.2 V output successfully. The start-up and fail-safe operations were confirmed through the measurement. The efficiency was more than 50% in the range of 2-6 µA load current.

  15. A Differential CMOS Common-Gate LNA Linearized by Cross-Coupled Post Distortion Technique

    Science.gov (United States)

    Guo, Benqing; Yang, Guomin; Bin, Xiexian

    2014-05-01

    A linearized differential common-gate CMOS low noise amplifier is proposed. The linearity is improved by a cross-coupled post distortion technique, employing auxiliary PMOS transistors in weak inversion region to cancel the third-order nonlinear currents of common-gate LNA and impair the second-order nonlinear currents of that. The negative conductance characteristic of cross-coupled auxiliary PMOS transistors improves the gain while the resulted NF is little affected. Furthermore, noise contribution and linearity deterioration from the cascode stage is eliminated by an inductor resonating with the parasitic capacitance observed at the source net of the cascode transistor. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 dB and 1.4 dB improvements in the designed frequency band, respectively. The noise figure of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

  16. A Comparison Theorem for Solution of the Fully Coupled Backward Stochastic Differential Equations

    Institute of Scientific and Technical Information of China (English)

    郭子君; 吴让泉

    2004-01-01

    The comparison theorems of solutions for BSDEs in fully coupled forward-backward stochastic differential equations (FBSDEs) are studied in this paper, here in the fully coupled FBSDEs the forward SDEs are the same structure.

  17. Differentiability at lateral boundary for fully nonlinear parabolic equations

    Science.gov (United States)

    Ma, Feiyao; Moreira, Diego R.; Wang, Lihe

    2017-09-01

    For fully nonlinear uniformly parabolic equations, the first derivatives regularity of viscosity solutions at lateral boundary is studied under new Dini type conditions for the boundary, which is called Reifenberg Dini conditions and is weaker than usual Dini conditions.

  18. Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

    Science.gov (United States)

    Zargham, Meysam; Gulak, P Glenn

    2015-04-01

    Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

  19. Integrated Circuit of CMOS DC-DC Buck Converter with Differential Active Inductor

    Directory of Open Access Journals (Sweden)

    Kaoutar Elbakkar

    2011-11-01

    Full Text Available In this paper, we propose a new design of DC-DC buck converter (BC, which the spiral inductor is replaced by a differential gyrator with capacitor load (gyrator-C implemented in 0.18um CMOS process. The gyrator-C transforms the capacitor load (which is the parasitic capacitor of MOSFETS to differential active inductor DAI. The low-Q value of DAI at switching frequency of converter (few hundred kHz is boosted by adding a negative impedance converter (NIC. The transistor parameters of DAI and NIC can be properly chosen to achieve the desirable value of equivalent inductance L (few tens H, and the maximum-Q value at the switching frequency, and thus the efficiency of converter is improved. Experimental results show that the converter supplied with an input voltage of 1V, provides an output voltage of 0.74V and output ripple voltage of 10mV at 155 kHz and Q-value is maximum (#8776;4226 at this frequency.

  20. The fully differential hadronic production of a Higgs boson via bottom quark fusion at NNLO

    CERN Document Server

    Buehler, Stephan; Lazopoulos, Achilleas; Mueller, Romain

    2012-01-01

    The fully differential computation of the hadronic production cross section of a Higgs boson via bottom quarks is presented at NNLO in QCD. Several differential distributions with their corresponding scale uncertainties are presented for the 8 TeV LHC. This is the first application of the method of non-linear mappings for NNLO differential calculations at hadron colliders.

  1. A 1.0 V differential VCO in 0.13μm CMOS technology*

    Institute of Scientific and Technical Information of China (English)

    Cao Shengguo; Han Kefeng; Tan Xi; Yan Na; Min Hao

    2011-01-01

    A differential complementary LC voltage controlled oscillator (VCO) with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS (I-MOS) capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 × 0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6.35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.

  2. Asteroid 4 Vesta: A Fully Differentiated Dwarf Planet

    Science.gov (United States)

    Mittlefehldt, David

    2014-01-01

    One conclusion derived from the study of meteorites is that some of them - most irons, stony irons, some achondrites - hail from asteroids that were heated to the point where metallic cores and basaltic crusts were formed. Telescopic observations show that there remains only one large asteroid with a basaltic crust, 4 Vesta; present day mean radius 263 km. The largest clan of achondrites, the howardite, eucrite and diogenite (HED) meteorites, represent the crust of their parent asteroid. Diogenites are cumulate harzburgites and orthopyroxenites from the lower crust whilst eucrites are cumulate gabbros, diabases and basalts from the upper crust. Howardites are impact-engendered breccias of diogenites and eucrites. A strong case can be made that HEDs are derived from Vesta. The NASA Dawn spacecraft orbited Vesta for 14 months returning data allowing geological, mineralogical, compositional and geophysical interpretations of Vesta's surface and structure. Combined with geochemical and petrological observations of HED meteorites, differentiation models for Vesta can be developed. Proto-Vesta probably consisted of primitive chondritic materials. Compositional evidence, primarily from basaltic eucrites, indicates that Vesta was melted to high degree (>=50%) which facilitated homogenization of the silicate phase and separation of immiscible Fe,Ni metal plus Fe sulphide into a core. Geophysical models based on Dawn data support a core of 110 km radius. The silicate melt vigorously convected and initially followed a path of equilibrium crystallization forming a harzburgitic mantle, possibly overlying a dunitic restite. Once the fraction of crystals was sufficient to cause convective lockup, the remaining melt collected between the mantle and the cool thermal boundary layer. This melt undergoes fractional crystallization to form a dominantly orthopyroxenite (diogenite) lower crust. The initial thermal boundary layer of primitive chondritic material is gradually replaced by a

  3. FULLY COUPLED FORWARD-BACKWARD STOCHASTIC DIFFERENTIAL EQUATIONS WITH GENERAL MARTINGALE

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The article first studies the fully coupled Forward-Backward Stochastic Differential Equations (FBSDEs) with the continuous local martingale. The article is mainly divided into two parts. In the first part, it considers Backward Stochastic Differential Equations (BSDEs) with the continuous local martingale. Then, on the basis of it, in the second part it considers the fully coupled FBSDEs with the continuous local martingale.It is proved that their solutions exist and are unique under the monotonicity conditions.

  4. SEMICONDUCTOR INTEGRATED CIRCUITS: A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    Science.gov (United States)

    Jingchao, Wang; Chun, Zhang; Zhihua, Wang

    2010-08-01

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU—in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 × 3.8 mm2 including pads.

  5. Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback

    DEFF Research Database (Denmark)

    Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre

    A fully differential rail-to-rail Operational Transconductance Amplifier (OTA) with improved DC-gain and reduced power consumption is proposed in this paper. By using the adaptive biasing circuit and two differential inputs, a low stand-by current can be obtained together with reduced power consu...

  6. Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback

    DEFF Research Database (Denmark)

    Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre

    A fully differential rail-to-rail Operational Transconductance Amplifier (OTA) with improved DC-gain and reduced power consumption is proposed in this paper. By using the adaptive biasing circuit and two differential inputs, a low stand-by current can be obtained together with reduced power...... consumption. The DC-gain of the proposed OTA is improved by adding a partial feedback loop. A Common-Mode Feedback (CMFB) circuit is required for fully differential rail-to-rail operation. Simulations show that the OTA topology has a low stand-by power consumption of 96μW and a high FoM of 3.84 [(V...

  7. A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2010-03-15

    Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

  8. A fully differential OTA with dynamic offset cancellation in 28nm FD-SOI process

    Science.gov (United States)

    Jaworski, Zbigniew

    2016-12-01

    This papers presents a classic fully differential operational transconductance amplifier (FDOTA) implemented in industrial 28 nm FD-SOI (Fully-Depleted SOI) technology. A novel approach to minimized the FDOTA offset voltage is proposed. The solution employs the unique feature of FD-SOI technology - back-gate biasing - combined with modern compensation methodology. The proposed method results in considerable design overhead. However, this offset cancellation approach is very effective and allows to improve FDOTA performance when classic techniques reach their limits.

  9. A CMOS current-mode operational amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1993-01-01

    A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...... current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2...

  10. CMOS Current-mode Operational Amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1992-01-01

    A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...... current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-range ±700¿A) and a (theoretically) unlimited slew-rate. The amplifier is realized in a standard CMOS 2...

  11. Fixed-gain CMOS differential amplifiers with no external feedback for a wide temperature range

    Science.gov (United States)

    Michal, Vratislav; Klisnick, Geoffroy; Sou, Gérard; Redon, Michel; Kreisler, Alain J.; Dégardin, Annick F.

    2009-11-01

    We present original CMOS amplifiers designed for the DC to 10 MHz frequency range and operating in the 70-380 K temperature range. Aimed applications concern readout circuitry to be associated with THz bolometric pixels (either high- Tc superconducting or uncooled semiconducting), which require accuracy, low noise and low power consumption. Two designs are described that both exhibit high fixed-gain (40 dB) in a feedback-free architecture, which is based on a new low-transconductance composite transistor for an accurate control of this gain. Both amplifiers have been realized in a regular 0.35 μm CMOS process and tested in the 4.2-380 K temperature range, exhibiting good agreement between designed and measured characteristics.

  12. Premature birth is associated with not fully differentiated contractile smooth muscle cells in human umbilical artery.

    Science.gov (United States)

    Roffino, S; Lamy, E; Foucault-Bertaud, A; Risso, F; Reboul, R; Tellier, E; Chareyre, C; Dignat-George, F; Simeoni, U; Charpiot, P

    2012-06-01

    Smooth muscle cells (SMCs) participate to the regulation of peripheral arterial resistance and blood pressure. To assume their function, SMCs differentiate throughout the normal vascular development from a synthetic phenotype towards a fully differentiated contractile phenotype by acquiring a repertoire of proteins involved in contraction. In human fetal muscular arteries and umbilical arteries (UAs), no data are available regarding the differentiation of SMCs during the last trimester of gestation. The objective of this study was to characterize the phenotype of SMCs during this gestation period in human UAs. We investigated the phenotype of SMCs in human UAs from very preterm (28-31 weeks of gestation), late preterm (32-35 weeks) and term (37-41 weeks) newborns using biochemical and immunohistochemical detection of α-actin, smooth muscle myosin heavy chain, smoothelin, and non-muscle myosin heavy chain. We found that the number of SMCs positive for smoothelin in UAs increased with gestational age. Western blot analysis revealed a higher content of smoothelin in term compared to very preterm UAs. These results show that SMCs in human UAs gradually acquire a fully differentiated contractile phenotype during the last trimester of gestation and thus that premature birth is associated with not fully differentiated contractile SMCs in human UAs. Copyright © 2012 Elsevier Ltd. All rights reserved.

  13. Noise analysis and characterization of a full differential CMOS interface circuit for capacitive closed-loop micro-accelerometer

    Institute of Scientific and Technical Information of China (English)

    LIU Xiao-wei; LI Hai-tao; YIN Liang; CHEN Wei-ping; SUO Chun-guang; ZHOU Zhi-ping

    2010-01-01

    To achieve a high precision capacitive closed-loop micro-accelerometer,a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit.This circuit consists of a balance-bridge module,a charge sensitive amplifier,a correlated-double-sampling module,and a logic timing control module.A special two-path feedback circuit configuration was given to improve the system linearity.The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit's noise,speed and accuracy.A detailed design method was given for this tradeoff.The noise performance optimized circuit has a noise root spectral density of 1.0 μV/√Hz,equivalent to rms noise root spectral density of1.63 μg/√Hz.Therefore,the sensor' s Brown noise becomes the main noise source in this design.This circuit is designed with 0.5 μm n-well CMOS process.Under a ± 5 V supply,the Hspice simulation shows that the system sensitivity achieves 0.616 V/g,the system offset is as low as 1.456 mV,the non-linearity is below0.03%,and the system linear range achieves ±5 g.

  14. t-SURFF: Fully Differential Two-Electron Photo-Emission Spectra

    CERN Document Server

    Scrinzi, Armin

    2012-01-01

    The time dependent surface flux (t-SURFF) method is extended to single and double ionization of two electron systems. Fully differential double emission spectra by strong pulses at extreme UV and infrared wave length are calculated using simulation volumes that only accommodate the effective range of the atomic binding potential and the quiver radius of free electrons in the external field. For a model system we find pronounced dependence of shake-up and non-sequential double ionization on phase and duration of the laser pulse. Extension to fully three-dimensional calculations is discussed.

  15. Fully Differential Vector-Boson-Fusion Higgs Production at Next-to-Next-to-Leading Order.

    Science.gov (United States)

    Cacciari, Matteo; Dreyer, Frédéric A; Karlberg, Alexander; Salam, Gavin P; Zanderighi, Giulia

    2015-08-21

    We calculate the fully differential next-to-next-to-leading-order (NNLO) corrections to vector-boson fusion (VBF) Higgs boson production at proton colliders, in the limit in which there is no cross talk between the hadronic systems associated with the two protons. We achieve this using a new "projection-to-Born" method that combines an inclusive NNLO calculation in the structure-function approach and a suitably factorized next-to-leading-order VBF Higgs plus three-jet calculation, using appropriate Higgs plus two-parton counterevents. An earlier calculation of the fully inclusive cross section had found small NNLO corrections, at the 1% level. In contrast, the cross section after typical experimental VBF cuts receives NNLO contributions of about (5-6)%, while differential distributions show corrections of up to (10-12)% for some standard observables. The corrections are often outside the next-to-leading-order scale-uncertainty band.

  16. Fully differential cross sections for the single ionization of He by C{sup 6+} ions

    Energy Technology Data Exchange (ETDEWEB)

    Colgan, J [Theoretical Division, Los Alamos National Laboratory, NM 87545 (United States); Pindzola, M S; Robicheaux, F [Department of Physics, Auburn University, Auburn, AL 36849 (United States); Ciappina, M F [ICFO-Institut de Ciences Fotoniques, 08860 Castelldefels (Barcelona) (Spain)

    2011-09-14

    We present fully differential cross sections for the single ionization of He by C{sup 6+} ions. A time-dependent close-coupling approach is used to describe the two-electron wavefunction in the field of the projectile for a range of impact parameters, and a Fourier transform approach is used to extract fully differential cross sections for a specific momentum transfer. Our calculations are compared to the measurements of Schulz et al (2003 Nature 422 48) and we find very good agreement in the scattering plane and good qualitative agreement in the perpendicular plane. In particular, our calculations in the perpendicular plane find a similar 'double-peak' structure in the angular distributions to those seen experimentally. We also discuss the various checks made on our calculations by comparing to a one-electron time-dependent calculation.

  17. Design and characterization of a fully differential MEMS accelerometer fabricated using MetalMUMPs technology.

    Science.gov (United States)

    Qu, Peng; Qu, Hongwei

    2013-05-02

    This paper presents a fully differential single-axis accelerometer fabricated using the MetalMUMPs process. The unique structural configuration and common-centriod wiring of the metal electrodes enables a fully differential sensing scheme with robust metal sensing structures. CoventorWare is used in structural and electrical design and simulation of the fully differential accelerometer. The MUMPs foundry fabrication process of the sensor allows for high yield, good process consistency and provides 20 μm structural thickness of the sensing element, which makes the capacitive sensing eligible. In device characterization, surface profile of the fabricated device is measured using a Veeco surface profilometer; and mean and gradient residual stress in the nickel structure are calculated as approximately 94.7 MPa and -5.27 MPa/μm, respectively. Dynamic characterization of the sensor is performed using a vibration shaker with a high-end commercial calibrating accelerometer as reference. The sensitivity of the sensor is measured as 0.52 mV/g prior to off-chip amplification. Temperature dependence of the sensing capacitance is also characterized. A -0.021fF/°C is observed. The findings in the presented work will provide useful information for design of sensors and actuators such as accelerometers, gyroscopes and electrothermal actuators that are to be fabricated using MetalMUMPs technology.

  18. Design and Characterization of a Fully Differential MEMS Accelerometer Fabricated Using MetalMUMPs Technology

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2013-05-01

    Full Text Available This paper presents a fully differential single-axis accelerometer fabricated using the MetalMUMPs process. The unique structural configuration and common-centriod wiring of the metal electrodes enables a fully differential sensing scheme with robust metal sensing structures. CoventorWare is used in structural and electrical design and simulation of the fully differential accelerometer. The MUMPs foundry fabrication process of the sensor allows for high yield, good process consistency and provides 20 μm structural thickness of the sensing element, which makes the capacitive sensing eligible. In device characterization, surface profile of the fabricated device is measured using a Veeco surface profilometer; and mean and gradient residual stress in the nickel structure are calculated as approximately 94.7 MPa and −5.27 MPa/μm, respectively. Dynamic characterization of the sensor is performed using a vibration shaker with a high-end commercial calibrating accelerometer as reference. The sensitivity of the sensor is measured as 0.52 mV/g prior to off-chip amplification. Temperature dependence of the sensing capacitance is also characterized. A −0.021fF/°C is observed. The findings in the presented work will provide useful information for design of sensors and actuators such as accelerometers, gyroscopes and electrothermal actuators that are to be fabricated using MetalMUMPs technology.

  19. Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

    Energy Technology Data Exchange (ETDEWEB)

    Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

    2016-07-11

    Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

  20. Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

    Science.gov (United States)

    Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

    2016-07-01

    Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

  1. A CMOS class-AB transconductance amplifier for switched-capacitor applications

    NARCIS (Netherlands)

    Rijns, J.J.F.; Rijns, J.J.F.; Wallinga, Hans

    1990-01-01

    A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high

  2. A CMOS class-AB transconductance amplifier for switched-capacitor applications

    NARCIS (Netherlands)

    Rijns, J.J.F.; Rijns, J.J.F.; Wallinga, Hans

    1990-01-01

    A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-

  3. NNLO QCD predictions for fully-differential top-quark pair production at the Tevatron

    CERN Document Server

    Czakon, Michal; Heymes, David; Mitov, Alexander

    2016-01-01

    We present a comprehensive study of differential distributions for Tevatron top-pair events at the level of stable top quarks. All calculations are performed in NNLO QCD with the help of a fully differential partonic Monte-Carlo and are exact at this order in perturbation theory. We present predictions for all kinematic distributions for which data exists. Particular attention is paid on the top-quark forward-backward asymmetry which we study in detail. We compare the NNLO results with existing approximate NNLO predictions as well as differential distributions computed with different parton distribution sets. Theory errors are significantly smaller than current experimental ones with overall agreement between theory and data.

  4. Equalizing Si photodetectors fabricated in standard CMOS processes

    Science.gov (United States)

    Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

    2017-05-01

    This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

  5. Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- DPLL

    Directory of Open Access Journals (Sweden)

    Rajeshwari D S

    2017-06-01

    Full Text Available Fully Differential ended charge pump (FDCP are proven to have advantages over single ended charge pump at the cost of complexity and required more power for implementation for digital phase locked loop(DPLL. Wide swing cascodebias voltage with the rail to rail operational amplifier(opamp as common mode feedback(CMFB provides efficient solutions for current mismatch due to its non-idealities. The FDCP is simulated across process corners using 65nm technology with tsmc foundry for10Ghz DPLL. The power consumption of FDCP is 23mW with 100uA as Charge Pump (CP current.

  6. Fully Bayesian mixture model for differential gene expression: simulations and model checks.

    Science.gov (United States)

    Lewin, Alex; Bochkina, Natalia; Richardson, Sylvia

    2007-01-01

    We present a Bayesian hierarchical model for detecting differentially expressed genes using a mixture prior on the parameters representing differential effects. We formulate an easily interpretable 3-component mixture to classify genes as over-expressed, under-expressed and non-differentially expressed, and model gene variances as exchangeable to allow for variability between genes. We show how the proportion of differentially expressed genes, and the mixture parameters, can be estimated in a fully Bayesian way, extending previous approaches where this proportion was fixed and empirically estimated. Good estimates of the false discovery rates are also obtained. Different parametric families for the mixture components can lead to quite different classifications of genes for a given data set. Using Affymetrix data from a knock out and wildtype mice experiment, we show how predictive model checks can be used to guide the choice between possible mixture priors. These checks show that extending the mixture model to allow extra variability around zero instead of the usual point mass null fits the data better. A software package for R is available.

  7. More on the 1/f(2) phase noise performance of CMOS differential-pair LC-tank oscillators

    DEFF Research Database (Denmark)

    Andreani, Pietro; Fard, Ali

    2006-01-01

    This paper presents a rigorous phase noise analysis in the 1/f2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents......, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of -144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure......-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theory...

  8. The effect of dynamical screening on helium (e, 2e) fully differential cross-sections

    Institute of Scientific and Technical Information of China (English)

    Sun Shi-Yan; Jia Xiang-Fu; Miao Xiang-Yang; Zhang Jun-Feng; Xie Yi; Li Xiong-Wei; Shi Wen-Qiang

    2009-01-01

    This paper presents the fully differential cross sections (FDCS) for 102eV electron impact single ionization of helium for both the coplanar and perpendicular plane asymmetric geometries within the framework of dynamically screened three-Coulomb-wave theory. Comparisons are made with the experimental data and those of the three-Coulomb wave function model and second-order distorted-wave Born method. The angular distribution and relative heights of the present FDCS is found to be in very good agreement with the experimental data in the perpendicular plane geometry.It is shown that dynamical screening effects are significant in this geometry. Three-body coupling is expected to be weak in the coplanar geometry, although the precise absolute value of the cross section is still sensitive to the interaction details.

  9. Fully differential cross sections for C6+single ionization of helium

    Institute of Scientific and Technical Information of China (English)

    Li Xia; Ma Xiao-Yan; Sun Shi-Yan; Jia Xiang-Fu

    2012-01-01

    The three-Coulomb-wave (3C) model is applied to study the single ionization of helium by 2 MeV/amu C6+impact.Fully differential cross sections (FDCS) are calculated in the scattering plane and the results are compared with experimental data and other theoretical predictions.It is shown that the 3C results of the recoil peak are in very good agreement with experimental observations,and variation of the position of the binary peak with increasing momentum transfer also conforms better to the experimental results.Furthermore,the contributions of different scattering amplitudes are discussed.It turns out that the cross sections are strongly influenced by the interference of these amplitudes.

  10. Cloning mice and ES cells by nuclear transfer from somatic stem cells and fully differentiated cells.

    Science.gov (United States)

    Wang, Zhongde

    2011-01-01

    Cloning animals by nuclear transfer (NT) has been successful in several mammalian species. In addition to cloning live animals (reproductive cloning), this technique has also been used in several species to establish cloned embryonic stem (ntES) cell lines from somatic cells. It is the latter application of this technique that has been heralded as being the potential means to produce isogenic embryonic stem cells from patients for cell therapy (therapeutic cloning). These two types of cloning differ only in the steps after cloned embryos are produced: for reproductive cloning the cloned embryos are transferred to surrogate mothers to allow them to develop to full term and for therapeutic cloning the cloned embryos are used to derive ntES cells. In this chapter, a detailed NT protocol in mouse by using somatic stem cells (neuron and skin stem cells) and fully differentiated somatic cells (cumulus cells and fibroblast cells) as nuclear donors is described.

  11. Interference pattern signatures in fully differential cross sections for single ionization of H{sub 2} molecules by fast protons

    Energy Technology Data Exchange (ETDEWEB)

    Ciappina, M F [Max Planck Institute for the Physics of Complex Systems, Noethnitzer Str 38, D-01187 Dresden (Germany); Rivarola, R D [Instituto de Fisica Rosario (CONICET-UNR), Av. Pellegrini 250, 2000 Rosario (Argentina)

    2008-01-14

    Electron interference signatures present in fully differential cross sections for single ionization by 6 MeV protons in H{sub 2} molecules are investigated. We employ a molecular version of the continuum-distorted wave-eikonal initial state model, where all the interactions present in the exit channel are considered on an equal footing. Calculations of fully differential cross sections are performed for different electron and projectile kinematical conditions and the range of validity of the theoretical approach is discussed. Furthermore, we explore the presence of interference patterns in differential cross sections for both aligned and randomly oriented targets in asymmetric coplanar geometries.

  12. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  13. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  14. Nano CMOS

    OpenAIRE

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  15. Development of a fully differential multi-gap resistive plate chamber for the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Deppner, Ingo Martin

    2013-11-21

    The subject of this thesis is the development of a modern time-of-flight detector, a MRPC (Multi-gap Resistive Plate Chamber) for the Compressed Baryonic Matter (CBM) experiment. The main goal of CBM is the investigation of the phase diagram of strongly interacting matter in the region of the highest baryon densities. In order to measure the necessary observables with unprecedented precision an excellent particle identification is required. The key element providing hadron identification in heavy ion reaction at incident energies between 2 and 35 AGeV is a 120 m{sup 2} large Time-of-Flight (ToF) wall composed of MRPCs. The ToF-wall is subdivided in a high rate, an intermediate rate and a low rate region. In this thesis we present a full-size demonstrator for the intermediate rate region and for the low rate region. In-beam and cosmic ray tests demonstrated that these fully differential prototypes fulfill the necessary requirements which are a counter time resolution of about 50 ps, an efficiency above 95 %, a rate capability of about 1 kHz/cm{sup 2} and a granularity between 25 - 50 cm{sup 2}. Based on these counters the so-called ''outer ToF-wall'' was designed in this work.

  16. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair

    Directory of Open Access Journals (Sweden)

    Ilias Chlis

    2014-01-01

    Full Text Available This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  17. Comparative analyses of phase noise in 28 nm CMOS LC oscillator circuit topologies: Hartley, Colpitts, and common-source cross-coupled differential pair.

    Science.gov (United States)

    Chlis, Ilias; Pepe, Domenico; Zito, Domenico

    2014-01-01

    This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  18. A HIGH PERFORMANCE FULLY DIFFERENTIAL PURE CURRENT MODE OPERATIONAL AMPLIFIER AND ITS APPLICATIONS

    Directory of Open Access Journals (Sweden)

    SEYED JAVAD AZHARI

    2012-08-01

    Full Text Available In this paper a novel high performance all current-mode fully-differential (FD Current mode Operational Amplifier (COA in BIPOLAR technology is presented. The unique true current mode simple structure grants the proposed COA the largest yet reported unity gain frequency while providing low voltage low power operation. Benefiting from some novel ideas, it also exhibits high gain, high common mode rejection ratio (CMRR, high power supply rejection ratio (PSRR, high output impedance, low input impedance and most importantly high current drive capability. Its most important parameters are derived and its performance is proved by PSPICE simulations using 0.8 μm BICMOS process parameters at supply voltage of ±1.2V indicating the values of 82.4 dB,52.3º, 31.5 Ω, 31.78 MΩ, 179.2 dB, 2 mW and 698 MHz for gain, phase margin, input impedance, output impedance, CMRR, power and unity gain frequency respectively. Its CMRR also shows very high frequency of 2.64 GHz at zero dB. Its very high PSRR+/PSRR- of 182 dB/196 dB makes the proposed COA a highly suitable block in Mixed-Mode (SOC chips. Most favourably it can deliver up to ±1.5 mA yielding a high current drive capability exceeding 25. To demonstrate the performance of the proposed COA, it is used to realize a constant bandwidth voltage amplifier and a high performance Rm amplifier.

  19. Pathogenesis of Human Enterovirulent Bacteria: Lessons from Cultured, Fully Differentiated Human Colon Cancer Cell Lines

    Science.gov (United States)

    Liévin-Le Moal, Vanessa

    2013-01-01

    SUMMARY Hosts are protected from attack by potentially harmful enteric microorganisms, viruses, and parasites by the polarized fully differentiated epithelial cells that make up the epithelium, providing a physical and functional barrier. Enterovirulent bacteria interact with the epithelial polarized cells lining the intestinal barrier, and some invade the cells. A better understanding of the cross talk between enterovirulent bacteria and the polarized intestinal cells has resulted in the identification of essential enterovirulent bacterial structures and virulence gene products playing pivotal roles in pathogenesis. Cultured animal cell lines and cultured human nonintestinal, undifferentiated epithelial cells have been extensively used for understanding the mechanisms by which some human enterovirulent bacteria induce intestinal disorders. Human colon carcinoma cell lines which are able to express in culture the functional and structural characteristics of mature enterocytes and goblet cells have been established, mimicking structurally and functionally an intestinal epithelial barrier. Moreover, Caco-2-derived M-like cells have been established, mimicking the bacterial capture property of M cells of Peyer's patches. This review intends to analyze the cellular and molecular mechanisms of pathogenesis of human enterovirulent bacteria observed in infected cultured human colon carcinoma enterocyte-like HT-29 subpopulations, enterocyte-like Caco-2 and clone cells, the colonic T84 cell line, HT-29 mucus-secreting cell subpopulations, and Caco-2-derived M-like cells, including cell association, cell entry, intracellular lifestyle, structural lesions at the brush border, functional lesions in enterocytes and goblet cells, functional and structural lesions at the junctional domain, and host cellular defense responses. PMID:24006470

  20. A 3.2-GHz fully integrated low-phase noise CMOS VCO with self-biasing current source for the IEEE 802.11a/hiperLAN WLAN standard

    Science.gov (United States)

    Quemada, C.; Adin, I.; Bistue, G.; Berenguer, R.; Mendizabal, J.

    2005-06-01

    A 3.3V, fully integrated 3.2-GHz voltage-controlled oscillator (VCO) is designed in a 0.18μm CMOS technology for the IEE 802.11a/HiperLAN WLAN standard for the UNII band from 5.15 to 5.35 GHz. The VCO is tunable between 2.85 GHz and 3.31 GHz. NMOS architecture with self-biasing current of the tank source is chosen. A startup circuit has been employed to avoid zero initial current. Current variation is lower than 1% for voltage supply variations of 10%. The use of a self-biasing current source in the tank provides a greater safety in the transconductance value and allows running along more extreme point operation The designed VCO displays a phase noise and output power of -98dBc/Hz (at 100 KHz offset frequency) and 0dBm respectively. This phase noise has been obtained with inductors of 2.2nH and quality factor of 12 at 3.2 GHz, and P-N junction varactors whose quality factor is estimated to exceed 40 at 3.2 GHz. These passive components have been fabricated, measured and modeled previously. The core of the VCO consumes 33mW DC power.

  1. CMOS集成频率综合器的稳定性补偿%A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation

    Institute of Scientific and Technical Information of China (English)

    何捷; 唐长文; 闵昊; 洪志良

    2005-01-01

    通过分析频率综合器的完整三阶闭环s域模型,同时采用根轨迹分析技术,定量分析了工艺、电压和温度引起的环路参数变化对频率综合器稳定性的影响,并提出变化裕量的概念来进行稳定性分析和参数设计.为了获得更加稳定的系统,在电荷泵中设计了结构简单的电流单元用于补偿额外的参数变化,并采用线性压控增益的VCO来减小参数的变化.最后设计了一个分辨率为250kHz,频率范围为1~1.05GHz的集成频率综合器来验证上述的分析和设计方法.%A complete closed-loop third-order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process, voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.

  2. Fully differential cross sections in single ionization of helium by ion impact: Assessing the role of correlated wave functions

    Energy Technology Data Exchange (ETDEWEB)

    Ciappina, M.F. [Max Planck Institute for the Physics of Complex Systems, Noethnitzer Str. 38, D-01187, Dresden (Germany)], E-mail: ciappi@pks.mpg.de; Cravero, W.R. [CONICET and Departamento de Fisica, Universidad Nacional del Sur, Av. Alem 1253, B8000CPB, Bahia Blanca (Argentina)

    2008-02-15

    We study the effect of final state dynamic correlation in single ionization of atoms by ion impact analyzing fully differential cross sections (FDCS). We use a distorted wave model where the final state is represented by a {phi}{sub 2} type correlated function, solution of a non-separable three body continuum Hamiltonian. This final state wave function partially includes the correlation of electron-projectile and electron-recoil relative motion as coupling terms of the wave equation. A comparison of fully differential results using this model with other theories and experimental data reveals that inclusion of dynamic correlation effects have little influence on FDCS, and do not contribute to a better description of available data in the case of electronic emission out-of scattering plane.

  3. Viscosity solutions of fully nonlinear second-order elliptic partial differential equations

    Science.gov (United States)

    Ishii, H.; Lions, P. L.

    We investigate comparison and existence results for viscosity solutions of fully nonlinear, second-order, elliptic, possibly degenerate equations. These results complement those recently obtained by R. Jensen and H. Ishii. We consider various boundary conditions like for instance Dirichlet and Neumann conditions. We also apply these methods and results to quasilinear Monge-Ampère equations. Finally, we also address regularity questions.

  4. Inflation in a Fully-Euroised Economy: Could Inflation Differentials Threaten Competitiveness?

    Directory of Open Access Journals (Sweden)

    Mitrović-Mijatović Marijana

    2017-05-01

    Full Text Available This paper analyses inflation in Montenegro, a country which uses euro outside the euro area, and investigates the factors which contribute to price differentials in Montenegro relative to the euro area. Furthermore, the paper examines whether changes in the real effective exchange rates, which in Montenegro’s case follow the path of price differentials, may have any influence on country’s competitiveness.

  5. Monolithic CMOS-MEMS integration for high-g accelerometers

    Science.gov (United States)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  6. Machine learning approximation algorithms for high-dimensional fully nonlinear partial differential equations and second-order backward stochastic differential equations

    OpenAIRE

    Beck, Christian; E, Weinan; Jentzen, Arnulf

    2017-01-01

    High-dimensional partial differential equations (PDE) appear in a number of models from the financial industry, such as in derivative pricing models, credit valuation adjustment (CVA) models, or portfolio optimization models. The PDEs in such applications are high-dimensional as the dimension corresponds to the number of financial assets in a portfolio. Moreover, such PDEs are often fully nonlinear due to the need to incorporate certain nonlinear phenomena in the model such as default risks, ...

  7. Fully differential cross sections for low to intermediate energy perpendicular plane ionization of xenon atoms

    Energy Technology Data Exchange (ETDEWEB)

    Purohit, G., E-mail: ghanshyam.purohit@spsu.ac.in; Singh, P.; Patidar, V.

    2014-12-15

    Highlights: • We present triply differential cross section (TDCS) results for the perpendicular plane ionization of xenon atoms. • The TDCS has been calculated in the modified distorted wave Born approximation formalism. • The effects of target polarization and post collision interaction have also been included. • The polarization potential, higher order effects and PCI has been found to be useful in the description of TDCS. - Abstract: Triple differential cross section (TDCS) results are reported for the perpendicular plane ionization of Xe (5p) at incident electron energies 5 eV, 10 eV, 20 eV, and 40 eV above ionization potential. The modified distorted wave Born approximation formalism with first as well as the second order Born terms has been used to calculate the TDCS. Effects of target polarization and post collision interaction have also been included. We compare the (e, 2e) TDCS results of our calculation with the recent available experimental data and theoretical results and discuss the process contributing to structure seen in the differential cross section. It has been observed from the present study that the second order effect and target polarization make significant contribution in description of collision dynamics of xenon at the low and intermediate energy for the perpendicular emission of electrons.

  8. Diphoton production at hadron colliders: a fully differential QCD calculation at next-to-next-to-leading order.

    Science.gov (United States)

    Catani, Stefano; Cieri, Leandro; de Florian, Daniel; Ferrera, Giancarlo; Grazzini, Massimiliano

    2012-02-17

    We consider direct diphoton production in hadron collisions, and we compute the next-to-next-to-leading order QCD radiative corrections at the fully differential level. Our calculation uses the q(T) subtraction formalism, and it is implemented in a parton-level Monte Carlo program. The program allows the user to apply arbitrary kinematical cuts on the final-state photons and the associated jet activity and to compute the corresponding distributions in the form of bin histograms. We present selected numerical results related to Higgs boson searches at the LHC and corresponding results at the Tevatron.

  9. Post-prior discrepancies in CDW-EIS calculations for ion impact ionization fully differential cross sections

    Energy Technology Data Exchange (ETDEWEB)

    Ciappina, M F; Cravero, W R [CONICET and Departamento de Fisica, Av Alem 1253 (8000) BahIa Blanca (Argentina)

    2006-03-14

    In this work we present fully differential cross sections (FDCSs) calculations using post and prior versions of CDW-EIS theory for helium single ionization by 100 MeV C{sup 6+} amu{sup -1} and 3.6 MeV amu{sup -1} Au{sup 24+} and Au{sup 53+} ions. We performed our calculations for different momentum transfer and ejected electron energies. The influence of internuclear potential on the ejected electron spectra is taken into account in all cases. We compare our calculations with absolute experimental measurements. It is shown that prior version calculations give better agreement with experiments in almost all studied cases.

  10. Post-Prior discrepancies in CDW-EIS calculations for ion impact ionization fully differential cross sections

    CERN Document Server

    Ciappina, M F

    2005-01-01

    In this work we present fully differential cross sections (FDCSs) calculations using post and prior version of CDW--EIS theory for helium single ionization by 100 MeV C$^{6+}$ amu$^{-1}$ and 3.6 MeV amu$^{-1}$ Au$^{24+}$ and Au$^{53+}$ ions. We performed our calculations for different momentum transfer and ejected electron energies. The influence of internuclear potential on the ejected electron spectra is taken into account in all cases. We compare our calculations with absolute experimental measurements. It is shown that prior version calculations give better agreement with experiments in almost all studied cases.

  11. Fully differential cross sections for ion-atom impact ionization in the presence of a laser field

    Energy Technology Data Exchange (ETDEWEB)

    Ciappina, M F [Max Planck Institute for the Physics of Complex Systems, Noethnitzer Str 38, D-01187, Dresden (Germany)

    2007-11-14

    We study fully differential cross sections (FDCS) for single ionization of helium by ion impact in the presence of a laser field. The field is assumed to have linear polarization, to be weak compared to the typical atomic field, and we use a frequency corresponding to a CO{sub 2} laser. We employ the continuum distorted wave-eikonal initial state (CDW-EIS) to describe our FDCS in the laser background. Analysing our numerical results we explore the dependence of the FDCS on the laser field properties as well as on the ionized electron parameters.

  12. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  13. Fully-differential NNLO predictions for vector-boson pair production with MATRIX

    CERN Document Server

    Wiesemann, Marius; Kallweit, Stefan; Rathlev, Dirk

    2016-01-01

    We review the computations of the next-to-next-to-leading order (NNLO) QCD corrections to vector-boson pair production processes in proton–proton collisions and their implementation in the numerical code MATRIX. Our calculations include the leptonic decays of W and Z bosons, consistently taking into account all spin correlations, off-shell effects and non-resonant contributions. For massive vector-boson pairs we show inclusive cross sections, applying the respective mass windows chosen by ATLAS and CMS to define Z bosons from their leptonic decay products, as well as total cross sections for stable bosons. Moreover, we provide samples of differential distributions in fiducial phase-space regions inspired by typical selection cuts used by the LHC experiments. For the vast majority of measurements, the inclusion of NNLO corrections significantly improves the agreement of the Standard Model predictions with data.

  14. Resolving the Tevatron Top Quark Forward-Backward Asymmetry Puzzle: Fully Differential Next-to-Next-to-Leading-Order Calculation.

    Science.gov (United States)

    Czakon, Michal; Fiedler, Paul; Mitov, Alexander

    2015-07-31

    We determine the dominant missing standard model (SM) contribution to the top quark pair forward-backward asymmetry at the Tevatron. Contrary to past expectations, we find a large, around 27%, shift relative to the well-known value of the inclusive asymmetry in next-to-leading order QCD. Combining all known standard model corrections, we find that A(FB)(SM)=0.095±0.007. This value is in agreement with the latest DØ measurement [V. M. Abazov et al. (D0 Collaboration), Phys. Rev. D 90, 072011 (2014)] A(FB)(D∅)=0.106±0.03 and about 1.5σ below that of CDF [T. Aaltonen et al. (CDF Collaboration), Phys. Rev. D 87, 092002 (2013)] A(FB)(CDF)=0.164±0.047. Our result is derived from a fully differential calculation of the next-to-next-to leading order (NNLO) QCD corrections to inclusive top pair production at hadron colliders and includes-without any approximation-all partonic channels contributing to this process. This is the first complete fully differential calculation in NNLO QCD of a two-to-two scattering process with all colored partons.

  15. Human pluripotent stem cells differentiated in fully defined medium generate hematopoietic CD34- and CD34+ progenitors with distinct characteristics.

    Science.gov (United States)

    Chicha, Laurie; Feki, Anis; Boni, Alessandro; Irion, Olivier; Hovatta, Outi; Jaconi, Marisa

    2011-02-25

    Differentiation of pluripotent stem cells in vitro provides a powerful means to investigate early developmental fates, including hematopoiesis. In particular, the use of a fully defined medium (FDM) would avoid biases induced by unidentified factors contained in serum, and would also allow key molecular mediators involved in such a process to be identified. Our goal was to induce in vitro, the differentiation of human embryonic stem cells (ESC) and induced pluripotent stem cells (iPSC) into morphologically and phenotypically mature leukocytes and erythrocytes, in the complete absence of serum and feeder cells. ESC and iPSC were sequentially induced in liquid cultures for 4 days with bone morphogenic protein-4, and for 4 days with FLT3-ligand, stem cell factor, thrombopoietin and vascular endothelium growth factor. Cell differentiation status was investigated by both mRNA expression and FACS expression profiles. Cells were further sorted and assayed for their hematopoietic properties in colony-forming unit (CFU) assays. In liquid cultures, cells progressively down-modulated Oct-4 expression while a sizeable cell fraction expressed CD34 de novo. SCL/Tal1 and Runx1 transcripts were exclusively detected in CD34(+) cells. In clonal assays, both ESC and iPSC-derived cells generated CFU, albeit with a 150-fold lower efficacy than cord blood (CB) CD34(+) cells. ESC-derived CD34(+) cells generated myeloid and fully hemoglobinized erythroid cells whereas CD34(-) cells almost exclusively generated small erythroid colonies. Both ESC and iPSC-derived erythroid cells expressed embryonic and fetal globins but were unable to synthesize adult β-globin in contrast with CB cells, suggesting that they had differentiated from primitive rather than from definitive hematopoietic progenitors. Short-term, animal protein-free culture conditions are sufficient to sustain the differentiation of human ESC and iPSC into primitive hematopoietic progenitors, which, in turn, produce more mature

  16. Human pluripotent stem cells differentiated in fully defined medium generate hematopoietic CD34- and CD34+ progenitors with distinct characteristics.

    Directory of Open Access Journals (Sweden)

    Laurie Chicha

    Full Text Available BACKGROUND: Differentiation of pluripotent stem cells in vitro provides a powerful means to investigate early developmental fates, including hematopoiesis. In particular, the use of a fully defined medium (FDM would avoid biases induced by unidentified factors contained in serum, and would also allow key molecular mediators involved in such a process to be identified. Our goal was to induce in vitro, the differentiation of human embryonic stem cells (ESC and induced pluripotent stem cells (iPSC into morphologically and phenotypically mature leukocytes and erythrocytes, in the complete absence of serum and feeder cells. METHODOLOGY/PRINCIPAL FINDINGS: ESC and iPSC were sequentially induced in liquid cultures for 4 days with bone morphogenic protein-4, and for 4 days with FLT3-ligand, stem cell factor, thrombopoietin and vascular endothelium growth factor. Cell differentiation status was investigated by both mRNA expression and FACS expression profiles. Cells were further sorted and assayed for their hematopoietic properties in colony-forming unit (CFU assays. In liquid cultures, cells progressively down-modulated Oct-4 expression while a sizeable cell fraction expressed CD34 de novo. SCL/Tal1 and Runx1 transcripts were exclusively detected in CD34(+ cells. In clonal assays, both ESC and iPSC-derived cells generated CFU, albeit with a 150-fold lower efficacy than cord blood (CB CD34(+ cells. ESC-derived CD34(+ cells generated myeloid and fully hemoglobinized erythroid cells whereas CD34(- cells almost exclusively generated small erythroid colonies. Both ESC and iPSC-derived erythroid cells expressed embryonic and fetal globins but were unable to synthesize adult β-globin in contrast with CB cells, suggesting that they had differentiated from primitive rather than from definitive hematopoietic progenitors. CONCLUSIONS/SIGNIFICANCE: Short-term, animal protein-free culture conditions are sufficient to sustain the differentiation of human ESC and i

  17. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    Directory of Open Access Journals (Sweden)

    Wei-Song Wang

    2010-03-01

    Full Text Available Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 ºpA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB.

  18. Fully differential cross sections for C{sup 6+} single ionization of helium: the role of nucleus-nucleus interaction

    Energy Technology Data Exchange (ETDEWEB)

    Ciappina, M F; Cravero, W R [CONICET and Departamento de Fisica, Universidad Nacional del Sur, Av. Alem 1253 (8000) BahIa Blanca (Argentina)

    2006-05-14

    In this work, we present fully differential cross section (FDCS) calculations using distorted wave theories for helium single ionization by 2 MeV amu{sup -1} C{sup 6+} ions. We study the influence of internuclear interaction on low-energy electron emission in the scattering plane. It is shown that by incorporating an internuclear effective charge which depends on the collision momentum transfer and taking into account its interplay with passive electron screening we obtain better agreement with experiments in most cases under consideration. Comparisons are made with absolute experimental measurements and with other theories. We found that for ejected-electron momentum similar to transferred momentum, internuclear potential effects have little contribution to FDCSs.

  19. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  20. Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

    Energy Technology Data Exchange (ETDEWEB)

    Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

    2016-07-11

    The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

  1. Dysfunctions at human intestinal barrier by water-borne protozoan parasites: lessons from cultured human fully differentiated colon cancer cell lines.

    Science.gov (United States)

    Liévin-Le Moal, Vanessa

    2013-06-01

    Some water-borne protozoan parasites induce diseases through their membrane-associated functional structures and virulence factors that hijack the host cellular molecules and signalling pathways leading to structural and functional lesions in the intestinal barrier. In this Microreview we analyse the insights on the mechanisms of pathogenesis of Entamoeba intestinalis, Giardia and Cryptosporidium observed in the human colon carcinoma fully differentiated colon cancer cell lines, cell subpopulations and clones expressing the structural and functional characteristics of highly specialized fully differentiated epithelial cells lining the intestinal epithelium and mimicking structurally and functionally an intestinal barrier. © 2013 John Wiley & Sons Ltd.

  2. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  3. Reliability engineering in RF CMOS

    OpenAIRE

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies.

  4. Electronically Tunable Fully Integrated Fractional-Order Resonator

    KAUST Repository

    Tsirimokou, Georgia

    2017-03-20

    A fully integrated implementation of a parallel fractional-order resonator which employs together a fractional order capacitor and a fractional-order inductor is proposed in this paper. The design utilizes current-controlled Operational Transconductance Amplifiers as building blocks, designed and fabricated in AMS 0:35m CMOS process, and based on a second-order approximation of a fractional-order differentiator/ integrator magnitude optimized in the range 10Hz–700Hz. An attractive benefit of the proposed scheme is its electronic tuning capability.

  5. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  6. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    Science.gov (United States)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  7. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  8. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  9. Linear CMOS transconductance element for VHF filters

    NARCIS (Netherlands)

    Nauta, B.; Seevinck, E.

    1989-01-01

    A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, Vipp=1.8 V), nondominant poles in the gigaher

  10. Design of a 12-Bit 200MS/S CMOS Sample-and-Hold Circuit

    Directory of Open Access Journals (Sweden)

    Hamid Mahmoodian

    2014-07-01

    Full Text Available In this paper, a new 12bit, 200MS/s fully differential sample and hold circuit is presented. In order to increase the linearity and input voltage dynamic range; bootstrapped-switches are used for sampling the input signal. Furthermore, a tunable gain buffer is used as the output stage of the circuit to prevent the loading effects of the succeeding stages on the proposed circuit. The circuit is simulated in HSPICE using 0.35µm CMOS technology parameters. As it is discussed in the paper, simulation results justify the good performance of the proposed circuit for using in 12bit, 200MS/s applications.

  11. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS

    OpenAIRE

    Payami, Sima

    2012-01-01

    In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The open-loop DC-gain of the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz. Phase-Margin (PM) of the ...

  12. Optimal Geometry of CMOS Voltage-Mode and Current-Mode Vertical Magnetic Hall Sensors

    OpenAIRE

    2015-01-01

    Four different geometries of a vertical Hall sensor\\ud are presented and studied in this paper. The current spinning\\ud technique compensates for the offset and the sensors, driven in\\ud current-mode, provide a differential signal current for a possible\\ud capacitive integration over a defined time-slot. The sensors have\\ud been fabricated using a 6-metal 0.18-μm CMOS technology and\\ud fully experimentally tested. The optimal solution will be further\\ud investigated for bendable electronics. ...

  13. A design approach for integrated CMOS LC-tank oscillators using bifurcation analysis

    Directory of Open Access Journals (Sweden)

    M. Prochaska

    2006-01-01

    Full Text Available Electrical oscillators play a decisive role in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper formulas for investigations of the stability as well as the amplitude of CMOS LC tank oscillators are derived, where an overall model of nonlinear gain elements is used. By means of these results we are able to present an improved design approach which gives a deeper insight into the functionality of LC tank VCOs.

  14. Voltage-to-frequency converters CMOS design and implementation

    CERN Document Server

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  15. Delta Doping High Purity CCDs and CMOS for LSST

    Science.gov (United States)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  16. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  17. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  18. A VLSI Implementation of a New Low Voltage 5th Order Differential Gm-C Low-Pass Filter with Auto-Tuning Loop in CMOS Technology

    Directory of Open Access Journals (Sweden)

    BOZOMITU, R. G.

    2011-02-01

    Full Text Available In this paper a new low voltage 5th order Gm-C Bessel type low-pass filter (LPF with auto-tuning loop and higher dynamic range, designed in CMOS technology, is presented. The cut-off frequency can be tuned in (10-42MHz range by modifying the values of the grounded capacitors using a digital logic. The proposed structure is based on an auto-tuning loop in order to maintain the Gm/C ratio independent of the process, supply voltage and temperature variations, assuring the cut-off frequency of the LPF independently of these factors. The proposed 5th order Gm-C Bessel type low-pass filter provides 5% variation of the cut-off frequency in all critical corners, a 400mVpp(diff dynamic range, THD less than 1% and 21.6mW power consumption from 1.8V supply voltage. The simulations performed in 65nm CMOS process confirm the theoretical results.

  19. A fully defined and scalable 3D culture system for human pluripotent stem cell expansion and differentiation

    Science.gov (United States)

    Lei, Yuguo; Schaffer, David V.

    2013-12-01

    Human pluripotent stem cells (hPSCs), including human embryonic stem cells and induced pluripotent stem cells, are promising for numerous biomedical applications, such as cell replacement therapies, tissue and whole-organ engineering, and high-throughput pharmacology and toxicology screening. Each of these applications requires large numbers of cells of high quality; however, the scalable expansion and differentiation of hPSCs, especially for clinical utilization, remains a challenge. We report a simple, defined, efficient, scalable, and good manufacturing practice-compatible 3D culture system for hPSC expansion and differentiation. It employs a thermoresponsive hydrogel that combines easy manipulation and completely defined conditions, free of any human- or animal-derived factors, and entailing only recombinant protein factors. Under an optimized protocol, the 3D system enables long-term, serial expansion of multiple hPSCs lines with a high expansion rate (∼20-fold per 5-d passage, for a 1072-fold expansion over 280 d), yield (∼2.0 × 107 cells per mL of hydrogel), and purity (∼95% Oct4+), even with single-cell inoculation, all of which offer considerable advantages relative to current approaches. Moreover, the system enabled 3D directed differentiation of hPSCs into multiple lineages, including dopaminergic neuron progenitors with a yield of ∼8 × 107 dopaminergic progenitors per mL of hydrogel and ∼80-fold expansion by the end of a 15-d derivation. This versatile system may be useful at numerous scales, from basic biological investigation to clinical development.

  20. Fully differential Higgs pair production in association with a W boson at next-to-next-to-leading order in QCD

    Science.gov (United States)

    Li, Hai Tao; Wang, Jian

    2017-02-01

    To clarify the electroweak symmetry breaking mechanism, we need to probe the Higgs self-couplings, which can be measured in Higgs pair productions. The associated production with a vector boson is special due to a clear tag in the final state. We perform a fully differential next-to-next-to-leading-order calculation of the Higgs pair production in association with a W boson at hadron colliders, and present numerical results at the 14 TeV LHC and a future 100 TeV hadron collider.

  1. Fully Differential Higgs Pair Production in Association With a $W$ Boson at Next-to-Next-to-Leading Order in QCD

    CERN Document Server

    Li, Hai Tao

    2016-01-01

    To clarify the electroweak symmetry breaking mechanism, we need to probe the Higgs self-couplings, which can be measured in Higgs pair productions. The associated production with a vector boson is special due to a clear tag in the final state. We perform a fully differential next-to-next-to-leading-order calculation of the Higgs pair production in association with a $W$ boson at hadron colliders, and present numerical results at the 14 TeV LHC and a future 100 TeV hadron collider.

  2. Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

    Science.gov (United States)

    Singh, Anil; Agarwal, Alpana

    2016-10-01

    A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

  3. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  4. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  5. CMOS compatible nanoscale nonvolatile resistance switching memory.

    Science.gov (United States)

    Jo, Sung Hyun; Lu, Wei

    2008-02-01

    We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

  6. Fully automatic differential diagnosis system for dementia with Lewy bodies and Alzheimer's disease using FDG-PET and 3D-SSP

    Energy Technology Data Exchange (ETDEWEB)

    Kono, Atsushi K.; Ishii, Kazunari; Sofue, Keitaro; Miyamoto, Naokazu [Hyogo Brain and Heart Center, Department of Radiology and Nuclear Medicine, Himeji, Hyogo (Japan); Sakamoto, Setsu [Himeji Central Hospital, PET Center, Himeji, Hyogo (Japan); Mori, Etsuro [Tohoku University Graduate School of Medicine, Behavioral Neurology and Cognitive Neuroscience, Sendai, Miyagi (Japan)

    2007-09-15

    To evaluate a fully automatic computer-assisted diagnostic system for mild dementia with Lewy bodies (DLB), permitting distinction from mild Alzheimer's disease (AD). Using{sup 18}F-fluorodeoxyglucose and positron emission tomography (FDG-PET), glucose metabolic images were obtained from mild DLB and mild AD patients. Two groups consisting of 16 mild DLB patients and 21 mild AD patients were recruited for diagnostic evaluation between mild DLB and mild AD. The mean age {+-} SD of the mild DLB group and the mild AD group was 74.3 {+-} 4.9 and 71.7 {+-} 2.1 years, respectively, and the mean scores of the MMSE for the mild DLB and the mild AD group were 21.7 {+-} 1.9 and 23.1 {+-} 2.1, respectively. A receiver operating characteristic (ROC) analysis was performed to compare the diagnostic performance, in terms of discrimination between DLB and AD, of conventional axial FDG-PET images inspected visually by experts and beginners with that of our fully automatic diagnosis system using the statistical brain mapping method and Z scores obtained with the DLB template. The diagnostic performance of the automatic system was comparable to that of visual inspection by experts. The area under the ROC curve for the automatic diagnosis system was 0.77. The mean area under the ROC curve for visual inspection by experts and beginners was 0.76 and 0.65, respectively. The fully automatic differential diagnosis system for distinction between mild DLB and AD showed a similar diagnostic accuracy to visual inspection by experts. It would be a useful diagnostic tool to distinguish mild DLB from mild AD in clinical practice. (orig.)

  7. CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

    Energy Technology Data Exchange (ETDEWEB)

    Fu Jian; Mei Niansong; Huang Yumei; Hong Zhiliang, E-mail: yumeihuang@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-09-15

    A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-{mu}m CMOS process for W-CDMA application is presented. The transformer not only accomplishes output impedance matching, but also acts as a balun for converting differential signals to single-ended ones. Under a supply voltage of 3.3 V, the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%. The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB, respectively. The die size is 0.91 x 1.12 mm{sup 2}. (semiconductor integrated circuits)

  8. CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

    Institute of Scientific and Technical Information of China (English)

    Fu Jian; Mei Niansong; Huang Yumei; Hong Zhiliang

    2011-01-01

    A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively.The die size is 0.91 × 1.12 mm2.

  9. CMOS-Compatible Silicon-Nanowire-Based Coulter Counter for Cell Enumeration.

    Science.gov (United States)

    Chen, Yu; Guo, Jinhong; Muhammad, Hamidullah; Kang, Yuejun; Ary, Sunil K

    2016-02-01

    A silicon-nanowire-based Coulter counter has been designed and fabricated for particle/cell enumeration. The silicon nanowire was fabricated in a fully complementary metal-oxide-semiconductor (CMOS)-compatible process and used as a field effect transistor (FET) device. The Coulter counter device worked on the principle of potential change detection introduced by the passing of microparticles/cells through a sensing channel. Device uniformity was confirmed by scanning electron microscopy and transmission electron microscopy. Current-voltage measurement showed the high sensitivity of the nanowire FET device to the surface potential change. The results revealed that the silicon-nanowire-based Coulter counter can differentiate polystyrene beads with diameters of 8 and 15 μm. Michigan Cancer Foundation-7 (MCF-7) cells have been successfully counted to validate the device. A fully CMOS-compatible fabrication process can help the device integration and facilitate the development of sensor arrays for high throughput application. With appropriate sample preparation steps, it is also possible to expand the work to applications such as rare-cells detection.

  10. Programmable differential capacitance-to-voltage converter for MEMS accelerometers

    Science.gov (United States)

    Royo, G.; Sánchez-Azqueta, C.; Gimeno, C.; Aldea, C.; Celma, S.

    2017-05-01

    Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.

  11. Building strong partnerships with CMOs.

    Science.gov (United States)

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings.

  12. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

    Energy Technology Data Exchange (ETDEWEB)

    Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

    2010-12-15

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  13. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    Energy Technology Data Exchange (ETDEWEB)

    Ko, Hyoungho [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Sangjun [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Paik, Seung-Joon [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Choi, Byoung-doo [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Yonghwa [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Lee, Sangmin [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Kim, Sungwook [SML Electronics, Inc. (Korea, Republic of); Lee, Sang Chul [SML Electronics, Inc. (Korea, Republic of); Lee, Ahra [SML Electronics, Inc. (Korea, Republic of); Yoo, Kwangho [SML Electronics, Inc. (Korea, Republic of); Lim, Jaesang [SML Electronics, Inc. (Korea, Republic of); Cho, Dong-il [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of)

    2006-04-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 {mu}m BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 {mu}g/{radical}Hz, the bias instability of 490 {mu}g, the input range of {+-}10 g, and the output nonlinearity of {+-}0.5 %FSO.

  14. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  15. Silicon pixel detector prototyping in SOI CMOS technology

    Science.gov (United States)

    Dasgupta, Roma; Bugiel, Szymon; Idzik, Marek; Kapusta, Piotr; Kucewicz, Wojciech; Turala, Michal

    2016-12-01

    The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

  16. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  17. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

  18. Knockdown of copper-transporting ATPase 1 (Atp7a) impairs iron flux in fully-differentiated rat (IEC-6) and human (Caco-2) intestinal epithelial cells.

    Science.gov (United States)

    Ha, Jung-Heun; Doguer, Caglar; Collins, James F

    2016-09-01

    Intestinal iron absorption is highly regulated since no mechanism for iron excretion exists. We previously demonstrated that expression of an intestinal copper transporter (Atp7a) increases in parallel with genes encoding iron transporters in the rat duodenal epithelium during iron deprivation (Am. J. Physiol.: Gastrointest. Liver Physiol., 2005, 288, G964-G971). This led us to postulate that Atp7a may influence intestinal iron flux. Therefore, to test the hypothesis that Atp7a is required for optimal iron transport, we silenced Atp7a in rat IEC-6 and human Caco-2 cells. Iron transport was subsequently quantified in fully-differentiated cells plated on collagen-coated, transwell inserts. Interestingly, (59)Fe uptake and efflux were impaired in both cell lines by Atp7a silencing. Concurrent changes in the expression of key iron transport-related genes were also noted in IEC-6 cells. Expression of Dmt1 (the iron importer), Dcytb (an apical membrane ferrireductase) and Fpn1 (the iron exporter) was decreased in Atp7a knockdown (KD) cells. Paradoxically, cell-surface ferrireductase activity increased (>5-fold) in Atp7a KD cells despite decreased Dcytb mRNA expression. Moreover, increased expression (>10-fold) of hephaestin (an iron oxidase involved in iron efflux) was associated with increased ferroxidase activity in KD cells. Increases in ferrireductase and ferroxidase activity may be compensatory responses to increase iron flux. In summary, in these reductionist models of the mammalian intestinal epithelium, Atp7a KD altered expression of iron transporters and impaired iron flux. Since Atp7a is a copper transporter, it is a logical supposition that perturbations in intracellular copper homeostasis underlie the noted biologic changes in these cell lines.

  19. A CMOS Wideband Linear Current Attenuator with Electronically Variable Gain

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1993-01-01

    A CMOS highly linear current attenuator is described. The circuit is suited for both differential and single input currents. The current gain is electronically variable between -1 and +1 by means of two controlling currents. A simple additional circuit is described to obtain a gain that is linearly

  20. A CMOS Wideband Linear Current Attenuator with Electronically Variable Gain

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1993-01-01

    A CMOS highly linear current attenuator is described. The circuit is suited for both differential and single input currents. The current gain is electronically variable between -1 and +1 by means of two controlling currents. A simple additional circuit is described to obtain a gain that is linearly

  1. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  2. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the theorethical description of MOS Current Mode Logic, and it is found that it is more difficult to model and simulate the circuit with compare to standard CMOS because of the differential inputs and low voltage swing....

  3. Full differential CMOS interface circuit for closed-loop capacitive micro-accelerometers%闭环电容式微加速度计全差分CMOS接口电路

    Institute of Scientific and Technical Information of China (English)

    刘晓为; 尹亮; 李海涛; 周治平

    2011-01-01

    提出了一种用于电容式微加速度计的低噪声、高线性度全差分接口电路.基于开关电容检测技术,该电路采用一种新的双路反馈结构来提高系统线性度,并采用2 μm n阱CMOS工艺完成芯片设计.仿真结果证明,电路中采用的双路反馈和全差分检测结构使系统的线性度达到0.01%.加入经过优化设计的比例-微分-积分控制器后,有效减小了系统稳态误差,系统响应速度提高了31%,系统线性度提高了66.7%.在±5 V工作电压下,选取64 kHz作为电路采样频率时,其电路等效输入噪声为8 μg·Hz-(1)/(2),系统灵敏度为1.22 V/g,线性度为0.03%,测量范围为±2 g.测试结果显示,提出的电路达到高精度微加速度计系统设计要求,可以应用到地震监测、石油勘探等领域中.%A CMOS full differential interface circuit with low noise and high linearity was presented for closed-loop capacitive micro-accelerometers. Based on switched-capacitor detection, the circuit was designed to improve its linearity by a 0.5 μm n-well CMOS process technology. The simulation result shows that the proposed two-path feedback structure provides a good system linearity of 0.01%. The optimized designed PID controller was added into the system, which decreases the stabilization error effectively, increases the system responding speed by 31%, and the linearity by 66.7%. With a ±5 V supply and a sampling frequency of 64 kHz, the circuit can offer the equivalent input noise in 8μg ·Hz-(1/2), system sensitivity in 1.22 V/g, system linearity in 0.03%, and the work range in ±2 g·These results prove that this circuit is suitable for applications of high performance micro-accelerome-ters to seism detection, oil exploration,etc..

  4. SEMICONDUCTOR INTEGRATED CIRCUITS: Low power CMOS preamplifier for neural recording applications

    Science.gov (United States)

    Xu, Zhang; Weihua, Pei; Beiju, Huang; Hongda, Chen

    2010-04-01

    A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

  5. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-01-15

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  6. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  7. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  8. CMOS array design automation techniques

    Science.gov (United States)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  9. CMOS Nonlinear Signal Processing Circuits

    OpenAIRE

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  10. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  11. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  12. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  13. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  14. CMOS bulk-metal design handbook

    Science.gov (United States)

    Edge, T. M.

    1978-01-01

    User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

  15. All-Digital ADC Design in 65 nm CMOS Technology

    OpenAIRE

    Pathapati, Srinivasa Rao

    2014-01-01

    The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the ...

  16. A CMOS floating point multiplier

    Science.gov (United States)

    Uya, M.; Kaneko, K.; Yasui, J.

    1984-10-01

    This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

  17. A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance

    DEFF Research Database (Denmark)

    Andreani, Pietro; Fard, Ali

    2006-01-01

    The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3mum CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V...

  18. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    Science.gov (United States)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  19. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  20. A CMOS Switched Transconductor Mixer

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, S.M.; Wienk, Gerhardus J.M.; Nauta, Bram

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled

  1. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis descri...

  2. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  3. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology.

    Science.gov (United States)

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K Kirk

    2015-02-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of -56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle.

  4. Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

    Science.gov (United States)

    Shoucheng, Li; Xin'an, Wang; Ke, Lin; Jinpeng, Shen; Jinhai, Zhang

    2014-10-01

    A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm

  5. Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

    OpenAIRE

    Yoshikawa, Nobuyuki; Tomida, T.; Tokuda, A.; Liu, Q.; Meng, X.(Institute of High Energy Physics, Beijing, China); Whiteley, SR.; VanDuzer, T.

    2005-01-01

    Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 mu m, 0.25 mu m, and 0.35 mu m commercial CMOS processes. Their static IN characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured...

  6. Some design aspects of a two-stage rail-to-rail CMOS op amp

    NARCIS (Netherlands)

    Gierkink, S.L.J.; Holzmann, Peter J.; Wiegerink, R.J.; Wassenaar, R.F.

    1999-01-01

    A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductan

  7. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    Science.gov (United States)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-02-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  8. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    Science.gov (United States)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-01-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

  9. Integrated Photodiodes in Standard CMOS Technology for CD and DVD Applications

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    2004-01-01

    The influence of two different geometries (layouts) and two structures of high-speed photodiodes in fully standard 0.18 μm CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. In addition, a possible application of the integrated photodiodes for the CD and DVD optical

  10. Integrated Photodiodes in Standard CMOS Technology for CD and DVD Applications

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    The influence of two different geometries (layouts) and two structures of high-speed photodiodes in fully standard 0.18 μm CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. In addition, a possible application of the integrated photodiodes for the CD and DVD optical

  11. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  12. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  13. Portable design rules for bulk CMOS

    Science.gov (United States)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  14. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence, the proc......This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence....... The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  15. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  16. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  17. Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

    Science.gov (United States)

    Aytar, Oktay

    2015-09-01

    This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (-0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

  18. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  19. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  20. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  1. CMOS Law-jitter Clock Driver Design

    OpenAIRE

    2012-01-01

    [ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. [CASTELLÀ] Diseño de un circuito integrado "clock driver" de bajo jitter y bajo ruido de fase en tecnología CMOS 40 nm. El trabajo se contextualiza en el campo del diseño de circuitos integrados analógicos en tecnologías CMOS nanométricas. [CATALÀ] Disseny d'un circuit "clock driver" de baix jitter i bai...

  2. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  3. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  4. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2011-07-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.

  5. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2012-06-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

  6. Fabrication and Measurement of a Suspended Nanochannel Microbridge Resonator Monolithically Integrated with CMOS Readout Circuitry

    Directory of Open Access Journals (Sweden)

    Gabriel Vidal-Álvarez

    2016-03-01

    Full Text Available We present the fabrication and characterization of a suspended microbridge resonator with an embedded nanochannel. The suspended microbridge resonator is electrostatically actuated, capacitively sensed, and monolithically integrated with complementary metal-oxide-semiconductor (CMOS readout circuitry. The device is fabricated using the back end of line (BEOL layers of the AMS 0.35 μm commercial CMOS technology, interconnecting two metal layers with a contact layer. The fabricated device has a 6 fL capacity and has one of the smallest embedded channels so far. It is able to attain a mass sensitivity of 25 ag/Hz using a fully integrable electrical transduction.

  7. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  8. OperationalAmplifier Analysis when Migrating from 0.18 µm to 65 µm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Karolis Kiela

    2013-05-01

    Full Text Available The article offers the analysis of operational amplifier parameter changes, when circuits are scaled from 0.18 μm to 65 nm CMOS technology. Two two-stage operational amplifiers were designed for this purpose: first uses n-MOS input differential pair; second uses cascaded active loads structure and p-MOS type input differential pair. The operational amplifiers were designed in 0.18 μm CMOS technology and scaled to 65 nm CMOS. Other scaling methods were also analysed when redesigning circuits from one IC technology to another. Results of the original and scaled operational amplifier parameters are presented and analysed.Article in Lithuanian

  9. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  10. Nanosecond monolithic CMOS readout cell

    Science.gov (United States)

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  11. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  12. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  13. Design of Transmission Gate VCO and Dynamic PFD for Low Power CMOS PLL

    Science.gov (United States)

    Yuan, S. C.

    2008-11-01

    To realize the high speed and low power CMOS PLL(Phase Locked Loop), the new circuits of VCO and PFD is designed in transistor level. In the VCO, the high speed and low power is realized using transmission-gate(TG) with an adaptive delay cell and low supply sensitivity. This delay cell has a built-in compensation circuit that senses and corrects the delay variation caused by supply fluctuation. And in the PFD, low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0.6μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000MHz and dissipate power less than 50mW.

  14. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Institute of Scientific and Technical Information of China (English)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  15. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  16. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  17. Fully Integrated Ultra-Low Voltage Step-up Converter with Voltage Doubling LC-Tank for Energy Harvesting Applications

    Science.gov (United States)

    Jayaweera, H. M. P. C.; Pathirana, W. P. M. R.; Muhtaroğlu, Ali

    2015-12-01

    This paper reports the design, fabrication, and validation of a novel integrated interface circuit for ultra-low voltage step up converter in 0.18 μm CMOS technology. The circuit does not use off-chip components. Fully integrated centre-tap differential inductors are introduced in the proposed LC oscillator design to achieve 38% area reduction compared to the use of four separate inductors. The efficiency of the system is hence enhanced through the elimination of clock buffer circuits traditionally utilized to drive the step-up converter. The experimental results prove that the system can self-start, and step 0.25 V up to 1.7 V to supply a 46 μW load with 15.5% efficiency. The minimum validated input voltage is 0.15 V, which is boosted up to 1.2 V under open circuit conditions.

  18. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  19. Analytical design of a 0.5V 5GHz CMOS LC-VCO

    OpenAIRE

    Yamashita, Fumiaki; Matsuoka, Toshimasa; Kihara, Takao; Takobe, Isao; Park, Hae-Ju; Taniguchi, Kenji

    2009-01-01

    A low-voltage complementary cross-coupled differential LC-VCO was investigated using simple modeling. The bias-controllability of the VCO provides a simple design for low-voltage operation. An analytical design approach realized a 5GHz VCO under a 0.5V supply voltage using a 90-nm digital CMOS process.

  20. Integrated RF MEMS/CMOS Devices

    CERN Document Server

    Mansour, R R; Bakeri-Kassem, M

    2008-01-01

    A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

  1. Spectrometry with consumer-quality CMOS cameras.

    Science.gov (United States)

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  2. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  3. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  4. Bridging faults in BiCMOS circuits

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  5. Carbon Nanotube Integration with a CMOS Process

    OpenAIRE

    Perez, Maximiliano S.; Betiana Lerner; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Pedro M. Julian; Pablo S. Mandolesi; Fabian A. Buffa; Alfredo Boselli; Alberto Lamagna

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new rout...

  6. Carbon nanotube integration with a CMOS process.

    Science.gov (United States)

    Perez, Maximiliano S; Lerner, Betiana; Resasco, Daniel E; Pareja Obregon, Pablo D; Julian, Pedro M; Mandolesi, Pablo S; Buffa, Fabian A; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  7. Carbon Nanotube Integration with a CMOS Process

    Directory of Open Access Journals (Sweden)

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  8. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  9. CMOS Direct-Injection Divide-by-3 Injection-Locked Frequency Dividers

    Institute of Scientific and Technical Information of China (English)

    Chia-Wei; Chang; Jhin-Fang; Huang; Sheng-Lyang; Jang; Ying-Hsiang; Liao; Miin-Horng; Juang

    2010-01-01

    <正>This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.

  10. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  11. Analog CMOS contrastive Hebbian networks

    Science.gov (United States)

    Schneider, Christian; Card, Howard

    1992-09-01

    CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

  12. Simple BiCMOS CCCTA design and resistorless analog function realization.

    Science.gov (United States)

    Tangsrirat, Worapong

    2014-01-01

    The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  13. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

  14. Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

    Directory of Open Access Journals (Sweden)

    Worapong Tangsrirat

    2014-01-01

    Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  15. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Directory of Open Access Journals (Sweden)

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  16. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  17. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  18. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths.......A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss

  19. Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

    OpenAIRE

    Akshay Kumar Kansal; Asst Prof. Gayatri Sakya

    2015-01-01

    CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V, the power consumption, slew rate and settling t...

  20. Improvement to the signaling interface for CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Shi, Zhan, E-mail: sz1134@163.com [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Tang, Zhenan, E-mail: tangza@dlut.edu.cn [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Feng, Chong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Dalian Minzu University, No.18 Liaohe West Road, 116600 Dalian (China); Cai, Hong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China)

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  1. Improvement to the signaling interface for CMOS pixel sensors

    Science.gov (United States)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  2. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier

    Directory of Open Access Journals (Sweden)

    De Xing Lioe

    2016-04-01

    Full Text Available A complementary metal-oxide semiconductor (CMOS lock-in pixel to observe stimulated Raman scattering (SRS using a high speed lateral electric field modulator (LEFM for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF and switched-capacitor (SC integrator with a fully CMOS differential amplifier. AC (modulated components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  3. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

    Science.gov (United States)

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-04-13

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  4. CMOS mm-wave transceivers for Gbps wireless communication

    Science.gov (United States)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  5. Design Of High Performance CMOS Dynamic Latch Comparator

    Directory of Open Access Journals (Sweden)

    G.Saroja

    2016-10-01

    Full Text Available High performance analog to digital converters (ADC, memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two factors they are speed and power consumption. The latch based comparator has two different stages encompassing of a dynamic differential input gain stage and an output latch.The output node in the differential gain stage of proposed comparator requires lesser time to regain higher charge potential. The proposed comparator hasbeen designed and simulated using 130nm CMOS 1P2M technology by using mentor graphics tools with a supply voltage of 1V. Proposed dynamic latch comparator iscompared with existing conventional dynamic latch comparator and with other comparators and the results are discussed in detail.

  6. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  7. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  8. Analog CMOS design for optical coherence tomography signal detection and processing.

    Science.gov (United States)

    Xu, Wei; Mathine, David L; Barton, Jennifer K

    2008-02-01

    A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

  9. A Monolithically Integrated Silicon Modulator with a 10Gb/s 5Vpp or 5.6Vpp Driver in 0.25µm SiGe:C BiCMOS

    Directory of Open Access Journals (Sweden)

    Bernhard eGoll

    2014-11-01

    Full Text Available This paper presents as a novelty a fully monolithically integrated 10Gb/s silicon modulator consisting of an electrical driver plus optical phase modulator in 0.25µm SiGe:C BiCMOS technology on one chip, where instead of a SOI CMOS process (only MOS transistors a SiGe BiCMOS process (MOS transistors and fast SiGe bipolar transistors is implemented. The fastest bipolar transistors in the BiCMOS product line used have a transit frequency of 120GHz and a collector-emitter breakdown voltage of 2.2V (IHP SG25H3. The main focus of this paper will be given to the electronic drivers, where two driver variants are implemented in the test chips. Circuit descriptions and simulations, which treat the influences of noise and bond wires, are presented. Measurements at separate test chips for the drivers show that the integrated driver variant one has a low power consumption in the range of 0.66W to 0.68W but a high gain of S21=37dB. From the large signal point of view this driver delivers an inverted as well as a non-inverted output data signal between 0V and 2.5V (5Vpp differential. Driver variant one is supplied with 2.5V and with 3.5V. Bit-error-ratio (BER measurements resulted in a BER better than 10E-12 for voltage differences of the input data stream down to 50mVpp. Driver variant two, which is an adapted version of driver variant one, is supplied with 2.5V and 4.2V, consumes 0.83W to 0.87W, delivers a differential data signal with 5.6Vpp at the output and has a gain of S21=40dB. The chip of the fully integrated modulator occupies an area of 12.3mm^2 due to the photonic components. Measurements with a 240mVpp electrical input data stream and for an optical input wavelength of 1540nm resulted in an extinction ratio of 3.3dB for 1mm long RF phase shifters in each modulator arm driven by driver variant one and a DC tuning voltage of 1.2V. The extinction ratio was 8.4dB at a DC tuning voltage of 7V for a device with 2mm long RF phase shifters and driver

  10. Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

    CERN Document Server

    Oliveira, João P

    2012-01-01

    This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC).  Experimental results are shown to validate the overall design technique. Provides the complete theoretical analysis, supported by electrical simulations, of the parametric amplification technique in both continuous time and discrete time domains; Describes the design flow of an ADC fully based on discrete-time parametric amplification in CMOS technology; Presents a high speed time-interleaved pipeline ADC, based on parametric MOS amplification techniques described, complementing theory discussed with experimental results.

  11. Post-CMOS wafer level growth of carbon nanotubes for low-cost microsensors-a proof of concept

    Energy Technology Data Exchange (ETDEWEB)

    Santra, Sumita; Guha, Prasanta K; Zhong, Guofang; Robertson, John; Milne, William I; Udrea, Florin [Engineering Department, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA (United Kingdom); Ali, Syed Z [Cambridge CMOS Sensors Ltd, Wellington House, East Road, Cambridge CB1 1BH (United Kingdom); Covington, James A; Gardner, Julian W, E-mail: ss778@cam.ac.uk [School of Engineering, University of Warwick, Coventry CV4 7AL (United Kingdom)

    2010-12-03

    Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

  12. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  13. Fully differential cross section for 16 MeV O7+ impact ionization of helium%16 MeV O7+碰撞氦原子单电离的全微分截面

    Institute of Scientific and Technical Information of China (English)

    段巧巧; 孙世艳; 冯丽丽; 贾祥富

    2015-01-01

    The modified-Coulomb-Born with internuclear interaction ( MCB-PT) model is used to calculate fully differential cross section ( FDCS) for helium single ionization by 16 MeV O7+impact in the scattering plane. Comparisons are made with experimental data and other theories from the three-Coulomb (3C) wave and the con-tinuum distorted-wave eikonal-initial-state ( CDW-EIS ) . We find that angular location of the binary peak is in good agreement with experiment at intermediate momentum transfer. Furthermore, we also assess the influence of distorting effect on the FDCS and find that the distorting effects play a significant role with increasing momentum transfer.%考虑核间相互作用,利用修正的库仑玻恩( MCB-PT)模型计算了入射能量为16 MeV的O7+碰撞氦单电离的全微分截面,并将计算结果与最近的实验数据和三体库仑波(3C)模型及连续扭曲波程函初态( CDW-EIS)模型所得结果进行了比较,发现MCB-PT理论结果在中间动量转移条件下binary峰的位置与实验结果符合得很好,且位于动量转移的方向上。此外,分析了扭曲效应对全微分截面的影响,表明随着动量转移的增加,扭曲效应更加明显。

  14. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  15. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    OpenAIRE

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal a...

  16. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  17. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  18. CMOS-compatible LVOF-based visible microspectrometer

    NARCIS (Netherlands)

    Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabricati

  19. Noise in sub-micron CMOS image sensors

    NARCIS (Netherlands)

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  20. An RF (R) MS Power Detector in Standard CMOS

    NARCIS (Netherlands)

    Aa, van der F.H.J.

    2006-01-01

    This Master thesis describes the research towards the integration of RF power detectors for 3G cellular phones and base stations in CMOS technology1. It is a feasibility study with the emphasis on the identification of fundamental limitations of CMOS (particularly CMOS9) and of a number of squaring

  1. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  2. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  3. Scaling CMOS devices through alternative structures

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  4. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  5. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  6. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  7. Evaluation of a scientific CMOS camera for astronomical observations

    Institute of Scientific and Technical Information of China (English)

    Peng Qiu; Yong-Na Mao; Xiao-Meng Lu; E Xiang; Xiao-Jun Jiang

    2013-01-01

    We evaluate the performance of the first generation scientific CMOS (sCMOS) camera used for astronomical observations.The sCMOS camera was attached to a 25 cm telescope at Xinglong Observatory,in order to estimate its photometric capabilities.We further compared the capabilities of the sCMOS camera with that of full-frame and electron multiplying CCD cameras in laboratory tests and observations.The results indicate the sCMOS camera is capable of performing photometry of bright sources,especially when high spatial resolution or temporal resolution is desired.

  8. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  9. Android Fully Loaded

    CERN Document Server

    Huddleston, Rob

    2012-01-01

    Fully loaded with the latest tricks and tips on your new Android! Android smartphones are so hot, they're soaring past iPhones on the sales charts. And the second edition of this muscular little book is equally impressive--it's packed with tips and tricks for getting the very most out of your latest-generation Android device. Start Facebooking and tweeting with your Android mobile, scan barcodes to get pricing and product reviews, download your favorite TV shows--the book is positively bursting with practical and fun how-tos. Topics run the gamut from using speech recognition, location-based m

  10. On Fully Homomorphic Encryption

    OpenAIRE

    Fauzi, Prastudy

    2012-01-01

    Fully homomorphic encryption is an encryption scheme where a party can receive encrypted data and perform arbitrary operations on this data efficiently.The data remains encrypted throughout, but the operations can be done regardless, without having to know the decryption key.Such a scheme would be very advantageous, for example in ensuring the privacy of data that is sent to a third-party service.This is in contrast with schemes like Paillier where you can not perform a multiplication of encr...

  11. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    Science.gov (United States)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  12. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  13. Low power SEU immune CMOS memory circuits

    Science.gov (United States)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  14. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  15. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique...

  16. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  17. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  18. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  19. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  20. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  1. CMOS VHF transconductance-C lowpass filter

    NARCIS (Netherlands)

    Nauta, B.

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  2. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transisto

  3. Fully Integrated Discrete-Time Superheterodyne Receiver in Nano-Scale CMOS

    NARCIS (Netherlands)

    Tohidian, M.

    2015-01-01

    In a radio-frequency (RF) system-on-chip (SoC), a digital baseband/application processor, which occupies most of the silicon area, determines the SoC fabrication process technology and voltage supply. The rest of the circuitry, including RF front-end and frequency synthesizer, must then adopt the

  4. Fully Integrated Discrete-Time Superheterodyne Receiver in Nano-Scale CMOS

    NARCIS (Netherlands)

    Tohidian, M.

    2015-01-01

    In a radio-frequency (RF) system-on-chip (SoC), a digital baseband/application processor, which occupies most of the silicon area, determines the SoC fabrication process technology and voltage supply. The rest of the circuitry, including RF front-end and frequency synthesizer, must then adopt the ch

  5. Fully Integrated Discrete-Time Superheterodyne Receiver in Nano-Scale CMOS

    NARCIS (Netherlands)

    Tohidian, M.

    2015-01-01

    In a radio-frequency (RF) system-on-chip (SoC), a digital baseband/application processor, which occupies most of the silicon area, determines the SoC fabrication process technology and voltage supply. The rest of the circuitry, including RF front-end and frequency synthesizer, must then adopt the ch

  6. Monolithic integration of GMR sensors for standard CMOS-IC current sensing

    Science.gov (United States)

    De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

    2017-09-01

    In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

  7. An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

    Science.gov (United States)

    Guo, Zhiyong; Li, Qiang; Liu, Haiqi; Yan, Bo; Li, Guangjun

    2011-06-01

    This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), ? input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

  8. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  9. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  10. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  11. Integrated on-chip 0.35 μm BiCMOS current-mode DC-DC buck converter

    Science.gov (United States)

    Lee, Chan-Soo; Kim, Nam-Soo; Gendensuren, Munkhsuld; Choi, Jae-Ho; Choi, Joong-Ho

    2012-12-01

    A current-mode DC-DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC-DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

  12. Fully Awake Breast Reduction.

    Science.gov (United States)

    Filson, Simon A; Yarhi, Danielle; Ramon, Yitzhak

    2016-11-01

    The authors present 25 cases and an in-depth 4-minute video of fully awake aesthetic breast reduction, which was made possible by thoracic epidural anesthesia. There are obvious and important advantages to this technique. Not only does this allow for intraoperative patient cooperation (i.e., patient self-positioning and opinion for comparison of breasts), meaning a shorter and more efficient intraoperative time, there also is a reduction in postoperative pain, complications, recovery, and discharge times. The authors have also enjoyed great success and no complications with this technique in over 150 awake abdominoplasty/total body lift patients. The authors feel that the elimination of the need for general anesthesia by thoracic epidural sensorial-only anesthesia is a highly effective and efficient technique, with very few disadvantages/complications, providing advantages to both patients and surgeons. Therapeutic, IV.

  13. Graphene/Si CMOS hybrid hall integrated circuits.

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  14. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  15. Fully electric waste collection

    CERN Multimedia

    Anaïs Schaeffer

    2015-01-01

    Since 15 June, Transvoirie, which provides waste collection services throughout French-speaking Switzerland, has been using a fully electric lorry for its collections on the CERN site – a first for the region!   Featuring a motor powered by electric batteries that charge up when the brakes are used, the new lorry that roams the CERN site is as green as can be. And it’s not only the motor that’s electric: its waste compactor and lifting mechanism are also electrically powered*, making it the first 100% electric waste collection vehicle in French-speaking Switzerland. Considering that a total of 15.5 tonnes of household waste and paper/cardboard are collected each week from the Meyrin and Prévessin sites, the benefits for the environment are clear. This improvement comes as part of CERN’s contract with Transvoirie, which stipulates that the firm must propose ways of becoming more environmentally friendly (at no extra cost to CERN). *The was...

  16. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    Science.gov (United States)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  17. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  18. Spatio-temporal simulation in subthreshold CMOS

    Science.gov (United States)

    Neeley, John; Harris, John G.

    1997-05-01

    This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua's circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit's dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.

  19. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  20. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  1. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  2. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  3. A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    Institute of Scientific and Technical Information of China (English)

    Liu Nan; Chen Guoping; Hong Zhiliang

    2009-01-01

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodi-ode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

  4. Cantilever-Based Biosensors in CMOS Technology

    CERN Document Server

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  5. CMOS current amplifiers : speed versus nonlinearity

    OpenAIRE

    2000-01-01

    This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived tha...

  6. CMOS Design of Ternary Arithmetic Devices

    Institute of Scientific and Technical Information of China (English)

    吴训威; F.Prosser

    1991-01-01

    This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.

  7. CMOS-array design-automation techniques

    Science.gov (United States)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  8. CMOS Camera Array With Onboard Memory

    Science.gov (United States)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  9. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  10. Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

    Directory of Open Access Journals (Sweden)

    Akshay Kumar Kansal

    2015-12-01

    Full Text Available CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V, the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain frequency.

  11. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  12. Efficient design of CMOS TSC checkers

    Science.gov (United States)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  13. A logarithmic low dark current CMOS pixel

    Science.gov (United States)

    Brunetti, Alessandro Michel; Choubey, Bhaskar

    2016-04-01

    High dynamic range pixels are required in a number of automotive and scientific applications. CMOS pixels provide different approaches to achieve this. However, these suffer from poor performance under low light conditions due to inherently high leakage current that is present in CMOS processes, also known as dark current. The typical approach to reduce this dark current involves process modifications. Nevertheless, energy considerations suggest that the leakage current will be close to zero at a close to zero voltage on the photodiode. Hence, the reduction in dark current can be achieved by forcing a zero voltage across the photodiode. In this paper, a novel logarithmic CMOS pixel design capable of reducing dark current without any process modifications is proposed. This pixel is also able to produce a wide dynamic range response. This circuit utilizes two current mirrors to force the in-pixel photodiode at a close to zero voltage. Additionally, a bias voltage is used to reduce a higher order effect known as Drain Induced Barrier Lowering (DIBL). In fact, the contribution of this effect can be compensated by increasing the body effect. In this paper, we studied the consequences of a negative bias voltage applied to the body of the current mirror pair to compensate for the DIBL effect thereby achieving a very small voltage drop on the photodiode and consequently, a higher sensitivity in low light conditions.

  14. On-Chip Hotplate for Temperature Control of Cmos Saw Resonators

    CERN Document Server

    Nordin, Anis; Zaghloul, Mona

    2008-01-01

    Due to the sensitivity of the piezoelectric layer in surface acoustic wave (SAW) resonators to temperature, a method of achieving device stability as a function of temperature is required. This work presents the design, modeling and characterization of integrated dual-serpentine polysilicon resistors as a method for temperature control of CMOS SAW resonators. The design employs the oven control temperature stabilization scheme where the device's temperature is elevated to higher than Tmax to maintain constant device temperature. The efficiency of the polysilicon resistor as a heating element was verified through a 1-D partial differential equation model, 3-D CoventorWare finite element simulations and measurements using Compix thermal camera. To verify that the on-chip hotplate is effective as a temperature control method, both DC and RF measurements of the heater together with the resonator were conducted. Experimental results have indicated that the TCF of the CMOS SAW resonator of -97.2 ppm/deg C has been ...

  15. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    Science.gov (United States)

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  16. Optical design of microlens array for CMOS image sensors

    Science.gov (United States)

    Zhang, Rongzhu; Lai, Liping

    2016-10-01

    The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

  17. Testing fully depleted CCD

    Science.gov (United States)

    Casas, Ricard; Cardiel-Sas, Laia; Castander, Francisco J.; Jiménez, Jorge; de Vicente, Juan

    2014-08-01

    The focal plane of the PAU camera is composed of eighteen 2K x 4K CCDs. These devices, plus four spares, were provided by the Japanese company Hamamatsu Photonics K.K. with type no. S10892-04(X). These detectors are 200 μm thick fully depleted and back illuminated with an n-type silicon base. They have been built with a specific coating to be sensitive in the range from 300 to 1,100 nm. Their square pixel size is 15 μm. The read-out system consists of a Monsoon controller (NOAO) and the panVIEW software package. The deafualt CCD read-out speed is 133 kpixel/s. This is the value used in the calibration process. Before installing these devices in the camera focal plane, they were characterized using the facilities of the ICE (CSIC- IEEC) and IFAE in the UAB Campus in Bellaterra (Barcelona, Catalonia, Spain). The basic tests performed for all CCDs were to obtain the photon transfer curve (PTC), the charge transfer efficiency (CTE) using X-rays and the EPER method, linearity, read-out noise, dark current, persistence, cosmetics and quantum efficiency. The X-rays images were also used for the analysis of the charge diffusion for different substrate voltages (VSUB). Regarding the cosmetics, and in addition to white and dark pixels, some patterns were also found. The first one, which appears in all devices, is the presence of half circles in the external edges. The origin of this pattern can be related to the assembly process. A second one appears in the dark images, and shows bright arcs connecting corners along the vertical axis of the CCD. This feature appears in all CCDs exactly in the same position so our guess is that the pattern is due to electrical fields. Finally, and just in two devices, there is a spot with wavelength dependence whose origin could be the result of a defectous coating process.

  18. CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

    CERN Document Server

    Hehn, Thorsten

    2014-01-01

    This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

  19. Design and implementation of IEEE 802.11ac MAC controller in 65 nm CMOS process

    Science.gov (United States)

    Peng, Cheng; Bin, Wu; Yong, Hei

    2016-02-01

    An IEEE-802.11ac-1*1 wireless LAN system-on-a-chip (SoC) that integrates an analog front end, a digital base-band processor and a media access controller has been implemented in 65 nm CMOS technology. It can provide significantly increased throughput, high efficiency rate selection, and fully backward compatibility with the existing 802.11a/n WLAN protocols. Especially the measured maximum throughput of UDP traffic can be up to 267 Mbps. Project supported by the National Great Specific Project of China (No. 2012ZX03004004_001).

  20. Detailed study of particle detectors OTA-based CMOS Semi-Gaussian shapers

    Science.gov (United States)

    Noulis, T.; Deradonis, C.; Siskos, S.; Sarrabayrouse, G.

    2007-12-01

    An analysis of readout front-end electronics Semi-Gaussian (S-G) shapers is carried out. An innovative design methodology is proposed and advanced filter design techniques based on Operational Transconductance Amplifiers (OTA) are used. Five CMOS shaper topologies are designed using OTAs and compared in terms of noise performance, total harmonic distortion, dynamic range and power consumption in order to examine which is the most preferable in readout applications. Although all shaper architectures are fully integrated, they exhibit a large peaking time. The results are obtained from SPICE simulations for implementations in a 0.6 μm process of Austria Mikro Systeme (AMS).

  1. A 6.2 mW 0.024 mm2 fully-passive RF downconverter with 12 dB gain enhancement using MOS parametric amplification

    DEFF Research Database (Denmark)

    Custódio, J. R.; Bastos, I.; Oliveira, L. B.

    2013-01-01

    This paper describes a fully-passive discrete-time switched-capacitor RF downconverter with an on-chip oscillator, that combines quadrature mixing and harmonic rejection, designed in a 130 nm digital CMOS technology. By using MOS capacitors (varactors) to perform parametric amplification, it is p......This paper describes a fully-passive discrete-time switched-capacitor RF downconverter with an on-chip oscillator, that combines quadrature mixing and harmonic rejection, designed in a 130 nm digital CMOS technology. By using MOS capacitors (varactors) to perform parametric amplification...

  2. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  3. A CMOS pressure sensor tag chip for passive wireless applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  4. CMOS microelectrode array for the monitoring of electrogenic cells.

    Science.gov (United States)

    Heer, F; Franks, W; Blau, A; Taschini, S; Ziegler, C; Hierlemann, A; Baltes, H

    2004-09-15

    Signal degradation and an array size dictated by the number of available interconnects are the two main limitations inherent to standalone microelectrode arrays (MEAs). A new biochip consisting of an array of microelectrodes with fully-integrated analog and digital circuitry realized in an industrial CMOS process addresses these issues. The device is capable of on-chip signal filtering for improved signal-to-noise ratio (SNR), on-chip analog and digital conversion, and multiplexing, thereby facilitating simultaneous stimulation and recording of electrogenic cell activity. The designed electrode pitch of 250 microm significantly limits the space available for circuitry: a repeated unit of circuitry associated with each electrode comprises a stimulation buffer and a bandpass filter for readout. The bandpass filter has corner frequencies of 100 Hz and 50 kHz, and a gain of 1000. Stimulation voltages are generated from an 8-bit digital signal and converted to an analog signal at a frequency of 120 kHz. Functionality of the read-out circuitry is demonstrated by the measurement of cardiomyocyte activity. The microelectrode is realized in a shifted design for flexibility and biocompatibility. Several microelectrode materials (platinum, platinum black and titanium nitride) have been electrically characterized. An equivalent circuit model, where each parameter represents a macroscopic physical quantity contributing to the interface impedance, has been successfully fitted to experimental results.

  5. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  6. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  7. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    Science.gov (United States)

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  8. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  9. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.;

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process...

  10. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  11. Analysis of bipolar and CMOS amplifiers

    CERN Document Server

    Sodagar, Amir M

    2007-01-01

    The classical approach to analog circuit analysis is a daunting prospect to many students, requiring tedious enumeration of contributing factors and lengthy calculations. Most textbooks apply this cumbersome approach to small-signal amplifiers, which becomes even more difficult as the number of components increases. Analysis of Bipolar and CMOS Amplifiers offers students an alternative that enables quick and intuitive analysis and design: the analysis-by-inspection method.This practical and student-friendly text demonstrates how to achieve approximate results that fall within an acceptable ran

  12. Vertical Isolation for Photodiodes in CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  13. An Approach for Low Power CMOS Design

    Directory of Open Access Journals (Sweden)

    Ravindra kumar chejara

    2015-03-01

    Full Text Available Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay. In this paper, variable supply-voltage scheme (dual-VS scheme for dual power supplies along with voltage level converter is presented. Also paper presents an overall comparative analysis among various methods to achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the best methods for same at this technology.

  14. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  15. RF Circuit Design in Nanometer CMOS

    OpenAIRE

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer C...

  16. Method and circuitry for CMOS transconductor linearization

    OpenAIRE

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a sec...

  17. Silicon Light Emitting Devices in CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    CHEN Hong-Da; LIU Hai-Jun; LIU Jin-Bin; GU Ming; HUANG Bei-Ju

    2007-01-01

    @@ Two silicon light emitting devices with different structures are realized in standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/cm2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm.

  18. Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

    Science.gov (United States)

    Vishnoi, U.; Noll, T. G.

    2012-09-01

    The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit

  19. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  20. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  1. Design of high speed camera based on CMOS technology

    Science.gov (United States)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  2. A low-noise current preamplifier in 120 nm CMOS technology

    Directory of Open Access Journals (Sweden)

    H. Uhrmann

    2008-05-01

    Full Text Available In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS based point-to-point data links or preamplifiers for photodetectors.

  3. Theoretical performance analysis for CMOS based high resolution detectors.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-06

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

  4. Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters

    Science.gov (United States)

    Gevaert, D.

    2007-05-01

    The design and testing of a 12-bit Analog-to-Digital (A/D) converter, in current mode, arranged in an 8-bit LSB and a 4- bit MSB architecture together with the integration of specialized test building blocks on chip allows the set up of a design automation technique for current folding and interpolation CMOS A/D converter architectures. The presented design methodology focuses on the automation for CMOS A/D building blocks in a flexible target current folding and interpolating architecture for a downscaling technology and for different quality specifications. The comprehensive understanding of all sources of mismatching in the crucial building blocks and the use of physical based mismatch modeling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of the A/D converter. In this design the folding degree is 16, the number of folders is 64 and the interpolation level is 4. The number of folders is reduced by creating intermediate folding signals with a 4-level interpolator based on current division techniques. Current comparators detect the zero-crossing between the differential folder output currents. The outputs of the comparators deliver a cyclic thermometer code. The digital synthesis part for decoding and error correction building blocks is a standardized digital standard cell design. The basic building blocks in the target architecture were designed in 0.35μ CMOS technology; they are suitable for topological reuse and are in an automated way downscaled into a 0.18μ CMOS technology.

  5. Fully implicit kinetic modelling of collisional plasmas

    Energy Technology Data Exchange (ETDEWEB)

    Mousseau, V.A.

    1996-05-01

    This dissertation describes a numerical technique, Matrix-Free Newton Krylov, for solving a simplified Vlasov-Fokker-Planck equation. This method is both deterministic and fully implicit, and may not have been a viable option before current developments in numerical methods. Results are presented that indicate the efficiency of the Matrix-Free Newton Krylov method for these fully-coupled, nonlinear integro-differential equations. The use and requirement for advanced differencing is also shown. To this end, implementations of Chang-Cooper differencing and flux limited Quadratic Upstream Interpolation for Convective Kinematics (QUICK) are presented. Results are given for a fully kinetic ion-electron problem with a self consistent electric field calculated from the ion and electron distribution functions. This numerical method, including advanced differencing, provides accurate solutions, which quickly converge on workstation class machines. It is demonstrated that efficient steady-state solutions can be achieved to the non-linear integro-differential equation, obtaining quadratic convergence, without incurring the large memory requirements of an integral operator. Model problems are presented which simulate plasma impinging on a plate with both high and low neutral particle recycling typical of a divertor in a Tokamak device. These model problems demonstrate the performance of the new solution method.

  6. One-chip electronic detection of DNA hybridization using precision impedance-based CMOS array sensor.

    Science.gov (United States)

    Lee, Kang-Ho; Lee, Jeong-Oen; Sohn, Mi-Jin; Lee, Byunghun; Choi, Suk-Hwan; Kim, Sang Kyu; Yoon, Jun-Bo; Cho, Gyu-Hyeong

    2010-12-15

    This paper describes a label-free and fully electronic detection method of DNA hybridization, which is achieved through the use of a 16×8 microarray sensor in conjunction with a new type of impedance spectroscopy constructed with standard complementary metal-oxide-semiconductor (CMOS) technology. The impedance-based method is based on changes in the reactive capacitance and the charge-transfer resistance after hybridization with complementary DNA targets. In previously published label-free techniques, the measured capacitance presented unstable capacitive properties due to the parallel resistance that is not infinite and can cause a leakage by discharging the charge on the capacitor. This paper presents an impedance extraction method that uses excitation by triangular wave voltage, which enables a reliable measurement of both C and R producing a highly sensitive sensor with a stable operation independent of external variables. The system was fabricated in an industrial 0.35-μm 4-metal 2-poly CMOS process, integrating working electrodes and readout electronics into one chip. The integrated readout, which uses a parasitic insensitive integrator, achieves an enlarged detection range and improved noise performance. The maximum average relative variations of C and R are 31.5% and 68.6%, respectively, after hybridization with a 1 μM target DNA. The proposed sensor allows quantitative evaluation of the molecule densities on the chip with distinguishable variation in the impedance. This fully electronic microsystem has great potential for use with bioanalytical tools and point-of-care diagnosis.

  7. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  8. Metrology Of Silicide Contacts For Future CMOS

    Science.gov (United States)

    Zollner, Stefan; Gregory, Richard B.; Kottke, M. L.; Vartanian, Victor; Wang, Xiang-Dong; Theodore, David; Fejes, P. L.; Conner, J. R.; Raymond, Mark; Zhu, Xiaoyan; Denning, Dean; Bolton, Scott; Chang, Kyuhwan; Noble, Ross; Jahanbani, Mohamad; Rossow, Marc; Goedeke, Darren; Filipiak, Stan; Garcia, Ricardo; Jawarani, Dharmesh; Taylor, Bill; Nguyen, Bich-Yen; Crabtree, P. E.; Thean, Aaron

    2007-09-01

    Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid-gap silicide, i.e., the Fermi level of the NiSi metal is pinned half-way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source-drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band-edge silicides, such as PtSi for contacts to p-type or rare earth silicides for contacts to n-type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufacturing, with special emphasis on x-ray reflectance and x-ray fluorescence. We also report measurement methods useful for development of a PtSi PMOS module.

  9. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  10. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  11. Design of Current steering DAC using 250nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Vineet Tiwari

    2012-06-01

    applied at the reference terminal. Analog to digital converter performs the reverse operation. It has many era of operations in audio and Video form and whiffletree electromagnetic device uses DAC linkage in typewriter. It describes the 3.3 volt, 65 MHz 8 bit CMOS digital to analog converter, includes two stage current cell matrix. This paper describes a 1v CMOS 8 bit DAC with two stage current cell matrix architecture which consists of 4 MSB and 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the no of high swing current mirrors. The designed DAC with a by 90 nm nwell CMOS standard process. The experiment is based on settling time, Integrity, or non linearity. The designed DAC is fully operational for power supply down to 1 volt such that DAC is suitable for low voltage and low power applications.

  12. Second-order sigma-delta modulator in standard cmos technology

    Directory of Open Access Journals (Sweden)

    Milovanović Dragiša

    2004-01-01

    Full Text Available As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 µm technology.

  13. Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0.25 μm 2.5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

  14. A high-speed CMOS current op amp for very low supply voltage operation

    DEFF Research Database (Denmark)

    Bruun, Erik

    1994-01-01

    A CMOS implementation of a high-gain current mode operational amplifier (op amp) with a single-ended input and a differential output is described. This configuration is the current mode counterpart of the traditional voltage mode op amp. In order to exploit the inherent potential for high speed......, low voltage operation normally associated with current mode analog signal processing, the op amp has been designed to operate off a supply voltage of 1.5 V, and the signal path has been confined to N-channel transistors. With this design, a gain of 94 dB and a gain-bandwidth product of 65 MHz has been...

  15. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  16. Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

    Science.gov (United States)

    Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

    2016-12-21

    One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

  17. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  18. A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

    Directory of Open Access Journals (Sweden)

    Mauro Olivieri

    2013-01-01

    Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

  19. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  20. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  1. Design of A Low Power Low Voltage CMOS Opamp

    CERN Document Server

    Baruah, Ratul Kr

    2010-01-01

    In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp ...

  2. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  3. Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Li Di; Yang Yintang; Shi Lichun; Wu Xiaofeng

    2009-01-01

    This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.

  4. A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 {mu}m CMOS for OFDM-UWB

    Energy Technology Data Exchange (ETDEWEB)

    Zheng Renliang; Ren Junyan; Li Wei; Li Ning, E-mail: jyren@fudan.edu.c [Micro/Nano Science and Innovation Platform, State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-12-15

    A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18 {mu}m RF CMOS process with an area of 1.74 mm{sup 2} and only consumes 32 mA current (at 1.8 V) including the test associated parts. (semiconductor integrated circuits)

  5. A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

    Energy Technology Data Exchange (ETDEWEB)

    Meng Lingbu; Lu Lei; Zhao Wei; Tang Zhangwen, E-mail: zwtang@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-07-15

    This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7{sup 0} in integer-N mode and less than 1{sup 0} in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm{sup 2} in a 0.18-{mu}m CMOS process.

  6. A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

    Science.gov (United States)

    Lingbu, Meng; Lei, Lu; Wei, Zhao; Zhangwen, Tang

    2010-07-01

    This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7° in integer-N mode and less than 1° in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-μm CMOS process.

  7. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  8. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  9. A monolithically integrated torsional CMOS-MEMS relay

    Science.gov (United States)

    Riverola, M.; Sobreviela, G.; Torres, F.; Uranga, A.; Barniol, N.

    2016-11-01

    We report experimental demonstrations of a torsional microelectromechanical (MEM) relay fabricated using the CMOS-MEMS approach (or intra-CMOS) which exploits the full foundry inherent characteristics enabling drastic reduction of the fabrication costs and batch production. In particular, the relay is monolithically integrated in the back end of line of a commercial standard CMOS technology (AMS 0.35 μm) and released by means of a simple one-step mask-less wet etching. The fabricated torsional relay exhibits an extremely steep switching behaviour symmetrical about both contact sides with an on-state contact resistance in the k Ω -range throughout the on-off cycling test.

  10. Design of Low Voltage Low Power CMOS OP-AMP

    OpenAIRE

    2014-01-01

    Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipa...

  11. High-speed multicolor photometry with CMOS cameras

    CERN Document Server

    Pokhvala, S M; Reshetnyk, V M

    2012-01-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11" on Peak Terskol. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR color system of CMOS sensors is close to the Johnson BVR system. The results of testing show that we can measure the stars up to V $\\simeq$ 14 with the precision of 0.01 mag. Stars up to magnitude V $\\sim$ 10 can shoot at 24 frames per second in the video mode.

  12. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  13. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  14. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise...... model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...

  15. CMOS imager for pointing and tracking applications

    Science.gov (United States)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  16. IMEC pushes the limits of CMOS

    Directory of Open Access Journals (Sweden)

    George Marsh

    2002-06-01

    Visionary stuff, but although the day of the cyborg may still be some way off, IMEC (Inter-University MicroElectronics Centre — Europe’s leading independent microelectronics research organization — sees its role as expediting some aspects of this future. This means, inter alia, a dedication to maintaining the currency of Moore’s Law, in the belief that this can continue for several years yet before fundamental limits impose insurmountable barriers. Success will require further extension of the boundaries of complementary metal oxide silicon (CMOS, that backbone of mainstream electronic technology. Materials, both the manipulation of existing and development of new, are germane to this, as Materials Today discovered on a recent visit.

  17. CMOS digital pixel sensors: technology and applications

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  18. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  19. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  20. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    Institute of Scientific and Technical Information of China (English)

    ZHANG Guo-An; ZHANG Dong-Wei; HE Jin; SU Yan-Mei; WANG Cheng; CHEN Qin; LIANG Hai-Lang; YE Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1T CMOS APS) architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus,the reset and selected transistors can be removed. In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

  1. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  2. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  3. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

    2016-01-01

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

  4. Failures Of CMOS Devices At Low Radiation-Dose Rates

    Science.gov (United States)

    Goben, Charles A.; Price, William E.

    1990-01-01

    Method for obtaining approximate failure-versus-dose-rate curves derived from experiments on failures of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated circuits irradiated by Co60 and Cs137 radioactive sources.

  5. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  6. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...... poor performance compared to the bipolar designs, but CMOS has a potential for CFB op-amp design if more ingenious circuit configurations are applied...

  7. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  8. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    D Contarato; J-M Bussat; P Denes; L Griender; T Kim; T Stezeberger; H Weiman; M Battaglia; B Hooberman; L Tompkins

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  9. High swing CMOS realization for third generation current conveyor (CCIII)

    OpenAIRE

    Minaei, Shahram; Yıldız, Merih; Türköz, Sait; Kuntman, Hakan

    2003-01-01

    In this paper a new CMOS realization for third generation current conveyor (CCIII) is proposed. The proposed circuit provides high swing range at terminals X and Y. The circuit has low input impedances at terminals X and Y and high output impedance at terminals Z+ and Z-. The circuit has 180MHz -3dB cutoff frequency in voltage follower mode. SPICE simulation results using MIETEC 1.2 CMOS process model are given.

  10. Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

    Science.gov (United States)

    2013-04-01

    Red, Green, Blue, Yellow, Magenta, Cyan) averaged CIE Delta-E 2000 = 16.6-19.3 after a white balance and color matrix correction is applied to the...insertion loss and also metal-insulator-metal waveguides; iii) developed a full format CMOS image sensor with plasmonic color filters; iv) explored... color filters and demonstration of imaging. v. Design of a plasMOStor plasmonic switching device, with low insertion loss, implemented in CMOS Si

  11. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  12. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  13. Chordal Graphs are Fully Orientable

    CERN Document Server

    Lai, Hsin-Hao

    2012-01-01

    Suppose that D is an acyclic orientation of a graph G. An arc of D is called dependent if its reversal creates a directed cycle. Let m and M denote the minimum and the maximum of the number of dependent arcs over all acyclic orientations of G. We call G fully orientable if G has an acyclic orientation with exactly d dependent arcs for every d satisfying m <= d <= M. A graph G is called chordal if every cycle in G of length at least four has a chord. We show that all chordal graphs are fully orientable.

  14. A study of phase noise in colpitts and LC-tank CMOS oscillators

    DEFF Research Database (Denmark)

    Andreani, Pietro; Wang, Xiaoyan; Vandi, Luca

    2005-01-01

    This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f(2) phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under...... very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes...... of both Colpitts and LC-tank oscillators have been implemented in a 0.35-mu m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of similar to 189 d...

  15. A construction of fully diverse unitary space-time codes

    Institute of Scientific and Technical Information of China (English)

    YU Fei; TONG HongXi

    2009-01-01

    Fully diverse unitary space-time codes are useful in multiantenna communications,especially in multiantenna differential modulation.Recently,two constructions of parametric fully diverse unitary space-time codes for three antennas system have been introduced.We propose a new construction method based on the constructions.In the present paper,fully diverse codes for systems of odd prime number antennas are obtained from this construction.Space-time codes from present construction are found to have better error performance than many best known ones.

  16. A construction of fully diverse unitary space-time codes

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    Fully diverse unitary space-time codes are useful in multiantenna communications, especially in multiantenna differential modulation. Recently, two constructions of parametric fully diverse unitary space-time codes for three antennas system have been introduced. We propose a new construction method based on the constructions. In the present paper, fully diverse codes for systems of odd prime number antennas are obtained from this construction. Space-time codes from present construction are found to have better error performance than many best known ones.

  17. A CMOS pressure sensor with integrated interface for passive RFID applications

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

    2014-12-01

    This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18 μm CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2 fF kPa-1. The sensor interface consumes only 1.1 µW of power at 0.5 V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

  18. Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

    Directory of Open Access Journals (Sweden)

    Ler Chun Lee

    2008-01-01

    Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

  19. In vitro and in vivo on-chip biofluorescence imaging using a CMOS image sensor

    Science.gov (United States)

    Ng, David C.; Matsuo, Masamichi; Tokuda, Takashi; Kagawa, Keiichiro; Nunoshita, Masahiro; Ohta, Jun

    2006-02-01

    We have designed and fabricated a 176×144-pixels (QCIF) CMOS image sensor for on-chip bio-fluorescence imaging of the mouse brain. In our approach, a single CMOS image sensor chip without additional optics is used. This enables imaging at arbitrary depths into the brain; a clear advantage compared to existing optical microscopy methods. Packaging of the chip represents a challenge for in vivo imaging. We developed a novel packaging process whereby an excitation filter is applied onto the sensor. This eliminates the use of a filter cube found in conventional fluorescence microscopes. The fully packaged chip is about 350 μm thick. Using the device, we demonstrated in vitro on-chip fluorescence imaging of a 400 μm thick mouse brain slice detailing the hippocampus. The image obtained compares favorably to the image captured by conventional microscopes in terms of image resolution. In order to study imaging in vivo, we also developed a phantom media. In situ fluorophore measurement shows that detection through the turbid medium of up to 1 mm thickness is possible. We have successfully demonstrated imaging deep into the hippocampal region of the mouse brain where quantitative fluorometric measurements was made. This work is expected to lead to a promising new tool for imaging the brain in vivo.

  20. Integration of III-V materials and Si-CMOS through double layer transfer process

    Science.gov (United States)

    Lee, Kwang Hong; Bao, Shuyu; Fitzgerald, Eugene; Tan, Chuan Seng

    2015-03-01

    A method to integrate III-V compound semiconductor and SOI-CMOS on a common Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III-V/Si hybrid structure on a common substrate. Through this method, high temperature III-V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damage to the CMOS layer is avoided.

  1. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  2. An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

    Institute of Scientific and Technical Information of China (English)

    Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

    2009-01-01

    One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a twostage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 X 200 μm2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

  3. High-speed charge transfer pinned-photodiode for a CMOS time-of-flight range image sensor

    Science.gov (United States)

    Takeshita, Hiroaki; Sawada, Tomonari; Iida, Tetsuya; Yasutomi, Keita; Kawahito, Shoji

    2010-01-01

    This paper presents a structure and method of range calculation for CMOS time-of-flight(TOF) range image sensors using pinned photodiodes. In the proposed method, a LED light with short pulse width and small duty ratio irradiates the objects and a back-reflected light is received by the CMOS TOF range imager.Each pixel has a pinned photodiode optimized for high speed charge transfer and unwanted charge draining. In TOF range image sensors, high speed charge transfer from the light receiving part to a charge accumulator is essential.It was found that the fastest charge transfer can be realized when the lateral electric field along the axis of charge transfer is constant and this conditon is met when the shape of the diode exactly follows the relationship between the fully-depleted potential and width. A TOF range imager prototype is designed and implemented with 0.18um CMOS image sensor technology with pinned photodiode 4transistor(T) pixels. The measurement results show that the charge transfer time is a few ns from the pinned photodiode to a charge accumulator.

  4. Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

    Institute of Scientific and Technical Information of China (English)

    Liu Hong-Xia; Li Jin; Li Bin; Cao Lei; Yuan Bo

    2011-01-01

    This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer.The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model,the new structure also provides the basic designing guidance for further immunity of short channel effect and drain-induced barrier-lowering of CMOS-based devices in nanometre scale.

  5. A Fully Integrated RF-Powered Contact Lens With a Single Element Display.

    Science.gov (United States)

    Pandey, J; Yu-Te Liao; Lingley, Andrew; Mirjalili, R; Parviz, B; Otis, B

    2010-12-01

    We present progress toward a wirelessly-powered active contact lens comprised of a transparent polymer substrate, loop antenna, power harvesting IC, and micro-LED. The fully integrated radio power harvesting and power management system was fabricated in a 0.13 μm CMOS process with a total die area of 0.2 mm(2). It utilizes a small on-chip capacitor for energy storage to light up a micro-LED pixel. We have demonstrated wireless power transfer at 10 cm distance using the custom IC and on-lens antenna.

  6. CMOS多通道芯片%CMOS Multi-Channel Chips

    Institute of Scientific and Technical Information of China (English)

    康凯; 高宗智

    2016-01-01

    In order to overcome a number of challenges in CMOS millimeter-wave integrated circuit design, the millimeter-wave device modeling, antenna design, circuit block, and multi-channel transceiver system are introduced in this paper. The equivalent-circuit models of millimeter-wave on-chip interconnected lines, multiple-coupled inductors, six-portM:N transformers, and the model of terahertz active device are studied and proposed, respectively. Moreover, a low noise amplifier with noise canceling and a power amplifier with a fully symmetrical distributed active transformer are introduced in this paper. Furthermore, the CMOS 60 GHz receiver with on-chip antenna and the multi-channel phase array transceiver are described, respectively.%针对互补金属氧化物半导体(CMOS)工艺在毫米波集成电路设计中存在的诸多挑战,分别从毫米波器件建模和天线设计,毫米波电路模块设计和多通道收发系统设计方面进行介绍,以克服相应挑战。该文研究和建立了毫米波频段片上互连线,耦合电感和六端口M:N变压器的等效模型和太赫兹有源器件模型,并对毫米波片上天线进行设计;介绍了基于噪声抵消的低噪声放大器电路和基于全对称平衡分布式有源变压器的功率放大器电路、毫米波移相器电路以及集成片上天线的CMOS 60 GHz接收机和多通道相控阵收发系统。

  7. LC-Oscillator for 94 GHz Automotive Radar System Fabricated in SiGe:C BiCMOS Technology

    OpenAIRE

    2004-01-01

    This paper presents the design and measurement of a voltage-controlled oscillator (VCO) for the use in a 94 GHz automotive radar system and other applications. The oscillator has been fabricated in a 200 GHz SiGe:C BiCMOS technology with 0.25 µm minimum feature size. The oscillator is fully integrated on a single chip with a chip area of only 0.25 mm2. The fabricated oscillator has a tuning range of 2.2 GHz and a supply voltage of -3 Volt.

  8. On noise in time-delay integration CMOS image sensors

    Science.gov (United States)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  9. CMOS SiPM with integrated amplifier

    Science.gov (United States)

    Schwinger, Alexander; Brockherde, Werner; Hosticka, Bedrich J.; Vogt, Holger

    2017-02-01

    The integration of silicon photomultiplier (SiPM) and frontend electronics in a suitable optoelectronic CMOS process is a promising approach to increase the versatility of single-photon avalanche diode (SPAD)-based singlephoton detectors. By integrating readout amplifiers, the device output capacitance can be reduced to minimize the waveform tail, which is especially important for large area detectors (>10 × 10mm2). Possible architectures include a single readout amplifier for the whole detector, which reduces the output capacitance to 1:1 pF at minimal reduction in detector active area. On the other hand, including a readout amplifier in every SiPM cell would greatly improve the total output capacitance by minimizing the influence of metal routing parasitic capacitance, but requiring a prohibitive amount of detector area. As tradeoff, the proposed detector features one readout amplifier for each column of the detector matrix to allow for a moderate reduction in output capacitance while allowing the electronics to be placed in the periphery of the active detector area. The presented detector with a total size of 1.7 ♢ 1.0mm2 features 400 cells with a 50 μm pitch, where the signal of each column of 20 SiPM cells is summed in a readout channel. The 20 readout channels are subsequently summed into one output channel, to allow the device to be used as a drop-in replacement for commonly used analog SiPMs.

  10. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  11. A CMOS readout circuit for microstrip detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  12. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  13. Low Power CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Sujata Pandey,

    2010-08-01

    Full Text Available Here, two new designs of CMOS digitally controlled oscillators (DCO for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and withtwo NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 - 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 - 700.2977] μW and [617.6616 -6 77.3996] μW respectively.

  14. NSC 800, 8-bit CMOS microprocessor

    Science.gov (United States)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  15. CMOS circuits for electromagnetic vibration transducers interfaces for ultra-low voltage energy harvesting

    CERN Document Server

    Maurath, Dominic

    2015-01-01

    Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100µW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over...

  16. Low Power Designing of PLL with 0.125μm CMOS technology

    Directory of Open Access Journals (Sweden)

    Divya Patel Yash Kshirsagar

    2011-10-01

    Full Text Available This paper deals with the designing of Low Power PLL by reducing power consumtion of VCO to generate well-timed on chip clock signals for digital signals. Switching of digital system introduce power supply or substrate noise which perturb the more sensitive blocks in VCO and clock buffer. Since power dissipation in PLL is small fraction of total active power but it increase with increasing operating frequency of digital system. This paper is describing the design of a fully-integrated low-jitter PLL for low power application. To achieve the low jitter performance, our work is proposed on jitter reduction method on both system and circuit level. The results are verified for both circuit and system level. The PLL is implemented in 0.25μm CMOS technology and consumes 10mW from a 2.5V supply

  17. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  18. A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

    Energy Technology Data Exchange (ETDEWEB)

    Zheng Yongzheng; Xia Lingli; Li Weinan; Huang Yumei; Hong Zhiliang, E-mail: yumeihuang@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-09-15

    A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 {mu}m CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 x 1.8 mm{sup 2}.

  19. 7~11GHz CMOS环形压控振荡器的设计%Design of a 7-11 GHz Ring VCO Based on CMOS Process

    Institute of Scientific and Technical Information of China (English)

    何芝兰; 段吉海

    2011-01-01

    设计了一种全集成差分高速环形压控振荡器(VCO).采用三级延迟单元环路复用结构,通过正反馈技术以及改变负载电阻值的方法,有效优化延迟单元;采用双控制电压粗/细调谐方式,实现振荡器高频率、低功耗的要求.在SMIC 0.18μm CMOS RF工艺模型下,采用ADS软件对振荡电路进行仿真,在外接电源电压Vdd=1.8 V时,输出频率的调谐范围为7.32~11.07 GHz,当频率为11 GHz时,在偏离中心频率1 MHz处相位噪声为-88.32 dBc/Hz,在偏离中心频率10MHz处相位噪声为-112.7 dBc/Hz,平均功耗为63.5 mW.该VCO可应用于锁相环和雷达通信系统.%A fully integrated differential high-speed ring voltage-controlled oscillator (VCO) was designed, which was comprised of three-stage delay cell with multi-loop structure. The delay cell was optimized by using positive feedback and modifying load resistance value. In this circuit, high frequency and low power was realized by coarse/ fine frequency control. Based on SMIC's 0.18 um 1P6M CMOS process model, the VCO was simulated with ADS. At 1. 8 V supply voltage, the VCO had a linear tuning range from 7. 32 GHz to 11. 07 GHz. Simulation results showed that, for an oscillating frequency of 11 GHz, the circuit had a phase noise of -88. 32 dBc/Hz and -112. 7 dBc/Hz at 1 MHz and 10 MHz off center frequency, respectively, with an average power of 63. 5 mW.

  20. CMOS Cell Sensors for Point-of-Care Diagnostics

    Directory of Open Access Journals (Sweden)

    Haluk Kulah

    2012-07-01

    Full Text Available The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS. CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  1. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  2. CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria.

    Science.gov (United States)

    Lei Yao; Lamarche, P; Tawil, N; Khan, R; Aliakbar, A M; Hassan, M H; Chodavarapu, V P; Mandeville, R

    2011-06-01

    We present the design and implementation of a prototype complementary metal-oxide semiconductor (CMOS) conductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The detection of E. coli is done by employing T4 bacteriophages as receptor organisms. The conductometric system operates by measuring the resistance of the test sample between the electrodes of a two-electrode electrochemical system (reference electrode and working electrode). The CMOS IC is fabricated in a TSMC 0.35-μm process and uses a current-to-frequency (I to F) conversion circuit to convert the test sample resistance into a digital output modulated in frequency. Pulsewidth control (one-shot circuit) is implemented on-chip to control the pulsewidth of the output digital signal. The novelty in the current work lies in the ability of the CMOS sensor system to monitor very low initial concentrations of bacteria (4×10(2) to 4×10(4) colony forming unit (CFU)/mL). The CMOS system is also used to record the interaction between E. coli and its specific receptor T4 bacteriophage. The prototype CMOS IC consumes an average power of 1.85 mW with a 3.3-V dc power supply.

  3. CMOS cell sensors for point-of-care diagnostics.

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  4. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  5. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  6. Figures of merit for CMOS SPADs and arrays

    Science.gov (United States)

    Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

    2013-05-01

    SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

  7. Hybrid CMOS / Microfluidic Systems for Cell Manipulation with Dielectrophoresis

    Science.gov (United States)

    Hunt, Tom; Issadore, David; Westervelt, Robert M.

    2007-03-01

    A hybrid CMOS/microfluidic chip combines the biocompatibility of microfluidics with the built-in logic, programmability, and sensitivity of CMOS integrated circuits (ICs)^1 We have designed a CMOS IC for moving individual cells using dielectrophoresis (DEP). The IC was built in a commercial foundry and we subsequently fabricated a microfluidic chamber on the top surface. The chip consists of a 1.4 by 2.8mm array of over 32,000 individually addressable 11x11 micron pixels. An RF voltage of 5V at 10MHz can be applied to each pixel with respect to the conductive lid of the microfluidic chamber, producing a localized electric field that can trap a cell. By shifting the location of energized pixels, the array can trap and move cells along programmable paths through the microfluidic chamber. We show the design, fabrication, and testing of the hybrid chip. Bringing together the biocompatibility of microfluidics and the power of CMOS chips, hybrid CMOS / microfluidic systems are an exciting technology for biomedical research. Thanks to NSEC NSF grant PHY-0117795 and the NCI MIT-Harvard CCNE. [1] H Lee, Y Liu, RM Westervelt, D Ham, IEEE JSSC 41, 6, pp. 1471-1480, 2006

  8. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  9. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  10. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Liu, Wei; Kovalgin, Alexey Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  11. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Science.gov (United States)

    2012-12-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors and...

  12. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    Science.gov (United States)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

  13. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  14. Operation and biasing for single device equivalent to CMOS

    Science.gov (United States)

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  15. High-speed polysilicon CMOS photodetector for telecom and datacom

    Science.gov (United States)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  16. CMOS biosensors for in vitro diagnosis - transducing mechanisms and applications.

    Science.gov (United States)

    Lei, Ka-Meng; Mak, Pui-In; Law, Man-Kay; Martins, Rui P

    2016-09-21

    Complementary metal oxide semiconductor (CMOS) technology enables low-cost and large-scale integration of transistors and physical sensing materials on tiny chips (e.g., key functions of biosensors: transducing and signal processing. Recent CMOS biosensors unified different transducing mechanisms (impedance, fluorescence, and nuclear spin) and readout electronics have demonstrated competitive sensitivity for in vitro diagnosis, such as detection of DNA (down to 10 aM), protein (down to 10 fM), or bacteria/cells (single cell). Herein, we detail the recent advances in CMOS biosensors, centering on their key principles, requisites, and applications. Together, these may contribute to the advancement of our healthcare system, which should be decentralized by broadly utilizing point-of-care diagnostic tools.

  17. Piezoresistive Sensors Development Using Monolithic CMOS MEMS Technology

    Directory of Open Access Journals (Sweden)

    A. Chaehoi

    2011-04-01

    Full Text Available This paper presents the development of a monolithic CMOS-MEMS platform under the iDesign and SemeMEMS projects with the aim of jointly providing an open access “one-stop-shop” design and prototyping facility for integrated CMOS-MEMS. This work addresses the implementation of a 3-axis accelerometer and a pressure sensor using Semefab’s in-house 2-poly 1-metal CMOS process on a 380/4/15 μm SOI wafer; the membrane and the proof mass being micromachined using double-sided Deep Reactive Ion Etching (DRIE. This monolithic approach promises, in high volume production and using low complexity processes, a dramatic cost reduction over hybrid sensors. Furthermore, the embedded signal conditioning and the low-noise level in polysilicon gauges enables high performance to be achieved by implementing dedicated on-chip amplification and filtering circuitry.

  18. Ultra High-Speed CMOS Circuits Beyond 100 GHz

    CERN Document Server

    Gharavi, Sam

    2012-01-01

    The book covers the CMOS-based millimeter wave circuits and devices and presents methods and design techniques to use CMOS technology for circuits operating beyond 100 GHz.� Coverage includes a detailed description of both active and passive devices, including modeling techniques and performance optimization. Various mm-wave circuit blocks are discussed, emphasizing their design distinctions from low-frequency design methodologies. This book also covers a device-oriented circuit design technique that is essential for ultra high speed circuits and gives some examples of device/circuit co-design that can be used for mm-wave technology. Offers a detailed description of high frequency device modeling from a circuit designer perspective; Presents a set of techniques for optimizing the performance of CMOS for mm-wave technology, including noise and low noise design for mm-wave; Introduces circuit/device co-design techniques. �

  19. Design of Low Voltage Low Power CMOS OP-AMP

    Directory of Open Access Journals (Sweden)

    Shahid Khan,

    2014-11-01

    Full Text Available Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.

  20. Electroplated solenoid-type inductors for CMOS rf CO

    Science.gov (United States)

    Nam, Chul; Choi, Wonseo; Chun, KukJin

    2000-10-01

    A Solenoid-type Inductors have been realized using electroplating technique mainly used for 2 Ghz band CMOS RF VCO applications. The integrated spiral inductor has low Q factor due to substrate loss and skin effects. And it also occupies large area compared to solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower substrate loss and other interference with integrated passive components. In this research, Solenoid-type inductors are simulated and modeled as equivalent circuit for CMOS RF VCO based on extracted S- parameters. The electroplated solenoid-type inductors are fabricated on both a standard silicon substrate and glass substrate by thick PR photolithography and copper electroplating. The achieved inductance varies range from 1 nH to 5 nH, and maximum Q factor over 10. The inductors are scheduled to be integrated on CMOS RF VCO with RF MEMS capacitor for future.

  1. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  2. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri......This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation...... of the electrical parameters of n-channel and p-channel transistors. The magnetron sputtering technique is shown to be compatible with standard CMOS electronics without any restriction of the metal types and annealing requirements....

  3. Design of CMOS logic gates for TID radiation

    Science.gov (United States)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  4. Radiation imaging with a new scintillator and a CMOS camera

    Science.gov (United States)

    Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

    2014-07-01

    A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

  5. CMOS reliability issues for emerging cryogenic Lunar electronics applications

    Science.gov (United States)

    Chen, Tianbing; Zhu, Chendong; Najafizadeh, Laleh; Jun, Bongim; Ahmed, Adnan; Diestelhorst, Ryan; Espinel, Gustavo; Cressler, John D.

    2006-06-01

    We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

  6. Architectures for Low-noise CMOS Electronic Imaging

    Science.gov (United States)

    Kawahito, Shoji

    This chapter discusses various types of signal readout architectures for CMOS image sensors, implementing ultra-low-noise conversion of photo-generated charge packets into digital output values. It is based on a detailed analysis of the different noise sources in a CMOS imager, the noise responses of column noise cancelling circuits using correlated double sampling (CDS) and correlated multiple sampling (CMS) techniques and a noiseless signal readout technique using a precise digitizer. Finally, a practical example for the design of a CMOS image sensor with single-photon resolution is presented, and the technological requirements for meeting the condition for room-temperature readout noise of significantly less than 1 electron are discussed.

  7. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    Science.gov (United States)

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-05

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. A low-power column-parallel ADC for high-speed CMOS image sensor

    Science.gov (United States)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  9. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  10. Physics of Fully Depleted CCDs

    CERN Document Server

    Holland, S E; Kolbe, W F; Lee, J S

    2014-01-01

    In this work we present simple, physics-based models for two effects that have been noted in the fully depleted CCDs that are presently used in the Dark Energy Survey Camera. The first effect is the observation that the point-spread function increases slightly with the signal level. This is explained by considering the effect on charge-carrier diffusion due to the reduction in the magnitude of the channel potential as collected signal charge acts to partially neutralize the fixed charge in the depleted channel. The resulting reduced voltage drop across the carrier drift region decreases the vertical electric field and increases the carrier transit time. The second effect is the observation of low-level, concentric ring patterns seen in uniformly illuminated images. This effect is shown to be most likely due to lateral deflection of charge during the transit of the photogenerated carriers to the potential wells as a result of lateral electric fields. The lateral fields are a result of space charge in the fully...

  11. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  12. A 65 nm CMOS LNA for Bolometer Application

    Science.gov (United States)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  13. A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

    Directory of Open Access Journals (Sweden)

    Mrs. Devendra Rani

    2012-06-01

    Full Text Available Voltage-Controlled Ring Oscillators are crucial components in many wireless communication systems. The goal of this project is to design a high speed and lower power consumption, a voltage controlled oscillator (VCO, based on ring oscillators in 250nm CMOS technology, which provides a frequency of 2.4GHz. This CMOS based VCO is used for high speed wireless communication applications. A design of VCO includes delay cell, bias circuitry, and tuning circuitry using Tanner 13.0v software.

  14. Modifications in CMOS Dynamic Logic Style: A Review Paper

    Science.gov (United States)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  15. Statistical circuit design for yield improvement in CMOS circuits

    Science.gov (United States)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  16. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  17. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  18. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  19. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  20. CMOS-compatible photonic devices for single-photon generation

    Science.gov (United States)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  1. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  2. DMAPS: a fully depleted monolithic active pixel sensor - analog performance characterization

    CERN Document Server

    Havránek, Miroslav; Krüger, Hans; Fu, Yunan; Germic, Leonard; Kishishita, Tetsuichi; Obermann, Theresa; Wermes, Norbert

    2014-01-01

    Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10-15 $\\mu$m) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal is small ($\\approx$ 1000 e$^-$) and the radiation tolerance is much below the LHC requirements by factors of 100 to 1000. In this paper we present the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a test chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (50 $\\mu$m) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry i...

  3. DMAPS: a fully depleted monolithic active pixel sensor—analog performance characterization

    Science.gov (United States)

    Havránek, M.; Hemperek, T.; Krüger, H.; Fu, Y.; Germic, L.; Kishishita, T.; Marinas, C.; Obermann, T.; Wermes, N.

    2015-02-01

    Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10-15 μm) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal of these conventional MAPS is small (≈1000 e-) and the radiation tolerance is limited. In this paper, the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume is presented. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a prototype chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (≈50 μm) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry inside the pixel. Different matrix types with several variants of collection electrodes and pixel electronics have been implemented. Measurements of the analog performance of this first implementation of DMAPS pixels are presented.

  4. Fully integrated, fully automated generation of short tandem repeat profiles

    Science.gov (United States)

    2013-01-01

    Background The generation of short tandem repeat profiles, also referred to as ‘DNA typing,’ is not currently performed outside the laboratory because the process requires highly skilled technical operators and a controlled laboratory environment and infrastructure with several specialized instruments. The goal of this work was to develop a fully integrated system for the automated generation of short tandem repeat profiles from buccal swab samples, to improve forensic laboratory process flow as well as to enable short tandem repeat profile generation to be performed in police stations and in field-forward military, intelligence, and homeland security settings. Results An integrated system was developed consisting of an injection-molded microfluidic BioChipSet cassette, a ruggedized instrument, and expert system software. For each of five buccal swabs, the system purifies DNA using guanidinium-based lysis and silica binding, amplifies 15 short tandem repeat loci and the amelogenin locus, electrophoretically separates the resulting amplicons, and generates a profile. No operator processing of the samples is required, and the time from swab insertion to profile generation is 84 minutes. All required reagents are contained within the BioChipSet cassette; these consist of a lyophilized polymerase chain reaction mix and liquids for purification and electrophoretic separation. Profiles obtained from fully automated runs demonstrate that the integrated system generates concordant short tandem repeat profiles. The system exhibits single-base resolution from 100 to greater than 500 bases, with inter-run precision with a standard deviation of ±0.05 - 0.10 bases for most alleles. The reagents are stable for at least 6 months at 22°C, and the instrument has been designed and tested to Military Standard 810F for shock and vibration ruggedization. A nontechnical user can operate the system within or outside the laboratory. Conclusions The integrated system represents the

  5. Fully automated (operational) modal analysis

    Science.gov (United States)

    Reynders, Edwin; Houbrechts, Jeroen; De Roeck, Guido

    2012-05-01

    Modal parameter estimation requires a lot of user interaction, especially when parametric system identification methods are used and the modes are selected in a stabilization diagram. In this paper, a fully automated, generally applicable three-stage clustering approach is developed for interpreting such a diagram. It does not require any user-specified parameter or threshold value, and it can be used in an experimental, operational, and combined vibration testing context and with any parametric system identification algorithm. The three stages of the algorithm correspond to the three stages in a manual analysis: setting stabilization thresholds for clearing out the diagram, detecting columns of stable modes, and selecting a representative mode from each column. An extensive validation study illustrates the accuracy and robustness of this automation strategy.

  6. Singularities in fully developed turbulence

    Energy Technology Data Exchange (ETDEWEB)

    Shivamoggi, Bhimsen K., E-mail: bhimsen.shivamoggi@ucf.edu

    2015-09-18

    Phenomenological arguments are used to explore finite-time singularity (FTS) development in different physical fully-developed turbulence (FDT) situations. Effects of spatial intermittency and fluid compressibility in three-dimensional (3D) FDT and the role of the divorticity amplification mechanism in two-dimensional (2D) FDT and quasi-geostrophic FDT and the advection–diffusion mechanism in magnetohydrodynamic turbulence are considered to provide physical insights into the FTS development in variant cascade physics situations. The quasi-geostrophic FDT results connect with the 2D FDT results in the barotropic limit while they connect with 3D FDT results in the baroclinic limit and hence apparently provide a bridge between 2D and 3D. - Highlights: • Finite-time singularity development in turbulence situations is phenomenologically explored. • Spatial intermittency and compressibility effects are investigated. • Quasi-geostrophic turbulence is shown to provide a bridge between two-dimensional and three-dimensional cases.

  7. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  8. Performance Comparison of Bipolar Vs CMOS VCO in BiCMOS Technology%基于BiCMOS工艺的Bipolar VCO和CMOS VCO性能对比

    Institute of Scientific and Technical Information of China (English)

    欧阳宏志; 陈洪云; 苏旷宇

    2007-01-01

    阐述了基于BiCMOS工艺的全集成LC调谐压控振荡器的基本原理.为了比较Bipolar VCO和CMOS VCO的性能,他们很好地设计在同一块芯片上.在560M的中心频率上,CMOS VCO无论在功耗,还是在相位噪声方面都要优于Bipolar VCO,他们的电流消耗分别为3.9 mA和5.9 mA,两种VCO都是基于0.6 μm BiCMOS工艺而仿真和测量的.

  9. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  10. CMOS integrator based lock-in pixel for heterodyne interferometry

    NARCIS (Netherlands)

    Soloviev, O.; Vdovin, G.

    2005-01-01

    This article presents a prototype of a CMOS phase sensor for high accuracy (1 Angstrom) heterodyne interferometry. Switched integrators realization of a lock-in pixel for 4-bucket phase detection algorithm is described and illustrated by experimental results. Factors that limit the accuracy of this

  11. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.;

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of t...

  12. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  13. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  14. Reducing crosstalk in vertically integrated CMOS image sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2010-01-01

    Image sensors can benefit from 3D IC fabrication methods because photodetectors and electronic circuits may be fabricated using significantly different processes. When fabricating the die that contains the photodetectors, it is desirable to avoid pixel level patterning of the light sensitive semiconductor. But without a physical border between adjacent photodetectors, lateral currents may flow between neighboring devices, which is called "crosstalk". This work introduces circuits that can be used to reduce crosstalk in vertically-integrated (VI) CMOS image sensors with an unpatterned photodetector array. It treats the case of a VI-CMOS image sensor composed of a silicon die with CMOS read-out circuits and a transparent die with an unpatterned array of photodetectors. A reduction in crosstalk can be achieved by maintaining a constant electric potential at all nodes, at which the photodetector array connects with the readout circuit array. This can be implemented by designing a pixel circuit that uses an operational amplifier with a logarithmic feedback to control the voltage at the input node. The work presents several optional circuit configurations for the pixel circuit, and indicates the one that is the most power efficient. Afterwards, it uses a simplified small-signal model of the pixel circuit to address stability and compensation issues. Lastly, the method is validated through circuit simulation for a standard CMOS process.

  15. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  16. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    Science.gov (United States)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  17. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...

  18. Planar CMOS analog SiPMs: design, modeling, and characterization

    Science.gov (United States)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  19. CMOS image sensors as an efficient platform for glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-07

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

  20. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    Science.gov (United States)

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  1. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    Directory of Open Access Journals (Sweden)

    Mao-Chen Liu

    2010-02-01

    Full Text Available This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  2. A CMOS OTA for HF filters with programmable transfer function

    NARCIS (Netherlands)

    van de Zwan, Eric J.; Klumperink, Eric A.M.; Seevinck, E.; Seevinck, Evert

    1991-01-01

    A CMOS operational transconductance amplifier (OTA) for programmable HF filters is presented. When used in an OTA-C integrator, the unity-gain frequency phase error remains less than 0.3° for frequencies up to more than one tenth of the OTA bandwidth. The OTA has built-in phase compensation, which

  3. A CMOS low-noise instrumentation amplifier using chopper modulation

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...

  4. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  5. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Science.gov (United States)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  6. A CMOS image sensor with row and column profiling means

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.; Wang, X.; Leijtens, J.A.P.; Hakkesteegt, H.; Jansen, H.

    2008-01-01

    This paper describes the implementation and firstmeasurement results of a new way that obtains row and column profile data from a CMOS Image Sensor, which is developed for a micro-Digital Sun Sensor (μDSS).The basic profiling action is achieved by the pixels with p-type MOS transistors which realize

  7. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the outpu

  8. Fundamental Characteristics of a Pinned Photodiode CMOS Pixels

    NARCIS (Netherlands)

    Xu, Y.

    2015-01-01

    This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier.

  9. Design of a CMOS temperature sensor with current output

    NARCIS (Netherlands)

    Kolling, A.; Kölling, Arjan; Bak, Frans; Bergveld, Piet; Seevinck, E.; Seevinck, Evert

    1990-01-01

    In this paper a CMOS temperature-to-current converter is presented of which the output current is the difference between a PTC current and an NTC current. The PTC current is derived from a PTAT cell, while the NTC current is derived from a threshold voltage reference source. It is shown that this

  10. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  11. Gamma measurement based on CMOS sensor and ARM microcontroller

    National Research Council Canada - National Science Library

    Cheng, Qian-Qian; Yuan, Yan-Zhong; Ma, Chun-Wang; Wang, Fang

    2017-01-01

    A setup based on CMOS sensor and ARM microcontroller is designed to measure the γ-rays. STM32F103 is used as the main platform to control real-time online analysis of the image collected by the OV7670 CAMERACHIP...

  12. Chopper amplifier circuit with CMOS switches and amplifier FETs

    NARCIS (Netherlands)

    Huijsing, J.H.; Bakker, A.

    1997-01-01

    Abstract of NL 1001231 (C2) The input voltage is fed to the inputs of an operational amplifier via a chopping reversal switchThe CMOS operational amplifier has a current source and a current mirror. The operational amplifier output is fed to an output circuit. The possible offset voltage is supp

  13. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  14. Research-grade CMOS image sensors for remote sensing applications

    Science.gov (United States)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  15. A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

    Directory of Open Access Journals (Sweden)

    Hanie Ghaedrahmati

    2012-12-01

    Full Text Available A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC using a novel mirror telescopic operational amplifiers (opamp with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA into the first multiplying digital-to-analog converter (MDAC using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved

  16. A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG Signals

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  17. A 3-5 GHz CMOS UWB power amplifier with {+-}8 ps group delay ripple

    Energy Technology Data Exchange (ETDEWEB)

    Xi Tianzuo; Huang Lu; Zheng Zhong; Feng Lisong, E-mail: xitianzuo@hotmail.co [Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027 (China)

    2010-04-15

    A differential power amplifier (PA), designed using the linear-phase filter model, for a BPSK modulated ultra-wideband (UWB) system operating in the 3-5 GHz frequency range is presented. The proposed PA was fabricated using 0.18 {mu}m SMIC CMOS technology. To achieve sufficient linearity and efficiency, this PA operates in the class-AB region, delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm. It consumes 28.8 mW, realizing a flat gain of 9.11 {+-} 0.39 dB and a very low group delay ripple of {+-}8 ps across the whole band of operation. (semiconductor integrated circuits)

  18. A LOW POWER CMOS ANALOG CIRCUIT DESIGN FOR ACQUIRING MULTICHANNEL EEG SIGNALS

    Directory of Open Access Journals (Sweden)

    G. Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  19. Design of 6-Bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator

    Directory of Open Access Journals (Sweden)

    Gulrej Ahmed

    2014-04-01

    Full Text Available This paper presents the design of 6-bit flash analog to digital Converter (ADC using the new variable switching voltage (VSV comparator. In general, Flash ADCs attain the highest conversion speed at the cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of 1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral nonlinearities (DNL and INL of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.

  20. A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

    Directory of Open Access Journals (Sweden)

    Hanie Ghaedrahmat

    2013-01-01

    Full Text Available A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC using a novel mirror telescopic operational amplifiers (opamp with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA into the first multiplying digital-to-analog converter (MDAC using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved