Fully depleted back-illuminated p-channel CCD development

Energy Technology Data Exchange (ETDEWEB)

Bebek, Chris J.; Bercovitz, John H.; Groom, Donald E.; Holland, Stephen E.; Kadel, Richard W.; Karcher, Armin; Kolbe, William F.; Oluseyi, Hakeem M.; Palaio, Nicholas P.; Prasad, Val; Turko, Bojan T.; Wang, Guobin

2003-07-08

An overview of CCD development efforts at Lawrence Berkeley National Laboratory is presented. Operation of fully-depleted, back-illuminated CCD's fabricated on high resistivity silicon is described, along with results on the use of such CCD's at ground-based observatories. Radiation damage and point-spread function measurements are described, as well as discussion of CCD fabrication technologies.

Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

Science.gov (United States)

Takulapalli, Bharath R

2010-02-23

Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2016-10-01

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

Hydrogen interactions with silicon-on-insulator materials

OpenAIRE

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

Heterojunction fully depleted SOI-TFET with oxide/source overlap

Science.gov (United States)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

Science.gov (United States)

Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

2013-07-29

We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

Back-illuminated, fully-depleted CCD image sensors for use in optical and near-IR astronomy

CERN Document Server

Groom, D E; Levi, M E; Palaio, N P; Perlmutter, S; Stover, R J; Wei, M

2000-01-01

Charge-coupled devices (CCDs) of novel design have been fabricated at Lawrence Berkeley National Laboratory (LBNL), and the first large-format science-grade chips for astronomical imaging are now being characterized at Lick Observatory. They are made on 300-mu m thick n-type high-resistivity (approx 10 000 OMEGA cm) silicon wafers, using a technology developed at LBNL to fabricate low-leakage silicon microstrip detectors for high-energy physics. A bias voltage applied via a transparent contact on the back side fully depletes the substrate, making the entire volume photosensitive and ensuring that charge reaches the potential wells with minimal lateral diffusion. The development of a thin, transparent back-side contact compatible with fully depleted operation permits blue response comparable to that obtained with thinned CCDs. Since the entire region is active, high quantum efficiency is maintained to nearly lambda=1000 nm, above which the silicon band gap effectively truncates photoproduction. Early character...

First tests with fully depleted PN-CCD's

International Nuclear Information System (INIS)

Strueder, L.; Lutz, G.; Sterzik, M.; Holl, P.; Kemmer, J.; Prechtel, U.; Ziemann, T.; Rehak, P.

1987-01-01

We have fabricated 280 μm thick fully depletable pn CCD's on high resistivity silicon (/rho/ ∼ 2.5 kΩcm). Its operation is based on the semiconductor drift chamber principle proposed by Gatti and Rheak. They are designed as energy and position sensitive radiation detector for (minimum) ionizing particles and X-ray imaging. Two dimensional semiconductor device modeling demonstrates the basic charge transer mechanisms. Prototypes of the detectors have been tested in static and dynamic conditions. A preliminary charge transfer inefficiency was determined to 6 x 10/sup/minus/3/. The charge loss during the transfer is discussed and as a consequence we have developed an improved design for a second fabrication iteration which is now being produced. 4 refs., 15 figs

Total dose hardening of buried insulator in implanted silicon-on-insulator structures

International Nuclear Information System (INIS)

Mao, B.Y.; Chen, C.E.; Pollack, G.; Hughes, H.L.; Davis, G.E.

1987-01-01

Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants

Ultra-low-loss inverted taper coupler for silicon-on-insulator ridge waveguide

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Ou, Haiyan

2010-01-01

An ultra-low-loss coupler for interfacing a silicon-on-insulator ridge waveguide and a single-mode fiber in both polarizations is presented. The inverted taper coupler, embedded in a polymer waveguide, is optimized for both the transverse-magnetic and transverse-electric modes through tapering...... the width of the silicon-on-insulator waveguide from 450 nm down to less than 15 nm applying a thermal oxidation process. Two inverted taper couplers are integrated with a 3-mm long silicon-on-insulator ridge waveguide in the fabricated sample. The measured coupling losses of the inverted taper coupler...... for transverse-magnetic and transverse-electric modes are ~0.36 dB and ~0.66 dB per connection, respectively....

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

Science.gov (United States)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

Energy Technology Data Exchange (ETDEWEB)

Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

2015-10-15

The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

ARROW-based silicon-on-insulator photonic crystal waveguides with reduced losses

DEFF Research Database (Denmark)

Lavrinenko, Andrei; Novitsky, A.; Zhilko, V.V.

2006-01-01

We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits.......We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits....

Experimental and theoretical study of the signal electron motion in fully depleted silicon

International Nuclear Information System (INIS)

Kimmel, N.; Andritschke, R.; Hartmann, R.; Holl, P.; Meidinger, N.; Richter, R.; Strueder, L.

2010-01-01

Imaging spectrometers based on a fully depleted silicon substrate are sensitive over the whole device volume. Therefore, a high detection efficiency for X-rays of up to 20 keV is achieved. Our experimental method facilitates measurements of the detected signal pulse height in a pixel as a function of the photon conversion position in the pixel array. Further analysis of the measurements delivers the size of a signal electron cloud after its drift from the photon conversion position to the storage cells. These results can be used to reconstruct the conversion position of each detected X-ray photon. A reconstruction accuracy of 1μm can be achieved with a pixel size of 51μm. Complementary to the measurements, we have created a physical model of the signal electron collection process. The change of the drift mobility with the electric drift field strength in the detection volume is considered in order to correctly describe the drift speed of the charge cloud. The electric field values and the values of the charge density in the detector volume are delivered by numerical device simulations with the software package 'TeSCA'. Comparisons of the simulations with the measurements confirmed the correctness of the applied physical model. We have thus established a method which enables device designers to simulate the process of signal charge collection in future detector concepts.

Hydrogen interactions with silicon-on-insulator materials

NARCIS (Netherlands)

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously

A high-temperature silicon-on-insulator stress sensor

International Nuclear Information System (INIS)

Wang Zheyao; Tian Kuo; Zhou Youzheng; Pan Liyang; Liu Litian; Hu Chaohong

2008-01-01

A piezoresistive stress sensor is developed using silicon-on-insulator (SOI) wafers and calibrated for stress measurement for high-temperature applications. The stress sensor consists of 'silicon-island-like' piezoresistor rosettes that are etched on the SOI layer. This eliminates leakage current and enables excellent electrical insulation at high temperature. To compensate for the measurement errors caused by the misalignment of the piezoresistor rosettes with respect to the crystallographic axes, an anisotropic micromachining technique, tetramethylammonium hydroxide etching, is employed to alleviate the misalignment issue. To realize temperature-compensated stress measurement, a planar diode is fabricated as a temperature sensor to decouple the temperature information from the piezoresistors, which are sensitive to both stress and temperature. Design, fabrication and calibration of the piezoresistors are given. SOI-related characteristics such as piezoresistive coefficients and temperature coefficients as well as the influence of the buried oxide layer are discussed in detail

Nonlinear Optical Functions in Crystalline and Amorphous Silicon-on-Insulator Nanowires

DEFF Research Database (Denmark)

Baets, R.; Kuyken, B.; Liu, X.

2012-01-01

Silicon-on-Insulator nanowires provide an excellent platform for nonlinear optical functions in spite of the two-photon absorption at telecom wavelengths. Work on both crystalline and amorphous silicon nanowires is reviewed, in the wavelength range of 1.5 to 2.5 µm....

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

Science.gov (United States)

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

DEFF Research Database (Denmark)

Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

2014-01-01

We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

Science.gov (United States)

Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

2016-10-01

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Science.gov (United States)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

360° tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

DEFF Research Database (Denmark)

Pu, Minhao; Xue, Weiqi; Liu, Liu

2010-01-01

We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained......We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained...

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

Directory of Open Access Journals (Sweden)

Xiaojun Cheng

2014-05-01

Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

Science.gov (United States)

Kapoor, V. J.; Shokrani, M.

1991-01-01

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Silicon-on-Insulator Nanowire Based Optical Waveguide Biosensors

International Nuclear Information System (INIS)

Li, Mingyu; Liu, Yong; Chen, Yangqing; He, Jian-Jun

2016-01-01

Optical waveguide biosensors based on silicon-on-insulator (SOI) nanowire have been developed for label free molecular detection. This paper reviews our work on the design, fabrication and measurement of SOI nanowire based high-sensitivity biosensors employing Vernier effect. Biosensing experiments using cascaded double-ring sensor and Mach-Zehnder- ring sensor integrated with microfluidic channels are demonstrated (paper)

Flexible high-κ/Metal gate metal/insulator/metal capacitors on silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-10-01

Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 {\\ m cm}2 and thickness: 25 \\\\mu{\\ m m}) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections. © 1963-2012 IEEE.

Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

Science.gov (United States)

2016-08-01

APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...high sound velocity — makes guiding acoustic waves difficult, motivating the use of soft chalcogenide glasses and partial or complete releases (removal

Ultra-low loss nano-taper coupler for Silicon-on-Insulator ridge waveguide

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Ou, Haiyan

2010-01-01

A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler.......A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler....

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Science.gov (United States)

Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

2017-08-01

Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Characterization of silicon-on-insulator wafers

Science.gov (United States)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

International Nuclear Information System (INIS)

Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

2013-01-01

Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

Widely tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Xue, Weiqi

2010-01-01

We propose and demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator microring resonators. The phase-shifting range and the RF-power variation are analyzed. A maximum phase-shifting range of 0~600° is achieved by utilizing a dual-microring resonator...

Ultra-High-Efficiency Apodized Grating Coupler Using a Fully Etched Photonic Crystal

DEFF Research Database (Denmark)

Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

2013-01-01

We demonstrate an apodized fiber-to-chip grating coupler using fully etched photonic crystal holes on the silicon-on-insulator platform. An ultra-high coupling efficiency of 1.65 dB (68%) with 3 dB bandwidth of 60 nm is experimentally demonstrated.......We demonstrate an apodized fiber-to-chip grating coupler using fully etched photonic crystal holes on the silicon-on-insulator platform. An ultra-high coupling efficiency of 1.65 dB (68%) with 3 dB bandwidth of 60 nm is experimentally demonstrated....

Ultra-low coupling loss fully-etched apodized grating coupler with bonded metal mirror

DEFF Research Database (Denmark)

Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

2014-01-01

A fully etched apodized grating coupler with bonded metal mirror is designed and demonstrated on the silicon-on-insulator platform, showing an ultra-low coupling loss of only 1.25 dB with 3 dB bandwidth of 69 nm.......A fully etched apodized grating coupler with bonded metal mirror is designed and demonstrated on the silicon-on-insulator platform, showing an ultra-low coupling loss of only 1.25 dB with 3 dB bandwidth of 69 nm....

Code development for analysis of MHD pressure drop reduction in a liquid metal blanket using insulation technique based on a fully developed flow model

International Nuclear Information System (INIS)

Smolentsev, Sergey; Morley, Neil; Abdou, Mohamed

2005-01-01

The paper presents details of a new numerical code for analysis of a fully developed MHD flow in a channel of a liquid metal blanket using various insulation techniques. The code has specially been designed for channels with a 'sandwich' structure of several materials with different physical properties. The code includes a finite-volume formulation, automatically generated Hartmann number sensitive meshes, and effective convergence acceleration technique. Tests performed at Ha ∼ 10 4 have showed very good accuracy. As an illustration, two blanket flows have been considered: Pb-17Li flow in a channel with a silicon carbide flow channel insert, and Li flow in a channel with insulating coating

Integrated programmable photonic filter on the silicon -on- insulator platform

DEFF Research Database (Denmark)

Liao, Shasha; Ding, Yunhong; Peucheret, Christophe

2014-01-01

We propose and demonstrate a silicon - on - insulator (SOI) on - chip programmable filter based on a four - tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heater s. We further demonstrate...... the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability...

Peculiarities of electronic structure of silicon-on-insulator structures and their interaction with synchrotron radiation

Directory of Open Access Journals (Sweden)

Vladimir A. Terekhov

2015-09-01

Full Text Available SOI (silicon-on-insulator structures with strained and unstrained silicon layers were studied by ultrasoft X-ray emission spectroscopy and X-ray absorption near edge structure spectroscopy with the use of synchrotron radiation techniques. Analysis of X-ray data has shown a noticeable transformation of the electron energy spectrum and local partial density of states distribution in valence and conduction bands in the strained silicon layer of the SOI structure. USXES Si L2,3 spectra analysis revealed a decrease of the distance between the L2v′ и L1v points in the valence band of the strained silicon layer as well as a shift of the first two maxima of the XANES first derivation spectra to the higher energies with respect to conduction band bottom Ec. At the same time the X-ray standing waves of synchrotron radiation (λ~12–20 nm are formed in the silicon-on-insulator structure with and without strains of the silicon layer. Moreover changing the synchrotron radiation grazing angle θ by 2° leads to a change of the electromagnetic field phase to the opposite.

Optical microcavities based on surface modes in two-dimensional photonic crystals and silicon-on-insulator photonic crystals

DEFF Research Database (Denmark)

Xiao, Sanshui; Qiu, M.

2007-01-01

Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor is gr...... is gradually enhanced and the resonant frequency converges to that of the corresponding surface mode in the photonic crystals. These structures have potential applications such as sensing.......Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor...

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

International Nuclear Information System (INIS)

Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

2010-01-01

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

Theoretical model for the detection of charged proteins with a silicon-on-insulator sensor

International Nuclear Information System (INIS)

Birner, S; Uhl, C; Bayer, M; Vogl, P

2008-01-01

For a bio-sensor device based on a silicon-on-insulator structure, we calculate the sensitivity to specific charge distributions in the electrolyte solution that arise from protein binding to the semiconductor surface. This surface is bio-functionalized with a lipid layer so that proteins can specifically bind to the headgroups of the lipids on the surface. We consider charged proteins such as the green fluorescent protein (GFP) and artificial proteins that consist of a variable number of aspartic acids. Specifically, we calculate self-consistently the spatial charge and electrostatic potential distributions for different ion concentrations in the electrolyte. We fully take into account the quantum mechanical charge density in the semiconductor. We determine the potential change at the binding sites as a function of protein charge and ionic strength. Comparison with experiment is generally very good. Furthermore, we demonstrate the superiority of the full Poisson-Boltzmann equation by comparing its results to the simplified Debye-Hueckel approximation

Compact wavelength-insensitive fabrication-tolerant silicon-on-insulator beam splitter.

Science.gov (United States)

Rasigade, Gilles; Le Roux, Xavier; Marris-Morini, Delphine; Cassan, Eric; Vivien, Laurent

2010-11-01

A star coupler-based beam splitter for rib waveguides is reported. A design method is presented and applied in the case of silicon-on-insulator rib waveguides. Experimental results are in good agreement with simulations. Excess loss lower than 1 dB is experimentally obtained for star coupler lengths from 0.5 to 1 μm. Output balance is better than 1 dB, which is the measurement accuracy, and broadband transmission is obtained over 90 nm.

Porous silicon formation by hole injection from a back side p+/n junction for electrical insulation applications

International Nuclear Information System (INIS)

Fèvre, A; Menard, S; Defforge, T; Gautier, G

2016-01-01

In this paper, we propose to study the formation of porous silicon (PS) in low doped (1 × 10 14 cm −3 ) n-type silicon through hole injection from a back side p + /n junction in the dark. This technique is investigated within the framework of electrical insulation. Three different types of junctions are investigated. The first one is an epitaxial n-type layer grown on p + doped silicon wafer. The two other junctions are carried out by boron diffusion leading to p + regions with junction depths of 20 and 115 μm. The resulting PS morphology is a double layer with a nucleation layer (NL) and macropores fully filled with mesoporous material. This result is unusual for low doped n-type silicon. Morphology variations are described depending on the junction formation process, the electrolyte composition, the anodization current density and duration. In order to validate the more interesting industrial potentialities of the p + /n injection technique, a comparison is achieved with back side illumination in terms of resulting morphology and experiments confirm comparable results. Electrical characterizations of the double layer, including NL and fully filled macropores, are then performed. To our knowledge, this is the first electrical investigation in low doped n type silicon with this morphology. Compared to the bulk silicon, the measured electrical resistivities are 6–7 orders of magnitude higher at 373 K. (paper)

Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

International Nuclear Information System (INIS)

Margail, J.

1987-03-01

Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

Science.gov (United States)

Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

2017-04-03

We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

Realization of a Hole-Doped Mott Insulator on a Triangular Silicon Lattice

Science.gov (United States)

Ming, Fangfei; Johnston, Steve; Mulugeta, Daniel; Smith, Tyler S.; Vilmercati, Paolo; Lee, Geunseop; Maier, Thomas A.; Snijders, Paul C.; Weitering, Hanno H.

2017-12-01

The physics of doped Mott insulators is at the heart of some of the most exotic physical phenomena in materials research including insulator-metal transitions, colossal magnetoresistance, and high-temperature superconductivity in layered perovskite compounds. Advances in this field would greatly benefit from the availability of new material systems with a similar richness of physical phenomena but with fewer chemical and structural complications in comparison to oxides. Using scanning tunneling microscopy and spectroscopy, we show that such a system can be realized on a silicon platform. The adsorption of one-third monolayer of Sn atoms on a Si(111) surface produces a triangular surface lattice with half filled dangling bond orbitals. Modulation hole doping of these dangling bonds unveils clear hallmarks of Mott physics, such as spectral weight transfer and the formation of quasiparticle states at the Fermi level, well-defined Fermi contour segments, and a sharp singularity in the density of states. These observations are remarkably similar to those made in complex oxide materials, including high-temperature superconductors, but highly extraordinary within the realm of conventional s p -bonded semiconductor materials. It suggests that exotic quantum matter phases can be realized and engineered on silicon-based materials platforms.

High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

International Nuclear Information System (INIS)

Caër, Charles; Le Roux, Xavier; Cassan, Eric

2013-01-01

We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

Crosstalk analysis of silicon-on-insulator nanowire-arrayed waveguide grating

International Nuclear Information System (INIS)

Li Kai-Li; An Jun-Ming; Zhang Jia-Shun; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin Xiao-Jie; Hu Xiong-Wei

2016-01-01

The factors influencing the crosstalk of silicon-on-insulator (SOI) nanowire arrayed waveguide grating (AWG) are analyzed using the transfer function method. The analysis shows that wider and thicker arrayed waveguides, outsider fracture of arrayed waveguide, and larger channel space, could mitigate the deterioration of crosstalk. The SOI nanowire AWGs with different arrayed waveguide widths are fabricated by using deep ultraviolet lithography (DUV) and inductively coupled plasma etching (ICP) technology. The measurement results show that the crosstalk performance is improved by about 7 dB through adopting 800 nm arrayed waveguide width. (paper)

Silicon nanowire hot carrier electroluminescence

Energy Technology Data Exchange (ETDEWEB)

Plessis, M. du, E-mail: monuko@up.ac.za; Joubert, T.-H.

2016-08-31

Avalanche electroluminescence from silicon pn junctions has been known for many years. However, the internal quantum efficiencies of these devices are quite low due to the indirect band gap nature of the semiconductor material. In this study we have used reach-through biasing and SOI (silicon-on-insulator) thin film structures to improve the internal power efficiency and the external light extraction efficiency. Both continuous silicon thin film pn junctions and parallel nanowire pn junctions were manufactured using a custom SOI technology. The pn junctions are operated in the reach-through mode of operation, thus increasing the average electric field within the fully depleted region. Experimental results of the emission spectrum indicate that the most dominant photon generating mechanism is due to intraband hot carrier relaxation processes. It was found that the SOI nanowire light source external power efficiency is at least an order of magnitude better than the comparable bulk CMOS (Complementary Metal Oxide Semiconductor) light source. - Highlights: • We investigate effect of electric field on silicon avalanche electroluminescence. • With reach-through pn junctions the current and carrier densities are kept constant. • Higher electric fields increase short wavelength radiation. • Higher electric fields decrease long wavelength radiation. • The effect of the electric field indicates intraband transitions as main mechanism.

Depletion voltage studies on n-in-n MCz silicon diodes after irradiation with 70 MeV protons

CERN Document Server

Holmkvist, William

2014-01-01

Silicon detectors is the main component in the pixel detectors in the ATLAS experiment at CERN in order to detect the particles and recreate their tracks after a proton-proton collision. One criteria on these detectors is to be able to operate in the high radiation field close to the particle collision. The usual behavior of the silicon detectors is that they get type inverted and an increase in the depletion voltage can be seen after exposed to significant amounts of radiation. In contrast n-type Magnetic Czochralski (MCz) silicon doesn’t follow FZ silicons pattern of getting type inverted when it comes to high energy particle irradiation, in the range of GeV. However it was observed that MCz silicon diodes that had been irradiated with 23 MeV protons followed the FZ silicon behavior and did type invert. The aim of the project is to find out how the depletion voltage of MCz silicon changes after being irradiated by 70 MeV at fluencies of 1E13, 1E14 and 5E14 neq/cm2, to give a further insight of at what en...

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

Guided acoustic and optical waves in silicon-on-insulator for Brillouin scattering and optomechanics

Directory of Open Access Journals (Sweden)

Christopher J. Sarabalis

2016-10-01

Full Text Available We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.

A pile-up phenomenon during arsenic diffusion in silicon-on-insulator structures formed by oxygen implantation

Science.gov (United States)

Normand, P.; Tsoukalas, D.; Guillemot, N.; Chenevier, P.

1989-10-01

Arsenic diffusion in silicon-on-insulator formed by deep oxygen implantation is studied by secondary ion mass spectroscopy and speading resistance measurements. An enhanced diffusivity as well as a pile-up phenomenon are observed in the thin silicon layer. The McNabb and Foster equations [Trans. TMS-AIME 22, 618 (1963)] for diffusion with trapping are solved in order to simulate this last effect.

SEMICONDUCTOR DEVICES: Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

Science.gov (United States)

Jin, Li; Hongxia, Liu; Bin, Li; Lei, Cao; Bo, Yuan

2010-08-01

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a “rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

The paradox of characteristics of silicon detectors operated at temperature close to liquid helium

Science.gov (United States)

Eremin, V.; Shepelev, A.; Verbitskaya, E.; Zamantzas, C.; Galkin, A.

2018-05-01

The aim of this study is to give characterization of silicon p+/n/n+ detectors for the monitoring systems of the Large Hadron Collider machine at CERN with the focus on justifying the choice of silicon resistivity for the detector operation at the temperature of 1.9-10 K. The detectors from n-type silicon with the resistivity of 10, 4.5, and 0.5 kΩ cm were investigated at the temperature from 293 up to 7 K by the Transient Current Technique with a 660 nm pulse laser and alpha-particles. The shapes of the detector current pulse response allowed revealing a paradox in the properties of shallow donors of phosphorus, i.e., native dopants in the n-type Si. There was no carrier freeze-out on the phosphorus energy levels in the space charge region (SCR), and they remained positively charged irrespective of temperature, thus limiting the depleted region depth. As for the base region of a partially depleted detector, the levels became neutral at T < 28 K, which transformed silicon to an insulator. The reduction of the activation energy for carrier emission in the detector SCR estimated in the scope of the Poole-Frenkel effect failed to account for the impact of the electric field on the properties of phosphorus levels. The absence of carrier freeze-out in the SCR justifies the choice of high resistivity silicon as the only proper material for detector operation in a fully depleted mode at extremely low temperature.

Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI

Directory of Open Access Journals (Sweden)

John E. Cunningham

2012-04-01

Full Text Available We have investigated the selective epitaxial growth of GeSi bulk material on silicon-on-insulator substrates by reduced pressure chemical vapor deposition. We employed AFM, SIMS, and Hall measurements, to characterize the GeSi heteroepitaxy quality. Optimal growth conditions have been identified to achieve low defect density, low RMS roughness with high selectivity and precise control of silicon content. Fabricated vertical p-i-n diodes exhibit very low dark current density of 5 mA/cm² at −1 V bias. Under a 7.5 V/µm E-field, GeSi alloys with 0.6% Si content demonstrate very strong electro-absorption with an estimated effective ∆α/α around 3.5 at 1,590 nm. We compared measured ∆α/α performance to that of bulk Ge. Optical modulation up to 40 GHz is observed in waveguide devices while small signal analysis indicates bandwidth is limited by device parasitics.

Helium ion beam induced electron emission from insulating silicon nitride films under charging conditions

Science.gov (United States)

Petrov, Yu. V.; Anikeva, A. E.; Vyvenko, O. F.

2018-06-01

Secondary electron emission from thin silicon nitride films of different thicknesses on silicon excited by helium ions with energies from 15 to 35 keV was investigated in the helium ion microscope. Secondary electron yield measured with Everhart-Thornley detector decreased with the irradiation time because of the charging of insulating films tending to zero or reaching a non-zero value for relatively thick or thin films, respectively. The finiteness of secondary electron yield value, which was found to be proportional to electronic energy losses of the helium ion in silicon substrate, can be explained by the electron emission excited from the substrate by the helium ions. The method of measurement of secondary electron energy distribution from insulators was suggested, and secondary electron energy distribution from silicon nitride was obtained.

Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Directory of Open Access Journals (Sweden)

Avi Karsenty

2015-01-01

Full Text Available Nanoscale Gate-Recessed Channel (GRC Fully Depleted- (FD- SOI MOSFET device with a silicon channel thickness (tSi as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Influence of germanium on thermal dewetting and agglomeration of the silicon template layer in thin silicon-on-insulator

International Nuclear Information System (INIS)

Zhang, P P; Yang, B; Rugheimer, P P; Roberts, M M; Savage, D E; Lagally, M G; Liu Feng

2009-01-01

We investigate the influence of heteroepitaxially grown Ge on the thermal dewetting and agglomeration of the Si(0 0 1) template layer in ultrathin silicon-on-insulator (SOI). We show that increasing Ge coverage gradually destroys the long-range ordering of 3D nanocrystals along the (1 3 0) directions and the 3D nanocrystal shape anisotropy that are observed in the dewetting and agglomeration of pure SOI(0 0 1). The results are qualitatively explained by Ge-induced bond weakening and decreased surface energy anisotropy. Ge lowers the dewetting and agglomeration temperature to as low as 700 0 C.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

Science.gov (United States)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

Analytical modeling of subthreshold current and subthreshold swing of Gaussian-doped strained-Si-on-insulator MOSFETs

International Nuclear Information System (INIS)

Rawat, Gopal; Kumar, Sanjay; Goel, Ekta; Kumar, Mirgender; Jit, S.; Dubey, Sarvesh

2014-01-01

This paper presents the analytical modeling of subthreshold current and subthreshold swing of short-channel fully-depleted (FD) strained-Si-on-insulator (SSOI) MOSFETs having vertical Gaussian-like doping profile in the channel. The subthreshold current and subthreshold swing have been derived using the parabolic approximation method. In addition to the effect of strain on silicon layer, various other device parameters such as channel length (L), gate-oxide thickness (t ox ), strained-Si channel thickness (t s-Si ), peak doping concentration (N P ), project range (R p ) and straggle (σ p ) of the Gaussian profile have been considered while predicting the device characteristics. The present work may help to overcome the degradation in subthreshold characteristics with strain engineering. These subthreshold current and swing models provide valuable information for strained-Si MOSFET design. Accuracy of the proposed models is verified using the commercially available ATLAS™, a two-dimensional (2D) device simulator from SILVACO. (semiconductor devices)

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

Science.gov (United States)

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

A Difference in Using Atomic Layer Deposition or Physical Vapour Deposition TiN as Electrode Material in Metal-Insulator-Metal and Metal-Insulator-Silicon Capacitors

NARCIS (Netherlands)

Groenland, A.W.; Wolters, Robertus A.M.; Kovalgin, Alexeij Y.; Schmitz, Jurriaan

2011-01-01

In this work, metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) capacitors are studied using titanium nitride (TiN) as the electrode material. The effect of structural defects on the electrical properties on MIS and MIM capacitors is studied for various electrode configurations. In the

Waveguide silicon nitride grating coupler

Science.gov (United States)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Special Issue: Planar Fully-Depleted SOI technology

Science.gov (United States)

Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

2016-03-01

We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

Science.gov (United States)

Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

2017-10-01

We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

Modelling of a DBR laser based on Raman effect in a silicon-on-insulator rib waveguide

International Nuclear Information System (INIS)

De Leonardis, Francesco; Dimastrodonato, Valeria; Passaro, Vittorio M N

2008-01-01

In this paper, third-order nonlinearities in silicon-on-insulator rib waveguides are investigated to obtain complete modelling, describing the behaviour of a stimulated Raman scattering based laser. The simulations of a distributed Bragg reflector laser operation in a time domain allow for the first time to study in detail the dependence of threshold and output powers on different device parameters. Both continuous wave and pulsed laser operations are theoretically demonstrated, as well as their dependence on device parameters

Operation of heavily irradiated silicon detectors in non-depletion mode

International Nuclear Information System (INIS)

Verbitskaya, E.; Eremin, V.; Ilyashenko, I.; Li, Z.; Haerkoenen, J.; Tuovinen, E.; Luukka, P.

2006-01-01

The non-depletion detector operation mode has generally been disregarded as an option in high-energy physics experiments. In this paper, the non-depletion operation is examined by detailed analysis of the electric field distribution and the current pulse response of heavily irradiated silicon (Si) detectors. The previously reported model of double junction in heavily irradiated Si detector is further developed and a simulation of the current pulse response has been performed. It is shown that detectors can operate in a non-depletion mode due to the fact that the value of the electric field in a non-depleted region is high enough for efficient carrier drift. This electric field originates from the current flow through the detector and a consequent drop of the potential across high-resistivity bulk of a non-depleted region. It is anticipated that the electric field in a non-depleted region, which is still electrically neutral, increases with fluence that improves the non-depleted detector operation. Consideration of the electric field in a non-depleted region allows the explanation of the recorded double-peak current pulse shape of heavily irradiated Si detectors and definition of the requirements for the detector operational conditions. Detailed reconstruction of the electric field distribution gives new information on radiation effects in Si detectors

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

Science.gov (United States)

Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

2005-01-01

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

International Nuclear Information System (INIS)

Yu-Feng, Guo; Zhi-Gong, Wang; Gene, Sheu; Jian-Bing, Cheng

2010-01-01

We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

International Nuclear Information System (INIS)

Chen Peng; An Zhenghua; Zhu Ming; Fu, Ricky K.Y.; Chu, Paul K.; Montgomery, Neil; Biswas, Sukanta

2004-01-01

The indium implant damage and diffusion behavior in thin silicon-on-insulator (SOI) with a 200 nm top silicon layer were studied for different implantation energies and doses. Rutherford backscattering spectrometry in the channeling mode (RBS/C) was used to characterize the implant damage before and after annealing. Secondary ion mass spectrometry (SIMS) was used to study the indium transient enhanced diffusion (TED) behavior in the top Si layer of the SOI structure. An anomalous redistribution of indium after relatively high energy (200 keV) and dose (1 x 10 14 cm -2 ) implantation was observed in both bulk Si and SOI substrates. However, there exist differences in these two substrates that are attributable to the more predominant out-diffusion of indium as well as the influence of the buried oxide layer in the SOI structure

Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

Science.gov (United States)

Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

2014-11-25

Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

Observation of an optical event horizon in a silicon-on-insulator photonic wire waveguide.

Science.gov (United States)

Ciret, Charles; Leo, François; Kuyken, Bart; Roelkens, Gunther; Gorza, Simon-Pierre

2016-01-11

We report on the first experimental observation of an optical analogue of an event horizon in integrated nanophotonic waveguides, through the reflection of a continuous wave on an intense pulse. The experiment is performed in a dispersion-engineered silicon-on-insulator waveguide. In this medium, solitons do not suffer from Raman induced self-frequency shift as in silica fibers, a feature that is interesting for potential applications of optical event horizons. As shown by simulations, this also allows the observation of multiple reflections at the same time on fundamental solitons ejected by soliton fission.

Ultrahigh-efficiency apodized grating coupler using fully etched photonic crystals

DEFF Research Database (Denmark)

Ding, Yunhong; Ou, Haiyan; Peucheret, Christophe

2013-01-01

We present an efficient method to design apodized grating couplers with Gaussian output profiles for efficient coupling between standard single mode fibers and silicon chips. An apodized grating coupler using fully etched photonic crystal holes on the silicon-on-insulator platform is designed......, and fabricated in a single step of lithography and etching. An ultralow coupling loss of x2212;1.74x2009;x2009;dB (67% coupling efficiency) with a 3xA0;dB bandwidth of 60xA0;nm is experimentally measured....

Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

Science.gov (United States)

Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

2008-04-01

We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

Energy Technology Data Exchange (ETDEWEB)

Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

2017-06-15

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

International Nuclear Information System (INIS)

Lam, H.W.; Pinizzotto, R.F.; Yuan, H.T.; Bellavance, D.W.

1981-01-01

By implanting a dose of 6 x 10 17 cm -2 of 32 O 2 + at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200 0 C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm 2 /Vs has been measured in n-channel MOSFETs fabricated in a 0.5 μm-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at Vsub(DS)=2 V has been measured. (author)

The depletion properties of silicon microstrip detectors with variable strip pitch

International Nuclear Information System (INIS)

Krizmanic, J.F.

1994-01-01

We have investigated the depletion properties of trapezoidal shaped silicon microstrip detectors which have variable strip pitch. Four types of detectors were examined: three detectors have constant strip width and a fourth has a varying strip width. The detectors are single sided with readout performed via p + strips. The depletion properties of the devices were measured using two different methods. The first used capacitance versus voltage measurements, while the second used a 1060 nm wavelength laser coupled to a single mode fiber with a mode field diameter less than 10 μm. The small laser spot size allowed for the depletion depth to be measured in a localized area of the detector. The laser induced charge on an electrode was measured as a function of reverse bias voltage using a sensitive charge preamplifier. The depletion voltages of the detectors demonstrate a strong dependence upon the ratio of strip width to strip pitch. Moreover, these measurements show that a large value of this ratio yields a lower depletion voltage and vice versa. (orig.)

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

Science.gov (United States)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Interstellar Silicon Depletion and the Ultraviolet Extinction

Science.gov (United States)

Mishra, Ajay; Li, Aigen

2018-01-01

Spinning small silicate grains were recently invoked to account for the Galactic foreground anomalous microwave emission. These grains, if present, will absorb starlight in the far ultraviolet (UV). There is also renewed interest in attributing the enigmatic 2175 Å interstellar extinction bump to small silicates. To probe the role of silicon in the UV extinction, we explore the relations between the amount of silicon required to be locked up in silicates [Si/H]dust and the 2175 Å bump or the far-UV extinction rise, based on an analysis of the extinction curves along 46 Galactic sightlines for which the gas-phase silicon abundance [Si/H]gas is known. We derive [Si/H]dust either from [Si/H]ISM - [Si/H]gas or from the Kramers- Kronig relation which relates the wavelength-integrated extinction to the total dust volume, where [Si/H]ISM is the interstellar silicon reference abundance and taken to be that of proto-Sun or B stars. We also derive [Si/H]dust from fi�tting the observed extinction curves with a mixture of amorphous silicates and graphitic grains. We fi�nd that in all three cases [Si/H]dust shows no correlation with the 2175 Å bump, while the carbon depletion [C/H]dust tends to correlate with the 2175 Å bump. This supports carbon grains instead of silicates as the possible carrier of the 2175 Å bump. We also �find that neither [Si/H]dust nor [C/H]dust alone correlates with the far-UV extinction, suggesting that the far-UV extinction is a combined effect of small carbon grains and silicates.

Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

International Nuclear Information System (INIS)

Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

1989-01-01

Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

New Insights into Fully-Depleted SOI Transistor Response During Total Dose Irradiation

International Nuclear Information System (INIS)

Burns, J.A.; Dodd, P.E.; Keast, C.L.; Schwank, J.R.; Shaneyfelt, M.R.; Wyatt, P.W.

1999-01-01

Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. No evidence was found for total-dose induced snap back. These results have implications for hardness assurance testing

A monolithically integrated detector-preamplifier on high-resistivity silicon

International Nuclear Information System (INIS)

Holland, S.; Spieler, H.

1990-02-01

A monolithically integrated detector-preamplifier on high-resistivity silicon has been designed, fabricated and characterized. The detector is a fully depleted p-i-n diode and the preamplifier is implemented in a depletion-mode PMOS process which is compatible with detector processing. The amplifier is internally compensated and the measured gain-bandwidth product is 30 MHz with an input-referred noise of 15 nV/√Hz in the white noise regime. Measurements with an Am 241 radiation source yield an equivalent input noise charge of 800 electrons at 200 ns shaping time for a 1.4 mm 2 detector with on-chip amplifier in an experimental setup with substantial external pickup

Characterizing the effects of free carriers in fully etched, dielectric-clad silicon waveguides

Science.gov (United States)

Sharma, Rajat; Puckett, Matthew W.; Lin, Hung-Hsi; Vallini, Felipe; Fainman, Yeshaiahu

2015-06-01

We theoretically characterize the free-carrier plasma dispersion effect in fully etched silicon waveguides, with various dielectric material claddings, due to fixed interface charges and trap states at the silicon-dielectric interfaces. The values used for these charges are obtained from the measured capacitance-voltage characteristics of SiO2, SiNx, and Al2O3 thin films deposited on silicon substrates. The effect of the charges on the properties of silicon waveguides is then calculated using the semiconductor physics tool Silvaco in combination with the finite-difference time-domain method solver Lumerical. Our results show that, in addition to being a critical factor in the analysis of such active devices as capacitively driven silicon modulators, this effect should also be taken into account when considering the propagation losses of passive silicon waveguides.

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

Science.gov (United States)

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

2007-07-25

A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

Effects of aging on the structural, mechanical, and thermal properties of the silicone rubber current transformer insulation bushing for a 500 kV substation.

Science.gov (United States)

Wang, Zhigao; Zhang, Xinghai; Wang, Fangqiang; Lan, Xinsheng; Zhou, Yiqian

2016-01-01

In order to analyze the cracking and aging reason of the silicone rubber current transformer (CT) insulation bushing used for 8 years from a 500 kV alternating current substation, characteristics including Fourier transform infrared (FTIR) spectroscopy, mechanical properties analysis, hardness, and thermo gravimetric analysis have been carried out. The FTIR results indicated that the external surface of the silicone rubber CT insulation bushing suffered from more serious aging than the internal part, fracture of side chain Si-C bond was much more than the backbone. Mechanical properties and thermal stability results illustrated that the main aging reasons were the breakage of side chain Si-C bond and the excessive cross-linking reaction of the backbone. This study can provide valuable basis for evaluating degradation mechanism and aging state of the silicone rubber insulation bushing in electric power field.

Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections.

Science.gov (United States)

Chen, George F R; Ong, Jun Rong; Ang, Thomas Y L; Lim, Soon Thor; Png, Ching Eng; Tan, Dawn T H

2017-08-03

Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

Tunable complex-valued multi-tap microwave photonic filter based on single silicon-on-insulator microring resonator.

Science.gov (United States)

Lloret, Juan; Sancho, Juan; Pu, Minhao; Gasulla, Ivana; Yvind, Kresten; Sales, Salvador; Capmany, José

2011-06-20

A complex-valued multi-tap tunable microwave photonic filter based on single silicon-on-insulator microring resonator is presented. The degree of tunability of the approach involving two, three and four taps is theoretical and experimentally characterized, respectively. The constraints of exploiting the optical phase transfer function of a microring resonator aiming at implementing complex-valued multi-tap filtering schemes are also reported. The trade-off between the degree of tunability without changing the free spectral range and the number of taps is studied in-depth. Different window based scenarios are evaluated for improving the filter performance in terms of the side-lobe level.

Space and military radiation effects in silicon-on-insulator devices

International Nuclear Information System (INIS)

Schwank, J.R.

1996-09-01

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

Improved Spatial Resolution in Thick, Fully-Depleted CCDs withEnhanced Red Sensitivity

Energy Technology Data Exchange (ETDEWEB)

Fairfield, Jessamyn A.

2005-11-10

The point spread function (PSF) is an important measure ofspatial resolution in CCDs for point-like objects, since it can affectuse in imaging and spectroscopic applications. We present new data andtheoretical developments in the study of lateral charge diffusion inthick, fully-depleted charge-coupled devices (CCDs) developed at LawrenceBerkeley National Laboratory (LBNL). Because they are fully depleted, theLBNL devices have no field-free region, and diffusion can be controlledthrough the application of an external bias voltage. We give results fora 3512x3512 format, 10.5 ?m pixel back-illuminated p-channel CCDdeveloped for the SuperNova/ Acceleration Probe (SNAP), a proposedsatellite-based experiment designed to study dark energy. The PSF wasmeasured at substrate bias voltages between 3 V and 115 V. At a biasvoltage of 115V, we measure an rms diffusion of 3.7 +- 0.2 ?m. Lateralcharge diffusion in LBNL CCDs is thus expected to meet the SNAPrequirements.

Improved Spatial Resolution in Thick, Fully-Depleted CCDs with Enhanced Red Sensitivity

International Nuclear Information System (INIS)

Fairfield, Jessamyn A.

2005-01-01

The point spread function (PSF) is an important measure of spatial resolution in CCDs for point-like objects, since it can affect use in imaging and spectroscopic applications. We present new data and theoretical developments in the study of lateral charge diffusion in thick, fully-depleted charge-coupled devices (CCDs) developed at Lawrence Berkeley National Laboratory (LBNL). Because they are fully depleted, the LBNL devices have no field-free region, and diffusion can be controlled through the application of an external bias voltage. We give results for a 3512x3512 format, 10.5 ?m pixel back-illuminated p-channel CCD developed for the SuperNova/Acceleration Probe (SNAP), a proposed satellite-based experiment designed to study dark energy. The PSF was measured at substrate bias voltages between 3 V and 115 V. At a bias voltage of 115V, we measure an rms diffusion of 3.7 ± 0.2 (micro)m. Lateral charge diffusion in LBNL CCDs is thus expected to meet the SNAP requirements

Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

Science.gov (United States)

Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

2007-01-01

We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

Electrical characterization of high-pressure reactive sputtered ScOx films on silicon

International Nuclear Information System (INIS)

Castan, H.; Duenas, S.; Gomez, A.; Garcia, H.; Bailon, L.; Feijoo, P.C.; Toledano-Luque, M.; Prado, A. del; San Andres, E.; Lucia, M.L.

2011-01-01

Al/ScO x /SiN x /n-Si and Al/ScO x /SiO x /n-Si metal-insulator-semiconductor capacitors have been electrically characterized. Scandium oxide was grown by high-pressure sputtering on different substrates to study the dielectric/insulator interface quality. The substrates were silicon nitride and native silicon oxide. The use of a silicon nitride interfacial layer between the silicon substrate and the scandium oxide layer improves interface quality, as interfacial state density and defect density inside the insulator are decreased.

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

2012-01-01

The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

To minimized power outage by the application of 'RTV' (room temperature vulcanizing) silicon on high voltage porcelain insulators in Pakistan

International Nuclear Information System (INIS)

Hafiz Tehzeeb ul Hassan

2003-01-01

In Pakistan power network comprises of 500KV, 220KV, 132KV, 66KV and 33KV transmission lines and 11KV power distribution systems. Number of insulators are used in connected units in the shape of strings with transmission line as per insulation requirements with proper design according to the various kinds of pollution stresses. The transmission lines are passing from or near polluted areas and very dusty plains of Punjab and Sindh provinces. Practices are being used in these transmission lines for removal of accumulated contamination of insulators by periodic cleaning twice a year or de-energized transmission lines. Even then discontinuation of supply takes place in the polluted areas in foggy weather. Special technique of using water repellent (Room Temperature Vulcanizing) silicone coating/paint has been introduced on high voltage disc Insulators to minimize the outage in power net work in Pakistan. Especially in high pollution areas near chemical factories and near brick kilns etc comparison study of coated and uncoated disc Insulators have been carried out by ESDD (Equal Salt Deposit Density) measurement in salt fog chamber. (author)

Ultrathin silicon oxynitride layer on GaN for dangling-bond-free GaN/insulator interface.

Science.gov (United States)

Nishio, Kengo; Yayama, Tomoe; Miyazaki, Takehide; Taoka, Noriyuki; Shimizu, Mitsuaki

2018-01-23

Despite the scientific and technological importance of removing interface dangling bonds, even an ideal model of a dangling-bond-free interface between GaN and an insulator has not been known. The formation of an atomically thin ordered buffer layer between crystalline GaN and amorphous SiO 2 would be a key to synthesize a dangling-bond-free GaN/SiO 2 interface. Here, we predict that a silicon oxynitride (Si 4 O 5 N 3 ) layer can epitaxially grow on a GaN(0001) surface without creating dangling bonds at the interface. Our ab initio calculations show that the GaN/Si 4 O 5 N 3 structure is more stable than silicon-oxide-terminated GaN(0001) surfaces. The electronic properties of the GaN/Si 4 O 5 N 3 structure can be tuned by modifying the chemical components near the interface. We also propose a possible approach to experimentally synthesize the GaN/Si 4 O 5 N 3 structure.

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

Science.gov (United States)

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

Light extraction from GaN-based LED structures on silicon-on-insulator substrates

Energy Technology Data Exchange (ETDEWEB)

Tripathy, S.; Teo, S.L.; Lin, V.K.X.; Chen, M.F. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), 117602 (Singapore); Dadgar, A.; Krost, A. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany); AZZURRO Semiconductors AG, Universitaetsplatz 1, 39016 Magdeburg (Germany); Christen, J. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany)

2010-01-15

Nano-patterning of GaN-based devices is a promising technology in the development of high output power devices. Recent researches have been focused on the realization of two-dimensional (2D) photonic crystal (PhC) structure to improve light extraction efficiency and to control the direction of emission. In this study, we have demonstrated improved light extraction from green light emitting diode (LED) structures on thin silicon-on-insulator (SOI) substrates using surface nanopatterning. Scanning electron microscopy (SEM) is used to probe the size, shape, and etch depth of nano-patterns on the LED surfaces. Different types of nanopatterns were created by e-beam lithography and inductively coupled plasma etching. The LED structures after post processing are studied by photoluminescence (PL) measurements. The GaN nanophotonic structures formed by ICP etching led to more than five-fold increase in the intensity of the green emission. The improved light extraction is due to the combination of SOI substrate reflectivity and photonic structures on top GaN LED surfaces. (copyright 2010 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Accelerated life test of an ONO stacked insulator film for a silicon micro-strip detector

International Nuclear Information System (INIS)

Okuno, Shoji; Ikeda, Hirokazu; Saitoh, Yutaka

1996-01-01

We have used to acquire the signal through an integrated capacitor for a silicon micro-strip detector. When we have been using a double-sided silicon micro-strip detector, we have required a long-term stability and a high feasibility for the integrated capacitor. An oxide-nitride-oxide (ONO) insulator film was theoretically expected to have a superior nature in terms of long term reliability. In order to test long term reliability for integrated capacitor of a silicon micro-strip detector, we made a multi-channel measuring system for capacitors

Thermal radiative near field transport between vanadium dioxide and silicon oxide across the metal insulator transition

Energy Technology Data Exchange (ETDEWEB)

Menges, F.; Spieser, M.; Riel, H.; Gotsmann, B., E-mail: bgo@zurich.ibm.com [IBM Research-Zurich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Dittberner, M. [IBM Research-Zurich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Photonics Laboratory, ETH Zurich, 8093 Zurich (Switzerland); Novotny, L. [Photonics Laboratory, ETH Zurich, 8093 Zurich (Switzerland); Passarello, D.; Parkin, S. S. P. [IBM Almaden Research Center, 650 Harry Road, San Jose, California 95120 (United States)

2016-04-25

The thermal radiative near field transport between vanadium dioxide and silicon oxide at submicron distances is expected to exhibit a strong dependence on the state of vanadium dioxide which undergoes a metal-insulator transition near room temperature. We report the measurement of near field thermal transport between a heated silicon oxide micro-sphere and a vanadium dioxide thin film on a titanium oxide (rutile) substrate. The temperatures of the 15 nm vanadium dioxide thin film varied to be below and above the metal-insulator-transition, and the sphere temperatures were varied in a range between 100 and 200 °C. The measurements were performed using a vacuum-based scanning thermal microscope with a cantilevered resistive thermal sensor. We observe a thermal conductivity per unit area between the sphere and the film with a distance dependence following a power law trend and a conductance contrast larger than 2 for the two different phase states of the film.

Silicon-on-insulator based nanopore cavity arrays for lipid membrane investigation.

Science.gov (United States)

Buchholz, K; Tinazli, A; Kleefen, A; Dorfner, D; Pedone, D; Rant, U; Tampé, R; Abstreiter, G; Tornow, M

2008-11-05

We present the fabrication and characterization of nanopore microcavities for the investigation of transport processes in suspended lipid membranes. The cavities are situated below the surface of silicon-on-insulator (SOI) substrates. Single cavities and large area arrays were prepared using high resolution electron-beam lithography in combination with reactive ion etching (RIE) and wet chemical sacrificial underetching. The locally separated compartments have a circular shape and allow the enclosure of picoliter volume aqueous solutions. They are sealed at their top by a 250 nm thin Si membrane featuring pores with diameters from 2 µm down to 220 nm. The Si surface exhibits excellent smoothness and homogeneity as verified by AFM analysis. As biophysical test system we deposited lipid membranes by vesicle fusion, and demonstrated their fluid-like properties by fluorescence recovery after photobleaching. As clearly indicated by AFM measurements in aqueous buffer solution, intact lipid membranes successfully spanned the pores. The nanopore cavity arrays have potential applications in diagnostics and pharmaceutical research on transmembrane proteins.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

Science.gov (United States)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Fully depleted CMOS pixel sensor development and potential applications

Energy Technology Data Exchange (ETDEWEB)

Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

2015-07-01

CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

Extreme temperature stability of thermally insulating graphene-mesoporous-silicon nanocomposite

Science.gov (United States)

Kolhatkar, Gitanjali; Boucherif, Abderraouf; Rahim Boucherif, Abderrahim; Dupuy, Arthur; Fréchette, Luc G.; Arès, Richard; Ruediger, Andreas

2018-04-01

We demonstrate the thermal stability and thermal insulation of graphene-mesoporous-silicon nanocomposites (GPSNC). By comparing the morphology of GPSNC carbonized at 650 °C as-formed to that after annealing, we show that this nanocomposite remains stable at temperatures as high as 1050 °C due to the presence of a few monolayers of graphene coating on the pore walls. This does not only make this material compatible with most thermal processes but also suggests applications in harsh high temperature environments. The thermal conductivity of GPSNCs carbonized at temperatures in the 500 °C-800 °C range is determined through Raman spectroscopy measurements. They indicate that the thermal conductivity of the composite is lower than that of silicon, with a value of 13 ± 1 W mK-1 at room temperature, and not affected by the thin graphene layer, suggesting a role of the high concentration of carbon related-defects as indicated by the high intensity of the D-band compared to G-band of the Raman spectra. This morphological stability at high temperature combined with a high thermal insulation make GPSNC a promising candidate for a broad range of applications including microelectromechanical systems and thermal effect microsystems such as flow sensors or IR detectors. Finally, at 120 °C, the thermal conductivity remains equal to that at room temperature, attesting to the potential of using our nanocomposite in devices that operate at high temperatures such as microreactors for distributed chemical conversion, solid oxide fuel cells, thermoelectric devices or thermal micromotors.

Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

Science.gov (United States)

Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

2016-02-10

We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

The distribution of silicon on BP Boo

International Nuclear Information System (INIS)

Hatzes, A.P.

1990-01-01

A version of the Doppler imaging technique which incorporates the principles of maximum entropy reconstruction is used to derive the silicon distribution on the Ap star BP Boo (HR 5857). The method used made it possible to detect an error in the published photometric period and a new value of 1.29557 d was determined. The silicon distribution consists of two depleted spots of unequal area separated by about 180deg in longitude. These spots may coincide with the location of the magnetic poles of the star as in the case of γ 2 Ari. Near the larger of the depleted silicon spots is a spot of enhanced abundance. The unequal area of the depleted spots as well as the close proximity of the enhanced spot to one of the depleted regions suggests the presence of non-axisymmetric magnetic field lines. (author)

A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

Energy Technology Data Exchange (ETDEWEB)

DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

1999-11-01

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

Evanescently Coupled Rectangular Microresonators in Silicon-on-Insulator with High Q-Values: Experimental Characterization

Directory of Open Access Journals (Sweden)

Manuel Mendez-Astudillo

2017-04-01

Full Text Available We report on evanescently coupled rectangular microresonators with dimensions up to 20 × 10 μm2 in silicon-on-insulator in an add-drop filter configuration. The influence of the geometrical parameters of the device was experimentally characterized and a high Q value of 13,000 was demonstrated as well as the multimode optical resonance characteristics in the drop port. We also show a 95% energy transfer between ports when the device is operated in TM-polarization and determine the full symmetry of the device by using an eight-port configuration, allowing the drop waveguide to be placed on any of its sides, providing a way to filter and route optical signals. We used the FDTD method to analyze the device and e-beam lithography and dry etching techniques for fabrication.

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

International Nuclear Information System (INIS)

Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

2008-01-01

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

Energy Technology Data Exchange (ETDEWEB)

Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

2008-03-03

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

Organic filler from golden apple snails shells to improve the silicone rubber insulator properties

Science.gov (United States)

Tepsila, Sujirat; Suksri, Amnart

2018-02-01

This paper investigates the effect of an addition of filler compound using golden apple snail shell as an organic filler to the silicone rubber insulator. The filler obtained from golden apple snail shell is found mostly contained calcium carbonate. The organic calcium carbonate (CaCO3) with particle size of 45, 75, 100 and 300 micron were prepared. Sample of silicone rubber that were filled with fillers were tested under ASTM D638-02a type standard for mechanical test. Also, electrical test such as I-V characteristics (ASTM D257-07) and dry arc test according to ASTM D495-14 have been performed. The results revealed that using larger particle size of organic filler obtained from the golden apple snail shell resulted to higher value of dielectric constant as well as higher dielectric strength. Also, the filler helps slow down the tracking activity at an insulator surface due to its crystals of calcium carbonate. However, when using excessive amount of filler, the sample will have a drawbacks in mechanical properties. By using agriculture waste as a filler compound, one can reduced the usage of commercial CaCO3 as an inorganic materials and to lower the investment cost to a final silicone rubber product.

In situ nanoscale refinement by highly controllable etching of the (111) silicon crystal plane and its influence on the enhanced electrical property of a silicon nanowire

International Nuclear Information System (INIS)

Gong Yibin; Dai Pengfei; Gao Anran; Li Tie; Zhou Ping; Wang Yuelin

2011-01-01

Nanoscale refinement on a (100) oriented silicon-on-insulator (SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide (TMAH, 25 wt%) anisotropic silicon etchant, with temperature kept at 50 °C to achieve precise etching of the (111) crystal plane. Specifically for a silicon nanowire (SiNW) with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral (2.3 nm/min) and vertical (1.7 nm/min) dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor (FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the (111) plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields. (semiconductor materials)

Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

Science.gov (United States)

Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

2018-04-01

We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

Cryogenic microwave imaging of metal–insulator transition in doped silicon

KAUST Repository

Kundhikanjana, Worasom; Lai, Keji; Kelly, Michael A.; Shen, Zhi-Xun

2011-01-01

We report the instrumentation and experimental results of a cryogenic scanning microwave impedance microscope. The microwave probe and the scanning stage are located inside the variable temperature insert of a helium cryostat. Microwave signals in the distance modulation mode are used for monitoring the tip-sample distance and adjusting the phase of the two output channels. The ability to spatially resolve the metal-insulator transition in a doped silicon sample is demonstrated. The data agree with a semiquantitative finite element simulation. Effects of the thermal energy and electric fields on local charge carriers can be seen in the images taken at different temperatures and dc biases. © 2011 American Institute of Physics.

Evaluation of diagnostic technique for degradation of low-voltage electric cables with silicone rubber insulator

International Nuclear Information System (INIS)

Mikami, Masao

2005-01-01

As a part of countermeasures against ageing problems of nuclear power plants, it is requested to establish non-destructive diagnostic technique for their degradation of low voltage electric cables and assessment standard of their life. Having aimed at investigating the degradation of low-voltage electric cable with silicone rubber insulator, change of its surface hardness at elevated temperature were measured by indenter modules. Moreover, we also measured the elongation at break, which is regarded as general degradation index of electric cables, and the surface hardness with a micro hardness meter. Consequently, it is seen that the indenter modulus measurement is (1) capable to obtain general feature of the thermal degradation of silicone rubber insulator, (2) applicable to diagnose the degree of degradation of the electric cable by converting the result to elongation at break, (3) well correlated with the hardness measurement of the electric cable with the micro hardness meter. (author)

Depleted Monolithic Pixels (DMAPS) in a 150 nm technology: lab and beam results

International Nuclear Information System (INIS)

Obermann, T.; Hemperek, T.; Hügging, F.; Krüger, H.; Pohl, D.-L.; Wermes, N.; Schwenker, B.

2017-01-01

The fully depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a fully depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and high resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, were developed in a 150 nm process on a high resistive n-type wafer of 50 μm thickness. The prototypes have 352 square pixels of 40 μm pitch and small n-well charge collection node with very low capacitance (n + -implantation size: 5 μm by 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part).

Developments in Silicon Detectors and their impact on LHCb Physics Measurements

CERN Document Server

Gouldwell-Bates, A

2005-01-01

The LHCb experiment is a high energy physics detector at the Large Hadron Collider (LHC) which will probe the current understanding of the Standard Model through precise measurements of CP violation and rare decays. The LHCb detector heavily depends on the silicon vertexing (VELO) sub-detector for excellent vertex and proper decay time resolutions. The VELO detector sits at a position of only 7 mm from the LHC proton beams. However, the proximity of the silicon sensors to the proton beams results in the detectors suffering radiation damage. Radiation damage results in three changes in the macroscopic properties of the silicon detector: an increase of the leakage current, a decrease in the charge collection efficiency, and changes in the operation voltage required to fully deplete the silicon detector of the free charge carriers. Due to this radiation damage, it is expected that a replacement or upgrade of the LHCb vertex detector will be required by 2010, only 3 years after the turn-on of the LHC. This thesis...

Design of a charge sensitive preamplifier on high resistivity silicon

International Nuclear Information System (INIS)

Radeka, V.; Rehak, P.; Rescia, S.; Gatti, E.; Longoni, A.; Sampietro, M.; Holl, P.; Strueder, L.; Kemmer, J.

1987-01-01

A low noise, fast charge sensitive preamplifier was designed on high resistivity, detector grade silicon. It is built at the surface of a fully depleted region of n-type silicon. This allows the preamplifier to be placed very close to a detector anode. The preamplifier uses the classical input cascode configuration with a capacitor and a high value resistor in the feedback loop. The output stage of the preamplifier can drive a load up to 20pF. The power dissipation of the preamplifier is 13mW. The amplifying elements are ''Single Sided Gate JFETs'' developed especially for this application. Preamplifiers connected to a low capacitance anode of a drift type detector should achieve a rise time of 20ns and have an equivalent noise charge (ENC), after a suitable shaping, of less than 50 electrons. This performance translates to a position resolution better than 3μm for silicon drift detectors. 6 refs., 9 figs

Analysis and design of tunable wideband microwave photonics phase shifter based on Fabry-Perot cavity and Bragg mirrors in silicon-on-insulator waveguide.

Science.gov (United States)

Qu, Pengfei; Zhou, Jingran; Chen, Weiyou; Li, Fumin; Li, Haibin; Liu, Caixia; Ruan, Shengping; Dong, Wei

2010-04-20

We designed a microwave (MW) photonics phase shifter, consisting of a Fabry-Perot filter, a phase modulation region (PMR), and distributed Bragg reflectors, in a silicon-on-insulator rib waveguide. The thermo-optics effect was employed to tune the PMR. It was theoretically demonstrated that the linear MW phase shift of 0-2pi could be achieved by a refractive index variation of 0-9.68x10(-3) in an ultrawideband (about 38?GHz-1.9?THz), and the corresponding tuning resolution was about 6.92 degrees / degrees C. The device had a very compact size. It could be easily integrated in silicon optoelectronic chips and expected to be widely used in the high-frequency MW photonics field.

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

Directory of Open Access Journals (Sweden)

Jiayang Wu

2018-04-01

Full Text Available We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI nanowires implemented by cascaded Sagnac loop reflector (CSLR resonators. We investigate mode splitting in these standing-wave (SW resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

Science.gov (United States)

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Dielectric response of fully and partially depleted ferroelectric thin films and inversion of the thickness effect

International Nuclear Information System (INIS)

Misirlioglu, I B; Yildiz, M

2013-01-01

We study the effect of full and partial depletion on the dielectric response characteristics of ferroelectric thin films with impurities via a computational approach. Using a thermodynamic approach along with the fundamental equations for semiconductors, we show that films with partial depletion display unique features and an enhanced dielectric response compared with those fully depleted. We find that the capacitance peak at switching can be significantly suppressed in the case of high impurity densities (>10 25 m −3 ) with relatively low ionization energy, of the order of 0.5 eV. For conserved number of species in films, electromigration of ionized impurities at room temperature is negligible and has nearly no effect on the dielectric response. In films with high impurity density, the dielectric response at zero bias is enhanced with respect to charge-free films or those with relatively low impurity density ( 24 m −3 ). We demonstrate that partially depleted films should be expected to exhibit peculiar capacitance–voltage characteristics at low and high bias and that the thickness effect probed in experiments in ferroelectric thin films could be entirely inverted in thin films with depletion charges where a higher dielectric response can be measured in thicker films. Therefore, depletion charge densities in ferroelectric thin films should be estimated before size-effect-related studies. Finally, we noted that these findings are in good qualitative agreement with dielectric measurements carried out on PbZr x Ti 1−x O 3 . (paper)

Active silicon x-ray for measuring electron temperature

International Nuclear Information System (INIS)

Snider, R.T.

1994-07-01

Silicon diodes are commonly used for x-ray measurements in the soft x-ray region between a few hundred ev and 20 keV. Recent work by Cho has shown that the charge collecting region in an underbiased silicon detector is the depletion depth plus some contribution from a region near the depleted region due to charge-diffusion. The depletion depth can be fully characterized as a function of the applied bias voltage and is roughly proportional to the squart root of the bias voltage. We propose a technique to exploit this effect to use the silicon within the detector as an actively controlled x-ray filter. With reasonable silicon manufacturing methods, a silicon diode detector can be constructed in which the sensitivity of the collected charge to the impinging photon energy spectrum can be changed dynamically in the visible to above the 20 keV range. This type of detector could be used to measure the electron temperature in, for example, a tokamak plasma by sweeping the applied bias voltage during a plasma discharge. The detector samples different parts of the energy spectrum during the bias sweep, and the data collected contains enough information to determine the electron temperature. Benefits and limitations of this technique will be discussed along with comparisons to similar methods for measuring electron temperature and other applications of an active silicon x-ray filter

A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

2015-10-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

International Nuclear Information System (INIS)

Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

2006-01-01

Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

International Nuclear Information System (INIS)

Obermann, Theresa

2017-06-01

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n + -implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e - to 3000 e - while the noise is 30 e - due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10 14 neutrons/cm 2 the performance suffers from the radiation damage leading to a signal of 1000 e - and a higher noise of 60 e - due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10 14 particles/cm 2 . Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10 14 particles/cm 2 ). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget

Improved Spatial Resolution in Thick, Fully-Depleted CCDs withEnhanced Red Sensitivity

Energy Technology Data Exchange (ETDEWEB)

Fairfield, Jessamyn A.; Groom, Donald E.; Bailey, Stephen J.; Bebek, Christopher J.; Holland, Stephen E.; Karcher, Armin; Kolbe,William F.; Lorenzon, Wolfgang; Roe, Natalie A.

2006-03-09

The point spread function (PSF) is an important measure of spatial resolution in CCDs for point-like objects, since it affects image quality and spectroscopic resolution. We present new data and theoretical developments for lateral charge diffusion in thick, fully-depleted charge-coupled devices (CCDs) developed at Lawrence Berkeley National Laboratory (LBNL). Because they can be over-depleted, the LBNL devices have no field-free region and diffusion is controlled through the application of an external bias voltage. We give results for a 3512 x 3512 format, 10.5 {micro}m pixel back-illuminated p-channel CCD developed for the SuperNova/Acceleration Probe (SNAP), a proposed satellite-based experiment designed to study dark energy. The PSF was measured at substrate bias voltages between 3 V and 115 V. At a bias voltage of 115 V, we measure an rms diffusion of 3.7 {+-} 0.2 {micro}m. Lateral charge diffusion in LBNL CCDs will meet the SNAP requirements.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Science.gov (United States)

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Electronic properties of InAs-based metal-insulator-semiconductor structures

CERN Document Server

Kuryshev, G L; Valisheva, N A

2001-01-01

The peculiarities of electronic processes in InAs-based MIS structures operating in the charge injection device mode and using as photodetectors in spectral range 2.5-3.05 mu m are investigated. A two-layer system consisting of anodic oxide and low-temperature silicon dioxide is used as an insulator. It is shown that fluoride-containing components that is introduced into the electrolyte decreases the value of the built-in charge and the surface state static density down to minimal measurable values <= 2 x 10 sup 1 sup 0 cm sup - sup 2 eV sup - sup 2. Physical and chemical characteristics of the surface states at the InAs-dielectric interface are discussed on the basis of data on phase composition of anodic oxides obtained by means of X-ray photoelectronic spectroscopy. Anomalous field generation was also observed under the semiconductor non-equilibrium depletion. The processes of tunnel generation and the noise behavior of MIS structures under non-equilibrium depletion are investigated

Temperature dependence of the radiation induced change of depletion voltage in silicon PIN detectors

International Nuclear Information System (INIS)

Ziock, H.J.; Holzscheiter, K.; Morgan, A.; Palounek, A.P.T.; Ellison, J.; Heinson, A.P.; Mason, M.; Wimpenny, S.J.; Barberis, E.; Cartiglia, N.; Grillo, A.; O'Shaughnessy, K.; Rahn, J.; Rinaldi, P.; Rowe, W.A.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E.; Webster, A.; Wichmann, R.; Wilder, M.; Coupal, D.; Pal, T.

1993-01-01

The silicon microstrip detectors that will be used in the SDC experiment at the Superconducting Super Collider (SSC) will be exposed to very large fluences of charged particles, neutrons, and gammas. The authors present a study of how temperature affects the change in the depletion voltage of silicon PIN detectors damaged by radiation. They study the initial radiation damage and the short-term and long-term annealing of that damage as a function of temperature in the range from -10 degrees C to +50 degrees C, and as a function of 800 MeV proton fluence up to 1.5 x 10 14 p/cm 2 . They express the pronounced temperature dependencies in a simple model in terms of two annealing time constants which depend exponentially on the temperature

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

Science.gov (United States)

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-08-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Natural Contamination and Surface Flashover on Silicone Rubber Surface under Haze–Fog Environment

Directory of Open Access Journals (Sweden)

Ang Ren

2017-10-01

Full Text Available Anti-pollution flashover of insulator is important for power systems. In recent years, haze-fog weather occurs frequently, which makes discharge occurs easily on the insulator surface and accelerates insulation aging of insulator. In order to study the influence of haze-fog on the surface discharge of room temperature vulcanized silicone rubber, an artificial haze-fog lab was established. Based on four consecutive years of insulator contamination accumulation and atmospheric sampling in haze-fog environment, the contamination configuration appropriate for RTV-coated surface discharge test under simulation environment of haze-fog was put forward. ANSYS Maxwell was used to analyze the influence of room temperature vulcanized silicone rubber surface attachments on electric field distribution. The changes of droplet on the polluted room temperature vulcanized silicone rubber surface and the corresponding surface flashover voltage under alternating current (AC, direct current (DC positive polar (+, and DC negative polar (− power source were recorded by a high speed camera. The results are as follows: The main ion components from haze-fog atmospheric particles are NO3−, SO42−, NH4+, and Ca2+. In haze-fog environment, both the equivalent salt deposit density (ESDD and non-soluble deposit density (NSDD of insulators are higher than that under general environment. The amount of large particles on the AC transmission line is greater than that of the DC transmission line. The influence of DC polarity power source on the distribution of contamination particle size is not significant. After the deposition of haze-fog, the local conductivity of the room temperature vulcanized silicone rubber surface increased, which caused the flashover voltage reduce. Discharge is liable to occur at the triple junction point of droplet, air, and room temperature vulcanized silicone rubber surface. After the deformation or movement of droplets, a new triple junction

Solar thermoelectric generators fabricated on a silicon-on-insulator substrate

International Nuclear Information System (INIS)

De Leon, Maria Theresa; Chong, Harold; Kraft, Michael

2014-01-01

Solar thermal power generation is an attractive electricity generation technology as it is environment-friendly, has the potential for increased efficiency, and has high reliability. The design, modelling, and evaluation of solar thermoelectric generators (STEGs) fabricated on a silicon-on-insulator substrate are presented in this paper. Solar concentration is achieved by using a focusing lens to concentrate solar input onto the membrane of the STEG. A thermal model is developed based on energy balance and heat transfer equations using lumped thermal conductances. This thermal model is shown to be in good agreement with actual measurement results. For a 1 W laser input with a spot size of 1 mm, a maximum open-circuit voltage of 3.06 V is obtained, which translates to a temperature difference of 226 °C across the thermoelements and delivers 25 µW of output power under matched load conditions. Based on solar simulator measurements, a maximum TEG voltage of 803 mV was achieved by using a 50.8 mm diameter plano-convex lens to focus solar input to a TEG with a length of 1000 µm, width of 15 µm, membrane diameter of 3 mm, and 114 thermocouples. This translates to a temperature difference of 18 °C across the thermoelements and an output power under matched load conditions of 431 nW. This paper demonstrates that by utilizing a solar concentrator to focus solar radiation onto the hot junction of a TEG, the temperature difference across the device is increased; subsequently improving the TEG’s efficiency. By using materials that are compatible with standard CMOS and MEMS processes, integration of solar-driven TEGs with on-chip electronics is seen to be a viable way of solar energy harvesting where the resulting microscale system is envisioned to have promising applications in on-board power sources, sensor networks, and autonomous microsystems. (paper)

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

Directory of Open Access Journals (Sweden)

D. SINDHANAISELVI

2017-07-01

Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

Science.gov (United States)

Pradeepkumar, Aiswarya; Zielinski, Marcin; Bosi, Matteo; Verzellesi, Giovanni; Gaskill, D. Kurt; Iacopi, Francesca

2018-06-01

Heteroepitaxial 3C-SiC films on silicon substrates are of technological interest as enablers to integrate the excellent electrical, electronic, mechanical, thermal, and epitaxial properties of bulk silicon carbide into well-established silicon technologies. One critical bottleneck of this integration is the establishment of a stable and reliable electronic junction at the heteroepitaxial interface of the n-type SiC with the silicon substrate. We have thus investigated in detail the electrical and transport properties of heteroepitaxial cubic silicon carbide films grown via different methods on low-doped and high-resistivity silicon substrates by using van der Pauw Hall and transfer length measurements as test vehicles. We have found that Si and C intermixing upon or after growth, particularly by the diffusion of carbon into the silicon matrix, creates extensive interstitial carbon traps and hampers the formation of a stable rectifying or insulating junction at the SiC/Si interface. Although a reliable p-n junction may not be realistic in the SiC/Si system, we can achieve, from a point of view of the electrical isolation of in-plane SiC structures, leakage suppression through the substrate by using a high-resistivity silicon substrate coupled with deep recess etching in between the SiC structures.

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

Science.gov (United States)

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

High-field Overhauser dynamic nuclear polarization in silicon below the metal-insulator transition.

Science.gov (United States)

Dementyev, Anatoly E; Cory, David G; Ramanathan, Chandrasekhar

2011-04-21

Single crystal silicon is an excellent system to explore dynamic nuclear polarization (DNP), as it exhibits a continuum of properties from metallic to insulating as a function of doping concentration and temperature. At low doping concentrations DNP has been observed to occur via the solid effect, while at very high-doping concentrations an Overhauser mechanism is responsible. Here we report the hyperpolarization of (29)Si in n-doped silicon crystals, with doping concentrations in the range of (1-3) × 10(17) cm(-3). In this regime exchange interactions between donors become extremely important. The sign of the enhancement in our experiments and its frequency dependence suggest that the (29)Si spins are directly polarized by donor electrons via an Overhauser mechanism within exchange-coupled donor clusters. The exchange interaction between donors only needs to be larger than the silicon hyperfine interaction (typically much smaller than the donor hyperfine coupling) to enable this Overhauser mechanism. Nuclear polarization enhancement is observed for a range of donor clusters in which the exchange energy is comparable to the donor hyperfine interaction. The DNP dynamics are characterized by a single exponential time constant that depends on the microwave power, indicating that the Overhauser mechanism is a rate-limiting step. Since only about 2% of the silicon nuclei are located within 1 Bohr radius of the donor electron, nuclear spin diffusion is important in transferring the polarization to all the spins. However, the spin-diffusion time is much shorter than the Overhauser time due to the relatively weak silicon hyperfine coupling strength. In a 2.35 T magnetic field at 1.1 K, we observed a DNP enhancement of 244 ± 84 resulting in a silicon polarization of 10.4 ± 3.4% following 2 h of microwave irradiation.

Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

2012-01-01

Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

Determination of the quasi-TE mode (in-plane) graphene linear absorption coefficient via integration with silicon-on-insulator racetrack cavity resonators.

Science.gov (United States)

Crowe, Iain F; Clark, Nicholas; Hussein, Siham; Towlson, Brian; Whittaker, Eric; Milosevic, Milan M; Gardes, Frederic Y; Mashanovich, Goran Z; Halsall, Matthew P; Vijayaraghaven, Aravind

2014-07-28

We examine the near-IR light-matter interaction for graphene integrated cavity ring resonators based on silicon-on-insulator (SOI) race-track waveguides. Fitting of the cavity resonances from quasi-TE mode transmission spectra reveal the real part of the effective refractive index for graphene, n(eff) = 2.23 ± 0.02 and linear absorption coefficient, α(gTE) = 0.11 ± 0.01dBμm(-1). The evanescent nature of the guided mode coupling to graphene at resonance depends strongly on the height of the graphene above the cavity, which places limits on the cavity length for optical sensing applications.

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Obermann, Theresa

2017-06-15

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n{sup +}-implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e{sup -} to 3000 e{sup -} while the noise is 30 e{sup -} due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10{sup 14} neutrons/cm{sup 2} the performance suffers from the radiation damage leading to a signal of 1000 e{sup -} and a higher noise of 60 e{sup -} due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10{sup 14} particles/cm{sup 2}. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10{sup 14} particles/cm{sup 2}). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

2016-07-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

Flexible and transparent silicon-on-polymer based sub-20 nm non-planar 3D FinFET for brain-architecture inspired computation

KAUST Repository

Sevilla, Galo T.; Rojas, Jhonathan Prieto; Fahad, Hossain M.; Hussain, Aftab M.; Ghanem, Rawan; Smith, Casey; Hussain, Muhammad Mustafa

2014-01-01

An industry standard 8′′ silicon-on-insulator wafer based ultra-thin (1 μm), ultra-light-weight, fully flexible and remarkably transparent state-of-the-art non-planar three dimensional (3D) FinFET is shown. Introduced by Intel Corporation in 2011 as the most advanced transistor architecture, it reveals sub-20 nm features and the highest performance ever reported for a flexible transistor. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible and transparent silicon-on-polymer based sub-20 nm non-planar 3D FinFET for brain-architecture inspired computation

KAUST Repository

Sevilla, Galo T.

2014-02-22

An industry standard 8′′ silicon-on-insulator wafer based ultra-thin (1 μm), ultra-light-weight, fully flexible and remarkably transparent state-of-the-art non-planar three dimensional (3D) FinFET is shown. Introduced by Intel Corporation in 2011 as the most advanced transistor architecture, it reveals sub-20 nm features and the highest performance ever reported for a flexible transistor. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An Ultra-Efficient Nonlinear Platform: AlGaAs-On-Insulator

DEFF Research Database (Denmark)

Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

The combination of nonlinear and integrated photonics enables applications including optical signal processing, multi-wavelength lasers, metrology, spectroscopy, and quantum information science. Silicon-on-insulator (SOI) has emerged as a promising platform [1, 2] due to its high material...... nonlinearity and its compatibility with the CMOS industry. However, silicon suffers two-photon absorption (TPA) in the telecommunication wavelength band around 1.55 µm, which hampers its applications. Different platforms have been proposed to avoid TPA in the telecom wavelength range such as Si3N4 and Hydex [3...... a nonlinear index (n2) on the order of 10−17 W/m2 and a high refractive index (n ≈3.3), a large transparency window (from near- to mid-infrared), and the ability to engineer the material bandgap to mitigate TPA [5]. In this presentation, we introduce AlGaAson-insulator (AlGaAsOI) platform which combines both...

Improved installation approach for variable spring setting on a pipe yet to be insulated

International Nuclear Information System (INIS)

Shah, H.H.; Chitnis, S.S.; Rencher, D.

1993-01-01

This paper provides an approach in setting of variable spring supports for noninsulated or partially insulated piping systems so that resetting these supports is not required when the insulation is fully installed. This approach shows a method of deriving the spring coldload setting tolerance values that can be readily utilized by craft personnel. This method is based on the percentage of the weight of the insulation compared to the total weight of the pipe and the applicable tolerance. Use of these setting tolerances eliminates reverification of the original cold-load settings, for the majority of variable springs when the insulation is fully installed

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

International Nuclear Information System (INIS)

Wang Zhigang; Zhang Bo; Li Zhaoji

2013-01-01

A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

Science.gov (United States)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET.

Science.gov (United States)

Jang, Taejin; Baek, Myung-Hyun; Kim, Hyungjin; Park, Byung-Gook

2018-09-01

In this paper, we demonstrate the characteristics of the floating body effect of poly-silicon with grain boundary by SENTAURUS™ TCAD simulation. As drain voltage increases, impact ionization occurs at the drain-channel junction. And these holes created by impact ionization are deposited on the bottom of the body to change the threshold voltage. This feature, the kink effect, is also observed in fully depleted silicon on insulator because grain boundary of the poly-silicon serve as a storage to trap the holes. We simulate the transfer curve depending on the density and position of the grain boundary. The trap density of the grain boundary affects the device characteristics significantly. However similar properties appear except where the grain boundary is located on the drain side.

Resistivity measurements on the neutron irradiated detector grade silicon materials

Energy Technology Data Exchange (ETDEWEB)

Li, Zheng

1993-11-01

Resistivity measurements under the condition of no or low electrical field (electrical neutral bulk or ENB condition) have been made on various device configurations on detector grade silicon materials after neutron irradiation. Results of the measurements have shown that the ENB resistivity increases with neutron fluence ({Phi}{sub n}) at low {phi}{sub n} (<10{sup 13} n/cm{sup 2}) and saturates at a value between 300 and 400 k{Omega}-cm at {phi}{sub n} {approximately}10{sup 13} n/cm{sup 2}. Meanwhile, the effective doping concentration N{sub eff} in the space charge region (SCR) obtained from the C-V measurements of fully depleted p{sup +}/n silicon junction detectors has been found to increase nearly linearly with {phi}{sub n} at high fluences ({phi}{sub n} > 10{sup 13} n/cm{sup 2}). The experimental results are explained by the deep levels crossing the Fermi level in the SCR and near perfect compensation in the ENB by all deep levels, resulting in N{sub eff} (SCR) {ne} n or p (free carrier concentrations in the ENB).

Formation and dielectric properties of polyelectrolyte multilayers studied by a silicon-on-insulator based thin film resistor.

Science.gov (United States)

Neff, Petra A; Wunderlich, Bernhard K; Klitzing, Regine V; Bausch, Andreas R

2007-03-27

The formation of polyelectrolyte multilayers (PEMs) is investigated using a silicon-on-insulator based thin film resistor which is sensitive to variations of the surface potential. The buildup of the PEMs at the silicon oxide surface of the device can be observed in real time as defined potential shifts. The influence of polymer charge density is studied using the strong polyanion poly(styrene sulfonate), PSS, combined with the statistical copolymer poly(diallyl-dimethyl-ammoniumchloride-stat-N-methyl-N-vinylacetamide), P(DADMAC-stat-NMVA), at various degrees of charge (DC). The multilayer formation stops after a few deposition steps for a DC below 75%. We show that the threshold of surface charge compensation corresponds to the threshold of multilayer formation. However, no reversion of the preceding surface charge was observed. Screening of polyelectrolyte charges by mobile ions within the polymer film leads to a decrease of the potential shifts with the number of layers deposited. This decrease is much slower for PEMs consisting of P(DADMAC-stat-NMVA) and PSS as compared to PEMs consisting of poly(allylamine-hydrochloride), PAH, and PSS. From this, significant differences in the dielectric constants of the polyelectrolyte films and in the concentration of mobile ions within the films can be derived.

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

Science.gov (United States)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

High-density oxidized porous silicon

International Nuclear Information System (INIS)

Gharbi, Ahmed; Souifi, Abdelkader; Remaki, Boudjemaa; Halimaoui, Aomar; Bensahel, Daniel

2012-01-01

We have studied oxidized porous silicon (OPS) properties using Fourier transform infraRed (FTIR) spectroscopy and capacitance–voltage C–V measurements. We report the first experimental determination of the optimum porosity allowing the elaboration of high-density OPS insulators. This is an important contribution to the research of thick integrated electrical insulators on porous silicon based on an optimized process ensuring dielectric quality (complete oxidation) and mechanical and chemical reliability (no residual pores or silicon crystallites). Through the measurement of the refractive indexes of the porous silicon (PS) layer before and after oxidation, one can determine the structural composition of the OPS material in silicon, air and silica. We have experimentally demonstrated that a porosity approaching 56% of the as-prepared PS layer is required to ensure a complete oxidation of PS without residual silicon crystallites and with minimum porosity. The effective dielectric constant values of OPS materials determined from capacitance–voltage C–V measurements are discussed and compared to FTIR results predictions. (paper)

Fully developed magnetohydrodynamic flows in rectangular ducts with insulating walls

International Nuclear Information System (INIS)

Molokov, S.; Kernforschungszentrum Karlsruhe GmbH; Shishko, A.

1993-10-01

In the first part the effect of magnetic field inclination on the flow structure and the pressure drop is considered. The duct walls are insulating. An asymptotic solution to the problem at high Hartmann numbers is obtained. The results show that for a square duct the increase of the pressure gradient due to the field inclination is negligible (less than 10% for any angle). For blanket relevant values of inclination of up to 10 the deviation of the velocity profile from the slug profile is insignificant. The second part studies the flow in a duct with insulating walls parallel to the magnetic field, while the Hartmann walls are covered by an insulating coating. A new type of the boundary condition is derived, which takes into account finite coating resistance. The effect of the latter on the flow characteristics is studied. An exact solution to the problem is obtained and several approximate formulas for the pressure drop at high Hartmann numbers are presented. (orig./HP) [de

Characterization of light element impurities in ultrathin silicon-on-insulator layers by luminescence activation using electron irradiation

International Nuclear Information System (INIS)

Nakagawa-Toyota, Satoko; Tajima, Michio; Hirose, Kazuyuki; Ohshima, Takeshi; Itoh, Hisayoshi

2009-01-01

We analyzed light element impurities in ultrathin top Si layers of silicon-on-insulator (SOI) wafers by luminescence activation using electron irradiation. Photoluminescence (PL) analysis under ultraviolet (UV) light excitation was performed on various commercial SOI wafers after the irradiation. We detected the C-line related to a complex of interstitial carbon and oxygen impurities and the G-line related to a complex of interstitial and substitutional carbon impurities in the top Si layer with a thickness down to 62 nm after electron irradiation. We showed that there were differences in the impurity concentration depending on the wafer fabrication methods and also that there were variations in these concentrations in the respective wafers. Xenon ion implantation was used to activate top Si layers selectively so that we could confirm that the PL signal under the UV light excitation comes not from substrates but from top Si layers. The present method is a very promising tool to evaluate the light element impurities in top Si layers. (author)

Label-free electrical determination of trypsin activity by a silicon-on-insulator based thin film resistor.

Science.gov (United States)

Neff, Petra A; Serr, Andreas; Wunderlich, Bernhard K; Bausch, Andreas R

2007-10-08

A silicon-on-insulator (SOI) based thin film resistor is employed for the label-free determination of enzymatic activity. We demonstrate that enzymes, which cleave biological polyelectrolyte substrates, can be detected by the sensor. As an application, we consider the serine endopeptidase trypsin, which cleaves poly-L-lysine (PLL). We show that PLL adsorbs quasi-irreversibly to the sensor and is digested by trypsin directly at the sensor surface. The created PLL fragments are released into the bulk solution due to kinetic reasons. This results in a measurable change of the surface potential allowing for the determination of trypsin concentrations down to 50 ng mL(-1). Chymotrypsin is a similar endopeptidase with a different specificity, which cleaves PLL with a lower efficiency as compared to trypsin. The activity of trypsin is analyzed quantitatively employing a kinetic model for enzyme-catalyzed surface reactions. Moreover, we have demonstrated the specific inactivation of trypsin by a serine protease inhibitor, which covalently binds to the active site of the enzyme.

Study of thin insulating films using secondary ion emission

International Nuclear Information System (INIS)

Hilleret, Noel

1973-01-01

Secondary ion emission from insulating films was investigated using a CASTAING-SLODZIAN ion analyzer. Various different aspects of the problem were studied: charge flow across a silica film; the mobilization of sodium during ion bombardment; consequences of the introduction of oxygen on the emission of secondary ions from some solids; determination of the various characteristics of secondary ion emission from silica, silicon nitride and silicon. An example of measurements made using this type of operation is presented: profiles (concentration as a function of depth) of boron introduced by diffusion or implantation in thin films of silica on silicon or silicon nitride. Such measurements have applications in microelectronics. The same method of operation was extended to other types of insulating film, and in particular, to the metallurgical study of passivation films formed on the surface of stainless steels. (author) [fr

Ultrafast all-optical switching and error-free 10 Gbit/s wavelength conversion in hybrid InP-silicon on insulator nanocavities using surface quantum wells

Energy Technology Data Exchange (ETDEWEB)

Bazin, Alexandre; Monnier, Paul; Beaudoin, Grégoire; Sagnes, Isabelle; Raj, Rama [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Lenglé, Kevin; Gay, Mathilde; Bramerie, Laurent [Université Européenne de Bretagne (UEB), 5 Boulevard Laënnec, 35000 Rennes (France); CNRS-Foton Laboratory (UMR 6082), Enssat, BP 80518, 22305 Lannion Cedex (France); Braive, Rémy; Raineri, Fabrice, E-mail: fabrice.raineri@lpn.cnrs.fr [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Université Paris Diderot, Sorbonne Paris Cité, 75207 Paris Cedex 13 (France)

2014-01-06

Ultrafast switching with low energies is demonstrated using InP photonic crystal nanocavities embedding InGaAs surface quantum wells heterogeneously integrated to a silicon on insulator waveguide circuitry. Thanks to the engineered enhancement of surface non radiative recombination of carriers, switching time is obtained to be as fast as 10 ps. These hybrid nanostructures are shown to be capable of achieving systems level performance by demonstrating error free wavelength conversion at 10 Gbit/s with 6 mW switching powers.

Annealing effects on magnetic properties of silicone-coated iron-based soft magnetic composites

Science.gov (United States)

Wu, Shen; Sun, Aizhi; Zhai, Fuqiang; Wang, Jin; Zhang, Qian; Xu, Wenhuan; Logan, Philip; Volinsky, Alex A.

2012-03-01

This paper focuses on novel iron-based soft magnetic composites synthesis utilizing high thermal stability silicone resin to coat iron powder. The effect of an annealing treatment on the magnetic properties of synthesized magnets was investigated. The coated silicone insulating layer was characterized by scanning electron microscopy and energy dispersive X-ray spectroscopy. Silicone uniformly coated the powder surface, resulting in a reduction of the imaginary part of the permeability, thereby increasing the electrical resistivity and the operating frequency of the synthesized magnets. The annealing treatment increased the initial permeability, the maximum permeability, and the magnetic induction, and decreased the coercivity. Annealing at 580 °C increased the maximum permeability by 72.5%. The result of annealing at 580 °C shows that the ferromagnetic resonance frequency increased from 2 kHz for conventional epoxy resin coated samples to 80 kHz for the silicone resin insulated composites.

Formation and properties of the buried isolating silicon-dioxide layer in double-layer “porous silicon-on-insulator” structures

Energy Technology Data Exchange (ETDEWEB)

Bolotov, V. V.; Knyazev, E. V.; Ponomareva, I. V.; Kan, V. E., E-mail: kan@obisp.oscsbras.ru; Davletkildeev, N. A.; Ivlev, K. E.; Roslikov, V. E. [Russian Academy of Sciences, Omsk Scientific Center, Siberian Branch (Russian Federation)

2017-01-15

The oxidation of mesoporous silicon in a double-layer “macroporous silicon–mesoporous silicon” structure is studied. The morphology and dielectric properties of the buried insulating layer are investigated using electron microscopy, ellipsometry, and electrical measurements. Specific defects (so-called spikes) are revealed between the oxidized macropore walls in macroporous silicon and the oxidation crossing fronts in mesoporous silicon. It is found that, at an initial porosity of mesoporous silicon of 60%, three-stage thermal oxidation leads to the formation of buried silicon-dioxide layers with an electric-field breakdown strength of E{sub br} ~ 10{sup 4}–10{sup 5} V/cm. Multilayered “porous silicon-on-insulator” structures are shown to be promising for integrated chemical micro- and nanosensors.

Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

Energy Technology Data Exchange (ETDEWEB)

Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

2009-06-10

We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film.

Science.gov (United States)

Yebo, Nebiyu A; Lommens, Petra; Hens, Zeger; Baets, Roel

2010-05-24

Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 microm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.

Processing of n{sup +}/p{sup −}/p{sup +} strip detectors with atomic layer deposition (ALD) grown Al{sub 2}O{sub 3} field insulator on magnetic Czochralski silicon (MCz-si) substrates

Energy Technology Data Exchange (ETDEWEB)

Härkönen, J., E-mail: jaakko.harkonen@helsinki.fi [Helsinki Institute of Physics (Finland); Tuovinen, E. [Helsinki Institute of Physics (Finland); VTT Technical Research Centre of Finland, Microsystems and Nanoelectronics (Finland); Luukka, P.; Gädda, A.; Mäenpää, T.; Tuominen, E.; Arsenovich, T. [Helsinki Institute of Physics (Finland); Junkes, A. [Institute for Experimental Physics, University of Hamburg (Germany); Wu, X. [VTT Technical Research Centre of Finland, Microsystems and Nanoelectronics (Finland); Picosun Oy, Tietotie 3, FI-02150 Espoo Finland (Finland); Li, Z. [School of Materials Science and Engineering, Xiangtan University, Xiangtan, Hunan 411105 (China)

2016-08-21

Detectors manufactured on p-type silicon material are known to have significant advantages in very harsh radiation environment over n-type detectors, traditionally used in High Energy Physics experiments for particle tracking. In p-type (n{sup +} segmentation on p substrate) position-sensitive strip detectors, however, the fixed oxide charge in the silicon dioxide is positive and, thus, causes electron accumulation at the Si/SiO{sub 2} interface. As a result, unless appropriate interstrip isolation is applied, the n-type strips are short-circuited. Widely adopted methods to terminate surface electron accumulation are segmented p-stop or p-spray field implantations. A different approach to overcome the near-surface electron accumulation at the interface of silicon dioxide and p-type silicon is to deposit a thin film field insulator with negative oxide charge. We have processed silicon strip detectors on p-type Magnetic Czochralski silicon (MCz-Si) substrates with aluminum oxide (Al{sub 2}O{sub 3}) thin film insulator, grown with Atomic Layer Deposition (ALD) method. The electrical characterization by current–voltage and capacitance−voltage measurement shows reliable performance of the aluminum oxide. The final proof of concept was obtained at the test beam with 200 GeV/c muons. For the non-irradiated detector the charge collection efficiency (CCE) was nearly 100% with a signal-to-noise ratio (S/N) of about 40, whereas for the 2×10{sup 15} n{sub eq}/cm{sup 2} proton irradiated detector the CCE was 35%, when the sensor was biased at 500 V. These results are comparable with the results from p-type detectors with the p-spray and p-stop interstrip isolation techniques. In addition, interestingly, when the aluminum oxide was irradiated with Co-60 gamma-rays, an accumulation of negative fixed oxide charge in the oxide was observed.

Evaluation of a silicon 5 MHz p–n diode actuator with a laterally vibrating extensional mode

Science.gov (United States)

Miyazaki, Fumito; Baba, Kazuki; Tanigawa, Hiroshi; Furutsuka, Takashi; Suzuki, Kenichiro

2018-05-01

In this paper, we describe p–n diode actuators that are laterally driven by the force induced in a depletion layer. The previously reported p–n diode actuators have been vertically driven. Because the resonant frequency depends on the thickness of the vibrating plate, the integration of resonators with different frequencies on a chip has been difficult. The resonators in this work are driven laterally by using length-extensional vibration. We have developed a compact model based on an analytical expression, in which p–n diode actuators are driven by the forces induced by the spread of the depletion layer. The deflection generated by the p–n diode actuators was proportional to the ratio of the depletion layer width to the resonator thickness as well as the position of the p–n junction. Good agreement of experimental results with the theory was confirmed by comparing the measured values for silicon p–n diode rectangular-plate actuators fabricated using a silicon-on-insulator (SOI) substrate. The displacement amplitude of the actuators was proportional to the DC bias, while the resonant frequency was independent of the DC bias. The latter characteristic is very different from that of widely used electrostatic actuators. Although the amplitude of the actuator measured in this work was very small, it is expected that the amplitude will increase greatly by increasing the doping of the p–n diode actuators.

Thermal insulation product for insulation, especially in nuclear power engineering, and method of its production

International Nuclear Information System (INIS)

Veselovsky, P.; Zink, S.; Balacek, P.; Mares, I.

1989-01-01

The insulation consists of a sewn fabric cover made of inorganic fibers, in which the fiber filling is reinforced mechanically by dense point interweaving. The inorganic fibers, 1 to 5 μm in diameter, consist of min. 97 wt.% mixture of aluminium and silicon oxides in the vitreous state. The fibers making up the cover consist of min. 95% silicon, aluminium, calcium, magnesium and boron oxides in the vitreous state; the rest can consist of alloy steel fibres. The bulk density of the insulation is 70 to 150 kg/m 3 . The product is highly resistant to temperature and to the action of chemicals, water, and acid and alkaline deactivation solutions. Its manufacture is fast and undemanding. It is designed for thermal insulation of pipes, tanks and valves in nuclear power plants. (M.D.). 2 figs

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Science.gov (United States)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Silicon Chip-to-Chip Mode-Division Multiplexing

DEFF Research Database (Denmark)

Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

2018-01-01

A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

Science.gov (United States)

Maulik, Subhodip; Sarkar, Anirban; Basu, Srismrita; Daniels-Race, Theda

2018-05-01

A facile, cost-effective, voltage-controlled, "single-step" method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

Oxygen-induced inhibition of silicon-on-insulator dewetting

Energy Technology Data Exchange (ETDEWEB)

Curiotto, S.; Leroy, F.; Cheynis, F.; Müller, P. [Aix Marseille Université, CNRS, CINaM UMR 7325, 13288 Marseille (France)

2014-02-10

We report that solid state dewetting of Si thin film on SiO{sub 2} can be reversibly inhibited by exposing the Si surface to a partial pressure of dioxygen (∼10{sup −7}Torr) at high temperature (∼1100K). Coupling in situ Low-Energy Electron Microscopy and ex situ atomic force microscopy we propose that the pinning of the contact line induced by the presence of small amounts of silicon oxide is the main physical process that inhibits the dewetting.

Friction-induced nanofabrication on monocrystalline silicon

International Nuclear Information System (INIS)

Yu Bingjun; Qian Linmao; Yu Jiaxin; Zhou Zhongrong; Dong Hanshan; Chen Yunfei

2009-01-01

Fabrication of nanostructures has become a major concern as the scaling of device dimensions continues. In this paper, a friction-induced nanofabrication method is proposed to fabricate protrusive nanostructures on silicon. Without applying any voltage, the nanofabrication is completed by sliding an AFM diamond tip on a sample surface under a given normal load. Nanostructured patterns, such as linear nanostructures, nanodots or nanowords, can be fabricated on the target surface. The height of these nanostructures increases rapidly at first and then levels off with the increasing normal load or number of scratching cycles. TEM analyses suggest that the friction-induced hillock is composed of silicon oxide, amorphous silicon and deformed silicon structures. Compared to the tribochemical reaction, the amorphization and crystal defects induced by the mechanical interaction may have played a dominating role in the formation of the hillocks. Similar to other proximal probe methods, the proposed method enables fabrication at specified locations and facilitates measuring the dimensions of nanostructures with high precision. It is highlighted that the fabrication can also be realized on electrical insulators or oxide surfaces, such as quartz and glass. Therefore, the friction-induced method points out a new route in fabricating nanostructures on demand.

The effects of imperfect insulator coatings on MHD and heat transfer in rectangular duct

International Nuclear Information System (INIS)

Ying, A.Y.; Gaizer, A.A.

1994-01-01

In self cooled liquid metal blankets, the use of an insulator coating to reduce the flow of the eddy current to the structure leads to a significant reduction in MHD pressure drop. Furthermore, this insulating layer alters the velocity structure by reducing the potential difference between the side wall and boundary layer. The questions which arise are: (1) How the imperfections in the insulator coating affect the velocity profiles and their consequent impacts on heat transfer performance?; and, (2) How much crack can lead to an unacceptable MHD pressure drop? The dynamics of the crack healing in an insulator coating duct is one of the important subjects requiring study. The purpose of this work is to present numerical simulations of fully developed MHD flow and developing heat transfer characteristics in imperfectly insulated ducts, and to quantify the influences of crack locations, sizes and resistivities on 2-D MHD pressure drops. Comparisons of finite element solutions of pressure drops in partially insulated ducts with analytical solutions obtained from a circuit analogy show excellent agreement. In addition, the remarkable side layer velocity profile observed in a laminar MHD flow of a conducting duct gradually diminishes as the resistance of the insulating layer increases. The average side wall Nusselt number drops by a factor of 2 as the duct becomes fully insulated

Silicon on insulator by ion implantation: A dream or a reality

Energy Technology Data Exchange (ETDEWEB)

Pinizzotto, R F [Ultrastructure, Inc., Richardson, TX (USA)

1985-03-01

One method of producing a silicon-on-oxide structure is to implant a sufficient dose of oxygen into a conventional silicon substrate to synthesize a layer of SiO/sub 2/ just below the surface. If the proper implant conditions are maintained, the top silicon layer will be a single crystal. The required doses are large, but the use of commercially available medium current implanters can reduce the time to 25 minutes per wafer. This adds about $ 10 per chip in process related costs. A very large implanter (100 mA analyzed beam) may not be the best approach for scaling up the process. The power in the beam and the power required for operation of the machine are both enormous. A more conservative approach of using multiple medium current implanters may prove to be more economical in the long run.

Buried oxide layer in silicon

Science.gov (United States)

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

The bipolar silicon microstrip detector: A proposal for a novel precision tracking device

International Nuclear Information System (INIS)

Horisberger, R.

1990-01-01

It is proposed to combine the technology of fully depleted microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. The resulting structure has amplifying properties and is referred to as bipaolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking. (orig.)

A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

Science.gov (United States)

Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

2008-01-01

A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure

International Nuclear Information System (INIS)

Uchino, T; Gili, E; Ashburn, P; Tan, L; Buiu, O; Hall, S

2012-01-01

A vertical MOSFET (VMOST) incorporating an epitaxial channel and a drain junction in a stacked silicon-insulator structure is presented. In this device structure, an oxide layer near the drain junction edge (referred to as a junction stop) acts as a dopant diffusion barrier and consequently a shallow drain junction is formed to suppress short channel effects. To investigate the scalability of this device, a simulation study in the sub-100 nm regime calibrated to measured results on the fabricated devices is carried out. The use of an epitaxial channel delivers 50% higher drive current due to the higher mobility of the retrograde channel and the junction stop structure delivers improvements of threshold voltage roll-off and drain-induced barrier lowering compared with a conventional VMOST. (fast track communication)

Combined effect of bulk and surface damage on strip insulation properties of proton irradiated n$^{+}$-p silicon strip sensors

CERN Document Server

Dalal, R; Ranjan, K; Moll, M; Elliott-Peisert, A

2014-01-01

Silicon sensors in next generation hadron colliders willface a tremendously harsh radiation environment. Requirement tostudy rarest reaction channels with statistical constraints hasresulted in a huge increment in radiation flux, resulting in bothsurface damage and bulk damage. For sensors which are used in acharged hadron environment, both of these degrading processes takeplace simultaneously. Recently it has been observed in protonirradiated n$^{+}$-p Si strip sensors that n$^{+}$ strips had a goodinter-strip insulation with low values of p-spray and p-stop dopingdensities which is contrary to the expected behaviour from thecurrent understanding of radiation damage. In this work a simulationmodel has been devised incorporating radiation damage to understandand provide a possible explanation to the observed behaviour ofirradiated sensors.

Technology development for SOI monolithic pixel detectors

International Nuclear Information System (INIS)

Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

2006-01-01

A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

Bipolar resistive switching in metal-insulator-semiconductor nanostructures based on silicon nitride and silicon oxide

Science.gov (United States)

Koryazhkina, M. N.; Tikhov, S. V.; Mikhaylov, A. N.; Belov, A. I.; Korolev, D. S.; Antonov, I. N.; Karzanov, V. V.; Gorshkov, O. N.; Tetelbaum, D. I.; Karakolis, P.; Dimitrakis, P.

2018-03-01

Bipolar resistive switching in metal-insulator-semiconductor (MIS) capacitor-like structures with an inert Au top electrode and a Si3N4 insulator nanolayer (6 nm thick) has been observed. The effect of a highly doped n +-Si substrate and a SiO2 interlayer (2 nm) is revealed in the changes in the semiconductor space charge region and small-signal parameters of parallel and serial equivalent circuit models measured in the high- and low-resistive capacitor states, as well as under laser illumination. The increase in conductivity of the semiconductor capacitor plate significantly reduces the charging and discharging times of capacitor-like structures.

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

All-optical switching via four-wave mixing Bragg scattering in a silicon platform

Directory of Open Access Journals (Sweden)

Yun Zhao

2017-02-01

Full Text Available We employ the process of non-degenerate four-wave mixing Bragg scattering to demonstrate all-optical control in a silicon platform. In our configuration, a strong, non-information-carrying pump is mixed with a weak control pump and an input signal in a silicon-on-insulator waveguide. Through the optical nonlinearity of this highly confining waveguide, the weak pump controls the wavelength conversion process from the signal to an idler, leading to a controlled depletion of the signal. The strong pump, on the other hand, plays the role of a constant bias. In this work, we show experimentally that it is possible to implement this low-power switching technique as a first step towards universal optical logic gates, and test the performance with random binary data. Even at very low powers, where the signal and control pump levels are almost equal, the eye-diagrams remain open, indicating a successful operation of the logic gates.

Emerging heterogeneous integrated photonic platforms on silicon

Directory of Open Access Journals (Sweden)

Fathpour Sasan

2015-05-01

Full Text Available Silicon photonics has been established as a mature and promising technology for optoelectronic integrated circuits, mostly based on the silicon-on-insulator (SOI waveguide platform. However, not all optical functionalities can be satisfactorily achieved merely based on silicon, in general, and on the SOI platform, in particular. Long-known shortcomings of silicon-based integrated photonics are optical absorption (in the telecommunication wavelengths and feasibility of electrically-injected lasers (at least at room temperature. More recently, high two-photon and free-carrier absorptions required at high optical intensities for third-order optical nonlinear effects, inherent lack of second-order optical nonlinearity, low extinction ratio of modulators based on the free-carrier plasma effect, and the loss of the buried oxide layer of the SOI waveguides at mid-infrared wavelengths have been recognized as other shortcomings. Accordingly, several novel waveguide platforms have been developing to address these shortcomings of the SOI platform. Most of these emerging platforms are based on heterogeneous integration of other material systems on silicon substrates, and in some cases silicon is integrated on other substrates. Germanium and its binary alloys with silicon, III–V compound semiconductors, silicon nitride, tantalum pentoxide and other high-index dielectric or glass materials, as well as lithium niobate are some of the materials heterogeneously integrated on silicon substrates. The materials are typically integrated by a variety of epitaxial growth, bonding, ion implantation and slicing, etch back, spin-on-glass or other techniques. These wide range of efforts are reviewed here holistically to stress that there is no pure silicon or even group IV photonics per se. Rather, the future of the field of integrated photonics appears to be one of heterogenization, where a variety of different materials and waveguide platforms will be used for

Effect of Silicon on Intergranular Corrosion Resistance of Ti-stabilized 11 wt% Cr Ferritic Stainless Steels

International Nuclear Information System (INIS)

Hyun, Youngmin; Kim, Heesan

2013-01-01

Ti-stabilized 11 wt% Cr ferritic stainless steels (FSSs) for automotive exhaust systems have been experienced intergranular corrosion (IC) in some heat-affected zone (HAZ). The effects of sensitizing heat-treatment and silicon on IC were studied. Time-Temperature-Sensitization (TTS) curves showed that sensitization to IC was observed at the steels heat-treated at the temperature lower than 650 .deg. C and that silicon improved IC resistance. The sensitization was explained by chromium depletion theory, where chromium is depleted by precipitation of chromium carbide during sensitizing heat-treatment. It was confirmed with the results from the analysis of precipitates as well as the thermodynamical prediction of stable phases. In addition, the role of silicon on IC was explained with the stabilization of grain boundary. In other words, silicon promoted the formation of the grain boundaries with low energy where precipitation was suppressed and consequently, the formation of Cr-depleted zone was retarded. The effect of silicon on the formation of grain boundaries with low energy was proved by the analysis of coincidence site lattice (CSL) grain boundary, which is a typical grain boundary with low energy

Effect of Silicon on Intergranular Corrosion Resistance of Ti-stabilized 11 wt% Cr Ferritic Stainless Steels

Energy Technology Data Exchange (ETDEWEB)

Hyun, Youngmin; Kim, Heesan [Hongik Univ., Sejong (Korea, Republic of)

2013-06-15

Ti-stabilized 11 wt% Cr ferritic stainless steels (FSSs) for automotive exhaust systems have been experienced intergranular corrosion (IC) in some heat-affected zone (HAZ). The effects of sensitizing heat-treatment and silicon on IC were studied. Time-Temperature-Sensitization (TTS) curves showed that sensitization to IC was observed at the steels heat-treated at the temperature lower than 650 .deg. C and that silicon improved IC resistance. The sensitization was explained by chromium depletion theory, where chromium is depleted by precipitation of chromium carbide during sensitizing heat-treatment. It was confirmed with the results from the analysis of precipitates as well as the thermodynamical prediction of stable phases. In addition, the role of silicon on IC was explained with the stabilization of grain boundary. In other words, silicon promoted the formation of the grain boundaries with low energy where precipitation was suppressed and consequently, the formation of Cr-depleted zone was retarded. The effect of silicon on the formation of grain boundaries with low energy was proved by the analysis of coincidence site lattice (CSL) grain boundary, which is a typical grain boundary with low energy.

Fabrication of open-top microchannel plate using deep X-ray exposure mask made with silicon on insulator substrate

CERN Document Server

Fujimura, T; Etoh, S I; Hattori, R; Kuroki, Y; Chang, S S

2003-01-01

We propose a high-aspect-ratio open-top microchannel plate structure. This type of microchannel plate has many advantages in electrophoresis. The plate was fabricated by deep X-ray lithography using synchrotron radiation (SR) light and the chemical wet etching process. A deep X-ray exposure mask was fabricated with a silicon on insulator (SOI) substrate. The patterned Si microstructure was micromachined into a thin Si membrane and a thick Au X-ray absorber was embedded in it by electroplating. A plastic material, polymethylmethacrylate (PMMA) was used for the plate substrate. For reduction of the exposure time and high-aspect-ratio fast wet development, the fabrication condition was optimized with respect to not the exposure dose but to the PMMA mean molecular weight (M.W.) changing after deep X-ray exposure as measured by gel permeation chromatography (GPC). Decrement of the PMMA M.W. and increment of the wet developer temperature accelerated the etching rate. Under optimized fabrication conditions, a microc...

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

Science.gov (United States)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Forming of nanocrystal silicon films by implantation of high dose of H+ in layers of silicon on isolator and following fast thermal annealing

International Nuclear Information System (INIS)

Tyschenko, I.E.; Popov, V.P.; Talochkin, A.B.; Gutakovskij, A.K.; Zhuravlev, K.S.

2004-01-01

Formation of nanocrystalline silicon films during rapid thermal annealing of the high-dose H + ion implanted silicon-on-insulator structures was studied. It was found, that Si nanocrystals had formed alter annealings at 300-400 deg C, their formation being strongly limited by the hydrogen content in silicon and also by the annealing time. It was supposed that the nucleation of crystalline phase occurred inside the silicon islands between micropores. It is conditioned by ordering Si-Si bonds as hydrogen atoms are leaving their sites in silicon network. No coalescence of micropores takes place during the rapid thermal annealing at the temperatures up to ∼ 900 deg C. Green-orange photoluminescence was observed on synthesized films at room temperature [ru

Annealing effects on magnetic properties of silicone-coated iron-based soft magnetic composites

International Nuclear Information System (INIS)

Wu Shen; Sun Aizhi; Zhai Fuqiang; Wang Jin; Zhang Qian; Xu Wenhuan; Logan, Philip; Volinsky, Alex A.

2012-01-01

This paper focuses on novel iron-based soft magnetic composites synthesis utilizing high thermal stability silicone resin to coat iron powder. The effect of an annealing treatment on the magnetic properties of synthesized magnets was investigated. The coated silicone insulating layer was characterized by scanning electron microscopy and energy dispersive X-ray spectroscopy. Silicone uniformly coated the powder surface, resulting in a reduction of the imaginary part of the permeability, thereby increasing the electrical resistivity and the operating frequency of the synthesized magnets. The annealing treatment increased the initial permeability, the maximum permeability, and the magnetic induction, and decreased the coercivity. Annealing at 580 °C increased the maximum permeability by 72.5%. The result of annealing at 580 °C shows that the ferromagnetic resonance frequency increased from 2 kHz for conventional epoxy resin coated samples to 80 kHz for the silicone resin insulated composites. - Highlights: ► Silicone uniformly coated the powder, increased the operating frequency of SMCs. ► The annealing treatment increased the DC properties of SMCs. ► Annealing at 580 °C increased the maximum permeability by 72.5%. ► Compared with epoxy coated, the SMCs had higher resistivity annealing at 580 °C.

Reentrant Metal-Insulator Transitions in Silicon -

Science.gov (United States)

Campbell, John William M.

This thesis describes a study of reentrant metal -insulator transitions observed in the inversion layer of extremely high mobility Si-MOSFETs. Magneto-transport measurements were carried out in the temperature range 20mK-4.2 K in a ^3He/^4 He dilution refrigerator which was surrounded by a 15 Tesla superconducting magnet. Below a melting temperature (T_{M}~500 mK) and a critical electron density (n_{s }~9times10^{10} cm^{-2}), the Shubnikov -de Haas oscillations in the diagonal resistivity enormous maximum values at the half filled Landau levels while maintaining deep minima corresponding to the quantum Hall effect at filled Landau levels. At even lower electron densities the insulating regions began to spread and eventually a metal-insulator transition could be induced at zero magnetic field. The measurement of extremely large resistances in the milliKelvin temperature range required the use of very low currents (typically in the 10^ {-12} A range) and in certain measurements minimizing the noise was also a consideration. The improvements achieved in these areas through the use of shielding, optical decouplers and battery operated instruments are described. The transport signatures of the insulating state are considered in terms of two basic mechanisms: single particle localization with transport by variable range hopping and the formation of a collective state such as a pinned Wigner crystal or electron solid with transport through the motion of bound dislocation pairs. The experimental data is best described by the latter model. Thus the two dimensional electron system in these high mobility Si-MOSFETs provides the first and only experimental demonstration to date of the formation of an electron solid at zero and low magnetic fields in the quantum limit where the Coulomb interaction energy dominates over the zero point oscillation energy. The role of disorder in favouring either single particle localization or the formation of a Wigner crystal is explored by

Compact temperature-insensitive modulator based on a silicon microring assistant Mach—Zehnder interferometer

International Nuclear Information System (INIS)

Zhang Xue-Jian; Feng Xue; Zhang Deng-Ke; Huang Yi-Dong

2012-01-01

On the silicon-on-insulator platform, an ultra compact temperature-insensitive modulator based on a cascaded microring assistant Mach—Zehnder interferometer is proposed and demonstrated with numerical simulation. According to the calculated results, the tolerated variation of ambient temperature can be as high as 134 °C while the footprint of such a silicon modulator is only 340 μm 2 . (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

Hybrid Integrated Platforms for Silicon Photonics

Science.gov (United States)

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Distribution of electric field and charge collection in silicon strip detectors

International Nuclear Information System (INIS)

Anokhin, I.E.; Zinets, O.S.

1995-01-01

The distribution of electric field in silicon strip detectors is analyzed in the case of dull depletion as well as for partial depletion. Influence of inhomogeneous electric fields on the charge collection and performances of silicon strip detectors is discussed

The behavior of silicon and boron in the surface of corroded nuclear waste glasses: an EFTEM study

International Nuclear Information System (INIS)

Buck, E. C.; Smith, K. L.; Blackford, M. G.

1999-01-01

Using electron energy-loss filtered transmission electron microscopy (EFTEM), we have observed the formation of silicon-rich zones on the corroded surface of a West Valley (WV6) glass. This layer is approximately 100-200 nm thick and is directly underneath a precipitated smectite clay layer. Under conventional (C)TEM illumination, this layer is invisible; indeed, more commonly used analytical techniques, such as x-ray energy dispersive spectroscopy (EDS), have failed to describe fully the localized changes in the boron and silicon contents across this region. Similar silicon-rich and boron-depleted zones were not found on corroded Savannah River Laboratory (SRL) borosilicate glasses, including SRL-EA and SRL-51, although they possessed similar-looking clay layers. This study demonstrates a new tool for examining the corroded surfaces of materials

The Effect of Polymer Char on Nitridation Kinetics of Silicon

Science.gov (United States)

Chan, Rickmond C.; Bhatt, Ramakrishna T.

1994-01-01

Effects of polymer char on nitridation kinetics of attrition milled silicon powder have been investigated from 1200 to 1350 C. Results indicate that at and above 1250 C, the silicon compacts containing 3.5 wt percent polymer char were fully converted to Si3N4 after 24 hr exposure in nitrogen. In contrast, the silicon compacts without polymer char could not be fully converted to Si3N4 at 1350 C under similar exposure conditions. At 1250 and 1350 C, the silicon compacts with polymer char showed faster nitridation kinetics than those without the polymer char. As the polymer char content is increased, the amount of SiC in the nitrided material is also increased. By adding small amounts (approx. 2.5 wt percent) of NiO, the silicon compacts containing polymer char can be completely nitrided at 1200 C. The probable mechanism for the accelerated nitridation of silicon containing polymer char is discussed.

INSUL, Calculation of Thermal Insulation of Various Materials Immersed in He

International Nuclear Information System (INIS)

Kinkead, A.N.; Pitchford, B.E.

1977-01-01

1 - Nature of the physical problem solved: Performance of thermal insulation immersed in helium. 2 - Method of solution: Mineral fibre, metal fibre and metallic multi-layer foils are studied. An approximate analysis for performance evaluation of multi-layer insulation in vertical gas spaces including the regime between fully suppressed natural convection and that for which an accepted power relationship applies is included

Towards a fully integrated indium-phosphide membrane on silicon photonics platform

NARCIS (Netherlands)

van Engelen, J.P.; Pogoretskiy, V.; Smit, M.K.; van der Tol, J.J.G.M.; Jiao, Y.

2017-01-01

Recently a uni-traveling-carrier photodetector with high speed (> 67GHz) and a high-gain optical amplifier (110/cm at 4 kA/cm2) have been demonstrated using the InP membrane-on-Silicon (IMOS) integration technology. Passives in IMOS have shown features comparable to SOI platforms due to the tight

Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

2017-02-11

We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

A silicon pixel detector with routing for external VLSI read-out

International Nuclear Information System (INIS)

Thomas, S.L.; Seller, P.

1988-07-01

A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)

Modification of silicon nitride and silicon carbide surfaces for food and biosensor applications

NARCIS (Netherlands)

Rosso, M.

2009-01-01

Silicon-rich silicon nitride (SixN4, x > 3) is a robust insulating material widely used for the coating of microdevices: its high chemical and mechanical inertness make it a material of choice for the reinforcement of fragile microstructures (e.g. suspended microcantilevers, micro-fabricated

Hybrid Integrated Platforms for Silicon Photonics

Directory of Open Access Journals (Sweden)

John E. Bowers

2010-03-01

Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Stability of polarization in organic ferroelectric metal-insulator-semiconductor (MIS) structures

Energy Technology Data Exchange (ETDEWEB)

Kalbitz, Rene; Fruebing, Peter; Gerhard, Reimund [Department of Physics and Astronomy, University of Potsdam, Karl-Liebknecht-Strasse 24-25, 14476, Potsdam (Germany); Taylor, Martin [School of Electronic Engineering, Bangor University, Dean Street, Bangor Gwynedd, LL57 1UT (United Kingdom)

2011-07-01

Ferroelectric field effect transistors (FeFETs) offer the prospect of an organic-based memory device. Since the charge transport in such devices is confined to the interface between the insulator and the semiconductor, the focus of the present study was on the investigation of this region. Capacitance-voltage (C-V) measurements of all-organic MIS devices with poly(vinylidenefluoride- trifluoroethylene) (P(VDF-TrFE)) as gate insulator and poly(3-hexylthiophene)(P3HT) as semiconductor were carried out. When the structure was driven into depletion, a positive flat-band voltage shift was observed arising from the change in polarization state of the ferroelectric insulator. When driven into accumulation, the polarization was reversed. It is shown that both polarization states are stable. However, negative charge trapped at the interface during the depletion cycle masks the negative shift in flat-band voltage expected during the sweep to accumulation voltages. Measurements on P(VDF-TrFE)/P3HT based FeFETs yield further evidence for fixed charges at the interface. Output characteristics suggest the injection of negative charges into the interface region when a depletion voltage is applied between source and gate contact.

Imprinted silicon-based nanophotonics

DEFF Research Database (Denmark)

Borel, Peter Ingo; Olsen, Brian Bilenberg; Frandsen, Lars Hagedorn

2007-01-01

We demonstrate and optically characterize silicon-on-insulator based nanophotonic devices fabricated by nanoimprint lithography. In our demonstration, we have realized ordinary and topology-optimized photonic crystal waveguide structures. The topology-optimized structures require lateral pattern ...

Photonic crystal ring resonator-based four-channel dense wavelength division multiplexing demultiplexer on silicon on insulator platform: design and analysis

Science.gov (United States)

Sreenivasulu, Tupakula; Bhowmick, Kaustav; Samad, Shafeek A.; Yadunath, Thamerassery Illam R.; Badrinarayana, Tarimala; Hegde, Gopalkrishna; Srinivas, Talabattula

2018-04-01

A micro/nanofabrication feasible compact photonic crystal (PC) ring-resonator-based channel drop filter has been designed and analyzed for operation in C and L bands of communication window. The four-channel demultiplexer consists of ring resonators of holes in two-dimensional PC slab. The proposed assembly design of dense wavelength division multiplexing setup is shown to achieve optimal quality factor, without altering the lattice parameters or resonator size or inclusion of scattering holes. Transmission characteristics are analyzed using the three-dimensional finite-difference time-domain simulation approach. The radiation loss of the ring resonator was minimized by forced cancelation of radiation fields by fine-tuning the air holes inside the ring resonator. An average cross talk of -34 dB has been achieved between the adjacent channels maintaining an average quality factor of 5000. Demultiplexing is achieved by engineering only the air holes inside the ring, which makes it a simple and tolerant design from the fabrication perspective. Also, the device footprint of 500 μm2 on silicon on insulator platform makes it easy to fabricate the device using e-beam lithography technique.

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Friction, adhesion and wear properties of PDMS films on silicon sidewalls

International Nuclear Information System (INIS)

Penskiy, I; Gerratt, A P; Bergbreiter, S

2011-01-01

This paper demonstrates the first tests of friction, adhesion and wear properties of thin poly(dimethylsiloxane) (PDMS) films on the sidewalls of silicon-on-insulator structures. The test devices were individually calibrated using a simple method that included optical and electrical measurements. The static coefficient of friction versus normal pressure curves were obtained for PDMS–PDMS, PDMS–silicon and silicon–silicon sidewall interfaces. The effects of aging on friction and adhesion properties of PDMS were also evaluated. The results of friction tests showed that the static coefficient of friction follows the JKR contact model, which means that the friction force depends on the apparent area of contact. The wear tests showed high resistance of PDMS to abrasion over millions of cycles.

SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

International Nuclear Information System (INIS)

Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

1993-01-01

A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

LePix-A high resistivity, fully depleted monolithic pixel detector

CERN Document Server

Giubilato, P; Mugnier, H; Bisello, D; Marchioro, A; Snoeys, W; Denes, P; Pantano, D; Rousset, J; Mattiazzo, S; Kloukinas, K; Potenza, A; Rivetti, A; Chalmet, P

2013-01-01

The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 mu m to obtain back illuminated sensors operated in full depletion mode. By back processin...

Influence of the initial grain size of silicon on microstructure and mechanical properties of reaction-sintered silicon nitride

International Nuclear Information System (INIS)

Heinrich, J.

1977-01-01

The influence of the initial grain size of the silicon powder on the microstructure and the resulting mechanical properties are studied. The smaller the grain size of the silicon powders used, the higher will be the degree of reaction at the beginning of the nitridation reaction and the higher the amount of α-modification in the fully nitridated samples. Moreover, the nitrification time can be considerably shortened when fine-grained silicon powders ( [de

Wall insulation system

Energy Technology Data Exchange (ETDEWEB)

Kostek, P.T.

1987-08-11

In a channel specially designed to fasten semi-rigid mineral fibre insulation to masonry walls, it is known to be constructed from 20 gauge galvanized steel or other suitable material. The channel is designed to have pre-punched holes along its length for fastening of the channel to the drywall screw. The unique feature of the channel is the teeth running along its length which are pressed into the surface of the butted together sections of the insulation providing a strong grip between the two adjacent pieces of insulation. Of prime importance to the success of this system is the recent technological advancements of the mineral fibre itself which allow the teeth of the channel to engage the insulation fully and hold without mechanical support, rather than be repelled or pushed back by the inherent nature of the insulation material. After the insulation is secured to the masonry wall by concrete nail fastening systems, the drywall is screwed to the channel.

Fully CMOS-compatible titanium nitride nanoantennas

Energy Technology Data Exchange (ETDEWEB)

Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

2016-02-01

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

Effect of air on speed of insulating material deterioration under simulated LOCA environment. [Gamma radiation

Energy Technology Data Exchange (ETDEWEB)

Kusama, Yasuo; Yagi, Toshiaki; Ito, Masayuki; Okada, Sohei; Yoshikawa, Masato (Japan Atomic Energy Research Inst., Takasaki, Gunma. Takasaki Radiation Chemistry Research Establishment)

1982-12-01

To examine the quality approval testing method for the electric cables used for nuclear reactors, various covering insulating materials employed for the cables have been investigated from all angles. The factors which are considered to affect the deterioration of cable materials in a simulated LOCA (loss of coolant accident) environmental test are numerous. This paper reports on the result of investigation on the effect of air on the rate of deterioration of various organic materials usually used as the insulating and covering materials for the cables. Five kinds of polymer sheets (1 mm thick) used for reactor cables were employed as samples. The samples of both standard compounding ratio and the compounding ratio for practical reactor use were tested. As the deterioration prior to LOCA simulation, the thermal deterioration corresponding to 40 years aging (at 121 deg C for 7 days) was given, and subsequently, 50 Mrad gamma -irradiation at 1 Mrad/h was performed in the air. After that, the samples were subject to LOCA simulated environment. Since the results were different according to the kinds of samples, those are described separately for Hypalon, ethylene propylene rubber, cross-linked polyethylene, chloroprene and silicone rubber. The existence of air under LOCA environment accelerated the deterioration of insulation materials except silicone rubber, though its influence differed to the polymers. These materials swelled in the presence of air, and the degree of swelling increased with the temperature, having the close relation to oxidation deterioration. Polyethylene was more susceptible to the effect of air, and silicone rubber was rather stable. The samples of fire-retardant compounding ratio more swelled by water absorption than those of standard compounding ratio.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

Science.gov (United States)

Zhou, Hong; Maize, Kerry; Qiu, Gang; Shakouri, Ali; Ye, Peide D.

2017-08-01

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Method of forming buried oxide layers in silicon

Science.gov (United States)

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

Science.gov (United States)

Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

2016-03-01

In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

A Temperature-Hardened Sensor Interface with a 12-Bit Digital Output Using a Novel Pulse Width Modulation Technique

Directory of Open Access Journals (Sweden)

Emna Chabchoub

2018-04-01

Full Text Available A fully integrated sensor interface for a wide operational temperature range is presented. It translates the sensor signal into a pulse width modulated (PWM signal that is then converted into a 12-bit digital output. The sensor interface is based on a pair of injection locked oscillators used to implement a differential time-domain architecture with low sensitivity to temperature variations. A prototype has been fabricated using a 180 nm partially depleted silicon-on-insulator (SOI technology. Experimental results demonstrate a thermal stability as low as 65 ppm/°C over a large temperature range from −20 °C up to 220 °C.

Electrical insulator assembly with oxygen permeation barrier

Science.gov (United States)

Van Der Beck, Roland R.; Bond, James A.

1994-01-01

A high-voltage electrical insulator (21) for electrically insulating a thermoelectric module (17) in a spacecraft from a niobium-1% zirconium alloy wall (11) of a heat exchanger (13) filled with liquid lithium (16) while providing good thermal conductivity between the heat exchanger and the thermoelectric module. The insulator (21) has a single crystal alumina layer (SxAl.sub.2 O.sub.3, sapphire) with a niobium foil layer (32) bonded thereto on the surface of the alumina crystal (26) facing the heat exchanger wall (11), and a molybdenum layer (31) bonded to the niobium layer (32) to act as an oxygen permeation barrier to preclude the oxygen depleting effects of the lithium from causing undesirable niobium-aluminum intermetallic layers near the alumina-niobium interface.

SOI silicon on glass for optical MEMS

DEFF Research Database (Denmark)

Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

2003-01-01

and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

Crystalline silicon films sputtered on molybdenum A study of the silicon-molybdenum interface

Energy Technology Data Exchange (ETDEWEB)

Reinig, P.; Fenske, F.; Fuhs, W.; Schoepke, A.; Selle, B

2003-04-15

Polycrystalline silicon films were grown on molybdenum (Mo)-coated substrates at high deposition rate using the pulsed magnetron sputtering technique. Our study investigates the silicon-molybdenum interface of these films to elucidate stimulating mechanisms for an ordered crystalline silicon thin film growth. Both Auger electron spectroscopy and Rutherford backscattering reveal that at a substrate temperature as low as T{sub S}=450 deg. C during the deposition process intermixing of Si and Mo at the Si-Mo interface takes place leading to a compositional ratio Mo:Si of about 1:2. By Raman spectroscopy hexagonal {beta}-MoSi{sub 2} could be identified as the dominant phase in this intermixed region. The dependence of the resulting thickness of the reacted interface layer on the deposition conditions is not fully understood yet.

Crystalline silicon films sputtered on molybdenum A study of the silicon-molybdenum interface

International Nuclear Information System (INIS)

Reinig, P.; Fenske, F.; Fuhs, W.; Schoepke, A.; Selle, B.

2003-01-01

Polycrystalline silicon films were grown on molybdenum (Mo)-coated substrates at high deposition rate using the pulsed magnetron sputtering technique. Our study investigates the silicon-molybdenum interface of these films to elucidate stimulating mechanisms for an ordered crystalline silicon thin film growth. Both Auger electron spectroscopy and Rutherford backscattering reveal that at a substrate temperature as low as T S =450 deg. C during the deposition process intermixing of Si and Mo at the Si-Mo interface takes place leading to a compositional ratio Mo:Si of about 1:2. By Raman spectroscopy hexagonal β-MoSi 2 could be identified as the dominant phase in this intermixed region. The dependence of the resulting thickness of the reacted interface layer on the deposition conditions is not fully understood yet

110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

International Nuclear Information System (INIS)

Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Lai, Yin-Chieh; Yeh, Chien-Hung; Tsang, Hon-Ki

2016-01-01

We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism. (letter)

Etched ion tracks in silicon oxide and silicon oxynitride as charge injection or extraction channels for novel electronic structures

International Nuclear Information System (INIS)

Fink, D.; Petrov, A.V.; Hoppe, K.; Fahrner, W.R.; Papaleo, R.M.; Berdinsky, A.S.; Chandra, A.; Chemseddine, A.; Zrineh, A.; Biswas, A.; Faupel, F.; Chadderton, L.T.

2004-01-01

The impact of swift heavy ions onto silicon oxide and silicon oxynitride on silicon creates etchable tracks in these insulators. After their etching and filling-up with highly resistive matter, these nanometric pores can be used as charge extraction or injection paths towards the conducting channel in the underlying silicon. In this way, a novel family of electronic structures has been realized. The basic characteristics of these 'TEMPOS' (=tunable electronic material with pores in oxide on silicon) structures are summarized. Their functionality is determined by the type of insulator, the etch track diameters and lengths, their areal densities, the type of conducting matter embedded therein, and of course by the underlying semiconductor and the contact geometry. Depending on the TEMPOS preparation recipe and working point, the structures may resemble gatable resistors, condensors, diodes, transistors, photocells, or sensors, and they are therefore rather universally applicable in electronics. TEMPOS structures are often sensitive to temperature, light, humidity and organic gases. Also light-emitting TEMPOS structures have been produced. About 37 TEMPOS-based circuits such as thermosensors, photosensors, humidity and alcohol sensors, amplifiers, frequency multipliers, amplitude modulators, oscillators, flip-flops and many others have already been designed and successfully tested. Sometimes TEMPOS-based circuits are more compact than conventional electronics

A fully operational 1-kb variable threshold Josephson RAM

International Nuclear Information System (INIS)

Kurosawa, I.; Nakagawa, H.; Aoyagi, M.; Kosaks, S.; Takada, S.

1991-01-01

This paper describes the first fully operational Josephson RAM in LSI level integration. The chip was designed as a 4-b x 256-word data RAM unit for a 4-b Josephson computer, The variable threshold memory cell and the relating memory architecture were used. They are so simple in structure that the fabrication is satisfied by the current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip was fabricated with a 3-μm Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD silicon dioxide layer was introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer was improved during the oxidation process for making a tunnel barrier in this work

Fabrication of high quality GaAs-on-insulator via ion-cut of epitaxial GaAs/Ge heterostructure

Energy Technology Data Exchange (ETDEWEB)

Chang, Yongwei; Zhang, Miao [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Deng, Chuang; Men, Chuanling [School of Energy and Power Engineering, University of Shanghai for Science and Technology, Shanghai 200093 (China); Chen, Da [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); School of Physical Science and Technology, Lanzhou University, Lanzhou 730000 (China); Zhu, Lei; Yu, Wenjie; Wei, Xing [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Di, Zengfeng, E-mail: zfdi@mail.sim.ac.cn [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Wang, Xi [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China)

2015-08-15

Highlights: • GaAs-on-insulator has been achieved by integrating of epitaxy, ion-cut and selective chemical etching. • Superior to the direct ion-cut of bulk GaAs layer with the H implantation fluence 2.0 × 10{sup 17} cm{sup −2}, the fabrication of GaAs-on-insulator by the transfer of GaAs/Ge heterostructure only needs H implantation fluence as low as 0.8 × 10{sup 17} cm{sup −2}. • The crystalline quality of the top GaAs layer of the final GaAs-on-insulator wafer is not affected by the implantation process and comparable to the as-grown status. - Abstract: Due to the extraordinary electron mobility, III–V compounds are considered as the ideal candidate channel materials for future electronic devices. In this study, a novel approach for the fabrication of high-crystalline quality GaAs-on-insulator has been proposed by integrating of ion-cut and selective chemical etching. GaAs layer with good crystalline quality has been epitaxially grown on Ge by molecular beam epitaxy (MBE). With H implantation and wafer bonding process, the GaAs/Ge heterostructure is transferred onto silicon dioxide wafer after the proper thermal treatment. Superior to the direct ion-cut of GaAs layer, which requires the H implantation fluence as high as 2.0 × 10{sup 17} cm{sup −2}, the transfer of GaAs/Ge heterostructure in the present study only needs the implantation of 0.8 × 10{sup 17} cm{sup −2} H ions. GaAs-on-insulator structure was successfully achieved by the selective chemical etching of defective Ge layer using SF{sub 6} plasma. As the GaAs/Ge heterostructure can be easily epitaxy grown on silicon platform, the proposed approach for GaAs-on-insulator manufacturing is rather compatible with mature Si integrated circuits (ICs) technology and thus can be integrated to push the microelectronic technology to post-Si era.

Fabrication of high quality GaAs-on-insulator via ion-cut of epitaxial GaAs/Ge heterostructure

International Nuclear Information System (INIS)

Chang, Yongwei; Zhang, Miao; Deng, Chuang; Men, Chuanling; Chen, Da; Zhu, Lei; Yu, Wenjie; Wei, Xing; Di, Zengfeng; Wang, Xi

2015-01-01

Highlights: • GaAs-on-insulator has been achieved by integrating of epitaxy, ion-cut and selective chemical etching. • Superior to the direct ion-cut of bulk GaAs layer with the H implantation fluence 2.0 × 10 17 cm −2 , the fabrication of GaAs-on-insulator by the transfer of GaAs/Ge heterostructure only needs H implantation fluence as low as 0.8 × 10 17 cm −2 . • The crystalline quality of the top GaAs layer of the final GaAs-on-insulator wafer is not affected by the implantation process and comparable to the as-grown status. - Abstract: Due to the extraordinary electron mobility, III–V compounds are considered as the ideal candidate channel materials for future electronic devices. In this study, a novel approach for the fabrication of high-crystalline quality GaAs-on-insulator has been proposed by integrating of ion-cut and selective chemical etching. GaAs layer with good crystalline quality has been epitaxially grown on Ge by molecular beam epitaxy (MBE). With H implantation and wafer bonding process, the GaAs/Ge heterostructure is transferred onto silicon dioxide wafer after the proper thermal treatment. Superior to the direct ion-cut of GaAs layer, which requires the H implantation fluence as high as 2.0 × 10 17 cm −2 , the transfer of GaAs/Ge heterostructure in the present study only needs the implantation of 0.8 × 10 17 cm −2 H ions. GaAs-on-insulator structure was successfully achieved by the selective chemical etching of defective Ge layer using SF 6 plasma. As the GaAs/Ge heterostructure can be easily epitaxy grown on silicon platform, the proposed approach for GaAs-on-insulator manufacturing is rather compatible with mature Si integrated circuits (ICs) technology and thus can be integrated to push the microelectronic technology to post-Si era

DC breakdown characteristics of silicone polymer composites for HVDC insulator applications

Science.gov (United States)

Han, Byung-Jo; Seo, In-Jin; Seong, Jae-Kyu; Hwang, Young-Ho; Yang, Hai-Won

2015-11-01

Critical components for HVDC transmission systems are polymer insulators, which have stricter requirements that are more difficult to achieve compared to those of HVAC insulators. In this study, we investigated the optimal design of HVDC polymer insulators by using a DC electric field analysis and experiments. The physical properties of the polymer specimens were analyzed to develop an optimal HVDC polymer material, and four polymer specimens were prepared for DC breakdown experiments. Single and reverse polarity breakdown tests were conducted to analyze the effect of temperature on the breakdown strength of the polymer. In addition, electric fields were analyzed via simulations, in which a small-scale polymer insulator model was applied to prevent dielectric breakdown due to electric field concentration, with four DC operating conditions taken into consideration. The experimental results show that the electrical breakdown strength and the electric field distribution exhibit significant differences in relation to different DC polarity transition procedures.

Computer simulation for the formation of the insulator layer of silicon-on-insulator devices by N sup + and O sup + Co-implantation

CERN Document Server

Lin Qing; Xie Xin Yun; Lin Chenglu; Liu Xiang Hua

2002-01-01

A buried sandwiched layer consisting of silicon dioxide (upper part), silicon oxynitride (medium part) and silicon nitride (lower part) is formed by N sup + and O sup + co-implantation in silicon wafers at a constant temperature of 550 degree C. The microstructure is performed by cross-sectional transmission electron microscopy. To predict the quality of the buried sandwiched layer, the authors study the computer simulation for the formation of the SIMON (separated by implantation of oxygen and nitrogen) structure. The simulation program for SIMOX (separated by implantation of oxygen) is improved in order to be applied in O sup + and N sup + co-implantation on the basis of different formation mechanism between SIMOX and SIMNI (separated by implantation of nitrogen) structures. There is a good agreement between experiment and simulation results verifying the theoretical model and presumption in the program

Epitaxial Reactor Development for Growth of Silicon-on-Insulator Devices.

Science.gov (United States)

1987-04-01

emision from substrate reflected from interface 40 Constructive interference condition 2tc= n X / 1 * Destrictive interference condition 2tD= (2n+1) X...combinations of growth conditions resulted in no oxide growth on the original silicon wafer. Growths occurred for Si:O molecular ratios higher than 1:1...growth rates occurred at 1050 0 C with water vapor at 1250 cc/min and silane at 50 cc/min. These results are shown in Table 6. The molecular ratio was 2:1

LePix—A high resistivity, fully depleted monolithic pixel detector

International Nuclear Information System (INIS)

Giubilato, P.; Bisello, D.; Chalmet, P.; Denes, P.; Kloukinas, K.; Mattiazzo, S.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rivetti, A.; Rousset, J.; Snoeys, W.; Tindall, C.

2013-01-01

The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 μm to obtain back illuminated sensors operated in full depletion mode. By back-processing the chip and collecting the charge from the full substrate it is hence possible to efficiently detect soft X-rays up to 10 keV. Test results from first successfully processed detectors will be presented and discussed

Electronics and Sensor Study with the OKI SOI process

CERN Document Server

Arai, Yasuo

2007-01-01

While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

Laser direct writing of oxide structures on hydrogen-passivated silicon surfaces

DEFF Research Database (Denmark)

Müllenborn, Matthias; Birkelund, Karen; Grey, Francois

1996-01-01

on amorphous and crystalline silicon surfaces in order to determine the depassivation mechanism. The minimum linewidth achieved is about 450 nm using writing speeds of up to 100 mm/s. The process is fully compatible with local oxidation of silicon by scanning probe lithography. Wafer-scale patterns can...

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Additive advantage in characteristics of MIMCAPs on flexible silicon (100) fabric with release-first process

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show

Tunable complex-valued multi-tap microwave photonic filter based on single silicon-oninsulator microring resonator

DEFF Research Database (Denmark)

Lloret, Juan; Sancho, Juan; Pu, Minhao

2011-01-01

A complex-valued multi-tap tunable microwave photonic filter based on single silicon-on-insulator microring resonator is presented. The degree of tunability of the approach involving two, three and four taps is theoretical and experimentally characterized, respectively. The constraints of exploit...

Methods To Determine the Silicone Oil Layer Thickness in Sprayed-On Siliconized Syringes.

Science.gov (United States)

Loosli, Viviane; Germershaus, Oliver; Steinberg, Henrik; Dreher, Sascha; Grauschopf, Ulla; Funke, Stefanie

2018-01-01

The silicone lubricant layer in prefilled syringes has been investigated with regards to siliconization process performance, prefilled syringe functionality, and drug product attributes, such as subvisible particle levels, in several studies in the past. However, adequate methods to characterize the silicone oil layer thickness and distribution are limited, and systematic evaluation is missing. In this study, white light interferometry was evaluated to close this gap in method understanding. White light interferometry demonstrated a good accuracy of 93-99% for MgF 2 coated, curved standards covering a thickness range of 115-473 nm. Thickness measurements for sprayed-on siliconized prefilled syringes with different representative silicone oil distribution patterns (homogeneous, pronounced siliconization at flange or needle side, respectively) showed high instrument (0.5%) and analyst precision (4.1%). Different white light interferometry instrument parameters (autofocus, protective shield, syringe barrel dimensions input, type of non-siliconized syringe used as base reference) had no significant impact on the measured average layer thickness. The obtained values from white light interferometry applying a fully developed method (12 radial lines, 50 mm measurement distance, 50 measurements points) were in agreement with orthogonal results from combined white and laser interferometry and 3D-laser scanning microscopy. The investigated syringe batches (lot A and B) exhibited comparable longitudinal silicone oil layer thicknesses ranging from 170-190 nm to 90-100 nm from flange to tip and homogeneously distributed silicone layers over the syringe barrel circumference (110- 135 nm). Empty break-loose (4-4.5 N) and gliding forces (2-2.5 N) were comparably low for both analyzed syringe lots. A silicone oil layer thickness of 100-200 nm was thus sufficient for adequate functionality in this particular study. Filling the syringe with a surrogate solution including short

Performance of 3-D architecture silicon sensors after intense proton irradiation

CERN Document Server

Parker, S I

2001-01-01

Silicon detectors with a three-dimensional architecture, in which the n- and p-electrodes penetrate through the entire substrate, have been successfully fabricated. The electrodes can be separated from each other by distances that are less than the substrate thickness, allowing short collection paths, low depletion voltages, and large current signals from rapid charge collection. While no special hardening steps were taken in this initial fabrication run, these features of three dimensional architectures produce an intrinsic resistance to the effects of radiation damage. Some performance measurements are given for detectors that are fully depleted and working after exposures to proton beams with doses equivalent to that from slightly more than ten years at the B-layer radius (50 mm) in the planned Atlas detector at the Large Hadron Collider at CERN. (41 refs).

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

Energy Technology Data Exchange (ETDEWEB)

Tietun Sun; Jianmin Miao; Rongming Lin; Yongqing Fu [Nanyang Technological Univ., Micromachines Lab., Singapore (Singapore)

2005-01-01

In this paper, Ag-based paste was screen-printed on polished as well as on textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400 deg C for 5 min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate. (Author)

The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

Energy Technology Data Exchange (ETDEWEB)

Sun, Tietun; Miao, Jianmin; Lin, Rongming; Fu, Yongqing [Micromachines Laboratory, School of Mechanical and Production Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2005-01-01

In this paper, Ag-based paste was screen-printed on the polished as well as on the textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400{sup o}C for 5min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate.

Threshold stoichiometry for beam induced nitrogen depletion of SiN

International Nuclear Information System (INIS)

Timmers, H.; Weijers, T.D.M.; Elliman, R.G.; Uribasterra, J.; Whitlow, H.J.; Sarwe, E.-L.

2002-01-01

Measurements of the stoichiometry of silicon nitride films as a function of the number of incident ions using heavy ion elastic recoil detection (ERD) show that beam-induced nitrogen depletion depends on the projectile species, the beam energy, and the initial stoichiometry. A threshold stoichiometry exists in the range 1.3>N/Si≥1, below which the films are stable against nitrogen depletion. Above this threshold, depletion is essentially linear with incident fluence. The depletion rate correlates non-linearly with the electronic energy loss of the projectile ion in the film. Sufficiently long exposure of nitrogen-rich films renders the mechanism, which prevents depletion of nitrogen-poor films, ineffective. Compromising depth-resolution, nitrogen depletion from SiN films during ERD analysis can be reduced significantly by using projectile beams with low atomic numbers

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

International Nuclear Information System (INIS)

Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

2009-01-01

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

Effect on the insulation material of a MOSFET device submitted to a standard diagnostic radiation beam

International Nuclear Information System (INIS)

De Magalhaes, C M S; Dos Santos, L A P; Souza, D do N; Maia, A F

2010-01-01

MOSFET electronic devices have been used for dosimetry in radiology and radiotherapy. Several communications show that due to the radiation exposure defects appear on the semiconductor crystal lattice. Actually, the structure of a MOSFET consists of three materials: a semiconductor, a metal and an insulator between them. The MOSFET is a quadripolar device with a common terminal: gate-source is the input; drain-source is the output. The gate controls the electrical current passing through semiconductor medium by the field effect because the silicon oxide acts as insulating material. The proposal of this work is to show some radiation effects on the insulator of a MOSFET device. A 6430 Keithley sub-femtoamp SourceMeter was used to verify how the insulating material layer in the structure of the device varies with the radiation exposure. We have used the IEC 61267 standard radiation X-ray beams generated from a Pantak industrial unit in the radiation energy range of computed tomography. This range was chosen because we are using the MOSFET device as radiation detector for dosimetry in computed tomography. The results showed that the behaviour of the electrical current of the device is different in the insulator and semiconductor structures.

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

Science.gov (United States)

Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

2017-06-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

International Nuclear Information System (INIS)

Pernegger, H.; Hoorne, J.W. van; Kugathasan, T.; Musa, L.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E.J.; Snoeys, W.; Bates, R.; Buttar, C.; Maneuski, D.; Dalla, M.; Sbarra, C.

2017-01-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 10"1"5 n _e_q/cm"2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

Silicon Photonic Waveguides for Near- and Mid-Infrared Regions

Science.gov (United States)

Stankovic, S.; Milosevic, M.; Timotijevic, B.; Yang, P. Y.; Teo, E. J.; Crnjanski, J.; Matavulj, P.; Mashanovich, G. Z.

2007-11-01

The basic building block of every photonic circuit is a waveguide. In this paper we investigate the most popular silicon waveguide structures in the form of a silicon-on-insulator rib waveguide. We also analyse two structures that can find applications in mid- and long-wave infrared regions: free-standing and hollow core omnidirectional waveguides.

High Power Broadband Multispectral Source on a Hybrid Silicon Chip

Science.gov (United States)

2017-03-14

optical bandwidth of the erbium-doped- fiber -amplifier with densely-spaced frequency channels. To extend the spectral capacity of the Si-on-insulator...associated with non-uniform undercut at the taper tip across the chip after wet etching the active region. Figure 14. Normalized optical emission...Hutchinson, J., Shin, J.-H., Fish, G., and Fang, A., “Integrated silicon photonic laser sources for telecom and datacom,” in [National Fiber Optic

Transfer-free electrical insulation of epitaxial graphene from its metal substrate.

Science.gov (United States)

Lizzit, Silvano; Larciprete, Rosanna; Lacovig, Paolo; Dalmiglio, Matteo; Orlando, Fabrizio; Baraldi, Alessandro; Gammelgaard, Lauge; Barreto, Lucas; Bianchi, Marco; Perkins, Edward; Hofmann, Philip

2012-09-12

High-quality, large-area epitaxial graphene can be grown on metal surfaces, but its transport properties cannot be exploited because the electrical conduction is dominated by the substrate. Here we insulate epitaxial graphene on Ru(0001) by a stepwise intercalation of silicon and oxygen, and the eventual formation of a SiO(2) layer between the graphene and the metal. We follow the reaction steps by X-ray photoemission spectroscopy and demonstrate the electrical insulation using a nanoscale multipoint probe technique.

Transfer-Free Electrical Insulation of Epitaxial Graphene from its Metal Substrate

DEFF Research Database (Denmark)

Lizzit, Silvano; Larciprete, Rosanna; Lacovig, Paolo

2012-01-01

High-quality, large-area epitaxial graphene can be grown on metal surfaces, but its transport properties cannot be exploited because the electrical conduction is dominated by the substrate. Here we insulate epitaxial graphene on Ru(0001) by a stepwise intercalation of silicon and oxygen......, and the eventual formation of a SiO2 layer between the graphene and the metal. We follow the reaction steps by X-ray photoemission spectroscopy and demonstrate the electrical insulation using a nanoscale multipoint probe technique....

Persistent depletion of plasma gelsolin (pGSN) after exposure of mice to heavy silicon ions

Science.gov (United States)

Rithidech, Kanokporn Noy; Reungpatthanaphong, Paiboon; Tungjai, Montree; Jangiam, Witawat; Honikel, Louise; Whorton, Elbert B.

2018-05-01

Little is known about plasma proteins that can be used as biomarkers for early and late responses to radiation. The purpose of this study was to determine a link between depletion of plasma gelsolin (pGSN) and cell-death as well as inflammatory responses in the lung (one of the tissues known to be radiosensitive) of the same exposed CBA/CaJ mice after exposure to heavy silicon (28Si) ions. To prevent the development of multiple organ dysfunctions, pGSN (an important component of the extracellular actin-scavenging system) is responsible for the removal of actin that is released into the circulation during inflammation and from dying cells. We evaluated the levels of pGSN in plasma collected from groups of mice (5 mice in each) at 1 week (wk) and 1 month (1 mo) after exposure whole body to different doses of 28Si ions, i.e. 0, 0.1, 0.25, or 0.5 Gy (2 fractionated exposures, 15 days apart that totaled each selected dose). In the same mouse, the measurements of pGSN levels were coupled with the quantitation of injuries in the lung, determined by (a) the levels of cleaved poly (ADP-ribose) polymerase (cleaved-PARP), a marker of apoptotic cell-death, (b) the levels of activated nuclear factor-kappa B (NF-κB) and selected cytokines, i.e. tumor necrosis factor-alpha (TNF-α), interleukin-1 beta (IL-1β), and IL-6, from tissue-lysates of the lung. Further, the ratio of neutrophils and lymphocytes (N/L) was determined in the same mouse. Our data indicated: (i) the magnitude of pGSN depletion was dependent to radiation dose at both harvest times, (ii) a persistent depletion of pGSN up to 1 mo post-exposure to 0.25 or 0.5 Gy of 28Si ions, (iii) an inverse-correlation between pGSN depletion and increased levels of cleaved-PARP, including activated NF-κB/pro-inflammatory cytokines in the lung, and (iv) at both harvest times, statistically significant increases in the N/L ratio in groups of mice exposed to 0.5 Gy only. Our findings suggested that depletion in pGSN levels

Optoelectronic Device Integration in Silicon (OpSIS)

Science.gov (United States)

2015-10-26

silicon-on-insulator," Opt. Express 22, 17872-17879 (2014) Y. Yang, C. Galland, Y. Liu, K. Tan , R. Ding, Q. Li, K. Bergman, T. Baehr-Jones, M...Jaeger, Nicolas AF; Chrostowski, Lukas; “Electrically tunable resonant filters in phase-shifted contra- directional couplers” IEEE Group IV Photonics... Nicolas AF; Chrostowski, Lukas; “Silicon photonic grating-assisted, contra-directional couplers” Optics express Vol. 21, No. 3; 3633-3650 (2013

Bionics in textiles: flexible and translucent thermal insulations for solar thermal applications.

Science.gov (United States)

Stegmaier, Thomas; Linke, Michael; Planck, Heinrich

2009-05-13

Solar thermal collectors used at present consist of rigid and heavy materials, which are the reasons for their immobility. Based on the solar function of polar bear fur and skin, new collector systems are in development, which are flexible and mobile. The developed transparent heat insulation material consists of a spacer textile based on translucent polymer fibres coated with transparent silicone rubber. For incident light of the visible spectrum the system is translucent, but impermeable for ultraviolet radiation. Owing to its structure it shows a reduced heat loss by convection. Heat loss by the emission of long-wave radiation can be prevented by a suitable low-emission coating. Suitable treatment of the silicone surface protects it against soiling. In combination with further insulation materials and flow systems, complete flexible solar collector systems are in development.

Silicon photonics III systems and applications

CERN Document Server

Lockwood, David

2016-01-01

This book is volume III of a series of books on silicon photonics. It reports on the development of fully integrated systems where many different photonics component are integrated together to build complex circuits. This is the demonstration of the fully potentiality of silicon photonics. It contains a number of chapters written by engineers and scientists of the main companies, research centers and universities active in the field. It can be of use for all those persons interested to know the potentialities and the recent applications of silicon photonics both in microelectronics, telecommunication and consumer electronics market.

Enhanced light emission in photonic crystal nanocavities with Erbium-doped silicon nanocrystals

International Nuclear Information System (INIS)

Makarova, Maria; Sih, Vanessa; Vuckovic, Jelena; Warga, Joe; Li Rui; Dal Negro, Luca

2008-01-01

Photonic crystal nanocavities are fabricated in silicon membranes covered by thermally annealed silicon-rich nitride films with Erbium-doped silicon nanocrystals. Silicon nitride films were deposited by sputtering on top of silicon on insulator wafers. The nanocavities were carefully designed in order to enhance emission from the nanocrystal sensitized Erbium at the 1540 nm wavelength. Experimentally measured quality factors of ∼6000 were found to be consistent theoretical predictions. The Purcell factor of 1.4 was estimated from the observed 20-fold enhancement of Erbium luminescence

Six-beam homodyne laser Doppler vibrometry based on silicon photonics technology.

Science.gov (United States)

Li, Yanlu; Zhu, Jinghao; Duperron, Matthieu; O'Brien, Peter; Schüler, Ralf; Aasmul, Soren; de Melis, Mirko; Kersemans, Mathias; Baets, Roel

2018-02-05

This paper describes an integrated six-beam homodyne laser Doppler vibrometry (LDV) system based on a silicon-on-insulator (SOI) full platform technology, with on-chip photo-diodes and phase modulators. Electronics and optics are also implemented around the integrated photonic circuit (PIC) to enable a simultaneous six-beam measurement. Measurement of a propagating guided elastic wave in an aluminum plate (speed ≈ 909 m/s @ 61.5 kHz) is demonstrated.

Influence of additional heat exchanger block on directional solidification system for growing multi-crystalline silicon ingot - A simulation investigation

Science.gov (United States)

Nagarajan, S. G.; Srinivasan, M.; Aravinth, K.; Ramasamy, P.

2018-04-01

Transient simulation has been carried out for analyzing the heat transfer properties of Directional Solidification (DS) furnace. The simulation results revealed that the additional heat exchanger block under the bottom insulation on the DS furnace has enhanced the control of solidification of the silicon melt. Controlled Heat extraction rate during the solidification of silicon melt is requisite for growing good quality ingots which has been achieved by the additional heat exchanger block. As an additional heat exchanger block, the water circulating plate has been placed under the bottom insulation. The heat flux analysis of DS system and the temperature distribution studies of grown ingot confirm that the established additional heat exchanger block on the DS system gives additional benefit to the mc-Si ingot.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2014-12-01

Today\\'s mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Kutbee, Arwa T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Today's mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

International Nuclear Information System (INIS)

Li Lei; Zhou Wanting; Liu Huihua

2012-01-01

In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

Undepleted silicon detectors

International Nuclear Information System (INIS)

Rancoita, P.G.; Seidman, A.

1985-01-01

Large-size silicon detectors employing relatively low resistivity material can be used in electromagnetic calorimetry. They can operate in strong magnetic fields, under geometric constraints and with microstrip detectors a high resolution can be achieved. Low noise large capacitance oriented electronics was developed to enable good signal-to-noise ratio for single relativistic particles traversing large area detectors. In undepleted silicon detectors, the charge migration from the field-free region has been investigated by comparing the expected peak position (from the depleted layer only) of the energy-loss of relativistic electrons with the measured one. Furthermore, the undepleted detectors have been employed in a prototype of Si/W electromagnetic colorimeter. The sensitive layer was found to be systematically larger than the depleted one

Channel-Selectable Optical Link Based on a Silicon Microring for on-Chip Interconnection

International Nuclear Information System (INIS)

Qiu Chen; Hu Ting; Wang Wan-Jun; Yu Ping; Jiang Xiao-Qing; Yang Jian-Yi

2012-01-01

A channel-selectable optical link based on a silicon microring resonator is proposed and demonstrated. This optical link consists of the wavelength-tunable microring modulators and the filters, defined on a silicon-on-insulator (SOI) platform. With a p—i—n junction embedded in the microring modulator, light at the resonant wavelength of the ring resonator is modulated. The 2 nd -order microring add-drop filter routes the modulated light. The channel selectivity is demonstrated by heating the microrings. With a thermal tuning efficiency of 5.9 mW/nm, the filter drop port response was successfully tuned with 0.8 nm channel spacing. We also show that modulation can be achieved in these channels. This device aims to offer flexibility and increase the bandwidth usage efficiency in optical interconnection

Arc damage characteristics of inter-anode insulators in MHD generator

International Nuclear Information System (INIS)

Kato, Ken; Takano, Kiyonami

1990-01-01

The inter-anode arc caused by a Hall field is driven by a magnetic field into the anode-wall in an MHD generator, which limits the lifetime and performance of the generator. The arc damage to inter-anode insulators of an MHD generator has been studied experimentally, in order to obtain basic data for the design of the inter-anode insulation. The experiment was conducted using a pair of electrodes with an insulator between them. Arc currents was supplied from a DC power source and magnetic field was applied perpendicular to the arc current. Experimental parameters are the insulator thickness, arc current, magnetic field and insulator materials. Quartz glass, boron nitride, magnesia, alumina, silicon carbide, silicon nitride etc. were tested and evaluated. The following conclusions are evident from the experiments. Boron nitride and quartz glass are the most promising inter-anode insulators. Boron nitride has a higher arc voltage and longer cutting time than quartz glass, and it is the best material. Cutting time is approximately proportional to the -0.4 th power of the magnetic field. Loss of insulator is approximately proportional to the 0.7 th power of the arc current. The arc voltage increases linearly with the inter anode gap length. It also increases with magnetic field, but decreases with increase of arc current. An equation which approximates to such relations of arc voltage versus inter-anode gap length, arc current and magnetic field has been obtained. The standard deviation of the error of this equation is 12 % for boron nitride and 15 % for quartz glass. (author)

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

International Nuclear Information System (INIS)

Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

2014-01-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

Science.gov (United States)

Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

2014-12-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

Radiation hardness of silicon detectors manufactured on wafers from various sources

International Nuclear Information System (INIS)

Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

1997-01-01

Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

On the stability of silicon field effect capacitors with phosphate buffered saline electrolytic gate and self assembled monolayer gate insulator

International Nuclear Information System (INIS)

Hemed, Nofar Mintz; Inberg, Alexandra; Shacham-Diamand, Yosi

2013-01-01

We herein report on the stability of Electrolyte/Insulator/Semiconductor (EIS) devices with Self-Assembled Monolayer (SAM) gate insulator layers, i.e. Electrolyte/SAM/Semiconductor (ESS) devices. ESS devices can be functionalized creating highly specific sensors that can be integrated on standard silicon platform. However, biosensors by their nature are in contact with biological solutions that contain ions and molecules that may affect the device characteristics and cause electrical instability. In this paper we present a list of potential hazards to ESS devices and a study of the device stability under common testing conditions analyzing possible causes for the instabilities. ESS capacitors under open circuit conditions (i.e. open circuit bias of ∼0.6 V vs. Ag/AgCl reference electrode) were periodically characterized. We measured the complex impedance of the capacitors versus bias and extracted the effective capacitance vs. voltage (C–V) curves using two methods. We observed a parallel shift of the C–V curves toward negative bias; showing an effective accumulation of positive charge. The quantitative analysis of the drift vs. time was found to depend on the effective capacitance evaluation method. This effect is discussed and a best-known method is proposed. The devices surface composition was tested before and after the stress experiment by X-ray Photoelectron Spectroscopy (XPS) and sodium accumulation was observed. To further explore the flat-band voltage drift effect and to challenge the assumption that alkali ions are involved in the drift we conceived a novel alkali-free phosphate buffer saline (AF-PBS) where the sodium and potassium ions are replaced by ammonium ion and tested the capacitor under similar conditions to standard PBS. We found that the drift of the AF-PBS solution was much less at the first hour but was similar to that of the conventional PBS for longer stress times; hence, AF-PBS does not solve the long-term instability problem

A silicon-based electrical source for surface plasmon polaritons

NARCIS (Netherlands)

Walters, Robert J.; van Loon, Rob V.A.; Brunets, I.; Schmitz, Jurriaan; Polman, Albert

2009-01-01

This work demonstrates the fabrication of a silicon-based electrical source for surface plasmon polaritons (SPPs) at low temperatures using silicon nanocrystal doped alumina within a metal-insulator-metal (MIM) waveguide geometry. The fabrication method uses established microtechnology processes

Silicon based light emitter utilizing tunnel injection of excess carriers via MIS structure

Energy Technology Data Exchange (ETDEWEB)

Arguirov, Tzanimir; Kittler, Martin [IHP - Innovations for High Performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder) (Germany); IHP/BTU Joint Lab BTU Cottbus, Konrad-Wachsmann-Allee 1, 03013 Cottbus (Germany); Wenger, Christian; Lukosius, Mindaugas [IHP - Innovations for High Performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder) (Germany); Mchedlidze, Teimuraz [IHP/BTU Joint Lab BTU Cottbus, Konrad-Wachsmann-Allee 1, 03013 Cottbus (Germany); Reiche, Manfred [Max-Planck-Institut fuer Mikrostrukturphysik, Weinberg 2, 06120 Halle (Germany)

2011-04-15

We report on electro-luminescence from metal-insulator-semiconductor diodes (MISLED). MISLEDs prepared on silicon with HfO2 layers of different thicknesses were investigated and their properties compared with such prepared by using SiO2 insulator layer. The role of the insulator layer was studied in view of the efficiency of the band-to-band radiation from silicon. We show that the luminescence efficiency depends on the dielectric constant of the insulator as well as on its ability to conduct carriers by tunnelling. Efficiency enhancement of 3.3 times was detected when the SiO{sub 2} insulator was substituted by HfO{sub 2} in the MIS emitter. Optimal injection current exists, which leads to a maximal efficiency of the luminescence. The optimal current depends strongly on the thickness of the oxide. We relate the existence of an optimal current with the depth at which the injected minority carriers recombine radiatively. Thus the electric field in the semiconductor and the surface recombination are the factors determining the optimal injection (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

Science.gov (United States)

Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2018-06-01

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

Additive advantage in characteristics of MIMCAPs on flexible silicon (100) fabric with release-first process

KAUST Repository

Ghoneim, Mohamed T.

2013-11-20

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show that our approach to transform bulk silicon (100) into a flexible fabric adds an inherent advantage of enabling higher integration density dynamic random access memory (DRAM) on the same chip area. Our approach is to release an ultra-thin silicon (100) fabric (25 μm thick) from the bulk silicon wafer, then build MIMCAPs using sputtered aluminium electrodes and successive atomic layer depositions (ALD) without break-ing the vacuum of a high-κ aluminium oxide sandwiched between two tantalum nitride layers. This result shows that we can obtain flexible electronics on silicon without sacrificing the high density integration aspects and also utilize the non-planar geometry associated with fabrication process to obtain a higher integration density compared to bulk silicon integration due to an increased normalized capacitance per unit planar area. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Pr-O-Al-N dielectrics for metal insulator semiconductor stacks

Energy Technology Data Exchange (ETDEWEB)

Henkel, Karsten; Torche, Mohamed; Sohal, Rakesh; Karavaev, Konstantin; Burkov, Yevgen; Schwiertz, Carola; Schmeisser, Dieter [Brandenburg University of Technology, Chair of Applied Physics and Sensors, K.-Wachsmann-Allee 1, 03046 Cottbus (Germany)

2011-02-15

This work focuses on praseodymium oxide films as a high-k material on silicon and silicon carbide (SiC) in metal insulator semiconductor samples. The electrical results are correlated to spectroscopic findings on this material system. Strong interfacial reactions between the praseodymium oxide and the semiconductor as well as silicon inter-diffusion into the high-k material are observed. The importance of a buffer layer is discussed and its optimisation is addressed, too. In particular the improvement of the performance by the introduction of an aluminium oxynitride buffer layer, which acts as an inter-diffusion barrier and reduces the leakage current, the interface state density and the equivalent oxide thickness is demonstrated. (Copyright copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Two-dimensional optical phased array antenna on silicon-on-insulator.

Science.gov (United States)

Van Acoleyen, Karel; Rogier, Hendrik; Baets, Roel

2010-06-21

Optical wireless links can offer a very large bandwidth and can act as a complementary technology to radiofrequency links. Optical components nowadays are however rather bulky. Therefore, we have investigated the potential of silicon photonics to fabricated integrated components for wireless optical communication. This paper presents a two-dimensional phased array antenna consisting of grating couplers that couple light off-chip. Wavelength steering of $0.24 degrees /nm is presented reducing the need of active phase modulators. The needed steering range is $1.5 degrees . The 3dB angular coverage range of these antennas is about $0.007pi sr with a directivity of more than 38dBi and antenna losses smaller than 3dB.

Study of the effects of neutron irradiation on silicon strip detectors

International Nuclear Information System (INIS)

Giubellino, P.; Panizza, G.; Hall, G.; Sotthibandhu, S.; Ziock, H.J.; Ferguson, P.; Sommer, W.F.; Edwards, M.; Cartiglia, N.; Hubbard, B.; Leslie, J.; Pitzl, D.; O'Shaughnessy, K.; Rowe, W.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E.

1992-01-01

Silicon strip detectors and test structures were exposed to neutron fluences up to Φ=6.1x10 14 n/cm 2 , using the ISIS neutron source at the Rutherford Appleton Laboratory (UK). In this paper we report some of our results concerning the effects of displacement damage, with a comparison of devices made of silicon of different resistivity. The various samples exposed showed a very similar dependence of the leakage current on the fluence received. We studied the change of effective doping concentration, and observed a behaviour suggesting the onset of type inversion at a fluence of ∝2.0x10 13 n/cm 2 , a value which depends on the initial doping concentration. The linear increase of the depletion voltage for fluences higher than the inversion point could eventually determine the maximum fluence tolerable by silicon detectors. (orig.)

Microscopic models of impurities in silicon

International Nuclear Information System (INIS)

Assali, L.V.C.

1985-01-01

The study of electronic structure of insulated and complex puntual impurities in silicon responsible by the appearing of deep energy levels in the forbiden band of semiconductor, is presented. The molecular cluster model with the treatment of surface orbitals by Watson sphere within the formalism of Xα multiple scattering method, was used. The electronic structures of three clusters representative of perfect silicon crystal, which were used for the impurity studies, are presented. The method was applied to analyse insulated impurities of substitutional and interstitial hydrogen (Si:H and Si:H i ), subtitutional and interstitial iron in neutral and positive charge states (Si:Fe 0 , + , Si:Fe 0 , + ) and substitutional gold in three charge states(Si,Au - , 0 , + ). The thetraedic interstitial defect of silicon (Si:Si i ) was also studied. The complex impurities: neighbour iron pair in the lattice (Si:Fe 2 ), substitutional gold-interstitial iron pair (Si:Au s Fe) and substitutional boron-interstitial hydrogen pair (Si:B s H i ), were analysed. (M.C.K.) [pt

Explicit analytical modeling of the low frequency a-Si:H/c-Si heterojunction capacitance: Analysis and application to silicon heterojunction solar cells

Energy Technology Data Exchange (ETDEWEB)

Maslova, O. [Keldysh Institute of Applied Mathematics, Russian Academy of Sciences, Miusskaya sq., 4, Moscow 125047 (Russian Federation); GeePs (Group of electrical engineering of Paris), CNRS UMR 8507, CentraleSupélec, Univ Paris-Sud, Sorbonne Universités-UPMC Univ Paris 06, 11 rue Joliot-Curie, Plateau de Moulon, F-91192 Gif-sur-Yvette Cedex (France); Brézard-Oudot, A.; Gueunier-Farret, M.-E.; Alvarez, J.; Kleider, J.-P. [GeePs (Group of electrical engineering of Paris), CNRS UMR 8507, CentraleSupélec, Univ Paris-Sud, Sorbonne Universités-UPMC Univ Paris 06, 11 rue Joliot-Curie, Plateau de Moulon, F-91192 Gif-sur-Yvette Cedex (France)

2015-09-21

We develop a fully analytical model in order to describe the temperature dependence of the low frequency capacitance of heterojunctions between hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si). We demonstrate that the slope of the capacitance-temperature (C-T) curve is strongly enhanced if the c-Si surface is under strong inversion conditions compared to the usually assumed depletion layer capacitance. We have extended our analytical model to integrate a very thin undoped (i) a-Si:H layer at the interface and the finite thickness of the doped a-Si:H layer that are used in high efficiency solar cells for the passivation of interface defects and to limit short circuit current losses. Finally, using our calculations, we analyze experimental data on high efficiency silicon heterojunction solar cells. The transition from the strong inversion limited behavior to the depletion layer behavior is discussed in terms of band offsets, density of states in a-Si:H, and work function of the indium tin oxide (ITO) front electrode. In particular, it is evidenced that strong inversion conditions prevail at the c-Si surface at high temperatures down to 250 K, which can only be reproduced if the ITO work function is larger than 4.7 eV.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

Energy Technology Data Exchange (ETDEWEB)

Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

2016-07-11

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

Science.gov (United States)

Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

2016-07-01

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

Gain compensation technique by bias correction in arrays of Silicon Photomultipliers using fully differential fast shaper

International Nuclear Information System (INIS)

Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

2016-01-01

Proposed algorithm compensates the gain by changing the bias voltage of Silicon Photomultipliers (SiPM). The signal from SiPM is amplified in fully differential preamplifier then is formed in time by the fully differential fast shaper. The compensation method was tested with four channels common cathode multi-pixel photon counter from Hamamatsu. The measurement system requires only one high voltage power supply. The polarization voltage is adjusted individually in each channel indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The changes of VOCM affect the input voltage through the feedback network. Actual gain of the SiPM is calculated by measuring the mean amplitude of the signal resulting from detection of single photoelectron. The VOCM is adjusted by DAC so as to reach the desired value of gain by each channel individually. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in very similar conditions (have similar gain and dark count rate). The algorithm can compensate the variations of gain of SiPM by using thermally generated pulses. There is no need to use additional current to voltage conversion which could introduce extra noises.

Multifunctional epitaxial systems on silicon substrates

Energy Technology Data Exchange (ETDEWEB)

Singamaneni, Srinivasa Rao, E-mail: ssingam@ncsu.edu [Department of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Materials Science Division, Army Research Office, Research Triangle Park, North Carolina 27709 (United States); Department of Physics, The University of Texas at El Paso, El Paso, Texas 79968 (United States); Prater, John Thomas [Department of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States); Materials Science Division, Army Research Office, Research Triangle Park, North Carolina 27709 (United States); Narayan, Jagdish [Department of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina 27695 (United States)

2016-09-15

Multifunctional heterostructures can exhibit a wide range of functional properties, including colossal magneto-resistance, magnetocaloric, and multiferroic behavior, and can display interesting physical phenomena including spin and charge ordering and strong spin-orbit coupling. However, putting this functionality to work remains a challenge. To date, most of the work reported in the literature has dealt with heterostructures deposited onto closely lattice matched insulating substrates such as DyScO{sub 3}, SrTiO{sub 3} (STO), or STO buffered Si(100) using concepts of lattice matching epitaxy (LME). However, strain in heterostructures grown by LME is typically not fully relaxed and the layers contain detrimental defects such as threading dislocations that can significantly degrade the physical properties of the films and adversely affect the device characteristics. In addition, most of the substrates are incompatible with existing CMOS-based technology, where Si (100) substrates dominate. This review discusses recent advances in the integration of multifunctional oxide and non-oxide materials onto silicon substrates. An alternative thin film growth approach, called “domain matching epitaxy,” is presented which identifies approaches for minimizing lattice strain and unwanted defects in large misfit systems (7%–25% and higher). This approach broadly allows for the integration of multifunctional materials onto silicon substrates, such that sensing, computation, and response functions can be combined to produce next generation “smart” devices. In general, pulsed laser deposition has been used to epitaxially grow these materials, although the concepts developed here can be extended to other deposition techniques, as well. It will be shown that TiN and yttria-stabilized zirconia template layers provide promising platforms for the integration of new functionality into silicon-based computer chips. This review paper reports on a number of thin

Thin-barrier enhancement-mode AlGaN/GaN MIS-HEMT using ALD Al2O3 as gate insulator

International Nuclear Information System (INIS)

Wang Zheli; Zhou Jianjun; Kong Yuechan; Kong Cen; Dong Xun; Yang Yang; Chen Tangsheng

2015-01-01

A high-performance enhancement-mode (E-mode) gallium nitride (GaN)-based metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) that employs a 5-nm-thick aluminum gallium nitride (Al 0.3 Ga 0.7 N) as a barrier layer and relies on silicon nitride (SiN) passivation to control the 2DEG density is presented. Unlike the SiN passivation, aluminum oxide (Al 2 O 3 ) by atomic layer deposition (ALD) on AlGaN surface would not increase the 2DEG density in the heterointerface. ALD Al 2 O 3 was used as gate insulator after the depletion by etching of the SiN in the gate region. The E-mode MIS-HEMT with gate length (L G ) of 1 μm showed a maximum drain current density (I DS ) of 657 mA/mm, a maximum extrinsic transconductance (g m ) of 187 mS/mm and a threshold voltage (V th ) of 1 V. Comparing with the corresponding E-mode HEMT, the device performances had been greatly improved due to the insertion of Al 2 O 3 gate insulator. This provided an excellent way to realize E-mode AlGaN/GaN MIS-HEMTs with both high V th and I DS . (paper)

Cooperative effect of radiation and vapor environments on the deterioration of insulator materials

International Nuclear Information System (INIS)

Kusama, Yasuo; Okada, Sohei; Yagi, Toshiaki; Ito, Masayuki; Yoshida, Kenzo; Tamura, Naoyuki

1985-01-01

Experimental results and speculations are described on the cooperative effect of radiation and vapor environments for the deterioration of insulator cable cladding materials such as polyethylene chlorosulphonate, ethylene propylene rubber, cross-linked polyethylene, chloroprene and silicone rubber, by the separate, simultaneous or subsequent exposure of the above-mentioned two kinds of exposure factors. These experiment was carried out by considering main environmental factors in the LOCA (loss of coolant accident) conditions. Radiation experiment was made by employing 60 Co source of 9.7 kGy/h at a room-temperature air condition. Vapor environment exposure was conducted by the conditions of 120 to 160 deg C steam-saturated air conditions and others. With the experimental results described on the characteristics of the five kinds of the above-mentioned insulator materials in radiation and saturated vapor conditions, the following conclusions were obtained. Acceleration of deterioration by the cooperative action of radiation and saturated vapor was found for the examined materials except the cross-linked polyethylene. In the subsequent exposure of radiation and saturated vapor, deterioration behavior was dependent on insulator materials and component ratios of the insulator materials. For the cross-linked polyethylene, annealing effect by heat was found, and the effect was less significent in the simultaneous exposure. Restoration phenomenon was found in the cross-linked polyethylene even in the saturated vapor exposure stage of the subsequent exposure conditions of radiation exposure followed by saturated vapor. (Takagi, S.)

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Characterization of oxygen dimer-enriched silicon detectors

CERN Document Server

Boisvert, V; Moll, M; Murin, L I; Pintilie, I

2005-01-01

Various types of silicon material and silicon p+n diodes have been treated to increase the concentration of the oxygen dimer (O2i) defect. This was done by exposing the bulk material and the diodes to 6 MeV electrons at a temperature of about 350 °C. FTIR spectroscopy has been performed on the processed material confirming the formation of oxygen dimer defects in Czochralski silicon pieces. We also show results from TSC characterization on processed diodes. Finally, we investigated the influence of the dimer enrichment process on the depletion voltage of silicon diodes and performed 24 GeV/c proton irradiations to study the evolution of the macroscopic diode characteristics as a function of fluence.

Research on vacuum insulation for cryocables

International Nuclear Information System (INIS)

Graneau, P.

1974-01-01

Vacuum insulation, as compared with solid insulation, simplifies the construction of both resistive or superconducting cryogenic cables. The common vacuum space in the cable can furnish thermal insulation between the environment and the cryogenic coolant, provide electrical insulation between conductors, and establish thermal isolation between go- and return-coolant streams. The differences between solid and vacuum high voltage insulation are discussed, and research on the design, materials selection, and testing of vacuum insulated cryogenic cables is described

Effect of TMAH Etching Duration on the Formation of Silicon Nano wire Transistor Patterned by AFM Nano lithography

International Nuclear Information System (INIS)

Hutagalung, S.D.; Lew, K.C.

2012-01-01

Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)

Luminescence properties of ZnO layers grown on Si-on-insulator substrates

International Nuclear Information System (INIS)

Kumar, Bhupendra; Gong, Hao; Vicknesh, S.; Chua, S. J.; Tripathy, S.

2006-01-01

The authors report on the photoluminescence properties of polycrystalline ZnO thin films grown on compliant silicon-on-insulator (SOI) substrates by radio frequency magnetron sputtering. The ZnO thin films on SOI were characterized by micro-Raman and photoluminescence (PL) spectroscopy. The observation of E 2 high optical phonon mode near 438 cm -1 in the Raman spectra of the ZnO samples represents the wurtzite crystal structure. Apart from the near-band-edge free exciton (FX) transition around 3.35 eV at 77 K, the PL spectra of such ZnO films also showed a strong defect-induced violet emission peak in the range of 3.05-3.09 eV. Realization of such ZnO layers on SOI would be useful for heterointegration with SOI-based microelectronics and microelectromechanical systems

Novel results on fluence dependence and annealing behaviour of oxygenated and non-oxygenated silicon detectors

CERN Document Server

Martínez, C; Lozano, M; Campabadal, F; Santander, J; Fonseca, L; Ullán, M; Moreno, A

2002-01-01

This work presents the latest results on electrical properties degradation of silicon radiation detectors manufactured at IMB-CNM (Institut de Microelectronica de Barcelona) subjected to proton irradiation at CERN for high energy physics applications. The evolution of full depletion voltage and leakage current with fluence, as well as their annealing behaviour with time, were studied. The results obtained extend the previous understanding of the role played by technology and oxygenated material in hardening silicon radiation detectors. (15 refs).

Topology optimized mode multiplexing in silicon-on-insulator photonic wire waveguides

DEFF Research Database (Denmark)

Frellsen, Louise Floor; Ding, Yunhong; Sigmund, Ole

2016-01-01

We design and experimentally verify a topology optimized low-loss and broadband two-mode (de-)multiplexer, which is (de-)multiplexing the fundamental and the first-order transverse-electric modes in a silicon photonic wire. The device has a footprint of 2.6 μm x 4.22 μm and exhibits a loss 14 d...

Study of the effects of neutron irradiation on silicon strip detectors

Energy Technology Data Exchange (ETDEWEB)

Giubellino, P.; Panizza, G. (INFN Torino (Italy)); Hall, G.; Sotthibandhu, S. (Imperial Coll., London (United Kingdom)); Ziock, H.J.; Ferguson, P.; Sommer, W.F. (Los Alamos National Lab., NM (United States)); Edwards, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Cartiglia, N.; Hubbard, B.; Leslie, J.; Pitzl, D.; O' Shaughnessy, K.; Rowe, W.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E. (Santa Cruz Inst. for Particle Physics, Univ. California, CA (United States))

1992-05-01

Silicon strip detectors and test structures were exposed to neutron fluences up to {Phi}=6.1x10{sup 14} n/cm{sup 2}, using the ISIS neutron source at the Rutherford Appleton Laboratory (UK). In this paper we report some of our results concerning the effects of displacement damage, with a comparison of devices made of silicon of different resistivity. The various samples exposed showed a very similar dependence of the leakage current on the fluence received. We studied the change of effective doping concentration, and observed a behaviour suggesting the onset of type inversion at a fluence of {proportional to}2.0x10{sup 13} n/cm{sup 2}, a value which depends on the initial doping concentration. The linear increase of the depletion voltage for fluences higher than the inversion point could eventually determine the maximum fluence tolerable by silicon detectors. (orig.).

Design, fabrication and characterisation of advanced substrate crosstalk suppression structures in silicon on insulator substrates with buried ground planes (GPSOI)

International Nuclear Information System (INIS)

Stefanou, Stefanos

2002-07-01

Substrate crosstalk or coupling has been acknowledged to be a limiting factor in mixed signal RF integration. Although high levels of integration and high frequencies of operation are desirable for mixed mode RF and microwave circuits, they make substrate crosstalk more pronounced and may lead to circuit performance degradation. High signal isolation is dictated by requirements for low power dissipation, reduced number of components and lower integration costs for feasible system-on-chip (SoC) solutions. Substrate crosstalk suppression in ground plane silicon-on-insulator (GPSOI) substrates is investigated in this thesis. Test structures are designed and fabricated on SOI substrates with a buried WSi 2 plane that is connected to ground; hence it is called a ground plane. A Faraday cage structure that exhibits very high degrees of signal isolation is presented and compared to other SOI isolation schemes. The Faraday cage structure is shown to achieve 20 dB increased isolation in the frequency range of 0.5-50 GHz compared to published data for high resistivity (200 Ωcm) thin film SOI substrates with no ground planes, but where capacitive guard rings were used. The measurement results are analysed with the aid of planar electromagnetic simulators and compact lumped element models of all the fabricated test structures are developed. The accuracy of the lumped models is validated against experimental measurements. (author)

MOS structures containing silicon nanoparticles for memory device applications

International Nuclear Information System (INIS)

Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

2008-01-01

Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

Optical signal processing by silicon photonics

CERN Document Server

Ahmed, Jameel; Adeel, Freeha; Hussain, Ashiq

2014-01-01

The main objective of this book is to make respective graduate students understand the nonlinear effects inside SOI waveguide and possible applications of SOI waveguides in this emerging research area of optical fibre communication. This book focuses on achieving successful optical frequency shifting by Four Wave Mixing (FWM) in silicon-on-insulator (SOI) waveguide by exploiting a nonlinear phenomenon.

Silicon-photonics light source realized by III-V/Si grating-mirror laser

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2010-01-01

waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

Cobalt micro-magnet integration on silicon MOS quantum dots

Science.gov (United States)

Camirand Lemyre, Julien; Rochette, Sophie; Anderson, John; Manginell, Ronald P.; Pluym, Tammy; Ward, Dan; Carroll, Malcom S.; Pioro-Ladrière, Michel

Integration of cobalt micro-magnets on silicon metal-oxide-semiconductor (MOS) quantum dot devices has been investigated. The micro-magnets are fabricated in a lift-off process with e-beam lithography and deposited directly on top of an etched poly-silicon gate stack. Among the five resist stacks tested, one is found to be compatible with our MOS specific materials (Si and SiO2) . Moreover, devices with and without additional Al2O3 insulating layer show no additional gate leakage after processing. Preliminary transport data indicates electrostatic stability of our devices with integrated magnets. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Synthesis of silicon nanocomposite for printable photovoltaic devices on flexible substrate

Science.gov (United States)

Odo, E. A.; Faremi, A. A.

2017-06-01

Renewed interest has been established in the preparation of silicon nanoparticles for electronic device applications. In this work, we report on the production of silicon powders using a simple ball mill and of silicon nanocomposite ink for screen-printable photovoltaic device on a flexible substrate. Bulk single crystalline silicon was milled for 25 h in the ball mill. The structural properties of the produced silicon nanoparticles were investigated using X-ray diffraction (XRD) and transmission electron microscopy. The results show that the particles remained highly crystalline, though transformed from their original single crystalline state to polycrystalline. The elemental composition using energy dispersive X-ray florescence spectroscopy (EDXRF) revealed that contamination from iron (Fe) and chromium (Cr) of the milling media and oxygen from the atmosphere were insignificant. The size distribution of the nanoparticles follows a lognormal pattern that ranges from 60 nm to about 1.2 μm and a mean particle size of about 103 nm. Electrical characterization of screen-printed PN structures of the nanocomposite formed by embedding the powder into a suitable water-soluble polymer on Kapton sheet reveals an enhanced photocurrent transport resulting from photo-induced carrier generation in the depletion region with energy greater that the Schottky barrier height at the metal-composite interface.

Hybrid III-V/silicon lasers

Science.gov (United States)

Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

2014-05-01

The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

Luneburg lens in silicon photonics.

Science.gov (United States)

Di Falco, Andrea; Kehr, Susanne C; Leonhardt, Ulf

2011-03-14

The Luneburg lens is an aberration-free lens that focuses light from all directions equally well. We fabricated and tested a Luneburg lens in silicon photonics. Such fully-integrated lenses may become the building blocks of compact Fourier optics on chips. Furthermore, our fabrication technique is sufficiently versatile for making perfect imaging devices on silicon platforms.

New dynamic silicon photonic components enabled by MEMS technology

Science.gov (United States)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

Amorphization of silicon by femtosecond laser pulses

International Nuclear Information System (INIS)

Jia, Jimmy; Li Ming; Thompson, Carl V.

2004-01-01

We have used femtosecond laser pulses to drill submicron holes in single crystal silicon films in silicon-on-insulator structures. Cross-sectional transmission electron microscopy and energy dispersive x-ray analysis of material adjacent to the ablated holes indicates the formation of a layer of amorphous Si. This demonstrates that even when material is ablated using femtosecond pulses near the single pulse ablation threshold, sufficient heating of the surrounding material occurs to create a molten zone which solidifies so rapidly that crystallization is bypassed

Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

Directory of Open Access Journals (Sweden)

Wu Hao

2017-01-01

Full Text Available We propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG, which consists of a metal strip, a silicon core, and a silicon oxide (SiO2 insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

Defect formation and recrystallization in the silicon on sapphire films under Si{sup +} irradiation

Energy Technology Data Exchange (ETDEWEB)

Shemukhin, A.A., E-mail: shemuhin@gmail.com [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Nazarov, A.V.; Balakshin, Yu. V. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Chernysh, V.S. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Faculty of Physics, Lomonosov Moscow State University, Moscow (Russian Federation)

2015-07-01

Silicon-on-sapphire (SOS) is one of the most promising silicon-on-insulator (SOI) technologies. SOS structures are widely used in microelectronics, but to meet modern requirements the silicon layer should be 100 nm thick or less. The problem is in amount of damage in the interface layer, which decreases the quality of the produced devices. In order to improve the crystalline structure quality SOS samples with 300 nm silicon layers were implanted with Si{sup +} ions with energies in the range from 180 up to 230 keV with fluences in the range from 10{sup 14} up to 5 × 10{sup 15} cm{sup −2} at 0 °C. The crystalline structure of the samples was studied with RBS and the interface layer was studied with SIMS after subsequent annealing. It has been found out that to obtain silicon films with high lattice quality it is necessary to damage the sapphire lattice near the silicon–sapphire interface. Complete destruction of the strongly defected area and subsequent recrystallization depends on the energy of implanted ions and the substrate temperature. No significant mixing in the interface layer was observed with the SIMS.

Novel results on fluence dependence and annealing behavior of oxygenated and non-oxygenated silicon detectors

CERN Document Server

Martínez, C; Lozano, M; Campabadal, F; Santander, J; Fonseca, L; Ullán, M; Moreno, A J D

2002-01-01

This work presents the latest results on electrical properties degradation of silicon radiation detectors manufactured at the Institut de Microelectronica de Barcelona (IMB-CNM) subjected to proton irradiation at CERN, Switzerland, for high-energy physics (HEP) applications. The evolution of full depletion voltage and leakage current with fluence as well as their annealing behavior with time were studied. The results obtained extend the previous understanding of the role played by technology and oxygenated material in hardening silicon radiation detectors. (15 refs).

Silicon Nanowires for All-Optical Signal Processing in Optical Communication

DEFF Research Database (Denmark)

Pu, Minhao; Hu, Hao; Ji, Hua

2012-01-01

Silicon (Si), the second most abundant element on earth, has dominated in microelectronics for many decades. It can also be used for photonic devices due to its transparency in the range of optical telecom wavelengths which will enable a platform for a monolithic integration of optics...... and microelectronics. Silicon photonic nanowire waveguides fabricated on silicon-on-insulator (SOI) substrates are crucial elements in nano-photonic integrated circuits. The strong light confinement in nanowires induced by high index contrast SOI material enhances the nonlinear effects in the silicon nanowire core...... such as four-wave mixing (FWM) which is an imperative process for optical signal processing. Since the current mature silicon fabrication technology enables a precise dimension control on nanowires, dispersion engineering can be performed by tailoring nanowire dimensions to realize an efficient nonlinear...

Conformal deposition of an insulator layer and Ag nano paste filling of a through silicon via for a 3D interconnection

Energy Technology Data Exchange (ETDEWEB)

Baek, Kyu-Ha; Kim, Dong-Pyo; Park, Kun-Sik; Ham, Yong-Hyun; Do, Lee-Mi [Electronics and Telecommunications Research Institute, Daejeon (Korea, Republic of); Lee, Ki-Jun [Chungnam National University, Daejeon (Korea, Republic of); Kim, Kyung-Seob [Yeoju Institute of Technology, Yeoju (Korea, Republic of)

2011-09-15

In this study, we reported the feasibility of filling a high-aspect-ratio through silicon via (HARTSV) with Ag nano paste for a 3D interconnection. TSVs with aspect ratios of 8:1 {approx} 10:1 were fabricated in a deep reactive etching system by using the Bosch process. Then, SiO{sub 2} insulators were deposited by using various chemical vapor deposition (CVD) processes, including plasma enhanced CVD oxides, of which precursors were silane (PECVD Oxide) and tetraethoxysilane (PECVDTEOS), and sub-atmospheric CVD oxide (SACVD oxide). We succeeded in obtaining a SiO{sub 2} layer with good step coverage over 80% for all via CD sizes by using SACVD oxidation process. The thickness of SiO{sub 2} for the via top and the via bottom were in the range 158.8 {approx} 161.5 nm and 162.6 {approx} 170.7 nm, respectively. The HAR-TSVs were filled with Ag nano paste by using vacuum assisted paste printing. Then, the samples were cured on a hotplate at 80 .deg. C for 2 min. The temperature was increased to 180 .deg. C at a rate of 25 .deg. C/min and the samples were re-annealed for 2 min. We investigated the effects for the time of evacuation/purge process and of the vacuum drying on the filling properties. A field emission scanning electron microscope (FE-SEM), X-ray microscope and focused ion beam (FIB) microscope were used to investigate the filling profile of the TSV with Ag nano pastes. By increasing the evacuation/purge time and the vacuum drying time, we could fully fill the TSV was full filled with Ag nano paste and then form a metal plug.

Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

Science.gov (United States)

Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

2018-05-01

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

Forming Refractory Insulation On Copper Wire

Science.gov (United States)

Setlock, J.; Roberts, G.

1995-01-01

Alternative insulating process forms flexible coat of uncured refractory insulating material on copper wire. Coated wire formed into coil or other complex shape. Wire-coating apparatus forms "green" coat on copper wire. After wire coiled, heating converts "green" coat to refractory electrical insulator. When cured to final brittle form, insulating material withstands temperatures above melting temperature of wire. Process used to make coils for motors, solenoids, and other electrical devices to be operated at high temperatures.

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Directory of Open Access Journals (Sweden)

Soundous Chairat

2017-05-01

Full Text Available This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI technology at 0.6 V and a 1.1 ns/bit latency per stage.

Nano-multiplication region avalanche photodiodes and arrays

Science.gov (United States)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor)

2011-01-01

An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.

Magneto-optical non-reciprocal devices in silicon photonics

Directory of Open Access Journals (Sweden)

Yuya Shoji

2014-01-01

Full Text Available Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm.

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

Science.gov (United States)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS

VCSELs and silicon light sources exploiting SOI grating mirrors

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2012-01-01

In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

Effects of insulation on potted superconducting coils

International Nuclear Information System (INIS)

Zeller, A.F.; DeKamp, J.C.; Magsig, C.T.; Nolen, J.A.; McInturff, A.D.

1989-01-01

Test coils using identical wire but with either Formvar or Polyesterimid insulation were fabricated to determine the effects of insulation on training behavior. It was found that the type of insulation did not affect the training behavior. While considerable attention has been paid to epoxy formulations used for superconducting coils, little study has been devoted to the effects of the wire insulation on training behavior. If the insulation does not bind well with the epoxy, the wires will not be held securely in place, and training will be required to make the coil operate at its design limit. In fact, the coil may never reach its design current, showing considerable degredation. Conversely, if the epoxy-insulation reaction is to soften or weaken the insulation, then shorts and/or training may result. The authors have undertaken a study of the effects of the insulation on potted coils wet wound with Stycast 2850 FT epoxy. The wire was insulated with one of two insulting varnishes: Formvar (a polyvinyl formal resin) or Polyesterimid (a phenolic resin). Formvar is the standard insulation in the United States while Polyesterimid the European standard

Insulating Behavior in Graphene with Irradiation-induced Lattice Defects

Science.gov (United States)

Chen, Jian-Hao; Williams, Ellen; Fuhrer, Michael

2010-03-01

We irradiated cleaned graphene on silicon dioxide in ultra-high vacuum with low energy inert gas ions to produce lattice defects [1], and investigated in detail the transition from metallic to insulating temperature dependence of the conductivity as a function of defect density. We measured the low field magnetoresistance and temperature-dependent resistivity in situ and find that weak localization can only account for a small correction of the resistivity increase with decreasing temperature. We will discuss possible origins of the insulating temperature dependent resistivity in defected graphene in light of our recent experiments. [4pt] [1] Jian-Hao Chen, W. G. Cullen, C. Jang, M. S. Fuhrer, E. D. Williams, PRL 102, 236805 (2009)

Fabrication and characterization of NiO based metal-insulator-metal diode using Langmuir-Blodgett method for high frequency rectification

Science.gov (United States)

Azad, Ibrahim; Ram, Manoj K.; Goswami, D. Yogi; Stefanakos, Elias

2018-04-01

Thin film metal-insulator-metal (MIM) diodes have attracted significant attention for use in infrared energy harvesting and detection applications. As demonstrated over the past decades, MIM or metal-insulator-insulator-metal (MIIM) diodes can operate at the THz frequencies range by quantum tunneling of electrons. The aim of this work is to synthesize required ultra-thin insulating layers and fabricate MIM diodes using the Langmuir-Blodgett (LB) technique. The nickel stearate (NiSt) LB precursor film was deposited on glass, silicon (Si), ITO glass and gold coated silicon substrates. The photodesorption (UV exposure) and the thermodesorption (annealing at 100 °C and 350 °C) methods were used to remove organic components from the NiSt LB film and to achieve a uniform homogenous nickel oxide (NiO) film. These ultrathin NiO films were characterized by EDS, AFM, FTIR and cyclic voltammetry methods, respectively. The MIM diode was fabricated by depositing nickel (Ni) on the NiO film, all on a gold (Au) plated silicon (Si) substrate. The current (I)-voltage (V) characteristics of the fabricated diode were studied to understand the conduction mechanism assumed to be tunneling of electron through the ultra-thin insulating layer. The sensitivity of the diode was measured to be as high as 35 V-1. The diode resistance was ˜100 ohms (at a bias voltage of 0.60 V), and the rectification ratio was about 22 (for a signal voltage of ±200 mV). At the bias point, the diode response demonstrated significant non-linearity and high asymmetry, which are very desirable characteristics for applications in infrared detection and harvesting.

Mode converter based on an inverse taper for multimode silicon nanophotonic integrated circuits.

Science.gov (United States)

Dai, Daoxin; Mao, Mao

2015-11-02

An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future.

Effect of non-ideal clamping shape on the resonance frequencies of silicon nanocantilevers

Energy Technology Data Exchange (ETDEWEB)

Guillon, Samuel; Saya, Daisuke; Mazenq, Laurent; Nicu, Liviu [CNRS, LAAS, 7 Avenue du Colonel Roche, F-31077 Toulouse Cedex 4 (France); Perisanu, Sorin; Vincent, Pascal [LPMCN, Universite Claude Bernard Lyon 1 et CNRS, 43 boulevard du 11 novembre 1918, 69622 Villeurbanne Cedex (France); Lazarus, Arnaud; Thomas, Olivier, E-mail: sguillon@laas.fr [Structural Mechanics and Coupled Systems Laboratory, Conservatoire National des Arts et Metiers, 2 rue Conte, 75003 Paris (France)

2011-06-17

In this paper, we investigate the effects of non-ideal clamping shapes on the dynamic behavior of silicon nanocantilevers. We fabricated silicon nanocantilevers using silicon on insulator (SOI) wafers by employing stepper ultraviolet (UV) lithography, which permits a resolution of under 100 nm. The nanocantilevers were driven by electrostatic force inside a scanning electron microscope (SEM). Both lateral and out-of-plane resonance frequencies were visually detected with the SEM. Next, we discuss overhanging of the cantilever support and curvature at the clamping point in the silicon nanocantilevers, which generally arises in the fabrication process. We found that the fundamental out-of-plane frequency of a realistically clamped cantilever is always lower than that for a perfectly clamped cantilever, and depends on the cantilever width and the geometry of the clamping point structure. Using simulation with the finite-elements method, we demonstrate that this discrepancy is attributed to the particular geometry of the clamping point (non-zero joining curvatures and a flexible overhanging) that is obtained in the fabrication process. The influence of the material orthotropy is also investigated and is shown to be negligible.

Methodology for Evaluating Raw Material Changes to RSRM Elastomeric Insulation Materials

Science.gov (United States)

Mildenhall, Scott D.; McCool, Alex (Technical Monitor)

2001-01-01

The Reusable Solid Rocket Motor (RSRM) uses asbestos and silicon dioxide filled acrylonitrile butadiene rubber (AS-NBR) as the primary internal insulation to protect the case from heat. During the course of the RSRM Program, several changes have been made to the raw materials and processing of the AS-NBR elastomeric insulation material. These changes have been primarily caused by raw materials becoming obsolete. In addition, some process changes have been implemented that were deemed necessary to improve the quality and consistency of the AS-NBR insulation material. Each change has been evaluated using unique test efforts customized to determine the potential impacts of the specific raw material or process change. Following the evaluations, the various raw material and process changes were successfully implemented with no detectable effect on the performance of the AS-NBR insulation. This paper will discuss some of the raw material and process changes evaluated, the methodology used in designing the unique test plans, and the general evaluation results. A summary of the change history of RSRM AS-NBR internal insulation is also presented.

Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

Science.gov (United States)

Papes, Martin; Cheben, Pavel; Benedikovic, Daniel; Schmid, Jens H; Pond, James; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, Gonzalo; Ye, Winnie N; Xu, Dan-Xia; Janz, Siegfried; Dado, Milan; Vašinek, Vladimír

2016-03-07

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO 2 upper cladding thin high-index Si 3 N 4 layers. The Si 3 N 4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Nonlinear optical properties of silicon waveguides

International Nuclear Information System (INIS)

Tsang, H K; Liu, Y

2008-01-01

Recent work on two-photon absorption (TPA), stimulated Raman scattering (SRS) and optical Kerr effect in silicon-on-insulator (SOI) waveguides is reviewed and some potential applications of these optical nonlinearities, including silicon-based autocorrelation detectors, optical amplifiers, high speed optical switches, optical wavelength converters and self-phase modulation (SPM), are highlighted. The importance of free carriers generated by TPA in nonlinear devices is discussed, and a generalized definition of the nonlinear effective length to cater for nonlinear losses is proposed. How carrier lifetime engineering, and in particular the use of helium ion implantation, can enhance the nonlinear effective length for nonlinear devices is also discussed

Silicon Telescope Detectors

CERN Document Server

Gurov, Yu B; Sandukovsky, V G; Yurkovski, J

2005-01-01

The results of research and development of special silicon detectors with a large active area ($> 8 cm^{2}$) for multilayer telescope spectrometers (fulfilled in the Laboratory of Nuclear Problems, JINR) are reviewed. The detector parameters are listed. The production of totally depleted surface barrier detectors (identifiers) operating under bias voltage two to three times higher than depletion voltage is described. The possibility of fabrication of lithium drifted counters with a very thin entrance window on the diffusion side of the detector (about 10--20 $\\mu$m) is shown. The detector fabrication technique has allowed minimizing detector dead regions without degradation of their spectroscopic characteristics and reliability during long time operation in charge particle beams.

Memristive device based on a depletion-type SONOS field effect transistor

Science.gov (United States)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Topological insulators and superconductors from string theory

International Nuclear Information System (INIS)

Ryu, Shinsei; Takayanagi, Tadashi

2010-01-01

Topological insulators and superconductors in different spatial dimensions and with different discrete symmetries have been fully classified recently, revealing a periodic structure for the pattern of possible types of topological insulators and superconductors, both in terms of spatial dimensions and in terms of symmetry classes. It was proposed that K theory is behind the periodicity. On the other hand, D-branes, a solitonic object in string theory, are also known to be classified by K theory. In this paper, by inspecting low-energy effective field theories realized by two parallel D-branes, we establish a one-to-one correspondence between the K-theory classification of topological insulators/superconductors and D-brane charges. In addition, the string theory realization of topological insulators and superconductors comes naturally with gauge interactions, and the Wess-Zumino term of the D-branes gives rise to a gauge field theory of topological nature, such as ones with the Chern-Simons term or the θ term in various dimensions. This sheds light on topological insulators and superconductors beyond noninteracting systems, and the underlying topological field theory description thereof. In particular, our string theory realization includes the honeycomb lattice Kitaev model in two spatial dimensions, and its higher-dimensional extensions. Increasing the number of D-branes naturally leads to a realization of topological insulators and superconductors in terms of holography (AdS/CFT).

Experimental charge fractions of hydrogen scattered from insulators at 50-340 keV

CERN Document Server

Ross, Graham G

2002-01-01

Ion bombardment of insulators induces accumulation of electric charges at and under the insulator surfaces. This paper deals with the effect of the accumulated electric charges on the charge fractions of scattered hydrogen. We have measured and compiled charge fractions of hydrogen, in the energy range (for the scattered particles) from 50 to 340 keV, scattered from polystyrene, polymethylmethacrylate, polycarbonate, polyethylene and silicon. In order to establish the effect of the charge accumulation, some samples have been cut from a thick (1 mm) sheet, while some others have been spin coated (approx 250 nm) onto silicon wafers. Experimental measurements have been fitted with the equation f(0)=Aexp(-V sup 2 /V sub i V sub 0), where f(0) is the neutral fraction, V the velocity, V sub i the 'Bohr velocity' for the electron of projectiles, A and V sub 0 the fitting parameters. Comparisons using the least-square fitting procedure have shown that the accumulation of electric charges on the thick polymer samples ...

Small-scale, self-propagating combustion realized with on-chip porous silicon.

Science.gov (United States)

Piekiel, Nicholas W; Morris, Christopher J

2015-05-13

For small-scale energy applications, energetic materials represent a high energy density source that, in certain cases, can be accessed with a very small amount of energy input. Recent advances in microprocessing techniques allow for the implementation of a porous silicon energetic material onto a crystalline silicon wafer at the microscale; however, combustion at a small length scale remains to be fully investigated, particularly with regards to the limitations of increased relative heat loss during combustion. The present study explores the critical dimensions of an on-chip porous silicon energetic material (porous silicon + sodium perchlorate (NaClO4)) required to propagate combustion. We etched ∼97 μm wide and ∼45 μm deep porous silicon channels that burned at a steady rate of 4.6 m/s, remaining steady across 90° changes in direction. In an effort to minimize the potential on-chip footprint for energetic porous silicon, we also explored the minimum spacing between porous silicon channels. We demonstrated independent burning of porous silicon channels at a spacing of 0.5 m on a chip surface area of 1.65 cm(2). Smaller porous silicon channels of ∼28 μm wide and ∼14 μm deep were also utilized. These samples propagated combustion, but at times, did so unsteadily. This result may suggest that we are approaching a critical length scale for self-propagating combustion in a porous silicon energetic material.

Lithium-drifted silicon detector with segmented contacts

Science.gov (United States)

Tindall, Craig S.; Luke, Paul N.

2006-06-13

A method and apparatus for creating both segmented and unsegmented radiation detectors which can operate at room temperature. The devices include a metal contact layer, and an n-type blocking contact formed from a thin layer of amorphous semiconductor. In one embodiment the material beneath the n-type contact is n-type material, such as lithium compensated silicon that forms the active region of the device. The active layer has been compensated to a degree at which the device may be fully depleted at low bias voltages. A p-type blocking contact layer, or a p-type donor material can be formed beneath a second metal contact layer to complete the device structure. When the contacts to the device are segmented, the device is capable of position sensitive detection and spectroscopy of ionizing radiation, such as photons, electrons, and ions.

A water blown urethane insulation for use in cryogenic environments

Science.gov (United States)

Blevins, Elana; Sharpe, Jon

1995-01-01

Thermal Protection Systems (TPS) of NASA's Space Shuttle External Tank include polyurethane and polyisocyanurate modified polyurethane foam insulations. These insulations, currently foamed with CFC 11 blowing agent, serve to maintain cryogenic propellant quality, maintain the external tank structural temperature limits, and minimize the formation of ice and frost that could potentially damage the ceramic insulation on the space shuttle orbiter. During flight the external tank insulations are exposed to mechanical, thermal and acoustical stresses. TPS must pass cryogenic flexure and substrate adhesion tests at -253 C, aerothermal and radiant heating tests at fluxes up to approximately 14 kilowatts per square meter, and thermal conductivity tests at cryogenic and elevated temperatures. Due to environmental concerns, the polyurethane insulation industry and the External Tank Project are tasked with replacing CFC 11. The flight qualification of foam insulations employing HCFC 141b as a foaming agent is currently in progress; HCFC 141b blown insulations are scheduled for production implementation in 1995. Realizing that the second generation HCFC blowing agents are an interim solution, the evaluation of third generation blowing agents with zero ozone depletion potential is underway. NASA's TPS Materials Research Laboratory is evaluating third generation blowing agents in cryogenic insulations for the External Tank; one option being investigated is the use of water as a foaming agent. A dimensionally stable insulation with low friability, good adhesion to cryogenic substrates, and acceptable thermal conductivity has been developed with low viscosity materials that are easily processed in molding applications. The development criteria, statistical experimental approach, and resulting foam properties will be presented.

Sensitization to Gliadin Induces Moderate Enteropathy and Insulitis in Nonobese Diabetic-DQ8 Mice

Science.gov (United States)

Galipeau, Heather J.; Rulli, Nestor E.; Jury, Jennifer; Huang, Xianxi; Araya, Romina; Murray, Joseph A.; David, Chella S.; Chirdo, Fernando G.; McCoy, Kathy D.; Verdu, Elena F.

2012-01-01

Celiac disease (CD) is frequently diagnosed in patients with type 1 diabetes (T1D), and T1D patients can exhibit Abs against tissue transglutaminase, the auto-antigen in CD. Thus, gliadin, the trigger in CD, has been suggested to have a role in T1D pathogenesis. The objective of this study was to investigate whether gliadin contributes to enteropathy and insulitis in NOD-DQ8 mice, an animal model that does not spontaneously develop T1D. Gliadin-sensitized NOD-DQ8 mice developed moderate enteropathy, intraepithelial lymphocytosis, and barrier dysfunction, but not insulitis. Administration of anti-CD25 mAbs before gliadin-sensitization induced partial depletion of CD25+Foxp3+ T cells and led to severe insulitis, but did not exacerbate mucosal dysfunction. CD4+ T cells isolated from pancreatic lymph nodes of mice that developed insulitis showed increased proliferation and proinflammatory cytokines after incubation with gliadin but not with BSA. CD4+ T cells isolated from nonsensitized controls did not response to gliadin or BSA. In conclusion, gliadin sensitization induced moderate enteropathy in NOD-DQ8 mice. However, insulitis development required gliadin-sensitization and partial systemic depletion of CD25+Foxp3+ T cells. This humanized murine model provides a mechanistic link to explain how the mucosal intolerance to a dietary protein can lead to insulitis in the presence of partial regulatory T cell deficiency. PMID:21911598

On the timing performance of thin planar silicon sensors

Science.gov (United States)

Akchurin, N.; Ciriolo, V.; Currás, E.; Damgov, J.; Fernández, M.; Gallrapp, C.; Gray, L.; Junkes, A.; Mannelli, M.; Martin Kwok, K. H.; Meridiani, P.; Moll, M.; Nourbakhsh, S.; Pigazzini, S.; Scharf, C.; Silva, P.; Steinbrueck, G.; de Fatis, T. Tabarelli; Vila, I.

2017-07-01

We report on the signal timing capabilities of thin silicon sensors when traversed by multiple simultaneous minimum ionizing particles (MIP). Three different planar sensors, with depletion thicknesses 133, 211, and 285 μm, have been exposed to high energy muons and electrons at CERN. We describe signal shape and timing resolution measurements as well as the response of these devices as a function of the multiplicity of MIPs. We compare these measurements to simulations where possible. We achieve better than 20 ps timing resolution for signals larger than a few tens of MIPs.

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

Science.gov (United States)

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-12-13

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Movable MEMS Devices on Flexible Silicon

KAUST Repository

Ahmed, Sally

2013-05-05

Flexible electronics have gained great attention recently. Applications such as flexible displays, artificial skin and health monitoring devices are a few examples of this technology. Looking closely at the components of these devices, although MEMS actuators and sensors can play critical role to extend the application areas of flexible electronics, fabricating movable MEMS devices on flexible substrates is highly challenging. Therefore, this thesis reports a process for fabricating free standing and movable MEMS devices on flexible silicon substrates; MEMS flexure thermal actuators have been fabricated to illustrate the viability of the process. Flexure thermal actuators consist of two arms: a thin hot arm and a wide cold arm separated by a small air gap; the arms are anchored to the substrate from one end and connected to each other from the other end. The actuator design has been modified by adding etch holes in the anchors to suit the process of releasing a thin layer of silicon from the bulk silicon substrate. Selecting materials that are compatible with the release process was challenging. Moreover, difficulties were faced in the fabrication process development; for example, the structural layer of the devices was partially etched during silicon release although it was protected by aluminum oxide which is not attacked by the releasing gas . Furthermore, the thin arm of the thermal actuator was thinned during the fabrication process but optimizing the patterning and etching steps of the structural layer successfully solved this problem. Simulation was carried out to compare the performance of the original and the modified designs for the thermal actuators and to study stress and temperature distribution across a device. A fabricated thermal actuator with a 250 μm long hot arm and a 225 μm long cold arm separated by a 3 μm gap produced a deflection of 3 μm before silicon release, however, the fabrication process must be optimized to obtain fully functioning

High temperature resistant cermet and ceramic compositions. [for thermal resistant insulators and refractory coatings

Science.gov (United States)

Phillips, W. M. (Inventor)

1978-01-01

High temperature oxidation resistance, high hardness and high abrasion and wear resistance are properties of cermet compositions particularly to provide high temperature resistant refractory coatings on metal substrates, for use as electrical insulation seals for thermionic converters. The compositions comprise a sintered body of particles of a high temperature resistant metal or metal alloy, preferably molybdenum or tungsten particles, dispersed in and bonded to a solid solution formed of aluminum oxide and silicon nitride, and particularly a ternary solid solution formed of a mixture of aluminum oxide, silicon nitride and aluminum nitride. Ceramic compositions comprising a sintered solid solution of aluminum oxide, silicon nitride and aluminum nitride are also described.

Radiation damage in silicon detectors

CERN Document Server

Lindström, G

2003-01-01

Radiation damage effects in silicon detectors under severe hadron and gamma-irradiation are surveyed, focusing on bulk effects. Both macroscopic detector properties (reverse current, depletion voltage and charge collection) as also the underlying microscopic defect generation are covered. Basic results are taken from the work done in the CERN-RD48 (ROSE) collaboration updated by results of recent work. Preliminary studies on the use of dimerized float zone and Czochralski silicon as detector material show possible benefits. An essential progress in the understanding of the radiation-induced detector deterioration had recently been achieved in gamma irradiation, directly correlating defect analysis data with the macroscopic detector performance.

High-Performance Slab-on-Grade Foundation Insulation Retrofits

Energy Technology Data Exchange (ETDEWEB)

Goldberg, Louise F. [NorthernSTAR, St. Paul, MN (United States); Mosiman, Garrett E. [NorthernSTAR, St. Paul, MN (United States)

2015-09-01

A more accurate assessment of slab-on-grade foundation insulation energy savings than traditionally possible is now feasible. This has been enabled by advances in whole building energy simulation with 3-dimensional foundation modelling integration at each time step together with an experimental measurement of the site energy savings of SOG foundation insulation. Ten SOG insulation strategies were evaluated on a test building to identify an optimum retrofit insulation strategy in a zone 6 climate (Minneapolis, MN). The optimum insulation strategy in terms of energy savings and cost effectiveness consisted of two components: (a) R-20 XPS insulation above grade, and, (b) R-20 insulation at grade (comprising an outer layer of R-10 insulation and an interior layer of R-12 poured polyurethane insulation) tapering to R-10 XPS insulation at half the below-grade wall height (the lower half of the stem wall was uninsulated).

Toward the hybrid organic semiconductor FET (HOSFET) electrical and electrochemical characterization of functionalized and unfunctionalized, covalently bound organic monolayers on silicon

NARCIS (Netherlands)

Faber, Erik Jouwert

2006-01-01

Since their introduction in 1993 the class of covalently bound organic monolayers on oxide free silicon surfaces have found their way to multiple application fields such as passivation layers in solar cells, masking layers in lithographic processing, insulating films in hybrid moleculesilicon

Growth of light-emitting SiGe heterostructures on strained silicon-on-insulator substrates with a thin oxide layer

Energy Technology Data Exchange (ETDEWEB)

Baidakova, N. A., E-mail: banatale@ipmras.ru [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Bobrov, A. I. [University of Nizhny Novgorod (Russian Federation); Drozdov, M. N.; Novikov, A. V. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Pavlov, D. A. [University of Nizhny Novgorod (Russian Federation); Shaleev, M. V.; Yunin, P. A.; Yurasov, D. V.; Krasilnik, Z. F. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation)

2015-08-15

The possibility of using substrates based on “strained silicon on insulator” structures with a thin (25 nm) buried oxide layer for the growth of light-emitting SiGe structures is studied. It is shown that, in contrast to “strained silicon on insulator” substrates with a thick (hundreds of nanometers) oxide layer, the temperature stability of substrates with a thin oxide is much lower. Methods for the chemical and thermal cleaning of the surface of such substrates, which make it possible to both retain the elastic stresses in the thin Si layer on the oxide and provide cleaning of the surface from contaminating impurities, are perfecte. It is demonstrated that it is possible to use the method of molecular-beam epitaxy to grow light-emitting SiGe structures of high crystalline quality on such substrates.

Impact of substrate temperature on the incorporation of carbon-related defects and mechanism for semi-insulating behavior in GaN grown by molecular beam epitaxy

International Nuclear Information System (INIS)

Armstrong, A.; Poblenz, C.; Green, D.S.; Mishra, U.K.; Speck, J.S.; Ringel, S.A.

2006-01-01

The electrical conductivity and deep level spectrum of GaN grown by molecular beam epitaxy and codoped with carbon and silicon were investigated for substrate temperatures T s of 650 and 720 deg. C as a function relative carbon and silicon doping levels. With sufficiently high carbon doping, semi-insulating behavior was observed for films grown at both temperatures, and growth at T s =720 deg. C enhanced the carbon compensation ratio. Similar carbon-related band gap states were observed via deep level optical spectroscopy for films grown at both substrate temperatures. Due to the semi-insulating nature of the films, a lighted capacitance-voltage technique was required to determine individual deep level concentrations. Carbon-related band gap states underwent substantial redistribution between deep level and shallow acceptor configurations with change in T s . In light of a T s dependence for the preferential site of carbon incorporation, a model of semi-insulating behavior in terms of carbon impurity state incorporation mediated by substrate temperature is proposed

Controlling the Nanoscale Patterning of AuNPs on Silicon Surfaces

Directory of Open Access Journals (Sweden)

Chris J. Allender

2013-03-01

Full Text Available This study evaluates the effectiveness of vapour-phase deposition for creating sub-monolayer coverage of aminopropyl triethoxysilane (APTES on silicon in order to exert control over subsequent gold nanoparticle deposition. Surface coverage was evaluated indirectly by observing the extent to which gold nanoparticles (AuNPs deposited onto the modified silicon surface. By varying the distance of the silicon wafer from the APTES source and concentration of APTES in the evaporating media, control over subsequent gold nanoparticle deposition was achievable to an extent. Fine control over AuNP deposition (AuNPs/μm2 however, was best achieved by adjusting the ionic concentration of the AuNP-depositing solution. Furthermore it was demonstrated that although APTES was fully removed from the silicon surface following four hours incubation in water, the gold nanoparticle-amino surface complex was stable under the same conditions. Atomic force microscopy (AFM and X-ray photoelectron spectroscopy (XPS were used to study these affects.

Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

International Nuclear Information System (INIS)

Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

2008-01-01

Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

Effects of size and defects on the elasticity of silicon nanocantilevers

International Nuclear Information System (INIS)

Sadeghian, Hamed; Goosen, Johannes F L; Van Keulen, Fred; Yang, Chung-Kai; Bossche, Andre; French, Paddy J; Staufer, Urs

2010-01-01

The size-dependent elastic behavior of silicon nanocantilevers and nanowires, specifically the effective Young's modulus, has been determined by experimental measurements and theoretical investigations. The size dependence becomes more significant as the devices scale down from micro- to nano-dimensions, which has mainly been attributed to surface effects. However, discrepancies between experimental measurements and computational investigations show that there could be other influences besides surface effects. In this paper, we try to determine to what extent the surface effects, such as surface stress, surface elasticity, surface contamination and native oxide layers, influence the effective Young's modulus of silicon nanocantilevers. For this purpose, silicon cantilevers were fabricated in the top device layer of silicon on insulator (SOI) wafers, which were thinned down to 14 nm. The effective Young's modulus was extracted with the electrostatic pull-in instability method, recently developed by the authors (H Sadeghian et al 2009 Appl. Phys. Lett. 94 221903). In this work, the drop in the effective Young's modulus was measured to be significant at around 150 nm thick cantilevers. The comparison between theoretical models and experimental measurements demonstrates that, although the surface effects influence the effective Young's modulus of silicon to some extent, they alone are insufficient to explain why the effective Young's modulus decreases prematurely. It was observed that the fabrication-induced defects abruptly increased when the device layer was thinned to below 100 nm. These defects became visible as pinholes during HF-etching. It is speculated that they could be the origin of the reduced effective Young's modulus experimentally observed in ultra-thin silicon cantilevers.

Nanosílice como carga en la RTV SR usada para cubrir aisladores; Nanosilica as filler in the Room temperature vulcanized silicone rubber used to coat insulators

Directory of Open Access Journals (Sweden)

Ignat Pérez Almirall

2014-04-01

Full Text Available En el presente trabajo se realiza un estudio sobre la influencia que tiene agregar como carga nanosílice a la goma de silicona vulcanizada a temperatura ambiente (RTV SR, por sus siglas en inglés que es empleada para cubrir aisladores de vidrio o de porcelana. Con este objetivo se observó la dispersión de la nanosílice en la RTV SR por medio de microscopía electrónica de barrido (MEV, por sus siglas en inglés, se midió la permitividad de la RTV SR con y sin nanosílice para varias frecuencias y se evaluó la influencia que tiene la nanosílice en la resistencia a la erosión. Además fueron medidas las corrientes de fuga durante ensayos de niebla salina a aisladores de vidrio pintados con estos recubrimientos, analizando también la pérdida de hidrofobicidad que ocurre durante el ensayo y su recuperación una vez finalizado el mismo.  The present research work carries out a study on the influence of nanosilica on room temperature vulcanized silicone rubber (RTV SR used to coat insulators. Considering this objective, the dispersion of nanosilica was observed by means of scanning electron microscopy (MEV, the permittivity of the room temperature vulcanized silicone rubber was measured with and without nanosilica for different frequencies and the influence of nanosilica in erosion resistance. Leakage currents were also measured during salt spray tests to glass insulators covered with these coatings; the loss of hidrophobicity during the test was also measured and its recovery was analyzed the test was finished.

Nanosílice como carga en la RTV SR usada para cubrir aisladores/ Nanosilica as filler in the Room temperature vulcanized silicone rubber used to coat insulators

Directory of Open Access Journals (Sweden)

Ignat Pérez Almirall

2012-02-01

Full Text Available En el presente trabajo se realiza un estudio sobre la influencia que tiene agregar como carga nanosílice a la goma de silicona vulcanizada a temperatura ambiente (RTV SR, por sus siglas en inglés que es empleada para cubrir aisladores de vidrio o de porcelana. Con este objetivo se observó la dispersión de la nanosílice en la RTV SR por medio de microscopía electrónica de barrido (MEV, por sus siglas en inglés, se midió la permitividad de la RTV SR con y sin nanosílice para varias frecuencias y se evaluó la influencia que tiene la nanosílice en la resistencia a la erosión. Además fueron medidas las corrientes de fuga durante ensayos de niebla salina a aisladores de vidrio pintados con estos recubrimientos, analizando también la pérdida de hidrofobicidad que ocurre durante el ensayo y su recuperación una vez finalizado el mismo.The present research work carries out a study on the influence of nanosilica on room temperature vulcanized silicone rubber (RTV SR used to coat insulators. Considering this objective, the dispersion of nanosilica was observed by means of scanning electron microscopy (MEV, the permittivity of the room temperature vulcanized silicone rubber was measured with and without nanosilica for different frequencies and the influence of nanosilica in erosion resistance. Leakage currents were also measured during salt spray tests to glass insulators covered with these coatings; the loss of hidrophobicity during the test was also measured and its recovery was analyzed the test was finished.

Ultrathin, epitaxial cerium dioxide on silicon

Energy Technology Data Exchange (ETDEWEB)

Flege, Jan Ingo, E-mail: flege@ifp.uni-bremen.de; Kaemena, Björn; Höcker, Jan; Schmidt, Thomas; Falta, Jens [Institute of Solid State Physics, University of Bremen, Otto-Hahn-Allee 1, 28359 Bremen (Germany); Bertram, Florian [Photon Science, Deutsches Elektronensynchrotron (DESY), Notkestraße 85, 22607 Hamburg (Germany); Wollschläger, Joachim [Department of Physics, University of Osnabrück, Barbarastraße 7, 49069 Osnabrück (Germany)

2014-03-31

It is shown that ultrathin, highly ordered, continuous films of cerium dioxide may be prepared on silicon following substrate prepassivation using an atomic layer of chlorine. The as-deposited, few-nanometer-thin Ce{sub 2}O{sub 3} film may very effectively be converted at room temperature to almost fully oxidized CeO{sub 2} by simple exposure to air, as demonstrated by hard X-ray photoemission spectroscopy and X-ray diffraction. This post-oxidation process essentially results in a negligible loss in film crystallinity and interface abruptness.

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

Science.gov (United States)

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

Silicon sensor probing and radiation studies for the LHCb silicon tracker

International Nuclear Information System (INIS)

Lois, Cristina

2006-01-01

The LHCb Silicon Tracker (ST) will be built using silicon micro-strip technology. A total of 1400 sensors, with strip pitches of approximately 200μm and three different substrate thicknesses, will be used to cover the sensitive area with readout strips up to 38cm in length. We present the quality assurance program followed by the ST group together with the results obtained for the first batches of sensors from the main production. In addition, we report on an investigation of the radiation hardness of the sensors. Prototype sensors were irradiated with 24GeV/c protons up to fluences equivalent to 20 years of LHCb operation. The damage coefficient for the leakage current was studied, and full depletion voltages were determined

Electronics and readout of a large area silicon detector for LHC

International Nuclear Information System (INIS)

Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.

1994-01-01

The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)

Design and theoretical calculation of novel GeSn fully-depleted n-tunneling FET with quantum confinement model for suppression on GIDL effect

Science.gov (United States)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Miao, Yuanhao; Han, Genquan; Wang, Bin

2018-06-01

In this paper, a novel fully-depleted Ge1-xSnx n-Tunneling FET (FD Ge1-xSnx nTFET) with field plate is investigated theoretically based on the experiment previously published. The energy band structures of Ge1-xSnx are calculated by EMP and the band-to-band tunneling (BTBT) parameters of Ge1-xSnx are calculated by Kane's model. The electrical characteristics of FD Ge1-xSnx nTFET and FD Ge1-xSnx nTFET with field plate (FD-FP Ge1-xSnx nTFET) having various Sn compositions are investigated and simulated with quantum confinement model. The results indicated that the GIDL effect is serious in FD Ge1-xSnx nTFET. By employing the field plate structure, the GIDL effect of FD-FP Ge1-xSnx nTFET is suppressed and the off-state current Ioff is decreased more than 2 orders of magnitude having Sn compositions from 0 to 0.06 compared with FD Ge1-xSnx nTFET. The impact of the difference of work function between field plate metal and channel Φfps is also studied. With the optimized Φfps = 0.0 eV, the on-state current Ion = 4.6 × 10-5 A/μm, the off-state current Ioff = 1.6 × 10-13 A/μm and the maximum on/off ration Ion/Ioff = 2.9 × 108 are achieved.

Neutron irradiation test of depleted CMOS pixel detector prototypes

International Nuclear Information System (INIS)

Mandić, I.; Cindro, V.; Gorišek, A.; Hiti, B.; Kramberger, G.; Mikuž, M.; Zavrtanik, M.; Hemperek, T.; Daas, M.; Hügging, F.; Krüger, H.; Pohl, D.-L.; Wermes, N.; Gonella, L.

2017-01-01

Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 kΩ cm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1 · 10 13 n/cm 2 and 5 · 10 13 n/cm 2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1 · 10 15 n/cm 2 is more than 50 μm at 100 V bias. This is sufficient to guarantee satisfactory signal/noise performance on outer layers of pixel trackers in HL-LHC experiments.

RF characterization and analytical modelling of through silicon vias and coplanar waveguides for 3D integration

NARCIS (Netherlands)

Lamy, Y.; Jinesh, K.B.; Roozeboom, F.; Gravesteijn, D.J.; Besling, W.F.A.

2010-01-01

High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up

Novel Concepts for Silicon Based Photovoltaics and Photoelectrochemistry

NARCIS (Netherlands)

Han, L.

2015-01-01

Long term concerns about climate change and fossil fuel depletion will require a transition towards energy systems powered by solar radiation or other renewable sources. Novel concepts based on silicon materials and devices are investigated for applications in the next generation photovoltaic (PV)

Fabrication and characterization of fully ceramic microencapsulated fuels

Energy Technology Data Exchange (ETDEWEB)

Terrani, K.A., E-mail: kurt.terrani@gmail.com [Fuel Cycle and Isotopes Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Kiggans, J.O.; Katoh, Y. [Materials Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Shimoda, K. [Institute of Advanced Energy, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); Montgomery, F.C.; Armstrong, B.L.; Parish, C.M. [Materials Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Hinoki, T. [Institute of Advanced Energy, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); Hunn, J.D. [Fuel Cycle and Isotopes Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Snead, L.L. [Materials Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States)

2012-07-15

The current generation of fully ceramic microencapsulated fuels, consisting of Tristructural Isotropic fuel particles embedded in a silicon carbide matrix, is fabricated by hot pressing. Matrix powder feedstock is comprised of alumina-yttria additives thoroughly mixed with silicon carbide nanopowder using polyethyleneimine as a dispersing agent. Fuel compacts are fabricated by hot pressing the powder-fuel particle mixture at a temperature of 1800-1900 Degree-Sign C using compaction pressures of 10-20 MPa. Detailed microstructural characterization of the final fuel compacts shows that oxide additives are limited in extent and are distributed uniformly at silicon carbide grain boundaries, at triple joints between silicon carbide grains, and at the fuel particle-matrix interface.

Silicon opto-electronic wavelength tracker based on an asymmetric 2x3 Mach-Zehnder Interferometer

OpenAIRE

Doménech Gómez, José David; Sanchez Fandiño, Javier Antonio; Gargallo Jaquotot, Bernardo Andrés; Baños Lopez, Rocio; Muñoz Muñoz, Pascual

2014-01-01

In this paper we report on the experimental demonstration of a Silicon-on-Insulator opto-electronic wavelength tracker for the optical telecommunication C-band. The device consist of a 2x3 Mach-Zehnder Interferometer (MZI) with 10 pm resolution and photo-detectors integrated on the same chip. The MZI is built interconnecting two Multimode Interference (MMI) couplers with two waveguides whose length difference is 56 mm. The first MMI has a coupling ratio of 95:05 to com...

Low-loss slot waveguides with silicon (111 surfaces realized using anisotropic wet etching

Directory of Open Access Journals (Sweden)

Kapil Debnath

2016-11-01

Full Text Available We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI platform. Waveguides oriented along the (11-2 direction on the Si (110 plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

Technology Development on P-type Silicon Strip Detectors for Proton Beam Dosimetry

International Nuclear Information System (INIS)

Aouadi, K.; Bouterfa, M.; Delamare, R.; Flandre, D.; Bertrand, D.; Henry, F.

2013-06-01

In this paper, we present a technology for the fabrication of n-in-p silicon strip detectors, which is based on the use of Al 2 O 3 oxide compared to p-spray insulation scheme. This technology has been developed using the best technological parameters deduced from simulations, particularly for the p-spray implantation parameters. Different wafers were processed towards the fabrication of the radiation detectors with p-spray insulation and Al 2 O 3 . The evaluation of the prototype detectors has been carried out by performing the electrical characterization of the devices through the measurement of current-voltage and capacitance-voltage characteristics, as well as the measurement of detection response under radiation. The results of electrical measurements indicate that detectors fabricated with Al 2 O 3 exhibit a dark current several times lower than p-spray detectors and show an excellent electrical insulation between strips with a higher inter-strip resistance. Response of Al 2 O 3 strip detector under radiation has been found better. The resulting improved output signal dynamic range finally makes the use of Al 2 O 3 more attractive. (authors)

An update on irradiation of wire and cable

International Nuclear Information System (INIS)

Hildreth, N.

1981-01-01

Radiation curing with electron accelerators is a growing high technology application in the wire and cable industry. They are used with voltages ranging from 500,000 up to 3,000,000 electron volts. Furthermore new machines are available up to 5.0 MeV. These industrial machines are high powered accelerators which operate continuously between 60 and 75 kilowatts with a few of the new machines operating up to 200 kilowatts. Radiation curing is used as a tool for developing new insulation systems based on low cost materials for applications which previously required the use of expensive fluorocarbon or silicone rubber type insulations. With the development of the larger, more efficient and reliable accelerators and the continuous trend toward developing new insulations designed to fully utilize the potential of radiation chemistry, the authors are confident that industry will continue to be provided with better, lower cost insulation systems

Plasma texturing on large-area industrial grade CZ silicon solar cells

DEFF Research Database (Denmark)

Davidsen, Rasmus Schmidt; Nordseth, Ørnulf; Schmidt, Michael Stenbæk

2013-01-01

We report on an experimental study of nanostructuring of silicon solar cells using reactive ion etching (RIE). A simple mask-less, scalable RIE nanostructuring of the solar cell surface is shown to reduce the AM1.5-weighted average reflectance to a level below 1 % in a fully optimized RIE texturi...

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

Science.gov (United States)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Quality Tests of Double-Sided Silicon Strip Detectors

CERN Document Server

Cambon, T; CERN. Geneva; Fintz, P; Guillaume, G; Jundt, F; Kuhn, C; Lutz, Jean Robert; Pagès, P; Pozdniakov, S; Rami, F; Sparavec, K; Dulinski, W; Arnold, L

1997-01-01

The quality of the SiO2 insulator (AC coupling between metal and implanted strips) of double-sided Silicon strip detectors has been studied by using a probe station. Some tests performed on 23 wafers are described and the results are discussed. Remark This note seems to cause problems with ghostview but it can be printed without any problem.

Silicon Qubits

Energy Technology Data Exchange (ETDEWEB)

Ladd, Thaddeus D. [HRL Laboratories, LLC, Malibu, CA (United States); Carroll, Malcolm S. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2018-02-28

Silicon is a promising material candidate for qubits due to the combination of worldwide infrastructure in silicon microelectronics fabrication and the capability to drastically reduce decohering noise channels via chemical purification and isotopic enhancement. However, a variety of challenges in fabrication, control, and measurement leaves unclear the best strategy for fully realizing this material’s future potential. In this article, we survey three basic qubit types: those based on substitutional donors, on metal-oxide-semiconductor (MOS) structures, and on Si/SiGe heterostructures. We also discuss the multiple schema used to define and control Si qubits, which may exploit the manipulation and detection of a single electron charge, the state of a single electron spin, or the collective states of multiple spins. Far from being comprehensive, this article provides a brief orientation to the rapidly evolving field of silicon qubit technology and is intended as an approachable entry point for a researcher new to this field.

Effective carrier sweepout in a silicon waveguide by a metal-semiconductor-metal structure

DEFF Research Database (Denmark)

Ding, Yunhong; Hu, Hao; Ou, Haiyan

2015-01-01

We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated.......We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated....

Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

International Nuclear Information System (INIS)

Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

2016-01-01

The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

Energy Technology Data Exchange (ETDEWEB)

Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

2016-07-11

The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

Sharpness and intensity modulation of the metal-insulator transition in ultrathin VO2 films by interfacial structure manipulation

Science.gov (United States)

McGee, Ryan; Goswami, Ankur; Pal, Soupitak; Schofield, Kalvin; Bukhari, Syed Asad Manzoor; Thundat, Thomas

2018-03-01

Vanadium dioxide (VO2) undergoes a structural transformation from monoclinic (insulator) to tetragonal (metallic) upon heating above 340 K, accompanied by abrupt changes to its electronic, optical, and mechanical properties. Not only is this transition scientifically intriguing, but there are also numerous applications in sensing, memory, and optoelectronics. Here we investigate the effect different substrates and the processing conditions have on the characteristics metal-insulator transition (MIT), and how the properties can be tuned for specific applications. VO2 thin films were grown on c -plane sapphire (0001) and p-type silicon by pulsed laser deposition. High-resolution x-ray diffraction along with transmission electron microscopy reveals textured epitaxial growth on sapphire by domain-matching epitaxy, while the presence of a native oxide layer on silicon prevented any preferential growth resulting in a polycrystalline film. An orientation relationship of (010)VO2|| (0001)Al 2O3 was established for VO2 grown on sapphire, while no such relationship was found for VO2 grown on silicon. Surface-energy minimization is the driving force behind grain growth, as the lowest energy VO2 plane grew on silicon, while on sapphire the desire for epitaxial growth was dominant. Polycrystallinity of films grown on silicon caused a weaker and less prominent MIT than observed on sapphire, whose MIT was higher in magnitude and steeper in slope. The position of the MIT was shown to depend on the competing effects of misfit strain and grain growth. Higher deposition temperatures caused an increase in the MIT, while compressive strain resulted in a decreased MIT.

Large volume cryogenic silicon detectors

International Nuclear Information System (INIS)

Braggio, C.; Boscardin, M.; Bressi, G.; Carugno, G.; Corti, D.; Galeazzi, G.; Zorzi, N.

2009-01-01

We present preliminary measurements for the development of a large volume silicon detector to detect low energy and low rate energy depositions. The tested detector is a one cm-thick silicon PIN diode with an active volume of 31 cm 3 , cooled to the liquid helium temperature to obtain depletion from thermally-generated free carriers. A thorough study has been done to show that effects of charge trapping during drift disappears at a bias field value of the order of 100V/cm.

High-contrast gratings for long-wavelength laser integration on silicon

Science.gov (United States)

Sciancalepore, Corrado; Descos, Antoine; Bordel, Damien; Duprez, Hélène; Letartre, Xavier; Menezo, Sylvie; Ben Bakir, Badhise

2014-02-01

Silicon photonics is increasingly considered as the most promising way-out to the relentless growth of data traffic in today's telecommunications infrastructures, driving an increase in transmission rates and computing capabilities. This is in fact challenging the intrinsic limit of copper-based, short-reach interconnects and microelectronic circuits in data centers and server architectures to offer enough modulation bandwidth at reasonable power dissipation. In the context of the heterogeneous integration of III-V direct-bandgap materials on silicon, optics with high-contrast metastructures enables the efficient implementation of optical functions such as laser feedback, input/output (I/O) to active/passive components, and optical filtering, while heterogeneous integration of III-V layers provides sufficient optical gain, resulting in silicon-integrated laser sources. The latest ensure reduced packaging costs and reduced footprint for the optical transceivers, a key point for the short reach communications. The invited talk will introduce the audience to the latest breakthroughs concerning the use of high-contrast gratings (HCGs) for the integration of III-V-on-Si verticalcavity surface-emitting lasers (VCSELs) as well as Fabry-Perot edge-emitters (EELs) in the main telecom band around 1.55 μm. The strong near-field mode overlap within HCG mirrors can be exploited to implement unique optical functions such as dense wavelength division multiplexing (DWDM): a 16-λ100-GHz-spaced channels VCSEL array is demonstrated. On the other hand, high fabrication yields obtained via molecular wafer bonding of III-V alloys on silicon-on-insulator (SOI) conjugate excellent device performances with cost-effective high-throughput production, supporting industrial needs for a rapid research-to-market transfer.

Specific features of the current–voltage characteristics of SiO{sub 2}/4H-SiC MIS structures with phosphorus implanted into silicon carbide

Energy Technology Data Exchange (ETDEWEB)

Mikhaylova, A. I., E-mail: m.aleksey.spb@gmail.com; Afanasyev, A. V.; Ilyin, V. A.; Luchinin, V. V. [St. Petersburg State Electrotechnical University LETI (Russian Federation); Sledziewski, T. [Friedrich–Alexander–Universität Erlangen–Nürnberg (Germany); Reshanov, S. A.; Schöner, A. [Ascatron AB (Sweden); Krieger, M. [Friedrich–Alexander–Universität Erlangen–Nürnberg (Germany)

2016-01-15

The effect of phosphorus implantation into a 4H-SiC epitaxial layer immediately before the thermal growth of a gate insulator in an atmosphere of dry oxygen on the reliability of the gate insulator is studied. It is found that, together with passivating surface states, the introduction of phosphorus ions leads to insignificant weakening of the dielectric breakdown field and to a decrease in the height of the energy barrier between silicon carbide and the insulator, which is due to the presence of phosphorus atoms at the 4H-SiC/SiO{sub 2} interface and in the bulk of silicon dioxide.

Observation of apparent MOS regimes on Al/PECVD grown boron nitride/p-c-Si/Al MIS structure, investigated through admittance spectroscopy

Energy Technology Data Exchange (ETDEWEB)

Oezdemir, Orhan [Yildiz Technical University, Department of Physics, Esenler, istanbul (Turkey)

2009-02-15

PECVD grown boron nitride (BN) on crystalline silicon (c-Si) semiconductor was investigated by admittance measurement in the form of metal/insulator/semiconductor (MIS) structure. Apart from well-known regimes of traditional MOS structure, gradual bypassing of depletion layer was observed once ambient temperature (frequency) increased (decreased). Such an anomalous behavior was interpreted through modulations of charges located within BN film and/or at the interfacial layer of BN film/c-Si junction in terms of weighted average concept. (author)

ANATOMY OF DEPLETED INTERPLANETARY CORONAL MASS EJECTIONS

Energy Technology Data Exchange (ETDEWEB)

Kocher, M.; Lepri, S. T.; Landi, E.; Zhao, L.; Manchester, W. B. IV, E-mail: mkocher@umich.edu [Department of Climate and Space Sciences and Engineering, University of Michigan, 2455 Hayward Street, Ann Arbor, MI 48109-2143 (United States)

2017-01-10

We report a subset of interplanetary coronal mass ejections (ICMEs) containing distinct periods of anomalous heavy-ion charge state composition and peculiar ion thermal properties measured by ACE /SWICS from 1998 to 2011. We label them “depleted ICMEs,” identified by the presence of intervals where C{sup 6+}/C{sup 5+} and O{sup 7+}/O{sup 6+} depart from the direct correlation expected after their freeze-in heights. These anomalous intervals within the depleted ICMEs are referred to as “Depletion Regions.” We find that a depleted ICME would be indistinguishable from all other ICMEs in the absence of the Depletion Region, which has the defining property of significantly low abundances of fully charged species of helium, carbon, oxygen, and nitrogen. Similar anomalies in the slow solar wind were discussed by Zhao et al. We explore two possibilities for the source of the Depletion Region associated with magnetic reconnection in the tail of a CME, using CME simulations of the evolution of two Earth-bound CMEs described by Manchester et al.

Comparison of pad detectors produced on different silicon materials after irradiation with neutrons, protons and pions

International Nuclear Information System (INIS)

Kramberger, G.; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M.

2010-01-01

A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of Φ eq =3x10 15 cm -2 . The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.

Comparison of pad detectors produced on different silicon materials after irradiation with neutrons, protons and pions

Energy Technology Data Exchange (ETDEWEB)

Kramberger, G., E-mail: Gregor.Kramberger@ijs.s [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia); Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M. [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia)

2010-01-01

A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of PHI{sub eq}=3x10{sup 15}cm{sup -2}. The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.

The two sides of silicon detectors

International Nuclear Information System (INIS)

Devine, S.R.

2001-10-01

Results are presented on in situ irradiation of silicon detector's at cryogenic temperature. The results show that irradiation at cryogenic temperatures does not detrimentally effect a silicon detectors performance when compared to its irradiation at room temperature. Operation of silicon devices at cryogenic temperatures offers the advantage of reducing radiation-induced leakage current to levels of a few pA, while at 130K the Lazarus Effect plays an important role i.e. minimum voltage required for full depletion. Performing voltage scans on a 'standard' silicon pad detector pre- and post annealing, the charge collection efficiency was found to be 60% at 200V and 95% at 200V respectively. Time dependence measurements are presented, showing that for a dose of 6.5x10 14 p/cm 2 (450GeV protons) the time dependence of the charge collection efficiency is negligible. However, for higher doses, 1.2x10 15 p/cm 2 , the charge collection efficiency drops from an initial measured value of 67% to a stable value of 58% over a period of 15 minutes for reversed biased diodes. An analysis of the 'double junction' effect is also presented. A comparison between the Transient Current Technique and an X-ray technique is presented. The double junction has been observed in p + /n/n + silicon detectors after irradiation beyond 'type inversion', corresponding to a fluence equivalent to ∼3x10 13 cm -2 1MeV neutrons, producing p + /p/n + and essentially two p-n junctions within one device. With increasing bias voltage, as the electric field is extending into the detector bulk from opposite sides of the silicon detector, there are two distinct depletion regions that collect charge signal independently. Summing the signal charge from the two regions, one is able to reconstruct the initial energy of the incident particle. From Transient Current measurements it is apparent that E-field manipulation is possible by excess carrier injection, enabling a high enough E-field to extend across the

Effect of substrate bias voltage on tensile properties of single crystal silicon microstructure fully coated with plasma CVD diamond-like carbon film

Science.gov (United States)

Zhang, Wenlei; Hirai, Yoshikazu; Tsuchiya, Toshiyuki; Tabata, Osamu

2018-06-01

Tensile strength and strength distribution in a microstructure of single crystal silicon (SCS) were improved significantly by coating the surface with a diamond-like carbon (DLC) film. To explore the influence of coating parameters and the mechanism of film fracture, SCS microstructure surfaces (120 × 4 × 5 μm3) were fully coated by plasma enhanced chemical vapor deposition (PECVD) of a DLC at five different bias voltages. After the depositions, Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), thermal desorption spectrometry (TDS), surface profilometry, atomic force microscope (AFM) measurement, and nanoindentation methods were used to study the chemical and mechanical properties of the deposited DLC films. Tensile test indicated that the average strength of coated samples was 13.2-29.6% higher than that of the SCS sample, and samples fabricated with a -400 V bias voltage were strongest. The fracture toughness of the DLC film was the dominant factor in the observed tensile strength. Deviations in strength were reduced with increasingly negative bias voltage. The effect of residual stress on the tensile properties is discussed in detail.

Growth and characterization of semi-insulating carbon-doped/undoped GaN multiple-layer buffer

International Nuclear Information System (INIS)

Kim, Dong-Seok; Won, Chul-Ho; Kang, Hee-Sung; Kim, Young-Jo; Kang, In Man; Lee, Jung-Hee; Kim, Yong Tae

2015-01-01

We have proposed a new semi-insulating GaN buffer layer, which consists of multiple carbon-doped and undoped GaN layer. The buffer layer showed sufficiently good semi-insulating characteristics, attributed to the depletion effect between the carbon-doped GaN and the undoped GaN layers, even though the thickness of the carbon-doped GaN layer in the periodic structure was designed to be very thin to minimize the total carbon incorporation into the buffer layer. The AlGaN/AlN/GaN heterostructure grown on the proposed buffer exhibited much better electrical and structural properties than that grown on the conventional thick carbon-doped semi-insulating GaN buffer layer, confirmed by Hall measurement, x-ray diffraction, and secondary ion mass spectrometry. The fabricated device also showed excellent buffer breakdown characteristics. (paper)

Optical interconnects based on VCSELs and low-loss silicon photonics

Science.gov (United States)

Aalto, Timo; Harjanne, Mikko; Karppinen, Mikko; Cherchi, Matteo; Sitomaniemi, Aila; Ollila, Jyrki; Malacarne, Antonio; Neumeyr, Christian

2018-02-01

Silicon photonics with micron-scale Si waveguides offers most of the benefits of submicron SOI technology while avoiding most of its limitations. In particular, thick silicon-on-insulator (SOI) waveguides offer 0.1 dB/cm propagation loss, polarization independency, broadband single-mode (SM) operation from 1.2 to >4 µm wavelength and ability to transmit high optical powers (>1 W). Here we describe the feasibility of Thick-SOI technology for advanced optical interconnects. With 12 μm SOI waveguides we demonstrate efficient coupling between standard single-mode fibers, vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs), as well as wavelength multiplexing in small footprint. Discrete VCSELs and PDs already support 28 Gb/s on-off keying (OOK), which shows a path towards 50-100 Gb/s bandwidth per wavelength by using more advanced modulation formats like PAM4. Directly modulated VCSELs enable very power-efficient optical interconnects for up to 40 km distance. Furthermore, with 3 μm SOI waveguides we demonstrate extremely dense and low-loss integration of numerous optical functions, such as multiplexers, filters, switches and delay lines. Also polarization independent and athermal operation is demonstrated. The latter is achieved by using short polymer waveguides to compensate for the thermo-optic effect in silicon. New concepts for isolator integration and polarization rotation are also explained.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

Directory of Open Access Journals (Sweden)

Seok Young Ji

2018-02-01

Full Text Available The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

Science.gov (United States)

Ji, Seok Young; Choi, Wonsuk; Jeon, Jin-Woo; Chang, Won Seok

2018-01-01

The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag) nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations. PMID:29425144

Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET.

Science.gov (United States)

Voisin, B; Maurand, R; Barraud, S; Vinet, M; Jehl, X; Sanquer, M; Renard, J; De Franceschi, S

2016-01-13

Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz.

High-speed detection at two micrometres with monolithic silicon photodiodes

Science.gov (United States)

Ackert, Jason J.; Thomson, David J.; Shen, Li; Peacock, Anna C.; Jessop, Paul E.; Reed, Graham T.; Mashanovich, Goran Z.; Knights, Andrew P.

2015-06-01

With continued steep growth in the volume of data transmitted over optical networks there is a widely recognized need for more sophisticated photonics technologies to forestall a ‘capacity crunch’. A promising solution is to open new spectral regions at wavelengths near 2 μm and to exploit the long-wavelength transmission and amplification capabilities of hollow-core photonic-bandgap fibres and the recently available thulium-doped fibre amplifiers. To date, photodetector devices for this window have largely relied on III-V materials or, where the benefits of integration with silicon photonics are sought, GeSn alloys, which have been demonstrated thus far with only limited utility. Here, we describe a silicon photodiode operating at 20 Gbit s-1 in this wavelength region. The detector is compatible with standard silicon processing and is integrated directly with silicon-on-insulator waveguides, which suggests future utility in silicon-based mid-infrared integrated optics for applications in communications.

Effect of argon implantation on solid-state dewetting: control of size and surface density of silicon nanocrystals.

Science.gov (United States)

Almadori, Y; Borowik, Ł; Chevalier, N; Barbé, J-C

2017-01-27

Thermally induced solid-state dewetting of ultra-thin films on insulators is a process of prime interest, since it is capable of easily forming nanocrystals. If no particular treatment is performed to the film prior to the solid-state dewetting, it is already known that the size, the shape and the density of nanocrystals is governed by the initial film thickness. In this paper, we report a novel approach to control the size and the surface density of silicon nanocrystals based on an argon-implantation preliminary surface treatment. Using 7.5 nm thin layers of silicon, we show that increasing the implantation dose tends to form smaller silicon nanocrystals with diameter and height lower than 50 nm and 30 nm, respectively. Concomitantly, the surface density is increased by a factor greater than 20, going from 5 μm -2 to values over 100 μm -2 .

Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

DEFF Research Database (Denmark)

Strobel, S.; Albert, E.; Csaba, G.

2009-01-01

We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

Features of carrier tunneling between the silicon valence band and metal in devices based on the Al/high-K oxide/SiO_2/Si structure

International Nuclear Information System (INIS)

Vexler, M. I.; Grekhov, I. V.

2016-01-01

The features of electron tunneling from or into the silicon valence band in a metal–insulator–semiconductor system with the HfO_2(ZrO_2)/SiO_2 double-layer insulator are theoretically analyzed for different modes. It is demonstrated that the valence-band current plays a less important role in structures with HfO_2(ZrO_2)/SiO_2 than in structures containing only silicon dioxide. In the case of a very wide-gap high-K oxide ZrO_2, nonmonotonic behavior related to tunneling through the upper barrier is predicted for the valence-band–metal current component. The use of an insulator stack can offer certain advantages for some devices, including diodes, bipolar tunnel-emitter transistors, and resonant-tunneling diodes, along with the traditional use of high-K insulators in a field-effect transistor.

Large volume cryogenic silicon detectors

Energy Technology Data Exchange (ETDEWEB)

Braggio, C. [Dipartimento di Fisica, Universita di Padova, via Marzolo 8, 35131 Padova (Italy); Boscardin, M. [Fondazione Bruno Kessler (FBK), via Sommarive 18, I-38100 Povo (Italy); Bressi, G. [INFN sez. di Pavia, via Bassi 6, 27100 Pavia (Italy); Carugno, G.; Corti, D. [INFN sez. di Padova, via Marzolo 8, 35131 Padova (Italy); Galeazzi, G. [INFN lab. naz. Legnaro, viale dell' Universita 2, 35020 Legnaro (Italy); Zorzi, N. [Fondazione Bruno Kessler (FBK), via Sommarive 18, I-38100 Povo (Italy)

2009-12-15

We present preliminary measurements for the development of a large volume silicon detector to detect low energy and low rate energy depositions. The tested detector is a one cm-thick silicon PIN diode with an active volume of 31 cm{sup 3}, cooled to the liquid helium temperature to obtain depletion from thermally-generated free carriers. A thorough study has been done to show that effects of charge trapping during drift disappears at a bias field value of the order of 100V/cm.

Impurities of oxygen in silicon

International Nuclear Information System (INIS)

Gomes, V.M.S.

1985-01-01

The electronic structure of oxygen complex defects in silicon, using molecular cluster model with saturation by watson sphere into the formalism of Xα multiple scattering method is studied. A systematic study of the simulation of perfect silicon crystal and an analysis of the increasing of atom number in the clusters are done to choose the suitable cluster for the calculations. The divacancy in three charge states (Si:V 2 + , Si:V 2 0 , Si:V 2 - ), of the oxygen pair (Si:O 2 ) and the oxygen-vacancy pair (Si:O.V) neighbours in the silicon lattice, is studied. Distortions for the symmetry were included in the Si:V 2 + and Si:O 2 systems. The behavior of defect levels related to the cluster size of Si:V 2 0 and Si:O 2 systems, the insulated oxygen impurity of silicon in interstitial position (Si:O i ), and the complexes involving four oxygen atoms are analysed. (M.C.K.) [pt

Numerical studies on a plasmonic temperature nanosensor based on a metal-insulator-metal ring resonator structure for optical integrated circuit applications

Science.gov (United States)

Al-mahmod, Md. Jubayer; Hyder, Rakib; Islam, Md Zahurul

2017-07-01

A nanosensor, based on a metal-insulator-metal (MIM) plasmonic ring resonator, is proposed for potential on-chip temperature sensing and its performance is evaluated numerically. The sensor components can be fabricated by using planar processes on a silicon substrate, making its manufacturing compatible to planar electronic fabrication technology. The sensor, constructed using silver as the metal rings and a thermo-optic liquid ethanol film between the metal layers, is capable of sensing temperature with outstanding optical sensitivity, as high as -0.53 nm/°C. The resonance wavelength is found to be highly sensitive to the refractive index of the liquid dielectric film. The resonance peak can be tuned according to the requirement of intended application by changing the radii of the ring resonator geometries in the design phase. The compact size, planar and silicon-based design, and very high resolutions- these characteristics are expected to make this sensor technology a preferred choice for lab-on-a-chip applications, as compared to other contemporary sensors.

A data acquisition system for silicon microstrip detectors

International Nuclear Information System (INIS)

Adriani, O.; Civinini, C.; D'Alessandro, R.; Meschini, M.; Pieri, M.; Castellini, G.

1998-01-01

Following initial work on the readout of the L3 silicon microvertex detector, the authors have developed a complete data acquisition system for silicon microstrip detectors for use both in their home institute and at the various test beam facilities at the CERN laboratory. The system uses extensive decoupling schemes allowing a fully floating connection to the detector. This feature has many advantages especially in the readout of the latest double-sided silicon microstrip detectors

Development and application of nuclear radiation detector made from high resistivity silicon and compound semiconductor

International Nuclear Information System (INIS)

Ding Honglin; Zhang Xiufeng; Zhang Wanchang; Li Jiang

1995-11-01

The development of high resistivity silicon detectors and compound semiconductor detectors as well as their application in nuclear medicine are described. It emphasizes on several key techniques in fabricating detectors in order to meet their application in nuclear medicine. As for a high resistivity silicon detector, its counting rate to 125 I 28.5 keV X-ray has to be improved. So employing a conic mesa structure can increase the thickness of samples, and can raise the electric field of collecting charges under the same bias voltage. As for a GaAs detector, its performance of collecting charges has to be improved. So the thicknesses of GaAs samples are decreased and proper thermal treatment to make Ni-Ge-Au ohmic contacts are employed. Applying a suitable reverse bias voltage can obtain a fully depleted detector, and can obtain a lower forward turn-on voltage and a thinner weak electric field region. After resolving these key techniques, the performance of GaAs detectors has been distinctly improved. The count rate to 125 I X-ray has increased by three or five times under the same testing condition and background circumstance (2 refs., 8 figs., 3 tabs.)

On the improvement of mechanical properties of monolithic silica aerogels (for transparent insulating material); Silica aerogel (tomei dannetsu zairyo) kyodo no kaizen ni tsuite

Energy Technology Data Exchange (ETDEWEB)

Tajiri, K; Igarashi, K; Tanemura, S [National Industrial Research Institute of Nagoya, Nagoya (Japan)

1997-11-25

Study was made on improvement of the strength of silica aerogel as transparent insulating material. Silica aerogel is a low-density porous material with high heat insulation and transparency. To develop a insulating material with high transparency, monolithic silica aerogel was studied. For direct use of it for windows, its strength improvement was attempted. The aerogel was prepared by supercritical drying (alcohol or CO2) of silica wet gel obtained by hydrolysis and condensation of silicon alkoxide solution. To prepare the aerogel bonded on plate glass for strength improvement, the aerogel was bonded to alkoxide by exposing active silanol radical through F-etching of plate glass surface. However, to obtain the practical large-area bonded aerogel, shrinkage control of the aerogel in supercritical drying was necessary. Addition of Laponite into a silica network for strength improvement by polymer increased the bending strength by 50%. Although some reduction of its transparency was observed because of clouding, its heat insulation was stable. Further strength improvement is necessary for its practical use. 5 figs., 1 tab.

High Performance Slab-on-Grade Foundation Insulation Retrofits

Energy Technology Data Exchange (ETDEWEB)

Goldberg, Louise F. [NorthernSTAR, St. Paul, MN (United States); Mosiman, Garrett E. [NorthernSTAR, St. Paul, MN (United States)

2015-09-01

?A more accurate assessment of SOG foundation insulation energy savings than traditionally possible is now feasible. This has been enabled by advances in whole building energy simulation with 3-dimensional foundation modelling integration at each time step together with an experimental measurement of the site energy savings of SOG foundation insulation. Ten SOG insulation strategies were evaluated on a test building to identify an optimum retrofit insulation strategy in a zone 6 climate (Minneapolis, MN). The optimum insulation strategy in terms of energy savings and cost effectiveness consisted of two components: (a) R-20 XPS insulation above grade, and, (b) R-20 insulation at grade (comprising an outer layer of R-10 insulation and an interior layer of R-12 poured polyurethane insulation) tapering to R-10 XPS insulation at half the below-grade wall height (the lower half of the stem wall was uninsulated). The optimum insulation strategy was applied to single and multi-family residential buildings in climate zone 4 - 7. The highest site energy savings of 5% was realized for a single family home in Duluth, MN, and the lowest savings of 1.4 % for a 4-unit townhouse in Richmond, VA. SOG foundation insulation retrofit simple paybacks ranged from 18 to 47 years. There are other benefits of SOG foundation insulation resulting from the increase in the slab surface temperatures. These include increased occupant thermal comfort, and a decrease in slab surface condensation particularly around the slab perimeter.

Silicon epitaxy on textured double layer porous silicon by LPCVD

International Nuclear Information System (INIS)

Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

2010-01-01

Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

Evaluation of the high-voltage high-frequency transformer insulating materials for satellites

International Nuclear Information System (INIS)

Kurita, Hiroshi; Hasegawa, Taketoshi; Hirasawa, Eiichi; Gonai, Toshio; Ohsuga, Hiroyuki.

1987-01-01

Environment resistance evaluation was made of the insulating materials of impregnated injection type for high-voltage high-frequency transformers mounted in satellites. (1) The stress occurring in the impregnated injection type resin is small in silicon resin and urethane resin and large in epoxy resin. (2) The dielectric characteristic at high frequency is good in silicone resin. In epoxy resin, when the transformer is operated at high temperature, its thermal runaway may take place. (3) The radiation deterioration at 1 Mrad - 10 Mrad is slight in urethane resin. (4) The degassing is not good in silicone resin. (5) The adhesive power is good in urethane resin. (6) From the above results, in silicone resin there is problem in degassing and adhesive power. In epoxy resin there is problem in stress and dielectric characteristic. (Mori, K.)

Effects of Interfacial Charge Depletion in Organic Thin-Film Transistors with Polymeric Dielectrics on Electrical Stability

Directory of Open Access Journals (Sweden)

Jaehoon Park

2010-06-01

Full Text Available We investigated the electrical stabilities of two types of pentacene-based organic thin-film transistors (OTFTs with two different polymeric dielectrics: polystyrene (PS and poly(4-vinyl phenol (PVP, in terms of the interfacial charge depletion. Under a short-term bias stress condition, the OTFT with the PVP layer showed a substantial increase in the drain current and a positive shift of the threshold voltage, while the PS layer case exhibited no change. Furthermore, a significant increase in the off-state current was observed in the OTFT with the PVP layer which has a hydroxyl group. In the presence of the interfacial hydroxyl group in PVP, the holes are not fully depleted during repetitive operation of the OTFT with the PVP layer and a large positive gate voltage in the off-state regime is needed to effectively refresh the electrical characteristics. It is suggested that the depletion-limited holes at the interface, i.e., interfacial charge depletion, between the PVP layer and the pentacene layer play a critical role on the electrical stability during operation of the OTFT.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

Science.gov (United States)

Wang, Chong; Simoen, Eddy; Zhao, Ming; Li, Wei

2017-10-01

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p- substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p- and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Growing and testing mycelium bricks as building insulation materials

Science.gov (United States)

Xing, Yangang; Brewer, Matthew; El-Gharabawy, Hoda; Griffith, Gareth; Jones, Phil

2018-02-01

In order to improve energy performance of buildings, insulation materials (such as mineral glass and rock wools, or fossil fuel-based plastic foams) are being used in increasing quantities, which may lead to potential problem with materials depletions and landfill disposal. One sustainable solution suggested is the use of bio-based, biodegradable materials. A number of attempts have been made to develop biomaterials, such as sheep wood, hemcrete or recycled papers. In this paper, a novel type of bio insulation materials - mycelium is examined. The aim is to produce mycelium materials that could be used as insulations. The bio-based material was required to have properties that matched existing alternatives, such as expanded polystyrene, in terms of physical and mechanical characteristics but with an enhanced level of biodegradability. The testing data showed mycelium bricks exhibited good thermal performance. Future work is planned to improve growing process and thermal performance of the mycelium bricks.

Strong quantum-confined stark effect in germanium quantum-well structures on silicon

International Nuclear Information System (INIS)

Kuo, Y.; Lee, Y. K.; Gei, Y.; Ren, S; Roth, J. E.; Miller, D. A.; Harris, J. S.

2006-01-01

Silicon is the dominant semiconductor for electronics, but there is now a growing need to integrate such component with optoelectronics for telecommunications and computer interconnections. Silicon-based optical modulators have recently been successfully demonstrated but because the light modulation mechanisms in silicon are relatively weak, long (for example, several millimeters) devices or sophisticated high-quality-factor resonators have been necessary. Thin quantum-well structures made from III-V semiconductors such as GaAs, InP and their alloys exhibit the much stronger Quantum-Confined Stark Effect (QCSE) mechanism, which allows modulator structures with only micrometers of optical path length. Such III-V materials are unfortunately difficult to integrate with silicon electronic devices. Germanium is routinely integrated with silicon in electronics, but previous silicon-germanium structures have also not shown strong modulation effects. Here we report the discovery of the QCSE, at room temperature, in thin germanium quantum-well structures grown on silicon. The QCSE here has strengths comparable to that in III-V materials. Its clarity and strength are particularly surprising because germanium is an indirect gap semiconductor, such semiconductors often display much weak optical effects than direct gap materials (such as the III-V materials typically used for optoelectronics). This discovery is very promising for small, high-speed, low-power optical output devices fully compatible with silicon electronics manufacture. (author)

Modeling charge collection efficiency degradation in partially depleted GaAs photodiodes using the 1- and 2-carrier Hecht equations

International Nuclear Information System (INIS)

Auden, E.C.; Vizkelethy, G.; Serkland, D.K.; Bossert, D.J.; Doyle, B.L.

2017-01-01

The Hecht equation can be used to model the nonlinear degradation of charge collection efficiency (CCE) in response to radiation-induced displacement damage in both fully and partially depleted GaAs photodiodes. CCE degradation is measured for laser-generated photocurrent as a function of fluence and bias in Al_0_._3Ga_0_._7As/GaAs/Al_0_._2_5Ga_0_._7_5As p-i-n photodiodes which have been irradiated with 12 MeV C and 7.5 MeV Si ions. CCE is observed to degrade more rapidly with fluence in partially depleted photodiodes than in fully depleted photodiodes. When the intrinsic GaAs layer is fully depleted, the 2-carrier Hecht equation describes CCE degradation as photogenerated electrons and holes recombine at defect sites created by radiation damage in the depletion region. If the GaAs layer is partially depleted, CCE degradation is more appropriately modeled as the sum of the 2-carrier Hecht equation applied to electrons and holes generated within the depletion region and the 1-carrier Hecht equation applied to minority carriers that diffuse from the field-free (non-depleted) region into the depletion region. Enhanced CCE degradation is attributed to holes that recombine within the field-free region of the partially depleted intrinsic GaAs layer before they can diffuse into the depletion region.

Modeling charge collection efficiency degradation in partially depleted GaAs photodiodes using the 1- and 2-carrier Hecht equations

Energy Technology Data Exchange (ETDEWEB)

Auden, E.C., E-mail: eauden@sandia.gov; Vizkelethy, G.; Serkland, D.K.; Bossert, D.J.; Doyle, B.L.

2017-05-15

The Hecht equation can be used to model the nonlinear degradation of charge collection efficiency (CCE) in response to radiation-induced displacement damage in both fully and partially depleted GaAs photodiodes. CCE degradation is measured for laser-generated photocurrent as a function of fluence and bias in Al{sub 0.3}Ga{sub 0.7}As/GaAs/Al{sub 0.25}Ga{sub 0.75}As p-i-n photodiodes which have been irradiated with 12 MeV C and 7.5 MeV Si ions. CCE is observed to degrade more rapidly with fluence in partially depleted photodiodes than in fully depleted photodiodes. When the intrinsic GaAs layer is fully depleted, the 2-carrier Hecht equation describes CCE degradation as photogenerated electrons and holes recombine at defect sites created by radiation damage in the depletion region. If the GaAs layer is partially depleted, CCE degradation is more appropriately modeled as the sum of the 2-carrier Hecht equation applied to electrons and holes generated within the depletion region and the 1-carrier Hecht equation applied to minority carriers that diffuse from the field-free (non-depleted) region into the depletion region. Enhanced CCE degradation is attributed to holes that recombine within the field-free region of the partially depleted intrinsic GaAs layer before they can diffuse into the depletion region.

Flat-top passband filter based on parallel-coupled double microring resonators in silicon

Science.gov (United States)

Huang, Qingzhong; Xiao, Xi; Li, Yuntao; Li, Zhiyong; Yu, Yude; Yu, Jinzhong

2009-08-01

Optical filters with box-like response were designed and realized based on parallel-coupled double microrings in silicon-on-insulator. The properties of this design are simulated, considering the impact of the center-to-center distance of two rings, and coupling efficiency. Flat-top passband in the drop channel of the fabricated device was demonstrated with a 1dB bandwidth of 0.82nm, a 1dB/10dB bandwidth ratio of 0.51, an out of band rejection ratio of 14.6dB, as well as a free spectrum range of 13.6nm.

Research of mechanical and void properties of composite insulation for superconducting busbar

Energy Technology Data Exchange (ETDEWEB)

Huang, Xiongyi, E-mail: huangxy@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei 230031 (China); Li, Guoliang [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei 230031 (China); Clayton, Nicholas [ITER IO, Superconductor Systems & Auxiliaries Section, 13067 St Paul Lez Durance Cedex (France); Lu, Kun; Wang, Chunyu; Wang, Chao; Dai, Zhiheng [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei 230031 (China); Gung, Chen-yu; Devred, Arnaud [ITER IO, Superconductor Systems & Auxiliaries Section, 13067 St Paul Lez Durance Cedex (France); Song, Yuntao; Fang, Linlin [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei 230031 (China)

2017-01-15

Highlights: • Two curing methods for the pre-preg on the superconducting busbar are researched. • Vaccum bag and silicone rubber is used for pre-preg curing as complement of VPI in fusion filed. • The results of mechanical properties and void content is described and discussed. - Abstract: Pre-preg material has been widely-used in the industry of the aerospace, the wind power, which has many advantages on manufacture process, and can be chosen as an effective complementary insulation method for the Wet-winding and Vacuum Pressure Impregnation technology in the field of superconducting fusion magnets. ASIPP undertaken many engineering tasks on the superconducting coil and busbar design and manufacture for the large fusion device, the pre-preg material and the relevant curing technology were researched as a new method for the high voltage potential components in ITER Feeders, such as the busbars and current leads. Two types of Chinese industrial glass fiber pre-preg insulation composite material were studied and pre-qualified using vacuum bag and silicone rubber assistance technique in ASIPP. The mechanical properties including the ILSS and UTS at 77 K, and void content of this composites were measured and discussed in this paper in detail.

Note: A silicon-on-insulator microelectromechanical systems probe scanner for on-chip atomic force microscopy

Energy Technology Data Exchange (ETDEWEB)

Fowler, Anthony G.; Maroufi, Mohammad; Moheimani, S. O. Reza, E-mail: Reza.Moheimani@newcastle.edu.au [School of Electrical Engineering and Computer Science, University of Newcastle, Callaghan, NSW 2308 (Australia)

2015-04-15

A new microelectromechanical systems-based 2-degree-of-freedom (DoF) scanner with an integrated cantilever for on-chip atomic force microscopy (AFM) is presented. The silicon cantilever features a layer of piezoelectric material to facilitate its use for tapping mode AFM and enable simultaneous deflection sensing. Electrostatic actuators and electrothermal sensors are used to accurately position the cantilever within the x-y plane. Experimental testing shows that the cantilever is able to be scanned over a 10 μm × 10 μm window and that the cantilever achieves a peak-to-peak deflection greater than 400 nm when excited at its resonance frequency of approximately 62 kHz.

Second-harmonic generation in substoichiometric silicon nitride layers

Science.gov (United States)

Pecora, Emanuele; Capretti, Antonio; Miano, Giovanni; Dal Negro, Luca

2013-03-01

Harmonic generation in optical circuits offers the possibility to integrate wavelength converters, light amplifiers, lasers, and multiple optical signal processing devices with electronic components. Bulk silicon has a negligible second-order nonlinear optical susceptibility owing to its crystal centrosymmetry. Silicon nitride has its place in the microelectronic industry as an insulator and chemical barrier. In this work, we propose to take advantage of silicon excess in silicon nitride to increase the Second Harmonic Generation (SHG) efficiency. Thin films have been grown by reactive magnetron sputtering and their nonlinear optical properties have been studied by femtosecond pumping over a wide range of excitation wavelengths, silicon nitride stoichiometry and thermal processes. We demonstrate SHG in the visible range (375 - 450 nm) using a tunable 150 fs Ti:sapphire laser, and we optimize the SH emission at a silicon excess of 46 at.% demonstrating a maximum SHG efficiency of 4x10-6 in optimized films. Polarization properties, generation efficiency, and the second order nonlinear optical susceptibility are measured for all the investigated samples and discussed in terms of an effective theoretical model. Our findings show that the large nonlinear optical response demonstrated in optimized Si-rich silicon nitride materials can be utilized for the engineering of nonlinear optical functions and devices on a Si chip.

Test of the TRAPPISTe monolithic detector system

Science.gov (United States)

Soung Yee, L.; Álvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

2013-12-01

A monolithic pixel detector named TRAPPISTe-2 has been developed in Silicon-on-Insulator (SOI) technology. A p-n junction is implanted in the bottom handle wafer and connected to readout electronics integrated in the top active layer. The two parts are insulated from each other by a buried oxide layer resulting in a monolithic detector. Two small pixel matrices have been fabricated: one containing a 3-transistor readout and a second containing a charge sensitive amplifier readout. These two readout structures have been characterized and the pixel matrices were tested with an infrared laser source. The readout circuits are adversely affected by the backgate effect, which limits the voltage that can be applied to the metal back plane to deplete the sensor, thus narrowing the depletion width of the sensor. Despite the low depletion voltages, the integrated pixel matrices were able to respond to and track a laser source.

An electrically reprogrammable 1024 bits MNOS ROM using MNOS-SOS e/d technology

International Nuclear Information System (INIS)

Mackowiak, E.; Le Goascoz, V.

1976-01-01

A 1024 bits fully decoded electrically writable and erasable non volatile ROM is described. Memory cells and peripheral circuits are made using P channel silicon on sapphire enhancement depletion technology [fr

Quality assurance and irradiation studies on CMS silicon strip sensors

CERN Document Server

Furgeri, Alexander

The high luminosity at the Large Hadron Collider at the European Particle Physics Laboratory CERN in Geneva causes a harsh radiation environment for the detectors. The most inner layers of the tracker are irradiated to an equivalent fluence of 1.6e14 1MeV-neutrons per cmˆ2. The radiation causes damage in the silicon lattice of the sensors. This increases the leakage current and changes the full depletion voltage. Both of these parameters are after irradiation neither stable with time nor with temperatures above 0oC. This thesis presents the changes of the leakage currents, the full depletion voltages, and all strip parameters of the sensors after proton and neutron irradiation. After irradiation annealing studies have been carried out. All observed effects are used to simulate the evolution of full depletion voltage for different annealing times and annealing temperatures in order to keep the power consumption as low as possible. From the observed radiation damage and annealing effects the sensors of the tra...

Nonlinear silicon photonics

Science.gov (United States)

Tsia, Kevin K.; Jalali, Bahram

2010-05-01

An intriguing optical property of silicon is that it exhibits a large third-order optical nonlinearity, with orders-ofmagnitude larger than that of silica glass in the telecommunication band. This allows efficient nonlinear optical interaction at relatively low power levels in a small footprint. Indeed, we have witnessed a stunning progress in harnessing the Raman and Kerr effects in silicon as the mechanisms for enabling chip-scale optical amplification, lasing, and wavelength conversion - functions that until recently were perceived to be beyond the reach of silicon. With all the continuous efforts developing novel techniques, nonlinear silicon photonics is expected to be able to reach even beyond the prior achievements. Instead of providing a comprehensive overview of this field, this manuscript highlights a number of new branches of nonlinear silicon photonics, which have not been fully recognized in the past. In particular, they are two-photon photovoltaic effect, mid-wave infrared (MWIR) silicon photonics, broadband Raman effects, inverse Raman scattering, and periodically-poled silicon (PePSi). These novel effects and techniques could create a new paradigm for silicon photonics and extend its utility beyond the traditionally anticipated applications.

Effect of Sweating on Insulation of Footwear.

Science.gov (United States)

Kuklane, Kalev; Holmér, Ingvar

1998-01-01

The study aimed to find out the influence of sweating on footwear insulation with a thermal foot model. Simultaneously, the influence of applied weight (35 kg), sock, and steel toe cap were studied. Water to 3 sweat glands was supplied with a pump at the rate of 10 g/hr in total. Four models of boots with steel toe caps were tested. The same models were manufactured also without steel toe. Sweating reduced footwear insulation 19-25% (30-37% in toes). During static conditions, only a minimal amount of sweat evaporated from boots. Weight affected sole insulation: Reduction depended on compressibility of sole material. The influence of steel toe varied with insulation. The method of thermal foot model appears to be a practical tool for footwear evaluation.

Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

Directory of Open Access Journals (Sweden)

Jia Ge

2014-01-01

Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.