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Sample records for front-end readout electronics

  1. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  2. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  3. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  4. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  5. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  6. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Ye, J; The ATLAS collaboration

    2010-01-01

    Optical data links are used in detector front-end electronics readout systems of experiments in the Tevatron and the LHC. Optical links in high energy particle physics experiments usually have special requirements such as radiation tolerance, ultra high reliability and low power dissipation. These requirements are often not met by commercial components which are designed for applications in non-radiation, accessible (for maintenance) environment, and for multi-vendor systems so the parts must comply with certain standards. Future HEP experiments such as the upgrades for the sLHC call for optical links with ultra high data bandwidth, higher radiation tolerance and ultra low power dissipation. To meet these challenges and in particular those in the upgrade for the ATLAS Liquid Argon Calorimeter readout that calls for an optical link system of 100 Gbps for each front-end board, we adopted a full custom front-end electronics system design based on application specific integrated circuits. Reported here are the de...

  7. Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

    Science.gov (United States)

    Kleczek, Rafal

    2016-12-01

    The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

  8. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  9. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  10. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  11. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  12. A front-end readout Detector Board for the OpenPET electronics system

    Science.gov (United States)

    Choong, W.-S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C. Q.; Wu, J.-Y.

    2015-08-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ``time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.

  13. Ionization Readout Electronics for SuperCDMS SNOLAB Employing a HEMT Front-End

    Science.gov (United States)

    Partridge, R.

    2014-09-01

    The SuperCDMS SNOLAB experiment seeks to deploy 200 kg of cryogenic Ge detectors employing phonon and ionization readout to identify dark matter interactions. One of the design challenges for the experiment is to provide amplification of the high impedance ionization signal while minimizing power dissipation and noise. This paper describes the design and expected performance of the ionization readout being developed for an engineering model of the SuperCDMS SNOLAB Ge Tower System. The readout features the use of a low-noise HEMT front end transistor operating at 4 K to achieve a power dissipation of 100 W per channel, local grounding to minimize noise injection, and biasing circuitry that allows precise control of the HEMT operating point.

  14. Irradiation Tests of the Pixel Front-End Readout Electronics for the ALICE Experiment at LHC

    CERN Document Server

    Riggi, F; Barbera, R; Palmeri, A; Pappalardo, G S; Di Liberto, S; Meddi, F; Cavagnoli, A; Morando, M; Scarlassara, F; Segato, G F; Soramel, F; Vannucci, Luigi

    2002-01-01

    The problem of radiation damage for the electronics of the pixel detectors in the Inner Tracking System of the ALICE experiment is discussed. Simulations allowed to estimate the cumulated doses andparticle fluences during a ten year operational period. Several irradiation tests have been carried out on the various prototypes of the readout chips. The results obtained so far point out that the recent prototypes will retain their functionality up to doses and neutron fluences well above those expected in ALICE.

  15. Cold front-end electronics and Ethernet-based DAQ systems for large LAr TPC readout

    CERN Document Server

    D.Autiero,; B.Carlus,; Y.Declais,; S.Gardien,; C.Girerd,; J.Marteau; H.Mathez

    2010-01-01

    Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detectors implies severe constraints on their readout and DAQ system. We are carrying on a R&D in electronics on a complete readout chain including an ASIC located close to the collecting planes in the argon gas phase and a DAQ system based on smart Ethernet sensors implemented in a µTCA standard. The choice of the latter standard is motivated by the similarity in the constraints with those existing in Network Telecommunication Industry. We also developed a synchronization scheme developed from the IEEE1588 standard integrated by the use of the recovered clock from the Gigabit link

  16. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  17. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    CERN Document Server

    Bourrion, O; Grignon, C; Richer, J P; Guillaudin, O; Mayet, F; Billard, J; Santos, D

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i.e. decoded coordinates of hit tracks and corresponding energy measurements. The electronic designs, acquisition software and the results obtained are presented.

  18. FAZIA front-end electronics

    OpenAIRE

    Salomon F.; Edelbruck P.; Brulin G.; Boiano A.; Tortone G.; Ordine A.; Bini M.; Barlini S.; Valdré S.

    2015-01-01

    FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  19. FAZIA front-end electronics

    Directory of Open Access Journals (Sweden)

    Salomon F.

    2015-01-01

    Full Text Available FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  20. SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    Science.gov (United States)

    Bouchel, M.; Callier, S.; Dulucq, F.; Fleury, J.; Jaeger, J.-J.; de La Taille, C.; Martin-Chassard, G.; Raux, L.

    2011-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

  1. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  2. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  3. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  4. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  5. Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

    CERN Document Server

    AUTHOR|(CDS)2068589; Rohrich, Dieter

    2008-01-01

    The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

  6. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  7. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  8. SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Callier, S.; Fleury, J.; Dulucq, F.; De la Taille, C.; Chassard, G. Martin; Raux, L.; Seguin-Moreau, N.

    2013-01-01

    For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

  9. The next generation CBM MVD front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Wiebusch, Michael; Michel, Jan; Klaus, Philipp; Stroth, Joachim [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    The Micro Vertex Detector (MVD) for the CBM experiment is a highly granular precision tracking device. Due to the ambitious requirements regarding spatial resolution, radiation hardness, read-out speed and material budget, monolithic active pixel sensors (MAPS) are the most suited detector technology for this purpose. A full read-out chain for these sensors was designed and prototyped, comprising a multi-purpose FPGA platform and specialized front-end electronics. During the last year an updated version of the front-end electronics was produced and successfully commissioned. The current front-end electronics incorporate additional configuration and monitoring capabilities which shall be used to optimize the concept of biasing and routing critical analog signals to the sensor. Tests regarding these issues are ongoing. Recent efforts aim at building a quarter of an MVD station with more than a dozen individual MAPS sensors. This requires the adaption of the front-end electronics to the spacial constraints of the set-up. Also the schematics have to be streamlined based on the insights from the abovementioned tests. This contribution presents the outcomes of the adaption and optimization procedures.

  10. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  11. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  12. Readout Control Specifications for the Front-End and Back-End of the LHCb Upgrade

    CERN Document Server

    Alessio, F

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system [1] in order to run at between five and ten times the initial design luminosity. The various sub-systems in the readout architecture will need to be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. The development of a new readout control system for the upgraded LHCb readout system was investigated already in 2008 [2]. This work has evolved into a detailed system-level specification of the entire timing and readout control system [3]. In this paper, we specify in detail the functionalities that must be supported by the Front-End and the Back-End electronics to comply with the timing requirements and the readout scheme, and the necessary control and monitoring capabilities in order to validate, commission and operate the upgraded experiment efficiently and with sufficient flexibility. The document focuses entirely on the readout control aspects of the FE and BE, and the ECS inter...

  13. Front-end electronics and trigger systems - status and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-08-21

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described.

  14. Front-End Electronics for the Array Readout of a Microwave Kinetic Inductance Detector Towards Observation of Cosmic Microwave Background Polarization

    Science.gov (United States)

    Ishitsuka, H.; Ikeno, M.; Oguri, S.; Tajima, O.; Tomita, N.; Uchida, T.

    2016-07-01

    Precise measurements of polarization patterns in cosmic microwave background (CMB) provide deep knowledge about the begin of the Universe. The GroundBIRD experiment aims to measure the CMB polarization by using microwave kinetic inductance detector (MKID) arrays. The MKID is suited to multiplexing. One of our requirements is a MUX factor (the number of readout channels for a single wire pair) of at least 100. If we make frequency combs of the MKIDs with 2-MHz spacing, a bandwidth of 200 MHz satisfies 100 MUX. The analog electronics must consist of an analog-to-digital converter (ADC), digital-to-analog converter (DAC), and local oscillator. We developed our own analog electronics board " RHEA." Two outputs/inputs of DAC/ADC with a 200-MHz clock provide an effective bandwidth of 200 MHz. The RHEA allows us to measure both the amplitude and phase responses of each MKID simultaneously. These data are continuously sampled at a high rate (e.g., 1 kSPS) and with no dead time. We achieved 12 and 14 bits resolution for ADC and DAC, respectively. This corresponds to achieve that our electronics achieved low noise: 1/1000 compared with the detector noise. We also achieved low power consumption compared with that of other electronics development for other experiments. Another important feature is that the board is completely separated from the digital part. Each user can choose their preferred field-programmable array. With the combination of the Kintex-7 evaluation kit from Xilinx, we demonstrated readout of MKID response.

  15. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  16. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  17. Multi-channel front-end board for SiPM readout

    Science.gov (United States)

    Auger, M.; Ereditato, A.; Goeldi, D.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Weber, M. S.

    2016-10-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias for the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The signal-to-noise ratio of 12 is attained for the first photo-electron peak. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  18. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  19. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  20. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  1. FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

    1989-05-01

    The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.

  2. The analog front-end section of the BaBar silicon vertex tracker readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Manfredi, P.F.; Leona, A.; Mandelli, E.; Re, V.; Svelto, F. [Pavia Univ. (Italy). Dipartimento di Elettronica]|[INFN, Sezione di Pavia, Via Bassi 6, 27100 Pavia (Italy); Kipnis, I.; Luo, L.; Momayezi, M.; Nyman, M.; Pedrali-Noy, M.; Roe, N. [E.O. Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    1998-02-01

    This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip. (orig.). 6 refs.

  3. A Time-Based Front End Readout System for PET & CT

    CERN Document Server

    Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

    2007-01-01

    In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

  4. Development of ATLAS Liquid Argon Calorimeter front-end electronics for the HL-LHC

    Science.gov (United States)

    Liu, T.

    2017-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5–7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter cells at 40–80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented in this paper.

  5. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    Liu, Tiankuan; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  6. Passive front-ends for wideband millimeter wave electronic warfare

    Science.gov (United States)

    Jastram, Nathan Joseph

    This thesis presents the analysis, design and measurements of novel passive front ends of interest to millimeter wave electronic warfare systems. However, emerging threats in the millimeter waves (18 GHz and above) has led to a push for new systems capable of addressing these threats. At these frequencies, traditional techniques of design and fabrication are challenging due to small size, limited bandwidth and losses. The use of surface micromachining technology for wideband direction finding with multiple element antenna arrays for electronic support is demonstrated. A wideband tapered slot antenna is first designed and measured as an array element for the subsequent arrays. Both 18--36 GHz and 75--110 GHz amplitude only and amplitude/phase two element direction finding front ends are designed and measured. The design of arrays using Butler matrix and Rotman lens beamformers for greater than two element direction finding over W band and beyond using is also presented. The design of a dual polarized high power capable front end for electronic attack over an 18--45 GHz band is presented. To combine two polarizations into the same radiating aperture, an orthomode transducer (OMT) based upon a new double ridge waveguide cross section is developed. To provide greater flexibility in needed performance characteristics, several different turnstile junction matching sections are tested. A modular horn section is proposed to address flexible and ever changing operational requirements, and is designed for performance criteria such as constant gain, beamwidth, etc. A multi-section branch guide coupler and low loss Rotman lens based upon the proposed cross section are also developed. Prototyping methods for the herein designed millimeter wave electronic warfare front ends are investigated. Specifically, both printed circuit board (PCB) prototyping of micromachined systems and 3D printing of conventionally machined horns are presented. A 4--8 GHz two element array with

  7. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  8. New RPC front-end electronics for hades

    CERN Document Server

    Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

    2007-01-01

    Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

  9. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  10. Web-based DAQ systems: connecting the user and electronics front-ends

    Science.gov (United States)

    Lenzi, Thomas

    2016-12-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  11. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement

  12. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-09-02

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  13. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  14. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  15. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  16. System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

    Science.gov (United States)

    Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

    2017-03-01

    New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

  17. Front-end electronics for accurate energy measurement of double beta decays

    Energy Technology Data Exchange (ETDEWEB)

    Gil, A., E-mail: alejandro.gil@ific.uv.es [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Diaz, J.; Gomez-Cadenas, J.J. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Herrero, V. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Rodriguez, J.; Serra, L. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Toledo, J.; Esteve, R.; Monzo, J.M. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Monrabal, F.; Yahlali, N. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain)

    2012-12-11

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-{beta} decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  18. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  19. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  20. Front-End electronics configuration system for CMS

    CERN Document Server

    Gras, P; Funk, W; Gross, L; Vintache, D

    2001-01-01

    The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has bee...

  1. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    Science.gov (United States)

    Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

    1995-02-01

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

  2. A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

    Science.gov (United States)

    Singh, Harjit; Loach, James; Poon, Alan

    2012-10-01

    One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.

  3. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  4. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  5. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Acqua, A.; Hansen, M.; Lofstedt, B.; Vanuxem, J.P. (CERN, Geneva (Switzerland)); Svensson, C.; Yuan, J. (Univ. of Linkoeping (Sweden). Dept. of Physics and Measurement Technology); Hentzell, H. (Univ. of Linkoeping (Sweden). Center for Industrial Microelectronics and Materials Technology); Alippi, C.; Breveglieri, L.; Dadda, L.; Piuri, V.; Salice, F.; Sami, M.; Stefanelli, R. (Sezione INFN, Pavia, Milano (Italy). Dept. di Ellettronica); Cattaneo, P.; Fumagalli, G.; Goggi, V.G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Fisica Nucleare); Brigati, S.; Gatti, U.; Maloberti, F.; Torelli, G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Electronica); Carlson, P.; Fuglesang, C.; Kerek, A. (Manne Siegbahn Inst. of Physics, Stockholm (Sweden)); Appelquist, G.; Berglund, S.; Bohm, C.; Yamdagni, N. (Univ. of Stockholm (Sweden)); Sundblad, R. (SiCon AB, Linkoeping (Sweden))

    1993-08-01

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.

  6. A segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics for a PET scanner

    CERN Document Server

    Chesi, Enrico Guido; Joram, C; Mathot, S; Séguinot, Jacques; Weilhammer, P; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

    2006-01-01

    We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is put on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

  7. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  8. Review of input stages used in front end electronics for particle detectors

    CERN Document Server

    Kaplon, J

    2015-01-01

    In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

  9. Study of the performance of ATLAS prototype detectors using analogue LHC front-end electronics

    CERN Document Server

    Riedler, P; Kaplon, J; Weilhammer, Peter

    2002-01-01

    The silicon strip detectors in the ATLAS experiment at LHC will be exposed to very high hadron fluences. In order to study the radiation damage effects ATLAS prototype detectors and small test detectors were irradiated to a fluence of 3 * 10/sup 14/ 24 GeV protons/cm/sup 2/. After irradiation, the detectors were annealed at 25 degrees C to simulate the damage foreseen after 10 years of ATLAS operation. The detectors were then connected to the SCT32A analogue front-end chips and tested with a /sup 106/Ru source. The performance of the irradiated detectors was compared to non-irradiated detectors from the same batch. The charge collection efficiency is discussed taking into account the electronic response of the readout chip and the ballistic deficit. (10 refs).

  10. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  11. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  12. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  13. An Integrated Front-End Readout And Feature Extraction System for the BaBar Drift Chamber

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jinlong; /Colorado U.

    2006-08-10

    The BABAR experiment has been operating at SLAC's PEP-II asymmetric B-Factory since 1999. The accelerator has achieved more than three times its original design luminosity of 3 x 10{sup 33} cm{sup -2} s{sup -1}, with plans for an additional factor of three in the next two years. To meet the experiment's performance requirements in the face of significantly higher trigger and background rates, the drift chamber's front-end readout system has been redesigned around the Xilinx Spartan 3 FPGA. The new system implements analysis and feature-extraction of digitized waveforms in the front-end, reducing the data bandwidth required by a factor of four.

  14. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  15. Progress on the upgrade of the CMS Hadron Calorimeter Front-End electronics

    Energy Technology Data Exchange (ETDEWEB)

    Anderson, Jake; Whitmore, Juliana; /Fermilab

    2011-11-01

    We present a scheme to upgrade the CMS HCAL front-end electronics in the second long shutdown to upgrade the LHC (LS2), which is expected to occur around 2018. The HCAL electronics upgrade is required to handle the major instantaneous luminosity increase (up to 5 * 10{sup 34} cm{sup -2} s{sup -1}) and an expected integrated luminosity of {approx}3000 fb{sup -1}. A key aspect of the HCAL upgrade is to read out longitudinal segmentation information to improve background rejection, energy resolution, and electron isolation at the L1 trigger. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy. The electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ASIC ADC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design, and improvements in the overall readout architecture. We will report on the progress of the designs for these upgraded systems, along with performance requirements and initial design studies.

  16. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  17. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  18. The front-end electronics of the LSPE-SWIPE experiment

    Science.gov (United States)

    Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

    2016-07-01

    The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

  19. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  20. Front-End electronics development for the new Resistive Plate Chamber detector of HADES

    Science.gov (United States)

    Gil, A.; Belver, D.; Cabanelas, P.; Díaz, J.; Garzón, J. A.; González-Díaz, D.; Koenig, W.; Lange, J. S.; Marín, J.; Montes, N.; Skott, P.; Traxler, M.

    2007-11-01

    In this paper we present the new RPC wall, which is being installed in the HADES detector at Darmstadt GSI. It consists of time-of-flight (TOF) detectors used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The wall will contain 1024 RPC modules, covering an active area of around 7 m2, replacing the old TOFino detector at the low polar angle region. The excellent TOF and good charge resolutions of the new detector will improve the time resolution to values better than 100 ps. The Front-End electronics for the readout of the RPC signals is implemented with two types of boards to satisfy the space constraints: the Daughterboards are small boards that amplify the low level signals from the detector and provide fast discriminators for time of flight measurements, as well as an integrator for charge measurements. The Motherboard provides stable DC voltages and a stable ground, threshold DACs for the discriminators, multiplicity trigger and impedance matched paths for transfer of time window signals that contain information about time and charge. These signals are sent to a custom TDC board that label each event and send data through Ethernet to be conveniently stored.

  1. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  2. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  3. Front-end electronics and data acquisition system for a multi-wire 3D gas tracker

    CERN Document Server

    Lojek, K; Bodek, K; Perkowski, M; Severijns, N

    2015-01-01

    This paper presents the design and implementation of the front-end electronics and the data acquisition (DAQ) system for readout of multi-wire drift chambers (MWDC). Apart of the conventional drift time measurement the system delivers the hit position along the wire utilizing the charge division technique. The system consists of preamplifiers, and analog and digital boards sending data to a back-end computer via an Ethernet interface. The data logging software formats the received data and enables an easy access to the data analysis software. The use of specially designed preamplifiers and peak detectors allows the charge-division readout of the low resistance signal wire. The implication of the charge-division circuitry onto the drift time measurement was studied and the overall performance of the electronic system was evaluated in dedicated off-line tests.

  4. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  5. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  6. Front-end Electronics Test for the LHCb Muon Wire Chambers

    CERN Document Server

    Nobrega, R; Carboni, G; Massafferri, A; Santovetti, E

    2007-01-01

    This document describes the apparatus and procedures implemented to test Multi Wire Proportional Chambers (MWPC) after front-end assembly for the LHCb Muon Detector. Results of measurements of key noise parameters are also described. Given a fully equipped chamber, this system is able to diagnose every channel performing an analysis of front-end output drivers’ response and noise rate versus threshold. Besides, it allows to assess if the noise rate at the experiment threshold region is within appropriate limits. Aiming at an automatic, fast and user-friendly system for mass production tests of MWPC, the project has foreseen as well electronic identification of every chamber and front-end board, and data archiving in such a way to make it available to the Experiment Control System (ECS) while in operation.

  7. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  8. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  9. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    OpenAIRE

    al., H. Albrecht et

    2004-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns...

  10. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  11. A Simplified and Accurate Front-End Electronics Chain for Timing RPCs

    CERN Document Server

    Blanco, A; Fonte, Paulo J R; Ferreira-Marques, R; Gobbi, A; Policarpo, Armando

    2000-01-01

    Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficienciesclose to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possibleapplication in ALICE's T0 counter.(Abstract only available, full text to follow).

  12. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  13. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  14. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  15. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  16. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  17. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226662; The ATLAS collaboration

    2016-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  18. A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

    Science.gov (United States)

    Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

    2016-05-01

    This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

  19. A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Wei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun, E-mail: weitc@nwpu.edu.cn [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Li, Bo; Yang, Lifeng; Xue, Feifei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

    2016-05-11

    This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of −1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm{sup 2}. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

  20. Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

    Energy Technology Data Exchange (ETDEWEB)

    Sahin, Mehmet Oezguer

    2017-04-15

    previous searches with the 8 TeV center-of-mass energy in the single lepton final states is extended to m{sub t} = 675 GeV and m{sub χ{sup 0}} = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

  1. Anode Front-End Electronics for the Cathode Strip Chambers of the CMS Endcap Muon Detector

    CERN Document Server

    Ferguson, Thomas; Vorobev, I; Bondar, Nikolai; Golyash, Alexander; Sedov, Vladislav

    2001-01-01

    The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3 x 2.5 m2) and for the large input capacitance (up to 200 pf). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2 - 3 ns). The del ay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This note presents the anode front-end electro...

  2. A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

    Science.gov (United States)

    Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

    2017-06-01

    A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

  3. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Science.gov (United States)

    Lombigit, L.; Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-01

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  4. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  5. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  6. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  7. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  8. A wide dynamics neutron monitor with BF3 and logarithmic amplifier based front-end electronics

    OpenAIRE

    2010-01-01

    In this paper a wide dynamics neutron monitor based on BF3 neutron detector is described. The detector is used in current mode, and a front-end electronics based on a logarithmic amplifier is used in order to have a measurement capability ranging over many decades. The system has been calibrated at Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamics ranging ov...

  9. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  10. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet...

  11. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicate

  12. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    Science.gov (United States)

    Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

    2008-08-01

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector.

  13. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  14. Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

    Science.gov (United States)

    Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

    2009-05-01

    A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

  15. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  16. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo

    2014-11-21

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  17. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    OpenAIRE

    Födisch, P.; Berthel, M.; Lange, B; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-01-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, ...

  18. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    INSPIRE-00399968

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  19. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  20. FEC-CCS A common Front-End Controller card for the CMS detector electronics

    CERN Document Server

    Kloukinas, Kostas; Drouhin, F; Ljuslin, C; Marchioro, A; Murer, E; Paillard, C; Vlasov, E

    2007-01-01

    The FEC-CCS is a custom made 9U VME64x card for the CMS Off-Detector electronics. The FEC-CCS card is responsible for distributing the fast timing signals and the slow control data, through optical links, to the Front-End system. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS detectors namely the Tracker, ECAL, Preshower, PIXELs, RPCs and TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enable the common utilization by most of the CMS detectors. Results from the integration tests with the detector electronics subsystems and performance measurements will be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.

  1. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  2. Developments for the upgrade of the CMS HCAL front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Baden, D [Univ. of Maryland, College Park, MD 20742 (United States); Frahm, E; Mans, J [Univ. of Minnesota, Minneapolis, MN 55455 (United States); Freeman, J; Grassi, T; Los, S; Shaw, T; Whitmore, J; Zimmerman, T [FERMILAB, Batavia, IL 60510 (United States); Tully, C, E-mail: tullio.grassi@cern.c [Princeton University, Princeton NJ 08544 (United States)

    2010-11-15

    We present a scheme to upgrade the CMS HCAL front-end electronics in 2015-16. The HCAL upgrade is required to handle a major luminosity increase of LHC which is expected for 2017. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy in a harsh environment which is constrained by the existing system. The proposed solutions span from chip level to system level. They include the development of a new ADC ASIC, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design and improvements in the overall architecture.

  3. NOVEL ELECTRONIC TUNER USING VARACTORS FOR TUNABLE RF FRONT-ENDS

    Institute of Scientific and Technical Information of China (English)

    Li Liang; Liu Taijun; Ye Yan; Zhang Haili; Hui Ming; Li Jun; Wen Huafeng

    2013-01-01

    This paper presents a novel electronic tuner with high power handling capability utilizing varactors based on the asymmetric bilateral coupled microstrip transmission line.Through varying the bias voltage of the varactor at the Ultra High Frequency (UHF) band,the performance of the tuner is demonstrated according to simulated and measured results from several cases with the return loss (S11)below-20 dB and the insertion loss (S21) within ±0.5 dB.Compared with tuners using π and T network,electronic tuner of this paper shows superior frequency agility as well as wide impendence coverage.Advanced biasing structure has been developed to improve power handling for high power level applications.It is expected that the novel tuner would be part of intelligent Radio Frequency (RF)front-ends system and cognitive wireless system in the future.

  4. Front-end readout ASIC for charged particle counting with the RADEM instrument on the ESA JUICE mission

    Science.gov (United States)

    Stein, Timo A.; Pâhlsson, Philip; Meier, Dirk; Hasanbegovic, Amir; Otnes Berge, Hans Kristian; Altan, Mehmet Akif; Ackermann, Jörg; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Gheorghe, Codin; Steenari, David; Øya, Petter; Johansen, Tor Magnus; Maehlum, Gunnar

    2016-07-01

    The detector readout for the Radiation-hard Electron Monitor (RADEM) aboard the JUpiter ICy moons Explorer (JUICE) uses a custom-made application-specific integrated circuit (ASIC, model: IDE3466) for the charge signal readout from silicon radiation sensors. RADEM measures the total ionizing dose and dose rate for protons (5 MeV to 250 MeV), electrons (0.3 MeV to 40 MeV) and ions. RADEM has in total three chips of the same design: one chip for the proton and ion detector, one for the electron detector, and one for the directional detector. The ASIC has 36 chargesensitive pre-amplifiers (CSA), 36 counters of 22-bits each, and one analogue output for multiplexing the pulse heights from all channels. The counters count pulses from charged particles in the silicon sensors depending on the charge magnitude and the coincidence trigger pattern from the 36 channels. We have designed the ASIC in 0.35-μm CMOS process and an ASIC wafer lot has been manufactured at AMS. This article presents the ASIC design specifications and design validation results. The preliminary results from tests with bare chips indicate that the design meets the technical requirements.

  5. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  6. ANALOG FRONT-END ELECTRONICS FOR BEAM POSITION MEASUREMENT ON THE BEAM HALO MEASUREMENT

    Energy Technology Data Exchange (ETDEWEB)

    R.B. SHURTER; T.J. COTE; J.D. GILPATRICK

    2001-06-01

    Enhancements have been made to the log-ratio analog front-end electronics based on the Analog Devices 8307 logarithmic amplifier as used on the LEDA accelerator. The dynamic range of greater than 85 dB, has been extended to nearly the full capability of the AD8307 from the previous design of approximately 65 dB through the addition of a 350 MHz band-pass filter, careful use of ground and power plane placement, signal routing, and power supply bypassing. Additionally, selection of high-isolation RF switches (55dB) has been an integral part of a new calibration technique, which is fully described in another paper submitted to this conference. Provision has also been made for insertion of a first-stage low-noise amplifier for using the circuit under low-signal conditions.

  7. ANALOG FRONT-END ELECTRONICS FOR BEAM POSITION MEASUREMENT ON THE BEAM HALO MEASUREMENT

    Energy Technology Data Exchange (ETDEWEB)

    Shurter, R. B. (Robert B.); Cote, T. J. (Thomas J.); Gilpatrick, J. D. (John Douglas)

    2001-01-01

    Enhancements have been made to the log-ratio analog front-end electronics based on the Analog Devices 8307 logarithmic amplifier as used on the LEDA accelerator. The dynamic range of greater than 85 dB, has been extended to nearly the full capability of the AD8307 from the previous design of approximately 65 dB through the addition of a 350 MHz band-pass filter, careful use of ground and power plane placement, signal routing, and power supply bypassing. Additionally, selection of high-isolation RF switches (55dB) has been an integral part of a new calibration technique, which is fully described in another paper submitted to this conference. Provision has also been made for insertion of a first-stage low-noise amplifier for using the circuit under low-signal conditions.

  8. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  9. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  10. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Energy Technology Data Exchange (ETDEWEB)

    Noy, M., E-mail: matthew.noy@cern.ch [CERN, CH-1211 Geneva 23 (Switzerland); Aglieri Rinella, G.; Ceccucci, A. [CERN, CH-1211 Geneva 23 (Switzerland); Dellacasa, G. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Fiorini, M. [CERN, CH-1211 Geneva 23 (Switzerland); Garbolino, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Jarron, P. [CERN, CH-1211 Geneva 23 (Switzerland); INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Kaplon, J.; Kluge, A. [CERN, CH-1211 Geneva 23 (Switzerland); Marchetto, F. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Martin, E. [Universite Catholique de Louvain 1, Place de l' Universite BE-1348 Louvain-la-Neuve (Belgium); Mazza, G.; Martoiu, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Morel, M.; Perktold, L. [CERN, CH-1211 Geneva 23 (Switzerland); Rivetti, A. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Tiuraniemi, S. [CERN, CH-1211 Geneva 23 (Switzerland)

    2011-06-15

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16cm{sup 2} active area made of an assembly of 10 readout ASICs bump bonded to a 200{mu}m thick pixel silicon sensor, comprising 18000 pixels of 300{mu}mx300{mu}m. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5Mhit s{sup -1}mm{sup -2} together with an extreme time resolution of 100ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4ns, with a planar silicon sensor operating up to 300V over depletion. Moreover, the radiation level is severe, 2x10{sup 14}1MeVn{sub eq.}cm{sup -2} per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X{sub 0} to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  11. Characterization of Silicon Detector Readout Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Jones, M. [Purdue U.

    2015-07-22

    Configuration and calibration of the front-end electronics typical of many silicon detector configurations were investigated in a lab activity based on a pair of strip sensors interfaced with FSSR2 read-out chips and an FPGA. This simple hardware configuration, originally developed for a telescope at the Fermilab Test Beam Facility, was used to measure thresholds and noise on individual readout channels and to study the influence that different configurations of the front-end electronics had on the observed levels of noise in the system. An understanding of the calibration and operation of this small detector system provided an opportunity to explore the architecture of larger systems such as those currently in use at LHC experiments.

  12. Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

    Science.gov (United States)

    Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

    2012-07-01

    There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

  13. BPM Analog front-end electronics based on the AD8307 log amplifier

    Science.gov (United States)

    Shurter, R. B.; Gilpatrick, J. D.; Power, J.

    2000-11-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is "detected" by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5 V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  14. FPGA-Based Front-End Electronics for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Dewitt, Don; McDougald, Wendy; Lewellen, Thomas K; Miyaoka, Robert; Hauck, Scott

    2009-02-22

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

  15. BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

    Energy Technology Data Exchange (ETDEWEB)

    R. SHURTER; ET AL

    2000-06-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  16. Digital pulse processing and optimization of the front-end electronics for nuclear instrumentation.

    Science.gov (United States)

    Bobin, C; Bouchard, J; Thiam, C; Ménesguen, Y

    2014-05-01

    This article describes an algorithm developed for the digital processing of signals provided by a high-efficiency well-type NaI(Tl) detector used to apply the 4πγ technique. In order to achieve a low-energy threshold, a new front-end electronics has been specifically designed to optimize the coupling to an analog-to-digital converter (14 bit, 125 MHz) connected to a digital development kit produced by Altera(®). The digital pulse processing is based on an IIR (Infinite Impulse Response) approximation of the Gaussian filter (and its derivatives) that can be applied to the real-time processing of digitized signals. Based on measurements obtained with the photon emissions generated by an (241)Am source, the energy threshold is estimated to be equal to ~2 keV corresponding to the physical threshold of the NaI(Tl) detector. An algorithm developed for a Silicon Drift Detector used for low-energy x-ray spectrometry is also described. In that case, the digital pulse processing is specifically designed for signals provided by a reset-type preamplifier ((55)Fe source).

  17. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

    Energy Technology Data Exchange (ETDEWEB)

    Knopf, Jan

    2009-07-08

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  18. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  19. Silicon Photomultipliers and front-end electronics performance for Cherenkov Telescope Array camera development

    Science.gov (United States)

    Ambrosi, G.; Bissaldi, E.; Giglietto, N.; Giordano, F.; Ionica, M.; Paoletti, R.; Rando, R.; Simone, D.; Vagelli, V.

    2017-02-01

    In the last few years a number of efforts have been undertaken to develop new technology related to Silicon Photomultipliers (SiPMs). These photosensors consist of an array of identical Avalanche Photodiodes operating in Geiger mode and connected in parallel to a single output. The Italian Institute of Nuclear Physics (INFN) is involved in the R&D program Progetto Premiale Telescopi CHErenkov made in Italy (TECHE.it) to develop photosensors for a SiPM based camera that will be part of the Cherenkov Telescope Array (CTA) observatory. In this framework tests are ongoing on innovative devices suitable to detect Cherenkov light in the blue and near-UV wavelength region, the so-called Near Ultra-Violet Silicon Photomultipliers (NUV SiPMs). The tests on photosensors produced by Fondazione Bruno Kessler (FBK) are revealing promising performance: low operating voltage, capability to detect very low intensity light down to a single photon and high Photo Detection Efficiency (PDE) in the range 390-410 nm. In particular the developed device is a High Density NUV-SiPM (NUV-HD SiPM) based on a micro-cell of 30 μm×30 μm and 6 mm×6 mm area. Tests on this detector in single-cell configuration and in a matrix arrangement have been done. At the same time front-end electronics based on the waveform sampling technique optimized for the new NUV-HD SIPMs is under study and development.

  20. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J.A.; Kooijman, P.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  1. Readout electronics for LGAD sensors

    Science.gov (United States)

    Alonso, O.; Franch, N.; Canals, J.; Palacio, F.; López, M.; Vilà, A.; Diéguez, A.; Carulla, M.; Flores, D.; Hidalgo, S.; Merlos, A.; Pellegrini, G.; Quirion, D.

    2017-02-01

    In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

  2. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  3. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Science.gov (United States)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  4. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  5. Super-Altro 16: a Front-End System on Chip for DSP Based Readout of Gaseous Detectors

    CERN Document Server

    Aspell, P.; Franca, H.; Garcia Garcia, E.; Musa, L.

    2013-01-01

    This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4mm2/channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40MHz before providing the digitized signal to the DSP which performs baseline subtraction, signa...

  6. Front-end electronics for CsI based charged particle array for the study of reaction dynamics

    Energy Technology Data Exchange (ETDEWEB)

    Jhingan, Akhil, E-mail: akhil@iuac.res.in [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Sugathan, P. [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Kaur, Gurpreet; Kapoor, K. [Department of Physics, Panjab University, Chandigarh 160014 (India); Saneesh, N.; Banerjee, T. [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Singh, Hardev [Department of Physics, Kurukshetra University, Kurukshetra 136119 (India); Kumar, A.; Behera, B.R. [Department of Physics, Panjab University, Chandigarh 160014 (India); Nayak, B.K. [Nuclear Physics Division, Bhabha Atomic Research Centre, Mumbai 400085 (India)

    2015-06-21

    The characteristics and performance of a new detector system based on CsI(TI) scintillators, and its front-end electronics are presented. The detector system has been developed for the detection of light charged particles to investigate fusion–fission dynamics, and will also serve as ancillary detector for an array of neutron detectors. CsI scintillators are read by photo-diodes. The main feature of the array is its compact and simple high density front-end electronics which includes custom developed low noise charge sensitive preamplifiers (with very low power consumption for operation inside vacuum), NIM differential drivers, and commercially available Mesytec amplifiers with two different time constants for particle identification using a ballistic deficit technique.

  7. Front-end and high-voltage electronics developments for compact, dual ion-electron thermal measurements

    Science.gov (United States)

    Cara, A.; Lavraud, B.; Tap, H.; Ballot, Y.; Aoustin, C.; Chassela, O.; Cadu, A.; Devoto, P.; Fedorov, A.; Rouzaud, J.; Rubiella, J.; Sauvaud, J. A.; Seran, H. C.; Bernal, O.; Payan, D.; Rouzies, C.

    2015-12-01

    The Active Monitor Box of Electrostatic Risks (AMBER) is a double-head thermal electron and ion electrostatic analyzer (~0 - 30 keV) that will be launched onboard the Jason-3 spacecraft in 2015. The new generation AMBRE instrument (AMBER_NG) constitutes a significant new evolution that will be based on a single head with newly developed sub-systems to reduce all instrument resources. We will describe the main front-end and high-voltage electronics developments which are being made to perform such dual ion-electron measurements. The first purpose of AMBER_NG is the monitoring of spacecraft charging and of the plasma populations at the origin of this charging. The design is also appropriate for the study of space plasma processes in the Earth's magnetosphere, as well as at other planets where time resolution may not prevail over mass constraints.

  8. A 4-Channel Waveform Sampling ASIC in 0.13 μm CMOS for front-end Readout of Large-Area Micro-Channel Plate Detectors

    Science.gov (United States)

    Oberla, E.; Grabas, H.; Bogdan, M.; Frisch, H.; Genat, J. F.; Nishimura, K.; Varner, G.; Wong, A.

    We describe here the development of PSEC-3, a custom integrated circuit designed in the IBM-8RF 0.13 μm CMOS process and intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this chip has been designed as a prototype application-specific integrated circuit (ASIC) for the front-end transmission line readout of large-area micro-channel plate photomultiplier tubes (MCP-PMTs). With 4 channels, PSEC-3 has a buffer depth of 256 samples on each channel, a chip-parallel ramp-compare ADC, and a serial data readout that includes the capability for region-of-interest windowing to reduce dead time. Chip calibrations and performance results, including achieved sampling rates of 2.5-17 GSa/s, are reported. Some design issues are identified, in particular the dependence of analog bandwidth on location in the sampling array. The causes have been found and addressed in a subsequent PSEC-4 submission.

  9. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    Energy Technology Data Exchange (ETDEWEB)

    Gómez-Galán, J.A., E-mail: jgalan@uhu.es [Dpto de Ingeniería Electrónica, Sist. Informáticos y Automática, Universidad de Huelva (Spain); Sánchez-Rodríguez, T.; Sánchez-Raya, M.; Martel, I. [Dpto de Ingeniería Electrónica, Sist. Informáticos y Automática, Universidad de Huelva (Spain); López-Martín, A. [Dpto de Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra (Spain); Carvajal, R.G. [Dpto de Ingeniería Electrónica, Universidad de Sevilla (Spain); Ramírez-Angulo, J. [Klipsch School of Electrical Engineering, New Mexico State University (United States)

    2014-06-01

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

  10. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii

    2013-07-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

  11. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  12. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  13. A 130 nm CMOS mixed mode front end readout chip for silicon strip tracking at the future linear collider

    Energy Technology Data Exchange (ETDEWEB)

    Pham, T.H., E-mail: pham@lpnhe.in2p3.f [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Charpy, A.; Ciobanu, C. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Comerma, A. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); David, J.; Dhellot, M. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Dieguez, A.; Gascon, D. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); Genat, J.F.; Savoy Navarro, A.; Sefri, R. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France)

    2010-11-01

    A 130 nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low noise charge amplifier and integration with long pulse shaping, (ii) an eight by eight positions analog sampler for both storing successive events and reconstructing the full pulse shape, and (iii) a sparsifier performing analog sum of three adjacent inputs to decide whether there is signal or not. The whole system is controlled by the digital part, which allows configuring all the reference currents and voltages, drives the control signals to the analog memories, records the timing and channel information and subsequently performs the conversion to digital values of samples. The total surface of the circuit is 10x5 mm{sup 2}, with each analog channel occupying an area of 105x3500 {mu}m{sup 2}, and the remaining space of about 9000x700 {mu}m{sup 2} being filled by the analog channels on the silicon.

  14. The front-end electronics of the Spectrometer Telescope for Imaging X-Rays (STIX) on the ESA Solar Orbiter satellite

    Science.gov (United States)

    Grimm, O.; Bednarzik, M.; Commichau, V.; Graczyk, R.; Gröbelbauer, H. P.; Hurford, G.; Krucker, S.; Limousin, O.; Meuris, A.; Orleański, P.; Przepiórka, A.; Seweryn, K.; Skup, K.; Viertel, G.

    2012-12-01

    Solar Orbiter is an ESA mission to study the heliosphere in proximity to the Sun, scheduled for launch in January 2017. It carries a suite of ten instruments for comprehensive remote-sensing and in-situ measurements. The Spectrometer Telescope for Imaging X-Rays (STIX), one of the remote sensing instruments, images X-rays between 4 and 150keV using an Fourier technique. The angular resolution is 7 arcsec and the spectral resolution 1keV full-width-half-maximum at 6keV. X-ray detection uses pixelized Cadmium Telluride crystals provided by the Paul Scherrer Institute. The crystals are bonded to read-out hybrids developed by CEA Saclay, called Caliste-SO, incorporating a low-noise, low-power analog front-end ASIC IDeF-X HD. The crystals are cooled to -20°C to obtain very low leakage currents of less than 60pA per pixel, the prerequisite for obtaining the required spectral resolution. This article briefly describes the mission goals and then details the front-end electronics design and main challenges, resulting in part from the allocation limit in mass of 7kg and in power of 4W. Emphasis is placed on the design influence of the cooling requirement within the warm environment of a mission approaching the Sun to within the orbit of Mercury. The design for the long-term in-flight energy calibration is also explained.

  15. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland)

    2015-07-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  16. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  17. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  18. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  19. Search for Supersymmetric Top-Quark Partners Using Support Vector Machines and Upgrade of the Hadron Calorimeter Front-End Readout Control System at CMS

    CERN Document Server

    Sahin, Mehmet Ozgur; Schleper, Peter

    2017-01-01

    In this thesis a search for direct pair production of supersymmetric top-quark partners aswell as work on the upgrade of the front-end readout controller of the Hadron Calorimeter(HCAL) of the Compact Muon Solenoid (CMS) experiment are presented.The most appealing extension of the Standard Model (SM) is supersymmetry (SUSY), relating the integer spin (bosons) and half-integer spin elementary particles (fermions). Supersymmetric top-quark partners (t) around and below the TeV energy scale offer a solution to thehierarchy problem. Furthermore, R-parity conserving SUSY models propose a cold dark matter candidate in the form of stable lightest supersymmetric particles, e.g. lightest neutralinos(χ0 ).The analysis performed in this thesis is a search for top-squark pair production in a final state consisting of a single isolated lepton, jets, among which at least one is tagged asbottom-quark jet, and large missing transverse energy at the CMS experiment at the CERNLarge Hadron Collider (LHC) with 8 TeV center-of-...

  20. Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

    Science.gov (United States)

    Liu, Wei; Wei, Tingcun; Li, Bo; Guo, Panjie; Hu, Yongcai

    2015-06-01

    A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um2.

  1. Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Wei, E-mail: liouwei930@sina.com [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun; Li, Bo; Guo, Panjie [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

    2015-06-21

    A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um{sup 2}.

  2. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  3. Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

    CERN Document Server

    Drake, G; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

  4. Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mercado Perez, Jorge

    2008-11-10

    Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

  5. Characterization of a front-end electronics for the monitoring and control of hadrontherapy beams

    Science.gov (United States)

    La Rosa, A.; Donetti, M.; Borri, M.; Rivero, F.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Mazza, G.; Marchetto, F.; Pardo, J.; Pecka, A.; Peroni, C.

    2008-02-01

    An integrated 64-channel device for the read-out of parallel plate pixel and strip ionization detectors has been developed by the INFN and University of Torino. The detectors will be used for the monitoring and control of hadrontherapy beams. The ASIC has been designed in CMOS 0.8 μm technology and it is based on a current-to-frequency converter followed by a synchronous counter. In this paper, we present a detailed characterization of the device done with 113 chips.

  6. Characterization of a front-end electronics for the monitoring and control of hadrontherapy beams

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy)], E-mail: larosa@to.infn.it; Donetti, M. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milan 20123 (Italy); Borri, M.; Rivero, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Attili, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Cirio, R. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Givehchi, N. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Mazza, G.; Marchetto, F.; Pardo, J. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Pecka, A.; Peroni, C. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy)

    2008-02-21

    An integrated 64-channel device for the read-out of parallel plate pixel and strip ionization detectors has been developed by the INFN and University of Torino. The detectors will be used for the monitoring and control of hadrontherapy beams. The ASIC has been designed in CMOS 0.8 {mu}m technology and it is based on a current-to-frequency converter followed by a synchronous counter. In this paper, we present a detailed characterization of the device done with 113 chips.

  7. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  8. The Front-End electronics for the LHCb scintillating fibres detector

    CERN Document Server

    Chanal, Hervé; Pillet, Nicolas

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [ 1 ]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250 m m fibres with an area of 5 6 m 2 . It leads to a total of 500k SiPM channels which need to be read out at 40 MHz. This article gives an overview of the R&D; status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the other side. The PACIFIC chip is a 128-channels ASIC which can be connected to one 1...

  9. LHCb: The Front-End electronics for the LHCb scintillating fibres detector

    CERN Multimedia

    Chanal, H; Pillet, N

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250 $\\mu$m fibres with an area of 5×6 m$^2$. Its lead to a total of 500k SiPM channels which need to will be read out at 40MHz. This talk gives an overview of the R&D status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the other side . The PACIFIC chip is a 128 channel ASIC which can be connected to one 12...

  10. A wide dynamic range BF 3 neutron monitor with front-end electronics based on a logarithmic amplifier

    Science.gov (United States)

    Ferrarini, M.; Varoli, V.; Favalli, A.; Caresana, M.; Pedersen, B.

    2010-02-01

    This paper describes a wide dynamic range neutron monitor based on a BF 3 neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10 6 s -1. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

  11. A wide dynamic range BF{sub 3} neutron monitor with front-end electronics based on a logarithmic amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Ferrarini, M., E-mail: michele.ferrarini@polimi.i [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Fondazione CNAO, via Caminadella 16, 20123 Milano (Italy); Varoli, V. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Favalli, A. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Vatican City State, Holy See) (Italy); Caresana, M. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Pedersen, B. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Italy)

    2010-02-01

    This paper describes a wide dynamic range neutron monitor based on a BF{sub 3} neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10{sup 6} s{sup -1}. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

  12. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  13. Radiation Effects in Front-end Electronics for the ALICE ITS

    CERN Document Server

    Idzik, M; CERN. Geneva

    1996-01-01

    The goal of this paper is to review existing data on the radiation hardness of electronics components and circuits used in high energy physics detectors produced in non radiation-hard technologies. We consider here mainly CMOS technologies, since they are commonly in use and they offer the easiest way to link analog and digital designs. First, we will briefly recall the physical aspects of radiation influence on electronics systems and then we will review current data on radiation measurements of VLSI circuits. We will conclude with some considerations on the implications for the technology choices in the ALICE ITS.

  14. Challenges of front-end and triggering electronics for High Granularity Calorimetry

    CERN Document Server

    Puljak, Ivica

    2017-01-01

    A high granularity calorimeter is presently being designed by the CMS Collaboration to replace the existing endcap detectors. It must be able to cope with the very high collision rates, imposing the development of novel filtering and triggering strategies, as well as with the harsh radiation environment of the high-luminosity LHC. In this paper we present an overview of the full electronics architecture and the performance of prototype components and algorithms.

  15. LHCb Scintillating Fiber detector front end electronics design and quality assurance

    Science.gov (United States)

    Vink, W. E. W.; Pellegrino, A.; Ietswaard, G. C. M.; Verkooijen, J. C.; Carneiro, U.; Massefferi, A.

    2017-03-01

    The on-detector electronics of the LHCb Scintillating Fiber Detector consists of multiple PCBs assembled in a unit called Read Out Box, capable of reading out 2048 channels with an output rate of 70 Gbps. There are three types of boards: PACIFIC, Clusterization and Master Board. The Pacific Boards host PACIFIC ASICs, with pre-amplifier and comparator stages producing two bits of data per channel. A cluster-finding algorithm is then run in an FPGA on the Clusterization Board. The Master Board distributes fast and slow control, and power. We describe the design, production and test of prototype PCBs.

  16. Readout electronic for multichannel detectors

    CERN Document Server

    Kulibaba, V I; Naumov, S V

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

  17. Acoustic backing in 3-D integration of CMUT with front-end electronics.

    Science.gov (United States)

    Berg, Sigrid; Rønnekleiv, Arne

    2012-07-01

    Capacitive micromachined ultrasonic transducers (CMUTs) have shown promising qualities for medical imaging. However, there are still some problems to be investigated, and some challenges to overcome. Acoustic backing is necessary to prevent SAWs excited in the surface of the silicon substrate from affecting the transmit pattern from the array. In addition, echoes resulting from bulk waves in the substrate must be removed. There is growing interest in integrating electronic circuits to do some of the beamforming directly below the transducer array. This may be easier to achieve for CMUTs than for traditional piezoelectric transducers. We will present simulations showing that the thickness of the silicon substrate and thicknesses and acoustic properties of the bonding material must be considered, especially when designing highfrequency transducers. Through simulations, we compare the acoustic properties of 3-D stacks bonded with three different bonding techniques; solid-liquid interdiffusion (SLID) bonding, direct fusion bonding, and anisotropic conductive adhesives (ACA). We look at a CMUT array with a center frequency of 30 MHz and three silicon wafers underneath, having a total silicon thickness of 100 μm. We find that fusion bonding is most beneficial if we want to prevent surface waves from damaging the array response, but SLID and ACA are also promising if bonding layer thicknesses can be reduced.

  18. Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics

    Directory of Open Access Journals (Sweden)

    Abdelghani Dendouga

    2014-01-01

    Full Text Available The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor- based circuit applications. Six performances are considered in this study, direct current (DC gain, unity-gain bandwidth (GBW, phase margin (PM, power consumption (P, area (A, and slew rate (SR. We used the Matlab optimization toolbox to implement the program. Also, by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA is simulated by using Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company RF 0.18 μm CMOS technology. A good agreement is observed between the program optimization and electric simulation.

  19. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  20. Tissue Banking, Bioinformatics, and Electronic Medical Records: The Front-End Requirements for Personalized Medicine

    Science.gov (United States)

    Suh, K. Stephen; Sarojini, Sreeja; Youssif, Maher; Nalley, Kip; Milinovikj, Natasha; Elloumi, Fathi; Russell, Steven; Pecora, Andrew; Schecter, Elyssa; Goy, Andre

    2013-01-01

    Personalized medicine promises patient-tailored treatments that enhance patient care and decrease overall treatment costs by focusing on genetics and “-omics” data obtained from patient biospecimens and records to guide therapy choices that generate good clinical outcomes. The approach relies on diagnostic and prognostic use of novel biomarkers discovered through combinations of tissue banking, bioinformatics, and electronic medical records (EMRs). The analytical power of bioinformatic platforms combined with patient clinical data from EMRs can reveal potential biomarkers and clinical phenotypes that allow researchers to develop experimental strategies using selected patient biospecimens stored in tissue banks. For cancer, high-quality biospecimens collected at diagnosis, first relapse, and various treatment stages provide crucial resources for study designs. To enlarge biospecimen collections, patient education regarding the value of specimen donation is vital. One approach for increasing consent is to offer publically available illustrations and game-like engagements demonstrating how wider sample availability facilitates development of novel therapies. The critical value of tissue bank samples, bioinformatics, and EMR in the early stages of the biomarker discovery process for personalized medicine is often overlooked. The data obtained also require cross-disciplinary collaborations to translate experimental results into clinical practice and diagnostic and prognostic use in personalized medicine. PMID:23818899

  1. The front-end electronics for the 1.8-kchannel SiPM tracking plane in the NEW detector

    Science.gov (United States)

    Rodríguez, J.; Toledo, J.; Esteve, R.; Lorca, D.; Monrabal, F.

    2015-01-01

    NEW is the first phase of NEXT-100 experiment, an experiment aimed at searching for neutrinoless double-beta decay. NEXT technology combines an excellent energy resolution with tracking capabilities thanks to a combination of optical sensors, PMTs for the energy measurement and SiPMs for topology reconstruction. Those two tools result in one of the highest background rejection potentials in the field. This work describes the tracking plane that will be constructed for the NEW detector which consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards. Then it focuses in the development of the electronics needed to read the 1800 channels with a front-end board that includes per-channel differential transimpedance input amplifier, gated integrator, automatic offset voltage compensation and 12-bit ADC. Finally, a description of how the FPGA buffers data, carries out zero suppression and sends data to the DAQ interface using CERN RD-51 SRS's DTCC link specification complements the description of the electronics of the NEW detector tracking plane.

  2. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  3. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C. J.; Müller, W. F. J.

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  4. A custom readout electronics for the BESIII CGEM detector

    Science.gov (United States)

    Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

    2017-07-01

    For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

  5. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  6. Simulation study of STS-XYTER front-end electronics in overload situations for the silicon tracking system in the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Balog, Tomas [GSI, Darmstadt (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    In high-rate experiments, as the CBM Experiment at FAIR, a situation can occur in which the data rate temporarily exceeds the available bandwidth. With self-triggered front end electronics such overload situations would lead, without further measures, to uncontrolled data losses and potentially a large number of incomplete events. Mechanisms needed to control data losses and to ensure the collection of complete events can be understood via simulations performed with the hardware description language SystemC. Results from simulations of a simplified front-end electronics for the CBM Silicon Tracking System, based on the STS-XYTER ASIC, are presented. Performed simulations give first insight in the behavior of data flow and data losses in the DAQ system of the CBM experiment. Options and solutions for the data throttling mechanisms at beam conditions required by the CBM experiment are discussed.

  7. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    Science.gov (United States)

    Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

    2016-12-01

    The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  8. Upgrade of the ALICE-TPC read-out electronics

    Energy Technology Data Exchange (ETDEWEB)

    Junique, A; Mager, M; Musa, L; Rehman, A Ur, E-mail: Magnus.Mager@cern.ch [CERN, Geneva (Switzerland)

    2010-12-15

    The ALICE experiment at CERN LHC employs a large volume time projection chamber (TPC) as its main tracking device. Instigated by analyses indicating that the high level trigger is capable of sifting events with rare physics probes, it is endeavoured to read out the TPC an order of magnitude faster then was reckoned during the design of its read-out electronics. Based on an analysis of the read-out performance of the current system, an upgrade of the front-end read-out network is proposed. The performance of the foreseen architecture is simulated with raw data from real 7 TeV pp collisions. Events are superimposed in order to emulate the future ALICE running conditions: high multiplicity events generated either by PbPb collisions or by the superposition (pile-up) of a large number of pp collisions. The first prototype of the main building block has been produced and characterised, demonstrating the feasibility of the approach.

  9. Upgrade of the ALICE-TPC read-out electronics

    CERN Document Server

    Junique, A; Musa , L; Rehman , A U

    2010-01-01

    The ALICE experiment at CERN LHC employs a large volume time projection chamber (TPC) as its main tracking device. Instigated by analyses indicating that the high level trigger is capable of sifting events with rare physics probes, it is endeavoured to read out the TPC an order of magnitude faster then was reckoned during the design of its read-out electronics. Based on an analysis of the read-out performance of the current system, an upgrade of the front-end read-out network is proposed. The performance of the foreseen architecture is simulated with raw data from real 7 TeV pp collisions. Events are superimposed in order to emulate the future ALICE running conditions: high multiplicity events generated either by PbPb collisions or by the superposition (pile-up) of a large number of pp collisions. The first prototype of the main building block has been produced and characterised, demonstrating the feasibility of the approach

  10. New Front End Technology

    Energy Technology Data Exchange (ETDEWEB)

    Pennington, D; Jovanovic, I; Comaskey, B J

    2001-02-01

    The next generation of Petawatt class lasers will require the development of new laser technology. Optical parametric chirped pulse amplification (OPCPA) holds a potential to increase the peak power level to >10 PW with existing grating technology through ultrashort pulses. Furthermore, by utilizing a new type of front-end system based on optical parametric amplification, pulses can be produced with substantially higher contrast than with Ti:sapphire regenerative amplifier technology. We performed extensive study of OPCPA using a single crystal-based OPA. We developed a replacement for Ti:sapphire regenerative amplifier for high peak power lasers based on OPCPA, with an output of 30 mJ, at 10 Hz repetition rate and 16.5 nm spectral bandwidth. We developed a 3D numerical model for OPCPA and we performed a theoretical study of influences of pump laser beam quality on optical parametric amplification. Our results indicate that OPCPA represents a valid replacement for Ti:sapphire in the front end of high energy short pulse lasers.

  11. The STAR Heavy Flavor Tracker PXL detector readout electronics

    Science.gov (United States)

    Schambach, J.; Contin, G.; Greiner, L.; Stezelberger, T.; Sun, X.; Szelezniak, M.; Vu, C.

    2016-01-01

    The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel ("PXL") subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector.

  12. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  13. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  14. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  15. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  16. Design and characterization of the PREC (Prototype Readout Electronics for Counting particles)

    Science.gov (United States)

    Assis, P.; Brogueira, P.; Ferreira, M.; Luz, R.; Mendes, L.

    2016-08-01

    The design, tests and performance of a novel, low noise, acquisition system—the PREC (Prototype Readout Electronics for Counting particles) is presented in this article. PREC is a system developed using discrete electronics for particle counting applications using RPCs (Resistive Plate Chamber) detectors. PREC can, however, be used with other kind of detectors that present fast pulses, e.g. Silicon Photomultipliers. The PREC system consists in several Front-End boards that transmit data to a purely digital Motherboard. The amplification and discrimination of the signal is performed in the Front-End boards, making them the critical component of the system. In this paper, the Front-End was tested extensively by measuring the gain, noise level, crosstalk, trigger efficiency, propagation time and power consumption. The gain shows a decrease with the working temperature and an increase with the power supply voltage. The Front-End board shows a low noise level (Motherboard is estimated to be 5.82 ns. The maximum power consumption is 3.372 W for the Motherboard and 3.576 W and 1.443 W for each Front-End analogue circuitry and digital part, respectively.

  17. CCD Readout Electronics for the Subaru Prime Focus Spectrograph

    CERN Document Server

    Hope, Stephen C; Loomis, Craig P; Fitzgerald, Roger E; Peacock, Grant O

    2014-01-01

    We present details of the design for the CCD readout electronics for the Subaru Telescope Prime Focus Spectrograph (PFS). The spectrograph is comprised of four identical spectrograph modules, each collecting roughly 600 spectra. The spectrograph modules provide simultaneous wavelength coverage over the entire band from 380 nm to 1260 nm through the use of three separate optical channels: blue, red, and near infrared (NIR). A camera in each channel images the multi-object spectra onto a 4k x 4k, 15 um pixel, detector format. The two visible cameras use a pair of Hamamatsu 2k x 4k CCDs with readout provided by custom electronics, while the NIR camera uses a single Teledyne HgCdTe 4k x 4k detector and ASIC Sidecar to read the device. The CCD readout system is a custom design comprised of three electrical subsystems: the Back End Electronics (BEE), the Front End Electronics (FEE), and a Pre-amplifier. The BEE is an off-the-shelf PC104 computer, with an auxiliary Xilinx FPGA module. The computer serves as the main...

  18. An ASIC design for versatile receive front-end electronics of an ultrasonic medical imaging system--16 channel analog inputs and 4 dynamically focused beam outputs.

    Science.gov (United States)

    Park, Song B; Kwak, Jaeyoung; Lee, Kwyro

    2003-04-01

    An ultra large-scale ASIC is designed for the receive front-end electronics of an ultrasonic medical imaging system. The chip receives 16 channel analog rf signals and outputs 4 sets of sample-point-wise dynamically focused partial beam data. Four complete beam data sets are obtained in parallel by simply cascading as many chips as needed in an array system. High resolution of the focusing delay is obtained by nonuniformly selecting each channel data from a quadruply-interpolated rf data stream. The proposed ASIC can be applied to most practical array transducers in the frequency range of 2 to 10 MHz. The digital part of the designed ASIC can be implemented on a chip area of 17.9 microm2 with 0.18 mm CMOS technology, leaving sufficient room for 16 ADCs of 8 bits, 50 MHz on the 5.7 mm x 5.7 mm chip with a 208 pin package.

  19. Design of the readout electronics for the DAMPE Silicon Tracker detector

    CERN Document Server

    Zhang, Fei; Gong, Ke; Wu, Di; Dong, Yi-Fan; Qiao, Rui; Fan, Rui-Rui; Wang, Jin-Zhou; Wang, Huan-Yu; Wu, Xin; La Marra, Daniel; Azzarello, Philipp; Gallo, Valentina; Ambrosi, Giovanni; Nardinocchi, Andrea

    2016-01-01

    The Silicon Tracker (STK) is a detector of the DAMPE satellite to measure the incidence direction of high energy cosmic ray. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73,728 readout channels. It's a great challenge to readout the channels and process the huge volume of data in the critical space environment. 1152 Application Specific Integrated Circuits (ASIC) and 384 ADCs are adopted to readout the detector channels. The 192 Tracker Front-end Hybrid (TFH) modules and 8 identical Tracker Readout Board (TRB) modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for STK and its performance will be presented in detail.

  20. Development for PRESPEC: New front end electronic for multi sampling ionization chambers of the GSI-fragment separator

    Energy Technology Data Exchange (ETDEWEB)

    Pietri, Stephane; Gerl, Juergen; Kurz, Nik; Nociforo, Chiara; Schaffner, Henning; Simon, Haik [GSI, Planckstrasse 1, 64291 Darmstadt (Germany)

    2009-07-01

    To study detailed structure effects during in-beam gamma spectroscopy experiments at the GSI fragment separator high particles rates are needed at the final focal plane. The use of new position detector (TPC) having higher rate capability than the previous Multi-Wire Proportional Counter put the ionization chambers (MUSICs) used for the {delta}-E measurement as the limiting factor. The current electronics used for those detector does not allow to sustain rates of up to 100 kHz that the coming experimental program will request. Indeed at those rates the analog electronic is not able to disentangle pile-up events and thus give a wrong Z identification for the incoming nucleus. The ongoing work on new digital electronic and on signal characterization to allow higher rates capability of those detectors is presented.

  1. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  2. Electronic readout system for the Belle II imaging Time-Of-Propagation detector

    Science.gov (United States)

    Kotchetkov, Dmitri

    2017-07-01

    The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

  3. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

    Science.gov (United States)

    Alessio, F.; Caplan, C.; Gaspar, C.; Jacobsson, R.; Wyllie, K.

    2015-02-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  4. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Document Server

    Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  5. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  6. Performance of a resistive plate chamber equipped with a new prototype of amplified front-end electronics

    CERN Document Server

    Marchisone, Massimiliano

    2016-01-01

    ALICE is the LHC experiment dedicated to the study of heavy-ion collisions. At forward rapidity a muon spectrometer detects muons from low mass mesons, quarkonia, open heavy-flavor hadrons as well as weak bosons. A muon selection based on transverse momentum is made by a trigger system composed of 72 resistive plate chambers (RPCs). For the LHC Run 1 and the ongoing Run 2 the RPCs have been equipped with a non-amplified FEE called ADULT. However, in view of an increase in luminosity expected for Run 3 (2021-2023) the possibility to use an amplified FEE has been explored in order to improve the counting rate limitation and to prevent the aging of the detector, by reducing the charge per hit. A prototype of this new electronics (FEERIC) has been developed and tested first with cosmic rays before equipping one RPC in the ALICE cavern with it. In this talk the most important performance indicators - efficiency, dark current, dark rate, cluster size and total charge - of an RPC equipped with this new FEE will be r...

  7. The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

    Science.gov (United States)

    Aguilar, J. A.; Bilnik, W.; Borkowski, J.; Cadoux, F.; Christov, A.; della Volpe, D.; Favre, Y.; Heller, M.; Kasperek, J.; Lyard, E.; Marszałek, A.; Moderski, R.; Montaruli, T.; Porcelli, A.; Prandini, E.; Rajda, P.; Rameez, M.; Schioppa, E.; Troyano Pujadas, I.; Ziȩtara, K.; Błocki, J.; Bogacz, L.; Bulik, T.; Curyło, M.; Dyrda, M.; Frankowski, A.; Grudniki, Ł.; Grudzińska, M.; Idźkowski, B.; Jamrozy, M.; Janiak, M.; Lalik, K.; Mach, E.; Mandat, D.; Michałowski, J.; Neronov, A.; Niemiec, J.; Ostrowski, M.; Paśsko, P.; Pech, M.; Schovanek, P.; Seweryn, K.; Skowron, K.; Sliusar, V.; Sowiński, M.; Stawarz, Ł.; Stodulska, M.; Stodulski, M.; Toscano, S.; Walter, R.; Wiȩcek, M.; Zagdański, A.; Żychowski, P.

    2016-09-01

    The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented.

  8. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

    Science.gov (United States)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-02-01

    This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

  9. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  10. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  11. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  12. Design of the Front End Electronics for the Infrared Camera of JEM-EUSO, and manufacturing and verification of the prototype model

    CERN Document Server

    Maroto, Oscar; Carbonell, Jordi; Tomàs, Albert; Reyes, Marcos; Joven, Enrique; Martín, Yolanda; Ríos, J A Morales de los; Del Peral, Luis; Frías, M D Rodríguez

    2015-01-01

    The Japanese Experiment Module (JEM) Extreme Universe Space Observatory (EUSO) will be launched and attached to the Japanese module of the International Space Station (ISS). Its aim is to observe UV photon tracks produced by ultra-high energy cosmic rays developing in the atmosphere and producing extensive air showers. The key element of the instrument is a very wide-field, very fast, large-lense telescope that can detect extreme energy particles with energy above $10^{19}$ eV. The Atmospheric Monitoring System (AMS), comprising, among others, the Infrared Camera (IRCAM), which is the Spanish contribution, plays a fundamental role in the understanding of the atmospheric conditions in the Field of View (FoV) of the telescope. It is used to detect the temperature of clouds and to obtain the cloud coverage and cloud top altitude during the observation period of the JEM-EUSO main instrument. SENER is responsible for the preliminary design of the Front End Electronics (FEE) of the Infrared Camera, based on an unco...

  13. Design and Implementation of an Electronic Front-End Based on Square Wave Excitation for Ultrasonic Torsional Guided Wave Viscosity Sensor.

    Science.gov (United States)

    Rabani, Amir

    2016-10-12

    The market for process instruments generally requires low cost devices that are robust, small in size, portable, and usable in-plant. Ultrasonic torsional guided wave sensors have received much attention by researchers for measurement of viscosity and/or density of fluids in recent years. The supporting electronic systems for these sensors providing many different settings of sine-wave signals are bulky and expensive. In contrast, a system based on bursts of square waves instead of sine waves would have a considerable advantage in that respect and could be built using simple integrated circuits at a cost that is orders of magnitude lower than for a windowed sine wave device. This paper explores the possibility of using square wave bursts as the driving signal source for the ultrasonic torsional guided wave viscosity sensor. A simple design of a compact and fully automatic analogue square wave front-end for the sensor is also proposed. The successful operation of the system is demonstrated by using the sensor for measuring the viscosity in a representative fluid. This work provides the basis for design and manufacture of low cost compact standalone ultrasonic guided wave sensors and enlightens the possibility of using coded excitation techniques utilising square wave sequences in such applications.

  14. Design and Implementation of an Electronic Front-End Based on Square Wave Excitation for Ultrasonic Torsional Guided Wave Viscosity Sensor

    Directory of Open Access Journals (Sweden)

    Amir Rabani

    2016-10-01

    Full Text Available The market for process instruments generally requires low cost devices that are robust, small in size, portable, and usable in-plant. Ultrasonic torsional guided wave sensors have received much attention by researchers for measurement of viscosity and/or density of fluids in recent years. The supporting electronic systems for these sensors providing many different settings of sine-wave signals are bulky and expensive. In contrast, a system based on bursts of square waves instead of sine waves would have a considerable advantage in that respect and could be built using simple integrated circuits at a cost that is orders of magnitude lower than for a windowed sine wave device. This paper explores the possibility of using square wave bursts as the driving signal source for the ultrasonic torsional guided wave viscosity sensor. A simple design of a compact and fully automatic analogue square wave front-end for the sensor is also proposed. The successful operation of the system is demonstrated by using the sensor for measuring the viscosity in a representative fluid. This work provides the basis for design and manufacture of low cost compact standalone ultrasonic guided wave sensors and enlightens the possibility of using coded excitation techniques utilising square wave sequences in such applications.

  15. FRIB Front End Design Status

    CERN Document Server

    Pozdeyev, E; Machicoane, G; Morgan, G; Rao, X; Zhao, Q; Stovall, J; Vorozhtsov, S; Sun, L

    2013-01-01

    The Facility for Rare Isotope Beams (FRIB) will provide a wide range of primary ion beams for nuclear physics research with rare isotope beams. The FRIB SRF linac will be capable of accelerating medium and heavy ion beams to energies beyond 200 MeV/u with a power of 400 kW on the fragmentation target. This paper presents the status of the FRIB Front End designed to produce uranium and other medium and heavy mass ion beams at world-record intensities. The paper describes the FRIB high performance superconducting ECR ion source, the beam transport designed to transport two-charge state ion beams and prepare them for the injection in to the SRF linac, and the design of a 4-vane 80.5 MHz RFQ. The paper also describes the integration of the front end with other accelerator and experimental systems.

  16. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  17. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  18. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  19. Performance of an analog ASIC developed for the front-end electronics of the soft x-ray imager onboard ASTRO-H

    Science.gov (United States)

    Nakajima, H.; Idehara, T.; Matsuura, D.; Anabuki, N.; Tsunemi, H.; Doty, J. P.; Ikeda, H.

    2009-08-01

    We report on the performance of an analog application-specified integrated circuit (ASIC) developed for the front-end electronics of the X-ray CCD camera system (SXI: Soft X-ray Imager) onboard the ASTRO-H satellite. The ASIC consists of four identical channels and they simultaneously process the CCD signals at the pixel rate of 68kHz. Delta-Sigma modulator is adopted to achieve effective noise shaping and obtain a high resolution decimal values with relatively simple circuits. We will implement 16 ASIC chips in total in the focal plane assembly. The results of the unit test shows that it works properly with moderately low input noise of <30μV at the pixel rate of 80kHz. Power consumption is sufficiently low of 150mW. Dynamic range of input signals is +-20mV that covers effective energy range of the CCD chips of SXI (0.2-20keV). The integrated non-linearity of 0.2% satisfies the same performance as the conventional CCD detectors in orbit. The radiation tolerance against total ionizing dose (TID) effect and single event latch-up (SEL) has also been investigated. The irradiation test using 60Co gamma-rays and proton beam showed that the ASIC has sufficient tolerance against TID up to 200 and 167krad respectively, which thoroughly exceeds the expected operating duration in the planned low-inclination low-earth orbit. The irradiation of the Fe ion beam also showed no latch-up nor malfunctions up to the fluence of 4.7x10^7ions. The threshold against SEL is larger than 1.68MeVcm^2/mg, which is sufficiently high enough that SEL events should not be a major cause of instrument downtime.

  20. Front-End Electron Transfer Dissociation Coupled to a 21 Tesla FT-ICR Mass Spectrometer for Intact Protein Sequence Analysis

    Science.gov (United States)

    Weisbrod, Chad R.; Kaiser, Nathan K.; Syka, John E. P.; Early, Lee; Mullen, Christopher; Dunyach, Jean-Jacques; English, A. Michelle; Anderson, Lissa C.; Blakney, Greg T.; Shabanowitz, Jeffrey; Hendrickson, Christopher L.; Marshall, Alan G.; Hunt, Donald F.

    2017-09-01

    High resolution mass spectrometry is a key technology for in-depth protein characterization. High-field Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) enables high-level interrogation of intact proteins in the most detail to date. However, an appropriate complement of fragmentation technologies must be paired with FTMS to provide comprehensive sequence coverage, as well as characterization of sequence variants, and post-translational modifications. Here we describe the integration of front-end electron transfer dissociation (FETD) with a custom-built 21 tesla FT-ICR mass spectrometer, which yields unprecedented sequence coverage for proteins ranging from 2.8 to 29 kDa, without the need for extensive spectral averaging (e.g., 60% sequence coverage for apo-myoglobin with four averaged acquisitions). The system is equipped with a multipole storage device separate from the ETD reaction device, which allows accumulation of multiple ETD fragment ion fills. Consequently, an optimally large product ion population is accumulated prior to transfer to the ICR cell for mass analysis, which improves mass spectral signal-to-noise ratio, dynamic range, and scan rate. We find a linear relationship between protein molecular weight and minimum number of ETD reaction fills to achieve optimum sequence coverage, thereby enabling more efficient use of instrument data acquisition time. Finally, real-time scaling of the number of ETD reactions fills during method-based acquisition is shown, and the implications for LC-MS/MS top-down analysis are discussed. [Figure not available: see fulltext.

  1. Design of the front end electronics for the infrared camera of JEM-EUSO, and manufacturing and verification of the prototype model

    Science.gov (United States)

    Maroto, Oscar; Diez-Merino, Laura; Carbonell, Jordi; Tomàs, Albert; Reyes, Marcos; Joven-Alvarez, Enrique; Martín, Yolanda; Morales de los Ríos, J. A.; del Peral, Luis; Rodríguez-Frías, M. D.

    2014-07-01

    The Japanese Experiment Module (JEM) Extreme Universe Space Observatory (EUSO) will be launched and attached to the Japanese module of the International Space Station (ISS). Its aim is to observe UV photon tracks produced by ultra-high energy cosmic rays developing in the atmosphere and producing extensive air showers. The key element of the instrument is a very wide-field, very fast, large-lense telescope that can detect extreme energy particles with energy above 1019 eV. The Atmospheric Monitoring System (AMS), comprising, among others, the Infrared Camera (IRCAM), which is the Spanish contribution, plays a fundamental role in the understanding of the atmospheric conditions in the Field of View (FoV) of the telescope. It is used to detect the temperature of clouds and to obtain the cloud coverage and cloud top altitude during the observation period of the JEM-EUSO main instrument. SENER is responsible for the preliminary design of the Front End Electronics (FEE) of the Infrared Camera, based on an uncooled microbolometer, and the manufacturing and verification of the prototype model. This paper describes the flight design drivers and key factors to achieve the target features, namely, detector biasing with electrical noise better than 100μV from 1Hz to 10MHz, temperature control of the microbolometer, from 10°C to 40°C with stability better than 10mK over 4.8hours, low noise high bandwidth amplifier adaptation of the microbolometer output to differential input before analog to digital conversion, housekeeping generation, microbolometer control, and image accumulation for noise reduction. It also shows the modifications implemented in the FEE prototype design to perform a trade-off of different technologies, such as the convenience of using linear or switched regulation for the temperature control, the possibility to check the camera performances when both microbolometer and analog electronics are moved further away from the power and digital electronics, and

  2. ATLAS LAr calorimeters readout electronics upgrade R&D for sLHC

    CERN Document Server

    Chen, Hucheng

    2010-01-01

    The ATLAS Liquid Argon (LAr) calorimeters consist of an electromagnetic barrel calorimeter and two end-caps with electromagnetic, hadronic and forward calorimeters. A total of 182,468 signals are digitized and processed real-time on detector, to provide energy and time deposited in each detector element at every occurrence of the Level-1 trigger. A luminosity upgrade of the LHC will occur in the years 2018. The current readout electronics will need to be upgraded to sustain the higher radiation levels. A completely innovative readout scheme is being developed. The front-end readout will send out data continuously at each bunch crossing through high speed radiation resistant optical links, the data will be processed real-time with the possibility of implementing trigger algorithms. This article is an overview of the R&D activities and architectural studies the ATLAS LAr Calorimeter Group is developing.

  3. Design of the readout electronics for the DAMPE Silicon Tracker detector

    Science.gov (United States)

    Zhang, Fei; Peng, Wen-Xi; Gong, Ke; Wu, Di; Dong, Yi-Fan; Qiao, Rui; Fan, Rui-Rui; Wang, Jin-Zhou; Wang, Huan-Yu; Wu, Xin; La Marra, Daniel; Azzarello, Philipp; Gallo, Valentina; Ambrosi, Giovanni; Nardinocchi, Andrea

    2016-11-01

    The Silicon Tracker (STK) is one of the detectors of the DAMPE satellite used to measure the incidence direction of high energy cosmic rays. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73728 readout channels. It is a great challenge to read out the channels and process the huge volume of data in the harsh environment of space. 1152 Application Specific Integrated Circuits (ASIC) and 384 ADCs are used to read out the detector channels. 192 Tracker Front-end Hybrid (TFH) modules and 8 identical Tracker Readout Board (TRB) modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for the STK and its performance are presented in detail.

  4. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  5. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  6. BESIII ETOF upgrade readout electronics commissioning

    Science.gov (United States)

    Wang, Xiao-Zhuang; Dai, Hong-Liang; Wu, Zhi; Heng, Yue-Kun; Zhang, Jie; Cao, Ping; Ji, Xiao-Lu; Li, Cheng; Sun, Wei-Jia; Wang, Si-Yu; Wang, Yun

    2017-01-01

    It is proposed to upgrade the endcap time-of-flight (ETOF) of the Beijing Spectrometer III (BESIII) with a multi-gap resistive plate chamber (MRPC), aiming at an overall time resolution of about 80 ps. After completing the entire readout electronics system, some experiments, such as heat radiation, radiation hardness and large-current beam tests, have been carried out to confirm the reliability and stability of the readout electronics. An on-detector test of the readout electronics has also been performed with the beam at the BEPCII E3 line. The test results indicate that the readout electronics system fulfills its design requirements. Supported by Chinese Academy of Sciences (1G201331231172010)

  7. The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Ochoa, Ines; The ATLAS collaboration

    2017-01-01

    Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, and performances on prototypes will presented with the overall system design.

  8. Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

    Energy Technology Data Exchange (ETDEWEB)

    Budden, B.S., E-mail: bbudden@lanl.gov [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Stonehill, L.C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D.D.S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Kamto, J. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Electrical & Computer Engineering Department, Praire View A& M University, Prairie View, TX 77446 (United States)

    2015-09-21

    A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.

  9. Data acquisition at the front-end of the Mu3e pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

    2016-07-01

    The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

  10. Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00567140; The ATLAS collaboration

    2017-01-01

    The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events even at rather low transverse energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of 1 MHz are planned, combined with longer latencies up to 60 micro-seconds in order to read out the necessary data from all detector channels. Under these conditions, the current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons a replacement of the LAr front-end and back-end readout system is foreseen for all 182,500 readout channels, with the exception of t...

  11. Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

    CERN Document Server

    Chen, H

    2012-01-01

    The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS and its LAr calorimeters have been operating and collecting proton-proton collisions at LHC since 2009. The current front-end electronics of the LAr calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded high luminosity LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. The complexity of the present electronics and the obsolescence of some of components of which it is made, will not allow a partial replacement of the system. A completely new readout architecture scheme is under study and many components are being developed in various R&D programs of the LAr Calorimeter Group. The new front-end readout electronics will send data continuously at each bunch crossing through high speed...

  12. Upgraded Trigger Readout Electronics for the ATLAS LAr Calorimeters for Future LHC Running

    CERN Document Server

    Ma, H; The ATLAS collaboration

    2015-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that are digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first- level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34cm^−2s^−1. In order to retain the capability to trigger on low energy electrons and photons when the LHC is upgraded to higher luminosity, an improved LAr calorimeter trigger readout is proposed and being constructed. The new trigger readout system makes available the fine segmentation of the calorimeter at the L1 trigger with high precision in order to reduce the QCD jet background in electron, photon and tau triggers, and to improve jet and missing ET trigger performance. The new LAr Trigger Digitizer Board is designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a...

  13. Proposed STAR Time of Flight Readout Electronics and DAQ

    Science.gov (United States)

    Schambach, Joachim

    2006-04-01

    A novel Time-of-Flight (TOF) subsystem is under design for the STAR detector at RHIC. A total of 3840 Multi-gap Resistive Plate Chambers (MRPC) of 6 pads each are distributed over 120 trays. The total number of channels is 23040. Each TOF tray consists of 192 detector channels and three different types of electronic circuit cards, called "TINO", "TDIG", and "TCPU", listed in order of the data flow. Every 30 trays send their data to a "THUB" card that interfaces to the STAR trigger and transmits the data over a fiber to a fiber receiver which is part of STAR DAQ. The TINO contains the analog front end electronics based on a custom IC called NINO. The output of TINO is passed to the TDIG, where the data are digitized (using the CERN HPTDC ASIC). The TCPU formats and buffers the digital detector information. This formatted data is passed to THUB, which transmits it over an optical fiber to a data receiver in the STAR DAQ room. The architecture of this readout chain and DAQ will be described, and first results from prototypes of the component boards will be discussed.

  14. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  15. A prototype for the upgraded readout electronics of TileCal

    CERN Document Server

    Eriksson, D; Bohm, C; Kavianipour, H; Anderson, K; Oreglia, M; Tang, F

    2012-01-01

    Upgrade plans for ATLAS hadronic tile calorimeter (TileCal) include full readout of all data to the counting room. R&amp;D activities at different laboratories target different parts of the upgraded system. We are developing a possible implementation of the future readout electronics to be included in a full functional demonstrator. This must be capable of adapting to each of the three different front-end alternatives. Prototypes of the two PCBs that will be in charge of digitization, control and communication have been developed. The design is redundant and uses FPGAs with fault tolerant firmware for control and protocol conversion. Communication and clock synchronization between on and off detector electronics is implemented via high speed optical links using the GBT protocol.

  16. Electronic Readout of the Atlas Liquid Argon Calorimeter: Calibration and Performance

    CERN Document Server

    Majewski, S; The ATLAS collaboration

    2010-01-01

    The Liquid Argon (LAr) calorimeter is a key detector component in the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. The LHC is a proton-proton collider with a center-of-mass energy of 14 TeV. The machine has been operated at energies of 900 GeV and 2.36 TeV in 2009 and is expected to reach the energy of 7 TeV in 2010. The LAr calorimeter is designed to provide precision measurements of electrons, photons, jets and missing transverse energy. It consists of a set of sampling calorimeters with liquid argon as active medium kept into three separate cryostats. The LAr calorimeters are read out via a system of custom electronics. The electronic readout of the ATLAS LAr calorimeters is divided into a Front End (FE) system of boards mounted in custom crates directly on the cryostat feedthroughs, and a Back End (BE) system of VME-based boards located in an off-detector underground counting room where there is no radiation. The FE system includes Front End boards (FEBs), which perform the readout and dig...

  17. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  18. Muon front end for the neutrino factory

    CERN Document Server

    Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

    2013-01-01

    In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  19. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  20. Timing and Readout Contorl in the LHCb Upgraded Readout System

    CERN Document Server

    Alessio, Federico

    2016-01-01

    In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

  1. Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

    CERN Document Server

    Guan, Liang; The ATLAS collaboration

    2017-01-01

    The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small strip Thin Gap Chambers will be used to provide both trigger and tracking primitives. Muon segments found at NSW will be combined with the segments found at the Big Wheel to determine the muon transverse momentum at the first-level trigger. A new trigger and readout system is developed for the NSW detector. The new system has about 2.4 million trigger and readout channels and about 8,000 Front-End boards. The large number of input channels, short time available to prepare and transmit data, harsh radiation environment, and low power consumption all impose great challenges on the design. We will discuss the overall electronics design and studies with various ASICs and high-speed circuit board prototypes.

  2. Electronics development for the ATLAS liquid argon calorimeter trigger and readout for future LHC running

    Science.gov (United States)

    Hopkins, Walter

    2017-02-01

    The upgrade of the LHC will provide 7 times greater instantaneous and 10 times greater total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energies of all cells will be available at the second trigger level operating at 1 MHz, in order to allow further mitigation of pile-up effects in energy reconstruction. Radiation tolerant, low-power front-end electronics optimized for high pile-up conditions are currently being developed, including pre-amplifier, ADC and serializer components in 65-180 nm technology. This contribution will give an overview of the future LAr readout electronics and present research results from the two upgrade programs.

  3. Readout electronics for CBM-TOF super module quality evaluation based on 10 Gbps ethernet

    Science.gov (United States)

    Jiang, D.; Cao, P.; Huang, X.; Zheng, J.; Wang, Q.; Li, B.; Li, J.; Liu, S.; An, Q.

    2017-07-01

    The Compressed Baryonic Matter-Time of Flight (CBM-TOF) wall uses high performance of Multi-gap Resistive Plate Chambers (MRPC) assembled in super modules to identify charged particles with high channel density and high measurement precision at high event rate. Electronics meet the challenge for reading data out from a super module at high speed of about 6 Gbps in real time. In this paper, the readout electronics for CBM-TOF super module quality evaluation is proposed based on 10 Gigabit Ethernet. The digitized TOF data from one super module will be concentrated at the front-end electronics residing on the side of the super module and transmitted to an extreme speed readout module (XSRM) housed in the backend crate through the PCI Express (PCIe) protocol via optic channels. Eventually, the XSRM transmits data to the data acquisition (DAQ) system through four 10 Gbps Ethernet ports in real time. This readout structure has advantages of high performance and expansibility. Furthermore, it is easy to operate. Test results on the prototype show that the overall data readout performance for each XSRM can reach up to 28.8 Gbps, which means XSRM can meet the requirement of reading data out from 4 super modules with 1280 channels in real time.

  4. A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

  5. ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; O CONNOR,P.; KANDASAMY,A.; GROSHOLZ,J.

    2002-07-08

    A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 {micro}m CMOS and tested. Design concepts and experimental results are discussed.

  6. Chapter 9: Electronics

    OpenAIRE

    Spieler, Helmuth G

    2008-01-01

    Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques.

  7. Chapter 9: Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Grupen, Claus; Shwartz, Boris A.

    2006-12-19

    Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques.

  8. Chapter 9: Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Grupen, Claus; Shwartz, Boris A.

    2006-12-19

    Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques.

  9. Readout electronics for low dark count Geiger mode avalanche photodiodes fabricated in conventional HV-CMOS technologies for future linear colliders

    Energy Technology Data Exchange (ETDEWEB)

    Vilella, E; Arbat, A; Alonso, O; Vila, A; Dieguez, A [Department of Electronics, University of Barcelona (UB) MartI i Franques 1, 08028 Barcelona (Spain); Comerma, A; Trenado, J; Gascon, D; Garrido, L, E-mail: evilella@el.ub.es [Department of Structure and Constituents of Matter, University of Barcelona (UB) MartI i Franques 1, 08028 Barcelona (Spain)

    2011-01-15

    This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 {mu}m HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work.

  10. CMS ECAL Front-End boards the XFEST project

    CERN Document Server

    Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N; Romanteau, T

    2005-01-01

    The Front-End (FE) boards are part of the On-detector electronics system of the CMS electromagnetic calorimeter (ECAL). Their digital functionalities and properties are tested by a dedicated test bench located at Laboratoire Leprince-Ringuet, prior to the board integration in the CMS detector at CERN. XFEST, acronym for eXtended Front-End System Test, is designed to perform tests that can last several hours, on up to 12 FE boards in parallel. The system is designed to deliver 80 tested boards per week. This contribution presents the XFEST set-up and the results of the measurements on FE boards.

  11. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  12. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  13. Optimizing emergency department front-end operations.

    Science.gov (United States)

    Wiler, Jennifer L; Gentle, Christopher; Halfpenny, James M; Heins, Alan; Mehrotra, Abhi; Mikhail, Michael G; Fite, Diana

    2010-02-01

    As administrators evaluate potential approaches to improve cost, quality, and throughput efficiencies in the emergency department (ED), "front-end" operations become an important area of focus. Interventions such as immediate bedding, bedside registration, advanced triage (triage-based care) protocols, physician/practitioner at triage, dedicated "fast track" service line, tracking systems and whiteboards, wireless communication devices, kiosk self check-in, and personal health record technology ("smart cards") have been offered as potential solutions to streamline the front-end processing of ED patients, which becomes crucial during periods of full capacity, crowding, and surges. Although each of these operational improvement strategies has been described in the lay literature, various reports exist in the academic literature about their effect on front-end operations. In this report, we present a review of the current body of academic literature, with the goal of identifying select high-impact front-end operational improvement solutions.

  14. Development of ATLAS Liquid Argon Calorimeter readout electronics for the HL-LHC

    Science.gov (United States)

    Brooijmans, G.

    2017-07-01

    The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events at electroweak energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of up to 1 MHz are planned, combined with longer latencies up to 40 micro-seconds in order to read out the necessary data from all detector channels. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. For these reasons a replacement of the LAr front-end and off-detector readout systems is foreseen for all 182,500 readout channels, with the exception of the cold pre-amplifier and summing devices of the hadronic LAr Calorimeter. The new low-power electronics must be able to capture the triangular detector pulses of about 400-600 nano-seconds length with signal currents up to 10 mA and a dynamic range of 16 bits. Results from performance simulation of the calorimeter readout system for different options and results from first tests of the components are presented.

  15. A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN

    CERN Multimedia

    Alessio, F; Guzik, Z

    2009-01-01

    LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-End

  16. Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC

    CERN Document Server

    Strässner, A

    2009-01-01

    The ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2017, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gbps per front-end board, each covering 128 readout channels. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system will be ...

  17. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    FRAGNAUD, J; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS LAr Calorimeters will be improved for the Phase-I luminosity upgrade of the LHC to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being set up which is planned to be installed on the ATLAS detector during the upcoming LHC run. Results from system tests of the analog signal treatment, the trigger digitizer, the optical signal transmission and the FPGA-based back-end are reported.

  18. 用于碲锌镉探测器前端读出电路的SAR ADC设计%Design of SAR ADC for Front-End Readout Circuits of CZT Detector

    Institute of Scientific and Technical Information of China (English)

    刘永波; 魏廷存; 曾蕙明; 詹思维

    2013-01-01

    Based on the low—power, low—noise and high—precision features of front—end readout circuits for CZT detector, a 12 — bit, lMsps successive approximation register analog—to—digital converter (SAR ADC) is designed. The ADC consists of digital—to — analog converter (DAC), comparator, and so on. The DAC is implemented using charge scaling technique and principle of charge conservation, thus the matching accuracy of the scaling capacitor is improved. The comparator is multi-stage pre—amplifier and dynamic latch cascade structure; its offset error is minimized by using output offset calibration technique. The circuit is implemented and simulated in TSMC 0. 18μm mixed signal CMOS technology. Testing results show that, SAR ADC has -0. 1/0. 37 LSB DNL, -0. 44/0. 32 LSB INL, 65. 33dB SNR, 10. 55-bit ENOB and 1. 17mW power consumptioa The performances meet the requirements of the front—end readout circuits.%针对碲锌镉探测器前端读出电路要求低功耗、低噪声、高精度的特点,设计了一种12-bit、1Ms/s的逐次逼近式模数转换器(SAR ADC).该模数转换器由数模转换器(DAC)和比较器等组成.其中DAC采用电荷按比例缩放结构,利用电荷守恒原理,提高了缩放电容的匹配精度.比较器采用多级预放大器级联的动态锁存器结构,采用输出失调校准技术提高了比较器的精度.整个电路采用TSMC 0.18μm 1P6M CMOS混合工艺进行设计和实现.仿真结果表明,在1MHz的采样率、输入为97KHz正弦信号下,SAR ADC的DNL为-0.1/0.37LSB,INL为-0.44/0.32LSB,SNR为65.33dB,ENOB为10.55bit,功耗为1.17mW,满足了系统的设计要求.

  19. BESIII Muon 前端电子学数据链过流保护系统设计%The Design of Muon Front-end Electronics Overcurrent Protector for BESIII

    Institute of Scientific and Technical Information of China (English)

    陈颖; 习建博; 梁昊

    2016-01-01

    This paper introduces the design of an overcurrent protector which can monitor the power supply of BESIII Muon front -end electronics and protect it against large current .The hardware and software designs of the overcurrent protector are showed in this article .In addition , the test result for major technical index of the overcurrent protector prototype is given in detail .%论文介绍了BESIII Muon前端电子学数据链过流保护系统的设计,其主要功能是监控数据链供电,防止数据链受大电流损伤。文章主要阐述了过流保护系统的软硬件设计,同时给出了过流保护系统原型机各项基本指标的测试结果。

  20. Readout electronics for the SiPM tracking plane in the NEXT-1 prototype

    Energy Technology Data Exchange (ETDEWEB)

    Herrero, V. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Toledo, J., E-mail: jtoledo@eln.upv.es [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Catala, J.M.; Esteve, R. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Gil, A.; Lorca, D. [Instituto de Fisica Corpuscular (CSIC-Universidad de Valencia), 46980 Valencia (Spain); Monzo, J.M.; Sanchis, F. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Verdugo, A. [CIEMAT-Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas, Madrid (Spain)

    2012-12-11

    NEXT is a new experiment to search for neutrinoless double beta decay using a 100 kg radio-pure high-pressure gaseous xenon TPC with electroluminescence readout. A large-scale prototype with a SiPM tracking plane has been built. The primary electron paths can be reconstructed from time-resolved measurements of the light that arrives to the SiPM plane. Our approach is to measure how many photons have reached each SiPM sensor each microsecond with a gated integrator. We have designed and tested a 16-channel front-end board that includes the analog paths and a digital section. Each analog path consists of three different stages: a transimpedance amplifier, a gated integrator and an offset and gain control stage. Measurements show good linearity and the ability to detect single photoelectrons.

  1. Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

    CERN Document Server

    Zhu, Junjie; The ATLAS collaboration

    2017-01-01

    The planned Phase-I and Phase-II upgrades of the LHC accelerator drastically impacts the ATLAS trigger and trigger rates. A replacement of the ATLAS innermost endcap muon station with a new small wheel (NSW) detector is planned for the second long shutdown period of 2019 - 2020. This upgrade will allow us to maintain a low pT threshold for single muon and excellent tracking capability even after the High-Luminosity LHC upgrade. The NSW detector will feature two new detector technologies, Resistive Micromegas and small-strip Thin Gap Chambers. Both detector technologies will provide trigger and tracking primitives. The total number of trigger and readout channels is about 2.4 millions, and the overall power consumption is expected to be about 75 kW. The electronics design will be implemented in some 8000 front-end boards including the design of four custom front-end ASICs capable to drive trigger and tracking primitives with high speed sterilizers to drive trigger candidates to the backend trigger processor sy...

  2. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  3. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  4. UNIX NSW Front End Enhancements. Volume I.

    Science.gov (United States)

    1981-06-01

    Implementation UNIX MSG is implemented in the programming language C (D.M. Ritchie, S.C. Johnson, M.E. Lesk, and B.W. Kernighan , "The C Programming Language...8URC-0062 UNCLASSIFIED B BN4b I VOL-1 RADC-TR-81-lbA VOL-1 NL fRADCTR-81-164, Vol I (of two) Final Technical Report June 1981 .. UNIX NSW FRONT END...ABSTRACT (Conti--- on re0-r8. side If necessary and idenfify by block number) The effort to develop a UNIX NSW Front End is part of the National Software

  5. Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00069444; The ATLAS collaboration

    2017-01-01

    The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile- up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events at electroweak energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of up to 1 MHz are planned, combined with longer latencies up to 40 micro-seconds in order to read out the necessary data from all detector channels. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. For these reasons a replacement of the LAr front-end and off-detector readout systems is foreseen for all 182,500 readout channels, with the exception of the cold pre-amplifier and summing devices of the hadronic LAr Calorimeter. The new low-power electronics must be able to capture the triangular dete...

  6. PHYSICS RESULTS OF THE NSLS-II LINAC FRONT END TEST STAND

    Energy Technology Data Exchange (ETDEWEB)

    Fliller R. P.; Gao, F.; Yang, X.; Rose, J.; Shaftan, T.; Piel, C

    2012-05-20

    The Linac Front End Test Stand (LFETS) was installed at the Source Development Laboratory (SDL) in the fall of 2011 in order to test the Linac Front End. The goal of these tests was to test the electron source against the specifications of the linac. In this report, we discuss the results of these measurements and the effect on linac performance.

  7. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  8. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  9. FRED, a Front End for Databases.

    Science.gov (United States)

    Crystal, Maurice I.; Jakobson, Gabriel E.

    1982-01-01

    FRED (a Front End for Databases) was conceived to alleviate data access difficulties posed by the heterogeneous nature of online databases. A hardware/software layer interposed between users and databases, it consists of three subsystems: user-interface, database-interface, and knowledge base. Architectural alternatives for this database machine…

  10. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    . The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

  11. A Multi-Pulse Front-End Rectifier System with Electronic Phase-Shifting for Harmonic Mitigation in Motor Drive Applications

    DEFF Research Database (Denmark)

    Zare, Firuz; Davari, Pooya; Blaabjerg, Frede

    2016-01-01

    In this paper, an electronic phase-shifting strategy has been optimized for a multi-parallel configuration of line-commutated rectifiers with a common dc-bus voltage used in motor drive application. This feature makes the performance of the system independent of the load profile and maximizes its...... harmonic reduction ability. To further reduce the generated low order harmonics, a dc-link current modulation scheme and its phase shift values of multi-drive systems have been optimized. Analysis and simulations have been carried out to verify the proposed method....

  12. Development of new readout electronics for the ATLAS LAr Calorimeter at the sLHC

    CERN Document Server

    Strässner, A

    2009-01-01

    The readout of the ATLAS Liquid Argon (LAr) calorimeter is a complex multi-channel system to amplify, shape, digitize and process signals of the detector cells. The current on-detector electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2019/2020, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gb/s per front-end board. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system is given. The current R&D activities and architectural studies of the LAr Calorimeter group...

  13. Conceptual Design of Front Ends for the Advanced Photon Source Multi-bend Achromats Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Jaski, Y.; Westferro, F.; Lee, S. H.; Yang, B.; Abliz, M.; Ramanathan, M.

    2016-07-27

    The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shutters open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.

  14. Pixel front-end development in 65 nm CMOS technology

    CERN Document Server

    Havránek, M; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.

  15. Read-out electronics for DC squid magnetic measurements

    Science.gov (United States)

    Ganther, Jr., Kenneth R.; Snapp, Lowell D.

    2002-01-01

    Read-out electronics for DC SQUID sensor systems, the read-out electronics incorporating low Johnson noise radio-frequency flux-locked loop circuitry and digital signal processing algorithms in order to improve upon the prior art by a factor of at least ten, thereby alleviating problems caused by magnetic interference when operating DC SQUID sensor systems in magnetically unshielded environments.

  16. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  17. A radiation hard bipolar monolithic front-end readout

    CERN Document Server

    Baschirotto, A; Cappelluti, I; Castello, R; Cermesoni, M; Gola, A; Pessina, G; Pistolesi, E; Rancoita, P G; Seidman, A

    1999-01-01

    A fast bipolar monolithic charge sensitive preamplifier (CSP), implemented in the monolithic 2 mu m BiCMOS technology (called HF2CMOS) was designed and built in a quad monolithic chip. Studies of radiation effects in the CSP $9 performance, from non-irradiated and up to neutron irradiation of 5.3*10/sup 14/ n/cm/sup 2/, have confirmed that the use of bipolar npn transistors is suitable for the radiation level of the future LHC collider environment. The CSP $9 presents a new circuit solution for obtaining adequate slew rate performances which results in an integral linearity better than 0.8554330n 5 V at 20 ns of shaping time, regardless of the bias current selected for the CSP. This way $9 the bias current of the CSP can be set for optimizing the power dissipation with respect to series and parallel noise, especially useful when the CSP is put in a radiation environment. A prototype test with a novel monolithic 20 ns $9 time constant RC-CR shaper, capable to sum up four inputs has been also realized, featurin...

  18. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  19. The NA48 LKr calorimeter readout electronics

    CERN Document Server

    Gianoli, A; Barr, C; Brodier-Yourstone, P; Buchholz, P; Ceccucci, Augusto; Cerri, C; Chlopik, A; Constantini, F; Fantechi, R; Formenti, F; Funk, W; Giudici, Sergio; Gorini, B; Guzik, J A; Hallgren, Björn I; Kozhevnikov, Yu; Iwansky, W; de La Taille, C; Lacourt, A; Laverrière, G C; Ljuslin, C; Mannelli, I; Martin-Chassard, G; Martini, M; Papi, A; Seguin-Moreau, N; Sozzi, M; Tarlé, J C; Velasco, M; Vossnack, O; Wahl, H; Ziolkowski, M

    2000-01-01

    The NA48 experiment at the CERN SPS accelerator is making a measurement of the direct CP violation parameter epsilon '/ epsilon by comparing the four rates of decay of K/sub S/ and K/sub L/ into 2 pi /sup 0/ and pi /sup +/ pi /sup -/. To reconstruct the decays into 2 pi /sup 0/ the information from the almost 13500 channels of a quasi-homogeneous liquid krypton electromagnetic calorimeter is used. The readout electronics of the calorimeter has been designed to provide a dynamic range from a few MeV to about 50 GeV energy deposition per cell, and to sustain a high rate of incident particles. The system is made by cold charge preamplifiers (working at 120 degrees K), low-noise fast shapers followed by digitizer electronics at 40 MHz sampling rate that employs a gain switching technique to expand the dynamic range, where the gain can be selected for each sample individually (i.e. every 25 ns). To reduce the amount of data collected the system contains a zero suppression circuit based on halo expansion. (12 refs)...

  20. BESⅢ Muon鉴别器前端电子学读出系统%The Front-End Electronics and Readout System for BESⅢ Muon Counter

    Institute of Scientific and Technical Information of China (English)

    刘强; 梁昊; 陈一新; 薛俊东; 虞孝麒; 周永钊

    2008-01-01

    本文介绍了BESSⅢ Muon前端电子学读出系统的结构,详细说明了依据菊花链方式的前端板和基于USB的读出板的设计和实现方法.该系统中较多地采用了FPGA技术,极大地降低了系统的复杂程度和建造成本.文章最后介绍了系统的自检方式,并给出了该系统在北京高能物理研究所谱仪大厅内的宇宙线测试结果,论证了系统的可靠性.

  1. Prototype readout electronics for the upgraded ALICE Inner Tracking System

    Science.gov (United States)

    Sielewicz, K. M.; Aglieri Rinella, G.; Bonora, M.; Ferencei, J.; Giubilato, P.; Rossewij, M. J.; Schambach, J.; Vanat, T.

    2017-01-01

    The ALICE Collaboration is preparing a major upgrade to the experimental apparatus. A key element of the upgrade is the construction of a new silicon-based Inner Tracking System containing 12 Gpixels in an area of 10 m2. Its readout system consists of 192 readout units that control the pixel sensors and the power units, and deliver the sensor data to the counting room. A prototype readout board has been designed to test: the interface between the sensor modules and the readout electronics, the signal integrity and reliability of data transfer, the interface to the ALICE DAQ and trigger, and the susceptibility of the system to the expected radiation level.

  2. Trigger and readout electronics for the Phase-I upgrade of the ATLAS forward muon spectrometer

    CERN Document Server

    Moschovakos, Paris; The ATLAS collaboration

    2017-01-01

    The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas and small strip Thin Gap Chambers conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger and tracking...

  3. Trigger and Readout Electronics for the Phase-I Upgrade of the ATLAS Forward Muon Spectrometer

    CERN Document Server

    Moschovakos, Paris; The ATLAS collaboration

    2017-01-01

    The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger ...

  4. A reconfigurable image tube using an external electronic image readout

    Science.gov (United States)

    Lapington, J. S.; Howorth, J. R.; Milnes, J. S.

    2005-08-01

    We have designed and built a sealed tube microchannel plate (MCP) intensifier for optical/NUV photon counting applications suitable for 18, 25 and 40 mm diameter formats. The intensifier uses an electronic image readout to provide direct conversion of event position into electronic signals, without the drawbacks associated with phosphor screens and subsequent optical detection. The Image Charge technique is used to remove the readout from the intensifier vacuum enclosure, obviating the requirement for additional electrical vacuum feedthroughs and for the readout pattern to be UHV compatible. The charge signal from an MCP intensifier is capacitively coupled via a thin dielectric vacuum window to the electronic image readout, which is external to the sealed intensifier tube. The readout pattern is a separate item held in proximity to the dielectric window and can be easily detached, making the system easily reconfigurable. Since the readout pattern detects induced charge and is external to the tube, it can be constructed as a multilayer, eliminating the requirement for narrow insulator gaps and allowing it to be constructed using standard PCB manufacturing tolerances. We describe two readout patterns, the tetra wedge anode (TWA), an optimized 4 electrode device similar to the wedge and strip anode (WSA) but with a factor 2 improvement in resolution, and an 8 channel high speed 50 ohm device, both manufactured as multilayer PCBs. We present results of the detector imaging performance, image resolution, linearity and stability, and discuss the development of an integrated readout and electronics device based on these designs.

  5. The CMS silicon strip tracker and its electronic readout

    CERN Document Server

    Friedl, M

    2001-01-01

    The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m sup 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. I have modeled the charge collection in silicon detectors which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolut...

  6. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  7. System Electronics for the ATLAS Upgraded Strip Detector

    CERN Document Server

    Affolder, T; The ATLAS collaboration; Clark, A; Dabrowskic, W; Dewitt, J; Diez Cornell, S; Dressdant, N; Fadeyev, V; Farthouat, P; Ferrere, D; Greenall, A; Grillo, A; Kaplon, J; Key-Charriere, M; La Marra, D; Lipeles, E; Lynn, D; Newcomer, M; Pereirab, F; Phillips, P; Spencer, E; Swientekc, K; Warren, M; Weidberg, A

    2013-01-01

    The basic concept of the front-end system of the Silicon Strip Detector in the Atlas Detector upgraded for the HL-LHC is being elaborated and proposed. The readout electronics of this new detector is based on front-end chips (ABC130), Hybrid Controller chips (HCC) and End of Stave Controller chips (EOSC). This document defines the basic functionality of the front-end system and of the different ASICs.

  8. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  9. SR front ends of VEPP-4M storage ring

    CERN Document Server

    Fedotov, M G; Kuz'minykh, V S; Mironenko, L A; Mishnev, S I; Panchenko, V E; Protopopov, I Ya; Rachkova, V V; Rukhlyada, L P; Selivanov, A N

    2001-01-01

    The VEPP-4M storage ring system of SR front ends is described. SR is released by means of 14 front ends. Eleven of them are intended for beamlines of experimental stations. One front end is technical. For the permanent stabilization of an orbit of a beam with respect to a coordinate and angle in the vertical direction, two monitoring front ends are used. They take out SR from emission regions, which are at a large distance from one another.

  10. Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

    CERN Document Server

    Chen, H; The ATLAS collaboration

    2011-01-01

    The ATLAS experiment is one of the two general-purpose detectors designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS (and its LAr Calorimeters) has been operating and collecting p-p collisions at LHC since 2009. The on-detector electronics (front-end) part of the current readout electronics of the calorimeters measures the ionization current signals by means of preamplifiers, shapers and digitizers and then transfers the data to the off-detector electronics (back-end) for further elaboration, via optical links. Only the data selected by the level-1 calorimeter trigger system are transferred, achieving a bandwidth reduction to 1.6 Gbps. The analog trigger sum sig...

  11. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS Liquid Argon (LAr) Calorimeters will be improved for the Phase- I luminosity upgrade of the LHC, to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back- end electronics. In order to evaluate technical and performance aspects, a demonstrator system has been set up, many off-detector tests have been done. Analog signal parameters including the noise and cross-talk, as well as digital signal treatment, high speed data transmission have been measured and verified. After a series of tests, the demonstrator system has been installed on the ATLAS detector before the LHC run-2.

  12. Single Event Upsets in SRAM FPGA based readout electronics for the Time Projection Chamber in the ALICE experiment

    CERN Document Server

    Røed, K; Helstrup, H; Natås, T

    2009-01-01

    Single Event Upsets in SRAM FPGA based readout electronics for the Time Projection Chamber in the ALICE experiment irradiation test results have been used to predict the single event upset rate expected during operation in the ALICE experiment. Due to the number of FPGAs utilized in the TPC front-end electronics, single event upsets can be a reliability concern. In order to reduce the probability of system malfunction, a reconfiguration solution was developed that enables the possibility to clear single event upsets in the configuration memory of the FPGA. Irradiation test results show that combined with additional system level mitigation techniques, this reconfiguration solution can be used to finally reduce the functional failure rate of the FPGA. Because irradiation testing can be time consuming, costly and sometimes even technically difficult, a software based fault injection solution has been implemented without any modification to the existing hardware setup. It provides an alternative and possibly syst...

  13. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\

  14. Test Of The CMS Microstrip Silicon Tracker Readout And Control

    CERN Document Server

    Zghiche, A; Civinini, C; Coughlan, J; Drouhin, F; Figueiredo, P; Fiore, L; Furtjes, A; Giassi, A; Gutleber, J; Ljuslin, C; Loreti, M; Maazouzi, C; Marchioro, A; Marinelli, N; Mattig, P M; Parthipan, T; Paillard, C; Siegrist, P; Silvestris, L; Tsirou, A; Verdini, P G; Walsham, P; Wittmer, B

    2000-01-01

    The Microstrip Silicon tracker of the CMS detector is designed to provide robust particle tracking and vertex reconstruction within a strong magnetic field in the high luminosity environment of the LHC. The Tracker readout system employs Front End Driver cards to digitize and buffer the analogue data arriving via optical links from on detector pipeline chips. The control Chain of the front-end electronic is built to operate via optical fibers in order to shield the communications from the outside noise. Components close to the final design have been assembled to be tested in the X5 beam area at CERN where a dedicated 25ns temporal structrure beam has been made available by the SPS. This paper describes the hardware and the software developed for readout and control of data acquired by the front-end electronics operating at 40 MHz. Some preliminary results of the tests performed in the 25ns beam are also given.

  15. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  16. Low-Cost Ratiometric Front-End for Industrial PRT Applications

    Science.gov (United States)

    Smorgon, D.; Fernicola, V. C.; Coslovi, L.

    2011-12-01

    Cost, size, speed, and measurement range limitations make the resistance bridge not always suitable for temperature measurements with platinum resistance thermometers (PRTs) in industrial applications. However, high-accuracy resistance thermometer systems are often needed in many industrial applications, where measurement performances comparable to resistance bridges are often needed at a lower cost and size. A tiny, portable, ratiometric front-end exploiting a 24-bit analog-to-digital converter (ADC) with Σ Δ modulator is described. It was designed to measure the resistance ratio between a 100 Ω industrial PRT (IPRT) and a reference resistor with repeatability to within a few parts in 106. Its small size makes it ideal for integration in the stem-handle assembly of a thermometric probe, enabling an early transmission of measurement data in digital form. The ADC-based system design, development, and performance testing are discussed. The system was investigated in the resistance ratio range from about 4 × 10-3 to 5 × 10-2. Furthermore, a comparison between the system performance and a commercial AC resistance bridge was carried out and the results reported in this paper. An accurate thermometer for industrial applications resulted from the above developments. The compactness of the devices enabled an implementation of the `smart sensor' concept in the measurement chain, where the front-end electronics was placed inside the IPRT handle together with an integrated memory to hold device identification, calibration coefficients, and the associated uncertainty. All data are transmitted to the readout module and are available to the user at a 5 Hz update rate for further analysis.

  17. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  18. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  19. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS Liquid Argon Calorimeters are foreseen to be improved for the Phase-I luminosity upgrade of the LHC, in 2019, in order to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being developed, with the intention of installing it on the ATLAS detector for operation during the data-taking period beginning in 2015. Results from system tests of the analog signal treatment, the trigger digitizer, the optical signal transmission and the FPGA-based back-end modules will be reported.

  20. Front End Schaltung zur Online Auswertung von EKG-Signalen

    Directory of Open Access Journals (Sweden)

    E. Ayari

    2007-06-01

    Full Text Available Ein mobiles EKG-System zur Online Auswertung von EKG-Signalen wird dargestellt. Die Auswertung beruht auf ein energiesparendes Verfahren, das den Vorteil einer zulässigen Unterabtastung des Signals bietet und eine Interaktion zwischen der messenden Elektronik und dem funkgebundenen Auswertungsrechner ermöglicht. Diese Interaktion besteht darin, sowohl die Front End Schaltung im EKG-Sensor als auch den im ATmega8L eingebetteten A/D-Wandler vom Auswertungsrechner zu steuern und den Datenbedarf des Rechners dynamisch an die Erfordernisse des Analyseprogramms anzupassen. Das entwickelte EKG-System liefert erfolgreiche Charakterisierungen erfasster Elektrokardiogramme.

    A mobile ecg-system for an online analysis of electrocardiogram signals is presented. The analysis is based on an energy-saving procedure, which offers the advantage of an acceptable undersampling of the signal, and which allows an interaction between the measuring electronic and the radio-bound analysis-computer. In this interaction both the front-end circuit in the ecg-sensor and the A/D converter, which is embedded in the ATmega8L, are steered by the analysis computer. The data requirement of the computer is also dynamically adapted to the requirements of the analysis-program. The developed ecg-system supplies successful characterisations of measured electrocardiograms.

  1. Highly Integrated Mixed-Mode Electronics for the readout of Time Projection Chambers

    CERN Document Server

    França Santos, Hugo Miguel; Musa, Luciano

    Time Projection Chambers (TPCs) are one of the most prevalent particle trackers for high-energy physics experiments. Future planed TPCs for the International Linear Collider (ILC) and the Compact Linear Collider (CLIC) entail very high spatial resolution in large gas volumes, but impose low material budget for the end caps of the TPC cylinder. This constraint is not accomplished with the state-of-the-art front-end electronics because of its unsuited relatively large mass and of its associated water cooling system. To reach the required material budget, highly compact and power efficient dedicated TPC front-end electronics should be developed. This project aims at re-designing the different electronic elements with significant improvements in terms of performance, power efficiency and versatility, and developing an integrated circuit that merges all components of the front-end electronics. This chip ambitions a large volume production at low unitary cost and its employment in multiple detectors. The design of ...

  2. Test Results of the ALICE SDD Electronic Readout Prototypes

    CERN Document Server

    Mazza, G; Anelli, G; Bonazzola, G C; Cavagnino, D; Cerello, P G; De Remigis, P; Falchieri, D; Gabrielli, A; Gandolfi, E; Giubellino, P; Masetti, M; Montaño-Zetina, L M; Nouais, D; Rivetti, A; Tosello, F; Werbrouck, A E; Wheadon, R

    2000-01-01

    The first prototypes of the front-end electronics of the ALICE silicon driftdetectors have been designed and tested. The integrated circuits have been designed using state of the art technologies and, for the analog parts, with radiation-tolerantdesign techniques. In this paper, the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owingto the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a toleranceto a radiation dose much higher than the one foreseen for the ALICE environment.(Abstract only available, full text to follow).

  3. Radiation Tolerant Electronics and Digital Processing for the Phase-1 Readout Upgrade of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Milic, Adriana; The ATLAS collaboration

    2015-01-01

    The high luminosities of $L > 10^{34} cm^{-2} s^{-1}$ at the Large Hadron Collider (LHC) at CERN produce an intense radiation environment that the detectors and their electronics must withstand. The ATLAS detector is a multi-purpose apparatus constructed to explore the new particle physics regime opened by the LHC. Of the many decay particles observed by the ATLAS detector, the energy of the created electrons and photons is measured by a sampling calorimeter technique that uses Liquid Argon (LAr) as its active medium. The front end (FE) electronic readout of the ATLAS LAr calorimeter located on the detector itself consists of a combined analog and digital processing system. In order to exploit the higher luminosity while keeping the same trigger bandwidth of 100 kHz, higher transverse granularity, higher resolution and longitudinal shower shape information will be provided from the LAr calorimeter to the Level-1 trigger processors. New trigger readout electronics have been designed for this purpose, which wil...

  4. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  5. Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

    Science.gov (United States)

    Vilella, E.; Comerma, A.; Alonso, O.; Gascon, D.; Diéguez, A.

    2012-12-01

    Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to erroneous results and limit the range of detectable signals. They also increase the amount of data that has to be stored. In this work, we present a pixel based on a Geiger-mode avalanche photodiode operated in the gated mode to reduce the probability to detect noise counts interfering with photon arrival events. The readout circuit is based on a two grounds scheme to enable low reverse bias overvoltages and consequently lessen the dark count rate. Experimental characterization of the fabricated pixel with the HV-AMS 0.35 μm standard technology is also presented in this article.

  6. Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

    Energy Technology Data Exchange (ETDEWEB)

    Vilella, E., E-mail: evilella@el.ub.es [Department of Electronics, University of Barcelona (UB) Marti i Franques 1, 08028 Barcelona (Spain); Comerma, A. [Department of Structure and Constituents of Matter, University of Barcelona (UB) Marti i Franques 1, 08028 Barcelona (Spain); Alonso, O. [Department of Electronics, University of Barcelona (UB) Marti i Franques 1, 08028 Barcelona (Spain); Gascon, D. [Department of Structure and Constituents of Matter, University of Barcelona (UB) Marti i Franques 1, 08028 Barcelona (Spain); Dieguez, A. [Department of Electronics, University of Barcelona (UB) Marti i Franques 1, 08028 Barcelona (Spain)

    2012-12-11

    Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to erroneous results and limit the range of detectable signals. They also increase the amount of data that has to be stored. In this work, we present a pixel based on a Geiger-mode avalanche photodiode operated in the gated mode to reduce the probability to detect noise counts interfering with photon arrival events. The readout circuit is based on a two grounds scheme to enable low reverse bias overvoltages and consequently lessen the dark count rate. Experimental characterization of the fabricated pixel with the HV-AMS 0.35 {mu}m standard technology is also presented in this article.

  7. Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschätzung des Untergrundes im Zerfall $B^{0}_{s} \\to J\\Psi \\Phi$

    CERN Document Server

    Knopf, Jan

    2009-01-01

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1,6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Phi_s. It can be measured by using the golden decay m...

  8. FELIX: the detector readout upgrade of the ATLAS experiment

    CERN Document Server

    Ryu, Soo; The ATLAS collaboration

    2015-01-01

    After the Phase-I upgrade and onward, the Front-End Link eXchange(FELIX) system will be the interface between the readout system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a gateway to a commodity switched network which will use standard technologies (Ethernet or Infiniband) to communicate with data collecting and processing components. In this talk the system architecture of FELIX will be described and the testing results of the FELIX demonstrator will be presented

  9. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  10. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  11. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  12. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  13. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  14. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

  15. Self-calibrating quadrature mixing front-end for SDR

    CSIR Research Space (South Africa)

    De Witt, JJ

    2008-01-01

    Full Text Available A quadrature mixing front-end is well-suited toward software define radio (SDR) applications, due to its low complexity and the inherent flexibility that it affords the radio front-end. Its performance is, however, severely affected by gain...

  16. A micromachined surface stress sensor with electronic readout

    NARCIS (Netherlands)

    Carlen, E.T.; Weinberg, M.S.; Zapata, A.M.; Borenstein, J.T.

    2008-01-01

    A micromachined surface stress sensor has been fabricated and integrated off chip with a low-noise, differential capacitance, electronic readout circuit. The differential capacitance signal is modulated with a high frequency carrier signal, and the output signal is synchronously demodulated and filt

  17. A New Readout Electronics for the LHCb Muon Detector Upgrade

    CERN Multimedia

    Cadeddu, Sandro

    2016-01-01

    The 2018/2019 upgrade of LHCb Muon System foresees a 40 MHz readout scheme and requires the development of a new Off Detector Electronics (nODE) board that will be based on the nSYNC, a radiation tolerant custom ASIC developed in UMC 130 nm technology. Each nODE board has 192 input channels processed by 4 nSYNCs. The nSYNC is equipped with fully digital TDCs and it implements all the required functionalities for the readout: bunch crossing alignment, data zero suppression, time measurements. Optical interfaces, based on GBT and Versatile link components, are used to communicate with DAQ, TFC and ECS systems.

  18. Preparation for the upgrade of CMS Hadron Endcap Calorimeter front-end

    Science.gov (United States)

    Bychkova, O. V.; Popova, E. V.; Parygin, P. P.; Bunin, P. D.; Kalinin, A. Yu

    2017-01-01

    The hadron endcap (HE) calorimeter is one of the major sections of CMS detector, used for measurement of the hadrons energy. Phase1 upgrade of the front-end electronics components in the HE calorimeter is being prepared, in particular to improve ability to handle increased pile-up and mitigate radiation damage of optical system in the high eta region. Tests of Phase1 HE Front-end system including new photo-sensors, silicon photomultipliers (SiPM), as well as new charge integrator encoder (QIE11) were performed in the Burn-in station in b904 at CERN. In this note, analysis and measurement results for the new generation front-end electronics components are presented.

  19. Design of the NSLS-II Linac Front End Test Stand

    Energy Technology Data Exchange (ETDEWEB)

    Fliller III, R.; Johanson, M.; Lucas, M.; Rose, J.; Shaftan, T.

    2011-03-28

    The NSLS-II operational parameters place very stringent requirements on the injection system. Among these are the charge per bunch train at low emittance that is required from the linac along with the uniformity of the charge per bunch along the train. The NSLS-II linac is a 200 MeV linac produced by Research Instruments Gmbh. Part of the strategy for understanding to operation of the injectors is to test the front end of the linac prior to its installation in the facility. The linac front end consists of a 100 kV electron gun, 500 MHz subharmonic prebuncher, focusing solenoids and a suite of diagnostics. The diagnostics in the front end need to be supplemented with an additional suite of diagnostics to fully characterize the beam. In this paper we discuss the design of a test stand to measure the various properties of the beam generated from this section. In particular, the test stand will measure the charge, transverse emittance, energy, energy spread, and bunching performance of the linac front end under all operating conditions of the front end.

  20. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  1. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  2. Muon capture for the front end of a muon collider

    CERN Document Server

    Neuffer, D

    2011-01-01

    We discuss the design of the muon capture front end for a \\mu+-\\mu- Collider. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then cooled and accelerated to high energy into a storage ring for high-energy high luminosity collisions. Our initial design is based on the somewhat similar front end of the International Design Study (IDS) neutrino factory.

  3. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  4. Implementation of a 66 MHz analog memory as a front end for LHC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Munday, D.J.; Parker, M.A. (Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE (United Kingdom)); Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Gros, J.; Jarron, P.; Heijne, E.H.M.; Meddeler, G.; Pollet, L.; Santiard, J.C.; Verweij, H. (CERN, CH-1211 Geneva 23 (Switzerland)); Goessling, C.; Lisowsky, B. (Institut fuer Physik, Universitaet Dortmund, D-4600 Dortmund (Germany)); Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; La Marra, D.; Wu, X. (DPNC, Geneva University, CH-1211, Geneva 4 (Switzerland)); Moorhead, G. (School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia)); Weidberg, A. (Department of Nuclear Physics, Oxford University, Oxford (United Kingdom)); Campbell, D.; Murray, P.; Seller, P.; Stevens, R. (Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)); Beuville, E.; Rouger, M.; Teiger, J. (Centre d' Etudes Nucleaires de Saclay, F-91191 Gif-sur-Yvette (France))

    1992-02-05

    We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

  5. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  6. NIKEL_AMC: Readout electronics for the NIKA2 experiment

    CERN Document Server

    Bourrion, O; Bouly, J L; Bouvier, J; Bosson, G; Calvo, M; Catalano, A; Goupy, J; Li, C; Macías-Pérez, J F; Monfardini, A; Tourres, D; Ponchant, N; Vescovi, C

    2016-01-01

    The New Iram Kid Arrays-2 (NIKA2) instrument, dedicated to mm-wave astronomy, uses microwave kinetic inductance detectors (KID) as sensors. The three arrays installed in the camera feature a total of 3300 KID. To instrument these detectors, a specifically designed electronics, composed of 20 readout boards and hosted in three microTCA crates, has been developed. The implemented solution and the achieved performances are presented in this paper.

  7. Indico front-end: From spaghetti to lasagna

    CERN Document Server

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  8. Trigger and readout electronics for the STEREO experiment

    CERN Document Server

    Bourrion, O; Bouvier, J; Vescovi, C; Bosson, G; Helaine, V; Lamblin, J; Li, C; Montanet, F; Real, J S; Salagnac, T; Ponchant, N; Stutz, A; Tourres, D; Zsoldos, S

    2015-01-01

    The STEREO experiment will search for a sterile neutrino by measuring the anti-neutrino energy spectrum as a function of the distance from the source, the ILL nuclear reactor. A dedicated electronic, hosted in a single microTCA crate, was designed for this experiment. It performs triggering in two stages with various selectable conditions, processing and readout via UDP/IPBUS on 68 photomultiplier signals continuously digitized at 250 MSPS. Additionally, for detector performance monitoring, the electronics allow on-line calibration by driving LED synchronously with the data acquisition. This paper describes the electronics requirements, architecture and the performances achieved.

  9. Fabrication of the GLAST Silicon Tracker Readout Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Baldini, Luca; Brez, Alessandro; Himel, Thomas; Johnson, R.P.; Latronico, Luca; Minuti, Massimo; Nelson, David; Sadrozinski, H.F.-W.; Sgro, Carmelo; Spandre, Gloria; Sugizaki, Mutsumi; Tajima, Hiro; Cohen Tanugi, Johann; Young, Charles; Ziegler, Marcus; /Pisa U. /INFN, Pisa /SLAC /UC, Santa Cruz

    2006-03-03

    A unique electronics system has been built and tested for reading signals from the silicon-strip detectors of the Gamma-ray Large Area Space Telescope mission. The system amplifies and processes signals from 884,736 36-cm long silicon strips in a 4 x 4 array of tower modules. An aggressive mechanical design fits the readout electronics in narrow spaces between the tower modules, to minimize dead area. This design and the resulting departures from conventional electronics packaging led to several fabrication challenges and lessons learned. This paper describes the fabrication processes and how the problems peculiar to this design were overcome.

  10. Noise limits in a front-end system based on time-over-threshold signal processing

    CERN Document Server

    Manfredi, P F; Mandelli, E; Perazzo, A; Re, V

    2000-01-01

    An analog signal processor based on the Time-over-Threshold (ToT) range compression is employed in the front-end section of the readout chip of the microstrip vertex detector for the BaBar experiment. The paper, after describing the circuit solutions that have been adopted to optimize the ToT operation, focuses on the noise aspects of the ToT processor. Comparisons are made between the signal-to-noise ratio in the linear processor preceding the ToT circuit and that obtained at the output of the entire analog channel including the ToT function.

  11. A data readout approach for physics experiments

    Institute of Scientific and Technical Information of China (English)

    HUANG Xi-Ru; CAO Ping; GAO Li-Wei; ZHENG Jia-Jun

    2015-01-01

    With increasing physical event rates and the number of electronic channels,traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane.In this paper,a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ.Features of exPlicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments.Furthermore,to guarantee the readout performance and flexibility,a standalone embedded CPU system is utilized for network protocol stack processing.To receive the customized data format and protocol from front-end electronics,a field programmable gate array (FPGA) is used for logic reconfiguration.To optimize the interface and to improve the data throughput between CPU and FPGA,a sophisticated method based on SRAM is presented in this paper.For the purpose of evaluating this high-speed readout method,a simplified readout module is designed and implemented.Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.

  12. Radiation Tolerant Electronics and Digital Processing for the Phase-I Trigger Readout Upgrade of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Milic, Adriana; The ATLAS collaboration

    2015-01-01

    The high luminosities of $\\mathcal{L} > 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$at the Large Hadron Collider (LHC) at CERN produce an intense radiation environment that the detectors and their electronics must withstand. The ATLAS detector is a multi-purpose apparatus constructed to explore the new particle physics regime opened by the LHC. Of the many decay particles observed by the ATLAS detector, the energy of the created electrons and photons is measured by a sampling calorimeter technique that uses Liquid Argon (LAr) as its active medium. The Front End (FE) electronic readout of the ATLAS LAr calorimeter located on the detector itself consists of a combined analog and digital processing system. The FE electronics were qualified for radiation levels corresponding to 10 years of LHC operations. The high luminosity running of the LHC (HL-LHC), with instantaneous luminosities of $5 \\times 10^{34} \\mathrm{cm}^ {-2} \\mathrm{s}^{-1}$ and an integrated luminosity of $3000 \\ \\mathrm{fb}^{-1}$ will exceed these d...

  13. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  14. The front-end chip of the SuperB SVT detector

    Energy Technology Data Exchange (ETDEWEB)

    Giorgi, F., E-mail: giorgi@bo.infn.it [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università degli Studi di Bergamo (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pavia (Italy); Fabbri, L.; Gabrielli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Pellegrini, G.; Sbarra, C. [Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Berra, A.; Lietti, D.; Prest, M. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Wilson, F. [STFC Rutherford Appleton Laboratory, Harwell Oxford, Didcot OX11 0QX (United Kingdom); Beck, G.; Morris, J. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); and others

    2013-08-01

    The asymmetric e{sup +}e{sup −} collider SuperB is designed to deliver a high luminosity, greater than 10{sup 36}cm{sup −2}s{sup −1}, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  15. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  16. A new electronic read-out for the YAPPET scanner

    CERN Document Server

    Damiani, C; Malaguti, R; Guerra, A D; Domenico, G D; Zavattini, G

    2002-01-01

    A small animal PET-SPECT scanner (YAPPET) prototype was built at the Physics Department of the Ferrara University and is presently being used at the Nuclear Medicine Department for radiopharmaceutical studies on rats. The first YAPPET prototype shows very good performances, but needs some improvements before it can be fully used for intensive radiopharmaceutical research. The main problem of the actual prototype is its heavy electronics, based on NIM and CAMAC standard modules. For this reason a new, compact read-out electronics was developed and tested. The results of a first series of tests made on the first prototype will be presented in the paper.

  17. Tests of CMS Phase 1 Pixel Upgrade Back-End Electronics

    Science.gov (United States)

    Kilpatrick, Matthew

    2016-03-01

    The CMS detector will be upgraded so that it can handle the higher instantaneous luminosity of the 13-14 TeV collisions. The Phase 1 Pixel detector will experience a higher density of particle interactions requiring new front-end and read-out electronics. A front-end pixel data emulator was developed to validate the back-end readout electronics prior to installation and operation. A FPGA-based design emulates 400 Mbps data patterns from the front-end read-out chips and will be used to confirm that each Front End Driver (FED) can correctly decode and process the expected data patterns and error conditions. A FED test bench using the emulator can produce LHC-like conditions for stress testing FED hardware, firmware and online software. The design of the emulator and initial test results will be reported.

  18. Characterization of the JUDIDT Readout Electronics for Neutron Detection

    CERN Document Server

    Fabbri, R; Engels, R; Kemmerling, G; van Waasen, S; Juelich, Forschungszentrum

    2013-01-01

    The Group for the development of neutron and gamma detectors in the Central Institute of Engineering, Electronics and Analytics (ZEA-2) at Forschungszentrum Juelich (FZJ) has developed, in collaboration with European institutes, an Anger Camera prototype for improving the impact point reconstruction of neutron tracks. The detector is a chamber filled with $^3He+CF_4$ gas for neutron capture and subsequent production of a tritium and a proton. The energy deposition by the ions gives rise to drifting electrons with an avalanche amplification as they approach a micro-strip anode structure. The scintillating light, generated during the electron drift and avalanche stage, is collected by four vacuum photomultipliers. The position reconstruction is performed via software algorithms. The JUDIDT readout electronics was modified at ZEA-2 to cope with the data acquisition requirements of the prototype. The results of the commissioning of the electronics are here presented and commented.

  19. ALMA North American Integration Center Front-End Test System

    CERN Document Server

    Ediss, Geoffrey A; Crady, Kirk; Gaines, Erik; McLeod, Morgan; Morris, Greg; Williams, Rick; Perfetto, Antonio; Webber, John; 10.1007/s10762-010-9688-y

    2010-01-01

    The Atacama Large Millimeter/submillimeter (ALMA) Array Front End (FE) system is the first element in a complex chain of signal receiving, conversion, processing and recording. 70 Front Ends will be required for the project. The Front End is designed to receive signals in ten different frequency bands. In the initial phase of operations, the antennas will be fully equipped with six bands. These are Band 3 (84-116 GHz), Band 4 (125-163 GHz), Band 6 (211-275 GHz), Band 7 (275-373 GHz), Band 8 (385-500 GHz) and Band 9 (602-720 GHz). It is planned to equip the antennas with the missing bands at a later stage of ALMA operations, with a few Band 5 (163-211 GHz) and Band 10 (787-950 GHz) receivers in use before the end of the construction project. The ALMA Front End is far superior to any existing receiver systems; spin-offs of the ALMA prototypes are leading to improved sensitivities in existing millimeter and submillimeter observatories. The Front End units are comprised of numerous elements, produced at different...

  20. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  1. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    Science.gov (United States)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-02-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  2. Readout Electronics for BGO Calorimeter of DAMPE: Status during the First Half-year after Launching

    Science.gov (United States)

    Ma, Siyuan; Feng, Changqing; Zhang, Deliang; Wang, Qi

    2016-07-01

    The DAMPE (DArk Matter Particle Explorer) is a scientic satellite which was successfully launched into a 500 Km sun-synchronous orbit, on December 17th, 2015, from the Jiuquan Satellite Launch Center of China. The major scientific objective of DAMPE mission is indirect searching for dark matter by observing high energy primary cosmic rays, especially positrons/electrons and gamma rays with an energy range from 5 GeV to 10 TeV. The BGO (Bismuth Germanate Oxide) calorimeter, which is a critical sub-detector of DAMPE payload, was developed for measuring the energy of cosmic particles, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information. It is composed of 308 BGO crystal logs, with the size of 2.5cm*2.5cm*60cm for each log to form a total absorption electromagnetic calorimeter. All the BGO logs are stacked in 14 layers, with each layer consisting of 22 BGO crystal logs and each log is viewed by two Hamamatsu R5610A PMTs (photomultiplier tubes), from both sides respectively. Each PMT incorporates a three dynode pick off to achieve a large dynamic range, which results in 616 PMTs and 1848 signal channels. The main function of readout electronics system, which consists of 16 FEE(Front End Electronics) modules, is to precisely measure the charge of PMT signals and providing "hit" signals. The hit signals are sent to the trigger module of PDPU (Payload Data Process Unit) to generate triggers for the payload. The calibration of the BGO calorimeter is composed of pedestal testing and electronic linear scale, which are executed frequently in the space after launching. The data of the testing is transmitted to ground station in the form of scientific data. The monitor status consists of temperature, current and status words of the FEE, which are measured and recorded every 16 seconds and packed in the engineering data, then transmitted to ground station. The status of the BGO calorimeter can be evaluated by the calibration

  3. The next generation Front-End Controller for the Phase-I Upgrade of the CMS Hadron Calorimeters

    Science.gov (United States)

    Costanza, F.; Behrens, U.; Campbell, A.; Karakaya, T.; Martens, I.; Melzer-Pellmann, I. A.; Sahin, M. O.

    2017-03-01

    The next generation Front-End Controller (ngFEC) is the system responsible for slow and fast control within the Phase-I Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μTCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the front-end electronics through six GBT links. The latency of the fast control signals is fixed across power cycles. Even if the direct link to a front-end module is broken, a redundancy scheme ensures a successful communication using the link to the neighboring front-end module. Thanks to the ngFEC all front-end modules can be remotely programmed using the JTAG standard protocol. The CCM server software interfaces the ngFEC to the Detector Control System which constantly monitors voltages and temperatures on the front-end electronics. This document reviews the characteristics and the development status of the ngFEC.

  4. Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

    CERN Document Server

    Gallin-Martel, L; Hostachy, J Y; Rarbi, F; Rossetto, O

    2009-01-01

    The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.

  5. The National Ignition Facility front-end laser system

    Energy Technology Data Exchange (ETDEWEB)

    Burkhart, S.C.; Beach, R.J.; Crane, J.H.; Davin, J.M.; Perry, M.D.; Wilcox, R.B.

    1995-07-07

    The proposed National Ignition Facility is a 192 beam Nd:glass laser system capable of driving targets to fusion ignition by the year 2005. A key factor in the flexibility and performance of the laser is a front-end system which provides a precisely formatted beam to each beamline. Each of the injected beams has individually controlled energy, temporal pulseshape, and spatial shape to accommodate beamline-to-beamline variations in gain and saturation. This flexibility also gives target designers the options for precisely controlling the drive to different areas of the target. The design of the Front-End laser is described, and initial results are discussed.

  6. Analog readout modules for the ZEUS microvertex detector

    CERN Document Server

    Fusayasu, T

    1999-01-01

    Analog readout modules have been developed for a silicon microvertex detector of the electron-proton collision experiment ZEUS. Analog signals kept in the front end are read out and digitized by ADCs and processed afterwards to reduce the data volume while keeping the signal information. We have developed prototype modules with 10-bit 10 MHz ADCs and digital processors built in Field Programmable Gate Arrays. Their performance was investigated.

  7. Improvement of EEG Signal Acquisition: An Electrical Aspect for State of the Art of Front End

    Directory of Open Access Journals (Sweden)

    Ali Bulent Usakli

    2010-01-01

    Full Text Available The aim of this study is to present some practical state-of-the-art considerations in acquiring satisfactory signals for electroencephalographic signal acquisition. These considerations are important for users and system designers. Especially choosing correct electrode and design strategy of the initial electronic circuitry front end plays an important role in improving the system's measurement performance. Considering the pitfalls in the design of biopotential measurement system and recording session conditions creates better accuracy. In electroencephalogram (EEG recording electrodes, system electronics including filtering, amplifying, signal conversion, data storing, and environmental conditions affect the recording performance. In this paper, EEG electrode principles and main points of electronic noise reduction methods in EEG signal acquisition front end are discussed, and some suggestions for improving signal acquisition are presented.

  8. All-Dielectric Photonic-Assisted Radio Front-End Technology

    Science.gov (United States)

    Ayazi, Hossein Ali

    The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

  9. Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

    OpenAIRE

    Vilella Figueras, Eva; Comerma Montells, Albert; Alonso Casanovas, Oscar; Gascón Fora, David; Diéguez Barrientos, Àngel

    2011-01-01

    Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to er...

  10. Low background signal readout electronics for the MAJORANA DEMONSTRATOR

    Energy Technology Data Exchange (ETDEWEB)

    Guinn, I.; Buuck, M.; Cuesta, C.; Detwiler, J. A.; Gruszko, J.; Leon, J.; Robertson, R. G. H. [Center for Experimental Nuclear Physics and Astrophysics, and Department of Physics, University of Washington, Seattle, WA (United States); Abgrall, N.; Bradley, A. W.; Chan, Y-D.; Mertens, S.; Poon, A. W. P. [Nuclear Science Division, Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Arnquist, I. J.; Hoppe, E. W.; Kouzes, R. T.; LaFerriere, B. D.; Orrell, J. L. [Pacific Northwest National Laboratory, Richland, WA (United States); Avignone, F. T. [Department of Physics and Astronomy, University of South Carolina, Columbia, SC (United States); Oak Ridge National Laboratory, Oak Ridge, TN (United States); Baldenegro-Barrera, C. X.; Bertrand, F. E. [Oak Ridge National Laboratory, Oak Ridge, TN (United States); and others

    2015-08-17

    The MAJORANA Collaboration will seek neutrinoless double beta decay (0νββ) in {sup 76}Ge using isotopically enriched p-type point contact (PPC) high purity Germanium (HPGe) detectors. A tonne-scale array of HPGe detectors would require background levels below 1 count/ROI-tonne-year in the 4 keV region of interest (ROI) around the 2039 keV Q-value of the decay. In order to demonstrate the feasibility of such an experiment, the MAJORANA DEMONSTRATOR, a 40 kg HPGe detector array, is being constructed with a background goal of < 3 count/ROI-tonne-year, which is expected to scale down to < 1 count/ROI-tonne-year for a tonne-scale experiment. The signal readout electronics, which must be placed in close proximity to the detectors, present a challenge toward reaching this background goal. This talk will discuss the materials and design used to construct signal readout electronics with low enough backgrounds for the MAJORANA DEMONSTRATOR.

  11. Low Background Signal Readout Electronics for the MAJORANA DEMONSTRATOR

    CERN Document Server

    Guinn, I; Arnquist, I J; Avignone, F T; Baldenegro-Barrera, C X; Barabash, A S; Bertrand, F E; Bradley, A W; Brudanin, V; Busch, M; Buuck, M; Byram, D; Caldwell, A S; Chan, Y-D; Christofferson, C D; Cuesta, C; Detwiler, J A; Efremenko, Yu; Ejiri, H; Elliott, S R; Galindo-Uribarri, A; Gilliss, T; Giovanetti, G K; Goett, J; Green, M P; Gruszko, J; Guiseppe, V E; Henning, R; Hoppe, E W; Howard, S; Howe, M A; Jasinski, B R; Keeter, K J; Kidd, M F; Konovalov, S I; Kouzes, R T; LaFerriere, B D; Leon, J; MacMullin, J; Martin, R D; Meijer, S J; Mertens, S; Orrell, J L; O'Shaughnessy, C; Poon, A W P; Radford, D C; Rager, J; Rielage, K; Robertson, R G H; Romero-Romero, E; Shanks, B; Shirchenko, M; Snyder, N; Suriano, A M; Tedeschi, D; Trimble, J E; Varner, R L; Vasilyev, S; Vetter, K; Vorren, K; White, B R; Wilkerson, J F; Wiseman, C; Xu, W; Yakushev, E; Yu, C -H; Yumatov, V; Zhitnikov, I

    2015-01-01

    The MAJORANA Collaboration will seek neutrinoless double beta decay (0nbb) in 76Ge using isotopically enriched p-type point contact (PPC) high purity Germanium (HPGe) detectors. A tonne-scale array of HPGe detectors would require background levels below 1 count/ROI-tonne-year in the 4 keV region of interest (ROI) around the 2039 keV Q-value of the decay. In order to demonstrate the feasibility of such an experiment, the MAJORANA DEMONSTRATOR, a 40 kg HPGe detector array, is being constructed with a background goal of <3 counts/ROI-tonne-year, which is expected to scale down to <1 count/ROI-tonne-year for a tonne-scale experiment. The signal readout electronics, which must be placed in close proximity to the detectors, present a challenge toward reaching this background goal. This talk will discuss the materials and design used to construct signal readout electronics with low enough backgrounds for the MAJORANA DEMONSTRATOR.

  12. Low Background Signal Readout Electronics for the Majorana Demonstrator

    Energy Technology Data Exchange (ETDEWEB)

    Guinn, Ian [University of Washington; Rielage, Keith Robert [Los Alamos National Laboratory; Elliott, Steven Ray [Los Alamos National Laboratory; Xu, Wenqin [Los Alamos National Laboratory; Goett, John Jerome III [Los Alamos National Laboratory

    2015-06-11

    The MAJORANA Collaboration will seek neutrinoless double beta decay (0νββ) in 76Ge using isotopically enriched p-type point contact (PPC) high purity Germanium (HPGe) detectors. A tonne-scale array of HPGe detectors would require background levels below 1 count/ROI-tonne-year in the 4 keV region of interest (ROI) around the 2039 keV Q-value of the decay. In order to demonstrate the feasibility of such an experiment, the MAJORANA DEMONSTRATOR, a 40 kg HPGe detector array, is being constructed. The DEMONSTRATOR has a background goal of < 3 counts/ROI-tonne-year, which is expected to scale down to < 1 count/ROI-tonne-year for a one tonne experiment. The signal readout electronics, which must be placed in close proximity to the detectors, present a challenge toward reaching this background goal. This paper discusses the materials and design used to construct signal readout electronics with low enough backgrounds for the MAJORANA DEMONSTRATOR.

  13. Low Background Signal Readout Electronics for the Majorana Demonstrator

    Energy Technology Data Exchange (ETDEWEB)

    Guinn, Ian [University of Washington; Rielage, Keith Robert [Los Alamos National Laboratory; Elliott, Steven Ray [Los Alamos National Laboratory; Xu, Wenqin [Los Alamos National Laboratory; Goett, John Jerome III [Los Alamos National Laboratory

    2015-06-11

    The MAJORANA Collaboration will seek neutrinoless double beta decay (0νββ) in 76Ge using isotopically enriched p-type point contact (PPC) high purity Germanium (HPGe) detectors. A tonne-scale array of HPGe detectors would require background levels below 1 count/ROI-tonne-year in the 4 keV region of interest (ROI) around the 2039 keV Q-value of the decay. In order to demonstrate the feasibility of such an experiment, the MAJORANA DEMONSTRATOR, a 40 kg HPGe detector array, is being constructed. The DEMONSTRATOR has a background goal of < 3 counts/ROI-tonne-year, which is expected to scale down to < 1 count/ROI-tonne-year for a one tonne experiment. The signal readout electronics, which must be placed in close proximity to the detectors, present a challenge toward reaching this background goal. This paper discusses the materials and design used to construct signal readout electronics with low enough backgrounds for the MAJORANA DEMONSTRATOR.

  14. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  15. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  16. A socio-interactive framework for the fuzzy front end

    NARCIS (Netherlands)

    Smulders, Frido E.; Broek, van den Egon L.; Voort, van der Mascha C.

    2007-01-01

    This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary sociointeractive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive framework

  17. Business modelling in the fuzzy front end of innovation

    NARCIS (Netherlands)

    Limonard, A.J.P.; Berkers, F.T.H.M.; Niamut, O.A.; Bachet, T.T.; Reuver, M. de

    2011-01-01

    In this paper we address the techno-economic dilemma in the fuzzy front end of R&D consortia: how to bridge the gap between the lack of knowledge on future demand for a technology and the need to make design decisions. The problem in these types of collaborations that the business interests to devel

  18. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  19. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  20. Development of a front end controller/heap manager for PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Allen, M.D.; Musrock, M.S.; Walker, J.W.; Britton, C.L. Jr.; Wintenberg, A.L.; Young, G.R.

    1996-12-31

    A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

  1. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    CERN Document Server

    Simi, G; Batignani, G; Bettarini, S; Bondioli, M; Boscardin, M; Bosisio, L; Dalla Betta, Gian Franco; Dittongo, S; Forti, F; Giorgi, M; Gregori, P; Manghisoni, M; Morganti, M; Ratti, L; Re, V; Rizzo, G; Speziali, V; Zorzi, N

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

  2. Readout electronics development for the ATLAS silicon tracker

    Energy Technology Data Exchange (ETDEWEB)

    Borer, K. [Bern Univ. (Switzerland); Beringer, J. [Bern Univ. (Switzerland); Anghinolfi, F. [CERN, CH-1211 Geneva 23 (Switzerland); Aspell, P. [CERN, CH-1211 Geneva 23 (Switzerland); Chilingarov, A. [CERN, CH-1211 Geneva 23 (Switzerland)]|[Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Jarron, P. [CERN, CH-1211 Geneva 23 (Switzerland); Heijne, E.H.M. [CERN, CH-1211 Geneva 23 (Switzerland); Santiard, J.C. [CERN, CH-1211 Geneva 23 (Switzerland); Verweij, H. [CERN, CH-1211 Geneva 23 (Switzerland); Goessling, C. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Lisowski, B. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Reichold, A. [Institut fur Physik, Univ. Dortmund, D-4600 Dortmund (Germany); Bonino, R. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Clark, A.G. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Kambara, H. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); La Marra, D. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Leger, A. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Wu, X. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Richeux, J.P. [DPNC, University of Geneva, CH-1211 Geneva 4 (Switzerland); Taylor, G.N. [School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia); Fedotov, M. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Kuper, E. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Velikzhanin, Yu. [Budker Institute of Nuclear Physics, Novosibirsk (Russian Federation); Campbell, D. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Murray, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Seller, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)

    1995-06-01

    We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints. (orig.).

  3. Front-end chip for Silicon Photomultiplier detectors with pico-second Time-of-Flight resolution

    Science.gov (United States)

    Stankova, V.; Briggl, K.; Chen, H.; Gil, A.; Harion, T.; Munwes, Y.; Shen, W.; Schultz-Coulon, H.-C.

    2016-07-01

    A mixed-mode readout Application Specific Integrated Circuit (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM) for medical imaging and particle physics applications. The STiC3 is a 64-channel chip, with fully differential analog front-end for cross-talk and electronic noise immunity. The time and charge information from the SiPM signals are encrypted into two time stamps generated by integrated Time to Digital Converter (TDC) modules with 50 ps time binning. The TDC data is stored in an internal memory and transferred to a PC via a 160 MBit/s serial link using an 8/10 bit encoding. The chip provides an input bias tuning in a range of 0-900 mV to compensate the breakdown voltage variation of individual SiPMs. The TDC jitter together with the digital part is around 37 ps. A Coincidence Time Resolution (CTR) of 213.6 ps FWHM has been obtained with 3.1 × 3.1 × 15m2 LYSO:Ce scintillator crystals and Hamamatsu SiPM matrices (S12643-050CN(X)). Characterization measurements with the chip and its integration into the external plate of the EndoTOFPET-US prototype are presented.

  4. NIKEL_AMC: readout electronics for the NIKA2 experiment

    Science.gov (United States)

    Bourrion, O.; Benoit, A.; Bouly, J. L.; Bouvier, J.; Bosson, G.; Calvo, M.; Catalano, A.; Goupy, J.; Li, C.; Macías-Pérez, J. F.; Monfardini, A.; Tourres, D.; Ponchant, N.; Vescovi, C.

    2016-11-01

    The New Iram Kid Arrays-2 (NIKA2) instrument has recently been installed at the IRAM 30 m telescope. NIKA2 is a state-of-art instrument dedicated to mm-wave astronomy using microwave kinetic inductance detectors (KID) as sensors. The three arrays installed in the camera, two at 1.25 mm and one at 2.05 mm, feature a total of 3300 KIDs. To instrument these large array of detectors, a specifically designed electronics, composed of 20 readout boards and hosted in three microTCA crates, has been developed. The implemented solution and the achieved performances are presented in this paper. We find that multiplexing factors of up to 400 detectors per board can be achieved with homogeneous performance across boards in real observing conditions, and a factor of more than 3 decrease in volume with respect to previous generations.

  5. Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Rovati, L; Bonaiuti, M [Dipartimento di Ingegneria dell' Informazione, Universita di Modena e Reggio Emilia, Modena (Italy); Bettarini, S [Dipartimento di Fisica, Universita di Pisa and INFN Pisa, Pisa (Italy); Bosisio, L [Dipartimento di Fisica, Universita di Trieste and INFN Trieste, Trieste (Italy); Dalla Betta, G-F; Tyzhnevyi, V [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita di Trento e INFN Trento, Trento (Italy); Verzellesi, G [Dipartimento di Scienze e Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia and INFN Trento, Reggio Emilia (Italy); Zorzi, N, E-mail: giovanni.verzellesi@unimore.i [Fondazione Bruno Kessler (FBK), Trento (Italy)

    2009-11-15

    In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

  6. Single Front-End MIMO Architecture with Parasitic Antenna Elements

    Science.gov (United States)

    Yoshida, Mitsuteru; Sakaguchi, Kei; Araki, Kiyomichi

    In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

  7. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  8. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  9. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  10. Test of High Time Resolution MRPC with Different Readout Modes

    CERN Document Server

    Yang, S; Li, C; Heng, Y K; Qian, S; Chen, H F; Chen, T X; Dai, H L; Fan, H H; Liu, S B; Liu, S D; Jiang, X S; Shao, M; Tang, Z B; Zhang, H; Zhao, Z G

    2014-01-01

    In order to further enhance the particle identification capability of the Beijing Spectrometer (BESIII), it is proposed to upgrade the current end-cap time-of-flight (eTOF) detector with multi-gap resistive plate chamber (MRPC). The prototypes, together with the front end electronics (FEE) and time digitizer (TDIG) module have been tested at the E3 line of Beijing Electron Positron Collider (BEPCII) to study the difference between the single and double-end readout MRPC designs. The time resolutions (sigma) of the single-end readout MRPC are 47/53 ps obtained by 600 MeV/c proton/pion beam, while that of the double-end readout MRPC is 40 ps (proton beam). The efficiencies of three MRPC modules tested by both proton and pion beam are better than 98%. For the double-end readout MRPC, no incident position dependence is observed.

  11. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    of the staging of inno-vation processes, which focuses on the content and framing of ideas at the front end. The understanding sensitises hereby towards con-cerns of path-dependency and translations, inclu-ding trade-offs and potentialities involved in su-stainning or reframing matters of significance as part...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

  12. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  13. A new approach to front-­‐end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Borga, Andrea; The ATLAS collaboration; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Ryu, Soo; Zhang, Jinlong; Anderson, John Thomas; Boterenbrood, Hendrik; Chen, Kai; Chen, Hucheng; Drake, Gary; Donszelmann, Mark; Francis, David

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

  14. Holographic optical receiver front end for wireless infrared indoor communications.

    Science.gov (United States)

    Jivkova, S; Kavehrad, M

    2001-06-10

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver's small size, light weight, and low cost make the receiver front end a promising candidate for a user's portable equipment in broadband indoor wireless multimedia access.

  15. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  16. HDI flexible front-end hybrid prototype for the PS module of the CMS tracker upgrade

    Science.gov (United States)

    Kovacs, M.; Blanchot, G.; Gadek, T.; Honma, A.; Koliatos, A.

    2017-02-01

    The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with high-density interconnection flexible circuits that are wire bonded to silicon strip and pixel-strip sensors. The Front-End hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit technology and the parameters of the hybrids. This paper presents the Pixel-Strip (PS) mock-up hybrid in terms of testing, interconnection, fold-over, thermal properties and layout feasibility. Plans for circuit testing at operating temperature (-30o) are also presented.

  17. Electronics and readout of the UA1 uranium-TMP calorimeter

    Energy Technology Data Exchange (ETDEWEB)

    Bacci, C.; Bonino, R.; Ceradini, F.; Lacava, F.; Petrolo, E.; Tusi, A.; Veneziano, S.; Zanello, L.; Boniface, J.; Colas, J.

    1989-07-01

    The readout electronics realized for the uranium-TMP calorimeter of the UA1 experiment is presented. The main features of the electronics chain, from integration of the detector signal to the data digitization are discussed in detail. (orig.).

  18. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    Energy Technology Data Exchange (ETDEWEB)

    Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

    2015-07-15

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  19. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

    Science.gov (United States)

    Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

    2015-07-01

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  20. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Science.gov (United States)

    Fischer, P.; Comes, G.; Krüger, H.

    1999-07-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized.

  1. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Energy Technology Data Exchange (ETDEWEB)

    Fischer, P. E-mail: fischerp@physik.uni-bonn.de; Comes, G.; Krueger, H

    1999-07-11

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  2. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    CERN Document Server

    Fischer, P; Krüger, H

    1999-01-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  3. New and Efficient Neutrino Factory Front-End Design

    CERN Document Server

    Gallardo, Juan C; Kirk, Harold G; Neuffer, David V; Palmer, Robert; Paul, Kevin; Scott Berg, J

    2005-01-01

    As part of the APS Joint Study on the Future of Neutrino Physics* we have carried out detailed studies of the Neutrino Factory front-end. A major goal of the new study was to achieve equal performance to our earlier feasibility studies** at reduced cost. The optimal channel design is described in this paper. New innovations included an adiabatic buncher for phase rotation and a simplified cooling channel with LiH absorbers. The linear channel is 295 m long and produces 0.17 muons per proton on target into the assumed accelerator transverse acceptance of 30 mm and longitudinal acceptance of 150 mm.

  4. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  5. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  6. Review of the Neutrino Factory Muon Front End

    CERN Document Server

    Rogers, C

    2011-01-01

    Three major facilities have been proposed for the precision study of neutrino oscillation parameters, the Neutrino Factory, the Betabeam and the Superbeam. Of these the Neutrino Factory offers high precision measurement of oscillations parameters. The Neutrino Factory generates neutrinos by firing protons onto a target in order to produce pions. The pions decay to muons which are captured before being accelerated to 25 GeV and stored in racetrack-shaped rings where they decay to neutrinos. In this note the pion decay channel, longitudinal drift, adiabatic buncher, phase rotation and ionisation cooling system that make up the Neutrino Factory muon front end are reviewed.

  7. Instrument Front-Ends at Fermilab During Run II

    CERN Document Server

    Meyer, Thomas; Voy, Duane; 10.1088/1748-0221/6/11/T11004

    2012-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  8. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  9. The Readout Control Unit of the ALICE TPC

    CERN Document Server

    Lien, J A; Musa, L

    2004-01-01

    The ALICE Time Projection Chamber (TPC) is the main tracking detector of the central barrel of the ALICE (A Large Ion Collider) Experiment at the Large Hadron Collider (LHC), being constructed at CERN, Geneva. It is a 88 m$^{3}$ cylinder filled with gas and divided into two drift regions by the central electrode located at its axial center. The readout chambers of the TPC are multi-wire proportional chambers with cathode pad readout. About 570 000 pads are read-out by an electronics chain of amplification, digitalization and pre-processing. One of the challenges in designing the TPC for ALICE is the design of Front End Electronics (FEE) to cope with the data rates and the channel occupancy. The Readout Control Unit (RCU), which is presented in this work, is designed to control and monitor the Front End Electronics, and to collect and ship data to the High Level Trigger and the Data Acquisition System, via the Detector Data Link (DDL - optical fibre). The RCU must be capable of reading out up to 200 Mbytes/s f...

  10. Scintillating Fibre Tracker Front-End Electronics for LHCb upgrade

    CERN Multimedia

    Comerma, A

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will undergo major changes. Its components will be replaced by new technologies in order to cope with the increased hit occupancy and the higher radiation dose. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is envisaged for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. The detector will consist of 12 planes of 5 to 6 layers of 250μm fibres stacked covering a total area of 5x6m^2 . The desired spacial resolution on the reconstructed hit is 100μm. SiPMs have been adapted to the detector geometry reducing the dead area between channels. A total of 64 channels are arranged in a single die with common cathode connection and channel size of 0.23x1.32mm^2 . Two dies are packaged together with only 0.25mm of dead area between them. Radiation tolerance of such devices is ...

  11. Intelligent Front-end Electronics for Silicon photodetectors (IFES)

    Energy Technology Data Exchange (ETDEWEB)

    Sauerzopf, Clemens, E-mail: clemens.sauerzopf@oeaw.ac.at; Gruber, Lukas; Suzuki, Ken; Zmeskal, Johann; Widmann, Eberhard

    2016-05-21

    While high channel density can be easily achieved for big experiments using custom made microchips, providing something similar for small and medium size experiments imposes a challenge. Within this work we describe a novel and cost effective solution to operate silicon photodetectors such as silicon photo multipliers (SiPM). The IFES modules provide the bias voltage for the detectors, a leading edge discriminator featuring time over threshold and a differential amplifier, all on one printed circuit board. We demonstrate under realistic conditions that the module is usable for high resolution timing measurements exploiting both charge and time information. Furthermore we show that the modules can be easily used in larger detector arrays. All in all this confirms that the IFES modules are a viable option for a broad range of experiments if cost-effectiveness and small form factor are required.

  12. Intelligent Front-end Electronics for Silicon photodetectors (IFES)

    Science.gov (United States)

    Sauerzopf, Clemens; Gruber, Lukas; Suzuki, Ken; Zmeskal, Johann; Widmann, Eberhard

    2016-05-01

    While high channel density can be easily achieved for big experiments using custom made microchips, providing something similar for small and medium size experiments imposes a challenge. Within this work we describe a novel and cost effective solution to operate silicon photodetectors such as silicon photo multipliers (SiPM). The IFES modules provide the bias voltage for the detectors, a leading edge discriminator featuring time over threshold and a differential amplifier, all on one printed circuit board. We demonstrate under realistic conditions that the module is usable for high resolution timing measurements exploiting both charge and time information. Furthermore we show that the modules can be easily used in larger detector arrays. All in all this confirms that the IFES modules are a viable option for a broad range of experiments if cost-effectiveness and small form factor are required.

  13. Analog Front-End Electronics in Beam Instrumentation

    CERN Document Server

    Boscolo, A

    2005-01-01

    The work gives an overview of present and near future technological opportunities for the first analog conditioning and subsequent signal processing of sensor signal. The interactions between beam sensor capability, their signals characteristics and the system requirements are analyzed from different approaches as: full analog continuous, sampled time discrete, full digital time and amplitude discrete. Special attention will be given to the impact of measurement methods and new devices in circuits and instrumentation architecture design, especially from the metrological point of view. A lot of measurement methods and related systems have been developed in order to overcome technological drawbacks and to reach the best cost-performances ratio. By a system revamping, some of these still now show the capability of reaching the actual technological limits in a simpler way in many applications as: ADC, linear and non linear signal processing, ultra high speed logic, etc. These methods could be carried out by the n...

  14. Novel Front-end Electronics for Time Projection Chamber Detectors

    OpenAIRE

    2012-01-01

    Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET). En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente c...

  15. READOUT SYSTEM FOR ARRAYS OF FRISCH-RING CDZNTE DETECTORS.

    Energy Technology Data Exchange (ETDEWEB)

    CUI, Y.; BOLOTNIKOV, A.E.; CAMARDA, G.S.; DE GERONIMO, G.; O' CONNOR, P.; JAMES, R.B.; KARGAR, A.; HARRISON, M.J.; MCGREGOR, D.S.

    2006-10-29

    Frisch-ring CdZnTe detectors have demonstrated good energy resolution for identifying isotopes, <1% FWHM at 662 keV, and good efficiency for detecting gamma rays. We will fabricate and test at Brookhaven National Laboratory an integrated module of a 64-element array of 6 x 6 x 12 mm{sup 3} Frisch-ring detectors, coupled with a readout electronics system. It supports 64 readout channels, and includes front-end electronics, signal processing circuit, USB interface and high-voltage power supply. The data-acquisition software is used to process the data stream, which includes amplitude and timing information for each detected event. This paper describes the design and assembly of the detector modules, readout electronics, and a conceptual prototype system. Some test results are also reported.

  16. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  17. Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

    Science.gov (United States)

    Monteil, E.; Demaria, N.; Pacher, L.; Rivetti, A.; Da Rocha Rolo, M.; Rotondo, F.; Leng, C.

    2016-03-01

    The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

  18. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    AUTHOR|(CDS)2069646; Abbas, M.; Abbrescia, M.; Abdelalim, A.A.; Abi Akl, M.; Aboamer, O.; Acosta, D.; Ahmad, A.; Ahmed, W.; Ahmed, W.; Aleksandrov, A.; Aly, R.; Altieri, P.; Asawatangtrakuldee, C.; Aspell, P.; Assran, Y.; Awan, I.; Bally, S.; Ban, Y.; Banerjee, S.; Barashko, V.; Barria, P.; Bencze, G.; Beni, N.; Benussi, L.; Bhopatkar, V.; Bianco, S.; Bos, J.; Bouhali, O.; Braghieri, A.; Braibant, S.; Buontempo, S.; Calabria, C.; Caponero, M.; Caputo, C.; Cassese, F.; Castaneda, A.; Cauwenbergh, S.; Cavallo, F.R.; Celik, A.; Choi, M.; Choi, S.; Christiansen, J.; Cimmino, A.; Colafranceschi, S.; Colaleo, A.; Conde Garcia, A.; Czellar, S.; Dabrowski, M.M.; De Lentdecker, G.; De Oliveira, R.; de Robertis, G.; Dildick, S.; Dorney, B.; Elmetenawee, W.; Endroczi, G.; Errico, F.; Fenyvesi, A.; Ferry, S.; Furic, I.; Giacomelli, P.; Gilmore, J.; Golovtsov, V.; Guiducci, L.; Guilloux, F.; Gutierrez, A.; Hadjiiska, R.M.; Hassan, A.; Hauser, J.; Hoepfner, K.; Hohlmann, M.; Hoorani, H.; Iaydjiev, P.; Jeng, Y.G.; Kamon, T.; Karchin, P.; Korytov, A.; Krutelyov, S.; Kumar, A.; Kim, H.; Lee, J.; Lenzi, T.; Litov, L.; Madorsky, A.; Maerschalk, T.; Maggi, M.; Magnani, A.; Mal, P.K.; Mandal, K.; Marchioro, A.; Marinov, A.; Masod, R.; Majumdar, N.; Merlin, J.A.; Mitselmakher, G.; Mohanty, A.K.; Mohamed, S.; Mohapatra, A.; Molnar, J.; Muhammad, S.; Mukhopadhyay, S.; Naimuddin, M.; Nuzzo, S.; Oliveri, E.; Pant, L.M.; Paolucci, P.; Park, I.; Passeggio,G.; Pavlov, B.; Philipps, B.; Piccolo, D.; Postema, H.; Puig Baranac, A.; Radi, A.; Radogna, R.; Raffone, G.; Ranieri, A.; Rashevski, G.; Riccardi, C.; Rodozov, M.; Rodrigues, A.; Ropelewski, L.; RoyChowdhury, S.; Ryu, G.; Ryu, M.S.; Safonov, A.; Salva, S.; Saviano, G.; Sharma, A.; Sharma, A.; Sharma, R.; Shah, A.H.; Shopova, M.; Sturdy, J.; Sultanov, G.; Swain, S.K.; Szillasi, Z.; Talvitie, J.; Tamma, C.; Tatarinov, A.; Tuuva, T.; Tytgat, M.; Vai, I.; Van Stenis, M.; Venditti, R.; Verhagen, E.; Verwilligen, P.; Vitulo, P.; Volkov, S.; Vorobyev, A.; Wang, D.; Wang, M.; Yang, U.; Yang, Y.; Yonamine, R.; Zaganidis, N.; Zenoni, F.; Zhang, A.

    2016-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  19. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  20. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Energy Technology Data Exchange (ETDEWEB)

    Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

    2016-07-11

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

  1. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  2. Testing of the front-end hybrid circuits for the CMS Tracker upgrade

    Science.gov (United States)

    Gadek, T.; Blanchot, G.; Honma, A.; Kovacs, M.; Raymond, M.; Rose, P.

    2017-01-01

    The upgrade of the CMS Tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high-density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  3. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2016-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  4. The Cms Ecal Readout Architecture and the Clock and Control System

    Science.gov (United States)

    Benetta, R.; Gastal, M.; Hansen, M.; Kloukinas, K.; Ljuslin, C.; Marchioro, A.; Nash, J.; Sharp, P.; Hall, G.; Raymond, M.; Crooks, J.; French, M.; Dejardin, M.; Faure, J. L.; Djambazov, L.; Lusterman, W.

    2005-02-01

    This paper gives an overview of the readout and control system for the CMS Electromagnetic Calorimeter (ECAL) with emphasis on the newly developed ASIC chipset for the front end electronics and the off detector clock and control system. A newly developed ASIC chipset for the front-end electronics using a 0.25 μm radiation tolerant CMOS technology made feasible the implementation of a significant amount of functionality on the detector electronics and helped in keeping the optical fiber count between the front-end and the off-detector electronics at an acceptable level. A Multi-Gain Pre-Amplifier ASIC (MGPA) and a 12-bit, 40MSPS, quad channel ADC have been developed using an architecture of multiple gain ranges that spans the overall required dynamic range. A multifunctional digital ASIC, named FENIX, implements all the necessary DSP functionality needed for the generation of the Trigger Primitives, as well as the functionality needed for the event readout, namely the digital pipelines and the primary event buffers. For the off-detector electronics a set of VME boards have been developed. The Trigger Concentrator Card (TCC) that collects the front end trigger primitives, the Data Concentrator Card (DCC) that receives the crystal data and the Clock and Control System board (CCS) that distributes the fast timing signals to all parts of the system and provides a bidirectional communication path with the front-end electronics for slow control operation. The functionality and the implementation of the CCS board are described in detail.

  5. Proposal of Readout Electronics for CSNS-WNS BaF2 Detector

    CERN Document Server

    Zhang, Deliang; Wang, Qi; He, Bing; Zhang, Yaxi; Qi, Xincheng; Yu, Tao; An, Qi

    2016-01-01

    BaF2 (Barium fluoride) detector is one of the experiment facilities at the under construction CSNS-WNS (White Neutron Source at China Spallation Neutron Source). It is designed for precisely measuring (n,gamma) cross section with total 92 crystal elements and completely 4 pi steradian coverage. In this proposal for readout electronics, waveform digitizing technique with 1GSps sampling rate and 12-bit resolution is adopted to precisely capture the detector signal. To solve the problem of massive data readout and processing, the readout electronics system is designed into a distributed architecture with 4 PXIe crates. The digitized detector's signal is concentrated to PXIe crate controller through PCIe bus on backplane and transmitted to data acquisition system over Gigabit Ethernet in parallel. Besides, clock and trigger can be fanned out synchronously to each electronic channel over a high-precision distributing network. Test results showed that the prototype of the readout electronics system achieved good pe...

  6. Development of ATLAS Liquid Argon Calorimeter Read-out Electronics for the HL-LHC

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2015-01-01

    The high-luminosity phase of the Large Hadron Collider will provide a 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon Calorimeters and their read-out system. An improved trigger system with higher acceptance rate and longer latency and a better radiation tolerance require an upgrade of the read-out electronics. Concepts for the future read-out of the 183.000 calorimeter channels at 40-80 MHz and 16 bit dynamic range, and the development of radiation tolerant, low noise, low power and high-bandwidth electronic components will be presented.

  7. Electronics design of a PET detector module with APD array

    CERN Document Server

    Wang Yong

    2002-01-01

    The author summarizes the advantages of APD-array for using in PET scanner. The front-end electronics for an experimental APD detector module was built and tested. According to the characteristics of APD-array and the demands of the signal readout in PET scanner, the full electronics system of an APD detector module was designed and presented in detail

  8. Front-end ASIC for pixilated wide bandgap detectors

    Science.gov (United States)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  9. Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Ma, Hong; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34/cm^2/s. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger chan...

  10. Upgrade readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Yamanaka, T; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

  11. Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Yamanaka, T; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

  12. Neural-network front ends in unsupervised learning.

    Science.gov (United States)

    Pedrycz, W; Waletzky, J

    1997-01-01

    Proposed is an idea of partial supervision realized in the form of a neural-network front end to the schemes of unsupervised learning (clustering). This neural network leads to an anisotropic nature of the induced feature space. The anisotropic property of the space provides us with some of its local deformation necessary to properly represent labeled data and enhance efficiency of the mechanisms of clustering to be exploited afterwards. The training of the network is completed based upon available labeled patterns-a referential form of the labeling gives rise to reinforcement learning. It is shown that the discussed approach is universal and can be utilized in conjunction with any clustering method. Experimental studies are concentrated on three main categories of unsupervised learning including FUZZY ISODATA, Kohonen self-organizing maps, and hierarchical clustering.

  13. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  14. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  15. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... of development. We will through an in-depth case study demonstrate how this constitution of development is enacted as best practice for development., making it difficult to bring forth radical ideas. Furthermore we will describe how navigation and (re)enactment of the constitution of development are practiced...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...

  16. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  17. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  18. A software-radio front-end for microwave applications

    Science.gov (United States)

    Streifinger, M.; Müller, T.; Luy, J.-F.; Biebl, E. M.

    2003-05-01

    In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  19. Small-Scale Readout Systems Prototype for the STAR PIXEL Detector

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal A.; Besson, Auguste; Colledani, Claude; Dorokhov, Andrei; Dulinski, Wojciech; Greiner, Leo C.; Himmi, Abdelkader; Hu, Christine; Matis, Howard S.; Ritter, Hans Georg; Rose, Andrew; Shabetai, Alexandre; Stezelberger, Thorsten; Sun, Xiangming; Thomas, Jim H.; Valin, Isabelle; Vu, Chinh Q.; Wieman, Howard H.; Winter, Marc

    2008-10-01

    A prototype readout system for the STAR PIXEL detector in the Heavy Flavor Tracker (HFT) vertex detector upgrade is presented. The PIXEL detector is a Monolithic Active Pixel Sensor (MAPS) based silicon pixel vertex detector fabricated in a commercial CMOS process that integrates the detector and front-end electronics layers in one silicon die. Two generations ofMAPS prototypes designed specifically for the PIXEL are discussed. We have constructed a prototype telescope system consisting of three small MAPS sensors arranged in three parallel and coaxial planes with a readout system based on the readout architecture for PIXEL. This proposed readout architecture is simple and scales to the size required to readout the final detector. The real-time hit finding algorithm necessary for data rate reduction in the 400 million pixel detector is described, and aspects of the PIXEL system integration into the existing STAR framework are addressed. The complete system has been recently tested and shown to be fully functional.

  20. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    Directory of Open Access Journals (Sweden)

    Virgilio Valente

    2016-07-01

    Full Text Available This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR channels and four voltage-readout (VR channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis.

  1. READOUT ELECTRONICS FOR A HIGH-RATE CSC DETECTOR

    Energy Technology Data Exchange (ETDEWEB)

    OCONNOR,P.; GRATCHEV,V.; KANDASAMY,A.; POLYCHRONAKOS,V.; TCHERNIATINE,V.; PARSONS,J.; SIPPACH,W.

    1999-09-25

    A readout system for a high-rate muon Cathode Strip Chamber (CSC) is described. The system, planned for use in the forward region of the ATLAS muon spectrometer, uses two custom CMOS integrated circuits to achieve good position resolution at a flux of up to 2,500 tracks/cm{sup 2}/s.

  2. Star Time of Flight Readout Electronics, Daq, and Cosmic Ray Test Stand

    Science.gov (United States)

    Schambach, J.; Hoffmann, G.; Kajimoto, K.; Bridges, L.; Eppley, G.; Liu, J.; Llope, B.; Nussbaum, T.; Mesa, C.

    The new Time-of-Flight (TOF) subsystem for STAR at RHIC will have 3840 6-pad Multigap Resistive Plate Chambers (MRPC) distributed over 120 trays. Each tray contains 192 channels and three types of electronics cards: “TINO”, “TDIG” and “TCPU”. Every 30 trays send data to a “THUB” card that interfaces to STAR trigger and transmits data over fiber to a STAR DAQ fiber receiver. TINO contains analog front end electronics based on the CERN/LAA NINO custom IC. TDIG digitizes the data using the CERN HPTDC ASIC. TCPU formats and buffers the digital information. A cosmic ray test system comprised of three plastic scintillators, 4 MRPC modules, and TOF prototype electronics is used to determine the timing resolution to be achieved for the entire TOF system. Overall timing resolution of 80 - 110 ps has been achieved.

  3. Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

    CERN Document Server

    Horn, Philipp; The ATLAS collaboration

    2017-01-01

    The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40-80 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. The design of the readout chain and the status of the R&D of the components will be presented.

  4. Deep sub electron noise readout in CCD systems using digital filtering techniques

    CERN Document Server

    Cancelo, Gustavo; Moroni, Guillermo Fernandez; Treptow, Ken; Zmuda, Ted; Diehl, Tom

    2011-01-01

    Scientific CCDs designed in thick high resistivity silicon (Si) are excellent detectors for astronomy, high energy and nuclear physics, and instrumentation. Many applications can benefit from CCDs ultra low noise readout systems. The present work shows how sub electron noise CCD images can be achieved using digital signal processing techniques. These techniques allow readout bandwidths of up to 10 K pixels per second and keep the full CCD spatial resolution and signal dynamic range.

  5. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  6. Circuit techniques for cognitive radio receiver front-ends

    Science.gov (United States)

    Sadhu, Bodhisatwa

    This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit implementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks. A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor-capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, measurements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range. In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Transform): an RF front-end channelizer for software defined

  7. Study of the violation of the T and CP symmetries in the reactions {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0} + a vector meson. Validation of the Front-end electronics for the PreShower detector of the LHCb experiment; Recherche de la violation des symetries CP et T dans les reactions {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0} + un meson vecteur. Validation de l'architecture de lecteur des canaux du detecteur de pied de gerbe de l'experience LHCb

    Energy Technology Data Exchange (ETDEWEB)

    Conte, E

    2007-11-15

    This thesis probes the beauty baryon physics in the framework of the LHCb experiment. The present study deals with the {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}V decays where V is a vector meson such as J/{psi}({mu}{sup +}{mu}{sup -}), {phi}(K{sup +}K{sup -}), {omega}({pi}{sup +}{pi}{sup -}{pi}0) or the {rho}{sup 0} - {omega}{sup 0}({pi}{sup +}{pi}{sup -}) mixing. These processes allow to test independently the CP symmetry, which violation has not been observed yet in the baryonic sector, and the T symmetry, which experimental proofs are limited. Among the possible perspectives, a precise measurement of the {lambda}{sub b}{sup 0} lifetime could contribute to the resolution of the raising theoretical-experimental puzzle. A phenomenological model of the {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}V decays has been performed, from which branching ratios and angular distributions have been estimated. An advanced study of the reconstruction and the selection of these reactions by the LHCb apparatus shows that the channel {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}J/{psi} is the dominant channel on both statistics and purity aspects. The {lambda}{sub b}{sup 0} lifetime measure is the most imminent result; the constrains on asymmetries due to CP and T violation require several data taking years. Besides, an instrumental work has been achieved on the read-out electronics, called Front-End, of the experiment pre-shower. This contribution takes into account the validation of the prototype boards and the development of tools required by the qualification of the 100 production boards. (author)

  8. Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications.

    Science.gov (United States)

    Chi, Baoyong; Yao, Jinke; Han, Shuguang; Xie, Xiang; Li, Guolin; Wang, Zhihua

    2007-07-01

    State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.

  9. Numerical study of a magnetically insulated front-end channel for a neutrino factory

    Directory of Open Access Journals (Sweden)

    Diktys Stratakis

    2011-01-01

    Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

  10. Instrumentation of a Track Trigger with Double Buffer Front-End Architecture

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The planned high luminosity upgrade for the LHC (SLHC), will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. We describe a possible design which splits the level-1 trigger into a two-level system, where the first level, using only calorimetry and muon chambers, defines regions of interest in the tracker from which to extract information for a second, refined trigger. The use of a two-buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency will be s...

  11. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  12. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bourrion, O; Grignon, C; Guillaudin, O; Mayet, F; Santos, D

    2009-01-01

    A front end ASIC (BiCMOS-SiGe 0.35 um) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (keV) tracks with a gazeous uTPC. The development of this front end ASIC is a key point in this project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronic. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips are monitored.

  13. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    Energy Technology Data Exchange (ETDEWEB)

    Richer, J.P.; Bosson, G. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Bourrion, O., E-mail: olivier.bourrion@lpsc.in2p3.f [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Grignon, C.; Guillaudin, O.; Mayet, F.; Santos, D. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France)

    2010-08-21

    A front end ASIC (BiCMOS-SiGe 0.35{mu}m) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous {mu}TPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips of pixels are monitored.

  14. Towards a smart Holter system with high performance analogue front-end and enhanced digital processing.

    Science.gov (United States)

    Du, Leilei; Yan, Yan; Wu, Wenxian; Mei, Qiujun; Luo, Yu; Li, Yang; Wang, Lei

    2013-01-01

    Multiple-lead dynamic ECG recorders (Holter) play an important role in the earlier detection of various cardiovascular diseases. In this paper, we present the first several steps towards a 12-lead Holter system with high-performance AFE (Analogue Front-End) and enhanced digital processing. The system incorporates an analogue front-end chip (ADS1298 from TI), which has not yet been widely used in most commercial Holter products. A highly-efficient data management module was designated to handle the data exchange between the ADS1298 and the microprocessor (STM32L151 from ST electronics). Furthermore, the system employs a Field Programmable Gate Array (Spartan-3E from Xilinx) module, on which a dedicated real-time 227-step FIR filter was executed to improve the overall filtering performance, since the ADS1298 has no high-pass filtering capability and only allows limited low-pass filtering. The Spartan-3E FPGA is also capable of offering further on-board computational ability for a smarter Holter. The results indicate that all functional blocks work as intended. In the future, we will conduct clinical trials and compare our system with other state-of-the-arts.

  15. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  16. BORA a front end board, with local intelligence, for the RICH detector of the Compass collaboration

    CERN Document Server

    Baum, G; Bradamante, Franco; Bressan, A; Colavita, A A; Crespo, M; Costa, S; Dalla Torre, S; Fauland, P; Finger, M H; Fratnik, Fabio; Giorgi, M A; Gobbo, B; Grasso, A; Lamanna, M; Martin, A; Menon, G I; Panzieri, D; Schiavon, R P; Tessarotto, F; Zanetti, A M

    1999-01-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as to be part of a computer network that connects several similar boards of the detector with a PC...

  17. Upgrade of the D0 luminosity monitor readout system

    Energy Technology Data Exchange (ETDEWEB)

    Anderson, John; Bridges, Lloyd; Casey, Brendan; Enari, Yuji; Green, Johnny; Johnson, Marvin; Kwarciany, Rick; Miao, Chyi-Chiang; Partridge, Richard; Yoo, Hwi Dong; Wang,; /Brown U. /Fermilab

    2006-12-01

    We describe upgrades to the readout system for the D0 Luminosity Monitor. The D0 Luminosity Monitor consists of plastic scintillation detectors with fine-mesh photomultiplier readout that cover the pseudorapidity range 2.7 < |{eta}| < 4.4. The detector is designed to provide a precise measurement of the rate for non-diffractive inelastic collisions that is used to calculate the TeVatron luminosity at D0. The new readout system is based on custom VME electronics that make precise time-of-flight and charge measurements for each luminosity counter. These measurements are used to identify beam crossings with non-diffractive interactions by requiring in-time hits in both the forward and backward luminosity counters. We have also significantly increased signal/noise for the photomultiplier signals by developing a new front-end preamplifier and improving the grounding scheme.

  18. Highly scalable digital front end architectures for digital printing

    Science.gov (United States)

    Staas, David

    2011-01-01

    HP's digital printing presses consume a tremendous amount of data. The architectures of the Digital Front Ends (DFEs) that feed these large, very fast presses have evolved from basic, single-RIP (Raster Image Processor) systems to multirack, distributed systems that can take a PDF file and deliver data in excess of 3 Gigapixels per second to keep the presses printing at 2000+ pages per minute. This paper highlights some of the more interesting parallelism features of our DFE architectures. The high-performance architecture developed over the last 5+ years can scale up to HP's largest digital press, out to multiple mid-range presses, and down into a very low-cost single box deployment for low-end devices as appropriate. Principles of parallelism pervade every aspect of the architecture, from the lowest-level elements of jobs to parallel imaging pipelines that feed multiple presses. From cores to threads to arrays to network teams to distributed machines, we use a systematic approach to move bottlenecks. The ultimate goals of these efforts are: to take the best advantage of the prevailing hardware options at our disposal; to reduce power consumption and cooling requirements; and to ultimately reduce the cost of the solution to our customers.

  19. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  20. Digital Front End for Wide-Band VLBI Science Receiver

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Navarro, Robert; Goodhart, Charles; Rogstad, Steve; Chandra, Kumar; Finley, Sue; Trinh, Joseph; Soriano, Melissa; White, Les; hide

    2006-01-01

    An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

  1. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  2. DESIGN & IMPLEMENTATION OF RECONFIGURABLE FRONT END FOR MIMO-OFDM

    Directory of Open Access Journals (Sweden)

    VEENA M.B.

    2011-02-01

    Full Text Available This paper focuses on design, implement and optimization of digital front end module of Multiple Input Multiple Output (MIMO-Orthogonal Frequency Division Multiplexing (OFDM system on FPGA employing Alamouti Technique (Space Time Block coding. MIMO-OFDM can very effectively be used to achieve higher data rate’s and higher reliability and this is going to be the Key for 4G Technology. MIMO -OFDM designed in this work consists of Input/Output Memory, 16 QAM Modulator, MIMO Encoder (Space Time Encoder, Wireless Channel Model, MIMO Decoder Space Time Decoder and 16 QAM Demodulator. This paper has resulted in the development of a hardware prototype of a MIMO Transmitter, Receiver and channel, which is implemented on a Spartan-3 FPGA board. As the number format adopted is floating point,there was a need to develop a separate function which will show the equivalent real numbers for the corresponding floating point number. This made the task of debugging a lot easier. Test benches for individual model were developed and tested it for its correct functionality. The functional simulation was carried out for the entire design. The entire design was mapped on to FPGA. The results were compared with the MATLAB results and were found to be the same.

  3. Test of high time resolution MRPC with different readout modes for the BESIII upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Yang, S. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Sun, Y.J., E-mail: sunday@ustc.edu.cn [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Li, C., E-mail: licheng@ustc.edu.cn [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Heng, Y.K.; Qian, S. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Chen, H.F.; Chen, T.X. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Dai, H.L. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Fan, H.H.; Liu, S.B. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Liu, S.D.; Jiang, X.S. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Shao, M.; Tang, Z.B.; Zhang, H.; Zhao, Z.G. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China)

    2014-11-01

    In order to further enhance the particle identification capability of the Beijing Spectrometer (BESIII), it is proposed to upgrade the current end-cap time-of-flight (eTOF) detector with multi-gap resistive plate chamber (MRPC). The prototypes, together with the front end electronics (FEE) and time digitizer (TDIG) module have been tested at the E3 line of Beijing Electron Positron Collider (BEPCII) to study the difference between the single and double-end readout MRPC designs. The time resolutions (sigma) of the single-end readout MRPC are 47/53 ps obtained by 600 MeV/c proton/pion beam, while that of the double-end readout MRPC is 40 ps (proton beam). The efficiencies of three MRPC modules tested by both proton and pion beam are better than 98%. For the double-end readout MRPC, no incident position dependence is observed.

  4. Channel control ASIC for the CMS hadron calorimeter front end readout module

    Energy Technology Data Exchange (ETDEWEB)

    Ray Yarema et al.

    2002-09-26

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link.

  5. Performance of the Electronic Readout of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Abreu, H; Aleksa, M; Aperio Bella, L; Archambault, JP; Arfaoui, S; Arnaez, O; Auge, E; Aurousseau, M; Bahinipati, S; Ban, J; Banfi, D; Barajas, A; Barillari, T; Bazan, A; Bellachia, F; Beloborodova, O; Benchekroun, D; Benslama, K; Berger, N; Berghaus, F; Bernat, P; Bernier, R; Besson, N; Binet, S; Blanchard, JB; Blondel, A; Bobrovnikov, V; Bohner, O; Boonekamp, M; Bordoni, S; Bouchel, M; Bourdarios, C; Bozzone, A; Braun, HM; Breton, D; Brettel, H; Brooijmans, G; Caputo, R; Carli, T; Carminati, L; Caughron, S; Cavalleri, P; Cavalli, D; Chareyre, E; Chase, RL; Chekulaev, SV; Chen, H; Cheplakov, A; Chiche, R; Citterio, M; Cojocaru, C; Colas, J; Collard, C; Collot, J; Consonni, M; Cooke, M; Copic, K; Costa, GC; Courneyea, L; Cuisy, D; Cwienk, WD; Damazio, D; Dannheim, D; De Cecco, S; De La Broise, X; De La Taille, C; de Vivie, JB; Debennerot, B; Delagnes, E; Delmastro, M; Derue, F; Dhaliwal, S; Di Ciaccio, L; Doan, O; Dudziak, F; Duflot, L; Dumont-Dayot, N; Dzahini, D; Elles, S; Ertel, E; Escalier, M; Etienvre, AI; Falleau, I; Fanti, M; Farooque, T; Favre, P; Fayard, Louis; Fent, J; Ferencei, J; Fischer, A; Fournier, D; Fournier, L; Fras, M; Froeschl, R; Gadfort, T; Gallin-Martel, ML; Gibson, A; Gillberg, D; Gingrich, DM; Göpfert, T; Goodson, J; Gouighri, M; Goy, C; Grassi, V; Gray, J; Guillemin, T; Guo, B; Habring, J; Handel, C; Heelan, L; Heintz, H; Helary, L; Henrot-Versille, S; Hervas, L; Hobbs, J; Hoffman, J; Hostachy, JY; Hoummada, A; Hrivnac, J; Hrynova, T; Hubaut, F; Huber, J; Iconomidou-Fayard, L; Iengo, P; Imbert, P; Ishmukhametov, R; Jantsch, A; Javadov, N; Jezequel, S; Jimenez Belenguer, M; Ju, XY; Kado, M; Kalinowski, A; Kar, D; Karev, A; Katsanos, I; Kazarinov, M; Kerschen, N; Kierstead, J; Kim, MS; Kiryunin, A; Kladiva, E; Knecht, N; Kobel, M; Koletsou, I; König, S; Krieger, P; Kukhtin, V; Kuna, M; Kurchaninov, L; Labbe, J; Lacour, D; Ladygin, E; Lafaye, R; Laforge, B; Lamarra, D; Lampl, W; Lanni, F; Laplace, S; Laskus, H; Le Coguie, A; Le Dortz, O; Le Maner, C; Lechowski, M; Lee, SC; Lefebvre, M; Leonhardt, K; Lethiec, L; Leveque, J; Liang, Z; Liu, C; Liu, T; Liu, Y; Loch, P; Lu, J; Ma, H; Mader, W; Majewski, S; Makovec, N; Makowiecki, D; Mandelli, L; Mangeard, PS; Mansoulie, B; Marchand, JF; Marchiori, G; Martin, D; Martin-Chassard, G; Martin dit Latour, B; Marzin, A; Maslennikov, A; Massol, N; Matricon, P; Maximov, D; Mazzanti, M; McCarthy, T; McPherson, R; Menke, S; Meyer, JP; Ming, Y; Monnier, E; Mooshofer, P; Neganov, A; Niedercorn, F; Nikolic-Audit, I; Nugent, IM; Oakham, G; Oberlack, H; Ocariz, J; Odier, J; Oram, CJ; Orlov, I; Orr, R; Parsons, JA; Peleganchuk, S; Penson, A; Perini, L; Perrodo, P; Perrot, G; Perus, A; Petit, E; Pisarev, I; Plamondon, M; Poffenberger, P; Poggioli, L; Pospelov, G; Pralavorio, P; Prast, J; Prudent, X; Przysiezniak, H; Puzo, P; Quentin, M; Radeka, V; Rajagopalan, S; Rauter, E; Reimann, O; Rescia, S; Resende, B; Richer, JP; Ridel, M; Rios, R; Roos, L; Rosenbaum, G; Rosenzweig, H; Rossetto, O; Roudil, W; Rousseau, D; Ruan, X; Rudert, A; Rusakovich, N; Rusquart, P; Rutherfoord, J; Sauvage, G; Savine, A; Schaarschmidt, J; Schacht, P; Schaffer, A; Schram, M; Schwemling, P; Seguin Moreau, N; Seifert, F; Serin, L; Seuster, R; Shalyugin, A; Shupe, M; Simion, S; Sinervo, P; Sippach, W; Skovpen, K; Sliwa, R; Soukharev, A; Spano, F; Stavina, P; Straessner, A; Strizenec, P; Stroynowski, R; Talyshev, A; Tapprogge, S; Tarrade, F; Tartarelli, GF; Teuscher, R; Tikhonov, Yu; Tocut, V; Tompkins, D; Thompson, P; Tisserant, S; Todorov, T; Tomasz, F; Trincaz-Duvoid, S; Trinh, Thi N; Trochet, S; Trocme, B; Tschann-Grimm, K; Tsionou, D; Ueno, R; Unal, G; Urbaniec, D; Usov, Y; Voss, K; Veillet, JJ; Vincter, M; Vogt, S; Weng, Z; Whalen, K; Wicek, F; Wilkens, H; Wingerter-Seez, I; Wulf, E; Yang, Z; Ye, J; Yuan, L; Yurkewicz, A; Zarzhitsky, P; Zerwas, D; Zhang, H; Zhang, L; Zhou, N; Zimmer, J; Zitoun, R; Zivkovic, L

    2010-01-01

    The ATLAS detector has been designed for operation at the Large Hadron Collider at CERN. ATLAS includes electromagnetic and hadronic liquid argon calorimeters, with almost 200,000 channels of data that must be sampled at the LHC bunch crossing frequency of 40 MHz. The calorimeter electronics calibration and readout are performed by custom electronics developed specifically for these purposes. This paper describes the system performance of the ATLAS liquid argon calibration and readout electronics, including noise, energy and time resolution, and long term stability, with data taken mainly from full-system calibration runs performed after installation of the system in the ATLAS detector hall at CERN.

  6. The Drift Chamber Electronics and Readout for the NA48 Experiment

    CERN Document Server

    Augustin, I; Holder, M; Kreutz, A; Otto, W; Roschangar, M; Schöfer, B; Schwarze, I; Ziolkowski, M

    1998-01-01

    A drift chamber readout system for about 8000 channels with continuous sensitivity, i.e. concurrent data recording and readout, is described. Drift times are measured in bins of 1.56 ns with respect to a continuously running 40 MHz clock. The clock interval of 25 ns is divided into 16 bins by means of a 16 element delay chain. The length of this chain is linked to the clock interval by a phase locked loop. An ASIC chip was developed to perform time measurements and data storage for 16 channels. In an asynchronous readout of this chip, data are tranferred to intermediate buffers, for use in a first level trigger and eventual final readout. The design of the electronics is described and results from data taking runs are presented.

  7. Architectural modeling of pixel readout chips Velopix and Timepix3

    NARCIS (Netherlands)

    Poikela, T.; Plosila, J.; Westerlund, T.; Buytaert, J.; Campbell, M.; Llopart, X.; Plackett, R.; Wyllie, K.; van Beuzekom, M.; Gromov, V.; Kluit, R.; Zappon, F.; Zivkovic, V.; Brezina, C.; Desch, K.; Fang, X.; Kruth, A.

    2012-01-01

    We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout.

  8. An Enhanced Front-End Algorithm for Reducing Channel Change Time in DVB-T System

    Science.gov (United States)

    Joe, Inwhee; Choi, Jongsung

    To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

  9. Superconducting hot-electron nanobolometer with microwave bias and readout

    CERN Document Server

    Kuzmin, A A; Shitov, S V; Abramov, N N; Ermakov, A B; Arndt, M; Wuensch, S H; Ilin, K S; Ustinov, A V; Siegel, M

    2014-01-01

    We propose a new detection technique based on radio-frequency (RF) bias and readout of an antenna-coupled superconducting nanobolometer. This approach is suitable for Frequency-Division-Multiplexing (FDM) readout of large arrays using broadband low-noise RF amplifier. We call this new detector RFTES. This feasibility study was made on demonstrator devices which are made in all-Nb technology and operate at 4.2 K. The studied RFTES devices consist of an antenna-coupled superconducting nanobolometer made of ultrathin niobium films with transition temperature Tc = 5.2 K. The 0.65-THz antenna and nanobolometer are embedded as a load into a GHz-range coplanar niobium resonator (Tc = 8.9 K, Q = 4000). To heat the superconducting Nb nanobolometer close to the Tc, the RF power at resonator frequency f = 5.8 GHz is applied via a transmission line which is weakly coupled (-11 dB) to the loaded resonator. The THz-antenna of RFTES was placed in the focus of a sapphire immersion lens inside a He4-cryostat equipped with an ...

  10. Development of radiation hard readout electronics for LHCb

    CERN Document Server

    Sexauer, Edgar; Lindenstruth, Volker

    2001-01-01

    The experiment LHCb is under development at CERN and aims to measure CP-violation in the B-Meson system at very high precision. The experiment makes use of a vertex detector that is equipped with silicon microstrip detectors. A chip suitable for the readout of this detector has been developed in a working group at the ASIC-laboratory Heidelberg. This readout chip 'Beetle-1.0' contains 128 analog input stages of a charge sensitive preamplifier, a pulse shaper and a buffer. The analog signal is fed into a comparator, from which a fast trigger signal can be derived. The following pipeline, realized as an array of gate capacitances, can be used to either store the analog output of the input amplifiers or to store the digital comparator output. External trigger signals mark events that have to be read out and the according pipeline location is stored in a derandomizing buffer. Pending events are read out from the pipeline via a charge-sensitive, resetable amplifier and an analog multiplexer, which serializes the s...

  11. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  12. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  13. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  14. A prototype for the upgraded readout electronics for TileCal

    CERN Document Server

    Eriksson, D; The ATLAS collaboration; Bohm, C; Kavianipour, H; Muschter, S; Oreglia, M; Tang, F

    2011-01-01

    Upgrade plans for ATLAS hadronic calorimeter (TileCal) include full readout of all data to the counting room. We are developing a possible implementation of the future readout and trigger electronics aiming at a full functional demonstrator during Phase 0, starting from an existing functional test slice assembled using a combination of prototypes and emulators. Presently the first version of two PCBs in charge of digitization, control and communication are being developed. The design is highly redundant, using FPGAs with fault tolerant firmware for control and protocol conversion. Communication between on and off detector electronics is implemented via high speed optical links.

  15. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  16. Development of ATLAS Liquid Argon Calorimeters Readout Electronics for HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00388354; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon Calorimeters and their readout system. An improved trigger system with a higher acceptance rate of 1 MHz and a longer latency of up to 60 micro-seconds together with a better radiation tolerance require an upgrade of the readout electronics. Concepts for the future readout of the 182,500 calorimeter channels at 40/80 MHz and 16 bit dynamic range, and the development of low-noise, low-power and high-bandwidth electronic components will be presented. These include ASIC developments towards radiation-tolerant low-noise pre-amplifiers, analog-to-digital converters up to 14 bits and low-power optical links providing transfer rates of at least 10 Gb/s per fiber.

  17. Development of ATLAS Liquid Argon Calorimeters Readout Electronics for HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00388354; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider (LHC) will provide 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters and their readout system. The improved trigger system has a higher acceptance rate of 1 MHz and a longer latency of up to 60 micro-seconds. This requires an upgrade of the readout electronics, a better radiation tolerance is also required. This paper will present concepts for the future readout of the 182,468 calorimeter channels at 40 or 80 MHz with a 16 bit dynamic range. Progress of the development of low-noise, low-power and high-bandwidth electronic components will be presented. These include radiation-tolerant preamplifiers, analog-to-digital converters (ADC) up to 14 bits and low-power optical links providing transfer rates of at least 10 Gbps per fiber.

  18. Readout scheme of the upgraded ALICE TPC

    CERN Document Server

    Appelshaeuser, Harald; Ivanov, Marian; Lippmann, Christian; Wiechula, Jens

    2016-01-01

    In this document, we present the updated readout scheme for the ALICE TPC Upgrade. Two major design changes are implemented with respect to the concept that was presented in the TPC Upgrade Technical Design Report: – The SAMPA front-end ASIC will be used in direct readout mode. – The ADC sampling frequency will be reduced from 10 to 5 MHz. The main results from simulations and a description of the new readout scheme is outlined.

  19. Conductive Cooling of SDD and SSD Front-End Chips for ALICE

    CERN Document Server

    Van den Brink, A; Daudo, F; Feofilov, G A; Godisov, O N; Giraudo, G; Igolkin, S N; Kuijer, P; Nooren, G J L; Swichev, A; Tosello, F

    2001-01-01

    We present analysis, technology developments and test results of the heat drain system of the SDD and SSD front-end electronics for the ALICE Inner Tracker System (ITS). Application of super thermoconductive carbon fibre thin plates provides a practical solution for the development of miniature motherboards for the FEE chips situated inside the sensitive ITS volume. Unidirectional carbon fibre motherboards of 160 -300 micron thickness ensure the mounting of the FEE chips and an efficient heat sink to the cooling arteries. Thermal conductivity up to 1.3 times better than copper is achieved while preserving a negligible multiple scattering contribution by the material (less than 0.15 percent of X/Xo).

  20. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  1. Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

    CERN Document Server

    Caratelli, Alessandro; Jan Kaplon; Kloukinas, Konstantinos; Simone Scarfi

    2016-01-01

    The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\\sim$100\\,Gbps and reduces the output data flow from 1.3\\,Tbps to 30\\,Gbps per module while limiting the total power density to below 100\\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing mult...

  2. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of Innov

  3. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  4. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  5. Performance of multi-step avalanche chambers equipped with two-dimensional electronic readout

    NARCIS (Netherlands)

    Carlén, L.; El Chenawi, K.; Enosawa, K; Garpman, S; Gustafsson, H.A.; Kurata, M; Löhner, H.; Martin, M; Miake, Y; Miyamoto, Y; Naef, H; Nilsson, P; Nishimura, S; Nystrand, J; Oskarsson, A; Osterman, L; Otterlund, I.; Perrin, E; Rosselet, L; Rubio, JM; Sato, S; Soderstrom, K; Solomey, N; Stenlund, E; Svensson, T; Voros, S; Yagi, K; Yokota, Y

    1998-01-01

    We have developed large area multi-step avalanche chambers with electronic readout for tracking in a very high multiplicity environment in the WA98 experiment at the CERN SPS. The operational characteristics of the detection system is reported. The reconstruction efficiency of the chambers varies wi

  6. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    OpenAIRE

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to dig...

  7. Orthogonal sequencing multiplexer for superconducting nanowire single-photon detectors with RSFQ electronics readout circuit.

    Science.gov (United States)

    Hofherr, Matthias; Wetzstein, Olaf; Engert, Sonja; Ortlepp, Thomas; Berg, Benjamin; Ilin, Konstantin; Henrich, Dagmar; Stolz, Ronny; Toepfer, Hannes; Meyer, Hans-Georg; Siegel, Michael

    2012-12-17

    We propose an efficient multiplexing technique for superconducting nanowire single-photon detectors based on an orthogonal detector bias switching method enabling the extraction of the average count rate of a set of detectors by one readout line. We implemented a system prototype where the SNSPDs are connected to an integrated cryogenic readout and a pulse merger system based on rapid single flux quantum (RSFQ) electronics. We discuss the general scalability of this concept, analyze the environmental requirements which define the resolvability and the accuracy and demonstrate the feasibility of this approach with experimental results for a SNSPD array with four pixels.

  8. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  9. Implementation of the Timepix ASIC in the Scalable Readout System

    Science.gov (United States)

    Lupberger, M.; Desch, K.; Kaminski, J.

    2016-09-01

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  10. Readout electronics and test bench for the CMS Phase I pixel detector

    CERN Document Server

    Del Burgo, Riccardo

    2016-01-01

    The present CMS pixel detector will be replaced with an upgraded pixel system during the LHC extended technical stop in winter 2016/2017. The CMS Phase 1 pixel upgrade combines a new pixel readout chip, which minimizes detection inefficiencies, with several other design improvements to maintain the excellent tracking performance of CMS at the higher luminosity conditions foreseen for the coming years. The upgraded detector features new readout electronics which require detailed evaluation. For this purpose a test stand has been setup, including a slice of the CMS pixel DAQ system, all components of the upgraded readout chain together with a number of detector modules. The test stand allows for detailed evaluation and verification of all detector components, and is also crucial to develop tests and procedures to be used during the detector assembly and the commissioning and calibration of the detector. In this talk the system test and its functionalities will be described with a focus on the tests performed fo...

  11. IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

    Science.gov (United States)

    Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

    2011-04-01

    This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

  12. Alibava : A portable readout system for silicon microstrip sensors

    CERN Document Server

    Marco-Hernández, Ricardo; Casse, G; García, C; Greenall, A; Lacasta, C; Lozano, M; Martí i García, S; Martínez, R; Miñano, M; Pellegrini, G; Smith, N A; Ullán, M

    2007-01-01

    A portable readout system for silicon microstrip sensors is currently being developed. This system uses a front-end readout chip, which was developed for the LHC experiments. The system will be used to investigate the main properties of this type of sensors and their future applications. The system is divided in two parts: a daughter board and a mother board. The first one is a small board which contains two readout chips and has fan-ins and sensor support to interface the sensors. The last one is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. The core of this board is a FPGA that controls the readout chips, a 10 bit ADC, an integrated TDC and an USB controller. This board also contains the analogue electronics to process the data that comes from the readout chips. There is also provision for an external trigger input (e.g. scintillator trigger) and a 'synchronised' trigger output for ...

  13. Electron energy loss spectroscopy with parallel readout of energy and momentum

    CERN Document Server

    Ibach, Harald; Sforzini, Jessica; Soubatch, Serguei; Tautz, F Stefan

    2016-01-01

    We introduce a high energy resolution electron source that matches the requirements for parallel readout of energy and momentum of modern hemispherical electron energy analyzers. The system is designed as an add-on device to typical photoemission chambers. Due to the multiplex gain, a complete phonon dispersion of a Cu(111) surface was measured in seven minutes with 4 meV energy resolution.

  14. Development of hybrid photon detectors with integrated silicon pixel readout for the RICH counters of LHCb

    CERN Document Server

    Alemi, M; Formenti, F; Gys, Thierry; Piedigrossi, D; Puertolas, D; Rosso, E; Snoeys, W; Wyllie, Ken H

    1999-01-01

    We report on the ongoing work towards a hybrid photon detector with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment at the Large Hadron Collider at CERN. The photon detector is based $9 on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a fast, binary readout chip with matching pixel electronics. The $9 performance of a half-scale prototype is presented, together with the developments and tests of a full-scale tube with large active area. Specific requirements for pixel front-end and readout electronics in LHCb are outlined, and $9 recent results obtained from pixel chips applicable to hybrid photon detector design are summarized.

  15. Readout Electronics of the ATLAS Muon Cathode Strip Chambers

    CERN Document Server

    Gough Eschrich, I

    2008-01-01

    The ATLAS muon spectrometer employs cathode strip chambers (CSC) to measure high momentum muons in the forward regions (2.0 < | | < 2.7). Due to the severe radiation levels expected in this environment, the on-detector electronics are limited to amplifying and digitizing the signal while sparsification, event building and other tasks are performed off-detector.

  16. Readout Electronics of the ATLAS Muon Cathode Strip Chambers

    CERN Document Server

    Gough Eschrich, I

    2008-01-01

    The ATLAS muon spectrometer employs cathode strip chambers (CSC) to measure high momentum muons in the forward regions $(2.0 < |eta| < 2.7)$. Due to the severe radiation levels expected in this environment, the on-detector electronics are limited to amplifying and digitizing the signal while sparsification, event building and other tasks are performed off-detector.

  17. Electronics for the CMS muon drift tube chambers the read-out minicrate

    CERN Document Server

    Fernandez Bedoya, Cristina; Oller, Juan Carlos; Willmott, Carlos

    2005-01-01

    On the Compact Muon Solenoid (CMS) experimentat the Large Hadron Collider (LHC) at the CERN laboratory, the drift tube chambers are responsible for muon detection and precise momentum measurement. In this paper the first level of the read out electronics for these drift tube chambers is described. These drift tube chambers will be located inside the muon barrel detector in the so-called minicrates (MCs), attached to the chambers. The read out boards (ROBs) are the main component of this first level data acquisition system, and they are responsible for the time digitalization related to Level 1 Accept (L1A) trigger of the incoming signals from the front-end electronics, followed by a consequent data merging to the next stages of the data acquisition system. ROBs' architecture and functionality have been exhaustively tested, as well as their capability of operation beyond the expected environmental conditions inside the CMS detector. Due to the satisfactory results obtained, final production of ROBs and their a...

  18. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  19. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  20. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  1. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    Abstract: Most industries face continuing pressures from rising R&D costs, shortening product lifecycles and global competition. These challenges have increased the focus on shortening development times, which again puts pressure on the efficiency of front end innovation (FEI). In the attempt...... to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...

  2. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger. The ATLAS Tile Calorimeter on-detector electronics is housed in the drawers at the back of each of the 256 detector wedges. Each drawer services up to 48 photomultiplier tubes. The new readout system is designed to replace the present system as it will reach component lifetime and radiation tolerance limits making it incompatible with continued use into the HL-LHC era. Wi...

  3. Readout Driver Firmware Development for the ATLAS Insertable B-Layer

    CERN Document Server

    Chen, Shaw-Pin; Hsu, Shih-Chieh

    During the Large Hadron Collider shutdown from 2013 to 2014 a fourth silicon layer, called the Insertable-B Layer (IBL), was inserted inside the existing ATLAS Pixel Detector. The IBL uses the state-of-the-art FE-I4 front-end readout ASICs for enhanced detector readout efficiency during upcoming LHC runs at higher energy and luminosity. The control and data acquisition (DAQ) of the IBL requires the commissioning of new off-detector readout electronics, mainly consisting of Field-Programmable Gate Array (FPGA)-based Readout Driver (ROD) and Back-of-Crate (BOC) Cards. This thesis focuses on the architecture, implementation, simulation, and hardware test results of the new IBL ROD datapath firmware. Characterization of the IBL detector front-end and an overview of ATLAS Trigger DAQ (TDAQ) system are provided in the first chapters of the thesis. IBL ROD datapath firmware was designed and simulated in a ModelSim testbench with a realistic HDL FE-I4 model as source of data. The hardware tests using both real and em...

  4. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  5. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken into acco...... into account. The accuracy of the expressions has been verified by using Touchstone simulator. The agreement between the calculated and simulated front end performances is very good....

  6. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  7. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    OpenAIRE

    Bin You; Bo Yang; Xuan Wen; Liangyu Qu

    2013-01-01

    A new ultrahigh frequency radio frequency identification (UHF RFID) reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS) circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both th...

  8. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N...... in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates....

  9. Beam test results for the upgraded LHCb RICH opto-electronic readout system

    CERN Multimedia

    Carniti, Paolo

    2016-01-01

    The LHCb experiment is devoted to high-precision measurements of CP violation and search for New Physics by studying the decays of beauty and charmed hadrons produced at the Large Hadron Collider (LHC). Two RICH detectors are currently installed and operating successfully, providing a crucial role in the particle identification system of the LHCb experiment. Starting from 2019, the LHCb experiment will be upgraded to operate at higher luminosity, extending its potential for discovery and study of new phenomena. Both the RICH detectors will be upgraded and the entire opto-electronic system has been redesigned in order to cope with the new specifications, namely higher readout rates, and increased occupancies. The new photodetectors, readout electronics, mechanical assembly and cooling system have reached the final phase of development and their performance was thoroughly and successfully validated during several beam test sessions in 2014 and 2015 at the SPS facility at CERN. Details of the test setup and perf...

  10. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  11. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  12. Low Background Signal Readout Electronics for the MAJORANA DEMONSTRATOR

    Energy Technology Data Exchange (ETDEWEB)

    Guinn, I. [University of Washington, Seattle; Abgrall, N. [Lawrence Berkeley National Laboratory (LBNL); Avignone, III, F. T. [University of South Carolina/Oak Ridge National Laboratory (ORNL); Bertrand, F. E. [Oak Ridge National Laboratory (ORNL); Efremenko, Yuri [University of Tennessee (UTK) and Oak Ridge National Laboratory (ORNL); Galindo-Uribarri, A [Oak Ridge National Laboratory (ORNL); Green, M. P. [Oak Ridge National Laboratory (ORNL); Radford, D. C. [Oak Ridge National Laboratory (ORNL); Romero-Romero, E. [UTK/ORNL; Varner, R. L. [Oak Ridge National Laboratory (ORNL); White, B. R. [Oak Ridge National Laboratory (ORNL); Wilkerson, J. F. [UNC/Triangle Univ. Nucl. Lab, Durham, NC/ORNL; Yu, C.-H. [Oak Ridge National Laboratory (ORNL); Majorana, [MAJORANA Collaboration

    2015-01-01

    The MAJORANA DEMONSTRATOR is a planned 40 kg array of Germanium detectors intended to demonstrate the feasibility of constructing a tonne-scale experiment that will seek neutrinoless double beta decay (0 nu beta beta) in Ge-76. Such an experiment would require backgrounds of less than 1 count/tonne-year in the 4 keV region of interest around the 2039 keV Q-value of the beta beta decay. Designing low-noise electronics, which must be placed in close proximity to the detectors, presents a challenge to reaching this background target. This paper will discuss the MAJORANA collaboration's solutions to some of these challenges.

  13. Integration of a High Sensitivity MEMS Directional Sound Sensor With Readout Electronics

    Science.gov (United States)

    2012-12-01

    ERİŞMİŞ, “ MEMS accelerometers and gyroscopes for inertial measurement units,” M.S. thesis, Middle East Technical University, Cankaya, Ankara, Turkey...HIGH SENSITIVITY MEMS DIRECTIONAL SOUND SENSOR WITH READOUT ELECTRONICS by John D. Roth December 2012 Thesis Advisor: Gamani Karunasiri...3. REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Integration of a High Sensitivity MEMS Directional Sound Sensor with

  14. Upgraded Readout and Trigger Electronics for the ATLAS Liquid Argon Calorimeter at the LHC at the Horizons 2018-2022

    CERN Document Server

    Oliveira Damazio, Denis; The ATLAS collaboration

    2013-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

  15. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  16. Low noise 4-channel front end ASIC with on-chip DLL for the upgrade of the LHCb Calorimeter

    Science.gov (United States)

    Picatoste, E.; Bigbeder-Beau, C.; Duarte, O.; Garrido, L.; Gascon, D.; Grauges, E.; Lefrançois, J.; Machefert, F.; Mauricio, J.; Vilasis, X.

    2015-04-01

    An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and it incorporates dedicated solutions to achieve low noise, linearity and spill-over specifications. The included DLL is capable of shifting the phase of the LHC clock (25 ns) in steps of 1 ns. The selected technology is AMS SiGe BiCMOS 0.35 um.

  17. Cryogenic readout techniques for germanium detectors

    Energy Technology Data Exchange (ETDEWEB)

    Benato, G. [University of Zurich, (Switzerland); Cattadori, C. [INFN - Milano Bicocca, (Italy); Di Vacri, A. [INFN LNGS, (Italy); Ferri, E. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy); D' Andrea, V.; Macolino, C. [GSSI/INFN LNGS, (Italy); Riboldi, S. [Universita degli Studi di Milano/INFN Milano, (Italy); Salamida, F. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy)

    2015-07-01

    High Purity Germanium detectors are used in many applications, from nuclear and astro-particle physics, to homeland security or environment protection. Although quite standard configurations are often used, with cryostats, charge sensitive amplifiers and analog or digital acquisition systems all commercially available, it might be the case that a few specific applications, e.g. satellites, portable devices, cryogenic physics experiments, etc. also require the development of a few additional or complementary techniques. An interesting case is for sure GERDA, the Germanium Detector Array experiment, searching for neutrino-less double beta decay of {sup 76}Ge at the Gran Sasso National Laboratory of INFN - Italy. In GERDA the entire detector array, composed of semi-coaxial and BEGe naked crystals, is operated suspended inside a cryostat filled with liquid argon, that acts not only as cooling medium and but also as an active shield, thanks to its scintillation properties. These peculiar circumstances, together with the additional requirement of a very low radioactive background from all the materials adjacent to the detectors, clearly introduce significant constraints on the design of the Ge front-end readout electronics. All the Ge readout solutions developed within the framework of the GERDA collaboration, for both Phase I and Phase II, will be briefly reviewed, with their relative strength and weakness compared together and with respect to ideal Ge readout. Finally, the digital processing techniques developed by the GERDA collaboration for energy estimation of Ge detector signals will be recalled. (authors)

  18. Front-end ASICs for high-energy astrophysics in space

    Science.gov (United States)

    Gevin, O.; Limousin, O.; Meuris, A.

    2016-07-01

    In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a

  19. Electronics Development for the ATLAS Liquid Argon Calorimeter Trigger and Readout for Future LHC Running

    CERN Document Server

    Hopkins, Walter; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide 7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energies of a...

  20. Electronics Development for the ATLAS Liquid Argon Calorimeter Trigger and Readout for Future LHC Running

    CERN Document Server

    Pacheco Rodriguez, Laura; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide up to 7.5 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. The radiation tolerance criteria and the improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger-readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated ...