Front-end electronics for multichannel semiconductor detector systems

CERN Document Server

Grybos, P

2010-01-01

Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

Installation and testing of the 112 boards for the front-end electronics.

CERN Multimedia

2006-01-01

Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

de La Taille, C

2008-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

The Front-End Concentrator card for the RD51 Scalable Readout System

International Nuclear Information System (INIS)

Toledo, J; Esteve, R; Monzó, J M; Tarazona, A; Muller, H; Martoiu, S

2011-01-01

Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U × 220 mm Eurocard combo that fits on a 19'' subchassis. Adapter cards exist already for the first applications and more are in development.

A front-end electronic system for large arrays of bolometers

Science.gov (United States)

Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

2018-02-01

CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

Front-end electronics for accurate energy measurement of double beta decays

International Nuclear Information System (INIS)

Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

2012-01-01

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

2016-07-11

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

International Nuclear Information System (INIS)

Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

2016-01-01

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Hofsajer, I; Govender, M; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is the portable test-bench for the full certification of the front-end electronics of the ATLAS Tile calorimeter designed for the upgrade phase-II. It is a high throughput electronics system designed to simultaneously read-out all the samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read-out and control the front-end boards. The rest of the functionalities of the system are provided by a HV mezzanine board that to turn on the gain of the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog output of the front-end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

Front-end electronics and trigger systems - status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth G; Spieler, Helmuth G

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2009-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2007-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

Dead-time free pixel readout architecture for ATLAS front-end IC

CERN Document Server

Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

1999-01-01

A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

Web-based DAQ systems: connecting the user and electronics front-ends

International Nuclear Information System (INIS)

Lenzi, Thomas

2016-01-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Web-based DAQ systems: connecting the user and electronics front-ends

Science.gov (United States)

Lenzi, Thomas

2016-12-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

2016-01-01

The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

SPD very front end electronics

International Nuclear Information System (INIS)

Luengo, S.; Gascon, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasis, X.

2006-01-01

The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

CERN Document Server

AUTHOR|(CDS)2068589; Rohrich, Dieter

2008-01-01

The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

Front-end electronics and trigger systems-Status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not reduce the power required for the desired noise levels, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems, they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

Electronic front-end for LHCb electromagnetic and hadronic calorimeters

International Nuclear Information System (INIS)

Beigbeder, Ch.

2000-11-01

The electronic front-end of the LHCb electromagnetic and hadronic calorimeters will be described. It consists of a 9U 32 channel board, each channel including shaper-integrator, 12 bit ADC and look-up tables allowing to code the transverse energy information both for readout and for the Level 0 trigger. The readout information is stored in a fixed latency followed by a derandomizer. The trigger information is processed further on the board by FPGA, performing channel addition and comparison to extract the highest transverse energy local cluster for further processing. The system is fully synchronous and allows to extract candidates for calorimetric trigger at every 40 MHz clock cycle. The operation and characteristics (noise, linearity etc.) of a prototype board will be described. (author)

Digital front-end electronics for COMPASS Muon-Wall 1 detector

International Nuclear Information System (INIS)

Alekseev, G.D.; Zhuravlev, N.I.; Maggiora, A.

2005-01-01

The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

Front-end counting mode electronics for CdZnTe sensor readout

CERN Document Server

Moraes, Danielle; Kaplon, Jan

2004-01-01

The development of a front-end circuit optimized for CdZnTe detector readout, implemented in 0.25 mu m CMOS technology, is reported. The ASIC comprises 17 channels of a charge sensitive amplifier with an active feedback, followed by a gain-shaper stage and a discriminator with a 5 bit fine-tune DAC. The signal from the discriminator is sensed by a 25 ns mono-stable circuit and an 18-bit static ripple- counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at a maximum counting rate of 2 million counts/second. The amplifier shows a linear sensitivity of 24 mV/fC with 50 ns peaking time and an equivalent noise charge of about 650 e/sup -/, for a detector capacitance of 10 pF. When connected to a 3*3*7 mm/sup 3/ CdZnTe detector the amplifier gain is about 8 mV/keV with a noise around 3.6 keV.

Front-end readout system for PHENIX RICH

International Nuclear Information System (INIS)

Tanaka, Y.; Hara, H.; Ebisu, K.; Hibino, M.; Kametani, S.; Kikuchi, J.; Wintenberg, A.L.; Walker, J.W.; Franck, S.; Moscone, C.; Jones, J.P.; Young, G.R.; Matsumoto, T.; Sakaguchi, T.; Oyama, K.; Hamagaki, H.

2000-01-01

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2008-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

DEFF Research Database (Denmark)

Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

2012-01-01

This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

Front-end electronics for the CMS preshower detector

CERN Document Server

Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

2002-01-01

The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

Readout Electronics Upgrades of the ATLAS Liquid Argon Calorimeter

CERN Document Server

Anelli, Christopher Ryan; The ATLAS collaboration

2018-01-01

The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. First prototypes of the front-end electronics components show good promise to match the stringent specifications. The off-detector electronics will make use of FPGAs connected through high-speed links to perform energy reconstruction, data reduction and buffering. Results of tests of the first prototypes of front-end components will be presented, along with design studies on the performance of the off-detector readout system.

Development of an external readout electronics for a hybrid photon detector

CERN Document Server

Uyttenhove, Simon; Tichon, Jacques; Garcia, Salvador

The pixel hybrid photon detectors currently installed in the LHCb Cherenkov system encapsulate readout electronics in the vacuum tube envelope. The LHCb upgrade and the new trigger system will require their replacement with new photon detectors. The baseline photon detector candidate is the multi-anode photomultiplier. A hybrid photon detector with external readout electronics has been proposed as a backup option. This master thesis covers a R & D phase to investigate this latter concept. Extensive studies of the initial electronics system underlined the noise contributions from the Beetle chip used as front-end readout ASIC and from the ceramic carrier of the photon detector. New front-end electronic boards have been developed and made fully compatible with the existing LHCb-RICH infrastructure. With this compact readout system, Cherenkov photons have been successfully detected in a real particle beam environment. The proof-of-concept of a hybrid photon detector with external readout electronics was val...

RPC performance vs. front-end electronics

International Nuclear Information System (INIS)

Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

2012-01-01

Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

A multichannel front end ASIC for PMT readout in LHAASO WCDA

Science.gov (United States)

Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

2018-01-01

Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

The Majorana Low-noise Low-background Front-end Electronics

Science.gov (United States)

Abgrall, N.; Aguayo, E.; Avignone, F. T.; Barabash, A. S.; Bertrand, F. E.; Boswell, M.; Brudanin, V.; Busch, M.; Byram, D.; Caldwell, A. S.; Chan, Y.-D.; Christofferson, C. D.; Combs, D. C.; Cuesta, C.; Detwiler, J. A.; Doe, P. J.; Efremenko, Yu.; Egorov, V.; Ejiri, H.; Elliott, S. R.; Fast, J. E.; Finnerty, P.; Fraenkle, F. M.; Galindo-Uribarri, A.; Giovanetti, G. K.; Goett, J.; Green, M. P.; Gruszko, J.; Guiseppe, V. E.; Gusev, K.; Hallin, A. L.; Hazama, R.; Hegai, A.; Henning, R.; Hoppe, E. W.; Howard, S.; Howe, M. A.; Keeter, K. J.; Kidd, M. F.; Kochetov, O.; Konovalov, S. I.; Kouzes, R. T.; LaFerriere, B. D.; Leon, J.; Leviner, L. E.; Loach, J. C.; MacMullin, J.; MacMullin, S.; Martin, R. D.; Meijer, S.; Mertens, S.; Nomachi, M.; Orrell, J. L.; O'Shaughnessy, C.; Overman, N. R.; Phillips, D. G.; Poon, A. W. P.; Pushkin, K.; Radford, D. C.; Rager, J.; Rielage, K.; Robertson, R. G. H.; Romero-Romero, E.; Ronquest, M. C.; Schubert, A. G.; Shanks, B.; Shima, T.; Shirchenko, M.; Snavely, K. J.; Snyder, N.; Suriano, A. M.; Thompson, J.; Timkin, V.; Tornow, W.; Trimble, J. E.; Varner, R. L.; Vasilyev, S.; Vetter, K.; Vorren, K.; White, B. R.; Wilkerson, J. F.; Wiseman, C.; Xu, W.; Yakushev, E.; Young, A. R.; Yu, C.-H.; Yumatov, V.

The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope 76Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolution performances. We present here the low-noise low- background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.

Tester of the TRT front-end electronics for the ATLAS-experiment

CERN Document Server

Hajduk, Z; Kisielewski, B; Kotarba, A; Malecki, P; Natkaniec, Z; Olszowska, J; Ostrowicz, W; Krupinska, G

2000-01-01

The VME based tester for front-end electronics of the TRT (Transition Radiation Tracker) detector of the ATLAS-LHC experiment at CERN, Geneva, is described. The TRT read-out electronics for 424576 proportional tubes grouped on many thousands of cards requires stringent quality control after assembly and during installation. The tester provides all required data, pulses, timing and power supplies for tested cards. The essential part of the tester is its software that allows for device handling as well as facilitates functional and statistical tests. The prototype, present design as well as the new design for mass production tests are discussed. (17 refs).

A Time-Based Front End Readout System for PET & CT

CERN Document Server

Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

2007-01-01

In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

International Nuclear Information System (INIS)

Kureba, C O; Govender, M; Hofsajer, I; Ruan, X; Sandrock, C; Spoor, M

2015-01-01

The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade. (paper)

Fast front-end electronics for COMPASS MWPCs

CERN Document Server

Colantoni, M L; Ferrero, A; Frolov, V; Grasso, A; Heinz, S; Maggiora, A; Maggiora, M G; Panzieri, D; Popov, A; Tchalyshev, V

2000-01-01

In the COMPASS experiment, under construction at CERN, about 23000 channels of MWPCs will be used. The very high rate of the muon and hadron beams, and the consequently high trigger rate, require front- end electronics with innovative conceptual design. A new MWPC front- end electronics that fulfills the main COMPASS requirement to have a fast DAQ with a minimum dead-time has been designed. The general concept of the front-end cards is described; the comparative tests of two front-end chips, and different fast gas mixtures, are also shown. The commissioning of the experiment will start in the summer 2000, and production running, using the muon beam, is foreseen for the year 2001. (8 refs).

A custom readout electronics for the BESIII CGEM detector

International Nuclear Information System (INIS)

Rolo, M. Da Rocha; Alexeev, M.; Amoroso, A.; Bianchi, F.; Cossio, F.; Mori, F. De; Destefanis, M.; Ferroli, R. Baldini; Chai, J.Y.; Bertani, M.; Calcaterra, A.; Capodiferro, M.; Cerioni, S.; Bettoni, D.; Canale, N.; Carassiti, V.; Chiozzi, S.; Cibinetto, G.; Ramusino, A. Cotta; Bugalho, R.

2017-01-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM

A custom readout electronics for the BESIII CGEM detector

Science.gov (United States)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

Front-end electronics for the ALICE calorimeters

CERN Document Server

Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

2010-01-01

The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

International Nuclear Information System (INIS)

Fleury, J; Ahmad, S; Callier, S; Taille, C de La; Seguin, N; Thienpont, D; Dulucq, F; Martin, G

2014-01-01

Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

A front end ASIC for the readout of the PMT in the KM3NeT detector

International Nuclear Information System (INIS)

Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

2010-01-01

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

Design of the new front-end electronics for the readout of the upgraded CMS electromagnetic calorimeter for the HL-LHC

CERN Document Server

Cometti, Simona

2017-01-01

The Compact Muon Solenoid detector was originally designed to operate for about ten years, for LHC instantaneous luminosities up to $1 \\cdot 10^{34}$ cm$^{-2}$ s$^{-1}$ and integrated luminosity of 500 fb$^{-1}$. The High Luminosity LHC will increase the instantaneous luminosity by about a factor of 5 from current levels and CMS will accumulate an integrated luminosity of 3000 fb$^{-1}$ by about 2035. With such high luminosity the electromagnetic calorimeter of CMS will have to cope with a challenging increase in the number of interactions per bunch crossing and in radiation levels. The front-end readout electronics will be completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a faster pre-amplifier, increase the sampling frequency from 40 MS/s to 160 MS/s and implement a trigger system that resides entirely off-detector.

A segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics for a PET scanner

CERN Document Server

Chesi, Enrico Guido; Joram, C; Mathot, S; Séguinot, Jacques; Weilhammer, P; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

2006-01-01

We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is put on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

CERN Document Server

Andeen, Timothy; The ATLAS collaboration

2018-01-01

The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. First prototypes of the front-end electronics components show good promise to match the stringent specifications. The off-detector electronics will make use of FPGAs connected through high-speed links to perform energy reconstruction, data reduction and buffering. Results of tests of the first prototypes of front-end components will be presented, along with design studies on the performance of the off-detector readout system.

New read-out electronics for ICARUS-T600 liquid Argon TPC. Description, simulation and tests of the new front-end and ADC system arXiv

CERN Document Server

Bagby, L.; Bellini, V.; Bonesini, M.; Braggiotti, A.; Castellani, L.; Centro, S.; Cervi, T.; Cocco, A.G.; Fabris, F.; Falcone, A.; Farnese, C.; Fava, A.; Fichera, F.; Franciotti, D.; Galet, G.; Gibin, D.; Guglielmi, A.; Guida, R.; Ketchum, W.; Marchini, S.; Menegolli, A.; Meng, G.; Menon, G.; Montanari, C.; Nessi, M.; Nicoletto, M.; Pedrotta, R.; Picchi, P.; Pietropaolo, F.; Rampazzo, G.; Rappoldi, A.; Raselli, G.L.; Rossella, M.; Rubbia, C.; Scaramelli, A.; Sergiampietri, F.; Spanu, M.; Torti, M.; Tortorici, F.; Varanini, F.; Ventura, S.; Vignoli, C.; Zani, A.; Zatti, P.G.

The ICARUS T600, a liquid argon time projection chamber (LAr-TPC) detector mainly devoted to neutrino physics, underwent a major overhauling at CERN in 2016-2017, which included also a new design of the read-out electronics, in view of its operation in Fermilab on the Short Baseline Neutrino (SBN) beam from 2019. The new more compact electronics showed capability of handling more efficiently the signals also in the intermediate Induction 2 wire plane with a significant increase of signal to noise (S/N), allowing for charge measurement also in this view. The new front-end and the analog to digital conversion (ADC) system are presented together with the results of the tests on 50 liters liquid argon TPC performed at CERN with cosmic rays.

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

Parallel and pipelined front-end for multi-element silicon detectors in scanning electron microscopy

International Nuclear Information System (INIS)

Boulin, C.; Epstein, A.

1992-01-01

This paper discusses a silicon quadrant detector (128 elements) implemented as an electron detector in a Scanning Transmission Electron Microscope. As the electron beam scans over the sample, electrons are counted during each pixel. The authors developed an ASIC for the multichannel counting system. The digital front-end carries out the readout of all elements, in four groups, and uses these data to compute linear combinations to generate up to eight simultaneous images. For the preprocessing the authors implemented a parallel and pipelined system. Dedicated software tools were developed to generate the programs for all the processors. These tools are transparently accessed by the user via a user friendly interface

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

Energy Technology Data Exchange (ETDEWEB)

Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

2015-07-01

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

Review of input stages used in front end electronics for particle detectors

CERN Document Server

Kaplon, J

2015-01-01

In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

Characterization and performance of monolithic detector blocks with a dedicated ASIC front-end readout for PET imaging of the human brain

International Nuclear Information System (INIS)

Rato Mendes, Pedro; Sarasola Martin, Iciar; Canadas, Mario; Garcia de Acilu, Paz; Cuypers, Robin; Perez, Jose Manuel; Willmott, Carlos

2011-01-01

We are developing a human brain PET scanner prototype compatible with MRI based on monolithic scintillator crystals, APD matrices and a dedicated ASIC front-end readout. In this work we report on the performance of individual detector modules and on the operation of such modules in PET coincidence. Results will be presented on the individual characterization of detector blocks and its ASIC front-end readout, with measured energy resolutions of 13% full-width half-maximum (FWHM) at 511 keV and spatial resolutions of the order of 2 mm FWHM. First results on PET coincidence performance indicate spatial resolutions as good as 2.1 mm FWHM for SSRB/FBP reconstruction of tomographic data obtained using a simple PET demonstrator based on a pair of monolithic detector blocks with ASIC readout.

Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

Science.gov (United States)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

2016-08-01

The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

The upgraded CDF front end electronics for calorimetry

Energy Technology Data Exchange (ETDEWEB)

Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

1991-11-01

The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 {mu}Sec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals.

The upgraded CDF front end electronics for calorimetry

International Nuclear Information System (INIS)

Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

1991-11-01

The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

Directory of Open Access Journals (Sweden)

Trong-Hieu Tran

2016-09-01

Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

CMOS front-end electronics for radiation sensors

CERN Document Server

AUTHOR|(CDS)2071026

2015-01-01

This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

International Nuclear Information System (INIS)

Zeng, Huiming; Wei, Tingcun; Wang, Jia

2017-01-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e − +16.3e − /pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

Energy Technology Data Exchange (ETDEWEB)

Zeng, Huiming; Wei, Tingcun, E-mail: weitc@nwpu.edu.cn; Wang, Jia

2017-03-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e{sup −}+16.3e{sup −}/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

Front-end electronics for the Muon Portal project

Energy Technology Data Exchange (ETDEWEB)

Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M.C. [INAF, Osservatorio Astrofisico di Catania, Via S. Sofia 78, I-95123 Catania (Italy); Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D.G. [Università di Catania, Dipartimento di Fisica e Astronomia, and INFN, Sezione di Catania, Via S. Sofia 64, I-95123 Catania (Italy); Fallica, G.; Valvo, G. [ST-Microelectronics, Stradale V Primosole 50, Catania (Italy)

2016-10-11

The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

Development of a dedicated front-end electronics for straw tube trackers in the P-bar ANDA experiment

International Nuclear Information System (INIS)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Swientek, K.; Terlecki, P.; Tokarz, J.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.

2016-01-01

The design and tests of front-end electronics for straw tube trackers in the P-bar ANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

International Nuclear Information System (INIS)

Bagliesi, M.G.; Avanzini, C.; Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S.; Morsani, F.

2011-01-01

A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

Science.gov (United States)

Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

Front-end electronics for long straw tube systems

International Nuclear Information System (INIS)

Paulos, J.J.; Blake, S.L.

1990-01-01

This paper addresses several critical issues in the readout of long, small diameter plastic straw tubes for central tracking subsystems. Of particular concern are signal attentuation in long straw tubes and signal reflections which arise from improper termination at the ends of the tube. This work is part of a 12 institution collaboration to design and validate a hybrid central tracking chamber (HCTC) utilizing both straw tube and scintillating fiber components. The HCTC design calls for 4 mm diameter plastic straw tubes spanning the entire central tracking region (6-8 m) with readout electronics at both ends. An electrical isolator may be used at the center of each wire to separate each tube into two electrically isolated regions so as to reduce occupancy by a factor of two. With this scheme, no track is farther than 4 m from the associated readout electronics. The HCTC collaboration includes the participation of researchers at the University of Pennsylvania who have contributed a preamplifier and shaper ship which is used in the simulations presented here. A more complete discussion of the HCTC design can be found in the paper by Dr. Alfred Goshaw

Performance of the front-end signal processing electronics for the drift chambers of the Stanford Large Detector

International Nuclear Information System (INIS)

Honma, A.; Haller, G.M.; Usher, T.; Shypit, R.

1990-10-01

This paper reports on the performance of the front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector (SLD) detector at the Stanford Linear Collider. The electronics mounted on printed circuit boards include up to 64 channels of transimpedance amplification, analog sampling, A/D conversion, and associated control circuitry. Measurements of the time resolution, gain, noise, linearity, crosstalk, and stability of the readout electronics are described and presented. The expected contribution of the electronics to the relevant drift chamber measurement resolutions (i.e., timing and charge division) is given

Timing and Readout Contorl in the LHCb Upgraded Readout System

CERN Document Server

Alessio, Federico

2016-01-01

In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

CERN Document Server

Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

The control system for the CMS tracker front-end

CERN Document Server

Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

2002-01-01

The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00567140; The ATLAS collaboration

2017-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events even at rather low transverse energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of 1 MHz are planned, combined with longer latencies up to 60 micro-seconds in order to read out the necessary data from all detector channels. Under these conditions, the current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons a replacement of the LAr front-end and back-end readout system is foreseen for all 182,500 readout channels, with the exception of t...

DAQ system for testing RPC front-end electronics of the INO experiment

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Kesarkar, Tushar A.; Kumar, Sandeep; Chandratre, V.B.; Das, D.; Shinde, R.R.; Satyanarayana, B.

2015-01-01

The Resistive Plate Chamber (RPC) is the active detector element in the INO experiment. The in-house developed ANUSPARSH-III ASICs are being used as front-end electronics of the detector. The 2 m X 2 m RPC being used has 64-readout channels on X-side and 64-readout channels on Y-side. In order to test and validate the FE along with the RPC, a 64-channel DAQ system has been designed and developed. The detector parameters to be measured are noise rate, efficiency, hit pattern register and time resolution. The salient features of the DAQ system are: 64-channel LVDS receiver in FPGA, FPGA based parameter calculations and a micro controller for acquiring the processed data from FPGAs and sent through Ethernet and USB interfaces. The DAQ system consists of following parts: Two FPGAs each receiving 32 LVDS channels, FPGA firm-ware, micro controller firm-ware, Ethernet interface, embedded web server hosting data analysis software, USB interface, and Lab-windows based data analysis software. The DAQ system has been tested at TIFR with 1 m X 1 m RPC

A Full Front End Chain for Drift Chambers

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Panareo, M. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Primiceri, P. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Tassielli, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Fermilab, Batavia, Illinois (United States); Università Marconi, Roma (Italy)

2014-03-01

We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift tube and represents the outcome of balancing between efficiency and high speed performance.

Highly integrated front-end electronics for spaceborne fluxgate sensors

International Nuclear Information System (INIS)

Magnes, W; Valavanoglou, A; Hagen, C; Jernej, I; Baumjohann, W; Oberst, M; Hauer, H; Neubauer, H; Pierce, D; Means, J; Falkner, P

2008-01-01

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm 2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability ( −1 MFA temperature, −1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm 2 mg −1

R&D Studies of the ATLAS LAr Calorimeter Readout Electronics for super-LHC

CERN Document Server

Chen, H

2010-01-01

The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors, total about 180,000 signals are digitized and processed real-time on detector, to provide energy and time deposited in each detector element at every occurrence of the L1-trigger. A luminosity upgrade (x10) of the LHC will occur ~2017, the current readout electronics will have to be upgraded to sustain the higher radiation levels. A completely innovative readout scheme is being developed. The front-end readout will send out data continuously at each bunch crossing through high speed radiation resistant optical links, the data will be processed real-time with the possibility of implementing trigger algorithms. This article is an overview of the R&D activities and architectural studies the ATLAS LAr collaboration is developing: front-end analog and mixed-signal ASIC design, radiation resistance optical-links in SOS, high-speed back-end processing units based on FPGA architectures and power supply d...

SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

International Nuclear Information System (INIS)

Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

2013-06-01

In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

A GEM-TPC prototype with low-Noise highly integrated front-end electronics for linear collider studies

CERN Document Server

Kappler, Steffen; Kaminski, Jochen; Ledermann, Bernhard; Müller, Thomas; Ronan, Michael T; Ropelewski, Leszek; Sauli, Fabio; Settles, Ronald

2004-01-01

Connected to the linear collider project, studies on the readout of time projection chambers (TPCs) based on the gas electron multiplier (GEM) are ongoing. Higher granularity and intrinsically suppressed ion feedback are the major advantages of this technology. After a short discussion of these issues, we present the design of a small and very flexible TPC prototype, whose cylindrical drift volume can be equipped with endcaps of different gas detector types. An endcap with multi-GEM readout is currently set up and successfully operated with a low-noise highly integrated front-end electronics. We discuss results of measurements with this system in high intensity particle beams at CERN, where 99.3 plus or minus 0.2% single-pad-row efficiency could be achieved at an effective gain of 2.5 multiplied by 10**3 only, and spatial resolutions down to 63 plus or minus 3 mum could be demonstrated. Finally, these results are extrapolated to the high magnetic field in a linear collider TPC. 5 Refs.

A Real Time Electronics Emulator with Realistic Data Generation for Reception Tests of the CMS ECAL Front-End Boards

CERN Document Server

Romanteau, T; Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N

2005-01-01

The CMS [1] electromagnetic calorimeter (ECAL) [2] uses 3 132 Front-End boards (FE) performing both trigger and data readout functions. Prior to their integration at CERN, the FE boards have to be validated by dedicated test bench systems. The final one, called "XFEST" (eXtended Front-End System Test) and for which the present developments have been performed, is located at Laboratoire Leprince-Ringuet. In this contribution, a solution is described to efficiently test a large set of complex electronics boards characterized by a large number of input ports and a high throughput data rate. To perform it, an algorithm to simulate the Very Front End signals has been emulated. The project firmwares use VHDL embedded into XILINX Field Programmable Gate Array circuits (FPGA). This contribution describes the solutions developed in order to create a realistic digital input patterns real-time emul ator working at 40 MHz. The implementation of a real time comparison of the FE output streams as well as the test bench wil...

The LHCb front-end electronics and data acquisition system

CERN Document Server

Jost, B

2000-01-01

The LHCb experiment is the most recently approved of the four experiments under construction at CERN's LHC accelerator. It is a special purpose experiment designed to precisely measure the CP violation parameters in the B-B system and to study rare B-decays. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. We therefore decided to implement a four-level triggering scheme. The LHCb data acquisition (DAQ) system will have to cope with an average trigger rate of 40 kHz, after two levels of hardware triggers, and an average event size of 100 kB. Thus, an event-building network which can sustain an average bandwidth of 4 GB /s is required. A powerful software trigger farm will have to be installed to reduce the rate from 40 kHz to 100 Hz of events written for permanent storage. In this paper we will outline the general architectures of the front-end electronics and of the trigger and DAQ system and the readout protocols...

Data acquisition at the front-end of the Mu3e pixel detector

Energy Technology Data Exchange (ETDEWEB)

Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

2016-07-01

The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

Energy Technology Data Exchange (ETDEWEB)

Sahin, Mehmet Oezguer

2017-04-15

previous searches with the 8 TeV center-of-mass energy in the single lepton final states is extended to m{sub t} = 675 GeV and m{sub χ{sup 0}} = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

International Nuclear Information System (INIS)

Sahin, Mehmet Oezguer

2017-04-01

the 8 TeV center-of-mass energy in the single lepton final states is extended to m_t = 675 GeV and m_χ_"0 = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

The new version of the LHCb SOL40-SCA core to drive front-end GBT-SCAs for the LHCb upgrade

CERN Document Server

Viana Barbosa, Joao Vitor; Gaspar, Clara

2018-01-01

The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

Cold front-end electronics and Ethernet-based DAQ systems for large LAr TPC readout

CERN Document Server

D.Autiero,; B.Carlus,; Y.Declais,; S.Gardien,; C.Girerd,; J.Marteau; H.Mathez

2010-01-01

Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detectors implies severe constraints on their readout and DAQ system. We are carrying on a R&D in electronics on a complete readout chain including an ASIC located close to the collecting planes in the argon gas phase and a DAQ system based on smart Ethernet sensors implemented in a µTCA standard. The choice of the latter standard is motivated by the similarity in the constraints with those existing in Network Telecommunication Industry. We also developed a synchronization scheme developed from the IEEE1588 standard integrated by the use of the recovered clock from the Gigabit link

Performance of Front-End Readout System for PHENIX RICH

International Nuclear Information System (INIS)

Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

1999-01-01

A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Document Server

Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

International Nuclear Information System (INIS)

Alessio, F.; Gaspar, C.; Jacobsson, R.; Wyllie, K.; Caplan, C.

2015-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

International Nuclear Information System (INIS)

Anderson, J; Drake, G; Ryu, S; Zhang, J; Borga, A; Boterenbrood, H; Schreuder, F; Vermeulen, J; Chen, H; Chen, K; Lanni, F; Francis, D; Gorini, B; Miotto, G Lehmann; Schumacher, J; Vandelli, W; Levinson, L; Narevicius, J; Roich, A; Plessl, C

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed. (paper)

Front-end data processing the SLD data acquisition system

International Nuclear Information System (INIS)

Nielsen, B.S.

1986-07-01

The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B0s → J/ψ Φ

International Nuclear Information System (INIS)

Knopf, Jan

2009-01-01

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Φ s . It can be measured by using the golden decay mode B 0 s → J/ψ Φ. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

CERN Document Server

Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

2012-01-01

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Multimedia

Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

International Nuclear Information System (INIS)

Chen, Y.T.; La Taille, C. de; Suomijärvi, T.; Cao, Z.; Deligny, O.; Dulucq, F.; Ge, M.M.; Lhenry-Yvon, I.; Martin-Chassard, G.; Nguyen Trung, T.; Wanlin, E.; Xiao, G.; Yin, L.Q.; Yun Ky, B.; Zhang, L.; Zhang, H.Y.; Zhang, S.S.; Zhu, Z.

2015-01-01

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

Energy Technology Data Exchange (ETDEWEB)

Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

2015-09-21

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

LHCb: Test Station for the LHCb Muon Front-End Electronic

CERN Multimedia

Polycarpo, E

2005-01-01

The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

The upgrade of the multiwire drift chamber readout of the HADES experiment at GSI: the optical end point board

Energy Technology Data Exchange (ETDEWEB)

Tarantola, Attilio; Michel, Jan; Muentz, Christian; Stroth, Joachim [Institut fuer Kernphysik, Goethe-Universitaet, Frankfurt (Germany); GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Froehlich, Ingo; Stroebele, Herbert [Institut fuer Kernphysik, Goethe-Universitaet, Frankfurt (Germany); Kolb, Burkhard; Traxler, Michael [GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Palka, Marek [Smoluchowski Institute of Physics, Jagiellonian University, Krakow (Poland); GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Wuestenfeld, Joern [Institut fuer Strahlenphysik, Forschungszentrum, Dresden-Rossendorf (Germany)

2009-07-01

One of the goal of the HADES upgrade project is the realization of a new data acquisition scheme for the 24 Multiwire Drift Chambers (MDCs), which allows to increase the readout speed of the 40.000 TDC channels. On the existing MDC Front End Electronic (FEE) side an Optical End Point Board (OEPB) has been designed to control configuration and readout of the chamber's TDCs. The OEPB uses Plastic Optical Fibres (POF) for data transmission, which results in total electromagnetic immunity, amazing simplicity in handling and low power consumption. The employment of a Lattice ECP2/M FPGA with SERDES manages serial data transmission and its large resources allow for the storage of several events close-to-front-end. As 400 OEPBs will be located in the detector acceptance, dedicated FPGA hardware is used to detect Single Event Upsets (SEUs).

Rabbit System. Low cost, high reliability front end electronics featuring 16 bit dynamic range

International Nuclear Information System (INIS)

Drake, G.; Droege, T.F.; Nelson, C.A. Jr.; Turner, K.J.; Ohska, T.K.

1985-10-01

A new crate-based front end system has been built which features low cost, compact packaging, command capability, 16 bit dynamic range digitization, and a high degree of redundancy. The crate can contain a variety of instrumentation modules, and is designed to be situated close to the detector. The system is suitable for readout of a large number of channels via parallel multiprocessor data acquisition

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

2004-01-01

A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall

Science.gov (United States)

Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.

2010-10-01

A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m2, divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade .

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

International Nuclear Information System (INIS)

Alexanian, H.; Appelquist, G.; Bailly, P.

1995-01-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

Science.gov (United States)

Prele, D.

2015-08-01

As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

International Nuclear Information System (INIS)

Prele, D.

2015-01-01

As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

Energy Technology Data Exchange (ETDEWEB)

Knopf, Jan

2009-07-08

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

The Readout Control Unit of the ALICE TPC

CERN Document Server

Lien, J A; Musa, L

2004-01-01

The ALICE Time Projection Chamber (TPC) is the main tracking detector of the central barrel of the ALICE (A Large Ion Collider) Experiment at the Large Hadron Collider (LHC), being constructed at CERN, Geneva. It is a 88 m$^{3}$ cylinder filled with gas and divided into two drift regions by the central electrode located at its axial center. The readout chambers of the TPC are multi-wire proportional chambers with cathode pad readout. About 570 000 pads are read-out by an electronics chain of amplification, digitalization and pre-processing. One of the challenges in designing the TPC for ALICE is the design of Front End Electronics (FEE) to cope with the data rates and the channel occupancy. The Readout Control Unit (RCU), which is presented in this work, is designed to control and monitor the Front End Electronics, and to collect and ship data to the High Level Trigger and the Data Acquisition System, via the Detector Data Link (DDL - optical fibre). The RCU must be capable of reading out up to 200 Mbytes/s f...

The front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector

International Nuclear Information System (INIS)

Haller, G.M.; Freytag, D.R.; Fox, J.; Olsen, J.; Paffrath, L.; Yim, A.; Honma, A.

1990-10-01

The front-end signal processing electronics for the drift-chambers of the Stanford Large Detector (SLD) at the Stanford Linear Collider is described. The system is implemented with printed-circuit boards which are shaped for direct mounting on the detector. Typically, a motherboard comprises 64 channels of transimpedance amplification and analog waveform sampling, A/D conversion, and associated control and readout circuitry. The loaded motherboard thus forms a processor which records low-level wave forms from 64 detector channels and transforms the information into a 64 k-byte serial data stream. In addition, the package performs calibration functions, measures leakage currents on the wires, and generates wire hit patterns for triggering purposes. The construction and operation of the electronic circuits utilizing monolithic, hybridized, and programmable components are discussed

The PHENIX Drift Chamber Front End Electroncs

Science.gov (United States)

Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

1998-04-01

The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

International Nuclear Information System (INIS)

Blaha, J.

2008-05-01

A Very-Front-End (VFE) card is an important part of the on-detector read-out electronics of the CMS (Compact Muon Solenoid) electromagnetic calorimeter that is made of ∼ 76.000 radiation hard scintillating crystals PbWO 4 and operates on the Large Hadron Collider (LHC) at CERN. Almost 16.000 VFE cards that shape, amplify and digitize incoming signals from photodetectors generated by interacting particles. Since any maintenance of any part of the calorimeter is not possible during the 10-year lifetime of the experiment, the extensive screening program was employed throughout the whole manufacture process. As a part of readout electronics quality assurance program, the systems for burn-in and precise calibration of the VFE boards were developed and successfully used at IPN Lyon. In addition to functionality tests, all relevant electrical properties of each card were measured and analyzed in detail to obtain their full characterization and to build a database with all required parameters which will serve for the initial calibration of the whole calorimeter. In order to evaluate the calorimeter performance and also to deliver the most precise calibration constants, several fully equipped super-modules were extensively studied and calibrated during the test beam campaigns at CERN. As an important part of these tests, accurate studies of the electronics noise and relative gains, which are needed for measurement in high energy range, were carried out to optimize amplitude reconstruction procedure and thus improve the precision of the calorimeter energy determination. The heart of the thesis consists of the calibration of all VFE boards, including optimization of the laboratory calibration system and precise analysis of measured values to delivered desired calibration constants. The second half of the thesis is focused on the accurate evaluation and optimization of the read-out electronics in real data taking conditions. The results obtained in the laboratory at IPN Lyon

Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC

CERN Document Server

Strässner, A

2009-01-01

The ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2017, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gbps per front-end board, each covering 128 readout channels. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system will be ...

The STAR Heavy Flavor Tracker PXL detector readout electronics

International Nuclear Information System (INIS)

Schambach, J.; Contin, G.; Greiner, L.; Stezelberger, T.; Vu, C.; Sun, X.; Szelezniak, M.

2016-01-01

The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel ('PXL') subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector

The NA62 LAV front-end electronics and the L0 trigger generating firmware

CERN Document Server

Gonnella, Francesco; Corradi, Giovanni; Kozhuharov , Venelin ; Martellotti, Silvia; Moulson, Matthew; Raggi, Mauro; Spadaro, Tommaso

2014-01-01

The aim of the NA62 experiment is to measure the branching ratio of the decay K + ! p + n ̄ n to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from p + p 0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is 100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed.

Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

Energy Technology Data Exchange (ETDEWEB)

Budden, B.S., E-mail: bbudden@lanl.gov [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Stonehill, L.C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D.D.S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Kamto, J. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Electrical & Computer Engineering Department, Praire View A& M University, Prairie View, TX 77446 (United States)

2015-09-21

A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.

Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

2015-09-16

The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

CERN Document Server

Ochoa, Ines; The ATLAS collaboration

2017-01-01

Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, and performances on prototypes will presented with the overall system design.

A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

Energy Technology Data Exchange (ETDEWEB)

Liu, Wei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun, E-mail: weitc@nwpu.edu.cn [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Li, Bo; Yang, Lifeng; Xue, Feifei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

2016-05-11

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of −1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm{sup 2}. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

Front-end electronics for H.E.P

International Nuclear Information System (INIS)

Hrisoho, A.

1990-07-01

A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

CERN Document Server

Chen, H; The ATLAS collaboration

2011-01-01

The ATLAS experiment is one of the two general-purpose detectors designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS (and its LAr Calorimeters) has been operating and collecting p-p collisions at LHC since 2009. The on-detector electronics (front-end) part of the current readout electronics of the calorimeters measures the ionization current signals by means of preamplifiers, shapers and digitizers and then transfers the data to the off-detector electronics (back-end) for further elaboration, via optical links. Only the data selected by the level-1 calorimeter trigger system are transferred, achieving a bandwidth reduction to 1.6 Gbps. The analog trigger sum sig...

VME as a front-end electronics system in high energy physics experiments

International Nuclear Information System (INIS)

Ohska, T.K.

1990-01-01

It is only a few years since the VME became a standard system, yet the VME system is already so much more popular than other systems. The VME system was developed for industrial applications and not for the scientific research, and high energy physics field is a tiny market when compared with the industrial market. Considerations made here indicate that the VME system would be a good one for a rear-end system, but would not be a good candidate for front-end electronics in physics experiments. Furthermore, there is a fear that the VXI bus could become popular in this field of instrumentation since the VXI system is backed up by major suppliers of instrumentation in the high energy physics field. VXI would not be an adequate system for front-end electronics, yet advertised to be one. It would be worse to see the VXI system to become a standard system for high energy physics instrumentation than the VME system to be one. The VXI system would do a mediocre job so that people might be misled to think that the VXI system can be used as front-end system. (N.K.)

Photodetectors and front-end electronics for the LHCb RICH upgrade

Science.gov (United States)

Cassina, L.; LHCb RICH

2017-12-01

The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

International Nuclear Information System (INIS)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

2015-01-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

Energy Technology Data Exchange (ETDEWEB)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

2015-07-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

New RPC front-end electronics for hades

CERN Document Server

Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

2007-01-01

Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

Development of front-end electronics and TDC LSI for the ATLAS MDT

CERN Document Server

Arai, Y

2000-01-01

Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

2015-07-01

The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

Low noise monolithic CMOS front end electronics

International Nuclear Information System (INIS)

Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

1987-01-01

Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

International Nuclear Information System (INIS)

Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

2010-01-01

The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Enari, Yuji; The ATLAS collaboration

2018-01-01

Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, performances of the final prototypes and results of the system integration tests will presented along with the overall system design.

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

International Nuclear Information System (INIS)

Erdinger, Florian

2016-01-01

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

Energy Technology Data Exchange (ETDEWEB)

Erdinger, Florian

2016-11-22

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Front-end electronics for the upgraded GMRT

International Nuclear Information System (INIS)

Raut, Anil N; Bhalerao, Vilas; Kumar, A Praveen

2013-01-01

This paper first describes briefly the existing front-end receiver in use at the GMRT observatory and then details the ongoing development of next generation receiver systems for the upgraded GMRT. It covers the design of the new, two stage, room temperature, low noise amplifiers with better noise performance and matching, and improved dynamic range that are being implemented for the 130–260 MHz, 250–500 MHz and 550–900 MHz bands of the upgraded GMRT front-end systems.

Front-End Electronics in calorimetry: from LHC to ILC

International Nuclear Information System (INIS)

De La Taille, Ch.

2009-09-01

This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

Development of a 10-inch HPD with integrated readout electronics

CERN Document Server

Braem, André; Joram, C; Séguinot, Jacques; Weilhammer, Peter; Giunta, M; Malakhov, N; Menzione, A; Pegna, R; Piccioli, A; Raffaelli, F; Sartori, G

2003-01-01

A round 10-in. diameter Hybrid Photodiode (HPD) with spherical entrance window is under development for Cherenkov imaging applications in cosmic ray astronomy. The HPD adopts the fountain focusing electron optics, which, as already demonstrated in the 5 inch Pad HPD, allows for a linear demagnification of the image over practically the full tube diameter. Self-triggering front-end electronics providing also sparse readout capability, has been tested. High-efficiency Rb//2Te cathodes have been produced on a UV extended borosilicate glass windows with very thin conductive underlayers of Indium Tin Oxide. We report on the design of the 10- in. HPD, the fabrication procedure and first tests of a 5-in. HPD with Rb//2Te photocathode and 2048 channels.

Readout and trigger electronics for the TPC vertex chamber

International Nuclear Information System (INIS)

Ronan, M.T.; Jared, R.C.; McGathen, T.K.; Eisner, A.M.; Broeder, W.J.; Godfrey, G.L.

1987-10-01

The introduction of the vertex chamber required the addition of new front-end electronics and a new 1024-channel, high-accuracy TDC system. The preamplifier/discriminator should be capable of triggering on the first electrons and the time digitzer should preserve the measurement resolution. For the TDC's, in order to maintain compatibility with the existing TPC readout system, an upgrade of a previous inner drift chamber digitizer system has been chosen. Tests of the accuracy and stability of the original design indicated that the new design specifications would be met. The TPC detector requires a fast pretrigger to turn on its gating grid within 500 ns of the e/sup +/e/sup -/ beam crossing time, to minimize the loss of ionization information. A pretrigger based on the Straw Chamber signals, operating at a rate of about 2 K/sec, will be used for charged particle final states. In addition, in order to reject low mass Two-Photon events at the final trigger level, an accurate transverse momentum cutoff will be made by the Straw Chamber trigger logic. In this paper, we describe the readout and trigger electronics systems which have been built to satisfy the above requirements. 5 refs., 8 figs

Test of the CMS microstrip silicon tracker readout and control system

CERN Document Server

Zghiche, A

2001-01-01

The Microstrip Silicon tracker of the CMS detector is designed to provide robust particle tracking and vertex reconstruction within a strong magnetic field in the high luminosity environment of the LHC. The Tracker readout system employs Front-End Driver cards to digitize and buffer the analogue data arriving via optical links from on detector pipeline chips. The control chain of the front-end electronic is built to operate via optical fibers in order to shield the communications from the outside noise. Components close to the final design have been assembled to be tested in the X5 beam area at CERN where a dedicated 25 ns temporal structure beam has been made available by the SPS. This paper describes the hardware and the software developed for readout and control of data acquired by the front-end electronics operating at 40 MHz, Some preliminary results of the tests performed in the 25 ns beam are also given. (8 refs).

The HADES-RICH upgrade using Hamamatsu H12700 MAPMTs with DiRICH FEE + Readout

Science.gov (United States)

Patel, V.; Traxler, M.

2018-03-01

The High Acceptance Di-Electron Spectrometer (HADES) is operational since the year 2000 and uses a hadron blind RICH detector for electron identification. The RICH photon detector is currently replaced by Hamamatsu H12700 MAPMTs with a readout system based on the DiRICH front-end module. The electronic readout chain is being developed as a joint effort of the HADES-, CBM- and PANDA collaborations and will also be used in the photon detectors for the upcoming Compressed Baryonic Matter (CBM) and PANDA experiments at FAIR . This article gives a brief overview on the photomultipliers and their quality assurance test measurements, as well as first measurements of the new DiRICH front-end module in final configurations.

The hybridized front end electronics of the Central Drift Chamber in the Stanford Linear Collider Detector

International Nuclear Information System (INIS)

Lo, C.C.; Kirsten, F.A.; Nakamura, M.

1987-10-01

In order to accommodate the high packaging density requirements for the front end electronics of the Central Drift Chamber (CDC) in the SLAC Linear Collider Detector (SLD), the CDC front end electronics has been hybridized. The hybrid package contains eight channels of amplifiers together with all the associated circuits for calibration, event recognition and power economy switching functions. A total of 1280 such hybrids are used in the CDC

Online readout and control unit for high-speed/high resolution readout of silicon tracking detectors

International Nuclear Information System (INIS)

Buerger, J.; Hansen, K.; Lange, W.; Nowak, T.; Prell, S.; Zimmermann, W.

1997-01-01

We are describing a high speed VME readout and control module developed and presently working at the H1 experiment at DESY in Hamburg. It has the capability to read out 4 x 2048 analogue data channels at sampling rates up to 10 MHz with a dynamic input range of 1 V. The nominal resolution of the A/D converters can be adjusted between 8 and 12 bit. At the latter resolution we obtain signal-to-noise ratio better than 61.4 dB at a conversion rate of 5 MSps. At this data rate all 8192 detector channels can be read out to the internal raw data memory and VME interface within about 410 μs and 510 μs, respectively. The pedestal subtracted signals can be analyzed on-line. At a raw data hit occupation of 10%, the VME readout time is 50 μs per module. Each module provides four complementary CMOS signals to control the front-end electronics and four independent sets of power supplies for analogue and digital voltages (10 V, 100 mA) to drive the front-end electronics and for the bias voltage (100 V, 1.2 mA) to assure the full functionality of the detectors and the readout. (orig.)

Online readout and control unit for high-speed/high resolution readout of silicon tracking detectors

Science.gov (United States)

Bürger, J.; Hansen, K.; Lange, W.; Nowak, T.; Prell, S.; Zimmermann, W.

1997-02-01

We are describing a high speed VME readout and control module developed and presently working at the H1 experiment at DESY in Hamburg. It has the capability to read out 4 × 2048 analogue data channels at sampling rates up to 10 MHz with a dynamic input range of 1 V. The nominal resolution of the A/D converters can be adjusted between 8 and 12 bit. At the latter resolution we obtain signal-to-noise ratio better than 61.4 dB at a conversion rate of 5 MSps. At this data rate all 8192 detector channels can be read out to the internal raw data memory and VME interface within about 410 μs and 510 μs, respectively. The pedestal subtracted signals can be analyzed on-line. At a raw data hit occupation of 10%, the VME readout time is 50 μs per module. Each module provides four complementary CMOS signals to control the front-end electronics and four independent sets of power supplies for analogue and digital voltages (10 V, 100 mA) to drive the front-end electronics and for the bias voltage (100 V, 1.2 mA) to assure the full functionality of the detectors and the readout.

Online readout and control unit for high-speed / high resolution readout of silicon tracking detectors

International Nuclear Information System (INIS)

Buerger, J.; Hansen, K.; Lange, W.; Nowak, T.; Prell, S.; Zimmermann, W.

1996-09-01

We are describing a high speed VME readout and control module developed and presently working at the H1 experiment at DESY in Hamburg. It has the capability to read out 4 x 2048 analogue data channels at sampling rates up to 10 MHz with a dynamic input range of 1 V. The nominal resolution of the A/D converters can be adjusted between 8 and 12 bit. At the latter resolution we obtain signal-to-noise ratio better than 61.4 dB at a conversion rate of 5 MSps. At this data rate all 8192 detector channels can be read out to the internal raw data memory and VME interface within about 410 μs and 510 μs, respectively. The pedestal subtracted signals can be analyzed on-line. At a raw data hit occupation of 10%, the VME readout time is 50 μs per module. Each module provides four complementary CMOS signals to control the front-end electronics and four independent sets of power supplies for analogue and digital voltages (10 V, 100 mA) to drive the front-end electronics and for the bias voltage (100 V, 1.2 mA) to assure the full functionality of the detectors and the readout. (orig.)

Strip detectors read-out system user's guide

International Nuclear Information System (INIS)

Claus, G.; Dulinski, W.; Lounis, A.

1996-01-01

The Strip Detector Read-out System consists of two VME modules: SDR-Flash and SDR-seq completed by a fast logic SDR-Trig stand alone card. The system is a self-consistent, cost effective and easy use solution for the read-out of analog multiplexed signals coming from some of the front-end electronics chips (Viking/VA chips family, Premus 128 etc...) currently used together with solid (silicon) or gas microstrip detectors. (author)

The CMS Tracker Readout Front End Driver

CERN Document Server

Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

2004-01-01

The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

Development of new readout electronics for the ATLAS LAr Calorimeter at the sLHC

CERN Document Server

Strässner, A

2009-01-01

The readout of the ATLAS Liquid Argon (LAr) calorimeter is a complex multi-channel system to amplify, shape, digitize and process signals of the detector cells. The current on-detector electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2019/2020, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gb/s per front-end board. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system is given. The current R&D activities and architectural studies of the LAr Calorimeter group...

Test of high time resolution MRPC with different readout modes for the BESIII upgrade

Energy Technology Data Exchange (ETDEWEB)

Yang, S. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Sun, Y.J., E-mail: sunday@ustc.edu.cn [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Li, C., E-mail: licheng@ustc.edu.cn [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Heng, Y.K.; Qian, S. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Chen, H.F.; Chen, T.X. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Dai, H.L. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Fan, H.H.; Liu, S.B. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Liu, S.D.; Jiang, X.S. [Institute of High Energy Physics, Chinese Academy of Sciences(IHEP), Beijing 100049 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China); Shao, M.; Tang, Z.B.; Zhang, H.; Zhao, Z.G. [Department of Modern Physics, University of Science and Technology of China(USTC), Hefei 230026 (China); State Key Laboratory of Particle Detection and Electronics(USTC-IHEP) (China)

2014-11-01

In order to further enhance the particle identification capability of the Beijing Spectrometer (BESIII), it is proposed to upgrade the current end-cap time-of-flight (eTOF) detector with multi-gap resistive plate chamber (MRPC). The prototypes, together with the front end electronics (FEE) and time digitizer (TDIG) module have been tested at the E3 line of Beijing Electron Positron Collider (BEPCII) to study the difference between the single and double-end readout MRPC designs. The time resolutions (sigma) of the single-end readout MRPC are 47/53 ps obtained by 600 MeV/c proton/pion beam, while that of the double-end readout MRPC is 40 ps (proton beam). The efficiencies of three MRPC modules tested by both proton and pion beam are better than 98%. For the double-end readout MRPC, no incident position dependence is observed.

MDT-ASD, CMOS front-end for ATLAS MDT

CERN Document Server

Posch, C; Oliver, J

2007-01-01

This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

The read-out chain of the CBM STS detector

Energy Technology Data Exchange (ETDEWEB)

Lehnert, Joerg; Emschermann, David [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH (Germany); Collaboration: CBM-Collaboration

2016-07-01

The Compressed Baryonic Matter (CBM) experiment at FAIR will explore the QCD phase diagram at high baryon densities during nucleus-nucleus collisions in a fixed target setup. Its physics goals require interaction rates up to 10 MHz, which can be exploited with fast and radiation hard detectors equipped with free-streaming front-end and readout electronics, connected to a common Data Aquisition (DAQ) system to forward data to the First Level Event Selector (FLES). The core component of the CBM DAQ system is the Data Processing Board (DPB) implementing three important functionalities: - The incoming data via multiple lower-speed, short distance links is preprocessed, concentrated and forwarded to the FLES via higher-speed, long distance links. - The DPBs provide an interface for the Detector Control System (DCS) to configure readout and front-end electronics (FEE). - As part of the Timing and Fast Control (TFC) system the DPBs ensure transmission of the reference clock and synchronous commands necessary to synchronize the FEE. This contribution presents the readout and DAQ chain on the example of the core subdetector, the Silicon Tracking System (STS).

Development of a multi-channel front-end electronics module based on ASIC for silicon strip array detectors

International Nuclear Information System (INIS)

Zhao Xingwen; Yan Duo; Su Hong; Qian Yi; Kong Jie; Zhang Xueheng; Li Zhankui; Li Haixia

2014-01-01

The silicon strip array detector is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou (HIRFL-CSR). Using the ASICs, the front-end electronics module has been developed for the silicon strip array detectors and can implement measurement of energy of 96 channels. The performance of the front-end electronics module has been tested. The energy linearity of the front-end electronics module is better than 0.3% for the dynamic range of 0.1∼0.7 V. The energy resolution is better than 0.45%. The maximum channel crosstalk is better than 10%. The channel consistency is better than 1.3%. After continuously working for 24 h at room temperature, the maximum drift of the zero-peak is 1.48 mV. (authors)

Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2015-07-01

The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

Coherent operation of detector systems and their readout electronics in a complex experiment control environment

Energy Technology Data Exchange (ETDEWEB)

Koestner, Stefan [CERN (Switzerland)], E-mail: koestner@mpi-halle.mpg.de

2009-09-11

With the increasing size and degree of complexity of today's experiments in high energy physics the required amount of work and complexity to integrate a complete subdetector into an experiment control system is often underestimated. We report here on the layered software structure and protocols used by the LHCb experiment to control its detectors and readout boards. The experiment control system of LHCb is based on the commercial SCADA system PVSS II. Readout boards which are outside the radiation area are accessed via embedded credit card sized PCs which are connected to a large local area network. The SPECS protocol is used for control of the front end electronics. Finite state machines are introduced to facilitate the control of a large number of electronic devices and to model the whole experiment at the level of an expert system.

Analog lightwave links for detector front-ends at the LHC

International Nuclear Information System (INIS)

Baird, A.; Dowell, J.; Duthie, P.

1995-01-01

Lightwave links are being developed for volume application in the transfer of analog signals from the tracking detector front-ends to the readout electronics. The links are based on electro-optic intensity modulators which are mounted on detectors and connected by optical fibers to remotely located transceivers (lasers and photoreceivers). The modulators are 3--5 semiconductor reflective devices based on multi-quantum well structures. The transceivers will be integrated devices of a novel design. Modulator prototypes have been fabricated and tested. Neutron and γ-ray irradiation studies have been performed on modulators and fibers. The main results achieved so far are reported and key system issues are reviewed. This work is part of the CERN DRDC project RD23 project RD23

Characterization of front-end electronics for CZT based handheld radioisotope identifier

Energy Technology Data Exchange (ETDEWEB)

Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

2016-01-22

A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

Readout chip for the CMS pixel detector upgrade

Energy Technology Data Exchange (ETDEWEB)

Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

2014-11-21

For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

PMF: The front end electronic of the ALFA detector

Energy Technology Data Exchange (ETDEWEB)

Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

2010-11-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2010-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

Design of analog front-ends for the RD53 demonstrator chip

CERN Document Server

Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

2017-01-01

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00069444; The ATLAS collaboration

2017-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile- up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events at electroweak energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of up to 1 MHz are planned, combined with longer latencies up to 40 micro-seconds in order to read out the necessary data from all detector channels. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. For these reasons a replacement of the LAr front-end and off-detector readout systems is foreseen for all 182,500 readout channels, with the exception of the cold pre-amplifier and summing devices of the hadronic LAr Calorimeter. The new low-power electronics must be able to capture the triangular dete...

An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

The New APD Based Readout for the Crystal Barrel Calorimeter

International Nuclear Information System (INIS)

Urban, M; Honisch, Ch; Steinacher, M

2015-01-01

The CBELSA/TAPS experiment at ELSA measures double polarization observables in meson photoproduction off protons and neutrons. To be able to measure purely neutral reactions off polarized neutrons with high efficiency, the main calorimeter has to be integrated into the first level trigger. This requires to exchange the existing PIN photo diode by a new avalanche photo diode (APD) readout. The newly developed readout electronics will provide an energy resolution compatible to the previous set-up and a fast trigger signal down to 10 MeV energy deposit per crystal. After the successful final tests with a 3x3 CsI crystal matrix in Bonn at ELSA and in Mainz at MAMI all front-end electronics were produced in fall 2013. Automated test routines for the front-end electronics were developed and the characterization measurements of all APDs were successfully accomplished in Bonn. The project is supported by the Deutsche Forschungsgemeinschaft (SFB/TR16) and Schweizerischer Nationalfonds

Development of the control system of the ALICE Transition Radiation Detector and of a test environment for quality-assurance of its front-end electronics

CERN Document Server

Mercado Pérez, Jorge

2008-01-01

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE.

Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

International Nuclear Information System (INIS)

Mercado Perez, Jorge

2008-01-01

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

Energy Technology Data Exchange (ETDEWEB)

Mercado Perez, Jorge

2008-11-10

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

A Front-End Readout Architecture for the CMS Barrel Muon Detector: A Feasibility Study

International Nuclear Information System (INIS)

Aguayo, P.; Alberdi, J.; Barcala, J.M.; Marin, J.; Molinero, A.; Navarrete, J.; Pablos, J.L. de; Romero, L.; Willmot, C.

1995-01-01

A feasibility study of a possible architecture for the CMS barrel muon detector readout electronics is presented. some aspects of system reliability are discussed. Values for the required FIFO's to store data during the first level trigger latency are given

A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

International Nuclear Information System (INIS)

Alves, J.; Carrio, F.; Moreno, P.; Usai, G.; Valero, A.; Kim, H.Y.; Minashvili, I.; Shalyugin, A.; Reed, R.; Schettino, V.; Souza, J.; Solans, C.

2013-06-01

This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS

International Nuclear Information System (INIS)

DE GERONIMO, G.; O CONNOR, P.; KANDASAMY, A.; GROSHOLZ, J.

2002-01-01

A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 (micro)m CMOS and tested. Design concepts and experimental results are discussed

Electronics development for the ATLAS liquid argon calorimeter trigger and readout for future LHC running

Energy Technology Data Exchange (ETDEWEB)

Hopkins, Walter

2017-02-11

The upgrade of the LHC will provide 7 times greater instantaneous and 10 times greater total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019–2020, a trigger readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024–2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energies of all cells will be available at the second trigger level operating at 1 MHz, in order to allow further mitigation of pile-up effects in energy reconstruction. Radiation tolerant, low-power front-end electronics optimized for high pile-up conditions are currently being developed, including pre-amplifier, ADC and serializer components in 65–180 nm technology. This contribution will give an overview of the future LAr readout electronics and present research results from the two upgrade programs.

Anode front-end electronics for the cathode strip chambers of the CMS Endcap Muon detector

International Nuclear Information System (INIS)

Ferguson, T.; Bondar, N.; Golyash, A.; Sedov, V.; Terentiev, N.; Vorobiev, I.

2005-01-01

The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183,000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3x2.5 m 2 ) and for the large input capacitance (up to 200 pF). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2-3 ns). The delay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This paper presents the anode front-end electronics structure and results of the preproduction and the mass production tests, including radiation resistance and reliability tests. The special set of test equipment, techniques, and corresponding software developed and used in the test procedures are also described

Radiation hardness on very front-end for SPD

International Nuclear Information System (INIS)

Cano, Xavier; Graciani, Ricardo; Gascon, David; Garrido, Lluis; Bota, Sebastia; Herms, Atila; Comerma, Albert; Riera, Jordi

2005-01-01

The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

CERN Document Server

Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

2015-01-01

front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

Design of readout electronics for a scintillating plate calorimeter

International Nuclear Information System (INIS)

Crawley, H.B.; Meyer, W.T.; Rosenberg, E.I.; Thomas, W.D.; Blair, R.E.; Buehring, A.; Dawson, J.; Hill, N.; Noland, R.; Petereit, E.; Price, L.E.; Proudfoot, J.; Spinka, H.; Talaga, R.; Trost, H.J.; Underwood, D.; Wickland, A.B.; Hurlbut, C.; Hagopian, V.; Johnson, K.; Imlay, R.; McNeil, R.; Metcalf, W.; Bolen, L.; Cremaldi, L.; Reidy, J.; Summers, D.; Fu, P.; Gabriel, T.; Handler, T.; Ficenec, J.R.; Lu, B.; Mo, L.; Piilonen, L.E.; Nunamaker, T.; Burke, M.; Hackworth, D.T.; Porter, T.F.; Ravas, R.J.; Scherbarth, D.; Swensrud, R.; Carlsmith, D.; Foudas, C.; Lackey, J.; Loveless, D.; Reeder, D.; Robb, P.; Smith, W.H.

1990-01-01

A scintillator calorimeter produces unique problems for the designer of readout electronics. On the one hand the narrow time structure of scintillator pulses, ∼10 nsec, is well matched to the rf structure of the SSC and gives hope of isolating information from individual beam crossings. On the other hand, the compensation mechanism and the need to broaden the pulse shape for use with analog signal sampling devices gives a somewhat wider time structure, ∼50-100 nsec. Furthermore the granularity of such a device implies that the full energy of an electromagnetic shower may be totally contained within one readout channel. If the resolution of the electronics is not to compromise the intrinsic resolution of the calorimeter, assumed to be σ/E ∼ 15%/√E + 1% (E in Gev), coverage of the full dynamic range (40,000:1) requires at least two 12-bit devices with 7 bits of overlap for a linear front-end electronics chain. The positioning of the electronics also is a critical issue. At luminosities of 10 33 cm -2 sec -1 , electronics placed on the calorimeter must withstand doses of at least 10 10 neutron/cm 2 and 2,000 Rad per year at 90 degree. In the past year, the scintillating calorimeter collaboration has begun studying these and related issues. Among the work reported below is: a study related to remote location of the calorimeter electronics, a comprehensive program to evaluate the properties of FADCs capable of operation at 60-80 MHz, design of a analog memory unit and development of a benchmark system to help evaluate components under development both within and outside the authors' collaboration

Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

CERN Document Server

Zhu, Junjie; The ATLAS collaboration

2017-01-01

The planned Phase-I and Phase-II upgrades of the LHC accelerator drastically impacts the ATLAS trigger and trigger rates. A replacement of the ATLAS innermost endcap muon station with a new small wheel (NSW) detector is planned for the second long shutdown period of 2019 - 2020. This upgrade will allow us to maintain a low pT threshold for single muon and excellent tracking capability even after the High-Luminosity LHC upgrade. The NSW detector will feature two new detector technologies, Resistive Micromegas and small-strip Thin Gap Chambers. Both detector technologies will provide trigger and tracking primitives. The total number of trigger and readout channels is about 2.4 millions, and the overall power consumption is expected to be about 75 kW. The electronics design will be implemented in some 8000 front-end boards including the design of four custom front-end ASICs capable to drive trigger and tracking primitives with high speed sterilizers to drive trigger candidates to the backend trigger processor sy...

The front-end chip of the SuperB SVT detector

International Nuclear Information System (INIS)

Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.

2013-01-01

The asymmetric e + e − collider SuperB is designed to deliver a high luminosity, greater than 10 36 cm −2 s −1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

International Nuclear Information System (INIS)

Belver, D.; Cabanelas, P.; Castro, E.; Diaz, J.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-01-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m 2 with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12 C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

Science.gov (United States)

Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

CERN Document Server

Caratelli, Alessandro; Jan Kaplon; Kloukinas, Konstantinos; Simone Scarfi

2017-01-01

The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\\sim$100\\,Gbps and reduces the output data flow from 1.3\\,Tbps to 30\\,Gbps per module while limiting the total power density to below 100\\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing mult...

End-Users, Front Ends and Librarians.

Science.gov (United States)

Bourne, Donna E.

1989-01-01

The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

An ASIC implementation of digital front-end electronics for a high resolution PET scanner

International Nuclear Information System (INIS)

Newport, D.F.; Young, J.W.

1993-01-01

AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

Dead Time in the LAr Calorimeter Front-End Readout

CERN Document Server

Gingrich, D M

2002-01-01

We present readout time, latency, buffering, and dead-time calculations for the switched capacitor array controllers of the LAr calorimeter. The dead time is compared with algorithms for the dead-time generation in the level-1 central trigger processor.

Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

International Nuclear Information System (INIS)

Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

2008-01-01

The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

A new wire chamber front-end system, based on the ASD-8 B chip

International Nuclear Information System (INIS)

Kruesemann, B.A.M.; Bassini, R.; Ellinghaus, F.; Frekers, D.; Hagemann, M.; Hannen, V.M.; Heynitz, H. von; Heyse, J.; Rakers, S.; Sohlbach, H.; Woertche, H.J.

1999-01-01

The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

Gravitational Reference Sensor Front-End Electronics Simulator for LISA

International Nuclear Information System (INIS)

Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; Zweifel, Peter; Giardini, Domenico; Ten Pierick, Jan

2017-01-01

At the ETH Zurich we are developing a modular simulator that provides a realistic simulation of the Front End Electronics (FEE) for LISA Gravitational Reference Sensor (GRS). It is based on the GRS FEE-simulator already implemented for LISA Pathfinder. It considers, in particular, the non-linearity and the critical details of hardware, such as the non-linear multiplicative noise caused by voltage reference instability, test mass charging and detailed actuation and sensing algorithms. We present the simulation modules, considering the above-mentioned features. Based on the ETH GRS FEE-simulator for LISA Pathfinder we aim to develop a modular simulator that provides a realistic simulation of GRS FEE for LISA. (paper)

Performances of the Front-End Electronics for the HADES RPC TOF wall on a {sup 12}C beam

Energy Technology Data Exchange (ETDEWEB)

Belver, D. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)], E-mail: danielbf@usc.es; Cabanelas, P.; Castro, E. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Diaz, J. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Garzon, J.A. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Gil, A. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. [Gesellschaft fuer Schwerionenforschung, GSI, 64291 Darmstadt (Germany); Zapata, M. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m{sup 2} with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a {sup 12}C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Towards new analog read-out electronics for the HADES drift chamber system

Energy Technology Data Exchange (ETDEWEB)

Wiebusch, Michael [Goethe-Universitaet, Frankfurt (Germany); Collaboration: HADES-Collaboration

2016-07-01

Track reconstruction in HADES is realized with 24 planar, low-mass drift chambers (MDC). About 27000 drift cells provide precise spatial information of track hit points together with energy loss information, serving for particle ID. In order to handle high rates and track densities required at the future SIS100 accelerator at FAIR, an upgrade of the MDC system is necessary, i.e. by receiving additional redundant layers of drift cells in front of the magnet. This involves new front-end electronics, as the original analog read-out ASIC (ASD8) is no longer in stock and cannot be produced due to its legacy silicon process. Employing new FEE would allow to further increase the sensitivity, e.g. providing additional valuable information for the analysis. This contribution presents a market analysis of alternative state-of-the-art technologies for the analog read-out of drift chambers. Test procedures to evaluate the suitability for the HADES MDCs are discussed and preliminary results are shown. Emphasis is put on the benefits and possible implementations of using two separate analog channels for reading out a sense wire, i.e. a fast amplifier with a discriminator for recording the arrival time of the signal pulse and a slow integrating amplifier with a time-over-threshold discriminator to measure the total charge of the pulse.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

Energy Technology Data Exchange (ETDEWEB)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

2015-07-15

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

AVME readout module for multichannel ASIC characterization

International Nuclear Information System (INIS)

Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

2004-01-01

Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

The CMS silicon strip tracker and its electronic readout

International Nuclear Information System (INIS)

Friedl, M.

2001-05-01

The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4 T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. The charge collection in silicon detectors was modeled, which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolution method of fast pulse shaping, electronic noise constraints and radiation effects. Moreover, extensive measurements on prototype components of the CMS Tracker and different versions of the APV chip in particular were performed. There was a significant contribution to the construction of several detector modules, characterized them in particle beam tests and quantified radiation induced effects on the APV chip and on silicon detectors. In addition, a prototype of the analog optical link and the analog performance of the back-end digitization unit were evaluated. The results are very encouraging, demonstrating the feasibility of the CMS Silicon Strip Tracker system and motivating progress towards the construction phase. (author)

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

International Nuclear Information System (INIS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-01-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

CERN Document Server

Guan, Liang; The ATLAS collaboration

2017-01-01

The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small strip Thin Gap Chambers will be used to provide both trigger and tracking primitives. Muon segments found at NSW will be combined with the segments found at the Big Wheel to determine the muon transverse momentum at the first-level trigger. A new trigger and readout system is developed for the NSW detector. The new system has about 2.4 million trigger and readout channels and about 8,000 Front-End boards. The large number of input channels, short time available to prepare and transmit data, harsh radiation environment, and low power consumption all impose great challenges on the design. We will discuss the overall electronics design and studies with various ASICs and high-speed circuit board prototypes.

ATLAS Tile Calorimeter Readout Electronics Upgrade Program for the High Luminosity LHC

CERN Document Server

Cerqueira, A S

2013-01-01

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The ATLAS upgrade program is divided in three phases: The Phase~0 occurs during 2013-2014, Phase~1 during 2018-1019 and finally Phase~2, which is foreseen for 2022-2023, whereafter the peak luminosity will reach 5-7 x 10$^{34}$ cm$^2$s$^{-1}$ (HL-LHC). The main TileCal upgrade is focused on the Phase~2 period. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. All new electronics must be able to cope with the increased radiation levels. An ambitious upgrade development program is pursued to study different electronics options. Three options are presently being investigated for the front-end electronic upgrade. The first option is an improved version of the present system built using comm...

A circuit design for front-end read-out electronics of beam homogeneity measurement

International Nuclear Information System (INIS)

She Qianshun; Su Hong; Xu Zhiguo; Ma Xiaoli; Hu Zhengguo; Mao Ruishi; Xu Hushan

2011-01-01

It introduces a circuit design of beam homogeneity measurement for heavy ion beam in the monitoring needs, which convert multichannel weak current from 10 pA to 100 nA of the output of parallel plate avalanche counter (PPAC) for large area with sensitive two-dimensional position to voltage signal from -2 V to -20 mV by current-voltage-converter (IVC) circuit which composed of T-feedback resistor networks, combined with data acquisition and processing system realized the beam homogeneity measurement in heavy ion tumor therapy of the Institute of Modern Physics. Experiments have shown that the circuit with speed and high precision. This circuit can be used for read-out of the beam for the Multiwire Proportional Chamber, Faraday Cup and other weak current sources. (authors)

Readout electronic for multichannel detectors

CERN Document Server

Kulibaba, V I; Naumov, S V

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

Readout electronic for multichannel detectors

International Nuclear Information System (INIS)

Kulibaba, V.I.; Maslov, N.I.; Naumov, S.V.

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc

Status report on front end electronics for the EUSO photon detector

International Nuclear Information System (INIS)

Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P.

2002-01-01

In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions

Status report on front end electronics for the EUSO photon detector

Energy Technology Data Exchange (ETDEWEB)

Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P

2002-12-01

In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

Energy Technology Data Exchange (ETDEWEB)

Rivetti, Angelo

2014-11-21

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

Pixel detector readout electronics with two-level discriminator scheme

International Nuclear Information System (INIS)

Pengg, F.

1998-01-01

In preparation for a silicon pixel detector with more than 3,000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog front end of the readout electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.8 microm process but compatible with the design rules of the radiation hard Honeywell 0.8 microm bulk process. Each cell contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 microm by 140 microm. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900 mV for a minimum ionizing particle (MIP, about 24,000 e - for a 300 microm thick Si-detector) with a return to baseline within 750 ns for a 1 MIP input signal. The full readout chain (without detector) shows an equivalent noise charge to 60e - r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22 ns at a separation of 1,500 e - , which is adequate for the 40 MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40fF coupling capacitance, is less than 3%. A single cell consumes 35 microW at 3.5 V supply voltage

Test system for the production of the Atlas Tile Calorimeter front-end electronics

International Nuclear Information System (INIS)

Calvet, David

2004-01-01

The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

A readout system for position sensitive measurements of X-ray using silicon strip detectors

CERN Document Server

Dabrowski, W; Grybos, P; Idzik, M; Kudlaty, J

2000-01-01

In this paper we describe the development of a readout system for X-ray measurements using silicon strip detectors. The limitation concerning the inherent spatial resolution of silicon strip detectors has been evaluated by Monte Carlo simulation and the results are discussed. The developed readout system is based on the binary readout architecture and consists of two ASICs: RX32 front-end chip comprising 32 channels of preamplifiers, shapers and discriminators, and COUNT32 counter chip comprising 32 20-bit asynchronous counters and the readout logic. This work focuses on the design and performance of the front-end chip. The RX32 chip has been optimised for a low detector capacitance, in the range of 1-3 pF, and high counting rate applications. It can be used with DC coupled detectors allowing the leakage current up to a few nA per strip. For the prototype chip manufactured in a CMOS process all basic parameters have been evaluated by electronic measurements. The noise below 140 el rms has been achieved for a ...

Chapter 9: Electronics

International Nuclear Information System (INIS)

Grupen, Claus; Shwartz, Boris A.

2006-01-01

Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques

Trigger and readout electronics for the Phase-I upgrade of the ATLAS forward muon spectrometer

CERN Document Server

Moschovakos, Paris; The ATLAS collaboration

2017-01-01

The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas and small strip Thin Gap Chambers conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger and tracking...

Trigger and Readout Electronics for the Phase-I Upgrade of the ATLAS Forward Muon Spectrometer

CERN Document Server

Moschovakos, Paris; The ATLAS collaboration

2017-01-01

The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger ...

FAIR: A new fast trigger and readout bus system

International Nuclear Information System (INIS)

Ordine, A.; Boiano, A.; Zaghi, A.

1998-01-01

FAIR (FAst Intercrate Readout) is a synchronous ECL bus system dedicated to readout. It is based on a new trigger and readout hardware level protocol and on a new control system that learns how to setup and control modules. The hardware protocol along with the data structure allow both readout and event building at the same time at the rate of 22 ns/longword (1.44 Gbit/s) without the need of CPUs. It performs trigger management and full pipelining by using a multilevel FIFO structure. FAIR provides for a multi-crate front-end environment and uses an embedded serial network to accomplish front-end control and setup. The data transfer measured performances and the control system are presented in some detail

A new readout control system for the LHCb upgrade at CERN

International Nuclear Information System (INIS)

Alessio, F; Jacobsson, R

2012-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and a first hardware implementation of a new fast Readout Control system for the LHCb upgrade, which will be entirely based on FPGAs and bi-directional links. We also outline the real-time implementations of the new Readout Control system, together with solutions on how to handle the synchronous distribution of timing and synchronous information to the complex upgraded LHCb readout architecture. One section will also be dedicated to the control and usage of the newly developed CERN GBT chipset to transmit fast and slow control commands to the upgraded LHCb Front-End electronics. At the end, we outline the plans for the deployment of the system in the global LHCb upgrade readout architecture.

Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

Science.gov (United States)

Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

2017-12-01

Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

NARCIS (Netherlands)

Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Plessl, C.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Zhang, J.

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

Energy Technology Data Exchange (ETDEWEB)

Adinolfi, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Bibby, J.H. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Brisbane, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Gibson, V. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Harnew, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Jones, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Libby, J. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom)]. E-mail: j.libby1@physics.ox.ac.uk; Powell, A. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Newby, C. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Rotolo, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Smale, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Somerville, L.; Sullivan, P.; Topp-Jorgensen, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Wotton, S. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Wyllie, K. [CERN, CH-1211, Geneva 23 (Switzerland)

2007-03-11

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests.

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

International Nuclear Information System (INIS)

Adinolfi, M.; Bibby, J.H.; Brisbane, S.; Gibson, V.; Harnew, N.; Jones, M.; Libby, J.; Powell, A.; Newby, C.; Rotolo, N.; Smale, N.; Somerville, L.; Sullivan, P.; Topp-Jorgensen, S.; Wotton, S.; Wyllie, K.

2007-01-01

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests

A radiation tolerance study of the ALICE TPC Readout Control Unit 2

CERN Document Server

Zhao, Chengxin; Balk, Helge; Alme, Johan

2017-11-17

ALICE is a general-purpose detector that is designed to study the physics of quark-gluon plasma. The Time Projection Chamber (TPC) is one of the major detectors of ALICE. The TPC electronics consists of 4356 Front-end cards (FECs), which are controlled by 216 Readout Control Units (RCU). Each RCU connects to between 18 and 25 FECs using a multi-drop bus. In LHC Run1, the Readout Control Unit 1 (RCU1) performed even better than specification. However, in Run2 the energy of colliding beams is increased from 8 TeV to 14 TeV (maximum value) and higher luminosity, which leads to larger event size and higher radiation load on the electronics. As a solution, the Readout Control Unit 2 (RCU2) is designed to provide faster readout speed and improved radiation tolerance with respect to the RCU1. The RCU2 is conceptually similar to the RCU1 and it reuses the existing infrastructure and readout architecture of the TPC electronics. However, the multi-drop bus is split into four branches from the two branches and the bandw...

The Study of Fault Location for Front-End Electronics System

International Nuclear Information System (INIS)

Zhang Fan; Wang Dong; Huang Guangming; Zhou Daicui

2009-01-01

Since some devices on the latest developed 250 ALICE/PHOS Front-end electronics (FEE) system cards had been partly or completely damaged during lead-free soldering. To alleviate the influence on the performance of FEE system and to locate fault related FPGA accurately, we should find a method for locating fault of FEE system based on the deep study of FPGA configuration scheme. It emphasized on the problems such as JTAG configuration of multi-devices, PS configuration based on EPC series configuration devices and auto re-configuration of FPGA. The result of the massive FEE system cards testing and repairing show that that location method can accurately and quickly target the fault point related FPGA on FEE system cards. (authors)

The Phase-2 Electronics Upgrade of the ATLAS Liquid Argon Calorimeter System

CERN Document Server

Vachon, Brigitte; The ATLAS collaboration

2018-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile- up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS liquid argon calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the front-end and back- end readout system is foreseen for the 182,468 readout channels. The new readout system will be based on a free-running architecture, where calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40 MHz to the back-end for further processing. Results from the design studies on the performance of the components of the readou...

Solid-State Photomultiplier with Integrated Front End Electronics

Science.gov (United States)

Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

2009-10-01

The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

Test and improvement of readout system based on APV25 chip for GEM detector

International Nuclear Information System (INIS)

Hu Shouyang; Jian Siyu; Zhou Jing; Shan Chao; Li Xinglong; Li Xia; Li Xiaomei; Zhou Yi

2014-01-01

Gas electron multiplier (GEM) is the most promising position sensitive gas detector. The new generation of readout electronics system includes APV25 front-end card, multi-purpose digitizer (MPD), VME controller and Linux-based acquisition software DAQ. The construction and preliminary test of this readout system were finished, and the ideal data with the system working frequency of 40 MHz and 20 MHz were obtained. The long time running test shows that the system has a very good time-stable ability. Through optimizing the software configuration and improving hardware quality, the noise level was reduced, and the signal noise ratio was improved. (authors)

An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

International Nuclear Information System (INIS)

Fiorini, C.; Porro, M.

2006-01-01

We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

Readout electronics for the SiPM tracking plane in the NEXT-1 prototype

International Nuclear Information System (INIS)

Herrero, V.; Toledo, J.; Català, J.M.; Esteve, R.; Gil, A.; Lorca, D.; Monzó, J.M.; Sanchis, F.; Verdugo, A.

2012-01-01

NEXT is a new experiment to search for neutrinoless double beta decay using a 100 kg radio-pure high-pressure gaseous xenon TPC with electroluminescence readout. A large-scale prototype with a SiPM tracking plane has been built. The primary electron paths can be reconstructed from time-resolved measurements of the light that arrives to the SiPM plane. Our approach is to measure how many photons have reached each SiPM sensor each microsecond with a gated integrator. We have designed and tested a 16-channel front-end board that includes the analog paths and a digital section. Each analog path consists of three different stages: a transimpedance amplifier, a gated integrator and an offset and gain control stage. Measurements show good linearity and the ability to detect single photoelectrons.

Readout electronics for the SiPM tracking plane in the NEXT-1 prototype

Energy Technology Data Exchange (ETDEWEB)

Herrero, V. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Toledo, J., E-mail: jtoledo@eln.upv.es [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Catala, J.M.; Esteve, R. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Gil, A.; Lorca, D. [Instituto de Fisica Corpuscular (CSIC-Universidad de Valencia), 46980 Valencia (Spain); Monzo, J.M.; Sanchis, F. [Instituto de Instrumentacion para Imagen Molecular I3M (Centro mixto CSIC-Universitat Politecnica de Valencia-CIEMAT), 46022 Valencia (Spain); Verdugo, A. [CIEMAT-Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas, Madrid (Spain)

2012-12-11

NEXT is a new experiment to search for neutrinoless double beta decay using a 100 kg radio-pure high-pressure gaseous xenon TPC with electroluminescence readout. A large-scale prototype with a SiPM tracking plane has been built. The primary electron paths can be reconstructed from time-resolved measurements of the light that arrives to the SiPM plane. Our approach is to measure how many photons have reached each SiPM sensor each microsecond with a gated integrator. We have designed and tested a 16-channel front-end board that includes the analog paths and a digital section. Each analog path consists of three different stages: a transimpedance amplifier, a gated integrator and an offset and gain control stage. Measurements show good linearity and the ability to detect single photoelectrons.

Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

International Nuclear Information System (INIS)

Sorokin, Iurii

2013-01-01

The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10 14 n eq /cm 2 (n eq -neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the amplitude response on

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

Science.gov (United States)

Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

2016-12-01

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

2016-01-01

The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

International Nuclear Information System (INIS)

Anderson, J.; Drake, G.; Ryu, S.; Bauer, K.; Guest, D.; Borga, A.; Boterenbrood, H.; Schreuder, F.; Chen, H.; Chen, K.; Lanni, F.; Dönszelmann, M.; Francis, D.; Gorini, B.; Joos, M.; Miotto, G. Lehmann; Levinson, L.; Narevicius, J.; Roich, A.; Vazquez, W. Panduro

2016-01-01

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

Characterization of EASIROC as front-end for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

International Nuclear Information System (INIS)

Impiombato, D.; Giarrusso, S.; Mineo, T.; Belluso, M.; Billotta, S.; Bonanno, G.; Catalano, O.; Grillo, A.; La Rosa, G.; Marano, D.; Sottile, G.

2013-01-01

The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (<1%). Our results show that it is suitable as front-end chip for the camera prototype, although, specific modifications are necessary to adopt the device in the final version of the telescope

The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

CERN Document Server

Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

2007-01-01

In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

Science.gov (United States)

Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

2012-12-01

PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

International Nuclear Information System (INIS)

Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

2012-01-01

PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

A low-power high dynamic range front-end ASIC for imaging calorimeters

CERN Document Server

Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

2002-01-01

High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

Detector and Front-end electronics for ALICE and STAR silicon strip layers

CERN Document Server

Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

1998-01-01

Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

Front-end electronics for high rate, position sensitive neutron detectors

CERN Document Server

Yu, B; Harder, J A; Hrisoho, A; Radeka, V; Smith, G C

2002-01-01

Advanced neutron detectors for experiments at new spallation sources will require greater counting rate capabilities than previously attainable. This necessitates careful design of both detector and readout electronics. As part of a new instrument for protein crystallography at LANSCE, we are constructing a detector whose concept was described previously (IEEE Trans. Nucl. Sci. NS-46 (1999) 1916). Here, we describe the signal processing circuit, which is well suited for sup 3 He detectors with a continuous interpolating readout. The circuit is based on standard charge preamplification, transmission of this signal over 20 meters or so, followed by sample and hold using a second order gated baseline restorer. This latter unit provides high rate capability without requiring pole-zero and tail cancellation circuits. There is also provision for gain-adjustment. The circuits are produced in surface mounted technology.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

CERN Document Server

Schreuder, Frans Philip; The ATLAS collaboration

2018-01-01

Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

The CBM Experiment at FAIR-New challenges for Front-End Electronics, Data Acquisition and Trigger Systems

International Nuclear Information System (INIS)

Mueller, Walter F J

2006-01-01

The 'Compressed Baryonic Matter' (CBM) experiment at the new 'Facility for Antiproton and Ion Research' (FAIR) in Darmstadt is designed to study the properties of highly compressed baryonic matter produced in nucleus-nucleus collisions in the 10 to 45 A GeV energy range. One of the key observables is hidden (J/ψ) and open (D 0 , D ± ) charm production. To achieve an adequate sensitivity extremely high interaction rates of up to 10 7 events/second are required, resulting in major technological challenges for the detectors, front-end electronics and data processing. The front-end electronics will be self-triggered, autonomously detect particle hits, and output hit parameter together with a precise absolute time-stamp. Several layers of feature extraction and event selection will reduce the primary data flow of about 1 TByte/sec to a level of 1 GByte/sec. This new architecture avoids many limitations of conventional DAQ/Trigger systems and is for example essential for open charm detection, which requires the reconstruction of displaced vertices, in a high-rate heavy ion environment

The Phase-2 electronics upgrade of the ATLAS liquid argon calorimeter system

Science.gov (United States)

Vachon, B.

2018-03-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS liquid argon calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the front-end and off-detector readout system is foreseen for the 182,468 readout channels. The new readout system will be based on a free-running architecture, where calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40 MHz to the off-detector electronics for further processing. Results from the design studies on the performance of the components of the readout system are presented, as well as the results of the tests of the first prototypes.

A new PCI card for readout in high energy physics experiments

CERN Document Server

Floris, M; Marras, D; Usai, G L; David, A

2004-01-01

Recently some high energy physics experiments started to adopt readout systems based on the PCI architecture. In this context a new PCI card that can be adapted to several readout schemes has been designed. The card contains a large 64 MB local buffer, programmable FPGA logic and a PLX PCI bridge. The solution to use a PCI bridge external to the programmable logic allows to greatly simplify projects at the level of the on-board local bus. The card is presently used as the basic readout unit of the NA60 experiment. In this context, coupling it to different mezzanine cards it is possible to create interfaces to VME/CAMAC modules or to custom front-end electronics as for the case of the silicon vertex detector. Moreover, it is used as a readout test system for the ALICE muon chambers. (10 refs).

Highly Integrated Mixed-Mode Electronics for the readout of Time Projection Chambers

CERN Document Server

França Santos, Hugo Miguel; Musa, Luciano

Time Projection Chambers (TPCs) are one of the most prevalent particle trackers for high-energy physics experiments. Future planed TPCs for the International Linear Collider (ILC) and the Compact Linear Collider (CLIC) entail very high spatial resolution in large gas volumes, but impose low material budget for the end caps of the TPC cylinder. This constraint is not accomplished with the state-of-the-art front-end electronics because of its unsuited relatively large mass and of its associated water cooling system. To reach the required material budget, highly compact and power efficient dedicated TPC front-end electronics should be developed. This project aims at re-designing the different electronic elements with significant improvements in terms of performance, power efficiency and versatility, and developing an integrated circuit that merges all components of the front-end electronics. This chip ambitions a large volume production at low unitary cost and its employment in multiple detectors. The design of ...

Front end electronics and first results of the ALICE V0 detector

Energy Technology Data Exchange (ETDEWEB)

Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

2011-01-21

This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

International Nuclear Information System (INIS)

Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

2013-01-01

New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

Search for Supersymmetric Top-Quark Partners Using Support Vector Machines and Upgrade of the Hadron Calorimeter Front-End Readout Control System at CMS

CERN Document Server

Sahin, Mehmet Ozgur; Schleper, Peter

2017-01-01

In this thesis a search for direct pair production of supersymmetric top-quark partners aswell as work on the upgrade of the front-end readout controller of the Hadron Calorimeter(HCAL) of the Compact Muon Solenoid (CMS) experiment are presented.The most appealing extension of the Standard Model (SM) is supersymmetry (SUSY), relating the integer spin (bosons) and half-integer spin elementary particles (fermions). Supersymmetric top-quark partners (t) around and below the TeV energy scale offer a solution to thehierarchy problem. Furthermore, R-parity conserving SUSY models propose a cold dark matter candidate in the form of stable lightest supersymmetric particles, e.g. lightest neutralinos(χ0 ).The analysis performed in this thesis is a search for top-squark pair production in a final state consisting of a single isolated lepton, jets, among which at least one is tagged asbottom-quark jet, and large missing transverse energy at the CMS experiment at the CERNLarge Hadron Collider (LHC) with 8 TeV center-of-...

The PAUCam readout electronics system

Science.gov (United States)

Jiménez, Jorge; Illa, José M.; Cardiel-Sas, Laia; de Vicente, Juan; Castilla, Javier; Casas, Ricard

2016-08-01

The PAUCam is an optical camera with a wide field of view of 1 deg x 1 deg and up to 46 narrow and broad band filters. The camera is already installed on the William Herschel Telescope (WHT) in the Canary Islands, Spain and successfully commissioned during the first period of 2015. The paper presents the main results from the readout electronics commissioning tests and include an overview of the whole readout electronics system, its configuration and current performance.

A readout buffer prototype for ATLAS high-level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2001-01-01

Readout buffers are critical components in the dataflow chain of the ATLAS trigger/data-acquisition system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several readout buffers are grouped to form a readout buffer complex that acts as a data server for the high-level trigger selection algorithms and for the final data-collection system. This paper describes a functional prototype of a readout buffer based on a custom-made PCI mezzanine card that is designed to accept input data at up to 160 MB /s, to store up to 8 MB of data, and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and complex programmable logic devices. We present the integration of several of these cards in a readout buffer complex. We measure various performance figures and discuss to which extent these can fulfil ATLAS needs. (5 refs).

Detector and front-end electronics of a fissile mass flow monitoring system

International Nuclear Information System (INIS)

Paulus, M.J.; Uckan, T.; Lenarduzzi, R.; Mullens, J.A.; Castleberry, K.N.; McMillan, D.E.; Mihalczo, J.T.

1997-01-01

A detector and front-end electronics unit with secure data transmission has been designed and implemented for a fissile mass flow monitoring system for fissile mass flow of gases and liquids in a pipe. The unit consists of 4 bismuth germanate (BGO) scintillation detectors, pulse-shaping and counting electronics, local temperature sensors, and on-board local area network nodes which locally acquire data and report to the master computer via a secure network link. The signal gain of the pulse-shaping circuitry and energy windows of the pulse-counting circuitry are periodicially self calibrated and self adjusted in situ using a characteristic line in the fissile material pulse height spectrum as a reference point to compensate for drift such as in the detector gain due to PM tube aging. The temperature- dependent signal amplitude variations due to the intrinsic temperature coefficients of the PM tube gain and BGO scintillation efficiency have been characterized and real-time gain corrections introduced. The detector and electronics design, measured intrinsic performance of the detectors and electronics, and the performance of the detector and electronics within the fissile mass flow monitoring system are described

Control software for the CBM readout chain

Energy Technology Data Exchange (ETDEWEB)

Loizeau, Pierre-Alain [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH (Germany)

2016-07-01

The Compressed Baryonic Matter (CBM) experiment, which will be built at FAIR, will use free-streaming readout electronics to acquire high-statistics data-sets of physics probes in fixed target heavy-ion collisions. Since no simple signatures suitable for a hardware trigger are available for most of them, reconstruction and selection of the interesting collisions will be done in software, in a computer farm called First Level Event Selector (FLES). The raw data coming from the detectors is pre-processed, pre-calibrated and aggregated in a FPGA based layer called Data Preprocessing Boards (DPB). IPbus will be used to communicate with the DPBs and through them with the elements of the readout chain closer to detectors. A slow control environment based on this software is developed by CBM to configure in an efficient way the DPBs as well as the Front-End Electronics and monitor their performances. This contribution presents the layout planned for the slow control software, its first implementation and corresponding test results.

Development of telescope readout system based on FELIX for testbeam experiments

CERN Document Server

Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

2017-01-01

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

Science.gov (United States)

Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

2015-08-01

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Microstrip electrode readout noise for load-dominated long shaping-time systems

International Nuclear Information System (INIS)

Collier, Kelsey; Cunnington, Taylor; Crosby, Sean; Fadeyev, Vitaliy; Martinez-McKinney, Forest; Mistry, Khilesh; Schumm, Bruce A.; Spencer, Edwin; Taylor, Aaron; Wilder, Max

2013-01-01

In cases such as that of the proposed International Linear Collider (ILC), for which the beam-delivery and detector-occupancy characteristics permit a long shaping-time readout of the microstrip sensors, it is possible to envision long (∼1 meter) daisy-chained ‘ladders’ of fine-pitch sensors read out by a single front-end amplifier. In this study, a long shaping-time (∼2μsec) front-end amplifier has been used to measure readout noise as a function of detector load. Comparing measured noise to that expected from lumped and distributed models of the load network, it is seen that network effects significantly mitigate the amount of readout noise contributed by the detector load. Further reduction in noise is demonstrated for the case that the sensor load is read out from its center rather than its end

Microstrip electrode readout noise for load-dominated long shaping-time systems

Energy Technology Data Exchange (ETDEWEB)

Collier, Kelsey; Cunnington, Taylor; Crosby, Sean; Fadeyev, Vitaliy; Martinez-McKinney, Forest; Mistry, Khilesh; Schumm, Bruce A., E-mail: baschumm@ucsc.edu; Spencer, Edwin; Taylor, Aaron; Wilder, Max

2013-11-21

In cases such as that of the proposed International Linear Collider (ILC), for which the beam-delivery and detector-occupancy characteristics permit a long shaping-time readout of the microstrip sensors, it is possible to envision long (∼1 meter) daisy-chained ‘ladders’ of fine-pitch sensors read out by a single front-end amplifier. In this study, a long shaping-time (∼2μsec) front-end amplifier has been used to measure readout noise as a function of detector load. Comparing measured noise to that expected from lumped and distributed models of the load network, it is seen that network effects significantly mitigate the amount of readout noise contributed by the detector load. Further reduction in noise is demonstrated for the case that the sensor load is read out from its center rather than its end.

FATALIC: a fully integrated electronics readout for the ATLAS tile calorimeter at the HL-LHC

CERN Document Server

Angelidakis, Stylianos; The ATLAS collaboration

2018-01-01

The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. The current readout electronics of every sub-detector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the extreme HL-LHC operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfill these requirements. FATALIC is based on a $130\\,$nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization on a large dynamic range from $25\\,$fC to $1.2\\,$nC. The overall architecture of this current-reading ASIC is composed by current conveyors, shapers, 12-bits pipeline analog-to-digital converters operating at $40\\,$Mhz and a digital block dealing with the three gains implemented in this electronics. A dedicated channel for low current is also designed in order to be able to perform absolute calibration with radioactive cesium so...

The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

CERN Document Server

Cadeddu, S; Lai, A

2004-01-01

We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

International Nuclear Information System (INIS)

Fabbri, A; Notaristefani, F De; Galasso, M; Cencelli, V Orsolini; Falco, M D; Marinelli, M; Tortora, L; Verona, C; Rinati, G Verona

2013-01-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ''Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

Energy Technology Data Exchange (ETDEWEB)

Sorokin, Iurii

2013-07-01

The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

A read-out buffer prototype for ATLAS high level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2000-01-01

Read-Out Buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several Read-Out Buffers are grouped to form a Read-Out Buffer Complex that acts as a data server for the High Level Triggers selection algorithms and for the final data collection system. This paper describes a functional prototype of a Read-Out Buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel I960 processor and CPLDs. We present the integration of several of these cards in a Read-Out Buffer Complex. We measure various performance figures and we discuss to which extent these can fulfill ATLAS needs. 5 Refs.

The Phase-2 Electronics Upgrade of the ATLAS Liquid Argon Calorimeter System

CERN Document Server

Vachon, Brigitte; The ATLAS collaboration

2018-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the LAr front-end and back-end readout system is foreseen for the 182,500 readout channels. The system will follow a free-running architecture, where the calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40MHz to the backend, which performs the energy and time reconstruction, send inputs to the trigger, and buffers the data until trigge...

TDC for the front end architecture in the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

International Nuclear Information System (INIS)

R. SHURTER; ET AL

2000-01-01

Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design

The Front-End Electronics for the HADES RPC Wall (ESTRELA-FEE)

International Nuclear Information System (INIS)

Belver, D.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Lange, S.; Marin, J.; Montes, N.; Skott, P.; Traxler, M.; Zapata, M.

2006-01-01

A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m 2 with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most

MUON POLARIZATION EFFECTS IN THE FRONT END OF THE NEUTRINO FACTORY

International Nuclear Information System (INIS)

FERNOW, R.C.; GALLARDO, J.C.; FUKUI, Y.

2000-01-01

The authors summarize the methods used for simulation of polarization effects in the front end of a possible neutrino factory. They first discuss the helicity of muons in the pion decay process. They find that, neglecting acceptance considerations, the average helicity asymptotically approaches a magnitude of 0.185 at large pion momenta. Next they describe the methods used for tracking the spin through the complicated electromagnetic field configurations in the front end of the neutrino factory, including rf phase rotation and ionization cooling channels. Various depolarizing effects in matter are then considered, including multiple Coulomb scattering and elastic scattering from atomic electrons. Finally, they include all these effects in a simulation of a 480 m long, double phase rotation front end scenario

A real-time data transmission method based on Linux for physical experimental readout systems

International Nuclear Information System (INIS)

Cao Ping; Song Kezhu; Yang Junfeng

2012-01-01

In a typical physical experimental instrument, such as a fusion or particle physical application, the readout system generally implements an interface between the data acquisition (DAQ) system and the front-end electronics (FEE). The key task of a readout system is to read, pack, and forward the data from the FEE to the back-end data concentration center in real time. To guarantee real-time performance, the VxWorks operating system (OS) is widely used in readout systems. However, VxWorks is not an open-source OS, which gives it has many disadvantages. With the development of multi-core processor and new scheduling algorithm, Linux OS exhibits performance in real-time applications similar to that of VxWorks. It has been successfully used even for some hard real-time systems. Discussions and evaluations of real-time Linux solutions for a possible replacement of VxWorks arise naturally. In this paper, a real-time transmission method based on Linux is introduced. To reduce the number of transfer cycles for large amounts of data, a large block of contiguous memory buffer for DMA transfer is allocated by modifying the Linux Kernel (version 2.6) source code slightly. To increase the throughput for network transmission, the user software is designed into formation of parallelism. To achieve high performance in real-time data transfer from hardware to software, mapping techniques must be used to avoid unnecessary data copying. A simplified readout system is implemented with 4 readout modules in a PXI crate. This system can support up to 48 MB/s data throughput from the front-end hardware to the back-end concentration center through a Gigabit Ethernet connection. There are no restrictions on the use of this method, hardware or software, which means that it can be easily migrated to other interrupt related applications.

Monitoring the CMS strip tracker readout system

International Nuclear Information System (INIS)

Mersi, S; Bainbridge, R; Cripps, N; Fulcher, J; Wingham, M; Baulieu, G; Bel, S; Delaere, C; Drouhin, F; Mirabito, L; Cole, J; Giassi, A; Gross, L; Hahn, K; Nikolic, M; Tkaczyk, S

2008-01-01

The CMS Silicon Strip Tracker at the LHC comprises a sensitive area of approximately 200 m 2 and 10 million readout channels. Its data acquisition system is based around a custom analogue front-end chip. Both the control and the readout of the front-end electronics are performed by off-detector VME boards in the counting room, which digitise the raw event data and perform zero-suppression and formatting. The data acquisition system uses the CMS online software framework to configure, control and monitor the hardware components and steer the data acquisition. The first data analysis is performed online within the official CMS reconstruction framework, which provides many services, such as distributed analysis, access to geometry and conditions data, and a Data Quality Monitoring tool based on the online physics reconstruction. The data acquisition monitoring of the Strip Tracker uses both the data acquisition and the reconstruction software frameworks in order to provide real-time feedback to shifters on the operational state of the detector, archiving for later analysis and possibly trigger automatic recovery actions in case of errors. Here we review the proposed architecture of the monitoring system and we describe its software components, which are already in place, the various monitoring streams available, and our experiences of operating and monitoring a large-scale system

MMIC front-ends for optical communication systems

DEFF Research Database (Denmark)

Petersen, Anders Kongstad

1993-01-01

Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

Energy Technology Data Exchange (ETDEWEB)

DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

2007-10-27

We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

Implementation of the Timepix ASIC in the Scalable Readout System

Energy Technology Data Exchange (ETDEWEB)

Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

2016-09-11

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

Actuation stability test of the LISA pathfinder inertial sensor front-end electronics

Science.gov (United States)

Mance, Davor; Gan, Li; Weber, Bill; Weber, Franz; Zweifel, Peter

In order to limit the residual stray forces on the inertial sensor test mass in LISA pathfinder, √ it is required that the fluctuation of the test mass actuation voltage is within 2ppm/ Hz. The actuation voltage stability test on the flight hardware of the inertial sensor front-end electronics (IS FEE) is presented in this paper. This test is completed during the inertial sensor integration at EADS Astrium Friedrichshafen, Germany. The standard measurement method using voltmeter is not sufficient for verification, since the instrument low frequency √ fluctuation is higher than the 2ppm/ Hz requirement. In this test, by using the differential measurement method and the lock-in amplifier, the actuation stability performance is verified and the quality of the IS FEE hardware is confirmed by the test results.

Muon front end for the neutrino factory

CERN Document Server

Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

2013-01-01

In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

A radiation-tolerant electronic readout system for portal imaging

Science.gov (United States)

Östling, J.; Brahme, A.; Danielsson, M.; Iacobaeus, C.; Peskov, V.

2004-06-01

A new electronic portal imaging device, EPID, is under development at the Karolinska Institutet and the Royal Institute of Technology. Due to considerable demands on radiation tolerance in the radiotherapy environment, a dedicated electronic readout system has been designed. The most interesting aspect of the readout system is that it allows to read out ˜1000 pixels in parallel, with all electronics placed outside the radiation beam—making the detector more radiation resistant. In this work we are presenting the function of a small prototype (6×100 pixels) of the electronic readout board that has been tested. Tests were made with continuous X-rays (10-60 keV) and with α particles. The results show that, without using an optimised gas mixture and with an early prototype only, the electronic readout system still works very well.

Muon front end for the neutrino factory

Directory of Open Access Journals (Sweden)

C. T. Rogers

2013-04-01

Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

International Nuclear Information System (INIS)

Manazza, A.; Gaioni, L.; Re, V.

2011-01-01

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end.

Feedback from operational experience in front-end transportation

International Nuclear Information System (INIS)

Mondonel, J.L.; Parison, C.

1998-01-01

Transport forms an integral part of the nuclear fuel cycle, representing the strategic link between each stage of the cycle. In a way there is a transport cycle that parallels the nuclear fuel cycle. This concerns particularly the front-end of the cycle whose steps - mining conversion, enrichment and fuel fabrication - require numerous transports. Back-end shipments involve a handful of countries, but front-end transports involve all five continents, and many exotic countries. All over Europe such transports are routinely performed with an excellent safety track record. Transnucleaire dominates the French nuclear transportation market and carries out both front and back-end transports. For instance in 1996 more than 28,400 front-end packages were transported as well as more than 3,600 back-end packages. However front-end transport is now a business undergoing much change. A nuclear transportation company must now cope with an evolving picture including new technical requirements, new transportation schemes and new business conditions. This paper describes the latest evolutions in terms of front-end transportation and the way this activity is carried out by Transnucleaire, and goes on to discuss future prospects. (authors)

Rutherford X-ray spectrometer readout

International Nuclear Information System (INIS)

Bateman, J.E.

1978-07-01

Rutherford electronic X-ray spectrometer readout is based on the combination of two established techniques (a) the detection and location of soft X-rays by means of multichannel electron multiplier arrays (MCP's), and (b) the electronic readout of charge distributions (generally in multi-wire proportional counters) by means of the delay line techniques. In order for the latter device to function well a charge signal of approximately 10 6 electrons must be available to the delay line wand. This is achieved in the present device by means of two cascaded MCP's which can produce electron gains up to approximately 10 8 , and so operate the delay line from the single electron pulses generated at the front face of an MCP by a soft X-ray. The delay line readout technique was chosen because of its simplicity (both in terms of the necessary hardware and the associated electronics), robustness, and ease of implementation. In order to achieve the target spatial resolution of 50 μm (fwhm) or 20 μm (standard deviation) it was necessary to adapt the charge collection system so that the readout takes place from a length of delay line 200 mm long. The general layout of the system and the functions of the electronic circuits are described. Performance testing, setting up procedures and trouble shooting of the system are discussed. (U.K.)

Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

Czech Academy of Sciences Publication Activity Database

Campabadal, F.; Fleta, C.; Key, M.; Böhm, Jan; Mikeštíková, Marcela; Šťastný, Jan

2005-01-01

Roč. 552, - (2005), s. 292-328 ISSN 0168-9002 R&D Projects: GA MŠk 1P04LA212 Institutional research plan: CEZ:AV0Z10100502 Keywords : front-end electronics * binary readout * silicon strip detectors * application specific integrated circuits * quality assurance Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.224, year: 2005

Considerations on the design of front-end electronics for silicon calorimetry for the SSC

International Nuclear Information System (INIS)

Wintenberg, A.L.; Bauer, M.L.; Britton, C.L.; Kennedy, E.J.; Todd, R.A.; Berridge, S.C.; Bugg, W.M.

1990-01-01

Some considerations are described for the design of a silicon-based sampling calorimetry detector for the Superconducting Super Collider (SSC). The use of silicon as the detection medium allows fast, accurate, and fine-grained energy measurements - but for optimal performance, the front-end electronics must be matched to the detector characteristics and have the speed required by the high SSC interaction rates. The relation between the signal-to-noise rtio of the calorimeter electronics and the charge collection time, the preamplifier power dissipation, detector capacitance and leakage, charge gain, and signal shaping and sampling was studied. The electrostatic transformer connection was analyzed and found to be unusable for a tightly arranged calorimeter because of stray capacitance effects. The method of deconvolutional sampling was developed as a means for pileup correction following synchronous sampling and analog storage

Performance of the front-end electronics of the ANTARES neutrino telescope

NARCIS (Netherlands)

Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

2010-01-01

ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube

The ALICE silicon pixel detector front-end and read-out electronics

CERN Document Server

Kluge, A

2006-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost barrel layers of the ALICE inner tracker system. The SPD includes 120 half staves each of which consists of a linear array of 10 ALICE pixel chips bump bonded to two silicon sensors. Each pixel chip contains 8192 active cells, so the total number of pixel cells in the SPD is ≈107. The tight material budget and the limitation in physical dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. An essential part of the half stave is a low-mass multi-layer flex that carries power, ground, and signals to the pixel chips. Each half stave is read out using a multi-chip module (MCM). The MCM contains three radiation hard ASICs and an 800 Mbit/s custom developed optical link for the data transfer between the detector and the control room. The detector components are less than 3 mm thick. The production of the half-staves and MCMs is currently under way. Test results as well as on overvie...

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

International Nuclear Information System (INIS)

Havranek, Miroslav

2014-09-01

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Havranek, Miroslav

2014-09-15

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

Science.gov (United States)

Noy, M.; Aglieri Rinella, G.; Ceccucci, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Mazza, G.; Martoiu, S.; Morel, M.; Perktold, L.; Rivetti, A.; Tiuraniemi, S.

2011-06-01

The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16 cm active area made of an assembly of 10 readout ASICs bump bonded to a 200 μm thick pixel silicon sensor, comprising 18000 pixels of 300 μm×300 μm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5 Mhit s mm together with an extreme time resolution of 100 ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4 ns, with a planar silicon sensor operating up to 300 V over depletion. Moreover, the radiation level is severe, 2×10 1 MeV n cm per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130 nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

CERN Document Server

Drake, Gary; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

Redesigned front end for the upgrade at CHESS

International Nuclear Information System (INIS)

Headrick, R.L.; Smolenski, K.W.

1996-01-01

We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

FASTBUS readout system for the CDF DAQ upgrade

International Nuclear Information System (INIS)

Andresen, J.; Areti, H.; Black, D.

1993-11-01

The Data Acquisition System (DAQ) at the Collider Detector at Fermilab is currently being upgraded to handle a minimum of 100 events/sec for an aggregate bandwidth that is at least 25 Mbytes/sec. The DAQ System is based on a commercial switching network that has interfaces to VME bus. The modules that readout the front end crates (FASTBUS and RABBIT) have to deliver the data to the VME bus based host adapters of the switch. This paper describes a readout system that has the required bandwidth while keeping the experiment dead time due to the readout to a minimum

FATALIC: a fully integrated electronics readout for the ATLAS tile calorimeter at the HL-LHC

CERN Document Server

Angelidakis, Stylianos; The ATLAS collaboration

2018-01-01

The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. The current readout electronics of every sub-detector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the extreme HL-LHC operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfill these requirements. FATALIC is based on a $130\\,$nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization on a large dynamic range A dedicated channel for low current is also designed in order to perform absolute calibration with radioactive cesium source, producing a known but low signal with a typical frequency of $100\\,$Hz. In this document, the design of FATALIC is described and the measured performances as well as results of tests using beam of particles at CERN are discussed.

A test system for electronics components of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Lai, Alessandra; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich (Germany); Collaboration: PANDA-Collaboration

2016-07-01

The PANDA experiment is one of the main devices at the upcoming Facility for Antiproton and Ion Research(FAIR), under construction in Darmstadt, Germany. This fixed target experiment will study the transition region between perturbative and non-perturbative QCD in the energy regime of the charmonium. The innermost sub-detector system of the target spectrometer of the PANDA experiment is the Micro Vertex Detector(MVD). Two types of silicon detectors will be used: pixel detectors and double-sided strip detectors. Two front-end chips are required: the Torino Pixel ASIC(ToPix) and the PANDA Strip ASIC(PASTA). Both are designed to transmit data at a rate of several hundred Megabits per second and are capable of handling the expected hit rate in hot spots of the detector. One key component in the development of new front-end electronics is a test system capable to handle these high rates. It should be flexible enough to test different kinds of front-end electronics and it should be easy to adapt to new prototypes. Therefore, an FPGA-based system is the ideal candidate. For this test system suitable firmware and a software framework are needed. Such a system is under development at the Forschungszentrum Juelich. The main component of the Juelich Digital Readout System(JDRS) is a Virtex 6 FPGA on a development board from Xilinx. In this talk, the mentioned read-out system are introduced, and lab tests with the front-end electronics of the MVD are presented.

Adaptive RF front-ends for hand-held applications

CERN Document Server

van Bezooijen, Andre; van Roermund, Arthur

2010-01-01

The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

Functional tests of 2S modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-based readout system

CERN Document Server

Preuten, Marius; Klein, Katja; Lipinski, Martin; Rauch, Max; Feld, Lutz

2017-01-01

First full size 2S module prototypes for the CMS Phase-2 Outer Tracker Upgrade have been assembled. With two sensors of realistic dimensions and 16 CBC2 readout ASICs on two front-end hybrids, the characteristics of these novel and complex objects can be studied.A MicroTCA based readout system was developed to test multiple front-end hybrids simultaneously. Therefore the concurrent information of the full module can be used for noise and signal studies.

Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

CERN Document Server

Drake, G; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

Front-End ASICs for 3-D Ultrasound : From Beamforming to Digitization

NARCIS (Netherlands)

Chen, C.

2018-01-01

This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as

Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

Science.gov (United States)

Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

2011-02-01

This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

Design and construction of the front-end electronics data acquisition for the SLD CRID [Cherenkov Ring Imaging Detector

International Nuclear Information System (INIS)

Hoeflich, J.; McShurley, D.; Marshall, D.; Oxoby, G.; Shapiro, S.; Stiles, P.; Spencer, E.

1990-10-01

We describe the front-end electronics for the Cherenkov Ring Imaging Detector (CRID) of the SLD at the Stanford Linear Accelerator Center. The design philosophy and implementation are discussed with emphasis on the low-noise hybrid amplifiers, signal processing and data acquisition electronics. The system receives signals from a highly efficient single-photo electron detector. These signals are shaped and amplified before being stored in an analog memory and processed by a digitizing system. The data from several ADCs are multiplexed and transmitted via fiber optics to the SLD FASTBUS system. We highlight the technologies used, as well as the space, power dissipation, and environmental constraints imposed on the system. 16 refs., 10 figs

Investigation of a Huffman-based compression algorithm for the ALICE TPC read-out in LHC Run 3

Energy Technology Data Exchange (ETDEWEB)

Klewin, Sebastian [Physikalisches Institut, University of Heidelberg (Germany); Collaboration: ALICE-Collaboration

2016-07-01

Within the scope of the ALICE upgrade towards the Run 3 of the Large Hadron Collider at CERN, starting in 2020, the ALICE Time Projection Chamber (TPC) will be reworked in order to allow for a continuous read-out. This rework includes not only a replacement of the current read-out chambers with Gas Electron Multiplier (GEM) technology, but also new front-end electronics. To be able to read out the whole data stream without loosing information, in particular without zero-suppression, a lossless compression algorithm, the Huffman encoding, was investigated and adapted to the needs of the TPC. In this talk, an algorithm, adapted for an FPGA implementation, is presented. We show its capability to reduce the data volume to less than 40% of its original size.

Optimization of the ATLAS (s)MDT readout electronics for high counting rates

Energy Technology Data Exchange (ETDEWEB)

Kortner, Oliver; Kroha, Hubert; Nowak, Sebastian; Schmidt-Sommerfeld, Korbinian [Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut), Foehringer Ring 6, 80805 Muenchen (Germany)

2016-07-01

In the ATLAS muon spectrometer, Monitored Drift Tube (MDT) chambers are used for precise muon track measurement. For the high background rates expected at HL-LHC, which are mainly due to neutrons and photons produced by interactions of the proton collision products in the detector and shielding, new small-diameter muon drift tube (sMDT)-chambers with half the drift tube diameter of the MDT-chambers and ten times higher rate capability have been developed. The standard MDT readout electronics uses bipolar shaping in front of a discriminator. This shaping leads to an undershoot of same charge but opposite polarity following each pulse. With count rates also the probability of having the subsequent pulse in this undershoot increases, which leads to losses in efficiency and spatial resolution. In order to decrease this effect, discrete prototype electronics including Baseline Restoration has been developed. Results of their tests and data taken with them during muon beamtime measurements at CERN's Gamma Irradiation Facility will be presented. which causes a deterioration of signal pulses by preceding background hits, leading to losses in muon efficiency and drift tube spatial resolution. In order to mitigate these so-called signal pile-up effects, new readout electronics with active baseline restoration (BLR) is under development. Discrete prototype electronics with BLR functionality has been tested in laboratory measurements and in the Gamma Irradiation Facility at CERN under high γ-irradiation rates. Results of the measurements are presented.

A reconfigurable image tube using an external electronic image readout

Science.gov (United States)

Lapington, J. S.; Howorth, J. R.; Milnes, J. S.

2005-08-01

We have designed and built a sealed tube microchannel plate (MCP) intensifier for optical/NUV photon counting applications suitable for 18, 25 and 40 mm diameter formats. The intensifier uses an electronic image readout to provide direct conversion of event position into electronic signals, without the drawbacks associated with phosphor screens and subsequent optical detection. The Image Charge technique is used to remove the readout from the intensifier vacuum enclosure, obviating the requirement for additional electrical vacuum feedthroughs and for the readout pattern to be UHV compatible. The charge signal from an MCP intensifier is capacitively coupled via a thin dielectric vacuum window to the electronic image readout, which is external to the sealed intensifier tube. The readout pattern is a separate item held in proximity to the dielectric window and can be easily detached, making the system easily reconfigurable. Since the readout pattern detects induced charge and is external to the tube, it can be constructed as a multilayer, eliminating the requirement for narrow insulator gaps and allowing it to be constructed using standard PCB manufacturing tolerances. We describe two readout patterns, the tetra wedge anode (TWA), an optimized 4 electrode device similar to the wedge and strip anode (WSA) but with a factor 2 improvement in resolution, and an 8 channel high speed 50 ohm device, both manufactured as multilayer PCBs. We present results of the detector imaging performance, image resolution, linearity and stability, and discuss the development of an integrated readout and electronics device based on these designs.

A new avalanche photo diode based readout for the crystal barrel calorimeter

Energy Technology Data Exchange (ETDEWEB)

Urban, Martin [Helmholtz-Institut fuer Strahlen- und Kernphysik, Nussallee 14-16, 53115 Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

2015-07-01

The CBELSA/TAPS experiment at ELSA has proven successful in the measurement of double polarization observables in meson photoproduction off protons and neutrons. To be able to measure purely neutral reactions on a polarized neutron target with high efficiency, the main calorimeter consisting of 1320 CsI(Tl) crystals has to be integrated into the first level trigger. Key requirement to achieve this goal is an exchange of the existing PIN photo diode by a new avalanche photo diode (APD) readout. The main advantage of the new readout system is that it will provide timing information which allows a fast trigger signal. The energy resolution will remain compatible to the previous system. Besides the development of automated test routines for the front end electronics, the characterization of all APDs was successfully accomplished in Bonn. After tests with a 3 x 3 CsI(Tl) crystal matrix at the tagged photon beam facilities at ELSA and MAMI the first half of the Crystal Barrel was upgraded in 2014. This talk shows the result of the latest test measurements including the gain stabilization of the new APD readout electronics and presents the progress of the ongoing upgrade.

Managing Controversies in the Fuzzy Front End

DEFF Research Database (Denmark)

Christiansen, John K.; Gasparin, Marta

2016-01-01

This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

Front-End Electronics for Verification Measurements: Performance Evaluation and Viability of Advanced Tamper Indicating Measures

International Nuclear Information System (INIS)

Smith, E.; Conrad, R.; Morris, S.; Ramuhalli, P.; Sheen, D.; Schanfein, M.; Ianakiev, K.; Browne, M.; Svoboda, J.

2015-01-01

The International Atomic Energy Agency (IAEA) continues to expand its use of unattended, remotely monitored measurement systems. An increasing number of systems and an expanding family of instruments create challenges in terms of deployment efficiency and the implementation of data authentication measures. A collaboration between Pacific Northwest National Laboratory (PNNL), Idaho National Laboratory (INL), and Los Alamos National Laboratory (LANL) is working to advance the IAEA's capabilities in these areas. The first objective of the project is to perform a comprehensive evaluation of a prototype front-end electronics package, as specified by the IAEA and procured from a commercial vendor. This evaluation begins with an assessment against the IAEA's original technical specifications and expands to consider the strengths and limitations over a broad range of important parameters that include: sensor types, cable types, and the spectrum of industrial electromagnetic noise that can degrade signals from remotely located detectors. A second objective of the collaboration is to explore advanced tamper-indicating (TI) measures that could help to address some of the long-standing data authentication challenges with IAEA's unattended systems. The collaboration has defined high-priority tampering scenarios to consider (e.g., replacement of sensor, intrusion into cable), and drafted preliminary requirements for advanced TI measures. The collaborators are performing independent TI investigations of different candidate approaches: active time-domain reflectometry (PNNL), passive noise analysis (INL), and pulse-by-pulse analysis and correction (LANL). The initial investigations focus on scenarios where new TI measures are retrofitted into existing IAEA UMS deployments; subsequent work will consider the integration of advanced TI methods into new IAEA UMS deployments where the detector is separated from the front-end electronics. In this paper, project progress

The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

International Nuclear Information System (INIS)

Dabrowski, M.; Aspell, P.; Bonacini, S.; Ciaglia, D.; Kloukinas, K.; Lentdecker, G. De; Robertis, G. De; Kupiainen, M.; Talvitie, J.; Tuuva, T.; Leroux, P.; Tavernier, F.

2015-01-01

This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

The readout system of the new H1 silicon detectors

International Nuclear Information System (INIS)

Buerger, J.; Hansen, K.; Lange, W.; Prell, S.; Zimmermann, W.; Henschel, H.; Haynes, W.J.; Noyes, G.W.; Joensson, L.; Gabathuler, K.; Horisberger, R.; Wagener, M.; Eichler, R.; Erdmann, W.; Niggli, H.; Pitzl, D.

1995-03-01

The H1 detector at HERA at DESY undergoes presently a major upgrade. In this context silicon strip detectors have been installed at beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 Silicon Detectors and performance data of the complete readout chain. (orig.)

Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

Science.gov (United States)

Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

2012-07-01

There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

Upgrading the ATLAS Tile Calorimeter electronics

CERN Document Server

Oreglia, M; The ATLAS collaboration

2013-01-01

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The main upgrade will occur for the High Luminosity LHC phase (phase 2) which is scheduled around 2022. The upgrade aims at replacing the majority of the on- and off- detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. An ambitious upgrade development program is pursued studying different electronics options. Three different options are presently being investigated for the front-end electronic upgrade. Which one to use will be decided after extensive test beam studies. High speed optical links are used to read out all digitized data to the counting room. For the off-detector electronics a new back-end architecture is being developed, including the initial trigger processing and pipeline memories. A demonstrator prototype read-out for a slice of the ...

Readout scheme for the Baby-MIND detector

CERN Document Server

Noah, Etam; Cadoux, F; Favre, Y; Martinez, B; Nicola, L; Parsa, S; Rayner, M; Antonova, M; Fedotov, S; Izmaylov, A; Kleymenova, A; Khabibullin, M; Khotyantsev, A; Kudenko, Y; Likhacheva, V; Mefodiev, A; Mineev, O; Ovsiannikova, T; Shaykhiev, A; Suvorov, S; Yershov, N; Tsenov, R

2016-01-01

A readout scheme has been designed for the plastic scintillator bars of the Baby-MIND detector modules. This spectrometer will measure momentum and identify the charge of 1 GeV/c muons with magnetized iron plates interleaved with detector modules. One challenge the detector aims to address is that of keeping high charge identification efficiencies for momenta below 1 GeV/c where multiple scattering in the iron plates degrades momentum resolution. A front-end board has been developed, with 3 CITIROC readout chips per board and up to 96 channels. Hamamatsu MPPCs type S12571-025C photosensors were chosen for readout of wavelength shifting fibers embedded in plastic scintillators. Procurement of the MPPCs has been carried out to instrument 3000 channels in total. Design choices and first results of this readout scheme are presented.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

Energy Technology Data Exchange (ETDEWEB)

Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

2016-11-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

International Nuclear Information System (INIS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

2016-01-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

CERN Document Server

Chen, Kai; The ATLAS collaboration

2016-01-01

The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

Concepts for a Muon Accelerator Front-End

Energy Technology Data Exchange (ETDEWEB)

Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

2017-03-16

We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

Upgraded readout electronics for the ATLAS LAr Calorimeter at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase [1] in 2018, new digital tower builder boards (sTBB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and identifies sig...

Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

CERN Document Server

Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

1997-01-01

We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

CERN Document Server

Lo Presti, D; Caponetto, L

2007-01-01

A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

An X-Ray facility to perform irradiation tests and TID studies on electronics and detectors

CERN Document Server

Brundu, Davide; Cadeddu, Sandro; Wyllie, Ken; Ciambrone, Paolo

2018-01-01

The X-Ray irradiation system of the LHCb group, installed in Cagliari, is presented; with a particular focus on the setup configuration and dose rate calibration. The system can be used to perform Total Ionizing Dose (TID) studies for detectors, readout and front-end electronics. It was already used to test the nSYNC chip, an ASIC for the readout of the LHCb upgraded muon system.

Upgrade of the ALICE muon trigger electronics

International Nuclear Information System (INIS)

Dupieux, P; Joly, B; Jouve, F; Manen, S; Vandaële, R

2014-01-01

The ALICE muon trigger is a large scale detector based on single gap bakelite RPCs. An upgrade of the electronics is needed in order to withstand the increase of luminosity after the LHC Long Shutdown-2 in 2018-2019. The detector will be read out at the minimum bias rate of 100 kHz in Pb–Pb collisions (including a safety factor of 2), two orders of magnitude above the present design. For the most exposed RPCs and in the present conditions of operation, the total integrated charge could be as high as 100 mC/cm 2 with rates up to 100 Hz/cm 2 , which is above the present limit for safe operation. In order to overcome these limitations, upgrade projects of the Front-End (FE) and Readout Electronics are scheduled. The readout upgrade at high rate with low dead time requires changing most of the present electronics. It involves a new design for the 234 Local cards receiving the LVDS signals from the FE electronics and the 16 Regional concentrator cards. The readout chain is completed by a single Common Readout Unit developed for most ALICE sub-detectors. The new architecture of the muon trigger readout will be briefly presented. The present FE electronics, designed for the streamer mode, must be replaced to prevent ageing of the RPCs in the future operating conditions. The new FE called FEERIC (for Front-End Electronics Rapid Integrated Circuit) will have to perform amplification of the analog input signals. This will allow for RPC operation in a low-gain avalanche mode, with a much smaller charge deposit (factor 3-5) in the detector as compared to the present conditions. The purpose is to discriminate RPC signals with a charge threshold around 100 fC, in both polarities, and with a time jitter below 1 ns. We will describe the FE card and FEERIC ASIC features and first prototype performance, report on test results obtained on a cosmic test bench and discuss ongoing developments

Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

CERN Document Server

Posch, C

2002-01-01

Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

RF front-end world class designs

CERN Document Server

Love, Janine

2009-01-01

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

CERN Document Server

Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

2013-01-01

The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

NECTAR: New electronics for the Cherenkov Telescope Array

Science.gov (United States)

Naumann, Christopher Lindsay; Bolmont, J.; Corona, P.; Delagnes, E.; Dzahini, D.; Feinstein, F.; Gascon, D.; Glicenstein, J.-F.; Nayman, P.; Rarbi, F.; Ribo, M.; Sanuy, A.; Siero, X.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The international CTA consortium is currently in the preparatory phase for the development of the next-generation Cherenkov Telescope Array (CTA [1]), based on the return of experience from the three major current-generation arrays H.E.S.S., MAGIC and VERITAS. To achieve an unprecedented sensitivity and energy range for TeV gamma rays, a new kind of flexible and powerful yet inexpensive front-end hardware will be required for the order of 105 channels of photodetectors in up to 100 telescopes. One possible solution is the NECTAr (New Electronics for the Cherenkov Telescope Array) system, based on the integration of as much as possible of the front-end electronics (amplifiers, fast analogue samplers, memory and ADCs) into a single ASIC for very fast readout performance and a significant reduction of the cost and the lower consumption per channel, while offering a high degree of flexibility both for the triggering and the readout of the telescope. The current status of its development is presented, along with newest results from measurements and simulation studies.

Effects of high-energy particle showers on the embedded front-end electronics of an electromagnetic calorimeter for a future lepton collider

CERN Document Server

Adloff, C.; Repond, J.; Smith, J.; Trojand, D.; Xia, L.; Baldolemar, E.; Li, J.; Park, S.T.; Sosebee, M.; White, A.P.; Yu, J.; Mikami, Y.; Watson, N.K.; Mavromanolakis, G.; Thomson, M.A.; Ward, D.R.; Yan, W.; Benchekroun, D.; Hoummada, A.; Khoulaki, Y.; Benyamna, M.; Carloganu, C.; Fehr, F.; Gay, P.; Manen, S.; Royer, L.; Blazey, G.C.; Dyshkant, A.; Zutshi, V.; Hostachy, J.Y.; Morin, L.; Cornett, U.; David, D.; Fabbri, R.; Falley, G.; Gadow, K.; Garutti, E.; Gottlicher, P.; Gunter, C.; Karstensen, S.; Krivan, F.; Lucaci-Timoce, A.I.; Lu, S.; Lutz, B.; Marchesini, I.; Meyer, N.; Morozov, S.; Morgunov, V.; Reinecke, M.; Sefkow, F.; Smirnov, P.; Terwort, M.; Vargas-Trevino, A.; Wattimena, N.; Wendt, O.; Feege, N.; Haller, J.; Richter, S.; Samson, J.; Eckert, P.; Kaplan, A.; Schultz-Coulon, H.Ch.; Shen, W.; Stamen, R.; Tadday, A.; Bilki, B.; Norbeck, E.; Onel, Y.; Kawagoe, K.; Uozumi, S.; Dauncey, P.D.; Magnan, A.M.; Bartsch, V.; Salvatore, F.; Laktineh, I.; Calvo Alamillo, E.; Fouz, M.C.; Puerta-Pelayo, J.; Frey, A.; Kiesling, C.; Simon, F.; Bonis, J.; Bouquet, B.; Callier, S.; Cornebise, P.; Doublet, Ph.; Dulucq, F.; Faucci Giannelli, M.; Fleury, J.; Li, H.; Martin-Chassard, G.; Richard, F.; de la Taille, Ch.; Poschl, R.; Raux, L.; Seguin-Moreau, N.; Wicek, F.; Anduze, M.; Boudry, V.; Brient, J.C.; Jeans, D.; Mora de Freitas, P.; Musat, G.; Reinhard, M.; Ruan, M.; Videau, H.; Marcisovsky, M.; Sicho, P.; Vrba, V.; Zalesak, J.; Belhorma, B.; Ghazlane, H.

2011-01-01

Application Specific Integrated Circuits, ASICs, similar to those envisaged for the readout electronics of the central calorimeters of detectors for a future lepton collider have been exposed to high-energy electromagnetic showers. A salient feature of these calorimeters is that the readout electronics will be embedded into the calorimeter layers. In this article it is shown that interactions of shower particles in the volume of the readout electronics do not alter the noise pattern of the ASICs. No signal at or above the MIP level has been observed during the exposure. The upper limit at the 95% confidence level on the frequency of faked signals is smaller than 1x10^{-5} for a noise threshold of about 60% of a MIP. For ASICs with similar design to those which were tested, it can thus be largely excluded that the embedding of the electronics into the calorimeter layers compromises the performance of the calorimeters.

Progress on the development of a detector mounted analog and digital readout system for the ATLAS TRT

CERN Document Server

Baxter, C; Dressnandt, N; Gay, C; Lundberg, B; Munar, A; Mayers, G; Newcomer, M; Van Berg, R; Williams, H H

2004-01-01

The 430,000 element ATLAS Transition Radiation straw tube Tracker (TRT) is divided into a central barrel tracker consisting of 104,000 axially mounted straws and two radially arranged end caps on either side of the barrel with 160,000 straws each. To achieve a track position resolution of 140 mu m, the front end electronics must operate at a low (2fC) threshold with a time marking capability of ~1ns. Two ASICs, the ASDBLR and DTMROC provide the complete pipelined readout chain. Custom designed FBGA packages for the ASICs provide a small enough outline to be detector mounted and the extensive use of low level differential signals make mounting the analog packages on printed circuit boards directly opposite the 40 MHz digital chips feasible. The readout electronics for the barrel occupies a potentially important part of the active tracker volume and an aggressive effort has been made to make it as compact as possible. Utilizing a single board for both analog and digital ASICS a 0.1 cm /sup 3/ per channel volume...

Indico front-end: From spaghetti to lasagna

CERN Multimedia

CERN. Geneva

2017-01-01

We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

The read-out electronics of the AMS prototype RICH detector

International Nuclear Information System (INIS)

Gallin-Martel, L.; Eraud, L.; Pouxe, J.; Aguayo de Hoyos, P.; Marin Munoz, J.; Martinez Botella, G.

2003-01-01

A Ring Imaging Cherenkov (RICH) counter dedicated to the AMS experiment is under development. An integrated circuit has been designed with the Austriamicrosystems 0.6 πm CMOS technology to process the signals of the 16 anode PMTs used in the photon detection. To improve the detector compactness, the read out electronics is placed very close to the PMTs. This lead to the design of a detection cell that comprises: a light guide, a PMT, a high voltage divider, an analog front end chip and an analog to digital converter. The analog front-end chips were extensively and successfully tested in a laboratory environment, 96 of them are now mounted on the RICH prototype. Tests with cosmic rays have started. Ion beam tests are planed in a near future. (authors)

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

Science.gov (United States)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

OpenAIRE

Aliaga Varea, Ramón José; Herrero Bosch, Vicente; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo Pardo, C.; Gadea Gironés, Rafael; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

2015-01-01

The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz...

Idea management in support of pharmaceutical front end innovation

DEFF Research Database (Denmark)

Aagaard, Annabeth

2012-01-01

The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

CERN Multimedia

J.Coughlan

1998-01-01

The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

Design of the Front-End Detector Control System of the ATLAS New Small Wheels

CERN Document Server

Koulouris, Aimilianos; The ATLAS collaboration

2017-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

Upgraded Readout Electronics for the ATLAS Liquid Argon Calorimeters at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase cite{pahse1loi} in 2018, new LAr Trigger Digitizer Boards (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and id...

Upgrading the ATLAS Tile Calorimeter Electronics

CERN Document Server

Popeneciu, G; The ATLAS collaboration

2014-01-01

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at LHC. Around 2023, after the upgrade of the LHC (High Luminosity LHC, phase 2) the peak luminosity will increase by a factor of 5 compared to the design value (1034 cm-2 s-1), thus requiring an upgrade of the TileCal readout electronics. Except the 9852 photomultipliers (PMTs), most of the on- and off-detector electronics will be replaced, with the aim of digitizing all PMT pulses at 40 MHz at the front-end level and sending them with 10 Gbps optical links to the back-end electronics. Moreover, to increase reliability, redundancy will be introduced at different levels. Three different options are currently being investigated for the front-end electronics and extensive test beam studies are planned to select the best option. One demonstrator prototype module is also planned to be inserted in TileCal in 2014 that will include hybrid electronic components able to probe the new design, but still compatible with the presen...

FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

CERN Document Server

AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

2016-01-01

From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

Ultra-wideband wireless receiver front-end for high-speed indoor applications

Directory of Open Access Journals (Sweden)

Zhe-Yang Huang

2014-12-01

Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

Science.gov (United States)

Fossum, Eric R.

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Data readout system utilizing photonic integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

2013-10-11

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Development of readout electronics for monolithic integration with diode strip detectors

International Nuclear Information System (INIS)

Hosticka, B.J.; Wrede, M.; Zimmer, G.; Kemmer, J.; Hofmann, R.; Lutz, G.

1984-03-01

Parallel in - serial out analog readout electronics integrated with silicon strip detectors will bring a reduction of two orders of magnitude in external electronics. The readout concept and the chosen CMOS technology solve the basic problem of low noise and low power requirements. A hybrid solution is an intermediate step towards the final goal of monolithic integration of detector and electronics. (orig.)

Programmer's guide to FFE: a fast front-end data-acquisition program

International Nuclear Information System (INIS)

Million, D.L.

1983-05-01

The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Science.gov (United States)

Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

2016-07-01

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Energy Technology Data Exchange (ETDEWEB)

Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

2016-07-11

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

Align the Front End First.

Science.gov (United States)

Perry, Jim

1995-01-01

Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

Development and Implementation of Optimal Filtering in a Virtex FPGA for the Upgrade of the ATLAS LAr Calorimeter Readout

CERN Document Server

Stärz, S; The ATLAS collaboration

2012-01-01

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation in the high-luminosity phase of the LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming detector signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed; Ghazzai, Hakim; Kadri, Abdullah; Alouini, Mohamed-Slim

2016-01-01

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed

2016-06-14

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

Cryogenic readout techniques for germanium detectors

Energy Technology Data Exchange (ETDEWEB)

Benato, G. [University of Zurich, (Switzerland); Cattadori, C. [INFN - Milano Bicocca, (Italy); Di Vacri, A. [INFN LNGS, (Italy); Ferri, E. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy); D' Andrea, V.; Macolino, C. [GSSI/INFN LNGS, (Italy); Riboldi, S. [Universita degli Studi di Milano/INFN Milano, (Italy); Salamida, F. [Universita Milano Bicocca/INFN Milano Bicocca, (Italy)

2015-07-01

High Purity Germanium detectors are used in many applications, from nuclear and astro-particle physics, to homeland security or environment protection. Although quite standard configurations are often used, with cryostats, charge sensitive amplifiers and analog or digital acquisition systems all commercially available, it might be the case that a few specific applications, e.g. satellites, portable devices, cryogenic physics experiments, etc. also require the development of a few additional or complementary techniques. An interesting case is for sure GERDA, the Germanium Detector Array experiment, searching for neutrino-less double beta decay of {sup 76}Ge at the Gran Sasso National Laboratory of INFN - Italy. In GERDA the entire detector array, composed of semi-coaxial and BEGe naked crystals, is operated suspended inside a cryostat filled with liquid argon, that acts not only as cooling medium and but also as an active shield, thanks to its scintillation properties. These peculiar circumstances, together with the additional requirement of a very low radioactive background from all the materials adjacent to the detectors, clearly introduce significant constraints on the design of the Ge front-end readout electronics. All the Ge readout solutions developed within the framework of the GERDA collaboration, for both Phase I and Phase II, will be briefly reviewed, with their relative strength and weakness compared together and with respect to ideal Ge readout. Finally, the digital processing techniques developed by the GERDA collaboration for energy estimation of Ge detector signals will be recalled. (authors)

Analog electronics for radiation detection

CERN Document Server

2016-01-01

Analog Electronics for Radiation Detection showcases the latest advances in readout electronics for particle, or radiation, detectors. Featuring chapters written by international experts in their respective fields, this authoritative text: Defines the main design parameters of front-end circuitry developed in microelectronics technologies Explains the basis for the use of complementary metal oxide semiconductor (CMOS) image sensors for the detection of charged particles and other non-consumer applications Delivers an in-depth review of analog-to-digital converters (ADCs), evaluating the pros and cons of ADCs integrated at the pixel, column, and per-chip levels Describes incremental sigma delta ADCs, time-to-digital converter (TDC) architectures, and digital pulse-processing techniques complementary to analog processing Examines the fundamental parameters and front-end types associated with silicon photomultipliers used for single visible-light photon detection Discusses pixel sensors ...

FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

DEFF Research Database (Denmark)

Aagaard, Annabeth

2017-01-01

This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

International Nuclear Information System (INIS)

Pietro, V. Di; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Stockmanns, T.; Zambanini, A.; Rivetti, A.; Rolo, M.D.

2016-01-01

The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

Performance of the Prototype Readout System for the CMS Endcap Hadron Calorimeter Upgrade

Science.gov (United States)

Chaverin, Nate; Dittmann, Jay; Hatakeyama, Kenichi; Pastika, Nathaniel; CMS Collaboration

2016-03-01

The Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider (LHC) will upgrade the photodetectors and readout systems of the endcap hadron calorimeter during the technical stop scheduled for late 2016 and early 2017. A major milestone for this project was a highly successful testbeam run at CERN in August 2015. The testbeam run served as a full integration test of the electronics, allowing a study of the response of the preproduction electronics to the true detector light profile, as well as a test of the light yield of various new plastic scintillator materials. We present implications for the performance of the hadron calorimeter front-end electronics based on testbeam data, and we report on the production status of various components of the system in preparation for the upgrade.

Upgrading the Atlas Tile Calorimeter Electronics

CERN Document Server

Popeneciu, G; The ATLAS collaboration

2014-01-01

Tile Calorimeter is the central hadronic calorimeter of the ATLAS experiment at LHC. Around 2024, after the upgrade of the LHC the peak luminosity will increase by a factor of 5 compared to the design value, thus requiring an upgrade of the Tile Calorimeter readout electronics. Except the photomultipliers tubes (PMTs), most of the on- and off-detector electronics will be replaced, with the aim of digitizing all PMT pulses at the front-end level and sending them with 10 Gb/s optical links to the back-end electronics. One demonstrator prototype module is planned to be inserted in Tile Calorimeter in 2015 that will include hybrid electronic components able to probe the new design.

Electronics design of the RPC system for the OPERA muon

International Nuclear Information System (INIS)

Acquafredda, R.; Ambrosio, M.; Consiglio, L.

2004-01-01

The present document describes the front-end electronics of the RPC system that instruments the magnet muon spectrometer of the OPERA experiment. The main task of the OPERA spectrometer is to provide particle tracking information for muon identification and simplify the matching between the Precision Trackers. As no trigger has been foreseen for the experiment, the spectrometer electronics must be self-triggered with single-plane readout capability. Moreover, precision time information must be added within each event frame for off-line reconstruction. The read-out electronics is made of three different stages: the Front-End Boards (FEBs) system, the Controller Boards (CBs) system and Trigger Boards (TBs) system. The FEB system provides discrimination of the strip incoming signals; a FAST-OR output of the input signals is also available for trigger plane signal generation. FEB signals are required by the CB system that provides the zero suppression and manages the communication to the DAQ and Slow Control. A Trigger Board allows to operate in both self-trigger mode (the FEB's FAST-OR signal starts the plane acquisition) or in external-trigger mode (different conditions can be set on the FAST-OR signals generated from different planes)

A fast integrated readout system for a cathode pad photon detector

Energy Technology Data Exchange (ETDEWEB)

French, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Lovell, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Chesi, E. (CERN, ECP Div., Geneva (Switzerland)); Racz, A. (CERN, ECP Div., Geneva (Switzerland)); Seguinot, J. (Coll. de France, Paris (France)); Ypsilantis, T. (Coll. de France, Paris (France)); Arnold, R. (CRN, Louis Pasteur Univ., Strasbourg (France)); Guyonnet, J.L. (CRN, Louis Pasteur Univ., Strasbourg (France)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland))

1994-04-01

A fast integrated electronic chain is presented to read out the cathode pad array of a multiwire photon detector for a fast RICH counter. Two VLSI circuits have been designed and produced. An analog eight channel, low noise, fast, bipolar, current preamplifier and discriminator chip serves as front-end electronics. It has an rms equivalent noise current of 10 nA (2000 e[sup -]), 50 MHz bandwidth with 10 mW of power consumption per channel. Two analogue chips are coupled to a digital 16 channels CMOS readout chip, operating at 20 MHz, that provides a pipelined delay of 1.3 [mu]s and zero suppression with a power consumption of about 6 mW per channel. Readout of a 4000 pad sector requires 3-4 [mu]s depending on the number of hit pads. The full RICH counter is made up of many of such sectors (the prototype has three fully equipped sectors), read out in parallel. The minimum time to separate successive hits on the same pad is about 70 ns. The time skew of the full chain is about 15 ns. (orig.)

Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

International Nuclear Information System (INIS)

Conforti Di Lorenzo, S.

2010-10-01

The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

MMIC tuned front-end for a coherent optical receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

1993-01-01

A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

General-purpose readout electronics for white neutron source at China Spallation Neutron Source.

Science.gov (United States)

Wang, Q; Cao, P; Qi, X; Yu, T; Ji, X; Xie, L; An, Q

2018-01-01

The under-construction White Neutron Source (WNS) at China Spallation Neutron Source is a facility for accurate measurements of neutron-induced cross section. Seven spectrometers are planned at WNS. As the physical objectives of each spectrometer are different, the requirements for readout electronics are not the same. In order to simplify the development of the readout electronics, this paper presents a general method for detector signal readout. This method has advantages of expansibility and flexibility, which makes it adaptable to most detectors at WNS. In the WNS general-purpose readout electronics, signals from any kinds of detectors are conditioned by a dedicated signal conditioning module corresponding to this detector, and then digitized by a common waveform digitizer with high speed and high precision (1 GSPS at 12-bit) to obtain the full waveform data. The waveform digitizer uses a field programmable gate array chip to process the data stream and trigger information in real time. PXI Express platform is used to support the functionalities of data readout, clock distribution, and trigger information exchange between digitizers and trigger modules. Test results show that the performance of the WNS general-purpose readout electronics can meet the requirements of the WNS spectrometers.

Design, Construction and Testing of the Digital Hadron Calorimeter (DHCAL) Electronics

CERN Document Server

Adams, C; Bilki, B; Butler, J; Corriveau, F; Cundiff, T; Drake, G; Francis, K; Guarino, V; Haberichter, B; Hazen, E; Hoff, J; Holm, S; Kreps, A; DeLurgio, P; Monte, L Dal; Mucia, N; Norbeck, E; Northacker, D; Onel, Y; Pollack, B; Repond, J; Schlereth, J; Smith, J R; Trojand, D; Underwood, D; Velasco, M; Walendziak, J; Wood, K; Wu, S; Xia, L; Zhang, Q; Zhao, A

2016-01-01

A novel hadron calorimeter is being developed for future lepton colliding beam detectors. The calorimeter is optimized for the application of Particle Flow Algorithms (PFAs) to the measurement of hadronic jets and features a very finely segmented readout with 1 x 1 cm2 cells. The active media of the calorimeter are Resistive Plate Chambers (RPCs) with a digital, i.e. one-bit, readout. To first order the energy of incident particles in this calorimeter is reconstructed as being proportional to the number of pads with a signal over a given threshold. A large-scale prototype calorimeter with approximately 500,000 readout channels has been built and underwent extensive testing in the Fermilab and CERN test beams. This paper reports on the design, construction, and commissioning of the electronic readout system of this prototype calorimeter. The system is based on the DCAL front-end chip and a VME-based back-end.

Superconductor Microwave Kinetic Inductance Detectors: System Model of the Readout Electronics

Directory of Open Access Journals (Sweden)

F. Alimenti

2009-06-01

Full Text Available This paper deals with the readout electronics needed by superconductor Microwave Kinetic Inductance Detectors (MKIDs. MKIDs are typically implemented in the form of cryogenic-cooled high quality factor microwave resonator. The natural frequency of these resonators changes as a millimeter or sub-millimeter wave radiation impinges on the resonator itself. A quantitative system model of the readout electronics (very similar to that of a vector network analyzer has been implemented under ADS environment and tested by several simulation experiments. The developed model is a tool to further optimize the readout electronic and to design the frequency allocation of parallel-connected MKIDs resonators. The applications of MKIDs will be in microwave and millimeter-wave radiometric imaging as well as in radio-astronomy focal plane arrays.

An asynchronous data-driven readout prototype for CEPC vertex detector

Science.gov (United States)

Yang, Ping; Sun, Xiangming; Huang, Guangming; Xiao, Le; Gao, Chaosong; Huang, Xing; Zhou, Wei; Ren, Weiping; Li, Yashu; Liu, Jianchao; You, Bihui; Zhang, Li

2017-12-01

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

CERN Document Server

Tang, F; The ATLAS collaboration

2014-01-01

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and de...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Science.gov (United States)

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

DEFF Research Database (Denmark)

Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

2018-01-01

as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players.......This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...

REASONING IN THE FUZZY FRONT END OF INNOVATION:

DEFF Research Database (Denmark)

Haase, Louise Møller; Laursen, Linda Nhu

2018-01-01

in the fuzzy front end is the reasoning process: innovation teams are faced with open-ended, ill-defined problems, where they need to make decisions about an unknown future but have only incomplete, ambiguous and contradicting insights available. We study the reasoning of experts, how they frame to make sense...... of all the insights and create a basis for decision-making in relation to a new project. Based on case studies of five innovative products from various industries, we propose a Product DNA model for understanding the reasoning in the fuzzy front end of innovation. The Product DNA Model explains how...... experts reason and what direct their reasoning....

Ultrafast Readout of Scintillating Fibres Using Upgraded Position-Sensitive Photomultipliers

CERN Multimedia

2002-01-01

% RD-17 \\\\ \\\\To design a high rate topological trigger device for the future DIRAC Experiment at CERN an extensive work is in progress on a scintillating-fibre detector using a position-sensitive photomultiplier. Several detector prototypes with different lengths ($<$~50~cm) of sensitive area have been tested at T7S~PS beam. \\\\ \\\\With 0.5~mm diameter fibres a spatial resolution of $\\sim$125~$\\mu$m was obtained with a detection efficiency higher than 95\\%. The time resolution is $\\sim$600~ps, and the track position is properly digitized in real time (about 10~ns) by multi-channel peak sensing circuit. Based on experimental data simulations were also performed a comparison of different types of front-end electronics for multi-channel readout.

Terahertz performance of quasioptical front-ends with a hotelectron bolometer

International Nuclear Information System (INIS)

Semenov, A; Richter, H; Guenther, B; Huebers, H-W; Karamarkovic, J

2006-01-01

We present terahertz performance of quasioptical front-ends consisting of a hotelectron bolometer imbedded in a planar feed antenna and integrated with an immersion lens. The impedance and radiation pattern of the log-spiral and double-slot planar feeds are evaluated using the method of moments; the collimating action of the lens is modelled using the physical optics. The total efficiency of the front-ends is computed taking into account frequency dependent impedance of the bolometer. Measured performance of the front-ends qualifies the simulation technique as a reliable tool for the design of terahertz receivers

A wide dynamic range BF3 neutron monitor with front-end electronics based on a logarithmic amplifier

International Nuclear Information System (INIS)

Ferrarini, M.; Varoli, V.; Favalli, A.; Caresana, M.; Pedersen, B.

2010-01-01

This paper describes a wide dynamic range neutron monitor based on a BF 3 neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10 6 s -1 . It has also proved effective in measuring the PUNITA facility pulse integral fluence.

An Alternative Front End Analysis Strategy for Complex Systems

Science.gov (United States)

2014-12-01

missile ( ABM ) system . Patriot is employed in the field through a battalion echelon organizational structure. The line battery is the basic building...Research Report 1981 An Alternative Front End Analysis Strategy for Complex Systems M. Glenn Cobb U.S. Army Research Institute...NUMBER W5J9CQ11D0003 An Alternative Front End Analysis Strategy for Complex Systems 5b. PROGRAM ELEMENT NUMBER 633007 6

Development of the specialized integrated circuit for signal readout from micro-strip structures of a coordinate detectors

International Nuclear Information System (INIS)

Aulchenko, V.; Shekhtman, L.; Zhulanov, V.

2015-01-01

The paper presents current status of development of a specialized 64-channel integrated circuit (IC, ASIC) for front-end electronics of coordinate detectors in the Budker INP. The ASIC is produced using 180 nm process. During the recording phase the IC allows integration of short current pulses from strips of a coordinate sensor, and storing of up to 100 corresponding charge values in the analogue memory with minimum time interval of 100 ns. Maximum input charge is equal to 2×10 6 electrons, equivalent noise charge is ∼2.7×10 3 electrons. Conversion of the data, stored in the analogue memory, to digital form is performed by an external ADC during the readout through an analogue multiplexer

Technology for the compatible integration of silicon detectors with readout electronics

International Nuclear Information System (INIS)

Zimmer, G.

1984-01-01

Compatible integration of detectors and readout electronics on the same silicon substrate is of growing interest. As the methods of microelectronics technology have already been adapted for detector fabrication, a common technology basis for detectors and readout electronics is available. CMOS technology exhibits most attractive features for the compatible realization of readout electronics when advanced LSI processing steps are combined with detector requirements. The essential requirements for compatible integration are the availability of high resistivity (100)-oriented single crystalline silicon substrate, the formation of suitably doped areas for MOS circuits and the isolation of the low voltage circuit from the detector operated at much higher supply voltage. Junction isolation as a first approach based on present production technology and dielectric isolation based on an advanced SOI-LSI technology are discussed as the most promising solutions for present and future applications, respectively. (orig.)

The Belle II SVD data readout system

Energy Technology Data Exchange (ETDEWEB)

Thalmeier, R., E-mail: Richard.Thalmeier@oeaw.ac.at [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Adamczyk, K. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Aihara, H. [Department of Physics, University of Tokyo, Tokyo 113-0033 (Japan); Angelini, C. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Aziz, T.; Babu, V. [Tata Institute of Fundamental Research, Mumbai 400005 (India); Bacher, S. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Bahinipati, S. [Indian Institute of Technology Bhubaneswar, Satya Nagar (India); Barberio, E.; Baroncelli, Ti.; Baroncelli, To. [School of Physics, University of Melbourne, Melbourne, Victoria 3010 (Australia); Basith, A.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Batignani, G. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bauer, A. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Behera, P.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Bettarini, S. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bhuyan, B. [Indian Institute of Technolog y Guwahati, Assam 781039 (India); Bilka, T. [Faculty of Mathematics and Physics, Charles University, 12116 Prague (Czech Republic); Bosi, F. [INFN Sezione di Pisa, I-56127 Pisa (Italy); and others

2017-02-11

The Belle II Experiment at the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, will explore the asymmetry between matter and antimatter and search for new physics beyond the standard model. 172 double-sided silicon strip detectors are arranged cylindrically in four layers around the collision point to be part of a system which measures the tracks of the collision products of electrons and positrons. A total of 1748 radiation-hard APV25 chips read out 128 silicon strips each and send the analog signals by time-division multiplexing out of the radiation zone to 48 Flash Analog Digital Converter Modules (FADC). Each of them applies processing to the data; for example, it uses a digital finite impulse response filter to compensate line signal distortions, and it extracts the peak timing and amplitude from a set of several data points for each hit, using a neural network. We present an overview of the SVD data readout system, along with front-end electronics, cabling, power supplies and data processing.

Design and implementation of the ATLAS TRT front end electronics

Science.gov (United States)

Newcomer, Mitch; Atlas TRT Collaboration

2006-07-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

Design and implementation of the ATLAS TRT front end electronics

International Nuclear Information System (INIS)

Newcomer, Mitch

2006-01-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

Electronic zooming TV readout system for an x-ray microscope

International Nuclear Information System (INIS)

Kinoshita, K.; Matsumura, T.; Inagaki, Y.; Hirai, N.; Sugiyama, M.; Kihara, H.; Watanabe, N.; Shimanuki, Y.

1993-01-01

The electronic zooming TV readout system using the X-ray zooming tube has been developed for purposes of real-time readout of very high resolution X-ray image, e.g. the output image from an X-ray microscope. The system limiting resolution is 0.2∼0.3 μm and it is easy to operate in practical applications

Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

CERN Document Server

Tang, F; Anderson, K; Bohm, C; Hildebrand, K; Muschter, S; Oreglia, M

2015-01-01

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and de...

Phase I Upgrade of the CMS Hadron Calorimeter

CERN Document Server

Cooper, Seth Isaac

2014-01-01

In preparation for Run 2 (2015) and Run 3 of the LHC (2019), the CMS hadron calorimeter has begun a series of ambitious upgrades. These include new photodetectors in addition to improved front-end and back-end readout electronics. In the hadron forward calorimeter, the existing photomultiplier tubes are being replaced with thinner window, multi-anode readout models, while in the central region, the hybrid photodiodes will be replaced with silicon photomultipliers. The front-end electronics will include high precision timing readout, and the backend electronics will handle the increased data bandwidth. The barrel and endcap longitudinal segmentation will also be increased. This report will describe the motivation for the upgrade, its major components, and its current status.

Sustainability in the front-end of innovation at design agencies

NARCIS (Netherlands)

Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

2013-01-01

In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

Energy Technology Data Exchange (ETDEWEB)

Esch, Simone

2014-04-28

high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

Upgrade readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

Proposal for the LHCb outer tracker front-end electronics

CERN Document Server

Deppe, H; Feuerstack-Raible, M; Srowig, A; Stange, U; Hommels, B; Sluijk, T

2001-01-01

A market survey on available TDCs for reading out the LHCb Outer Tracker has left over only one TDC, which is not optimal for this purpose. Hence, a new readout architecture which is based on a TDC to be developed anew has been defined. This system fits optimal the requirements of the LHCb Outer Tracker and also should be much cheaper. The system and its main issues are described in this paper.

AREUS - a software framework for the ATLAS Readout Electronics Upgrade Simulation

CERN Document Server

Horn, Philipp; The ATLAS collaboration

2018-01-01

The design of readout electronics for the LAr calorimeters of the ATLAS detector to be operated at the future High-Luminosity LHC (HL-LHC) requires a detailed simulation of the full readout chain in order to find optimal solutions for the analog and digital processing of the detector signals. Due to the long duration of the LAr calorimeter pulses relative to the LHC bunch crossing time, out-of-time signal pile-up needs to be taken intoaccountandrealisticpulsesequencesmustbesimulatedtogetherwiththeresponseoftheelectronics. For this purpose, the ATLAS Readout Electronics Upgrade Simulation framework (AREUS) has been developed based on the Observer design pattern to provide a fast and flexible simulation tool. Energy deposits in the LAr calorimeters from fully simulated HL-LHC collision events are taken as input. Simulated and measured analog pulse shapes proportional to these energies are then combined in discrete time series with proper representation of electronics noise. Analog-to-digital conversion, gain se...

Electronic calibration developed for the CMS electromagnetic calorimeter

CERN Document Server

Baek, Y W; David, P Y; Ditta, J; Hermel, V; Fouque, N; Mendiburu, J P; Nédélec, P; Peigneux, J P; Poireau, V; Rebecchi, P; Silou, D

2004-01-01

An electronic system, designed to provide a relative calibration for the readout of the CMS electromagnetic calorimeter (CMS-ECAL), is described. On request, this system injects a pulse at the input of a predetermined group of preamplifiers with preselected amplitude and a shape identical to the one produced by the photodetectors. Several chips, in DMILL 0.8 mu m technology, have been developed for integration on the front-end electronics. We describe the principle, the testing, the measurement of their precision, and radiation hardness. (6 refs).

The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

International Nuclear Information System (INIS)

Lafond, E.; Mur, M.; Schanne, S.

1998-01-01

The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

The front-end electronics for the 1.8-kchannel SiPM tracking plane in the NEW detector

International Nuclear Information System (INIS)

Rodríguez, J.; Lorca, D.; Monrabal, F.; Toledo, J.; Esteve, R.

2015-01-01

NEW is the first phase of NEXT-100 experiment, an experiment aimed at searching for neutrinoless double-beta decay. NEXT technology combines an excellent energy resolution with tracking capabilities thanks to a combination of optical sensors, PMTs for the energy measurement and SiPMs for topology reconstruction. Those two tools result in one of the highest background rejection potentials in the field. This work describes the tracking plane that will be constructed for the NEW detector which consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards. Then it focuses in the development of the electronics needed to read the 1800 channels with a front-end board that includes per-channel differential transimpedance input amplifier, gated integrator, automatic offset voltage compensation and 12-bit ADC. Finally, a description of how the FPGA buffers data, carries out zero suppression and sends data to the DAQ interface using CERN RD-51 SRS's DTCC link specification complements the description of the electronics of the NEW detector tracking plane

A 10 MHz micropower CMOS front end for direct readout of pixel detectors

International Nuclear Information System (INIS)

Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

1990-01-01

In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

CERN Document Server

Moschovakos, Paris

2018-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

A micromachined surface stress sensor with electronic readout

NARCIS (Netherlands)

Carlen, Edwin; Weinberg, M.S.; Zapata, A.M.; Borenstein, J.T.

2008-01-01

A micromachined surface stress sensor has been fabricated and integrated off chip with a low-noise, differential capacitance, electronic readout circuit. The differential capacitance signal is modulated with a high frequency carrier signal, and the output signal is synchronously demodulated and

Prototype ALICE front-end card

CERN Multimedia

Maximilien Brice

2004-01-01

This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

A compact front-end electronics module for the SDC strawtube outer tracker

International Nuclear Information System (INIS)

Emery, M.S.; Alley, G.T.; Leitch, R.M.; Maples, R.A.; Holmes, W.

1993-01-01

The challenges of building a detector for the Superconducting Super Collider have been talked about for the last several years. Those challenges are proving to be real and in some cases tougher than expected as prototype subsystem and component development continues within the different collaborations. Not to be daunted, engineers and scientists are using ingenuity and novel designs to meet the challenges. One such area has been in the development of the outer tracker readout electronics for the Solenoidal Detector Collaboration (SDC) detector. The tracker has over 100,000 channels and is composed of strawtubes that are 4 mm in diameter and 4 meters long. The sheer number of channels and small-diameter tubes require a very high density packaging scheme with critical attendant concerns, including power consumption, cooling, and crosstalk. This paper describes the novel approach taken to solve some of these challenges

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

Science.gov (United States)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

CERN Document Server

AUTHOR|(SzGeCERN)394193

2016-01-01

A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

HINS Linac front end focusing system R&D

Energy Technology Data Exchange (ETDEWEB)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

2008-08-01

This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

Measurements of the performance of a beam condition monitor prototype in a 5 GeV electron beam

Energy Technology Data Exchange (ETDEWEB)

Hempel, M., E-mail: maria.hempel@desy.de [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Afanaciev, K. [NCPHEP, Minsk 220040 (Belarus); Burtowy, P.; Dabrowski, A. [CERN, Geneva 1211 (Switzerland); Henschel, H. [DESY, Zeuthen 15738 (Germany); Idzik, M. [AGH University of Science and Technology, Cracow 30-059 (Poland); Karacheban, O. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); Lange, W.; Leonard, J. [DESY, Zeuthen 15738 (Germany); Levy, I. [Tel Aviv University, Tel Aviv 6997801 (Israel); Lohmann, W. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Pollak, B. [Northwestern University, Evanston, IL 60208 (United States); Przyborowski, D. [AGH University of Science and Technology, Cracow 30-059 (Poland); Ryjov, V. [CERN, Geneva 1211 (Switzerland); Schuwalow, S. [DESY, Zeuthen 15738 (Germany); Stickland, D. [Princeton University, Princeton, NJ 08544 (United States); Walsh, R. [DESY, Zeuthen 15738 (Germany); Zagozdzinska, A. [CERN, Geneva 1211 (Switzerland)

2016-08-01

The Fast Beam Conditions Monitor, BCM1F, in the Compact Muon Solenoid, CMS, experiment was operated since 2008 and delivered invaluable information on the machine induced background in the inner part of the CMS detector supporting a safe operation of the inner tracker and high quality data. Due to the shortening of the time between two bunch crossings from 50 ns to 25 ns and higher expected luminosity at the Large Hadron Collider, LHC, in 2015, BCM1F needed an upgrade to higher bandwidth. In addition, BCM1F is used as an on-line luminometer operated independently of CMS. To match these requirements, the number of single crystal diamond sensors was enhanced from 8 to 24. Each sensor is subdivided into two pads, leading to 48 readout channels. Dedicated fast front-end ASICs were developed in 130 nm technology, and the back-end electronics is completely upgraded. An assembled prototype BCM1F detector comprising sensors, a fast front-end ASIC and optical analog readout was studied in a 5 GeV electron beam at the DESY-II accelerator. Results on the performance are given.

Front end designs for the 7-GeV advanced photon source

International Nuclear Information System (INIS)

Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

1992-01-01

The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

Magnet Misalignment Studies for the Front-end of the Neutrino Factory

CERN Document Server

Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

2013-01-01

In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

Parameters-adjustable front-end controller in digital nuclear measurement system

International Nuclear Information System (INIS)

Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

2013-01-01

Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

Muon Identification with the ATLAS Tile Calorimeter Read-Out Driver for Level-2 Trigger Purposes

CERN Document Server

Ruiz-Martinez, A

2008-01-01

The Hadronic Tile Calorimeter (TileCal) at the ATLAS experiment is a detector made out of iron as passive medium and plastic scintillating tiles as active medium. The light produced by the particles is converted to electrical signals which are digitized in the front-end electronics and sent to the back-end system. The main element of the back-end electronics are the VME 9U Read-Out Driver (ROD) boards, responsible of data management, processing and transmission. A total of 32 ROD boards, placed in the data acquisition chain between Level-1 and Level-2 trigger, are needed to read out the whole calorimeter. They are equipped with fixed-point Digital Signal Processors (DSPs) that apply online algorithms on the incoming raw data. Although the main purpose of TileCal is to measure the energy and direction of the hadronic jets, taking advantage of its projective segmentation soft muons not triggered at Level-1 (with pT<5 GeV) can be recovered. A TileCal standalone muon identification algorithm is presented and i...

Performance of the Electronic Readout of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Abreu, H; Aleksa, M; Aperio Bella, L; Archambault, JP; Arfaoui, S; Arnaez, O; Auge, E; Aurousseau, M; Bahinipati, S; Ban, J; Banfi, D; Barajas, A; Barillari, T; Bazan, A; Bellachia, F; Beloborodova, O; Benchekroun, D; Benslama, K; Berger, N; Berghaus, F; Bernat, P; Bernier, R; Besson, N; Binet, S; Blanchard, JB; Blondel, A; Bobrovnikov, V; Bohner, O; Boonekamp, M; Bordoni, S; Bouchel, M; Bourdarios, C; Bozzone, A; Braun, HM; Breton, D; Brettel, H; Brooijmans, G; Caputo, R; Carli, T; Carminati, L; Caughron, S; Cavalleri, P; Cavalli, D; Chareyre, E; Chase, RL; Chekulaev, SV; Chen, H; Cheplakov, A; Chiche, R; Citterio, M; Cojocaru, C; Colas, J; Collard, C; Collot, J; Consonni, M; Cooke, M; Copic, K; Costa, GC; Courneyea, L; Cuisy, D; Cwienk, WD; Damazio, D; Dannheim, D; De Cecco, S; De La Broise, X; De La Taille, C; de Vivie, JB; Debennerot, B; Delagnes, E; Delmastro, M; Derue, F; Dhaliwal, S; Di Ciaccio, L; Doan, O; Dudziak, F; Duflot, L; Dumont-Dayot, N; Dzahini, D; Elles, S; Ertel, E; Escalier, M; Etienvre, AI; Falleau, I; Fanti, M; Farooque, T; Favre, P; Fayard, Louis; Fent, J; Ferencei, J; Fischer, A; Fournier, D; Fournier, L; Fras, M; Froeschl, R; Gadfort, T; Gallin-Martel, ML; Gibson, A; Gillberg, D; Gingrich, DM; Göpfert, T; Goodson, J; Gouighri, M; Goy, C; Grassi, V; Gray, J; Guillemin, T; Guo, B; Habring, J; Handel, C; Heelan, L; Heintz, H; Helary, L; Henrot-Versille, S; Hervas, L; Hobbs, J; Hoffman, J; Hostachy, JY; Hoummada, A; Hrivnac, J; Hrynova, T; Hubaut, F; Huber, J; Iconomidou-Fayard, L; Iengo, P; Imbert, P; Ishmukhametov, R; Jantsch, A; Javadov, N; Jezequel, S; Jimenez Belenguer, M; Ju, XY; Kado, M; Kalinowski, A; Kar, D; Karev, A; Katsanos, I; Kazarinov, M; Kerschen, N; Kierstead, J; Kim, MS; Kiryunin, A; Kladiva, E; Knecht, N; Kobel, M; Koletsou, I; König, S; Krieger, P; Kukhtin, V; Kuna, M; Kurchaninov, L; Labbe, J; Lacour, D; Ladygin, E; Lafaye, R; Laforge, B; Lamarra, D; Lampl, W; Lanni, F; Laplace, S; Laskus, H; Le Coguie, A; Le Dortz, O; Le Maner, C; Lechowski, M; Lee, SC; Lefebvre, M; Leonhardt, K; Lethiec, L; Leveque, J; Liang, Z; Liu, C; Liu, T; Liu, Y; Loch, P; Lu, J; Ma, H; Mader, W; Majewski, S; Makovec, N; Makowiecki, D; Mandelli, L; Mangeard, PS; Mansoulie, B; Marchand, JF; Marchiori, G; Martin, D; Martin-Chassard, G; Martin dit Latour, B; Marzin, A; Maslennikov, A; Massol, N; Matricon, P; Maximov, D; Mazzanti, M; McCarthy, T; McPherson, R; Menke, S; Meyer, JP; Ming, Y; Monnier, E; Mooshofer, P; Neganov, A; Niedercorn, F; Nikolic-Audit, I; Nugent, IM; Oakham, G; Oberlack, H; Ocariz, J; Odier, J; Oram, CJ; Orlov, I; Orr, R; Parsons, JA; Peleganchuk, S; Penson, A; Perini, L; Perrodo, P; Perrot, G; Perus, A; Petit, E; Pisarev, I; Plamondon, M; Poffenberger, P; Poggioli, L; Pospelov, G; Pralavorio, P; Prast, J; Prudent, X; Przysiezniak, H; Puzo, P; Quentin, M; Radeka, V; Rajagopalan, S; Rauter, E; Reimann, O; Rescia, S; Resende, B; Richer, JP; Ridel, M; Rios, R; Roos, L; Rosenbaum, G; Rosenzweig, H; Rossetto, O; Roudil, W; Rousseau, D; Ruan, X; Rudert, A; Rusakovich, N; Rusquart, P; Rutherfoord, J; Sauvage, G; Savine, A; Schaarschmidt, J; Schacht, P; Schaffer, A; Schram, M; Schwemling, P; Seguin Moreau, N; Seifert, F; Serin, L; Seuster, R; Shalyugin, A; Shupe, M; Simion, S; Sinervo, P; Sippach, W; Skovpen, K; Sliwa, R; Soukharev, A; Spano, F; Stavina, P; Straessner, A; Strizenec, P; Stroynowski, R; Talyshev, A; Tapprogge, S; Tarrade, F; Tartarelli, GF; Teuscher, R; Tikhonov, Yu; Tocut, V; Tompkins, D; Thompson, P; Tisserant, S; Todorov, T; Tomasz, F; Trincaz-Duvoid, S; Trinh, Thi N; Trochet, S; Trocme, B; Tschann-Grimm, K; Tsionou, D; Ueno, R; Unal, G; Urbaniec, D; Usov, Y; Voss, K; Veillet, JJ; Vincter, M; Vogt, S; Weng, Z; Whalen, K; Wicek, F; Wilkens, H; Wingerter-Seez, I; Wulf, E; Yang, Z; Ye, J; Yuan, L; Yurkewicz, A; Zarzhitsky, P; Zerwas, D; Zhang, H; Zhang, L; Zhou, N; Zimmer, J; Zitoun, R; Zivkovic, L

2010-01-01

The ATLAS detector has been designed for operation at the Large Hadron Collider at CERN. ATLAS includes electromagnetic and hadronic liquid argon calorimeters, with almost 200,000 channels of data that must be sampled at the LHC bunch crossing frequency of 40 MHz. The calorimeter electronics calibration and readout are performed by custom electronics developed specifically for these purposes. This paper describes the system performance of the ATLAS liquid argon calibration and readout electronics, including noise, energy and time resolution, and long term stability, with data taken mainly from full-system calibration runs performed after installation of the system in the ATLAS detector hall at CERN.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

Science.gov (United States)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

International Nuclear Information System (INIS)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

Energy Technology Data Exchange (ETDEWEB)

Blaha, J. [Czech Technical University in Prague, CTU, Praha (Czech Republic); Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France)], E-mail: j.blaha@ipnl.in2p3.fr; Cartiglia, N. [Instituto Nazionale di Fisica Nucleare, INFN, Torino (Italy); Combaret, C. [Czech Technical University in Prague, CTU, Praha (Czech Republic); Fay, J. [Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France); Lustermann, W. [Eidgenossische Technische Hoschschule, ETH, Zuerich (Switzerland); Maurelli, G. [Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France); Nardulli, A. [Eidgenossische Technische Hoschschule, ETH, Zuerich (Switzerland); Obertino, M. [Instituto Nazionale di Fisica Nucleare, INFN, Torino (Italy)

2007-10-15

The Very-Front-End cards processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee their functionality and reliability. The characteristics of the VFE cards designed for the calorimeter barrel are presented. The results confirm the high quality of the cards production and show that the specifications are fully reached.

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

International Nuclear Information System (INIS)

Blaha, J.; Cartiglia, N.; Combaret, C.; Fay, J.; Lustermann, W.; Maurelli, G.; Nardulli, A.; Obertino, M.

2007-01-01

The Very-Front-End cards processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee their functionality and reliability. The characteristics of the VFE cards designed for the calorimeter barrel are presented. The results confirm the high quality of the cards production and show that the specifications are fully reached

Research and Development for a Free-Running Readout System for the ATLAS LAr Calorimeters at the High Luminosity LHC

CERN Document Server

Hils, Maximilian; The ATLAS collaboration

2015-01-01

The ATLAS Liquid Argon (LAr) Calorimeters were designed and built to measure electromagnetic and hadronic energy in proton-proton collisions produced at the LHC at centre-of-mass energies up to 14 TeV and instantaneous luminosities up to $10^{34} \\text{cm}^{-2} \\text{s}^{-1}$. The High Luminosity LHC (HL-LHC) programme is now developed for up to 5-7 times the design luminosity, with the goal of accumulating an integrated luminosity of $3000~\\text{fb}^{-1}$. In the HL-LHC phase, the increased radiation levels require a replacement of the front-end electronics of the LAr Calorimeters. Furthermore, the ATLAS trigger system is foreseen to increase the trigger accept rate by a factor 10 to 1 MHz and the trigger latency by a factor of 20 which requires a larger data volume to be buffered. Therefore, the LAr Calorimeter read-out will be exchanged with a new front-end and a high bandwidth back-end system for receiving data from all 186.000 channels at 40 MHz LHC bunch-crossing frequency and for off-detector buffering...

Next generation of optical front-ends for numerical services - 15387

International Nuclear Information System (INIS)

Fullenbaum, M.; Durieux, A.; Dubroca, G.; Fuss, P.

2015-01-01

Visual Inspection and surveillance technology means in environments exhibiting high levels of gamma and neutron radiation are nowadays fulfilled through the use of analog tubes. The images are thus acquired with analog devices whose vast majority relies on 1 and 2/3 inch imaging formats and deliver native analog images. There is a growing demand for real time image processing and distribution through Ethernet services for quicker and seamless process integration throughout many sectors. This will call for the inception of solid state sensor (CCD, CMOS) to generate numerical native images as the first step and building block towards end to end numerical processing (ICT), assuming these sensors can be hardened or protected in the field of the nuclear industry. On the one hand, these sensor sizes will be significantly reduced (by a factor of 2-3) versus those of the tubes, and on the other hand, one will also be presented with the opportunity of increased spatial resolution, stemming from the high pixel count of the solid state technology, for implementation of new or better services or of enhanced pieces of information for decision making purposes. In order to reap the benefits of such sensors, new optical front-ends will have to be designed. Over and beyond the mere aspects of matching the reduced sensor size to the size of the scenes at stake, optical performances of these front-end will also bear an impact on the whole optical chain applications. As an example, detection and tracking needs will be different from a performance standpoint and the overall performances will have to be balanced out in between the optical front-end, the image format, the image processing software capability, processing speed,...just to name a few. In this paper we will review and explain the missing gaps in order to switch to a full numerical optical chain by focusing on the optical front-end and the associated cost trade-offs. Finally, we will conclude by clearly stating the best

Measurement of Design Process Front-End – Radical Innovation Approach

DEFF Research Database (Denmark)

Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

2014-01-01

The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase...... of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

Optimized capture section for a muon accelerator front end

Directory of Open Access Journals (Sweden)

Hisham Kamal Sayed

2014-07-01

Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

Repetitive readout of a single electronic spin via quantum logic with nuclear spin ancillae.

Science.gov (United States)

Jiang, L; Hodges, J S; Maze, J R; Maurer, P; Taylor, J M; Cory, D G; Hemmer, P R; Walsworth, R L; Yacoby, A; Zibrov, A S; Lukin, M D

2009-10-09

Robust measurement of single quantum bits plays a key role in the realization of quantum computation and communication as well as in quantum metrology and sensing. We have implemented a method for the improved readout of single electronic spin qubits in solid-state systems. The method makes use of quantum logic operations on a system consisting of a single electronic spin and several proximal nuclear spin ancillae in order to repetitively readout the state of the electronic spin. Using coherent manipulation of a single nitrogen vacancy center in room-temperature diamond, full quantum control of an electronic-nuclear system consisting of up to three spins was achieved. We took advantage of a single nuclear-spin memory in order to obtain a 10-fold enhancement in the signal amplitude of the electronic spin readout. We also present a two-level, concatenated procedure to improve the readout by use of a pair of nuclear spin ancillae, an important step toward the realization of robust quantum information processors using electronic- and nuclear-spin qubits. Our technique can be used to improve the sensitivity and speed of spin-based nanoscale diamond magnetometers.

Upgrading the ATLAS Tile Calorimeter Electronics

Directory of Open Access Journals (Sweden)

Carrió Fernando

2013-11-01

Full Text Available This work summarizes the status of the on-detector and off-detector electronics developments for the Phase 2 Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in the middle of 2014 during the first Long Shutdown. For the on-detector readout, three different front-end boards (FEB alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The Main Board will provide communication and control to the FEBs and the Daughter Board will transmit the digitized data to the off-detector electronics in the counting room, where the super Read-Out Driver (sROD will perform processing tasks on them and will be the interface to the trigger levels 0, 1 and 2.

Electronic readout for THGEM detectors based on FPGA TDCs

Energy Technology Data Exchange (ETDEWEB)

Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

2013-07-01

In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

The Front-End electronics for the LHCb scintillating fibres detector

CERN Document Server

Chanal, Hervé; Pillet, Nicolas

2014-01-01

The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [ 1 ]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250 m m fibres with an area of 5 6 m 2 . It leads to a total of 500k SiPM channels which need to be read out at 40 MHz. This article gives an overview of the R&D; status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the other side. The PACIFIC chip is a 128-channels ASIC which can be connected to one 1...

Reliable and redundat FPGAbased read-out design in the ATLAS TileCal Demonstrator

CERN Document Server

Akerstedt, H; The ATLAS collaboration

2014-01-01

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases its luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but stays backwards compatible with the present detector system by providing analog trigger signals. The Demonstrator is comprised of 4 identical “mini-drawers”, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize the 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and detector operatio...

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

Energy Technology Data Exchange (ETDEWEB)

Rovati, L; Bonaiuti, M [Dipartimento di Ingegneria dell' Informazione, Universita di Modena e Reggio Emilia, Modena (Italy); Bettarini, S [Dipartimento di Fisica, Universita di Pisa and INFN Pisa, Pisa (Italy); Bosisio, L [Dipartimento di Fisica, Universita di Trieste and INFN Trieste, Trieste (Italy); Dalla Betta, G-F; Tyzhnevyi, V [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita di Trento e INFN Trento, Trento (Italy); Verzellesi, G [Dipartimento di Scienze e Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia and INFN Trento, Reggio Emilia (Italy); Zorzi, N, E-mail: giovanni.verzellesi@unimore.i [Fondazione Bruno Kessler (FBK), Trento (Italy)

2009-11-15

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

International Nuclear Information System (INIS)

Rovati, L; Bonaiuti, M; Bettarini, S; Bosisio, L; Dalla Betta, G-F; Tyzhnevyi, V; Verzellesi, G; Zorzi, N

2009-01-01

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

A wide dynamic range BF{sub 3} neutron monitor with front-end electronics based on a logarithmic amplifier

Energy Technology Data Exchange (ETDEWEB)

Ferrarini, M., E-mail: michele.ferrarini@polimi.i [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Fondazione CNAO, via Caminadella 16, 20123 Milano (Italy); Varoli, V. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Favalli, A. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Vatican City State, Holy See) (Italy); Caresana, M. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Pedersen, B. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Italy)

2010-02-01

This paper describes a wide dynamic range neutron monitor based on a BF{sub 3} neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10{sup 6} s{sup -1}. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

1994-01-01

In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

Investigation of the readout electronics of DELPHI surround muon chamber

International Nuclear Information System (INIS)

Khovanskij, N.; Krumshtejn, Z.; Ol'shevskij, A.; Sadovskij, A.; Sedykh, Yu.; Molnar, J.; Sicho, P.; Tomsa, Z.

1995-01-01

The characteristics of the readout electronics of the DELPHI surround muon chambers with various AMPLEX chips (AMPLEX 16 and AMPLEX-SICAL) are presented. This electronics is studied in a cosmic rays test of the real surround muon chamber model. 4 refs., 6 figs., 1 tab

Radiological and environmental surveillance in front-end fuel cycle facilities

International Nuclear Information System (INIS)

Khan, A.H.; Sahoo, S.K.; Tripathi, R.M.

2004-01-01

This paper describes the occupational and environmental radiological safety measures associated with the operations of front end nuclear fuel cycle. Radiological monitoring in the facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised

Observations on dual-ended readout of 100 mm long LYSO crystals

Energy Technology Data Exchange (ETDEWEB)

Ur-Rehman, Fazal, E-mail: Fazal@physics.umanitoba.ca [Department of Physics and Astronomy, University of Manitoba, Winnipeg (Canada); McIntosh, Bryan [Department of Physics and Astronomy, University of Manitoba, Winnipeg (Canada); Goertzen, Andrew L. [Department of Physics and Astronomy, University of Manitoba, Winnipeg (Canada); Department of Radiology, University of Manitoba, Winnipeg (Canada)

2011-10-01

We are investigating using dual-ended readout of axially oriented long thin scintillator crystals in detectors for a compact geometry, small ring diameter animal PET system. The axial position of interaction is determined from the light sharing between two photodetectors at opposite ends of the crystal. We examine the light output, energy resolution and axial spatial resolution of 1.5-5x2x100 mm{sup 3} polished LYSO crystals by irradiating with an electronically collimated beam of 511 keV photons oriented perpendicular to the long axis and read out at either end by position sensitive photomultiplier tubes (PSPMTs). Three reflector materials, namely Teflon, 3 M enhanced specular reflector (ESR) and black paint are examined for the 2x2x100 mm{sup 3} crystal size. The light output increases and energy resolution improves with the crystal cross-section. Generally, the spatial resolution worsens with increase in crystal cross-section. For the 2x2x100 mm{sup 3} crystal size, the mean energy resolutions of the photopeak over the nine irradiation positions were 14.4{+-}0.4%, 16.0{+-}1.2% and 28.3{+-}2.1% with mean spatial resolutions of 7.0{+-}1.0, 9.4{+-}3.3 and 26.0{+-}5.0 mm using ESR, Teflon and black paint, respectively. ESR reflector gave the best light output, energy and axial spatial resolutions. These characterization results of PSPMT-based dual-ended long LYSO crystals will be useful in the design of detector modules for a highly compact geometry preclinical PET system using this detector technology.

Analog front end circuit design of CSNS beam loss monitor system

International Nuclear Information System (INIS)

Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

2013-01-01

The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Directory of Open Access Journals (Sweden)

Senkin Sergey

2018-01-01

Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Science.gov (United States)

Senkin, Sergey

2018-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

DEFF Research Database (Denmark)

Aagaard, Annabeth

2013-01-01

to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

Integrated X-band FMCW front-end in SiGe BiCMOS

NARCIS (Netherlands)

Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

2010-01-01

An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

Fabrication of 1m x 1m readout strips panel and quality verification of new set of SFS dielectric material

International Nuclear Information System (INIS)

Kumar, A.; Pandey, A.; Sogarwal, Hariom; Marimuthu, N.; Singh, V.; Subrahmanyam, V.S.

2016-01-01

India based Neutrino Observatory (INO) is going to use ∼ 30,000 Resistive Plate Chamber (RPC) as an active detector. Resistive Plate chambers are parallel plate fast gaseous detector made up of high resistivity (10"1"2 ohm) of glass or bakelite. Glass plates work as electrodes of positive and negative potential. When a charged particle passes through chamber it ionizes the gas and charge move towards opposite electrodes. The pick-up panels pick these signals. Signals are sent to front end electronics. The characteristic impedance of the strips of the panels should be matched with front end electronics which helps in minimizing the reflected signal. Since INO is an underground laboratory, all material used in it must be fireproof. Since ∼ 60,000 pick-up panels are going to be used in INO hence it should be cheaper also. We recently received a new set of Silicon Fiber Sheets - a dielectric material, of 25 pieces of 1m x 0.5m having thickness 05 mm. We fabricated a set of readout strips panel of dimension 1m x 1m. We will present this work in detail

Upgraded Readout and Trigger Electronics for the ATLAS Liquid Argon Calorimeter at the LHC at the Horizons 2018-2022

CERN Document Server

Oliveira Damazio, Denis; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

Upgraded Readout and Trigger Electronics for the ATLAS Liquid-Argon Calorimeters at the LHC at the Horizons 2018-2022

CERN Document Server

Damazio, D O; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

A multitasking, multisinked, multiprocessor data acquisition front end

International Nuclear Information System (INIS)

Fox, R.; Au, R.; Molen, A.V.

1989-01-01

The authors have developed a generalized data acquisition front end system which is based on MC68020 processors running a commercial real time kernel (rhoSOS), and implemented primarily in a high level language (C). This system has been attached to the back end on-line computing system at NSCL via our high performance ETHERNET protocol. Data may be simultaneously sent to any number of back end systems. Fixed fraction sampling along links to back end computing is also supported. A nonprocedural program generator simplifies the development of experiment specific code

Time over threshold readout method of SiPM based small animal PET detector

International Nuclear Information System (INIS)

Valastyan, I.; Gal, J.; Hegyesi, G.; Kalinka, G.; Nagy, F.; Kiraly, B.; Imrek, J.; Molnar, J.

2012-01-01

Complete text of publication follows. The aim of the work was to design a readout concept for silicon photomultiplier (SiPM) sensor array used in small animal PET scanner. The detector module consist of LYSO 35x35 scintillation crystals, 324 SiPM sensors (arranged in 2x2 blocks and those quads in a 9x9 configuration) and FPGA based readout electronics. The dimensions of the SiPM matrix are area: 48x48 mm 2 and the size of one SiPM sensor is 1.95x2.2 mm 2 . Due to the high dark current of the SiPM, conventional Anger based readout method does not provide sufficient crystal position maps. Digitizing the 324 SiPM channels is a straightforward way to obtain proper crystal position maps. However handling hundreds of analogue input channels and the required DSP resources cause large racks of data acquisition electronics. Therefore coding of the readout channels is required. Proposed readout method: The coding of the 324 SiPMs consists two steps: Step 1) Reduction of the channels from 324 to 36: Row column readout, SiPMs are connected to each other in column by column and row-by row, thus the required channels are 36. The dark current of 18 connected SiPMs is small in off for identifying pulses coming from scintillating events. Step 2) Reduction of the 18 rows and columns to 4 channels: Comparators were connected to each rows and columns, and the level was set above the level of dark noise. Therefore only few comparators are active when scintillation light enters in the tile. The output of the comparator rows and columns are divided to two parts using resistor chains. Then the outputs of the resistor chains are digitized by a 4 channel ADC. However instead of the Anger method, time over threshold (ToT) was used. Figure 1 shows the readout concept of the SiPM matrix. In order to validate the new method and optimize the front-end electronics of the detector, the analogue signals were digitized before the comparators using a CAEN DT5740 32 channel digitizer, then the

HINS Linac front end focusing system R and D

International Nuclear Information System (INIS)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; Fermilab; Argonne

2008-01-01

This report summarizes current status of an R and D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process

The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

International Nuclear Information System (INIS)

Balsamo, E; Bergnoli, A; Bertolin, A; Brugnera, R; Carrara, E; Ciesielski, R; Dal Corso, F; Dusini, S; Garfagnini, A; Kose, U; Longhin, A; Medinaceli, E; Stanco, L

2012-01-01

The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m 2 , and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

Directory of Open Access Journals (Sweden)

J.-M. Wu

2012-06-01

Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

Towards self-triggered digitization and data readout in the CBM time-of-flight system

Energy Technology Data Exchange (ETDEWEB)

Simon, Christian; Herrmann, Norbert [Physikalisches Institut und Fakultaet fuer Physik und Astronomie, Ruprecht-Karls-Universitaet Heidelberg, 69120 Heidelberg (Germany); Collaboration: CBM-Collaboration

2015-07-01

The design goal of the future Compressed Baryonic Matter (CBM) experiment is to measure rare probes of dense strongly interacting matter with an unprecedented accuracy. Target interaction rates of up to 10 MHz for heavy systems like Au+Au and the need to identify experimental signatures of probes like multi-strange hyperons in the online data stream place challenging demands on the experiment's data acquisition system. Each detector subsystem in CBM implements a self-triggered digitization and readout chain fitted to the respective front-end electronics sending continuous data streams to a high-performance computing farm called the First-Level Event Selector (FLES). Here, events are reconstructed online to identify the physically most interesting ones as only a fraction of the enormous data rate (up to 1 TB/s) can be stored permanently for later offline analysis. The time-of-flight (TOF) wall of CBM is composed of high-resolution timing multi-gap resistive plate chambers (MRPCs) which are estimated to deliver signal rates of up to 500 kHz per electronics channel. Prototypical readout schemes currently under test which are able to transport this high payload are presented, and an outline towards inclusion in the FLES network is given.

Observations on dual-ended readout of 100 mm long LYSO crystals

International Nuclear Information System (INIS)

Ur-Rehman, Fazal; McIntosh, Bryan; Goertzen, Andrew L.

2011-01-01

We are investigating using dual-ended readout of axially oriented long thin scintillator crystals in detectors for a compact geometry, small ring diameter animal PET system. The axial position of interaction is determined from the light sharing between two photodetectors at opposite ends of the crystal. We examine the light output, energy resolution and axial spatial resolution of 1.5-5x2x100 mm 3 polished LYSO crystals by irradiating with an electronically collimated beam of 511 keV photons oriented perpendicular to the long axis and read out at either end by position sensitive photomultiplier tubes (PSPMTs). Three reflector materials, namely Teflon, 3 M enhanced specular reflector (ESR) and black paint are examined for the 2x2x100 mm 3 crystal size. The light output increases and energy resolution improves with the crystal cross-section. Generally, the spatial resolution worsens with increase in crystal cross-section. For the 2x2x100 mm 3 crystal size, the mean energy resolutions of the photopeak over the nine irradiation positions were 14.4±0.4%, 16.0±1.2% and 28.3±2.1% with mean spatial resolutions of 7.0±1.0, 9.4±3.3 and 26.0±5.0 mm using ESR, Teflon and black paint, respectively. ESR reflector gave the best light output, energy and axial spatial resolutions. These characterization results of PSPMT-based dual-ended long LYSO crystals will be useful in the design of detector modules for a highly compact geometry preclinical PET system using this detector technology.

Fabrication of the GLAST Silicon Tracker Readout Electronics

Energy Technology Data Exchange (ETDEWEB)

Baldini, Luca; Brez, Alessandro; Himel, Thomas; Johnson, R.P.; Latronico, Luca; Minuti, Massimo; Nelson, David; Sadrozinski, H.F.-W.; Sgro, Carmelo; Spandre, Gloria; Sugizaki, Mutsumi; Tajima, Hiro; Cohen Tanugi, Johann; Young, Charles; Ziegler, Marcus; /Pisa U. /INFN, Pisa /SLAC /UC, Santa Cruz

2006-03-03

A unique electronics system has been built and tested for reading signals from the silicon-strip detectors of the Gamma-ray Large Area Space Telescope mission. The system amplifies and processes signals from 884,736 36-cm long silicon strips in a 4 x 4 array of tower modules. An aggressive mechanical design fits the readout electronics in narrow spaces between the tower modules, to minimize dead area. This design and the resulting departures from conventional electronics packaging led to several fabrication challenges and lessons learned. This paper describes the fabrication processes and how the problems peculiar to this design were overcome.

TID-dependent current measurements of IBL readout chips

Energy Technology Data Exchange (ETDEWEB)

Dette, Karola [TU Dortmund, Experimentelle Physik IV (Germany); CERN (Switzerland); Collaboration: ATLAS Pixel-Collaboration

2016-07-01

The ATLAS detector consists of several subsystems with a hybrid pixel detector as the innermost component of the tracking system. The pixel detector has been composed of three layers of silicon sensor assemblies during the first data taking run of the LHC and has been upgraded with a new 4th layer, the so-called Insertable B-Layer (IBL), in summer 2014. Each silicon sensor of the IBL is connected to a Front End readout chip (FE-I4) via bump bonds. During the first year of data taking an increase of the LV current produced by the readout chips was observed. This increase could be traced back to radiation damage inside the silicon. The dependence of the current on the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations and will be presented in this talk.

Development of the Experiment Control System and Performance Study of the Muon Chambers for the LHCb Experiment

CERN Document Server

Antunes Nobrega, R; Penso, G; Pinci, D

2010-01-01

The work of this thesis practically opened three fronts of the LHCb muon system : the development of the control and monitoring system of the readout electronics; the study of noise and threshold of the detector; and the study of the performance of the muon chambers. The LHCb muon readout apparatus is made 1368 Multi-Wire Proportional Chambers (MWPC) and 24 Gas Electron Multiplier (GEM) chambers connected to approximately 7500 16-channel front-end boards, resulting in 120000 output channels. The large-scale of this system naturally led to a complex control and monitoring system made of about 600 microcontrollers which are directly connected to the front-end electronics and handled by six computers. The development of this control system was accomplished within this thesis; the microcontroller’s firmware and the high level software, operating on the six local computers, were implemented. Besides configuring and monitoring the on-chamber readout electronics, a set of calibration and debugging oriented procedu...

Status on the development of front-end and readout electronics for ...

Indian Academy of Sciences (India)

look for the best integrated technologies available that allow to avoid as much ... Pulse height will be used to improve the position resolution to a few µm, 5–10 .... by the fall of 2006 including digital: chip control (state machine), buffer memory.

The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Yang, Yi-lin; The ATLAS collaboration

2018-01-01

The Super Cell has been proposed in the Phase-I LAr upgrade to replace the existing trigger system "Trigger Tower" due to higher luminosity environments in Run 3 at LHC. The higher granularity of the Super Cell trigger systems requires higher data transmission and processing rate. The new system is also needed to be compatible with the existing trigger system. To fulfill these requirements, the new electronics including frond end and back end are developed. In the front-end part, the new LSB sums the LAr cell signals into Super Cell signals. The new baseplane distributes analog signals among FEBs, LTDB and TBB. The LTDB sums Super Cell signals to Trigger Tower signals and redirected the signals to TBB. The Analog signals are also digitized in LTDB and then sent to back end electronics. In the back-end part, the architecture is based on ATCA. The LAr carrier is used for monitoring and controlling. The LATOMEs inserted into the LAr carrier provide energy calculation from the digitized signals. So far, the demon...

The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

Energy Technology Data Exchange (ETDEWEB)

Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

2013-12-21

The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

Energy Technology Data Exchange (ETDEWEB)

Loechner, S.

2006-07-26

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

International Nuclear Information System (INIS)

Loechner, S.

2006-01-01

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout