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Sample records for fpga delay circuit

  1. A Digital DLL-Based Delay Management Circuit for FPGA's IO Cell%基于数字延时锁相环的FPGA IO延时管理电路

    Institute of Scientific and Technical Information of China (English)

    王鹏翔; 周灏; 来金梅

    2013-01-01

    本文提出了一种基于过采样量化器和换挡(Gear-Shift)控制机制的新颖的数字延时锁相环(DDLL),可以嵌入于FPGA芯片IO单元的延时管理系统,实现了IO单元数据通路延时的精确校正,分辨率达到78 ps,可调节范围达4 ns,满足FPGA芯片对高速串行接口协议复杂时序的兼容.DDLL使用独具特色的过采样量化器,仅使用1 bit时间数字转换器(TDC)达到了98 dB SNR,等效理论分辨率达16位,并引入了全新的Gear-Shift控制机制,对误差信息合理的加权实现快速精确的锁入,结合2阶巴特沃斯衰减的数字环路滤波器,实现全数字环路控制,较传统模拟延时锁相环,节省了芯片面积和功耗,同时对数字电路所产生的衬底噪声具有更好耐受.DDLL采用65 nm数字工艺,嵌入复旦大学自主研发的FPGA芯片,经过后仿验证,锁定时间小于50 cycles.%A novel digital DLL based on over-sample quantization and Gear-Shift mechanism is proposed.It was embedded in the FPGA's IO cell for delay management and achieved precisely controlled delay length.The resolution is 78 ps and the adjustable range is 4 ns,thus the FPGA chip is compatible with high-speed serial interface protocol.The unique over sample quantization using 1 bit TDC achieves 98 dB SNR and equivalent resolution of 16 bits.The novel Gear-Shift control mechanism,processing the phase error information in reasonably weight,achieves fast and accurate locking-in.Combined with a 2-order Butterworth digital loop filter for attenuation,a fully digital control loop is accomplished.The locking-in process is speeded up with better tolerance to the sub-coupling noise generated by the digital circuits around.Fabricated in 65 nm digital process and embedded in the FPGA chip developed by Fudan University,simulation of the DLL demonstrates a lock time of less than 50 cycles.

  2. DYNAMIC LABELING BASED FPGA DELAY OPTIMIZATION ALGORITHM

    Institute of Scientific and Technical Information of China (English)

    吕宗伟; 林争辉; 张镭

    2001-01-01

    DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm's kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.

  3. Rapid FPGA-based Delay Estimation for the Hardware/Software Partitioning

    Directory of Open Access Journals (Sweden)

    Xiaoxia Niu

    2013-05-01

    Full Text Available To aid in the hardware/software partitioning of the reconfigurable computing systems, it is necessary to conduct fast and accurate FPGA-based delay estimations before the partitioning. Most previous works predict the delay by adopting a high-level delay estimation based on empirical formulae. In such method, the empirical formulae are often obtained by a regression analysis on the real values reported by the synthesis and place-and-route tools of FPGAs. With alternative properties of tools or different FPGA devices, the empirical formulae need to be re-analyzed and decided. However, it is time-consuming due to inevitably repeated running synthesis and place-and-route tasks, which results in slow estimation and always beyond the tolerance of the estimation time. To address this problem, we present an improved high-level delay-estimation method in this article. We derived theory formulae called increasing formulae for HLL (High Level Language operations from the basic idea of the hardware circuit design. These increasing formulae can be fit for most FPGAs. Combining the proposed formulae, the paper proposes a rapid estimation algorithm also. And the algorithm can obtain hardware delay of different hardware versions, thus reduces the number of times of running the time-consuming tasks greatly. Experimental results show that our method can achieve error within 2.69% for virtex-5 FPGA, compared with the real values.

  4. New Techniques for Implementation of Hardware Algorithms inside FPGA Circuits

    Directory of Open Access Journals (Sweden)

    IOAN, A. D.

    2010-05-01

    Full Text Available This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the "Altium Designer" software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a "Digilent Spartan-3" FPGA development board, which includes the user interface too.

  5. Delay locked loop integrated circuit.

    Energy Technology Data Exchange (ETDEWEB)

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  6. A new synchronization control circuit based on FPGA for the laser range-gated imaging system

    Institute of Scientific and Technical Information of China (English)

    HE Shan; LI Li; ZHOU Yan

    2009-01-01

    Synchronization control is a kernel technique of the laser range-gated (LRG) imaging system which controls the synchro-nization of the pulsed laser and the ICCD camera directly. It can achieve range gating effectively and improve the resolution of image precisely. Conventional control circuits which are composed of discrete components have a poor performance of anti-interference, and the transmitting signal has a-bad delay which affects the conventional circuit's precision and stabili-zation seriously. To solve these problems, a range-gated synchronization control circuit is designed. This circuit, which takes the advantages of FPGA's high compact and flexibility, uses the phase-locking-loop (PLL) to multiply the global clock frequency. This design improves the precision and stabilization greatly, makes the precision up to a nanosecond level and provides a real-time selection of the values of pulse width and delays. Experiments results indicate that this circuit has a high precise and stable range-gated pulse.

  7. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

    Science.gov (United States)

    Zhujia, Chen; Haigang, Yang; Fei, Liu; Yu, Wang

    2011-10-01

    A fast-locking all-digital delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array (FPGA). The ADDLL performs a 90° phase-shift so that the data strobe (DQS) can enlarge the data valid window in order to minimize skew. In order to further reduce the locking time and to prevent the harmonic locking problem, a time-to-digital converter (TDC) is proposed. A duty cycle corrector (DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%. The ADDLL, implemented in a commercial 0.13 μm CMOS process, occupies a total of 0.017 mm2 of active area. Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps. The time interval error (TIE) of the proposed circuit is 60.7 ps.

  8. Research of Delay-Fault Testing Technology in FPGA%FPGA 时延故障检测技术研究磁

    Institute of Scientific and Technical Information of China (English)

    杨士宁; 顾颖; 石雪梅

    2015-01-01

    With the fast application of FPGA devices ,the FPGA device fault testing and fault diagnosis method for a more comprehensive study is of great significance .The delay‐fault is an important type of FPGA interior faults .The FPGA delay‐fault includes interior logic resources delay and interior routing resources delay .Therefore ,the inter structure and de‐lay‐fault of FPGA are analyzed ,and the fault testing method for interior logic resources delay and interior routing resources delay are researched .The test approach is successfully implemented using one Virtex‐ Ⅱ FPGA of Xilinx .The realization of Delay‐Fault Testing technology in FPGAs is proved .%随着 FPGA 器件的应用越来越广泛,FPGA 的测试和故障诊断技术得到了广泛重视和研究。 FPGA 的时延故障是 FPGA 内部故障中非常重要的一类故障类型,主要包含器件内部逻辑资源时延故障和连线资源时延故障。论文通过分析 FPGA 的内部结构和时延故障特性,研究 FPGA 内部逻辑资源时延和连线资源时延故障检测方法。利用 Xilinx 公司Virtex‐Ⅱ系列 FPGA 完成时延故障检测方法验证,证明了 FPGA 时延故障检测的可实现性。

  9. Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

    Institute of Scientific and Technical Information of China (English)

    Wu Fang; Zhang Huowen; Lai Jinmei; Wang Yuan; Chen Liguang; Duan Lei; Tong Jiarong

    2009-01-01

    This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.

  10. Design and implementation of a programming circuit in radiation-hardened FPGA

    Institute of Scientific and Technical Information of China (English)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Stanley L. Chen

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme,optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si),dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  11. Design and implementation of a programming circuit in radiation-hardened FPGA

    Science.gov (United States)

    Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

    2011-08-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  12. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

    Institute of Scientific and Technical Information of China (English)

    Chen Zhujia; Yang Haigang; Liu Fei; Wang Yu

    2011-01-01

    A fast-locking all-digital delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array (FPGA).The ADDLL performs a 90° phase-shift so that the data strobe (DQS) can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter (TDC) is proposed.A duty cycle corrector (DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13 μm CMOS process,occupies a total of 0.017 mm2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error (TIE) of the proposed circuit is 60.7 ps.

  13. Delay Reduction in Optimized Reversible Multiplier Circuit

    Directory of Open Access Journals (Sweden)

    Mohammad Assarian

    2012-01-01

    Full Text Available In this study a novel reversible multiplier is presented. Reversible logic can play a significant role in computer domain. This logic can be applied in quantum computing, optical computing processing, DNA computing, and nanotechnology. One condition for reversibility of a computable model is that the number of input equate with the output. Reversible multiplier circuits are the circuits used frequently in computer system. For this reason, optimization in one reversible multiplier circuit can reduce its volume of hardware on one hand and increases the speed in a reversible system on the other hand. One of the important parameters that optimize a reversible circuit is reduction of delays in performance of the circuit. This paper investigates the performance characteristics of the gates, the circuits and methods of optimizing the performance of reversible multiplier circuits. Results showed that reduction of the reversible circuit layers has lead to improved performance due to the reduction of the propagation delay between input and output period. All the designs are in the nanometric scales.

  14. Photonic Quantum Circuits with Time Delays

    CERN Document Server

    Pichler, Hannes

    2015-01-01

    We study the dynamics of photonic quantum circuits consisting of nodes coupled by quantum channels. We are interested in the regime where time delay in communication between the nodes is significant. This includes the problem of quantum feedback, where a quantum signal is fed back on a system with a time delay. We develop a matrix product state approach to solve the Quantum Stochastic Schr\\"odinger Equation with time delays, which accounts in an efficient way for the entanglement of nodes with the stream of emitted photons in the waveguide, and thus the non-Markovian character of the dynamics. We illustrate this approach with two paradigmatic quantum optical examples: two coherently driven distant atoms coupled to a photonic waveguide with a time delay, and a driven atom coupled to its own output field with a time delay as an instance of a quantum feedback problem.

  15. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    Directory of Open Access Journals (Sweden)

    Chao Chen

    2014-01-01

    Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

  16. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

    2015-01-21

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

  17. Development of a Low-cost, FPGA-based, Delay Line Particle Detector for Satellite and Sounding Rocket Applications

    Science.gov (United States)

    Harrington, M.; Kujawski, J. T.; Adrian, M. L.; Weatherwax, A. T.

    2013-12-01

    Electrons are, by definition, a fundamental, chemical and electromagnetic constituent of any plasma. This is especially true within the partially ionized plasmas of Earth's ionosphere where electrons are a critical component of a vast array of plasma processes. Siena College is working on a novel method of processing information from electron spectrometer anodes using delay line techniques and inexpensive COTS electronics to track the movement of high-energy particles. Electron spectrometers use a variety of techniques to determine where an amplified electron cloud falls onto a collecting surface. One traditional method divides the collecting surface into sectors and uses a single detector for each sector. However, as the angular and spatial resolution increases, so does the number of detectors, increasing power consumption, cost, size, and weight of the system. An alternative approach is to connect each sector with a delay line built within the PCB material which is shielded from cross talk by a flooded ground plane. Only one pair of detectors (e.g., one at each end of the chain) are needed with the delay line technique which is different from traditional delay line detectors which use either Application Specific Integrated Circuits (ASICs) or very fast clocks. In this paper, we report on the implementation and testing of a delay line detector using a low-cost Xilinx FPGA and a thirty-two sector delay system. This Delay Line Detector has potential satellite and rocket flight applications due to its low cost, small size and power efficiency

  18. High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

    CERN Document Server

    Palchaudhuri, Ayan

    2016-01-01

    This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

  19. An FPGA Implementation of a Polychronous Spiking Neural Network with Delay Adaptation.

    Science.gov (United States)

    Wang, Runchun; Cohen, Gregory; Stiefel, Klaus M; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, André

    2013-01-01

    We present an FPGA implementation of a re-configurable, polychronous spiking neural network with a large capacity for spatial-temporal patterns. The proposed neural network generates delay paths de novo, so that only connections that actually appear in the training patterns will be created. This allows the proposed network to use all the axons (variables) to store information. Spike Timing Dependent Delay Plasticity is used to fine-tune and add dynamics to the network. We use a time multiplexing approach allowing us to achieve 4096 (4k) neurons and up to 1.15 million programmable delay axons on a Virtex 6 FPGA. Test results show that the proposed neural network is capable of successfully recalling more than 95% of all spikes for 96% of the stored patterns. The tests also show that the neural network is robust to noise from random input spikes.

  20. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Science.gov (United States)

    Zhang, Jie; Zhou, Dongming

    2015-01-01

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns.

  1. Time Delay Circuits: A Quality Criterion for Delay Variations versus Frequency

    NARCIS (Netherlands)

    Garakoui, Seyed Kasra; Klumperink, Eric A.M.; Nauta, Bram; Vliet, van Frank E.

    2010-01-01

    This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (fϕ=0) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of fϕ=0 for a single delay block

  2. FPGA Circuit Design Based on Xilinx ISE%基于Xilinx ISE平台的FPGA电路设计

    Institute of Scientific and Technical Information of China (English)

    于东阳; 苏彬

    2012-01-01

    Xilinx ISE is a tool set to design FPGA digital circuit. This tool set can make CPLD/FP-GA digital circuit layout facilely and fleetly. A calculate unit controlled by microinstruction is introduced to describe how to apply VHDL to designing FPGA circuit based on Xilinx.%Xilinx ISE集成综合环境是Xilinx公司的现场可编程逻辑器件数字电路开发工具集.其集成的工具可以使设计人员方便的完成CPLD/FPGA数字电路开发全过程.通过设计一个微指令控制的计算单元,描述基于ISE平台使用VHDL语言进行FPGA电路设计的原理和方法.

  3. Design of delay insensitive circuits using multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

    1992-01-01

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...... into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial...

  4. A new synchronization control circuit based on FPGA for the laser range-gated imaging system

    Science.gov (United States)

    He, Shan; Li, Li; Zhou, Yan

    2009-07-01

    Synchronization control is a kernel technique of the laser range-gated (LRG) imaging system which controls the synchronization of the pulsed laser and the ICCD camera directly. It can achieve range gating effectively and improve the resolution of image precisely. Conventional control circuits which are composed of discrete components have a poor performance of anti-interference, and the transmitting signal has a bad delay which affects the conventional circuit’s precision and stabilization seriously. To solve these problems, a range-gated synchronization control circuit is designed. This circuit, which takes the advantages of FPGA’s high compact and flexibility, uses the phase-locking-loop (PLL) to multiply the global clock frequency. This design improves the precision and stabilization greatly, makes the precision up to a nanosecond level and provides a real-time selection of the values of pulse width and delays. Experiments results indicate that this circuit has a high precise and stable range-gated pulse.

  5. Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

    Indian Academy of Sciences (India)

    S Jayanthy; M C Bhuvaneswari

    2015-02-01

    In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

  6. Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

    Directory of Open Access Journals (Sweden)

    Sumedh Dhabu

    2015-09-01

    Full Text Available This paper presents the design and FPGA implementation of interpolated continuously variable fractional delay structure based filter (ICVFD filter with fine control over the cutoff frequency. In the ICVFD filter, each unit delay of the prototype lowpass filter is replaced by a continuously variable fractional delay (CVFD element proposed in this paper. The CVFD element requires the same number of multiplications as that of the second-order fractional delay structure used in the existing fractional delay structure based variable filter (FDS based filter, however it provides fractional delays corresponding to the higher-order fractional delay structures. Hence, the proposed ICVFD filter provides wider cutoff frequency range compared to the FDS based filter. The ICVFD filter is also capable of providing variable bandpass and highpass responses. We use two-stage approach for the FPGA implementation of the ICVFD filter. First, we use pipelining stages to shorten the critical path and improve the operating frequency. Then, we make use of specific hardware resource, i.e. RAM-based Shift Register (SRL to further improve the operating frequency and resource usage.

  7. Synchronic, optical transmission data link integrated with FPGA circuits (for TESLA LLRF control system)

    Energy Technology Data Exchange (ETDEWEB)

    Zielinski, J.S.

    2006-07-15

    The X-ray free-electron laser X-FEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new possibilities for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated to the LLRF1 system in VUV FEL experiment It is being developed by the ELHEP2 group in the Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller to stabilize the vector sum of fields in cavities of one cryo-module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. The synchronic, optical link project was made for the accelerator X-FEL laser TESLA, the LLRF control system experiment at DESY, Hamburg. The control and diagnostic data is transmitted up to 2.5Gbit/s through a plastic fiber in a distance up to a few hundred meters. The link is synchronized once after power up, and never resynchronized when data is transmitted with maximum speed. The one way link bit error rate is less then 10{sup -15}. The transceiver component written in VHDL that works in the dedicated Altera registered Stratix registered GX FPGA circuit. During the work in the PERG laboratory a 2,5Gbit/s serial link with the long vector parallel interface transceiver was created. Long-Data-Vector transceiver transmits 16bit vector each 8ns with 120ns latency. (orig.)

  8. Efficient FPGA Implementation of High-Throughput Mixed Radix Multipath Delay Commutator FFT Processor for MIMO-OFDM

    Directory of Open Access Journals (Sweden)

    DALI, M.

    2017-02-01

    Full Text Available This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT processor implemented on Field Programmable Gate Arrays (FPGA for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM. The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively.

  9. Flash 型 FPGA 单粒子瞬态脉冲分段滤除电路设计%Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs

    Institute of Scientific and Technical Information of China (English)

    史方显; 曾立; 王淼; 曹建勋; 权妙静

    2016-01-01

    为提高 FPGA 在辐射环境条件下的抗单粒子脉冲(SET)的能力,设计了一种由多个延时单元和并联逻辑保护单元(Guard Gate,GG)构成的 SET 脉冲分段滤除电路.将 SET 脉冲处理延时减小至传统方法的10.42%~49.8%,从而提高电路对 SET 脉冲的处理能力,同时占用的逻辑资源未有明显增加.%A segmented filtering circuit with delay units and guard gates is proposed to filter SET pulses with different width,considering the range and distribution of SET pulse widths produced in FPGA and the propagation induced pulse broadening.Dividing the widths of SET pulses into several intervals,parallel guard gates with different delay buffers generate corresponding results to different intervals.According to the results,this circuit selects the output in the shortest time,improving the performance on dealing with SET pulses.Simulation results in Fusion family flash-based FPGA indicate that,compared to traditional methods,the segmented filtering circuit can cut the filtering delay of SET pulse in critical path down to 10.42%~49.8%,while power consumption decreasing and no hardware resource increase.

  10. Research on a High-Precision Delay Circuit in Data Acquisition Systems

    Institute of Scientific and Technical Information of China (English)

    MA Kai; SU Hong-qi; YANG Gong-xun

    2006-01-01

    This paper presents a novel precision delay circuit design for high-speed data acquisition systems. Many studies have suggested that various advanced electronic measurement apparatuses require that the delay circuit should have a high precision and a short delay interval. Practically, however, such measurement apparatuses are low in precision and long in delay interval at present. The structure and function of a data acquisition system is introduced first; then the principle of ramp-based precision delay circuits and the digitally programmable delay generator is studied and the precision delay circuit is designed. The authors also demonstrated 8-bit programmable delay circuits with a timing precision of 10 ps. Therefore the programmable precision delay circuit here presented has a higher precision, shorter interval and more detectable function than any other precision delay circuit.

  11. Recursive Delay Calculation Unit for Parametric Beamformer

    DEFF Research Database (Denmark)

    Nikolov, Svetoslav; Jensen, Jørgen Arendt; Tomov, Borislav Gueorguiev

    2006-01-01

    . The non-pipelined circuit occupies about 0.5 % of the FPGA resources and the pipelined one about 1 %. When the square root is found with a pipelined CORDIC processor, 2 % of the FPGA slices are used to deliver 150 million delays per second. © (2006) COPYRIGHT SPIE--The International Society for Optical...

  12. A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations

    Science.gov (United States)

    Takagi, Noboru

    Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

  13. SSTL I/O Standard Based Arithmetic Circuits Design on FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

    2016-01-01

    -Tiryagbhyam”. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. When we use SSTL135_R in place of SSTL12, SSTL12_DCI, SSTL15, and SSTL135_DCI, there is 42.5%, 82.7%, 28.12%, and 72.9% reduction in I/O power at 21oC, 40oC, 53.5oC and 56.7oC. This design is implemented on Artix-7 FPGA...

  14. Precise delay measurement through combinatorial logic

    Science.gov (United States)

    Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

    2010-01-01

    A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

  15. Serial Hardware Implementation of the MFCC and MLP Architecture on FPGA Circuit

    Directory of Open Access Journals (Sweden)

    KHAMLICH SALAH EDDINE

    2013-08-01

    Full Text Available Most audio processing algorithms require complex mathematical operations and a massive amount of data which are often performed in real time. Our robotic application requires complex algorithms such as MFCC, ANN (Artificial Neural Networks and voice database. It must therefore use a fast and efficient electronic system, for that we used a processor NIOSII based FPGA to implement materially MLP and perform voice recognition functions in real time. Moreover, it is now possible to modify the internal architecture of FPGAs to create one or more central processors (NIOSII. FPGAs now offer low-cost, flexible implementation, fast and convenient with a reduction in energy consumption for many digital systems which are based on NIOSII.

  16. Phased-Array Antenna Beam Squinting Related to Frequency Dependency of Delay Circuits

    NARCIS (Netherlands)

    Garakoui, S.K.; Klumperink, E.A.M.; Nauta, B.; Vliet, F.E. van

    2011-01-01

    Practical time delay circuits do not have a perfectly linear phase-frequency characteristic. When these delay circuits are applied in a phased-array system, this frequency dependency shows up as a frequency dependent beam direction (“beam squinting”). This paper quantifies beam squinting for a linea

  17. Delay modeling of bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) circuits

    Science.gov (United States)

    Yang, Andrew T.

    1986-08-01

    This report deals with the development of a delay-time model for timing simulation of large circuits consisting of Bipolar ECL(Emitter-Coupled Logic) and EFL (Emitter-Follower-Logic) networks. This model can provide adequate information on the performance of the circuits with a minimum expenditure of computation time. This goal is achieved by the use of proper circuit transient models on which analytical delay expressions can be derived with accurate results. The delay-model developed in this report is general enough to handle complex digital circuits with multiple inputs or/and multiple levels. The important effects of input slew rate are also included in the model.

  18. FPGA implementation of digital constant fraction algorithm with fractional delay for optimal time resolution

    Energy Technology Data Exchange (ETDEWEB)

    Jaeger, Markus, E-mail: jaeger@informatik.uni-leipzig.de [Faculty of Mathematics and Computer Science, University of Leipzig, PF 100920, 04009 Leipzig (Germany); Butz, Tilman, E-mail: butz@physik.uni-leipzig.de [Faculty of Physics and Earth Sciences, University of Leipzig, Linnestr. 5, 04103 Leipzig (Germany)

    2012-05-11

    In a recent development of a fully digital spectrometer for time differential perturbed angular correlations a true constant fraction trigger (CFT) algorithm was implemented that, however, allowed for integer delays, i.e. integer multiples of the sampling interval, only. With a sampling rate of 1 GS/s and BaF{sub 2} scintillators this turned out to be insufficient. Here, we present an extension of the algorithm to fractional delays implemented in field programmable gate arrays (FPGAs). Furthermore, we derive a criterion for the delay for optimum timing based on the steepest slope of the CFT signal. Experimental data are given for LaBr{sub 3}(Ce) scintillators and 511 keV-511 keV prompt coincidences that corroborate the theoretical result.

  19. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

    Directory of Open Access Journals (Sweden)

    Omnia S. Fadl

    2016-01-01

    Full Text Available Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

  20. A Low Power Linear Phase Programmable Long Delay Circuit.

    Science.gov (United States)

    Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, Alexander J

    2014-06-01

    A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

  1. Delay-area trade-off for MPRM circuits based on hybrid discrete particle swarm optimization

    Institute of Scientific and Technical Information of China (English)

    Jiang Zhidi; Wang Zhenhai; Wang Pengjun

    2013-01-01

    Polarity optimization for mixed polarity Reed-Muller (MPRM) circuits is a combinatorial issue.Based on the study on discrete particle swarm optimization (DPSO) and mixed polarity,the corresponding relation between particle and mixed polarity is established,and the delay-area trade-off of large-scale MPRM circuits is proposed.Firstly,mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO (HDPSO).Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model.Finally,the proposed algorithm is testified by MCNC Benchmarks.Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits.

  2. Synchronization transitions in coupled time-delay electronic circuits with a threshold nonlinearity.

    Science.gov (United States)

    Srinivasan, K; Senthilkumar, D V; Murali, K; Lakshmanan, M; Kurths, J

    2011-06-01

    Experimental observations of typical kinds of synchronization transitions are reported in unidirectionally coupled time-delay electronic circuits with a threshold nonlinearity and two time delays, namely feedback delay τ(1) and coupling delay τ(2). We have observed transitions from anticipatory to lag via complete synchronization and their inverse counterparts with excitatory and inhibitory couplings, respectively, as a function of the coupling delay τ(2). The anticipating and lag times depend on the difference between the feedback and the coupling delays. A single stability condition for all the different types of synchronization is found to be valid as the stability condition is independent of both the delays. Further, the existence of different kinds of synchronizations observed experimentally is corroborated by numerical simulations and from the changes in the Lyapunov exponents of the coupled time-delay systems.

  3. A systematic molecular circuit design method for gene networks under biochemical time delays and molecular noises

    Directory of Open Access Journals (Sweden)

    Chang Yu-Te

    2008-11-01

    Full Text Available Abstract Background Gene networks in nanoscale are of nonlinear stochastic process. Time delays are common and substantial in these biochemical processes due to gene transcription, translation, posttranslation protein modification and diffusion. Molecular noises in gene networks come from intrinsic fluctuations, transmitted noise from upstream genes, and the global noise affecting all genes. Knowledge of molecular noise filtering and biochemical process delay compensation in gene networks is crucial to understand the signal processing in gene networks and the design of noise-tolerant and delay-robust gene circuits for synthetic biology. Results A nonlinear stochastic dynamic model with multiple time delays is proposed for describing a gene network under process delays, intrinsic molecular fluctuations, and extrinsic molecular noises. Then, the stochastic biochemical processing scheme of gene regulatory networks for attenuating these molecular noises and compensating process delays is investigated from the nonlinear signal processing perspective. In order to improve the robust stability for delay toleration and noise filtering, a robust gene circuit for nonlinear stochastic time-delay gene networks is engineered based on the nonlinear robust H∞ stochastic filtering scheme. Further, in order to avoid solving these complicated noise-tolerant and delay-robust design problems, based on Takagi-Sugeno (T-S fuzzy time-delay model and linear matrix inequalities (LMIs technique, a systematic gene circuit design method is proposed to simplify the design procedure. Conclusion The proposed gene circuit design method has much potential for application to systems biology, synthetic biology and drug design when a gene regulatory network has to be designed for improving its robust stability and filtering ability of disease-perturbed gene network or when a synthetic gene network needs to perform robustly under process delays and molecular noises.

  4. 数字调制器载波产生电路的FPGA设计%Design of Digital Modulator Carrier Producing Circuit Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    雷能芳

    2011-01-01

    The common approach to implement Digital Modulator Carrier producing circuit on FPGA is based on a lookup table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of digital modulator carrier on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. The system was implemented in EP1C12Q240C8, and the hardware practical test was done by embedded logic analyzer SignalTap Ⅱ of Quartus Ⅱ. The correctness and feasibility of this design is verified by practical test result.%数字调制器载波产生电路的FPGA实现通常都是基于查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源去建立庞大的查找表.文中提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源,提高运算速度.电路在FPGA芯片EPIC12Q240C8上实现,并通过QuartusⅡ嵌入式逻辑分析仪SignalTapⅡ对硬件进行了实时测试,测试结果验证了设计的正确性及可行性.

  5. A Low-cost Optical Receiver Data Recovery Circuit Design and FPGA Implementation%一种低成本光接收器的数据恢复电路的设计及FPGA实现

    Institute of Scientific and Technical Information of China (English)

    宁少春

    2012-01-01

    Designed a FPGA programmable input delay unit(IDELAY) and phase-locked loop output combination with the frequency multi-phase clock four times over-sampling of high-speed clock and data recovery circuit.Recovery in the four parallel data at lower frequencies,effectively increase bandwidth and reduce the cost of the terminal,and automatically detect and determine the method detection data transition edge,eliminate the interference of data glitches.%设计了一种利用FPGA的可编程输入延时单元(IDELAY)和锁相环输出同频多相时钟结合的4倍过采样高速时钟数据恢复电路。可在较低频率同步恢复4位并行数据,有效地增大带宽并降低了终端成本,并采用自动检测和判断的方法检测数据跳变边沿,消除了数据毛刺的干扰。

  6. 低信噪比下互相关时延估计器的 FPGA 实现%FPGA Realization of Cross-correlation Time Delay Estimator under Low SNR

    Institute of Scientific and Technical Information of China (English)

    江雪; 刘源源; 雷维嘉; 谢显中

    2014-01-01

    The correlation method is a classical algorithm for time delay estimation(TDE). The time-do-main cross-correlation method can be used for integer and non-integer sample delay estimation. Even at low signal-to-noise ratio(SNR) environment,accurate and stable estimated results can be obtained with the more amount of data. In order to improve the resolution,this paper analyzes a correlation algorithm based on sinc function realizing non-integer sample delay,and draws the conclusion that this method has optimal performance by simulations and comparisons between no interpolation method,twice-interpolation method and sinc function method in terms of estimation accuracy and computation complexity. The im-proved cross-correlation estimator based on field programmable logic gate array(FPGA) can achieve accu-rate TDE under low SNR.%在时延估计算法中,相关法是一种经典的算法。时域互相关法可用来进行整数倍和非整数倍采样周期的时延估计,即使是在极低的信噪比(SNR)条件下,利用较多的数据也能获得准确和稳定的估计结果。为提高时延估计分辨率,给出了一种采用 sinc 函数对信号进行非整数倍采样周期延时的相关估计算法,通过仿真比较了未插值、两倍插值法和 sinc 函数延时法的估计精度和计算量,证明 sinc 函数延时法性能最优。基于现场可编程逻辑门阵列(FPGA)实现的改进型互相关时延估计器能够实现在低信噪比下时延差的准确估计。

  7. Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits

    Science.gov (United States)

    Maillard, Pierre

    The purpose of this PhD work has been to investigate, model, test, develop and provide hardening techniques and guidelines for the mitigation of single event transients (SETs) in analog mixed-signal (AMS) delay locked loops (DLLs) for radiation-hardened applications. Delay-locked-loops (DLLs) are circuit substructures that are present in complex ASIC and system-on-a-chip designs. These circuits are widely used in on-chip clock distribution systems to reduce clock skew, to reduce jitter noise, and to recover clock signals at regional points within a global clock distribution system. DLLs are critical to the performance of many clock distribution systems, and in turn, the overall performance of the associated integrated system; as such, complex systems often employ multiple DLLs for clock deskew and distribution tasks. In radiation environments such as on-orbit, these critical circuits represent at-risk points of malfunction for large sections of integrated circuits due to vulnerabilities to radiation-generated transients (i.e. single event transients) that fan out across the system. The analysis of single event effects in analog DLLs has shown that each DLL sub-circuit primitive is vulnerable to single event transients. However, we have identified the voltage controlled delay line (VCDL) sub-circuit as the most sensitive to radiation-induced single event effects generating missing clock pulses that increase with the operating frequency of the circuit. This vulnerability increases with multiple instantiation of DLLs as clock distribution nodes throughout an integrated system on a chip. To our knowledge, no complete work in the rad-hard community regarding the hardening of mixed-signal DLLs against single event effects (missing pulses) has been developed. Most of the work present in the literature applies the "brute force" and well-established digital technique of triple modular redundancy (TMR) to the digital subcomponents. We have developed two novel design

  8. Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

    OpenAIRE

    Mehrotra, Rashmi

    2013-01-01

    With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation o...

  9. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    Science.gov (United States)

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  10. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  11. FPGA Boot Loader and Scrubber

    Science.gov (United States)

    Wade, Randall S.; Jones, Bailey

    2009-01-01

    A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

  12. FPGA Trigger System to Run Klystrons

    Energy Technology Data Exchange (ETDEWEB)

    Gray, Darius; /Texas A-M /SLAC

    2010-08-25

    The Klystron Department is in need of a new trigger system to update the laboratory capabilities. The objective of the research is to develop the trigger system using Field Programmable Gate Array (FPGA) technology with a user interface that will allow one to communicate with the FPGA via a Universal Serial Bus (USB). This trigger system will be used for the testing of klystrons. The key materials used consists of the Xilinx Integrated Software Environment (ISE) Foundation, a Programmable Read Only Memory (Prom) XCF04S, a Xilinx Spartan 3E 35S500E FPGA, Xilinx Platform Cable USB II, a Printed Circuit Board (PCB), a 100 MHz oscillator, and an oscilloscope. Key considerations include eight triggers, two of which have variable phase shifting capabilities. Once the project was completed the output signals were able to be manipulated via a Graphical User Interface by varying the delay and width of the signal. This was as planned; however, the ability to vary the phase was not completed. Future work could consist of being able to vary the phase. This project will give the operators in the Klystron Department more flexibility to run various tests.

  13. GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

    Institute of Scientific and Technical Information of China (English)

    Lu Junming; Lin Zhenghui

    2002-01-01

    In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.

  14. The research of time-delay test methods based on FPGA%基于FPGA的时延测试方法研究

    Institute of Scientific and Technical Information of China (English)

    刘明波; 佘瑨; 周峰

    2011-01-01

    时延性能是信息传输系统中的一项重要指标,时延以及时延抖动等性能会直接影响传输系统的性能.介绍了几种基于FPGA的时延测试方法,对比了各种测试方法的特点,并运用VHDL语言,实现了其中的"脉冲沿"时延测试方法;利用Al-tera SignalTap技术,对脉冲式时延测试方法进行了验证.测试表明,系统占用资源少,工作稳定可靠,满足设计要求.%Time-delay is an important capability of information transferring system, which will directly affect the transmission performance of the system. Some time-delay test methods based on FPGA are introduced and are compared,then VHDL is used to achieve the‘ pulse edge’ time-delay test method. Altera SignalTap technology is used to verify this method. The test shows that the system takes up less resources and runs stably,which meets the design requirements.

  15. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  16. 一种适于FPGA芯片的SRAM单元及外围电路设计%A SRAM Cell and Control Circuits Design for FPGA

    Institute of Scientific and Technical Information of China (English)

    徐新宇; 徐玉婷; 林斗勋

    2014-01-01

    静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。%SRAM cell power contributes a key part of the whole chip power consumption, and the simulation of a large scale of SRAM will cost long time. In the paper, present a SRAM cell with low leakage current for FPGA based on 40 nm technology, and also design write/read control circuit for the cell. The simulation result shows that the cell which present works with lower leakage current than normal threshold voltage CMOS SRAM. In particular, build the behavioral model of the SRAM cell and the other driving circuits using the Verilog language for the convenient of the whole chip simulation.

  17. Estimation of leakage power and delay in CMOS circuits using parametric variation

    Directory of Open Access Journals (Sweden)

    Preeti Verma

    2016-09-01

    Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

  18. A twofold quantum delayed-choice experiment in a superconducting circuit.

    Science.gov (United States)

    Liu, Ke; Xu, Yuan; Wang, Weiting; Zheng, Shi-Biao; Roy, Tanay; Kundu, Suman; Chand, Madhavi; Ranadive, Arpit; Vijay, Rajamani; Song, Yipu; Duan, Luming; Sun, Luyan

    2017-05-01

    Wave-particle complementarity lies at the heart of quantum mechanics. To illustrate this mysterious feature, Wheeler proposed the delayed-choice experiment, where a quantum system manifests the wave- or particle-like attribute, depending on the experimental arrangement, which is made after the system has entered the interferometer. In recent quantum delayed-choice experiments, these two complementary behaviors were simultaneously observed with a quantum interferometer in a superposition of being closed and open. We suggest and implement a conceptually different quantum delayed-choice experiment by introducing a which-path detector (WPD) that can simultaneously record and neglect the system's path information, but where the interferometer itself is classical. Our experiment is realized with a superconducting circuit, where a cavity acts as the WPD for an interfering qubit. Using this setup, we implement the first twofold delayed-choice experiment, which demonstrates that the system's behavior depends not only on the measuring device's configuration that can be chosen even after the system has been detected but also on whether we a posteriori erase or mark the which-path information, the latter of which cannot be revealed by previous quantum delayed-choice experiments. Our results represent the first demonstration of both counterintuitive features with the same experimental setup, significantly extending the concept of quantum delayed-choice experiment.

  19. Optimization of FPGA-based Moore FSM

    Science.gov (United States)

    Barkalov, Aleksander; Titarenko, Larysa; Chmielewski, Sławomir

    2014-10-01

    A metod is proposed for hardware reduction in FPGA-based Moore FSM. It is based on using two sources of codes. It reduces the number of LUTs in the FSM circuit. The results of investigations are shown.

  20. Time delay along a chained lumped-circuits: for the physical analogy of half-wavelength power transmission lines

    Science.gov (United States)

    Zhan, Rongrong; Li, Yurong; Jiao, Chongqing; Yu, Yue; Meng, Jiangwen; Wang, Bei

    2017-09-01

    Half-wavelength AC power transmission (HWACT) technology is a kind of three-phase AC transmission technology, which can transmit electric power over a distance close to half power-frequency wavelength, i.e. 3000 km (50Hz) or 2500 km (60 Hz). In order to implement physical analogy of HWACT lines, in general, the equivalent lumped-circuits consisting of some chained π-type circuits or T-type circuits are used in laboratory. The number of the chained circuits is the most key parameter to establish good equivalence between the lumped-circuits and the transmission line. In this paper, the time delay of the chained circuits, which is defined as the time of a sine wave propagating from the sending end to the receiving end of the chained circuits, is calculated for different number of the chained circuits and different wave frequencies. Good equivalence requires the time delay equal to 10ms (the time of electromagnetic waves propagating along 3000km). It is shown that the time delay is dependent on the number of the chained circuits, as well as the wave frequency. For 50Hz, 4 chained π-type circuits can ensure that the relative error of the time delay is less than 2.6% and the sending-to-receiving voltage ratio is approximately 1. For frequencies below 400Hz, 30 chained π-type or T-type circuits can ensure that the relative error of the time delay is less than 3.2% and the sending-to-receiving voltage ratio is approximately 1. These works are instructive for the physical analogy of HWACT lines.

  1. Synthesis of RF Circuits with Negative Time Delay by Using LNA

    Directory of Open Access Journals (Sweden)

    Blaise Ravelo

    2013-02-01

    Full Text Available A demonstration of the negative time-delay by using active circuit topologies with negative group delay (NGD is described in this paper. This negative time delay is realized with two different topologies operating in base band and modulated frequencies. The first NGD topology is composed of an RL-network in feedback with an RF/microwave amplifier. Knowing the characteristics of the amplifier, a synthesis method of this circuit in function of the desired NGD values and the expected time advance is established. The feasibility of this extraordinary physical effect is illustrated with frequency- and time-domain analyses. It is shown in this paper that by considering an arbitrary waveform signal, output in advance of about 7 ns is observed compared to the corresponding input. It is stated that such an effect is not in contradiction with the causality. The other NGD topology is comprised of a microwave amplifier associated with an RLC-series resonant. The theoretical approach illustrating the functioning of this NGD circuit is established by considering the amplifier S-parameters. Then, synthesis relations enabling to choose the NGD device parameters according to the desired NGD and gain values are also established. To demonstrate the relevance of the theoretic concept, a microwave device exhibiting NGD function of about -1.5 ns at around 1.19 GHz was designed and analyzed. The NGD device investigated in this paper presents advantages on its faculty to exhibit positive transmission gain, the implementation of the bias network and matching in the considered NGD frequency band.

  2. Experimental confirmation of chaotic phase synchronization in coupled time-delayed electronic circuits.

    Science.gov (United States)

    Senthilkumar, D V; Srinivasan, K; Murali, K; Lakshmanan, M; Kurths, J

    2010-12-01

    We report the experimental demonstration of chaotic phase synchronization (CPS) in unidirectionally coupled time-delay systems using electronic circuits. We have also implemented experimentally an efficient methodology for characterizing CPS, namely, the localized sets. Snapshots of the evolution of coupled systems and the sets as observed from the oscilloscope confirming CPS are shown experimentally. Numerical results from different approaches, namely, phase differences, localized sets, changes in the largest Lyapunov exponents, and the correlation of probability of recurrence (C(CPR)) corroborate the experimental observations.

  3. GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

    Institute of Scientific and Technical Information of China (English)

    LuJunming; LinZhenghui

    2002-01-01

    In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.

  4. Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

    Institute of Scientific and Technical Information of China (English)

    WANG Youren; DENG Xiaoqian; CUI Jiang; YAO Rui; ZHANG Zhai

    2006-01-01

    The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines (SVM) classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

  5. 基于FPGA进位链TDC延时模型的建立与性能测试%Delay Model and Performance Testing for FPGA Carry Chain TDC

    Institute of Scientific and Technical Information of China (English)

    康晓文; 刘亚强; 崔均健; 杨章灿; 金永杰

    2011-01-01

    Time- of- flight (TOF) information would improve the performance of PET (positron emission tomography). TDC design is a key technique. It proposed Carry Chain TDG Delay model. Through changing the significant delay parameter of model, paper compared the difference of TDC performance, and finally realized Time- to- Digital Convertor (TDC) based on Carry Chain Method using FPGA EP2C20Q240C8N with 69 ps LSB, max error below 2 LSB. Such result could meet the TOF demand. It also proposed a Coaxial Cable Measuring method for TDC testing , without High - precision test equipment.%引入飞行时间信息,可以提高正电子断层显像仪(Positron Ernission Tomography,PET)系统的性能.电子学时间数字转换(TDC,Time-to-Digital Convertor)设计是其中一项关键技术.论文针对进位链(Carty Chain)TDC设计,建立了TDC的延时模型,推导了进位链TDC的延时公式.基于模型,通过调整关键信号的参数,比较了调整前后的TDC性能,在EP2C20Q240C8N芯片上实现和提升了进位链TDC的性能,最小测量间隔为69 ps,测量误差小于2 LSB,能够满足TOF测量时间精度的要求,并验证了模型公式的正确性.对TDC的测试方法选用高精度同轴电缆进行间接测量,解决了在缺乏ps级高精度测试设备情况下的时间精度测试问题.

  6. Design and Implementation of Multi-channel Data Acquisition Circuit Based on FPGA%基于FPGA的多通道数据采集电路的设计及实现

    Institute of Scientific and Technical Information of China (English)

    程惠; 任勇峰; 王强; 董小娜

    2013-01-01

    介绍了一个基于FPGA的多通道信号采集电路.该电路以FPGA芯片XC3S400作为电路的主控制器,采用电子开关ADG708对7路信号进行了循环采集,使用AD7667作为模数转换器,由主控制器FPGA控制,将采集到的模拟信号转换为数字信号.然后,通过单片机CY7C68013与上位机通信,将采集到的信号通过上位机软件读出并画图显示.通过试验已验证了该采集电路的功能的有效性.%An FPGA-based multi-channel signal acquisition circuit is introduced.The FPGA chip XC3S400 is designed as the main controller in the circuit,and ADG708 as the electronic switch which is to collect seven signals circulating,AD7667 used as ADC,control by the host controller FPGA,the collected analog signal is converted to digital signal.Then,through the communication of the CY7C68013 and computer,the collected signal is read and displayed on the computer screen.At the present,a series of test has done to verify the correctness of this acquisition circuit.

  7. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  8. Design and Implementation of the Digital Detection Circuit for RFOG Based on a Single FPGA%基于单片FPGA的谐振式光纤陀螺数字系统设计与实现

    Institute of Scientific and Technical Information of China (English)

    姚灵芝; 马慧莲; 金仲和

    2011-01-01

    谐振式光纤陀螺( Resonator Fiber Optic Gyro,RFOG)是基于Sagnac效应产生的谐振频率差来测量旋转角速度的一种新型光学传感器,在小型化和集成化方面具有明显优势.相比于传统的模拟检测技术,数字检测技术具有稳定性好、抗干扰能力强、处理速度快和体积小、易于集成等优势.本文设计了基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的数字RFOG系统,在单片FPGA上实现了基于比例积分控制的谐振频率伺服回路、相位调制器复位电压漂移补偿回路和第二闭环反馈控制回路.最后将研制的基于单片FPGA的闭环数字检测电路应用于实际RFOG系统,验证了上述功能,并实际检测了陀螺信号.%Resonator fiber optic gyro ( RFOG) is a late-model optical sensor to measure rotation velocity, of which resonant frequency is changed through the Sagnac effect. Compared with the traditional analogue circuit, the detection system based on a digital circuit has advantages of high stability, strong anti-interference ability and swift signal processing, small size and easy integration. A digital RFOG based on FPGA is set up. The resonant frequency servo loop based on the proportion integration controller and the automatic compensation circuits for voltage drift of the phase modulator, as well as the second closed-loop are all realized with a single FPGA. Applying the digital detection circuit with the closed-loop operation to the RFOG system,the functions of the FPGA are verified experimentally. On this basis, the gyro rotation signal is observed successfully.

  9. Emergent bimodality and switch induced by time delays and noises in a synthetic gene circuit

    Science.gov (United States)

    Zhang, Chun; Du, Liping; Xie, Qingshuang; Wang, Tonghuan; Zeng, Chunhua; Nie, Linru; Duan, Weilong; Jia, Zhenglin; Wang, Canjun

    2017-10-01

    Based on the kinetic model for obtaining emergent bistability proposed by Tan et al. (2009), the effects of the fluctuations of protein synthesis rate and maximum dilution rate, the cross-correlation between two noises, and the time delay and the strength of the feedback loop in the synthetic gene circuit have been investigated through theoretical analysis and numerical simulation. Our results show that: (i) the fluctuations of protein synthesis rate and maximum dilution rate enhance the emergent bimodality of the probability distribution phenomenon, while the cross-correlation between two noises(λ), the time delay(τ) and the strength of the feedback loop(K) cause it to disappear; and (ii) the mean first passage time(MFPT) as functions of the noise strengths exhibits a maximum, this maximum is called noise-delayed switching (NDS) of the high concentration state. The NDS phenomenon shows that the noise can modify the stability of a metastable system in a counterintuitive way, the system remains in the metastable state for a longer time compared to the deterministic case. And the τ and the K enhances the stability of the ON state. The physical mechanisms for the switch between the ON and OFF states can be explained from the point of view of the effective potential.

  10. On-Chip Built-in Jitter Measurement Circuit for PLL Based on Duty-Cycle Modulation Vernier Delay Line

    Institute of Scientific and Technical Information of China (English)

    YU Fei; Chung Len Lee; ZHANG Jingkai

    2007-01-01

    Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.

  11. Internal interface: I/O communication with FPGA circuits and hardware description standard for applications in HEP and FEL electronics ver. 1.0

    Energy Technology Data Exchange (ETDEWEB)

    Pozniak, K.T. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems ELHEP Laboratory

    2005-07-01

    The work describes hardware layer of the universal, parameterized communication interface for application in the FPGA chips. The interface is called in this work as the ''Internal Interface'' or in short the ''II''. The paper shows how to automatically create the address and data space, according to the user declarations. The methods to standardize the I/O communication with FPGA chips are described. The communication uses library functions and standardized, parametric components in VHDL. Theoretical background and technical description of the Internal Interface are illustrated with a few easy examples of simple interfaces. (orig.)

  12. FPGA implementation of image enhancement techniques

    Science.gov (United States)

    Kumar, Karan; Jain, Aditya; Srivastava, Atul Kumar

    2009-06-01

    The objective of this paper is designing, modeling, simulation and synthesis of four Image Enhancement techniques on FPGA. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel. Algorithms of all the techniques are studied and hardware circuits are realized for them. Then hardware logic is modeled in Matlab Simulink using Xilinx System Generator Block set and synthesized onto Virtex4 xc4vsx35-10ff668 FPGA chip. Using hardware co-simulation feature of FPGA kit, the algorithms developed are validated.

  13. 数字基带预失真系统中环路延迟估计的FPGA实现%An FPGA implementation of loop delay estimation in digital predistortion system

    Institute of Scientific and Technical Information of China (English)

    刘正平; 夏威; 何子述

    2011-01-01

    基于FPGA芯片Stratix Ⅱ EP2S60F672C4设计实现了数字基带预失真系统中的环路延迟估计模块.该模块运用了一种环路延迟估计新方法,易于FPGA实现.同时,在信号失真的情况下也能给出正确的估计结果.Modelsim SE 6.5c的时序仿真结果和SignalTaps Ⅱ的硬件调试结果验证了模块的有效性.%Based on FPGA chip Stratix II EP2S60F672C, this paper designed and implemented a loop-delay estimation model in predistortion system. This model used a novel method of estimate the loop-delay, which is easy to implement in FPGA, and can give the right loop - delay estimation value under the condition of signal distortion. The timing simulation result of Modelsim SE 6.5c and hardware debugging result of SignalTap II verified the valid of the model designed in this paper.

  14. DP-FPGA: An FPGA Architecture Optimized for Datapaths

    Directory of Open Access Journals (Sweden)

    Don Cherepacha

    1996-01-01

    Full Text Available This paper presents a new Field-Programmable Gate Array (FPGA architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.

  15. Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

    Directory of Open Access Journals (Sweden)

    Srilata Raman

    1996-01-01

    Full Text Available In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

  16. FPGA adders: performance evaluation and optimal design

    OpenAIRE

    Xing, S.; Yu, WWH

    1998-01-01

    Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.

  17. FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2016-01-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

  18. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  19. Note: Wide-range and high-resolution on-chip delay measurement circuit with low supply-voltage sensitivity for SoC applications

    Science.gov (United States)

    Sheng, Duo; Hung, Yu-Chan

    2016-11-01

    This paper presents an on-chip delay measurement (OCDM) circuit with a wide delay-measurement range, a high delay-measurement resolution and low supply-voltage sensitivity for efficient detection, and diagnosis in the high-performance system-on-chip (SoC). The proposed cascade-stage measurement structure can simultaneously achieve a delay-measurement range of several nanoseconds and a quantization resolution of several picoseconds. The proposed delay-measurement circuit has a high immunity to supply voltage variations without any additional calibration or self-biasing circuit. The delay-measurement range is 5.25 ns with 6 ps resolution; and the average delay resolution variation is 0.41% with ±10% supply voltage variations.

  20. Intelligent FPGA Data Acquisition Framework

    Science.gov (United States)

    Bai, Yunpeng; Gaisbauer, Dominic; Huber, Stefan; Konorov, Igor; Levit, Dmytro; Steffen, Dominik; Paul, Stephan

    2017-06-01

    In this paper, we present the field programmable gate arrays (FPGA)-based framework intelligent FPGA data acquisition (IFDAQ), which is used for the development of DAQ systems for detectors in high-energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in very high speed integrated circuit hardware description language, which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of Serializer/Deserializer (SERDES)-based time-to-digital conversion channels, an interface to a multichannel 80-MS/s 10-b analog-digital conversion, data transmission, and synchronization protocol between FPGAs, event builder, and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front end and data concentrator. This modular design also helps to scale and adapt the DAQ system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the drift chambers and the electromagnetic calorimeters (ECALs) of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this paper.

  1. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  2. The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

    Institute of Scientific and Technical Information of China (English)

    骆祖莹; 闵应骅; 杨士元; 李晓维

    2002-01-01

    The authors theoretically describe the monotonic increasing relationship between averagepowers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, whichcan be fast computed, has been used as the evaluation criterion for the power of a practical circuit withdelay, which needs more computing time, in such fields as fast estimation for the average power and themaximum power, and fast optimization for the Iow test power. The authors propose a novel simulationapproach that uses delay-free power to compact a long input vector pair sequence into a short sequenceand then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. Incomparison with the traditional simulation approach that uses an un-compacted input sequence to simu-late the average (or maximum) power, experiment results demonstrate that in the field of fast estimationfor the average power, the present approach can be 6-10 times faster without significant loss in accuracy(less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach canbe 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast op-timization for the test power, the authors propose a novel delay-free power optimization approach for thetest power. Experiment results demonstrate that, in comparison with the approach of direct optimizationand the approach of Hamming distance optimization, this approach is of the highest optimization effi-ciency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% testpower).

  3. ADC and TDC implemented using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Hansen, Sten; Shi, Zonghan; /Fermilab

    2007-11-01

    Several tests of FPGA devices programmed as analog waveform digitizers are discussed. The ADC uses the ramping-comparing scheme. A multi-channel ADC can be implemented with only a few resistors and capacitors as external components. A periodic logic levels are shaped by passive RC network to generate exponential ramps. The FPGA differential input buffers are used as comparators to compare the ramps with the input signals. The times at which these ramps cross the input signals are digitized by time-to-digital-converters (TDCs) implemented within the FPGA. The TDC portion of the logic alone has potentially a broad range of HEP/nuclear science applications. A 96-channel TDC card using FPGAs as TDCs being designed for the Fermilab MIPP electronics upgrade project is discussed. A deserializer circuit based on multisampling circuit used in the TDC, the 'Digital Phase Follower' (DPF) is also documented.

  4. FPGA-specific decimal sign-magnitude addition and subtraction

    Science.gov (United States)

    Vázquez, Martín; Todorovich, Elías

    2016-07-01

    The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten's complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.

  5. An Full-flow Verification Method of Asynchronous CircuitBased on FPGA%一种异步电路设计的FPGA全流程验证方法

    Institute of Scientific and Technical Information of China (English)

    王康; 黄乐天; 李广军

    2014-01-01

    以往异步电路在FPGA上的设计验证采用 HDL设计的M uller门搭建电路,在实现时需要手动布局布线来完成时序约束,设计繁琐复杂。对此完善了异步电路设计平台Balsa与FPGA设计工具相结合的设计验证流程,采用四相双轨延迟不敏感的握手协议,避免了手动布局布线的繁琐步骤。同时,在不同FPGA平台间具有良好的可移植性。重点设计了遵循异步握手协议的输入电路,完成了行为级到板级的全流程设计及验证。%Asynchronous circuit was designed and verified by the Muller gate designed by HDL on FPGAs previously ,and it was implemented with manual P&R to accomplish timing constraint ,which is so complex .In this paper ,the flow combining Balsa asynchronous circuits design platform and Xilinx FPGA P&R tools was perfected . The four phase dual-track handshake protocol was used to avoid the complex flow of manual P&R and this design has well performance of transplant . This paper focused on the design of the input circuit which follows the asynchronous handshake protocol and completed a behavioral level to board-level design and verification of the whole process .

  6. The Direction Measurement Circuit Based on FPGA for Yangbajing Muon Telescope%羊八井Muon望远镜中基于FPGA的方向测量电路

    Institute of Scientific and Technical Information of China (English)

    余杰; 李铁辉; 王辉; 张吉龙

    2009-01-01

    方向测量电路在羊八井Muon望远镜中用于测定Muon粒子的入射方向.该望远镜由上下相隔一定距离两层6X4排列的塑料闪烁体探测器阵列构成,能探测77个Muon粒子的入射方向及各个方向入射粒子计数率.能监测记录到高计数率、窄脉宽的输入信号以及极短的死时间是Muon望远镜对方向探测电路的要求.借助资源丰富、高速的FPGA,在单个芯片上实现了Muon望远镜方向探测电路所要求的全部功能.此外由于FPGA提供在线编程,使得对系统的功能修改或升级非常方便.低功耗是基于FPGA的方向测量电路的另一大优势.

  7. Pipelined Viterbi Decoder Using FPGA

    Directory of Open Access Journals (Sweden)

    Nayel Al-Zubi

    2013-02-01

    Full Text Available Convolutional encoding is used in almost all digital communication systems to get better gain in BER (Bit Error Rate, and all applications needs high throughput rate. The Viterbi algorithm is the solution in decoding process. The nonlinear and feedback nature of the Viterbi decoder makes its high speed implementation harder. One of promising approaches to get high throughput in the Viterbi decoder is to introduce a pipelining. This work applies a carry-save technique, which gets the advantage that the critical path in the ACS feedback becomes in one direction and get rid of carry ripple in the “Add” part of ACS unit. In this simulation and implementation show how this technique will improve the throughput of the Viterbi decoder. The design complexities for the bit-pipelined architecture are evaluated and demonstrated using Verilog HDL simulation. And a general algorithm in software that simulates a Viterbi Decoder was developed. Our research is concerned with implementation of the Viterbi Decoders for Field Programmable Gate Arrays (FPGA. Generally FPGA's are slower than custom integrated circuits but can be configured in the lab in few hours as compared to fabrication which takes few months. The design implemented using Verilog HDL and synthesized for Xilinx FPGA's.

  8. Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

    2014-05-15

    The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

  9. A new FPGA architecture suitable for DSP applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-05-15

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  10. FPGA Implementation of Wave Pipelining CORDIC Algorithms

    Institute of Scientific and Technical Information of China (English)

    CUI Wei

    2008-01-01

    The implementation of the coordinate rotational digital computer (CORDIC) algorithm with wave pipelining technique on field programmable gate array (FPGA) is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330MHz, which is a little lower than the speed of 336MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.

  11. Cycle slipping in nonlinear circuits under periodic nonlinearities and time delays

    NARCIS (Netherlands)

    Smirnova, Vera; Proskurnikov, Anton; Utina, Natalia V.

    2014-01-01

    Phase-locked loops (PLL), Costas loops and other synchronizing circuits are featured by the presence of a nonlinear phase detector, described by a periodic nonlinearity. In general, nonlinearities can cause complex behavior of the system such multi-stability and chaos. However, even phase locking ma

  12. Optoelectronic date acquisition system based on FPGA

    Science.gov (United States)

    Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

    2015-11-01

    An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

  13. Graph theory for FPGA minimum configurations

    Institute of Scientific and Technical Information of China (English)

    Ruan Aiwu; Li Wenchang; Xiang Chuanyin; Song Jiangmin; Kang Shi; Liao Yongbo

    2011-01-01

    A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations.This method is limited ifa large number of LUTs and multiplexers are presented.Since graph theory has been extensively applied to circuit analysis and test,this paper focuses on the modeling FPGA configurations.In our study,an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph,respectively.A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB.Based on the proposed modeling approach and exhaustive analysis,the minimum configuration numbers for CLB and IOB are five and three,respectively.

  14. A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2001-01-01

    A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing...... integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters....... The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system. A prototype...

  15. Design of Ultrasonic Phased Array Transmission System Based on FPGA%基于 FPGA 的超声相控阵发射系统设计

    Institute of Scientific and Technical Information of China (English)

    崔娟; 王红亮; 何常德; 薛晨阳

    2015-01-01

    In order to enhance the ultrasonic signal phased array transmission of underwater ultrasonic imaging system,the ul-trasonic phased array transmission system based on FPGA was designed.The transmission principle of phased focus was analyzed, and the eight channel ultrasonic phased array transmission system was achieved by using FPGA with rich I/ O pins and internal log-ic resources.Then the signal conditioning circuit for excitation signal D/ A conversion and amplification were designed to motivate the piezoelectric transducer effectively.The actual test results show that the system realizes ultrasonic signal phased array focus transmission,and the phase delay precision is 2. 5 ns.The system is with high integration and stable transmission,and it can be ap-plied to the underwater ultrasonic imaging implementation.%为了实现水下超声成像系统中超声信号的相控阵发射,提出并设计了一种基于 FPGA 的超声相控阵发射系统。分析了相控聚焦的发射原理,利用 FPGA 丰富的 I/ O 引脚和内部逻辑资源实现了八通道超声相控阵激励信号的发射,并设计了信号调理电路对激励信号进行 D/ A 转换及放大,以有效驱动压电换能器。通过实验测试表明,该系统可以实现超声信号的相控聚焦发射,相控延时精度达到2.5 ns,发射信号稳定,系统集成度高,可以应用于水下超声成像的实现。

  16. A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

    Science.gov (United States)

    Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

    2016-11-01

    In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

  17. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  18. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  19. Architecture Analysis of an FPGA-Based Hopfield Neural Network

    Directory of Open Access Journals (Sweden)

    Miguel Angelo de Abreu de Sousa

    2014-01-01

    Full Text Available Interconnections between electronic circuits and neural computation have been a strongly researched topic in the machine learning field in order to approach several practical requirements, including decreasing training and operation times in high performance applications and reducing cost, size, and energy consumption for autonomous or embedded developments. Field programmable gate array (FPGA hardware shows some inherent features typically associated with neural networks, such as, parallel processing, modular executions, and dynamic adaptation, and works on different types of FPGA-based neural networks were presented in recent years. This paper aims to address different aspects of architectural characteristics analysis on a Hopfield Neural Network implemented in FPGA, such as maximum operating frequency and chip-area occupancy according to the network capacity. Also, the FPGA implementation methodology, which does not employ multipliers in the architecture developed for the Hopfield neural model, is presented, in detail.

  20. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  1. Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)

    Science.gov (United States)

    Ceylan, Omer; Shafique, Atia; Burak, Abdurrahman; Caliskan, Can; Yazici, Melik; Abbasi, Shahbaz; Galioglu, Arman; Kayahan, Huseyin; Gurbuz, Yasar

    2016-11-01

    This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8 Me- while achieving quantization noise of 198 e- and power consumption of 14.35 mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90 × 8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51 dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays.

  2. Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

    Science.gov (United States)

    Won, Jun Yeon; Kwon, Sun Il; Yoon, Hyun Suk; Ko, Guen Bae; Son, Jeong-Whan; Lee, Jae Sung

    2016-02-01

    This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS.

  3. Bus Pneumatic Braking Circuit Delay Analysis and Control%客车气压制动时延分析及其控制研究

    Institute of Scientific and Technical Information of China (English)

    覃涛; 李刚炎; 涂鸣; 吴婷

    2012-01-01

    A bus pneumatic braking circuit delay control method is proposed in this research. Considering the delay characteristics of bus pneumatic braking circuit, the mathematical model of bus pneumatic braking circuit was established. The simulation models were built using Matlab/ Simulink and advanced modeling environment for simulation of engineering ( AMESim) software, respectively. The bus pneumatic braking circuit delay characteristic was analyzed by the combination methods of theoretical deduction and simulation experiments. Based on close-loop feedback control theory, the method to control bus pneumatic braking circuit delay was proposed. The delay controller was designed using PID control algorithm and the comparison between the results of experiment and simulation was implemented. Simulation shows that the designed delay controller could reduce delay effectively and it could be a good support for developing the bus pneumatic braking control system.%提出了一种客车气压制动时延控制方法.考虑到客车气压制动系统的延时特性,建立了客车气压制动回路的数学模型,运用Matlab/Simulink和AMESim软件分别建立了其仿真模型,采用理论分析与仿真实验相结合的方法,分析了客车气压制动的时延特性;基于闭环反馈控制理论,提出了客车气压制动回路时延控制方法.运用PID控制算法设计了时延控制器,并进行了对比仿真.仿真结果表明,进行时延控制后,客车的制动时延为0.3s,制动距离缩短1.8m,提高了客车的制动稳定性.

  4. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  5. Design and Implementations of Linear Congruential Generator into FPGA

    Directory of Open Access Journals (Sweden)

    Zulfikar

    2014-07-01

    Full Text Available This paper exposes circuit design of linear congruential generator (LCG and implementation in FPGA. The circuit is derived from LCG algorithm proposed by Lehmer. Wordlengths reduction technique has been used to simplify the circuit. Several nets connection among the blocks of the circuit are ignored or disconnected. Simulation either behavior or timing have been done successfully. Four best Xilinx chips are chosen to gather comparison data of maximum speed and area occupied. Kintex 7 is the fastest chip among all it is about 309 MHz and Spartan 6 is slowest one which is only 73 MHz. The area occupied is similar among all of the selected chips.

  6. Traffic Light Controller Using Fpga

    Directory of Open Access Journals (Sweden)

    D.Bhavana

    2015-04-01

    Full Text Available The traffic light sequence works on the specific switching of Red, Green and Yellow lights in a particular way with stipulated time form. The normal function of traffic lights requires sophisticated control and coordination to ensure that traffic moves as smoothly and safely as possible and that pedestrians are protected when they cross the roads [1] .This Traffic Light sequence is generated using a specific switching mechanism which will help to control a traffic light system on a road in a specified sequence. This paper focuses on the fact that the traffic lights can be varied in the day and night mode depending on the intensity of the traffic. It plays a vital role in supervising and running the metropolitan traffic and evade the possibilities of any unfortunate mishaps happening in and around the cities. It is a sequential machine to be scrutinized as per the requirements and programmed through a multistep development process. The methods that are used in this project are proposing the circuit, write a code, simulate, synthesis and implement on the hardware [8] . In this project, XILINX Software was chosen to devise a schematic using schematic edit, write a code using Verilog HDL (Hardware Description Language text editor and implements the circuit on Programmable Logic Device [PLD].The system has been successfully tested and implemented in hardware using Nexys 2 Digilent FPGA.

  7. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  8. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  9. DYNAMIC LABELING BASED FPGA DELAY OPTIMIZATION ALGORITHM

    Institute of Scientific and Technical Information of China (English)

    L; Zong-wei(

    2001-01-01

    [1]Puntambekar N V, Jablokow A G, Sommer H J. Unified review of 3D model generation for reverse engineering[J]. Computer Integrated Manufacturing System,1994,7(4):259~268.[2]Chikofsky E J. Reverse engineering and design recovery: a taxonomy[J]. IEEE Software,1990,6(3):13~17.[3]Chou Hon-yue. Application of reverse engineering in die and mold manufacturing[A]. 3rd Int Conf on Mould & Die Technique in Asia[C]. Taibei, China,1995.753~764.[4]Dipl-Ing Thomas Haller. Rapid mould and die making using reverse engineering and rapid prototyping[A]. 3rd Int Conf on Mould & Die Technique in Asia[C]. Taibei, China,1995.739~752.[5]Abella R J, Daschbach J M. Reverse engineering industrial applications[J]. Computers Ind Engng,1994,26(2):381~385.[6]Chen Y D, Tang X J. Automatic digitization of freeform curves by coordinate measuring machines[J]. ASME PED,1992,62:113~125.[7]Antonie van Rensburg. Implementing IDEF techniques as simulation modeling specifications[J]. Computers Ind Engng,1994,29(1-4):467~571.[8]Eastma C M, Fereshetian N. Informaiton models for use in product design: a comparison[J]. Computer-Aided Design.1994,26(7):551~572.

  10. Design of a FPGA based ABWR feedwater controller

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hsuanhan; Chou, Hwaipwu; Lin, Chaung [Dept. of Institute of Nuclear Engineering and Science, National Tsing Hua University, Hsinchu (China)

    2012-05-15

    A feedwater controller targeted for an ABWR has been implemented using a modern field programmable gate array (FPGA), and verified using the full scope simulator at Taipower's Lungmen nuclear power station. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulation model of the simulator was employed for verification and validation of the controller design under various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy logic control algorithm is a flexible yet feasible approach for feedwater controller design in nuclear power plant applications.

  11. Design of A FPGA Based ABWR Feedwater Controller

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hsuan Han; Chou, Hwai Pwu; Lin, Chaung [National Tsing Hua University, Hsinchu (China)

    2011-08-15

    A feedwater controller for the Taipower's Lungmen nuclear power station has been implemented using the modern field programmable gate array (FPGA) and verified using a full scope engineering simulator. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulator was employed for the verification and validation of the controller design with various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy control algorithm is a flexible yet feasible approach for controller design in nuclear power plant applications.

  12. Analysis of the effects of time delay in clock recovery circuits based on Phase-locked loops

    DEFF Research Database (Denmark)

    Zibar, Darko; Oxenløwe, Leif Katsuo; Clausen, Anders

    2004-01-01

    , are investigated by numerical simulations. Furthermore, simple expressions governing the stability properties of the loop, in the presence of time delay, are derived. For this purpose, three standard loop filters are considered: a Pl filter, a low pass (LP) filter and an active lag (AL) filter. The derived......Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain...

  13. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  14. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  15. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  16. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  17. FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Hauck, Scott; Lewellen, Thomas K; Miyaoka, Robert S

    2009-10-24

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex digital signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a series of high-resolution, small-animal PET scanners that utilize FPGAs as the core of the front-end electronics. For these next generation scanners, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report how we utilize the reconfigurable property of an FPGA to self-calibrate itself to determine pulse parameters necessary for some of the pulse processing steps. Specifically, we show how the FPGA can generate a reference pulse based on actual pulse data instead of a model. We also report how other properties of the photodetector pulse (baseline, pulse length, average pulse energy and event triggers) can be determined automatically by the FPGA.

  18. FPGA realization of multi-scroll chaotic oscillators

    Science.gov (United States)

    Tlelo-Cuautle, E.; Rangel-Magdaleno, J. J.; Pano-Azucena, A. D.; Obeso-Rodelo, P. J.; Nunez-Perez, J. C.

    2015-10-01

    Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua's circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK.

  19. An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

    Science.gov (United States)

    Mandal, Swagata; Saini, Jogender; Zabołotny, Wojciech M.; Sau, Suman; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2017-03-01

    Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

  20. A FPGA-Based Integrated Controller for Liquid Crystal Display%基于FPGA的液晶控制器设计

    Institute of Scientific and Technical Information of China (English)

    汪金辉; 张健; 宫娜; 吴武臣; 董利民

    2008-01-01

    介绍了一种基于 FPGA 的集成液晶控制器.系统由显示模块和控制模块组成,显示模块(LEM101)为10 bit 多功能通用型器件,内含看门狗(WDT)/时钟发生器,2 种频率的蜂鸣驱动电路,内置显示RAM,及3-4线串行接口.控制器基于1.5万门 FPGA 芯片(Xilinx XC3S1500),易于扩展和升级.利用 Verilog 语言,在 FPGA 芯片中实现了控制模块的设计,通过 GR-XC3S-1500 开发板验证,本设计完全满足对液晶模块的控制要求,并成功应用于光栅测量显示控制系统中.控制模块由四部分组成:存储、译码、串并转换器、输出控制.文章讨论了设计方法和设计过程,给出了部分 Verilog 代码.此外,本设计还创造性地在电源和 FPGA 芯片间插入低成本元件,满足了液晶上电后,初始化命令的延迟要求,从而节约了 FPGA 的硬件资源.%This paper presents a FPGA-based integrated controller for liquid crystal display system. The system consists of a display module and a controlling module. The former (LCM101 chip) is 10 bit multi-functional device with a WDT(watch dog timer), a dual frequency driving circuit, a display RAM and seri-al interface. The later is an integrated display controller using a FPGA chip of 1. 5million gate (Xilinx XC3S1500), so being easy to extend and upgrade. Integrated controller design in FPGA chip has been im-plemented by using Verilog language coding and verified in Xilinx Development Board. The design fits the requirements to control liquid crystal display entirely, and is successfully applied in a grating measurement system. The controller module includes four parts: storage, decoding, serial-parallel interface translation,and output controlling. This paper discusses the design method and the design process of each part above,providing Verilog codes partly. What's more a low-cost accessory is originally located between FPGA chip and power supply in hardware design to satisfy delay after liquid crystal electrify

  1. High Speed Fault Injection Tool Implemented With Verilog HDL on FPGA for Testing Fault Tolerance Designs

    Directory of Open Access Journals (Sweden)

    G. Gopinath Reddy

    2013-11-01

    Full Text Available This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an Open RISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEUfaults were injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure simulation-based fault injection with only 2.5% FPGA area overhead.

  2. Design and implementation of a low-cost FPGA-Based bioimpedance measurement system

    OpenAIRE

    González Gutiérrez, Miguel

    2014-01-01

    Currently, many impedance measurement systems have been developed. This project details the design, implementation and characterization of a FPGA-based bioimpedance measurement system, whose goal is obtaining good performance at low costs. Signal generation and processing circuits were implemented within the FPGA, as well as the NIOS II embedded processor. An ADA conversion board as well as a front-end previously designed and implemented by the group of instrumentation and biomedical engineer...

  3. A new pulse width signal processing with delay-line and non-linear circuit (for ToT)

    Energy Technology Data Exchange (ETDEWEB)

    Orita, Tadashi, E-mail: orita@sophie.q.t.u-tokyo.ac.jp [Department of Nuclear Engineering and Management, Graduate School of Engineering, University of Tokyo (Japan); Takahashi, Hiroyuki; Shimazoe, Kenji; Fujiwara, Takeshi; Boxuan, Shi [Department of Nuclear Engineering and Management, Graduate School of Engineering, University of Tokyo (Japan)

    2011-08-21

    Traditional pulse-height-analysis systems suffer from the complexity arising from ADC circuits. In particular, it is difficult to be applied to a large format array of pixilated detectors. Each channel of such an energy resolving multichannel system must be low power consumption and therefore it must be composed of simple circuits. The time-over-threshold (ToT) method provides an inexpensive way in such a system. However, ToT method suffers from a poor linearity. We now propose a method to improve the linearity with the dynamic time-over-threshold method that relies on a dynamic threshold voltage and the trapezoidal shaping method.

  4. Impaired executive control and reward circuit in Internet gaming addicts under a delay discounting task: independent component analysis.

    Science.gov (United States)

    Wang, Yifan; Wu, Lingdan; Zhou, Hongli; Lin, Xiao; Zhang, Yifen; Du, Xiaoxia; Dong, Guangheng

    2017-04-01

    This study utilized independent component analysis to explore the abnormal functional connectivity (FC) in male participants with Internet gaming disorder (IGD). Functional magnetic resonance imaging and behavioral data were collected from 21 healthy controls (HC) and 18 IGD patients when they were performing a delay discounting task. Behavioral results revealed that the IGD patients showed higher delay discounting rates than HC. Two networks were found to be associated with IGD: (1) the executive control network containing the anterior cingulate cortex and the medial and superior frontal gyrus, and (2) the basal ganglia network containing the lentiform nucleus. Comparing to HC, IGD exhibited stronger FC when selecting small and now options. In addition, the delay discounting rates were positively correlated with the modulation of the two networks and the reaction time. The results suggested that the IGD patients have enhanced sensitivity to reward and decreased ability to control their impulsivity effectively, which leads to myopic decision making.

  5. Implementation of large kernel 2-D convolution in limited FPGA resource

    Science.gov (United States)

    Zhong, Sheng; Li, Yang; Yan, Luxin; Zhang, Tianxu; Cao, Zhiguo

    2007-12-01

    2-D Convolution is a simple mathematical operation which is fundamental to many common image processing operators. Using FPGA to implement the convolver can greatly reduce the DSP's heavy burden in signal processing. But with the limit resource the FPGA can implement a convolver with small 2-D kernel. In this paper, An FIFO type line delayer is presented to serve as the data buffer for convolution to reduce the data fetching operation. A finite state machine is applied to control the reuse of multipliers and adders arrays. With these two techniques, a resource limited FPGA can be used to implement a larger kernel convolver which is commonly used in image process systems.

  6. Parity Codes Used for On-Line Testing in FPGA

    Directory of Open Access Journals (Sweden)

    P. Kubalík

    2005-01-01

    Full Text Available This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 

  7. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  8. Improving single slope ADC and an example implemented in FPGA with 16.7 GHz equivalent counter clook frequency

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; /Fermilab; Odeghe, John; /South Carolina State U.; Stackley, Scott; /Boston U.; Zha, Charles; /Rice U.

    2011-11-01

    Single slope ADC is a common building block in many ASCI or FPGA based front-end systems due to its simplicity, small silicon footprint, low noise interference and low power consumption. In single slope ADC, using a Gray code counter is a popular scheme for time digitization, in which the comparator output drives the clock (CK) port of a register to latch the bits from the Gray code counter. Unfortunately, feeding the comparator output into the CK-port causes unnecessary complexities and artificial challenges. In this case, the propagation delays of all bits from the counter to the register inputs must be matched and the counter must be a Gray code one. A simple improvement on the circuit topology, i.e., feeding the comparator output into the D-port of a register, will avoid these unnecessary challenges, eliminating the requirement of the propagation delay match of the counter bits and allowing the use of regular binary counters. This scheme not only simplifies current designs for low speeds and resolutions, but also opens possibilities for applications requiring higher speeds and resolutions. A multi-channel single slope ADC based on a low-cost FPGA device has been implemented and tested. The timing measurement bin width in this work is 60 ps, which would need a 16.7 GHz counter clock had it implemented with the conventional Gray code counter scheme. A 12-bit performance is achieved using a fully differential circuit making comparison between the input and the ramping reference, both in differential format.

  9. Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers

    Science.gov (United States)

    Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

    2016-10-01

    In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm3, and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

  10. Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers.

    Science.gov (United States)

    Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

    2016-10-07

    In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm(3), and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

  11. Fpga Implementation of 8-Bit Vedic Multiplier by Using Complex Numbers

    Directory of Open Access Journals (Sweden)

    Gundlapalle Nandakishore,

    2014-06-01

    Full Text Available The paper describes the implementation of 8-bit vedic multiplier using complex numbers previous technique describes that 8-bit vedic multiplier using barrel shifter by FPGA implementation comparing the both technique in this paper propagation delay is reduced so that processing of speed will be high 8-bit vedic multiplier using barrel shifter propagation delay nearly 22nsec but present technique 8-bit vedic multiplier using complex numbers where propagation delay is 19nsec. The design is implemented and verified by FPGA and ISE simulator. The core was implemented on the Spartan 3E starts board the preferred language is used in verilog.

  12. Solenoid-Simulation Circuit

    Science.gov (United States)

    Simon, R. A.

    1986-01-01

    Electrical properties of solenoids imitated for tests of control circuits. Simulation circuit imitates voltage and current responses of two engine-controlling solenoids. Used in tests of programs of digital engine-control circuits, also provides electronic interface with circuits imitating electrical properties of pressure sensors and linear variable-differential transformers. Produces voltages, currents, delays, and discrete turnon and turnoff signals representing operation of solenoid in engine-control relay. Many such circuits used simulating overall engine circuitry.

  13. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  14. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  15. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  16. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar Zulfikar

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  17. Evaluating system for SRAM-based FPGA single event upset rate

    Science.gov (United States)

    Wang, Yunlong; Bao, Bin

    2016-09-01

    This paper takes static random-access-memory (SRAM)-based field-programmable-gate-array (FPGA) as the research object. Attention is focused on the configuration memory of this kind of FPGA, and the research has been devoted to the contents of the configuration memory and the configuration circuit to manage its contents. The single event upset (SEU) happening in the configuration memory doesn't lead to a functional failure necessarily. The dynamic SEU is SEU which happens in the configuration memory and causes necessarily function failure. This paper introduces a test method of dynamic SUE rate for the SRAM-based FPGA by designing a FPGA with self-test function.

  18. Implementing kinematics computation in FPGA co-processor for a 6-DOF space manipulator

    Institute of Scientific and Technical Information of China (English)

    Zheng Yili; Sun Hanxu; Jia Qingxuan; Shi Guozhen

    2009-01-01

    Based on the coordinate rotation digital computer (CORDIC) algorithm, the high-speed kinematics calculation for a six degree of freedom (DOF) space manipulator is implemented in a field programmable gate array (FPGA) co-processor. A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation. The CORDIC soft-core and the CORDIC-based pipelined kinematics calculation co-processor are described with the very-high-speed integrated circuit hardware description language (VHDL) language and realized in the FPGA. Finally, the feasibility of the design is validated in the Spartan-3 FPGA of Xilinx Inc., and the performance specifications of FPGA co-processor are discussed. The results show that time-consumption of the kinematics calculation is greatly reduced.

  19. 160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA

    Directory of Open Access Journals (Sweden)

    Truong Kevin

    2007-06-01

    Full Text Available Abstract Background To infer homology and subsequently gene function, the Smith-Waterman (SW algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

  20. FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

    Science.gov (United States)

    Rao, Shanti

    2009-01-01

    A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

  1. Analysis on Marx Circuit of Solid-state Nanoseconds Pulse Generator Based on FPGA Control%全固态纳秒脉冲发生器电路分析

    Institute of Scientific and Technical Information of China (English)

    彭文邦; 于虹; 钱国超; 李亚宁; 韦根原

    2016-01-01

    s:Firstly, it was simulated by the Pspice software circuit simulation the Marx generator model with simple parameters. The mathematics analysis of Marx circuit model was tested and veriifed with experiments. then, multiple factor analysis of solid Marx circuit output characteristics, including MOSFET switch solid, driver circuit and stray parameters, was carried out. According to the requirements of pulse parameters, it was determined the selection of the solid-state circuit device parameters, including the solid Marx circuit parameters and solid state switch, energy storage capacitor. The pulse generator established the foundation for further study in transformer winding deformation with the pulse response method.%结合脉冲发生器的实际情况,利用Pspice电路仿真软件对简单参数下的Marx发生器模型进行了仿真,并以实验验证其数学分析的正确性,然后分析了MOSFET开关固态特性、驱动电路及杂散参数对固态Marx电路输出特性的影响。依据脉冲参数要求,确定固态Marx电路参数及固态开关、储能电容和隔离二极管等固态电路器件的选择。为进一步利用频响法检测变压器绕组变形奠定了基础。

  2. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    Energy Technology Data Exchange (ETDEWEB)

    Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul S [Los Alamos National Laboratory; Morgan, Keith S [Los Alamos National Laboratory; Caffrey, Michael P [Los Alamos National Laboratory

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  3. Multi-Objective Memetic Algorithm for FPGA Placement Using Parallel Genetic Annealing

    Directory of Open Access Journals (Sweden)

    Praveen T.

    2016-04-01

    Full Text Available Due to advancement in reconfigurable computing, Field Programmable Gate Array (FPGA has gained significance due to its low cost and fast prototyping. Parallelism, specialization, and hardware level adaptation, are the key features of reconfigurable computing. FPGA is a programmable chip that can be configured or reconfigured by the designer, to implement any digital circuit. One major challenge in FPGA design is the Placement problem. In this placement phase, the logic functions are assigned to specific cells of the circuit. The quality of the placement of the logic blocks determines the overall performance of the logic implemented in the circuits. The Placement of FPGA is a Multi-Objective Optimization problem that primarily involves minimization of three or more objective functions. In this paper, we propose a novel strategy to solve the FPGA placement problem using Non-dominated Sorting Genetic Algorithm (NSGA-II and Simulated Annealing technique. Experiments were conducted in Multicore Processors and metrics such as CPU time were measured to test the efficiency of the proposed algorithm. From the experimental results, it is evident that the proposed algorithm reduces the CPU consumption time to an average of 15% as compared to the Genetic Algorithm, 12% as compared to the Simulated Annealing, and approximately 6% as compared to the Genetic Annealing algorithm.

  4. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning

    CERN Document Server

    Lysecky, Roman

    2011-01-01

    Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-c...

  5. FPGA Based Quadruple Precision Floating Point Arithmetic for Scientific Computations

    Directory of Open Access Journals (Sweden)

    Mamidi Nagaraju

    2012-09-01

    Full Text Available In this project we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on IEEE 754 standard 128-bit floating-point number representations. Field Programmable Gate Arrays (FPGA is increasingly being used to design high end computationally intense microprocessors capable of handling floating point mathematical operations. Quadruple Precision Floating-Point Arithmetic is important in computational fluid dynamics and physical modelling, which require accurate numerical computations. However, modern computers perform binary arithmetic, which has flaws in representing and rounding the numbers. As the demand for quadruple precision floating point arithmetic is predicted to grow, the IEEE 754 Standard for Floating-Point Arithmetic includes specifications for quadruple precision floating point arithmetic. We implement quadruple precision floating point arithmetic unit for all the common operations, i.e. addition, subtraction, multiplication and division. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 128-bit quadruple precision circuits. The project will provide arithmetic operation, simulation result, hardware design, Input via PS/2 Keyboard interface and results displayed on LCD using Xilinx virtex5 (XC5VLX110TFF1136 FPGA device.

  6. An optimized ultrasound digital beamformer with dynamic focusing implemented on FPGA.

    Science.gov (United States)

    Almekkawy, Mohamed; Xu, Jingwei; Chirala, Mohan

    2014-01-01

    We present a resource-optimized dynamic digital beamformer for an ultrasound system based on a field-programmable gate array (FPGA). A comprehensive 64-channel receive beamformer with full dynamic focusing is embedded in the Altera Arria V FPGA chip. To improve spatial and contrast resolution, full dynamic beamforming is implemented by a novel method with resource optimization. This was conceived using the implementation of the delay summation through a bulk (coarse) delay and fractional (fine) delay. The sampling frequency is 40 MHz and the beamformer includes a 240 MHz polyphase filter that enhances the temporal resolution of the system while relaxing the Analog-to-Digital converter (ADC) bandwidth requirement. The results indicate that our 64-channel dynamic beamformer architecture is amenable for a low power FPGA-based implementation in a portable ultrasound system.

  7. Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

    Science.gov (United States)

    Matsubara, Takashi; Torikai, Hiroyuki

    2013-05-01

    A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

  8. Sigma Delta Modulation Based Ternary FIR Filter Mapping on FPGA

    Directory of Open Access Journals (Sweden)

    Tayabuddin Memon

    2011-07-01

    Full Text Available In this paper single-bit SDM (Sigma Delta Modulation based TFF (Ternary FIR Filter with balanced ternary coefficients (i.e. -1/0/+1 has been mapped on small commercially available FPGAs (Field Programmable Gate Arrays. Filter coefficients were obtained using second order sigma delta modulator. The filter structure is based on a hierarchical adder tree that can easily be pipelined for high performance purpose. Filter structure was coded in VHDL (Very High Speed Integrated Circuit Hardware Description Language and simulated in Quartus-II software. The filter exhibits low I/O (Input Output and core area usage and high performance-achieving clock speeds close to 200MHz on a low-cost FPGA and over 500MHz on a latest FPGA commercially available device. This single-bit ternary filter is intended to support video and audio processing applications in mobile communication systems.

  9. OCTAD-S: digital fast Fourier transform spectrometers by FPGA

    Science.gov (United States)

    Iwai, Kazumasa; Kubo, Yûki; Ishibashi, Hiromitsu; Naoi, Takahiro; Harada, Kenichi; Ema, Kenji; Hayashi, Yoshinori; Chikahiro, Yuichi

    2017-07-01

    We have developed a digital fast Fourier transform spectrometer made of an analog-to-digital converter (ADC) and a field-programmable gate array (FPGA). The base instrument has independent ADC and FPGA modules, which allow us to implement different spectrometers in a relatively easy manner. Two types of spectrometers have been instrumented: one with 4.096 GS/s sampling speed and 2048 frequency channels and the other with 2.048 GS/s sampling speed and 32,768 frequency channels. The signal processing in these spectrometers has no dead time, and the accumulated spectra are recorded in external media every 8 ms. A direct sampling spectroscopy up to 8 GHz is achieved by a microwave track-and-hold circuit, which can reduce the analog receiver in front of the spectrometer. Highly stable spectroscopy with a wide dynamic range was demonstrated in a series of laboratory experiments and test observations of solar radio bursts.

  10. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  11. Digital Waveform Generator Basedon FPGA

    Directory of Open Access Journals (Sweden)

    Shoucheng Ding

    2012-07-01

    Full Text Available Field Programmable Gate Array (FPGA of the Cyclone II series was as the core processor of frequency meter and the Quartus II was as the development plat form. This article had designed the fully digital signal generator. It use dall-digital frequency synthesizer technology and FPGA programming implemented the three waveforms: sin wave and square wave and triangle wave. The frequency was adjustable through10- bit phase accumulator and the analog multiplier achieved amplitude modulation. Using 51soft nuclear FPGA wrote a C program and realized the in put control word. The 4 × 4 matrix keyboard inputted frequency or amplitude value and the LCD1602displayedthem. The test results show that the system has high precision, distortion and low.

  12. FPGA based pulsed NQR spectrometer

    Science.gov (United States)

    Hemnani, Preeti; Rajarajan, A. K.; Joshi, Gopal; Motiwala, Paresh D.; Ravindranath, S. V. G.

    2014-04-01

    An NQR spectrometer for the frequency range of 1 MHz to 5 MHZ has been designed constructed and tested using an FPGA module. Consisting of four modules viz. Transmitter, Probe, Receiver and computer controlled (FPGA & Software) module containing frequency synthesizer, pulse programmer, mixer, detection and display, the instrument is capable of exciting nuclei with a power of 200W and can detect signal of a few microvolts in strength. 14N signal from NaNO2 has been observed with the expected signal strength.

  13. FPGA Architecture for Kriging Image Interpolation

    Directory of Open Access Journals (Sweden)

    Maciej Wielgosz

    2013-01-01

    Full Text Available This paper proposes an ultrafast scalable embedded image compression scheme based on discrete cosine transform. It is designed for general network architecture that guarantees maximum end-to-end delay (EED, in particular the Distributed Multimedia Plays (DMP architecture. DMP is designed to enable people to perform delay-sensitive real-time collaboration from remote places via their own collaboration space (CS. It requires much lower EED to achieve good synchronization than that in existing teleconference systems. A DMP node can drop packets from networked CSs intelligently to guarantee its local delay and degrade visual quality gracefully. The transmitter classifies visual information in an input image into priority ranks. Included in the bitstream as side information, the ranks enable intelligent packet dropping. The receiver reconstructs the image from the remaining packets. Four priority ranks for dropping are provided. Our promising results reveal that, with the proposed compression technique, maximum EED can be guaranteed with graceful degradation of image quality. The given parallel designs for its hardware implementation in FPGA shows its technical feasibility as a module in the DMP architecture.

  14. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  15. Design of FPGA-based radiation tolerant quench detectors for LHC

    Science.gov (United States)

    Steckert, J.; Skoczen, A.

    2017-04-01

    The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

  16. An Analytical Delay Model

    Institute of Scientific and Technical Information of China (English)

    MIN Yinghua; LI Zhongcheng

    1999-01-01

    Delay consideration has been a majorissue in design and test of high performance digital circuits. Theassumption of input signal change occurring only when all internal nodesare stable restricts the increase of clock frequency. It is no longertrue for wave pipelining circuits. However, previous logical delaymodels are based on the assumption. In addition, the stable time of arobust delay test generally depends on the longest sensitizable pathdelay. Thus, a new delay model is desirable. This paper explores thenecessity first. Then, Boolean process to analytically describe thelogical and timing behavior of a digital circuit is reviewed. Theconcept of sensitization is redefined precisely in this paper. Based onthe new concept of sensitization, an analytical delay model isintroduced. As a result, many untestable delay faults under thelogical delay model can be tested if the output waveforms can be sampledat more time points. The longest sensitizable path length is computedfor circuit design and delay test.

  17. Design and Implementation of Novel Smart Battery Management System for FPGA Based Portable Electronic Devices

    Directory of Open Access Journals (Sweden)

    Fangrong Xue

    2017-02-01

    Full Text Available This paper presents the analysis and design of a smart battery management system for Field Programmable Gate Array (FPGA based portable electronic devices. It is a novel concept of incorporating the functionality of a smart battery management system into the FPGA used by portable electronic devices, which provides the following advantages. (1 It lowers cost since the conventional commercial independent battery management circuit can be eliminated; (2 It offers more flexibility because FPGA based battery management algorithms can be specifically designed for different battery chemistries of different devices and can provide the flexibility of algorithms and functionalities updating as well. Smart battery management system concepts include four aspects: (1 smart charging; (2 battery balancing; (3 smart discharging; and (4 safety operating. One novel charging algorithm, which combines the merits of multistage charging and pulse charging, is proposed to charge a Li-ion battery pack smartly. A Proportional Integral (PI control method is introduced to achieve the current control of charging circuit with considerable close loop stability. Simulation results from the PSIM 9.0.4 software package and experimental results from the prototype built in the lab are demonstrated to verify the effectiveness of smart charging. The realizations of battery balancing, smart discharging, and safety operating are also briefly described by taking advantage of the proposed FPGA based smart battery management system topology, which verify the feasibility of the proposed FPGA based smart battery management system for portable electronic devices.

  18. FPGA密码模块恶意木马后门设计%Design of vicious trojan backdoor for FPGA cryptographical module

    Institute of Scientific and Technical Information of China (English)

    孙海涛; 刘洁; 何循来; 俞文文

    2013-01-01

    Security of FPGA contains two parts of data and program . Each phases in the life cycle of FPGA can bring significant influence for its security . The vulnerabilities in today ’ s design and fabrication process have raised the possibility of malicious circuit modification as known as trojans in a design to impact the functionality or transmit key information to the adver-sary . This paper designs a hardware trojan of transmitting key information towards FPGA . It is importantation to realize the imple-ment mechanism and raise the attention to IC security .%FPGA 器件安全性包括数据安全性和应用程序安全性两部分。FPGA 生命周期的各个阶段对其安全性都会产生至关重要的影响,由于 FPGA 电路在设计和生产中的脆弱性,使得恶意木马电路能够有机可乘。针对 FPGA 器件开发阶段,以 FPGA 密码模块为目标,设计能够泄露密钥的恶意木马后门电路,对于了解硬件木马实现机理、警示 FPGA 芯片安全具有重要作用。

  19. Research of Pipelined CORDIC Algorithm and Implementation Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    Zhongming JI; Xiaochen ZHAN

    2011-01-01

    CORDIC algorithm can transform the complex operations, which are difficult to be directly implemented by hardware circuits, into the simple addition and shift operations uniformly, then gradually approach the accurate result. The study gives a brief introduction of the ultimate principle and computing method of CORDIC algorithm. Taking sine and cosine as examples, the method of realization on FPGA is presented and it. is of good arithmetic speed as a result of using pipeline. The design has been provided correct by simulating and verification through Quartus II and Modelsim.

  20. Several key issues on implementing delay line based TDCs using FPGAs

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; /Fermilab

    2009-12-01

    Several topics in FPGA delay line based TDCs are discussed in this document. First, FPGA specific issues such as considerations on the delay line choice in different FPGA families, Wave Union Launchers, 'bubble proof' encoding logic, etc. are examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.

  1. 500kV变电站220kV线路断路器延时分闸故障分析%Fault Analysis of Delay Opening of 220 kV Circuit Breaker in 500 kV Substation

    Institute of Scientific and Technical Information of China (English)

    黄玮; 胡宏宇; 陈开群; 彭军海

    2012-01-01

    In view of the importance of close-open time, taking the delay opening failure of a 220 kV circuit breaker for an example, the reason of circuit breaker B phase delay opening is tested and a comprehensive analysis is given. The test results show that there exists conversion delay of the circuit breaker B phase auxiliary switch to cause the mismatch of open-close time of circuit breaker and operation time of relay protection equipment, which affected the opening time of the circuit breaker. Therefore, it is recommended to enhance the periodic test of the close-open time in power system test pro cedure to reduce the line fault.%鉴于断路器合-分时间参数的重要性,以一起220 kV线路断路器延时分闸故障为例,对断路器B相延时分闸的原因进行了现场测试,并进行了全面分析.测试结果表明,断路器B相辅助开关转换存在延时,造成断路器合—分时间与继电保护装置动作时间配合不当,影响了断路器的分闸时间,建议在电力系统相关试验规程中加强合—分时间的周期性测试,以减少线路故障.

  2. FPGA-Based Digital Current Switching Power Amplifiers Used in Magnetic Bearing Systems

    Science.gov (United States)

    Wang, Yin; Zhang, Kai; Dong, Jinping

    For a traditional two-level current switching power amplifier (PA) used in a magnetic bearing system, its current ripple is obvious. To increase its current ripple performance, three-level amplifiers are designed and their current control is generally based on analog and logical circuits. So the required hardware is complex and a performance increase from the hardware adjustment is difficult. To solve this problem, a FPGA-based digital current switching power amplifier (DCSPA) was designed. Its current ripple was obviously smaller than a two-level amplifier and its control circuit was much simpler than a tri-level amplifier with an analog control circuit. Because of the field-programmable capability of a FPGA chip used, different control algorithms including complex nonlinear algorithms could be easily implemented in the amplifier and their effects could be compared with the same hardware.

  3. Timing Constraints Based High Performance Des Design And Implementation On 28nm FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Pandey, Sujeet; Hussain, Dil muhammed Akbar

    2015-01-01

    in this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path...

  4. Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

    2016-01-01

    Multiplier is used for multiplication of a signal and a constant in digital signal processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XPower Analyzer. Vedic multiplier gain speed improvements by parallelizing the generation...... Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...... efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively....

  5. A new realization of time-to-digital converters based on FPGA internal routing resources.

    Science.gov (United States)

    Wang, Hai; Zhang, Min; Yao, Qin

    2013-09-01

    Time-to-digital converters (TDC) implemented in a single field-programmable gate array (FPGA) chip which overcome the difficulties found in other FPGA-based TDCs are proposed in this paper. Emphasis is placed on the construction of two delay lines with a good delay consistency, as well as a minimum delay difference by which the measurement resolution can be improved and measurement error can be reduced. A modified vernier delay line structure is introduced which abandoned special delay elements and directly used FPGA internal routing resources to generate the cell delay. To get a good consistency for the system, manual placement and manual routing are used to standardize the delays. The resolution of the system is 9 ps and the standard deviation is less than 1 least significant bit (LSB) within the whole measurement range. The corrected differential nonlinearity is as low as 0.11 LSB. Experiments showed that the proposed system features high accuracy, low cost, and high stability.

  6. An FPGA-based ultrasound imaging system using capacitive micromachined ultrasonic transducers.

    Science.gov (United States)

    Wong, Lawrence L P; Chen, Albert I; Logan, Andrew S; Yeow, John T W

    2012-07-01

    We report the design and experimental results of a field-programmable gate array (FPGA)-based real-time ultrasound imaging system that uses a 16-element phased-array capacitive micromachined ultrasonic transducer fabricated using a fusion bonding process. The imaging system consists of the transducer, discrete analog components situated on a custom-made circuit board, the FPGA, and a monitor. The FPGA program consists of five functional blocks: a main counter, transmit and receive beamformer, receive signal pre-processing, envelope detection, and display. No dedicated digital signal processor or personal computer is required for the imaging system. An experiment is carried out to obtain the sector B-scan of a 4-wire target. The ultrasound imaging system demonstrates the possibility of an integrated system-in-a-package solution.

  7. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  8. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  9. Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA

    CERN Document Server

    Ghosal, Prasun; Biswas, Manish

    2010-01-01

    Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely used in cryptography for securing the Internet traffic in modern day communication systems. The design of the digital cryptographic circuit was implemented in a Vertex 5 series (XCVLX5110T) target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz. Spartan 3, Spartan 3AN, Virtex 5, Virtex E device families. The novelty and contribution of this work is in three folds: (i) Extensive simulation and synthesis of the proposed design targeted for various FPGA devices, (ii) Complete hardware implementation of encryption and decryption algorithms onto Virtex 5 series device ...

  10. Synchronizing Hyperchaotic Circuits

    DEFF Research Database (Denmark)

    Tamasevicius, Arunas; Cenys, Antanas; Namajunas, Audrius

    1997-01-01

    Regarding possible applications to secure communications the technique of synchronizing hyperchaotic circuits with a single dynamical variable is discussed. Several specific examples including the fourth-order circuits with two positive Lyapunov exponents as well as the oscillator with a delay line...... characterized by multiple positive Lyapunov exponents are reviewd....

  11. 基于DSP的FPGA配置方法研究与实现%Research and Implement of FPGA Configuration with DSP

    Institute of Scientific and Technical Information of China (English)

    李飞飞; 苏延川; 王鹏

    2011-01-01

    在数字电路中,FPGA+DSP的系统结构应用日益广泛.为了减小此种结构的体积和降低成本,对FPGA采用了被动并行的配置方式.上电后,DSP首先完成自身程序的加载,之后充当配置FPGA的主处理器,从FLASH芯片中读取FPGA程序,按照配置时序完成FPGA的程序加载.在硬件设计上,创新性地采用了DSP,FPGA,FLASH共用数据总线的方式,当DSP从FLASH芯片中读取FPGA程序时,FPGA可以直接抓取出现在总线上数据来完成加载.实践证明,此种配置方法结构简洁,工作稳定,在一定程度上实现了小型化和低成本.%In digital circuits, the system structure of FPGA+DSP is widely used. To reduce the volume and cost of system structure, the slave SelectMAP configuration method is adopted for FPGA. After power on, DSP completes loading of its programme firstly, then acts as the primary processor of configuring FPGA to read the FPGA programme from FLASH chip, and fulfils the task of programme loading of FPGA according to the configuration time sequence. In hardware design, a new method of sharing the data bus of DSP, FPGA and FLASH is innovatively used. FPGA can catch the data appearing in the bus to complete the loading when DSP reads FPGA programme from FLASH. The configuration circuit is compact and works well in practice. The method implemented miniaturization and low cost in some degree.

  12. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  13. FPGA IMPLEMENTATION OF LOW POWER DIGITAL FREQUENCY

    Directory of Open Access Journals (Sweden)

    K. R. Rekha,

    2010-10-01

    Full Text Available In this Paper we are presenting a new FPGA approach to design an optimized use a Digital Frequency Synthesizer (DDFS in our system to generate a sampled sinusoidal wave of frequency. The major advantage of Digital Frequency Synthesizer (DFS is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under the control of a DSP. Other inherent DFS attributes include the ability to tune with extremely fine frequency and phase resolution and to rapidly “hop” between the frequencies. These combined characteristics have made this technology popular in military, radar and communications systems. The digital circuits used to implementsignal processing functions do not suffer the effects of thermal drifts, aging and component variations associated with their analog counterparts. The implementation of digital functional blocks makes it possible to achieve a high degree of system integration. Recent advances in IC fabrication technology, particularly the CMOS technology coupled with advanced DSP algorithms and architectures provide possible single chip solutions to complex communication and signal processing sub-systems such as modulators, demodulators, local oscillators, and programmable clock generators, cellular base stations, up converters, down converters, power line communication,wireless local loop base stations etc .

  14. Phase correction on FPGA for TOTEM clock distribution system

    CERN Document Server

    Bellina, Alessandra

    2017-01-01

    A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.

  15. OPENCORE NMR: open-source core modules for implementing an integrated FPGA-based NMR spectrometer.

    Science.gov (United States)

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  16. Real-time implementation of camera positioning algorithm based on FPGA & SOPC

    Science.gov (United States)

    Yang, Mingcao; Qiu, Yuehong

    2014-09-01

    In recent years, with the development of positioning algorithm and FPGA, to achieve the camera positioning based on real-time implementation, rapidity, accuracy of FPGA has become a possibility by way of in-depth study of embedded hardware and dual camera positioning system, this thesis set up an infrared optical positioning system based on FPGA and SOPC system, which enables real-time positioning to mark points in space. Thesis completion include: (1) uses a CMOS sensor to extract the pixel of three objects with total feet, implemented through FPGA hardware driver, visible-light LED, used here as the target point of the instrument. (2) prior to extraction of the feature point coordinates, the image needs to be filtered to avoid affecting the physical properties of the system to bring the platform, where the median filtering. (3) Coordinate signs point to FPGA hardware circuit extraction, a new iterative threshold selection method for segmentation of images. Binary image is then segmented image tags, which calculates the coordinates of the feature points of the needle through the center of gravity method. (4) direct linear transformation (DLT) and extreme constraints method is applied to three-dimensional reconstruction of the plane array CMOS system space coordinates. using SOPC system on a chip here, taking advantage of dual-core computing systems, which let match and coordinate operations separately, thus increase processing speed.

  17. FPGA implementation of Generalized Hebbian Algorithm for texture classification.

    Science.gov (United States)

    Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

    2012-01-01

    This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs.

  18. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  19. FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

    Directory of Open Access Journals (Sweden)

    Wei-Hao Lee

    2012-05-01

    Full Text Available This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA. It is embedded in a System-On-Programmable-Chip (SOPC platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance andlow area costs.

  20. A Neuron Model for FPGA Spiking Neuronal Network Implementation

    Directory of Open Access Journals (Sweden)

    BONTEANU, G.

    2011-11-01

    Full Text Available We propose a neuron model, able to reproduce the basic elements of the neuronal dynamics, optimized for digital implementation of Spiking Neural Networks. Its architecture is structured in two major blocks, a datapath and a control unit. The datapath consists of a membrane potential circuit, which emulates the neuronal dynamics at the soma level, and a synaptic circuit used to update the synaptic weight according to the spike timing dependent plasticity (STDP mechanism. The proposed model is implemented into a Cyclone II-Altera FPGA device. Our results indicate the neuron model can be used to build up 1K Spiking Neural Networks on reconfigurable logic suport, to explore various network topologies.

  1. FPGA Implementation of Secure Force (64-Bit Low Complexity Encryption Algorithm

    Directory of Open Access Journals (Sweden)

    Shujaat Khan

    2015-11-01

    Full Text Available Field-Programmable Gate Arrays (FPGAs have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loop-unroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

  2. FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video

    Directory of Open Access Journals (Sweden)

    Mariangela Genovese

    2013-01-01

    Full Text Available Circuits and systems able to process high quality video in real time are fundamental in nowadays imaging systems. The circuit proposed in the paper, aimed at the robust identification of the background in video streams, implements the improved formulation of the Gaussian Mixture Model (GMM algorithm that is included in the OpenCV library. An innovative, hardware oriented, formulation of the GMM equations, the use of truncated binary multipliers, and ROM compression techniques allow reduced hardware complexity and increased processing capability. The proposed circuit has been designed having commercial FPGA devices as target and provides speed and logic resources occupation that overcome previously proposed implementations. The circuit, when implemented on Virtex6 or StratixIV, processes more than 45 frame per second in 1080p format and uses few percent of FPGA logic resources.

  3. Cryptographic Applications using FPGA Technology

    Directory of Open Access Journals (Sweden)

    Alexandru Coman

    2011-03-01

    Full Text Available Cryptographic systems have become a part of our daily life through the need of security of many common activities such as communication, payments, data transfers etc. The best support in design and implementation of cryptographic applications is offered by embedded systems such as ASICs and FPGAs. In the past few years, the increase in performance of FPGAs has made them key components in implementing cryptographic systems. One of the most important parts of the cryptographic systems is the random number generator used. Combinations of PRNG and TRNG are commonly used. A good and efficient TRNG implementation is very important and can be achieved through FPGA technology.

  4. STRS Compliant FPGA Waveform Development

    Science.gov (United States)

    Nappier, Jennifer; Downey, Joseph

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

  5. FPGA design and implementation of Gaussian filter

    Science.gov (United States)

    Yang, Zhihui; Zhou, Gang

    2015-12-01

    In this paper , we choose four different variances of 1,3,6 and 12 to conduct FPGA design with three kinds of Gaussian filtering algorithm ,they are implementing Gaussian filter with a Gaussian filter template, Gaussian filter approximation with mean filtering and Gaussian filter approximation with IIR filtering. By waveform simulation and synthesis, we get the processing results on the experimental image and the consumption of FPGA resources of the three methods. We set the result of Gaussian filter used in matlab as standard to get the result error. By comparing the FPGA resources and the error of FPGA implementation methods, we get the best FPGA design to achieve a Gaussian filter. Conclusions can be drawn based on the results we have already got. When the variance is small, the FPGA resources is enough for the algorithm to implement Gaussian filter with a Gaussian filter template which is the best choice. But when the variance is so large that there is no more FPGA resources, we can chose the mean to approximate Gaussian filter with IIR filtering.

  6. Real-time windowing in imaging radar using FPGA technique

    Science.gov (United States)

    Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

    2005-02-01

    The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

  7. Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

    Science.gov (United States)

    Cristo, Alejandro; Fisher, Kevin; Perez, Rosa M.; Martinez, Pablo; Gualtieri, Anthony J.

    2012-01-01

    Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

  8. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    Science.gov (United States)

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-12-16

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  9. An FPGA-based open platform for ultrasound biomicroscopy.

    Science.gov (United States)

    Qiu, Weibao; Yu, Yanyan; Tsang, Fu; Sun, Lei

    2012-07-01

    Ultrasound biomicroscopy (UBM) has been extensively applied to preclinical studies in small animal models. Individual animal study is unique and requires different utilization of the UBM system to accommodate different transducer characteristics, data acquisition strategies, signal processing, and image reconstruction methods. There is a demand for a flexible and open UBM platform to allow users to customize the system for various studies and have full access to experimental data. This paper presents the development of an open UBM platform (center frequency 20 to 80 MHz) for various preclinical studies. The platform design was based on a field-programmable gate array (FPGA) embedded in a printed circuit board to achieve B-mode imaging and directional pulsed-wave Doppler. Instead of hardware circuitry, most functions of the platform, such as filtering, envelope detection, and scan conversion, were achieved by FPGA programs; thus, the system architecture could be easily modified for specific applications. In addition, a novel digital quadrature demodulation algorithm was implemented for fast and accurate Doppler profiling. Finally, test results showed that the platform could offer a minimum detectable signal of 25 μV, allowing a 51 dB dynamic range at 47 dB gain, and real-time imaging at more than 500 frames/s. Phantom and in vivo imaging experiments were conducted and the results demonstrated good system performance.

  10. FPGA control utility in JAVA

    Science.gov (United States)

    Drabik, Paweł; Pozniak, Krzysztof T.

    2008-01-01

    Processing of large amount of data for high energy physics experiments is modeled here in a form of a multichannel, distributed measurement system based on photonic and electrical modules. A method to control such a system is presented in this paper. This method is based on a new method of address space management called the Component Internal Interface (CII). An updatable and configurable environment provided by FPGA fulfills technological and functional demands imposed on complex measurement systems of the considered kind. A purpose, design process and realization of the object oriented software application, written in the high level code described. A few examples of usage of the suggested application is presented. The application is intended for usage in HEP experiments and FLASH, XFEL lasers.

  11. An FPGA-Based Electronic Cochlea

    OpenAIRE

    M. P. Leong; Jin, Craig T.; Leong, Philip H. W.

    2003-01-01

    A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coeffi...

  12. FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

    Science.gov (United States)

    Haselman, M D; Pasko, J; Hauck, S; Lewellen, T K; Miyaoka, R S

    2012-10-01

    Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources.

  13. Design and implementation of FPGA-based phase modulation control for series resonant inverters

    Indian Academy of Sciences (India)

    N Gayathri; M C Chandorkar

    2008-10-01

    Owing to the tremendous advances in the digital technology, and improved reliability and performance of the digital control mechanisms, this paper focuses on design and implementation of digital controller using FPGA-based circuit design approach. The digital controller proposed is designed for series resonant inverter used in DC–DC converter applications. Phase modulation technique is proposed for the realization of digital controller on FPGA. The Series Resonant Converter (SRC) is considered in this paper as a preferred converter topology for high power, high voltage power supplies. This paper studies the implementation of phase shift modulation technique using FPGA. The inverter designed, is IGBT based, and Zero Voltage Switching (ZVS) technique is implemented due to reduced stresses on devices and increased efficiency. The phase modulated series resonant inverters (PM-SRC) promotes ZVS operation when its switching frequency is greater than resonant frequency. The designed PM controller is realized using FPGA on which control algorithm and other features of a controller are developed. The series resonant inverter is built and tested for full load under open loop and closed loop conditions at a switching frequency of 20 kHz. The results are presented under varying load conditions. The simulation and the experimental results were found to match closely.

  14. FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model.

    Science.gov (United States)

    Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

    2014-01-01

    A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well.

  15. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  16. Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

    Directory of Open Access Journals (Sweden)

    Eshwararao. Boddepalli

    2011-12-01

    Full Text Available This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating one matrix line. Both fully combinational and pipelined versions of the algorithm were designed and tested until a functional physical implementation was obtained, including a user interface. The paper also presents new way to implement hardware structures inside programmable circuits, using portable schematic design from “Altium Designer” software environment instead textual description with HDL languages

  17. FPGA-based Accelerators for Parallel Data Sort

    Directory of Open Access Journals (Sweden)

    Sklyarov Valery

    2014-12-01

    Full Text Available The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1 using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2 parallel merging of many sorted sequences; 3 using even-odd transition networks built from other sorting networks; 4 rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×220 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item.

  18. Researching and implementation of reconfigurable Hash chip based on FPGA

    Institute of Scientific and Technical Information of China (English)

    Yang Xiaohui; Dai Zibin; Liu Yuanfeng; Wang Ting

    2007-01-01

    The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.

  19. A Digitalized Silicon Microgyroscope Based on Embedded FPGA

    Directory of Open Access Journals (Sweden)

    Dunzhu Xia

    2012-09-01

    Full Text Available This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC loop and software phase-locked loop (SPLL based on the Coordinated Rotation Digital Computer (CORDIC algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

  20. Research on Reactor Rod Control Indicating System Based on FPGA%基于FPGA的数字化棒控技术研究

    Institute of Scientific and Technical Information of China (English)

    蔡晨

    2016-01-01

    A application of FPGA (Field Programmable Gate Array)in reactor rod control a indicating system is presented.To take advantage of plentiful logic elements and flexible programmable characteristic of FPGA, the complex logic circuits in reactor rod control and rod position indicating system are integrated in one FPGA chip.The application of FPGA eliminates the intrinsic defects of traditional analog integrated circuit and improves the reliability and stability of system.With simple circuit structure, the system has high anti-noise performance and characteristic of miniaturization.%本文介绍了将FPGA(Field Programmable Gate Array现场可编程逻辑阵列)技术应用于反应堆棒控系统的概况。利用FPGA丰富的逻辑资源,编程的灵活性等特点来实现反应堆棒控系统的复杂逻辑电路,电路结构简单明了,将大量复杂的逻辑电路集成到一块FPGA芯片中,提高了系统的可靠性与稳定性,解决了原有模拟电路的很多固有缺陷,提高了系统的抗干扰性能,实现了设备数字化与小型化。

  1. Design and Implementation of Quintuple Processor Architecture Using FPGA

    Directory of Open Access Journals (Sweden)

    P.Annapurna

    2014-09-01

    Full Text Available The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.

  2. 基于 FPGA 的煤矿井下监控分站设计%Design the Monitoring Substation of Coal Mine Underground Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    辛永祥; 张小波; 刘京威

    2015-01-01

    针对现有煤矿安全监控系统中越来越多传感器支持485/C A N智能通信,分站支持接口个数少、采用单一的微处理器对传感器的数据进行采集,从而导致现有分站组网成本高、数据响应实时性差等问题。提出一种基于 FPGA 的煤矿井下监控分站设计方案。详细介绍分站的软件和硬件总体架构设计;FPGA 关键信号采集和信号处理技术;部分关键电路详细设计;双口 FIFO 完成 FPGA 与 MCU 之间的通信,解决了 FPGA 与 MCU 工作时钟不一致的问题;同时可以采用红外遥控,灵活设置 FPGA 工作参数,完成人机交互等任务。该方案设计的分站具有数据响应实时性好、485接口个数多、布局布线成本低、适用不同传输接口类型的传感器接入监控系统等优点。%In view of more and more sensors support 485/CAN intelligent communication in the coal mine safety monitoring system ,the substation has few interfaces ,using a single microprocessor for sensor data acquisition ,leads to the existing substation network of high cost ,poor real-time data re-sponse problems. The paper put forward a design scheme of based on FPGA monitoring substation of coal mine underground. Detailed introduction of software and hardware architecture of substation de-sign ;The FPGA key signal acquisition and signal processing technology ;detailed introduction some key circuits design ;use the Dual port FIFO to complete the communication between FPGA and MCU , solve the problem of between FPGA and MCU inconsistent work clock ;At the same time can use the infrared remote control ,flexible setting of FPGA parameters to complete the work ,such as human-computer interaction task. The scheme design of the substation has the advantages of good real-time performance ,response data interface layout and wiring ,485 more low cost ,suitable for different transmission interface type sensor access monitoring system.

  3. Printed Circuit Board Design with HDL Designer

    Science.gov (United States)

    Winkert, Thomas K.; LaFourcade, Teresa

    2004-01-01

    Staying up to date with the latest CAD tools both from a cost and time perspective is difficult. Within a given organization there may be experts in Printed Circuit Board Design tools and experts in FPGA/VHDL tools. Wouldn't it be great to have someone familiar with HDL Designer be able to design PCBs without having to learn another tool? This paper describes a limited experiment to do this.

  4. Three-dimensional design methodologies for tree-based FPGA architecture

    CERN Document Server

    Pangracious, Vinod; Mehrez, Habib

    2015-01-01

    This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

  5. Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

    Science.gov (United States)

    Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

    At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

  6. Real Time FPGA-Based Ethernet Control Communication for Robotic Arm

    Directory of Open Access Journals (Sweden)

    Ishak Mohamad Khairi

    2017-01-01

    Full Text Available In this paper, an approach for real time control communication using Ethernet is proposed. The strategy to support this at the network level and include Field Programmable Gate Array (FPGA implementation on the Ethernet platform for robotic arm. An embedded Ethernet controller is designed to send data packet via Ethernet Local Area Network (LAN. The transferring data also employs Arduino Mega as the medium of communication between FPGA board and the robotic arm. It is used as the receiver to receive data packet from FPGA board with the interface of Arduino Ethernet shield. The control operation on the robotic arm is performed once the desired data packet length is reached to the Arduino Mega. SolidWorks and MATLAB software are used to design the robotic arm and simulate the robotic arm working flexibility in real world respectively. The result of the average data packet delay between FPGA boards is lower in comparison to Arduiono board. The data packet can send successfully in through the network to test the robotic arm.

  7. FPGA-based trigger system for the Fermilab SeaQuest experiment

    CERN Document Server

    Shiu, Shiuan-Hal; McClellan, Randall Evan; Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu; Gilman, Ron; Nakano, Kenichi; Peng, Jen-Chieh; Wang, Su-Yin

    2015-01-01

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic {\\mu}+ and {\\mu}- produced in 120 GeV/c proton-nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns steps and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

  8. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    In this paper, the design and simulation of a Dough Mixer Controller (DMC) with Proportional ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ...... parative Analysis among DSP and FPGA-.

  9. Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

    2011-03-01

    Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code

  10. Heart sound signal collection based on FPGA%基于FPGA的心音信号采集

    Institute of Scientific and Technical Information of China (English)

    王晓燕; 曾庆宁; 粟秀尹

    2012-01-01

    This paper introduces a type of heart sound collection system based on FPGA. The system consists of high performance sensor sampling heart sounds, the preproeessing circuit, the A/D conversion module and serial communication circuit. Sensors transfer heart sound signal into electrical signal, which is amplified and filtrated through the pretreatment circuit, and then sent to the FPGA after MD conversion circuit. FPGA will transfer the collected data to PC. The experiment results show that the system can collect heat sounds signal noninvasively, fast and cheaply.%设计了基于FPGA的心音采集系统,该系统包括高性能的心音传感器、预处理电路、A/D转换电路和串口通信电路。传感器托心音信号转换成电信号,通过预处理电路的放大和滤波,再经过A/D转换电路送到FPGA,FPGA把现场采集到的数据及时可靠地传递给PC。实验结果表明。该系统能无创、快速、廉价地采集心音信号。

  11. Design and FPGA implementation of real-time automatic image enhancement algorithm

    Science.gov (United States)

    Dong, GuoWei; Hou, ZuoXun; Tang, Qi; Pan, Zheng; Li, Xin

    2016-11-01

    In order to improve image processing quality and boost processing rate, this paper proposes an real-time automatic image enhancement algorithm. It is based on the histogram equalization algorithm and the piecewise linear enhancement algorithm, and it calculate the relationship of the histogram and the piecewise linear function by analyzing the histogram distribution for adaptive image enhancement. Furthermore, the corresponding FPGA processing modules are designed to implement the methods. Especially, the high-performance parallel pipelined technology and inner potential parallel processing ability of the modules are paid more attention to ensure the real-time processing ability of the complete system. The simulations and the experimentations show that the algorithm is based on the design and implementation of FPGA hardware circuit less cost on hardware, high real-time performance, the good processing performance in different sceneries. The algorithm can effectively improve the image quality, and would have wide prospect on imaging processing field.

  12. FPGA Implementation of Parallel Particle Swarm Optimization Algorithm and Compared with Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    BEN AMEUR Mohamed sadek

    2016-08-01

    Full Text Available In this paper, a digital implementation of Particle Swarm Optimization algorithm (PSO is developed for implementation on Field Programmable Gate Array (FPGA. PSO is a recent intelligent heuristic search method in which the mechanism of algorithm is inspired by the swarming of biological populations. PSO is similar to the Genetic Algorithm (GA. In fact, both of them use a combination of deterministic and probabilistic rules. The experimental results of this algorithm are effective to evaluate the performance of the PSO compared to GA and other PSO algorithm. New digital solutions are available to generate a hardware implementation of PSO Algorithms. Thus, we developed a hardware architecture based on Finite state machine (FSM and implemented into FPGA to solve some dispatch computing problems over other circuits based on swarm intelligence. Moreover, the inherent parallelism of these new hardware solutions with a large computational capacity makes the running time negligible regardless the complexity of the processing.

  13. An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

    Directory of Open Access Journals (Sweden)

    Y. H. Lee

    2016-01-01

    Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

  14. A new cellular nonlinear network emulation on FPGA for EEG signal processing in epilepsy

    Science.gov (United States)

    Müller, Jens; Müller, Jan; Tetzlaff, Ronald

    2011-05-01

    For processing of EEG signals, we propose a new architecture for the hardware emulation of discrete-time Cellular Nonlinear Networks (DT-CNN). Our results show the importance of a high computational accuracy in EEG signal prediction that cannot be achieved with existing analogue VLSI circuits. The refined architecture of the processing elements and its resource schedule, the cellular network structure with local couplings, the FPGA-based embedded system containing the DT-CNN, and the data flow in the entire system will be discussed in detail. The proposed DT-CNN design has been implemented and tested on an Xilinx FPGA development platform. The embedded co-processor with a multi-threading kernel is utilised for control and pre-processing tasks and data exchange to the host via Ethernet. The performance of the implemented DT-CNN has been determined for a popular example and compared to that of a conventional computer.

  15. Real-time FPGA-based Non-Cryptography System for Wireless Network

    Directory of Open Access Journals (Sweden)

    Mostafa Abutaleb

    2012-05-01

    Full Text Available Traditional privacy techniques for wireless communications are facing great challenges, due to the open radio propagation environment and limited options of transmission techniques. A new bilateral pilot aided protocol is presented, with single-tone based burst transmission over slow time varying flat fading wireless channels, and is investigated to enhance the security of quadrature amplitude modulation (QAM system. In this paper, a real-time and link privacy method with FPGA-based design is proposed, which is based on the characteristics of radio channel including randomness and privacy. For the proposed approach, the unique instant channel state information (CSI of channel can be estimated in real-time by a proposed FPGA-based circuit to be used in giving confidentiality for transmitted data. The proposed approach is adequate for most real-time wireless communication systems.

  16. Research and development of infrared object detection system based on FPGA

    Science.gov (United States)

    Zhao, Jianhui; He, Jianwei; Wang, Pengpeng; Li, Fan

    2009-07-01

    Infrared object detection is an important technique of digital image processing. It is widely used in automatic navigation, intelligent video surveillance systems, traffic detection, medical image processing etc. Infrared object detection system requires large storage and high speed processing technology. The current development trend is the system which can be achieved by hardware in real-time with fewer operations and higher performance. As a main large-scale programmable specific integrated circuit, field programmable gate array (FPGA) can meet all the requirements of high speed image processing, with the characteristics of simple algorithm realization, easy programming, good portability and inheritability. So it could get better result by using FPGA to infrared object detection system. According to the requirements, the infrared object detection system is designed on FPGA. By analyzing some of the main algorithms of object detection, two new object detection algorithms called integral compare algorithm (ICA) and gradual approach centroid algorithm (GACA) are presented. The system design applying FPGA in hardware can implement high speed processing technology, which brings the advantage of both performance and flexibility. ICA is a new type of denoising algorithm with advantage of lower computation complexity and less execution time. What is more important is that this algorithm can be implemented in FPGA expediently. Base on image preprocessing of ICA, GACA brings high positioning precision with advantage of insensitivity to the initial value and fewer times of convergence iteration. The experiments indicate that the infrared object detection system can implement high speed infrared object detecting in real-time, with high antijamming ability and high precision. The progress of Verilog-HDL and its architecture are introduced in this paper. Considering the engineering application, this paper gives the particular design idea and the flow of this method

  17. Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

    Science.gov (United States)

    Seefeldt, James (Inventor); Feng, Xiaoxin (Inventor); Roper, Weston (Inventor)

    2013-01-01

    A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

  18. FPGA based Smart Wireless MIMO Control System

    Science.gov (United States)

    Usman Ali, Syed M.; Hussain, Sajid; Akber Siddiqui, Ali; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-12-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

  19. FPGA technology in instrumentation and related tools

    CERN Document Server

    Serrano, J

    2005-01-01

    Field Programmable Gate Arrays (FPGA) have become an alternative to traditional Digital Signal Processors (DSP) in many applications. In some cases, where high throughput is the main concern, an FPGA-based system may in fact be the only solution to fulfill the requirements. In the area of particle accelerators, FPGAs are used in many contexts, ranging from digital feedback loops for power converters and RF cavities to Digital Signal Processing for beam instrumentation. These designs harness the vast amount of logic resources inside FPGA chips to deliver unprecedented performance through parallelism and pipelining. After an introduction to the internal architecture of FPGAs and the design process, including advanced issues such as floor planning, we look at two important techniques to implement arithmetic in FPGAs: Distributed Arithmetic (DA) and the Coordinate Rotation DIgital Computer (CORDIC) algorithm. The goal is not to exhaust the list of Digital Signal Processing techniques for FPGAs, but rather to illu...

  20. Algebraic circuits

    CERN Document Server

    Lloris Ruiz, Antonio; Parrilla Roure, Luis; García Ríos, Antonio

    2014-01-01

    This book presents a complete and accurate study of algebraic circuits, digital circuits whose performance can be associated with any algebraic structure. The authors distinguish between basic algebraic circuits, such as Linear Feedback Shift Registers (LFSRs) and cellular automata, and algebraic circuits, such as finite fields or Galois fields. The book includes a comprehensive review of representation systems, of arithmetic circuits implementing basic and more complex operations, and of the residue number systems (RNS). It presents a study of basic algebraic circuits such as LFSRs and cellular automata as well as a study of circuits related to Galois fields, including two real cryptographic applications of Galois fields.

  1. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  2. FPGA Based Acceleration of Decimal Operations

    DEFF Research Database (Denmark)

    Nannarelli, Alberto

    2011-01-01

    Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show...... that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without...

  3. Synchro Controller of Radar on FPGA

    Institute of Scientific and Technical Information of China (English)

    JiangTie-zhen; ShiZhen-hua; WuShi-cai

    2003-01-01

    This paper mainly represents the realization of synchro controller based on the programmable logic devices FPGA by request of HF ground wave radar synchro controller under the instance of making the best of the virtues of FPGA.This design introduces the data communication between PC and synchro controller by I2C Bus, which can carry the synchronous signals' parameters to RAM of synchro controller,then according to the theory that the result of comparing counter value with signals' parameters is the needed wave,we produce all waves HF ground wave radar needs, moreover all waves are produced timesharing in order to save resources.

  4. Synchro Controller of Radar on FPGA

    Institute of Scientific and Technical Information of China (English)

    Jiang Tie-zhen; Shi Zhen-huat; Wu Shi-cai

    2003-01-01

    This paper mainly represents the realization of synchro controller based on the programmable logic devices FPGA by request of HF ground wave radar synchro controller under the instance of making the best of the virtues of FPGA.This design introduces the data communication between PC and synchro controller by I2C Bus, which can carry the syn-chronous signals' parameters to RAM of synchro controller,then according to the theory that the result of comparing counter value with signals' parameters is the needed wave,we produce all waves HF ground wave radar needs, moreover all waves are produced time-sharing in order to save re-sources.

  5. A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA.

    Science.gov (United States)

    Kim, HyunJin; Choi, Kang-Il

    2016-01-01

    This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is implemented with a look-up table (LUT) for the combinational logic circuit between registers. In addition, multiple state transitions between stages can be performed in a pipelined fashion. In this paper, it is proposed that multiple one-to-one state transitions, called merged state transitions, can be performed with an LUT. By cutting down the number of used LUTs for implementing state transitions, the hardware overhead of combinational logic circuits is greatly reduced in the proposed pipelined NFA-based string matching scheme.

  6. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  7. Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

    Science.gov (United States)

    Jamot, Robert F.; Monroe, Ryan M.

    2012-01-01

    With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

  8. An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC

    CERN Document Server

    Ballester, F J; Gras, J J; Lewis, J; Savioz, J J; Serrano, J

    2003-01-01

    The Beam Synchronous Timing system (BST) will be used around the LHC and its injector, the SPS, to broadcast timing meassages and synchronize actions with the beam in different receivers. To achieve beam synchronization, the BST Master card encodes messages using the bunch clock, with a nominal value of 40.079 MHz for the LHC. These messages are produced by a set of tasks every revolution period, which is every 89 us for the LHC and every 23 us for the SPS, therefore imposing a hard real-time constraint on the system. To achieve determinism, the BST Master uses a dedicated CPU inside its main Field Programmable Gate Array (FPGA) featuring zero-delay hardware task switching and a reduced instruction set. This paper describes the BST Master card, stressing the main FPGA design, as well as the associated software, including the LynxOS driver and the tailor-made assembler.

  9. ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

    Directory of Open Access Journals (Sweden)

    Suma

    2017-02-01

    Full Text Available The area of radiological image compression has not yet met its potential solution. After reviewing the existing mechanism of compression, it was found that majority of the existing techniques suffers from significant pitfalls e.g. more usage of transformation schemes, more resource utilization, delay, less focus on FPGA performance enhancement, extremely less emphasis on Vedic-multipliers. Hence, this paper presents an analytical modelling of ROI (Region of Interest-based radiological image compression that applies Vedic Multiplier Urdhva-Tiryagbhyam to enhance the performance of coding using Discrete Wavelet Transform (DWT. The study outcome was implemented in Matlab and multiple test bed of FPGA devices (Virtex 4 FX100 -12 FF1152 and Spartan 3 XC400-5TQ144 and assessed using both visual and numerical outcomes to find that proposed system excel better performance in comparison to recently existing techniques.

  10. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  11. FPGA Sequencer for Radar Altimeter Applications

    Science.gov (United States)

    Berkun, Andrew C.; Pollard, Brian D.; Chen, Curtis W.

    2011-01-01

    A sequencer for a radar altimeter provides accurate attitude information for a reliable soft landing of the Mars Science Laboratory (MSL). This is a field-programmable- gate-array (FPGA)-only implementation. A table loaded externally into the FPGA controls timing, processing, and decision structures. Radar is memory-less and does not use previous acquisitions to assist in the current acquisition. All cycles complete in exactly 50 milliseconds, regardless of range or whether a target was found. A RAM (random access memory) within the FPGA holds instructions for up to 15 sets. For each set, timing is run, echoes are processed, and a comparison is made. If a target is seen, more detailed processing is run on that set. If no target is seen, the next set is tried. When all sets have been run, the FPGA terminates and waits for the next 50-millisecond event. This setup simplifies testing and improves reliability. A single vertex chip does the work of an entire assembly. Output products require minor processing to become range and velocity. This technology is the heart of the Terminal Descent Sensor, which is an integral part of the Entry Decent and Landing system for MSL. In addition, it is a strong candidate for manned landings on Mars or the Moon.

  12. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  13. TOT Measurement Implemented in FPGA TDC

    CERN Document Server

    Fan, Huanhuan; Liu, Shubin; An, Qi

    2015-01-01

    Time measurement plays a crucial rule for the purpose of particle identification in high energy physical experiments. With the upgrading of physical goal and the developing of electronics, modern time measurement system meets the requirement of excellent resolution specification as well as high integrity. Due to Field Programmable Gate Array (FPGA), FPGA time-to-digital converter (TDC) becomes one of mature and prominent time measurement methods in recent years. For correcting time-walk effect caused by leading timing, time-over-threshold (TOT) measurement should be added in the FPGA TDC. TOT can be obtained by measuring the interval time of signal leading and trailing edge. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels can be used at the same time, one for leading, the other for trailing. However, this method will increase the amount of used FPGA resource and reduce the TDC's integrity unavoidably...

  14. Testing Microshutter Arrays Using Commercial FPGA Hardware

    Science.gov (United States)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  15. Accuracy and Resolution Analysis of a Direct Resistive Sensor Array to FPGA Interface.

    Science.gov (United States)

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2016-02-01

    Resistive sensor arrays are formed by a large number of individual sensors which are distributed in different ways. This paper proposes a direct connection between an FPGA and a resistive array distributed in M rows and N columns, without the need of analog-to-digital converters to obtain resistance values in the sensor and where the conditioning circuit is reduced to the use of a capacitor in each of the columns of the matrix. The circuit allows parallel measurements of the N resistors which form each of the rows of the array, eliminating the resistive crosstalk which is typical of these circuits. This is achieved by an addressing technique which does not require external elements to the FPGA. Although the typical resistive crosstalk between resistors which are measured simultaneously is eliminated, other elements that have an impact on the measurement of discharge times appear in the proposed architecture and, therefore, affect the uncertainty in resistance value measurements; these elements need to be studied. Finally, the performance of different calibration techniques is assessed experimentally on a discrete resistor array, obtaining for a new model of calibration, a maximum relative error of 0.066% in a range of resistor values which correspond to a tactile sensor.

  16. FPGA-based real-time simulation of power converters of renewable energy sources

    Energy Technology Data Exchange (ETDEWEB)

    Kokenyesi, Tamas; Varjasi, Istvan [Budapest University of Technology and Economics, Department of Automation and Applied Informatics (Hungary)], e-mail: kokenyesi.tamas@gmail.com, email: varjasi@aut.bme.hu

    2011-07-01

    This paper presents a hardware-in-the-loop testing (HIL) approach based on a field programmable gate array (FPGA) real-time simulation with real measured signals designed to reduce the cost and time for testing the main circuit of a power converter significantly. This method allows the control unit to measure its outputs on the same signal level in a completely transparent way, unlike other computer based simulation methods. As an example, a simulator for a three-phase inverter used for DC/AC conversion or frequency control is described and the simulated network illustrated. The calculation procedure and relative equations are also detailed, with simulation parameters and some measurement results being presented. It was found that the main advantage of this method is speed, which was only limited by the actual capabilities of the FPGA used. This method can be applied to a wide variety of analog circuits, reducing time to market. More complex circuits and higher frequencies could be simulated in the future with the evolution of FPGAs.

  17. Accuracy and Resolution Analysis of a Direct Resistive Sensor Array to FPGA Interface

    Directory of Open Access Journals (Sweden)

    Óscar Oballe-Peinado

    2016-02-01

    Full Text Available Resistive sensor arrays are formed by a large number of individual sensors which are distributed in different ways. This paper proposes a direct connection between an FPGA and a resistive array distributed in M rows and N columns, without the need of analog-to-digital converters to obtain resistance values in the sensor and where the conditioning circuit is reduced to the use of a capacitor in each of the columns of the matrix. The circuit allows parallel measurements of the N resistors which form each of the rows of the array, eliminating the resistive crosstalk which is typical of these circuits. This is achieved by an addressing technique which does not require external elements to the FPGA. Although the typical resistive crosstalk between resistors which are measured simultaneously is eliminated, other elements that have an impact on the measurement of discharge times appear in the proposed architecture and, therefore, affect the uncertainty in resistance value measurements; these elements need to be studied. Finally, the performance of different calibration techniques is assessed experimentally on a discrete resistor array, obtaining for a new model of calibration, a maximum relative error of 0.066% in a range of resistor values which correspond to a tactile sensor.

  18. Transistor switching and sequential circuits

    CERN Document Server

    Sparkes, John J

    1969-01-01

    Transistor Switching and Sequential Circuits presents the basic ideas involved in the construction of computers, instrumentation, pulse communication systems, and automation. This book discusses the design procedure for sequential circuits. Organized into two parts encompassing eight chapters, this book begins with an overview of the ways on how to generate the types of waveforms needed in digital circuits, principally ramps, square waves, and delays. This text then considers the behavior of some simple circuits, including the inverter, the emitter follower, and the long-tailed pair. Other cha

  19. Implementation of Brushed DC Motor Control in LabVIEW FPGA

    Directory of Open Access Journals (Sweden)

    K. Lamár

    2013-12-01

    Full Text Available The paper introduces the fundamentals of motor control. It explains the basic equations and introduces the control diagram of the brushed DC motor. It introduces the four quadrant DC chopper circuit and the basic methods to operate it. After that, it explains the fundamentals of the current control of DC motors and its two basic methods: the pulse width modulation and the hysteresis current control. Finally it gives a short example of the practical implementation of the hysteresis current controller for the four quadrant DC chopper in LabVIEW FPGA.

  20. High Performance Linear 288×4 CMOS Readout Integrated Circuit with Time-Delay-Integration%具备时间延迟积分的高性能线阵288×4 CMOS读出电路

    Institute of Scientific and Technical Information of China (English)

    高峻; 鲁文高; 刘菁; 唐矩; 崔文涛; 赵宝瑛; 陈中建; 吉利久

    2004-01-01

    描述了一种高性能CMOS线阵288×4读出电路的设计.该读出电路是一个大规模混合信号电路,集成了时间延迟积分以提高信噪比,实现了缺陷像素剔除以提高阵列的可靠性.其他特征包括积分时间可调,多级增益,双向扫描,超采样,以及内建电测试.该芯片采用1.2μm双层多晶硅双层金属CMOS工艺.测量得到的总功耗约为24mW,工作电压5V.%A high performance CMOS linear 288×4 readout integrated circuit(ROIC)is detailed in this paper.It is a large-scale mixed-signal circuit with time-delay integration(TDI)function to enhance the signal to noise ratio(S/N),and defective element deselection(DED)function to decrease the probability of bad columns.The other features include adjustable integration time,multi gain,bi-direction of TDI scan,super-sample,and electrical test.Digital I/O ports are designed to control its work mode.It is fabricated using 1.2μm double poly double metal(DPDM)CMOS technology.The measured power consume is about 24mW at 5 V supply.

  1. FPGA-Based Front-End Electronics for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Dewitt, Don; McDougald, Wendy; Lewellen, Thomas K; Miyaoka, Robert; Hauck, Scott

    2009-02-22

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

  2. Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

    Directory of Open Access Journals (Sweden)

    Oliver TimothyF

    2007-01-01

    Full Text Available A method of constructing prerouted FPGA cores, which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing systems, is presented. Two major challenges are considered: how to manage the wires crossing a core's borders; and how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. In order to maintain FPGA computing performance, it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. We present the first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. We use an abstract FPGA model and CAD tools that mirror those used in industry. An academic design flow has been modified to include a wire policy and an interface constraints framework that tightly constrains the use of the wires that cross a core's boundaries. Using this tool set we investigate the effect of prerouting on overall system optimality. Abutting cores are instantly connected by colocation of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores.

  3. Reconfigurable Optical Directed-Logic Circuits

    Science.gov (United States)

    2015-11-20

    and their switching delays do not accumulate. This is in contrast to conventional logic circuits where gate delays are cascaded, resulting in a...transistor logic circuits wherein gate delays are cascaded resulting in increased latencies with increased logic elements. Thus directed- logic ... reverse biased at -5 V ( logic ‘1’) and the transmission is high when the bias voltage is zero ( logic ‘0’). So the switch works in the block/pass mode

  4. Three-dimensional FPGA Architecture Embedded with IP Cores%引入IP核的三维FPGA结构研究

    Institute of Scientific and Technical Information of China (English)

    唐强; 林郁; 刘洋; 杨海钢

    2016-01-01

    为研究IP核的引入对三维FPGA芯片性能的影响,提出引入IP核同质和粗粒度异质两种三维FPGA结构。首先,利用二维FPGA CAD开源软件构建基于IP核和三维开关盒的三维FPGA CAD工具。然后,利用该工具从定性和定量的角度对不同堆叠层数引入IP核的同质三维FPGA结构进行性能分析。实验发现,随着堆叠层数的增加,关键路径延迟逐渐减小;芯片总面积逐渐增加,单层芯片面积逐渐减小。与引入IP核的同质三维FPGA结构相比,粗粒度异质三维FPGA结构的关键路径延迟更小,表明该结构在减小延时方面的有效性。%In order to fathom the effect on three-dimensional FPGA performance after IP cores are integrated,two FPGA structures are introduced in this paper:homogeneous 3D FPGAs with IP cores and coarse-grained heterogeneous ones.In the first place,we developed a new FPGA CAD tool,which is an upgrade version of a 2D FPGA CAD tool,to support FPGAs based on IP cores and 3D switch boxes,then use it to analyze the homogeneous 3D FPGA performance in different layers in terms of quality and quantity.Experiments reveal the fact that with the number of chip layer increases,total chip area will rise,in the other hand,critical path delay and chip area per layer fall accordingly. Compared to the homogeneous 3D structured FPGAs (with IP cores ), coarse-grained heterogeneous ones have better critical path delay,which proves such structure has the effectiveness on reducing critical path delay.

  5. Design of hand-held digital oscilloscope based on FPGA%基于 FPGA 的手持式数字示波器的设计∗

    Institute of Scientific and Technical Information of China (English)

    朱詠筠; 易艺; 郝建卫; 李俊凯; 王奕澄

    2015-01-01

    According to the weakness of traditional oscilloscope problems such as large volume and inconvenience,the project base on FPGA (Field Programmable Gate Array ) strong performance to develop a hand-held digital oscilloscope.The system use Altera FPGA as the main control chip to design a logic control circuit.And it use the Quartus II development tools and Verilog HDL language to describe the functions such as control logic, clock distribution,sampling buffer,trigger,frequency and amplitude measuring,etc.System design the SOPC Builder to build the Nios II soft core processor,and it through the C language programming to realize the touch control,display control functions.The test result shows that the oscilloscope system work is stable,and it has high performance and practicality.The project has reference value in the research of the hand-held digital oscilloscope.%针对传统示波器体积大、携带不便等问题,利用现场可编程门阵列(field programmable gate array,FPGA)强大的性能,研制一款基于 FPGA 的手持式数字示波器。系统以 Altera 公司 FPGA 为主控芯片组建逻辑控制电路,利用 Quartus II 开发工具以及 Verilog HDL 语言描述控制逻辑,实现时钟分配、采样缓冲、触发、测频、测幅等功能。用SOPC Builder 构建 Nios II 软核处理器,通过 C 语言编程实现触摸控制、显示控制等功能。经过实验测试表明,该示波器系统工作稳定,具有较高的性能指标和实用性,在手持式数字示波器的研制方面有较好的参考价值。

  6. 用于时钟恢复电路的低抖动可变延迟线锁相环电路%A Phase Locked Loop for Clock Recove ry Circuit Using Low-Jitter Variable Delay Line

    Institute of Scientific and Technical Information of China (English)

    李曙光; 朱正; 郭宇华; 任俊彦

    2001-01-01

    A charge pump phase-locked loop(PLL) based on voltage-cont rolleddelay line (VCDL) is presented, which is used to locate the sampling clock edge in the clock recovery circuit. This design is independ ent on environment and process. The improved delay unit in VCDL efficiently lowers the output jitter and a low-pass filter (LPF) is desi gned to avoid the charge-sharing error. Using 0.35 μm TSMC process, the circuit can operates at a low voltage of 3.3 V.In the worst- case condition, simulated jitter of single delay module is 20 ps and static phase error is only 45 ps between input and output.%文中给出了一个基于压控可变延迟线的电荷泵锁相环电路的设计,用于时钟恢复电路中采样时钟沿的定位,它的工作不受环境和工艺的影响,保证了采集数据的准确性。应用于延迟线中的改进的延迟单元有效地减小了相位抖动,环路滤波电路的设计避免了电荷重新分配引入的影响。电路采用0.35μmTSMC的MOS工艺,在3.3V的低电压下工作,模拟得到在最坏情况下,单个延迟模块的相位抖动为20ps,输出静态相位误差仅45ps。

  7. Solid-State dc Circuit Breaker

    Science.gov (United States)

    Harvey, P.

    1983-01-01

    Circuit breaker with no moving parts protects direct-current (dc) loads. Current which circuit breaker opens (trip current) is adjustable and so is time delay before breaker trips. Forward voltage drop rises from 0.6 to 1.2 V as current rises to trip point. Breaker has two terminals, like fuse, therefore replaces fuse in dc circuit. Powered by circuit it protects and reset by either turning off power source or disconnecting load.

  8. Designing and Implementing of Delay- Locked Loop%数字时钟锁相环的设计与实现

    Institute of Scientific and Technical Information of China (English)

    裴志强; 杨玉飞; 刘宝娟

    2012-01-01

    Delay - Locked Loop (DLL) has already got the extremely application in some fields , such as digital communication technology, wireless electronics and electric power automation system etc.. In according to actual condition, we may design special FPCA delay locked loop circuit in high density programmable logic device ( FPCA ). We can make use of device resources and combination some related digital electric circuits together. We not only raise the system integrate and credibility, lower consume and cost, but also make the electric circuit function get the obvious improvement.%数字锁相环电路已在数字通信、无线电电子学及电力系统自动化等领域中得到了极为广泛的应用.在高密度可编程逻辑器件(FPGA)中,根据实际要求,设计FPGA专用数字锁相环电路,可充分利用器件资源,同时把一些相关的数字电路组合在一起,不仅提高了系统的集成度和可靠性,降低了功耗,降低了成本,而且可以使电路性能得到明显改善.

  9. Design issues on using FPGA-based I and C systems in nuclear reactors

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

    2015-07-01

    The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

  10. 基于FPGA的智能小车设计%Design of Intelligent Car Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    高峻; 高向海; 张力行; 王玉花

    2011-01-01

    介绍基于FPGA的智能小车设计,小车包括在FPGA上构建以NiosⅡ嵌入式系统为核心的控制电路、传感器电路、动力及转向电路、LCM电路、温度和湿度测量电路、无线数据收发电路.在Nios Ⅱ集成开发环境(IDE)编写C语言程序,实现能远程遥控小车、自动避障、温度和湿度监测并无线传输至控制端的功能,其特点是能够无线控制小车和远程采集环境信息.%A way to devise an intelligent car based on FPGA is introduced.Nios Ⅱ embedded system taken as central control circuit, sencor circuit, LCM display circuit, temperature and humidity measuring circuit, and wireless data transceiving circuit is built with FPGA in the intteligent car.The C language program is written in Nios Ⅱ integrated development environment (IDE) to realize the car's functions of remote control, automatic avoidance of roadblocks, humidity/temperature monitoring, and data wireless transmission to the controller.Moreover, the highlight of this design is that the car can acquire environmental information remotely and transmit it to the controller wirelessly.

  11. Reversible and quantum circuits optimization and complexity analysis

    CERN Document Server

    Abdessaied, Nabila

    2016-01-01

    This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

  12. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA)

    Science.gov (United States)

    2015-03-01

    EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) CORNELL UNIVERSITY MARCH 2015 FINAL TECHNICAL REPORT APPROVED FOR PUBLIC...From - To) OCT 2011 – OCT 2014 4. TITLE AND SUBTITLE EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) 5a. CONTRACT NUMBER...in collaboration with Albany’s College of Nanoscale Science and Engineering. 15. SUBJECT TERMS 3D Technology, vertical interconnects, AFPGA, FPGA

  13. RSA Power Analysis Obfuscation: A Dynamic FPGA Architecture

    Science.gov (United States)

    2012-03-01

    research provides a VHDL coded dynamic architecture for synthesization on a Xilinx Virtex-5 FPGA. This architecture provides two-way communication...Component Under Test (CUT) is the dynamic RSA implementation. This dynamic hardware is synthesized from VHDL onto a Xilinx Virtex-5 FPGA. The built in...The hardware platform used for this research is a the Xil- inx Virtex-5 FX FPGA. VHDL code is synthesized using the Xilinx design suite and downloaded

  14. Sequence Convergence and Clock Switching in FPGA Disigning%FPGA设计中的时序收敛与时钟切换

    Institute of Scientific and Technical Information of China (English)

    梅建超

    2011-01-01

    FPGA作为最为广泛使用的可编程器件,已经广泛存在于我们的数字电路设计工作中。但是如果对FPGA缺乏深入了解,将严重影响FPGA实际工作的可靠性。本文介绍了FPGA设计中需要着重考虑的两个问题及解决方法。%Being a most widely used programmable component ,FPGA is widely used in our daily working while it is referred to digit circuit designing.But FPGA will be working in a unreliable condition ,if we do not know incide it very well. This papeKey words: FPGA S

  15. Speeding Up FPGA Placement via Partitioning and Multithreading

    Directory of Open Access Journals (Sweden)

    Cristinel Ababei

    2009-01-01

    placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

  16. GLITCH ANALYSIS AND REDUCTION IN DIGITAL CIRCUITS

    Directory of Open Access Journals (Sweden)

    Ronak Shah

    2016-08-01

    Full Text Available Hazard in digital circuits is unnecessary transitions due to gate propagation delay in that circuit. Hazards occur due to uneven delay offered in the path of the various ongoing signals. One of the important reasons for power dissipation in CMOS circuits is the switching activity .This include activities such as spurious pulses, called glitches. Power optimization techniques that concentrate on the reduction of switching power dissipation of a given circuit are called glitch reduction techniques. In this paper, we analyse various Glitch reduction techniques such as Hazard filtering Technique, Balanced Path Technique, Multiple Threshold Technique and Gate Freezing Technique. We also measure the parameters such as noise and delay of the circuits on application of various techniques to check the reliability of different circuits in various situations.

  17. Continuous Attributes Discretization Algorithm based on FPGA

    Directory of Open Access Journals (Sweden)

    Guoqiang Sun

    2013-07-01

    Full Text Available The paper addresses the problem of Discretization of continuous attributes in rough set. Discretization of continuous attributes is an important part of rough set theory because most of data that we usually gain are continuous data. In order to improve processing speed of discretization, we propose a FPGA-based discretization algorithm of continuous attributes making use of the speed advantage of FPGA. Combined attributes dependency degree of rough ret, the discretization system was divided into eight modules according to block design. This method can save much time of pretreatment in rough set and improve operation efficiency. Extensive experiments on a certain fighter fault diagnosis validate the effectiveness of the algorithm.  

  18. 3D FFTs on a Single FPGA.

    Science.gov (United States)

    Humphries, Benjamin; Zhang, Hansen; Sheng, Jiayi; Landaverde, Raphael; Herbordt, Martin C

    2014-05-01

    The 3D FFT is critical in many physical simulations and image processing applications. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multi-grid. We find the opposite: a simple design, operating at a conservative frequency, takes 4μs for 16(3), 21μs for 32(3), and 215μs for 64(3) single precision data points. The first two of these compare favorably with the 25μs and 29μs obtained running on a current Nvidia GPU. Some broader significance is that this is a critical piece in implementing a large scale FPGA-based MD engine: even a single FPGA is capable of keeping the FFT off of the critical path for a large fraction of possible MD simulations.

  19. An FPGA helix tracking algorithm for PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Galuska, Martin; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liang, Yutie; Liu, Ming; Spruck, Bjoern [Justus Liebig University Giessen (Germany); Spataro, Stefano [University of Torino (Italy)

    2010-07-01

    An online track finder for the PANDA experiment at the future FAIR facility was developed and tested. The central Panda tracking detectors for charged particles will consist of a silicon based micro vertex detector (MVD, 5-7 hits/track) and possibly of a straw tube tracker (STT, 15 double layers of straws). Due to the solenoidal magnetic field, tracks of charged particles can be parametrized by a helix (if neglecting energy loss). The algorithm works in several steps. Perpendicular to the beam direction the projection of the tracks is equivalent to a circle. Thus, first a conformal transformation will be used to convert the circles to straight lines. Second, a Hough transform is used to find the straight lines by a peak finding algorithm. Along the beam direction, a different Hough transformation is used. As the algorithm was developed for an FPGA, it uses lookup tables. Possible FPGA implementation is discussed.

  20. An FPGA-based Torus Communication Network

    CERN Document Server

    Pivanti, Marcello; Simma, Hubert

    2010-01-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results.

  1. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  2. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  3. A component-based FPGA design framework for neuronal ion channel dynamics simulations.

    Science.gov (United States)

    Mak, Terrence S T; Rachmuth, Guy; Lam, Kai-Pui; Poon, Chi-Sang

    2006-12-01

    Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field-programmable gate array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the alpha-amino-3-hydroxy-5-methyl-4-isoxazole propionic acid (AMPA) and N-methyl-D-aspartate (NMDA) synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution, as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired.

  4. A FPGA Implementation of JPEG Baseline Encoder for Wearable Devices.

    Science.gov (United States)

    Li, Yuecheng; Jia, Wenyan; Luan, Bo; Mao, Zhi-Hong; Zhang, Hong; Sun, Mingui

    2015-04-01

    In this paper, an efficient field-programmable gate array (FPGA) implementation of the JPEG baseline image compression encoder is presented for wearable devices in health and wellness applications. In order to gain flexibility in developing FPGA-specific software and balance between real-time performance and resources utilization, A High Level Synthesis (HLS) tool is utilized in our system design. An optimized dataflow configuration with a padding scheme simplifies the timing control for data transfer. Our experiments with a system-on-chip multi-sensor system have verified our FPGA implementation with respect to real-time performance, computational efficiency, and FPGA resource utilization.

  5. High resolution digital delay timer

    Science.gov (United States)

    Martin, Albert D.

    1988-01-01

    Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay (20) provides a first output signal (24) at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits (26, 28) latch the high resolution data (24) to form a first synchronizing data set (60). A selected time interval has been preset to internal counters (142, 146, 154) and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses (32, 34) count down the counters to generate an internal pulse delayed by an interval which is functionally related to the preset time interval. A second LCD (184) corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD (74) to generate a second set of synchronizing data (76) which is complementary with the first set of synchronizing data (60) for presentation to logic circuits (64). The logic circuits (64) further delay the internal output signal (72) to obtain a proper phase relationship of an output signal (80) with the internal pulses (32, 34). The final delayed output signal (80) thereafter enables the output pulse generator (82) to produce the desired output pulse (84) at the preset time delay interval following input of the trigger pulse (10, 12).

  6. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  7. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  8. TOT measurement implemented in FPGA TDC

    Science.gov (United States)

    Fan, Huan-Huan; Cao, Ping; Liu, Shu-Bin; An, Qi

    2015-11-01

    Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates. Supported by National Natural Science Foundation of China (11079003, 10979003)

  9. AREA OPTIMIZED FPGA IMPLEMENTATION OF ADAPTIVE BEAMFORMER

    Directory of Open Access Journals (Sweden)

    Harpreet Kaur

    2012-06-01

    Full Text Available Quadratic Rotation decomposition (QRD based recursive least squares (RLS algorithm can be used in variety of communication applications and its low complexity implementation can be of interest. In this paper we have presented an application of QRD based RLS algorithm using Coordinate Rotation by Digital Computer (CORDIC operator for implementing an adaptive beamformer. FPGA resource estimates along with actual implementation results have been presented and are being compared with its existing implementation.

  10. Implementation of Huffman Decoder on Fpga

    OpenAIRE

    Safia Amir Dahri; Dr Abdul Fattah Chandio

    2016-01-01

    Lossless data compression algorithm is most widely used algorithm in data transmission, reception and storage systems in order to increase data rate, speed and save lots of space on storage devices. Now-a-days, different algorithms are implemented in hardware to achieve benefits of hardware realizations. Hardware implementation of algorithms, digital signal processing algorithms and filter realization is done on programmable devices i.e. FPGA. In lossless data compression algorith...

  11. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  12. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  13. Implementing a Digital Phasemeter in an FPGA

    Science.gov (United States)

    Rao, Shanti R.

    2008-01-01

    Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses, the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains. The firmware also does the following: Causes the FPGA to compute the frequencies of the input signals; Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and Provides data for use in diagnosis of communication failures. The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.

  14. Implementation of Huffman Decoder on Fpga

    Directory of Open Access Journals (Sweden)

    Safia Amir Dahri

    2016-01-01

    Full Text Available Lossless data compression algorithm is most widely used algorithm in data transmission, reception and storage systems in order to increase data rate, speed and save lots of space on storage devices. Now-a-days, different algorithms are implemented in hardware to achieve benefits of hardware realizations. Hardware implementation of algorithms, digital signal processing algorithms and filter realization is done on programmable devices i.e. FPGA. In lossless data compression algorithms, Huffman algorithm is most widely used because of its variable length coding features and many other benefits. Huffman algorithms are used in many applications in software form, e.g. Zip and Unzip, communication, etc. In this paper, Huffman algorithm is implemented on Xilinx Spartan 3E board. This FPGA is programmed by Xilinx tool, Xilinx ISE 8.2i. The program is written in VHDL and text data is decoded by a Huffman algorithm on Hardware board which was previously encoded by Huffman algorithm. In order to visualize the output clearly in waveforms, the same code is simulated on ModelSim v6.4. Huffman decoder is also implemented in the MATLAB for verification of operation. The FPGA is a configurable device which is more efficient in all aspects. Text application, image processing, video streaming and in many other applications Huffman algorithms are implemented.

  15. High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

    Directory of Open Access Journals (Sweden)

    Hai Wang

    2017-01-01

    Full Text Available This paper presents the design and implementation of a new digital-to-time converter (DTC. The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL and integral nonlinearity (INL are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA chip.

  16. The characterization and application of a low resource FPGA-based time to digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

    2014-03-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

  17. A Fast Floating Point Double Precision Implementation on Fpga

    Directory of Open Access Journals (Sweden)

    Monika Maan

    2016-06-01

    Full Text Available In the modern day digital systems, floating point units are an important component in many signal and image processing applications. Many approaches of the floating point units have been proposed and compared with their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for floating point operations, single and double. In the proposed architecture double precision floating point unit is used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high speed adder, which is shared among other operations and can perform operations independently as a separate unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing technique which allows performing the operations with the minimum usage of the resources while computing the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results show the 23% improvement in the speed of the designed circuit.

  18. FPGA based digital backend system for the Gauribidanur Radioheliograph

    Science.gov (United States)

    Barve, Indrajit V.; Sarpotadar, Mayuresh; Sundara Rajan, M. S.; Ramesh, R.; Kathiravan, C.

    The Indian Institute of Astrophysics operates a low frequency (radio observatory (≈ 77°E 14°N) located about 100 km north of Bangalore (Ramesh et al. 1998; Ramesh 2011). The basic receiving element in the radioheliograph (called the Gauribidanur RAdioheliograPH, GRAPH) is a log-periodic dipole (LPD). The array has 384 of them arranged in a 'T' configuration. The arms of the `T' are in the east-west and north-south directions. The LPDs in the each of the above two arms are subdivided into 32 groups. RF signal from the 64 antenna groups in the array are presently correlated using a 4096-channel correlator system comprising of discrete digital circuit elements (Ramesh et al. 2006). Taking advantage of the developments in the field of signal processing, a FPGA based digital backend system is being developed for the GRAPH. To this date, a prototype 8-channel system has been designed and fabricated. All possible correlations between signals from 8 different antenna groups can be performed with this system either online or offline. http://www.iiap.res.in/centers/radio

  19. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  20. Evaluation of ATM Functioning Using VHDL and FPGA

    Directory of Open Access Journals (Sweden)

    Manali Dhar

    2015-06-01

    Full Text Available It has been almost four decades that banks and other financial organizations have been gradually computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of services for the customer. This method uses a computer to transfer debits and credits, with the help of electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated Teller Machine has become an important part in our daily lives. People use ATM for various purposes such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's money, it has to be a secure system on which we can rely. We have taken a step towards increasing this security and integrity by trying to implement the functioning of an ATM using VLSI-based programming, HDL(Hardware Description Language.The conventional coding languages such as C,C++ are replaced by VHDL(Very High Speed Integrated Circuit Hardware Description Language so that the code cannot be easily hacked or changed. This article consists of an insight into the various functions that can be performed using an ATM, a brief description of the Coding and the obtained simulation results. It also consists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50.

  1. A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

    Science.gov (United States)

    Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

    2015-08-01

    A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

  2. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    Science.gov (United States)

    Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

    2016-01-01

    Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  3. Complicated Electric Circuit P-T Calculus Model Based on VHDL%基于VHDL的复杂电路的P-T算法模型

    Institute of Scientific and Technical Information of China (English)

    刘丹非; 李曼义; 郭金怀

    2003-01-01

    When we design electric circuit with the hardware describe language VHDL,if the control of the electriccircuit is more than to calculate,we can design electric circuit as a controller which is based on multiplexer and is di-vided into the space part and the time part. Electric circuit is synthesized and form CPLD or FPGA circuit by adjustingthe P- T arithmetic model. We explain this method by designing the controller of CPU as a example.

  4. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  5. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    Institute of Scientific and Technical Information of China (English)

    Zhao Yan; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Zhao Kai; Stanley L.Chen; Yu Fang; Liu Zhongli; Wu Lihua; Han Xiaowei; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based fieldprogrammable gate array (FPGA) VS1000,which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute.Corresponding with the characteristics of the FPGA,each IOB includes a local routing pool and two IO cells composed of a signal path circuit,configurable input/output buffers and an ESD protection network.A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes.Programmable IO buffers can be used at TTL/CMOS standard levels.The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic.Radiation-hardened designs,including A-type and H-type body-tied transistors and special D-type registers,improve the anti-radiation performance.The ESD protection network,which provides a high-impulse discharge path on a pad,prevents the breakdown of the core logic caused by the immense current.These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs.The functionality and performance of the IOB array is proved after a functional test.The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si),a dose survivability rate of 1.5 × 1011 rad(Si)/s,and a neutron fluence immunity of 1 × 1014 n/cm2.

  6. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    Science.gov (United States)

    Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

  7. Real-time energy measurement of high repetition rate ultrashort laser pulses using pulse integration and FPGA processing.

    Science.gov (United States)

    Tang, Qi-Jie; Yang, Dong-Xu; Wang, Jian; Feng, Yi; Zhang, Hong-Fei; Chen, Teng-Yun

    2016-11-01

    Real-time energy measurement using pulse integration method for high repetition rate ultrashort laser pulses based on FPGA (Field-Programmable Gate Array) and high-speed pipeline ADC (Analog-to-Digital Convertor) is introduced in this paper. There are two parts contained in this method: pulse integration and real-time data processing. The pulse integration circuit will convert the pulse to the step type signals which are linear to the laser pulse energy. Through the real-time data processing part, the amplitude of the step signals will be obtained by ADC sampling and conducting calculation in real time in FPGA. The test result shows that the method with good linearity (4.770%) and without pulse measurement missing is suitable for ultrashort laser pulses with high repetition rate up to 100 MHz.

  8. Real-time energy measurement of high repetition rate ultrashort laser pulses using pulse integration and FPGA processing

    Science.gov (United States)

    Tang, Qi-jie; Yang, Dong-xu; Wang, Jian; Feng, Yi; Zhang, Hong-fei; Chen, Teng-yun

    2016-11-01

    Real-time energy measurement using pulse integration method for high repetition rate ultrashort laser pulses based on FPGA (Field-Programmable Gate Array) and high-speed pipeline ADC (Analog-to-Digital Convertor) is introduced in this paper. There are two parts contained in this method: pulse integration and real-time data processing. The pulse integration circuit will convert the pulse to the step type signals which are linear to the laser pulse energy. Through the real-time data processing part, the amplitude of the step signals will be obtained by ADC sampling and conducting calculation in real time in FPGA. The test result shows that the method with good linearity (4.770%) and without pulse measurement missing is suitable for ultrashort laser pulses with high repetition rate up to 100 MHz.

  9. A Multi-chain Measurements Averaging TDC Implemented in a 40 nm FPGA

    CERN Document Server

    Shen, Qi; Qi, Binxiang; An, Qi; Liao, Shengkai; Peng, Chengzhi; Liu, Weiyue

    2014-01-01

    A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.

  10. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele...

  11. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, Marcel A.; Zuijlen, van Jasper J.P.; Broenink, Jan F.

    2008-01-01

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control s

  12. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  13. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA...

  14. FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics

    CERN Document Server

    INSPIRE-00225390; Hu, Xueye; Schwarz, Thomas; Zhu, Junjie; Chapman, J.W.; Dai, Tiesheng; Zhou, Bing

    2015-01-01

    We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.

  15. Development of True Time Delay Circuits

    Science.gov (United States)

    2014-06-13

    Samsung Electro- Mechanics America, Inc CAP CER 1UF 6.3V 5% X5R 0402 CL05A105JQ 5NNNC 1276-1444-1- ND 3 4 C4,C9,C14,C1 6 Murata Electronics...North America CAP CER 10000PF 16V 10% X7R 0402 BLM15HD10 2SN1D 1276-1500-1- ND 4 3 C5,C10,C15 Samsung Electro- Mechanics America, Inc CAP...040B050BA 445-4876-1- ND 6 2 C19,C20 TDK Corporation CAP CER 3PF 50V NP0 0402 C1005C0G1H 030B050BA 445-4869-1- ND 7 3 C21,C25,C28 Samsung Electro

  16. Programmable delay circuit for sparker signal analysis

    Digital Repository Service at National Institute of Oceanography (India)

    Pathak, D.

    The sparker echo signal had been recorded along with the EPC recorder trigger on audio cassettes in a dual channel analog recorder. The sparker signal in the analog form had to be digitised for further signal processing techniques to be performed...

  17. Application of Remote FPGA Dynamic Reconfiguration System in LED Lighting

    Institute of Scientific and Technical Information of China (English)

    LI Wei; WANG Wei; NIU Ping-juan; ZHANG li-ping

    2009-01-01

    The dynamic reconfiguration technique based on field-programmable gate array (FPGA) can improve the resource utilization.Discussed are the dynamic reconfiguration principles and methods.Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet Physical layer transceiver(PHY).The hardware of the system is designed with Xilinx Virtex-II XC2V30P FPGA that embedds MicroBlaze and MAC IP core,and its network communication software based on transmission control protocol/Internet protocol (TCP/IP) protocol is programmed by loading LwlP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system(RFDRS) can switch freely in the eight lighting modes of light emitting diodes (LED),and that,using dynamic reconfiguration technology,FPGA resource utilization can be reduced remarkably,which is advantageous in the system upgrade and software update.

  18. Low resource FPGA-based Time to Digital Converter

    CERN Document Server

    Balla, A; Ciambrone, P; Gatta, M; Gonnella, F; Iafolla, L; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2...

  19. The FPGA Implementation of Short—Wave Channel Model

    Institute of Scientific and Technical Information of China (English)

    GANLiangcai; LIYuanyuan

    2003-01-01

    Based on the characteristic of timevariance,short-wave channel can be modeled as a real-time tors of fllter in frequency domain,the model can simulate short-wave channel exactly,such as delay spread,Doppler shift and Doppler spread.In the design,the bandwidth of short-wave channel model is 768kHz,and the frequency interval is 3kHz.A kind of Overlap-Discard algorithm based on the fast Fourier transform (FFT)is utilized to design the real-time FIR filter,and an architectural design structure based on Field Programmable Gate Arrays(FPGA)chip is adopted to implement 512-point FFT.The channel transfer function and the noise and interference function are periodically updated in real-time,which are stored in ROM in advance.The simulation result shows that the hardware implementation is simple and feasible and the wideband short-wave systems,such as frequency-hopping,direct sequence spread spectrum systems.

  20. Non-Destructive Investigation on Short Circuit Capability of Wind-Turbine-Scale IGBT Power Modules

    DEFF Research Database (Denmark)

    Wu, Rui; Iannuzzo, Francesco; Wang, Huai

    2014-01-01

    This paper presents a comprehensive investigation on the short circuit capability of wind-turbine-scale IGBT power modules by means of a 6 kA/1.1 kV non-destructive testing system. A Field Programmable Gate Array (FPGA) supervising unit is adpoted to achieve an accurate time control for short...

  1. STRS SpaceWire FPGA Module

    Science.gov (United States)

    Lux, James P.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.

    2011-01-01

    An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

  2. GATING CIRCUITS

    Science.gov (United States)

    Merrill, L.C.

    1958-10-14

    Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

  3. A digital pulsar backend based on FPGA

    Science.gov (United States)

    Luo, Jin-Tao; Chen, Lan; Han, Jin-Lin; Esamdin, Ali; Wu, Ya-Jun; Li, Zhi-Xuan; Hao, Long-Fei; Zhang, Xiu-Zhong

    2017-01-01

    A digital pulsar backend based on a Field Programmable Gate Array (FPGA) is developed. It is designed for incoherent de-dispersion of pulsar observations and has a maximum bandwidth of 512 MHz. The channel bandwidth is fixed to 1 MHz, and the highest time resolution is 10 {{μ }} s. Testing observations were carried out using the Urumqi 25-m telescope administered by Xinjiang Astronomical Observatory and the Kunming 40-m telescope administered by Yunnan Observatories, targeting PSR J0332+5434 in the L band and PSR J0437–4715 in the S band, respectively. The successful observation of PSR J0437–4715 demonstrates its ability to observe millisecond pulsars.

  4. Research and design of the protection circuits in LD controller

    Institute of Scientific and Technical Information of China (English)

    SHAN Jiang-dong; TIAN Xiao-jian; DENG Jun; ZHANG Shuang

    2006-01-01

    According to the parameters and applications of laser diode (LD), three protection circuits were designed: the time-delay soft-start protection circuit, the power-on impulse protection circuit and the limit-current protection circuit. In this article, the structure and the principle of every protection circuit have been detailed. From several tests and feedbacks from customers, the expected goals have been completed.

  5. Time-domain nature of group delay

    Institute of Scientific and Technical Information of China (English)

    王建武; 冯正和

    2015-01-01

    The characteristic of group delay is analyzed based on an electronic circuit, and its time-domain nature is studied with time-domain simulation and experiment. The time-domain simulations and experimental results show that group delay is the delay of the energy center of the amplitude-modulated pulse, rather than the propagation delay of the electromagnetic field. As group velocity originates from the definition of group delay and group delay is different from the propagation delay, the superluminality or negativity of group velocity does not mean the superluminal or negative propagation of the electromagnetic field.

  6. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

    OpenAIRE

    Abdulrazzaq, Bilal I.; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, ...

  7. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  8. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  9. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  10. A FAULT TOLERANT FPGA BASED IMAGE ENHANCEMENT FILTER USING SELF HEALING ALGORITHM

    Directory of Open Access Journals (Sweden)

    K.SRI RAMA KRISHNA,

    2010-09-01

    Full Text Available An original approach to automatic design of image filters is presented in this paper. The proposed solution employs Field Programmable Gate Array reconfigurable hardware at simplified functional level and produces high quality image when image features are corrupted by different types of noise. In addition, parallel architectures can be used to ease the enormous computational load due to different operations conducted on image data sets. Self healing circuit is the one which can compete against traditional designs in terms of quality and implementation cost in Xilinx’s chips. During the first phase, schemes for testing the configured processing elements of a reconfigurable circuit evolved for image enhancement application is presented. In the second phase, the internal Processing Elements in evolved circuit found faulty, they are restructured such that the sparse processing elements replace the faulty processing elements both functionally and structurally. Simulation results show that the evolved circuit is inherently testable and can restructure itself by avoiding the faulty ProcessingElements and make use of sparse ones. In third phase implantation of FPGA based image enhancement filter using Virtex-IV application board.

  11. Optimization of reversible sequential circuits

    CERN Document Server

    Sayem, Abu Sadat Md

    2010-01-01

    In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.

  12. Time-delay feedback control in a delayed dynamical chaos system and its applications

    Institute of Scientific and Technical Information of China (English)

    Ye Zhi-Yong; Yang Guang; Deng Cun-Bing

    2011-01-01

    The feedback control of a delayed dynamical system, which also includes various chaotic systems with time delays, is investigated. On the basis of stability analysis of a nonautonomons system with delays, some simple yet less conservative criteria are obtained for feedback control in a delayed dynamical system. Finally, the theoretical result is applied to a typical class of chaotic Lorenz system and Chua circuit with delays. Numerical simulations are also given to verify the theoretical results.

  13. Low cost FPGA based data acquisition system for a gamma imaging probe

    Science.gov (United States)

    Fysikopoulos, E.; Georgiou, M.; Loudos, G.; Matsopoulos, G.

    2013-11-01

    We present the development of a low cost field programmable gate arrays (FPGA) based data acquisition system for a gamma imaging probe proposed for sentinel lymph node (SLN) mapping. Radioguided surgery using a gamma probe is an established practice and has been widely introduced in SLN biopsies. For such applications, imaging systems require compact readout electronics and flexibility. Embedded systems implemented in the FPGA technology offer new possibilities in data acquisition for nuclear medicine imagers. FPGAs are inexpensive compared to application specific integrated circuits (ASICs), usually used for the readout electronics of dedicated gamma cameras and their size is rather small. In this study, cost effective analog to digital converters (ADCs) were used and signal processing algorithms were implemented in the FPGA to extract the energy and position information. The analog front-end electronics were carefully designed taking into account the low sampling rate of the ADCs. The reference gamma probe has a small field of view (2.5 cm × 2.5 cm) and is based on the R8900U-00-C12 position sensitive photomultiplier tube (PSPMT) coupled to a pixellated CsI(Na) scintillator with 1 mm × 1 mm × 5 mm crystal element size. Measurements were carried out using a general purpose collimator and 99mTc sources emitted at 140 keV. Performance parameters for the imaging gamma probe were compared with those obtained when data were acquired using the standard NIM (Nuclear Instrumentation Modules) electronics and found to be in very good agreement, which demonstrates the efficiency of the proposed implementation.

  14. FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

    Energy Technology Data Exchange (ETDEWEB)

    Suratia, Pooja, E-mail: poojasuratia@yahoo.com [Electrical Engineering Department, Faculty of Technology and Engineering, The Maharaja Sayajirao University of Baroda, Kalabhavan, Vadodara 390001, Gujarat (India); Patel, Jigneshkumar, E-mail: jjp@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India); Rajpal, Rachana, E-mail: rachana@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India); Kotia, Sorum, E-mail: smkotia-eed@msubaroda.ac.in [Electrical Engineering Department, Faculty of Technology and Engineering, The Maharaja Sayajirao University of Baroda, Kalabhavan, Vadodara 390001, Gujarat (India); Govindarajan, J., E-mail: govindarajan@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India)

    2012-11-15

    Highlights: Black-Right-Pointing-Pointer Evaluation and comparison of the working performance of FLC is done with that of PID Controller. Black-Right-Pointing-Pointer FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. Black-Right-Pointing-Pointer FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. Black-Right-Pointing-Pointer Developed FLC controller is able to maintain the plasma column within required range of {+-}0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional-Integral-Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

  15. 声光控延时开关电路的设计与制作%The Design and Manufacture of the Circuit of Delay Switches Controlled by Sound and Light

    Institute of Scientific and Technical Information of China (English)

    耿子庆

    2016-01-01

    本文主要介绍了具有声控、光控以及带有延时作用的节电开关的设计与制作.从爱迪生发明了电灯泡以来,电灯的照明技术就开始飞速发展,现代的电子技术科研人员研究出各式各样功能的电灯用来照明,使照明技术更加自动化,更加智能化,同时也越来越好地为人们生活服务.它不仅能适用于居民住宅,而且也适用于大型工厂、学校等公共场所,具有形状美观、体积小巧、制作简单、工作性能好、节约能源等优点.主要由整流、滤波、稳压和集成电路以及光敏电阻等元件组成.%This paper mainly introduces the design and fabrica-tion of power-saving switches with sound and light control and the delay function controlled by sound and light. Since the inven-tion of electric bulbs by Edison, the lighting technology of electric lights has been developing rapidly, and modern scientific re-searchers of electronic technology are starting to research all kinds of electric lights with various functions, making lighting technology more automatic and intelligent and better serve peo-ple's life. With a beautiful appearance, small size, simple tech-nique, good working performance and energy-saving function, it is not only suitable for the residential buildings, but also suitable for public places such as large factories, schools and so on. It mainly consists of such parts as rectifier, filter, voltage regulator and integrated circuits as well as photosensitive resistance.

  16. Six Channel Digital Delay Generator

    Science.gov (United States)

    1980-01-01

    Historically, delays were generated by R-C networks that fired thyratrons to provide the re- quired output pulses. Because of severe electrical interference...instruction manual. The system clock was an M. F. electronics model 5401-1 in a printed circuit mounting package. This particular model has a 10 MHz...constructed in-house to provide the high voltages required to trip flash x-ray systems and thyratron controlled firing units. Details of this circuit are

  17. FPGA Fuzzy Controller Design for Magnetic Ball Levitation

    Directory of Open Access Journals (Sweden)

    Basil Hamed

    2012-09-01

    Full Text Available this paper presents a fuzzy controller design for nonlinear system using FPGA. A magnetic levitation system is considered as a case study and the fuzzy controller is designed to keep a magnetic object suspended in the air counteracting the weight of the object. Fuzzy controller will be implemented using FPGA chip. The design will use a high-level programming language HDL for implementing the fuzzy logic controller using the Xfuzzy tools to implement the fuzzy logic controller into HDL code. This paper, advocates a novel approach to implement the fuzzy logic controller for magnetic ball levitation system by using FPGA.

  18. FPGA Implementation of ADPLL with Ripple Reduction Techniques

    Directory of Open Access Journals (Sweden)

    Manoj kumar

    2012-05-01

    Full Text Available In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

  19. FPGA Implementation of ADPLL with Ripple Reduction Techniques

    Directory of Open Access Journals (Sweden)

    Manoj Kumar

    2012-04-01

    Full Text Available In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

  20. 一种基于与非锥簇架构FPGA输入交叉互连设计优化方法%An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA

    Institute of Scientific and Technical Information of China (English)

    黄志洪; 李威; 杨立群; 江政泓; 魏星; 林郁; 杨海钢

    2016-01-01

    In order to break through the bottleneck of the huge cluster area in AIC (And-Inverter Cone) architecture based FPGA, the research on the optimisation of the input crossbar architecture is carried on. A post-pack netlist statistics method is creatively proposed to analyze the utilization of AIC cluster inputs and feedbacks and to guide the input crossbar design. And on the architecture parameter design level, it is firstly proposed to separately design the connective probability of the AIC cluster inputs and feedbacks. Through substantial experiments, optimum connective probability combination is derived. From the circuit implement view, dual-phases multiplexer input crossbar is presented according to the characteristics of AIC. The area of the AIC cluster, optimized through the proposed approach, achieves 21.21% smaller than the original one, the huge area problem is markedly ameliorated. When implementing the MCNC and VTR benchmarks, compared to Stratix IV, LUT based FPGA from Altera, the area-delay product of the AIC FPGA after optimisation is reduced by 48.49% and 26.29%, respectively. Compared to the original AIC-based FPGA architecture, the area-delay product is reduced by 28.48%and 28.37%, respectively.%该文针对与非锥(And-Inverter Cone, AIC)簇架构FPGA开发中面临的簇面积过大的瓶颈问题,对其输入交叉互连设计优化进行深入研究,在评估优化流程层次,首次创新性提出装箱网表统计法对AIC簇输入和反馈资源占用情况进行分析,为设计及优化输入交叉互连结构提供指导,以更高效获得优化参数。针对输入交叉互连模块,在结构参数设计层次,首次提出将引脚输入和输出反馈连通率分离独立设计,并通过大量的实验,获得最优连通率组合。在电路设计实现层次,有效利用AIC逻辑锥电路结构特点,首次提出双相输入交叉互连电路实现。相比于已有的AIC簇结构,通过该文提出的优化方

  1. Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

    Energy Technology Data Exchange (ETDEWEB)

    Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [PONUTech Co., Seoul (Korea, Republic of)

    2015-10-15

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket.

  2. Fractional linear systems and electrical circuits

    CERN Document Server

    Kaczorek, Tadeusz

    2015-01-01

    This monograph covers some selected problems of positive and fractional electrical circuits composed of resistors, coils, capacitors and voltage (current) sources. The book consists of 8 chapters, 4 appendices and a list of references. Chapter 1 is devoted to fractional standard and positive continuous-time and discrete-time linear systems without and with delays. In chapter 2 the standard and positive fractional electrical circuits are considered and the fractional electrical circuits in transient states are analyzed.  Descriptor linear electrical circuits and their properties are investigated in chapter 3,  while chapter 4 is devoted to the stability of fractional standard and positive linear electrical circuits. The reachability, observability and reconstructability of fractional positive electrical circuits and their decoupling zeros are analyzed in chapter 5. The fractional linear electrical circuits with feedbacks are considered in chapter 6. In chapter 7 solutions of minimum energy control for standa...

  3. An FPGA Implementation of a Robot Control System with an Integrated 3D Vision System

    Directory of Open Access Journals (Sweden)

    Yi-Ting Chen

    2015-05-01

    Full Text Available Robot decision making and motion control are commonly based on visual information in various applications. Position-based visual servo is a technique for vision-based robot control, which operates in the 3D workspace, uses real-time image processing to perform tasks of feature extraction, and returns the pose of the object for positioning control. In order to handle the computational burden at the vision sensor feedback, we design a FPGA-based motion-vision integrated system that employs dedicated hardware circuits for processing vision processing and motion control functions. This research conducts a preliminary study to explore the integration of 3D vision and robot motion control system design based on a single field programmable gate array (FPGA chip. The implemented motion-vision embedded system performs the following functions: filtering, image statistics, binary morphology, binary object analysis, object 3D position calculation, robot inverse kinematics, velocity profile generation, feedback counting, and multiple-axes position feedback control.

  4. Force to rebalance control of HRG and suppression of its errors on the basis of FPGA.

    Science.gov (United States)

    Wang, Xu; Wu, Wenqi; Luo, Bing; Fang, Zhen; Li, Yun; Jiang, Qingan

    2011-01-01

    A novel design of force to rebalance control for a hemispherical resonator gyro (HRG) based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  5. Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    SKLYAROV, V.

    2014-05-01

    Full Text Available This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations. Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.

  6. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA

    Directory of Open Access Journals (Sweden)

    Qingan Jiang

    2011-12-01

    Full Text Available A novel design of force to rebalance control for a hemispherical resonator gyro (HRG based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  7. Delay modeling in logic simulation

    Energy Technology Data Exchange (ETDEWEB)

    Acken, J. M.; Goldstein, L. H.

    1980-01-01

    As digital integrated circuit size and complexity increases, the need for accurate and efficient computer simulation increases. Logic simulators such as SALOGS (SAndia LOGic Simulator), which utilize transition states in addition to the normal stable states, provide more accurate analysis than is possible with traditional logic simulators. Furthermore, the computational complexity of this analysis is far lower than that of circuit simulation such as SPICE. An eight-value logic simulation environment allows the use of accurate delay models that incorporate both element response and transition times. Thus, timing simulation with an accuracy approaching that of circuit simulation can be accomplished with an efficiency comparable to that of logic simulation. 4 figures.

  8. Temperature Dependent Wire Delay Estimation in Floorplanning

    DEFF Research Database (Denmark)

    Winther, Andreas Thor; Liu, Wei; Nannarelli, Alberto;

    2011-01-01

    Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this w......Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability...

  9. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  10. Rad-Hard and ULP FPGA with "Full" Functionality Project

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  11. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  12. A design of FPGA based intelligent data handling interfacing card.

    Directory of Open Access Journals (Sweden)

    Anandaraj D

    2015-05-01

    Full Text Available With the increasing demand in the custom built logic for avionics systems, FPGA is used in this proposed interfacing card design. This FPGA based intelligent data handling card (IDHC for the IVHM system, will interface the data from aircraft subsystems to the aircraft digital data bus. This IDHC interfacing card is based on the Virtex-5 FPGA (Field Programmable Gate Array, which provides flexibility by re-programming, so that it can be configured to the required functionality. Fault detection can be done within the FPGA and only the anomalies passed to the computer, so that the bus bandwidth can be utilized effectively and also excessive wiring can be eliminated, that would have been required for multiple individual systems. The work concentrates on designing the schematic using OrCAD.

  13. Study and Implementation of MUX Based FPGA in QCA Technology

    Directory of Open Access Journals (Sweden)

    E.N.Ganesh

    2011-06-01

    Full Text Available This paper presents a simple Multiplexer based Field programmable gate arrays with interconnectsbased on quantum cellular automata technology. Quantum cellular automata (QCA technology is apromising nanotechnology of the future. QCA based 4:1 Multiplexer are designed and constructed as amodule in a FPGA. Multiplexer based designs are used to implement complex Boolean functions andeach module can act as a logic element or simple Multiplexer. We have studied here, NOR based logic toimplement Sum function of an adder in a QCA FPGA. Finally we have designed and simulated the MUXbased logic elements to construct QCA FPGA. This study can be useful for building complexConfigurable logic blocks to design a complete FPGA.

  14. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  15. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  16. Single event effects actel AX FPGA

    CERN Document Server

    Machefert, F P

    2002-01-01

    ACTEL and NASA performed irradiation tests at Brookhaven National Laboratory on the AX1000 component of the new ACTEL FPGA family "Axcelerator". The characteristics of these FPGAs are attractive and make them good candidates for the Front-End of the LHCb Calorimeters. The results of the measurements done at BNL are used to determine the resistance of the AX in the environment of the Calorimeter electronics. If mitigation techniques are used (triple voting or horizontal and vertical parity), no major worry is expected in spite of the safety factors applied in the evaluation. In this case and at maximum, a few bit errors could be observed per year on the full Calorimeter system.

  17. CHECHIA cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Technical Univ. Warsaw (Poland). ELHEP Laboratory, ISE; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany). TESLA

    2005-07-01

    The initial control of the superconductive cavity has recently been performed by applying the FPGA (Field Programmable Gate Array) technology system in DESY Hamburg. This first experiment turned attention to the general recognition of the cavity features and projected control methods. The electrical model of the cavity is taken as a consideration origin. The calibration of the signal channel is considered as a key preparation for an efficient cavity driving. The cavity parameters identification is confirmed as a proper approach for the required performance: driving on resonance during filling and field stabilization during flattop time with reasonable power consumption. The feed-forward and feedback modes were applied successfully for the CHECHIA cavity driving. Representative results of experiments are presented for different levels of the cavity field gradient. (orig.)

  18. FPGA for Power Control of MSL Avionics

    Science.gov (United States)

    Wang, Duo; Burke, Gary R.

    2011-01-01

    A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

  19. Controllable circuit

    DEFF Research Database (Denmark)

    2010-01-01

    A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...

  20. An FPGA Wave Union TDC for Time-of-Flight Applications

    Energy Technology Data Exchange (ETDEWEB)

    Wu, J.; /Fermilab

    2009-01-01

    An 18-channel time-of-flight (TOF) grade time-to-digit converter (TDC) has been implemented in a low cost FPGA device. The TDC has the following unique features. (1) The time recording structures of the TDC is based on the 'wave union TDC' we developed in our previous work. A leading edge of the input hit launches a bit pattern, or wave union into the delay chain-register array structure which yields two usable measurements. The two measurements effectively sub-divide timing bins for each other especially the 'ultra-wide bins' caused by the FPGA logic array block (LAB) structure and improves measurement precision both in terms of maximum bin width and RMS resolution. A coarser measurement on input signal trailing edge is also provided for time-over-threshold (TOT) applications. (2) The TDC supports advanced timing reference distribution schemes that are superior to conventional common start/stop schemes. The TDC has 16 regular measurement channels plus two channels for timing reference. The timing reference is established with multiple measurements rather than single shot common start/stop. An advanced scheme, the mean-timing approach even eliminates needs of high quality timing distribution media. (3) The ASIC-like encapsulation of the FPGA TDC significantly shorten the learning curve for potential users while maintain certain flexibility for various applications. Necessary digital post-processing functions including semicontinuous automatic calibration, data buffer, data link jam prevention logic etc. are integrated into the firmware to provide a turn-key solution for users.

  1. Central FPGA-based destination and load control in the LHCb MHz event readout

    Science.gov (United States)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  2. A Portable Laser Photoacoustic Methane Sensor Based on FPGA

    Science.gov (United States)

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-01-01

    A portable laser photoacoustic sensor for methane (CH4) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated. PMID:27657079

  3. A Portable Laser Photoacoustic Methane Sensor Based on FPGA.

    Science.gov (United States)

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-09-21

    A portable laser photoacoustic sensor for methane (CH₄) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated.

  4. FPGA Architecture for Multi-Style Asynchronous Logic

    CERN Document Server

    Huot, N; Fesquet, L; Renaudin, M

    2011-01-01

    This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.

  5. Electronic-generated holograms by FPGA and monochromatic LCD

    Science.gov (United States)

    Castillo-Atoche, A.; Pérez-Cortés, M.; López, M. A.; Ortiz-Gutiérrez, M.

    2006-02-01

    The majority of holograms are made using interference of light and computer-generated holograms. In this work we propose a technique in real time to generate digital holograms with a VLSI digital component, being specific FPGA and a liquid crystal device. The digital design with FPGA presents great advantage for its parallel procesing that carry out by its flexible structure, high integration and velocity. The design was verified using the platform MathLab/Simulink and Xilinx System Generator.

  6. Design of a system based on DSP and FPGA for video recording and replaying

    Science.gov (United States)

    Kang, Yan; Wang, Heng

    2013-08-01

    This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA

  7. FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

    Directory of Open Access Journals (Sweden)

    Elmar Yusifli

    2017-03-01

    Full Text Available With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit Hardware Description Language (VHDL implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC builder based Central Processing Unit (CPU core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC module. The IPDC is programmed in C++ and can run on a Personal Computer (PC or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

  8. Non-uniformity Correction of Linear Array Detector Based on FPGA%基于FPGA的线阵探测器非均匀校正的实现

    Institute of Scientific and Technical Information of China (English)

    高文清; 徐世伟; 刘严严; 丁艳艳

    2012-01-01

      充分利用了FPGA的硬件资源,提出一种采用电路逻辑设计的FPGA来实现两点校正;利用FPGA中的浮点加法器、浮点除法器、浮点乘法器,以及内部RAM、 ROM存储器,可以实时计算校正系数,然后对线阵红外探测器进行非均匀性校正,保证了校正精度。同时,充分利用FPGA并行处理能力强的特点,使系数、图像数据的读取在一个时钟周期内完成%  Based on the FPGA hardware resources, a FPGA in the logic circuit design is presented to achieve the two-point correction. The floating-point adder, floating-point divider, floating-point multiplier and the inter⁃nal RAM, ROM memory in FPGA can be used to calculate the correction factors in real time, and then the non-uni⁃formity correction is completed on the linear array infrared detector, thus the correction accuracy is ensured. At the same time, the coefficient and the reading of image data can be completed in a clock cycle by using the parallel pro⁃cessing ability of the FPGA.

  9. A Reconfigurable FPGA System for Parallel Independent Component Analysis

    Directory of Open Access Journals (Sweden)

    Du Hongtao

    2006-01-01

    Full Text Available A run-time reconfigurable field programmable gate array (FPGA system is presented for the implementation of the parallel independent component analysis (ICA algorithm. In this work, we investigate design challenges caused by the capacity constraints of single FPGA. Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA algorithm. During the implementation procedure, pICA is first partitioned into three temporally independent function blocks, each of which is synthesized by using several ICA-related reconfigurable components (RCs that are developed for reuse and retargeting purposes. All blocks are then integrated into a design and development environment for performing tasks such as FPGA optimization, placement, and routing. With partitioning and reconfiguration, the proposed reconfigurable FPGA system overcomes the capacity constraints for the pICA implementation on embedded systems. We demonstrate the effectiveness of this implementation on real images with large throughput for dimensionality reduction in hyperspectral image (HSI analysis.

  10. Application of FPGA technology for control of superconducting TESLA cavities in free electron laser

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2006-10-01

    Contemporary fundamental research in physics, biology, chemistry, pharmacology, material technology and other uses frequently methods basing on collision of high energy particles or penetration of matter with ultra-short electromagnetic waves. Kinetic energy of involved particles, considerably greater than GeV, is generated in accelerators of unique construction. The paper presents a digest of working principles of accelerators. There are characterized research methods which use accelerators. A method to stabilize the accelerating EM field in superconducting (SC) resonant cavity was presented. An example was given of usage of TESLA cavities in linear accelerator propelling the FLASH free electron laser (FEL) in DESY, Hamburg. Electronic and photonic control system was debated. The system bases on advanced FPGA circuits and cooperating fast DSP microprocessor chips. Examples of practical solutions were described. Test results of the debated systems in the real-time conditions were given.

  11. Design of an Oximeter Based on LED-LED Configuration and FPGA Technology

    Directory of Open Access Journals (Sweden)

    Radovan Stojanovic

    2013-01-01

    Full Text Available A fully digital photoplethysmographic (PPG sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (SpO2. The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (SpO2. N-LEDs configuration is proposed for multichannel SpO2 measurements. The approach resulted in better spectral sensitivity, increased and adjustable resolution, reduced noise, small size, low cost and low power consumption.

  12. An FPGA based Phased Array Processor for the Sub-Millimeter Array

    CERN Document Server

    Nagpal, Vinayak

    2012-01-01

    It has been widely acknowledged that Very Long Baseline Interferometry (VLBI) in the submillimeter wavelengths can make imaging observations of super massive black holes possible. The Sub-Millimeter Array (SMA) along with the James Clerk Maxwell Telescope (JCMT) and Caltech Submillimeter Observatory (CSO) on the Mauna Kea summit in Hawaii can together provide a large collecting area as one or more stations for VLBI observations aimed at studying an event horizon. To work as a VLBI station with full collecting area the SMA (or a combination SMA, JCMT, CSO antennas) would need a processor to enable phased array operation. This masters project focusses on building such a processor. Back end processing for high bandwidth radio telescopes has traditionally been done using custom designed application specific integrated circuits (ASIC). Recent advances in Field Programmable Gate Array (FPGA) technology have made FPGAs both powerful and economically viable for radio astronomy back ends. We have attempted to take adv...

  13. Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System

    Directory of Open Access Journals (Sweden)

    Wei Wang

    2015-06-01

    Full Text Available The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS and phase locked loop (PLL. A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA and digital signal processor (DSP pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation.

  14. Digital integrated circuits

    Science.gov (United States)

    Polasek, P.; Halamik, J.

    1984-05-01

    The term semicustom designed integrated circuits denotes integrated circuits of an all purpose character in which the production of chips is completed by using one to three custom design stencil type exposure masks. This involves in most cases interconnecting masks that are used to devise the circuit function desired by the customer. Silicon plates with an all purpose gate matrix are produced up to the interconnection level and can be kept at this phase in storage, after which a customer's specific demands can be met very expediently. All purpose logic fields containing 200 logic gates on a chip and an all purpose chip to be expanded to 1,000 logic gates are discussed. The technology facilitates the devising of fast gates with a delay of approximately 5 ns and power dissipation of 1 mW. In assembly it will be possible to make use of the entire assortment of the currently used casings with 16, 18, 20, 24, 28 and 40 outlets. In addition to the development of the mentioned technology, a general methodology for design of the mentioned gate fields is currently under way.

  15. Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

    Science.gov (United States)

    Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

    2016-03-01

    64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

  16. Research on the Key Technique of SPC Exchange Equipment Based on FPGA

    Directory of Open Access Journals (Sweden)

    Liu Yuansheng

    2013-07-01

    Full Text Available In the program controlled exchange technology college course, the signal transmission and voice data exchange for the communication system were usually achieved by utilizing the program controlled telephone exchange equipment choosing MT8980 series chip as the processing core which was limited to the numbers of communication channels and inflexibility of information interchange manners. A variety of extern circuits, taking time slice generation circuit and tone signal generation circuit as examples, will even be required which directly causes the complexity of the whole structure. Considering the disadvantages referred above, a new method of SPC (Stored Program Control exchange exploiting FPGA (Field Programmable Gate Array is proposed in this paper. The time slice generation, signal tone generation, user calls, voice data exchange functions, as well as other secondary functions, were realized by applying the new approach which allows the further development through hardware in-system programming. The superiority of the means is furnished in the end via comparing the experimental data in detail.  

  17. EDiFiSE full-FPGA adaptive optics: first laboratory results using the IACAT optical ground support equipment

    Science.gov (United States)

    Chulani, Haresh M.; Martín, Yolanda; Fuensalida, Jesús J.; Rodríguez-Ramos, Luis F.; Echeandía, Carlos; Puga, Marta; Alonso, Angel

    2016-07-01

    This paper reviews the EDiFiSE (Equalized and Diffraction-limited Field Spectrograph Experiment) full-FPGA (Field Programmable Gate Array) adaptive optics (AO) system and presents its first laboratory results. EDiFiSE is a prototype equalized integral field unit (EIFU) spectrograph for the observation of high-contrast systems in the Willian Herschel Telescope (WHT). Its AO system comprises two independent parallel full-FPGA control loops, one for tip-tilt and one for higher order aberrations. Xilinx's Virtex-4 and Virtex-5 FPGA's fixed point arithmetic and their interfacing with the rest of the AO components and the user have been adequately dealt with, and a very deterministic system with a negligible computational delay has been obtained. The AO system has been recently integrated in laboratory and verified using the IACAT (IAC Atmosphere and Telescope) optical ground support equipment. Closed loop correction bandwidths of 65 Hz for the tip-tilt and 25 Hz for higher order aberrations are obtained. The system has been tested in the visible range for the WHT with a 9 x 9 subpupil configuration, low star magnitude, wind speeds up to 10 m/s and Fried parameter down to 18 cm, and a resolution below the EIFU's fiber section has been obtained.

  18. Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

    Science.gov (United States)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-05-01

    A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

  19. FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

    Directory of Open Access Journals (Sweden)

    David H. K. Hoe

    2013-01-01

    Full Text Available This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

  20. FPGA Implementation of Complex Multiplier Using Urdhva Tiryakbham Sutra of Vedic Mathematics

    Directory of Open Access Journals (Sweden)

    Rupa A. Tomaskar

    2014-05-01

    Full Text Available In this work VHDL implementation of complex number multiplier using ancient Vedic mathematics is presented, also the FPGA implementation of 4-bit complex multiplier using Vedic sutra is done on SPARTAN 3 FPGA kit. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method was selected for implementation since it is applicable to all cases of multiplication. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay. The simulation results for 4-bit, 8-bit, 16-bit and 32 bit complex number multiplication using Vedic sutra are illustrated. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement multiplier efficiently in signal processing algorithms.

  1. Design of superconductor frame compression circuits

    Science.gov (United States)

    Sakurai, T.; Miyaho, N.; Miyahara, K.

    2007-10-01

    We proposed previously a novel interface circuit which was used between semiconductor data-input circuits and superconductor high-speed routers. The frame length of data packets is compressed in the interface circuit. Our proposed interface circuit has rather narrow timing margin. The problem was that our control circuit of the interface circuit could allow only very small timing delay. In this paper we propose a modified control circuit. We have improved the timing margin of the control circuit using RS-flip flop (RS-FF), where two shift registers and one control circuit are driven by clock pulses provided from a master clock-pulse generator. In this circuit, we have assumed fixed frame length packets. Our final target of master clock frequency is 100 GHz which will be realized with the device-parameter set of future advanced process. As the first step of realizing this target value, we aimed at 40 GHz clock operation with the conventional device-parameter set of NECs standard I process. The behavior of the whole frame compression circuit was simulated by a computer, and it was confirmed that it operated properly up to the master clock frequency of 23 GHz.

  2. SEU mitigation strategies for SRAM-based FPGA

    Science.gov (United States)

    Luo, Pei; Zhang, Jian

    2011-08-01

    The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the

  3. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  4. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  5. Delayed Puberty

    DEFF Research Database (Denmark)

    Kolby, Nanna; Busch, Alexander Siegfried; Juul, Anders

    2017-01-01

    Delayed puberty can be a source of great concern and anxiety, although it usually is caused by a self-limiting variant of the normal physiological timing named constitutional delay of growth and puberty (CDGP). Delayed puberty can, however, also be the first presentation of a permanent condition ...... mineral density) and psychological (e.g., low self-esteem) and underline the importance of careful clinical assessment of the patients.......Delayed puberty can be a source of great concern and anxiety, although it usually is caused by a self-limiting variant of the normal physiological timing named constitutional delay of growth and puberty (CDGP). Delayed puberty can, however, also be the first presentation of a permanent condition...

  6. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  7. Delayed fission

    Energy Technology Data Exchange (ETDEWEB)

    Hatsukawa, Yuichi [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment

    1997-07-01

    Delayed fission is a nuclear decay process that couples {beta} decay and fission. In the delayed fission process, a parent nucleus undergoes {beta} decay and thereby populates excited states in the daughter. If these states are of energies comparable to or greater than the fission barrier of the daughter, then fission may compete with other decay modes of the excited states in the daughter. In this paper, mechanism and some experiments of the delayed fission will be discussed. (author)

  8. Broadband hyperchaotic oscillator with delay line

    DEFF Research Database (Denmark)

    Cenys, Antanas; Lindberg, Erik; Anagnostopoulos, A. N.;

    2002-01-01

    Dynamical systems with time delay can be employed as high dimensional hyperchaotic oscillators with multiple positive Lyapunov exponents. We describe an electronic circuit composed of a 3-stage amplifier and a delay line in the feedback loop. The 1st stage of the amplifier is a nonlinear one while...

  9. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  10. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  11. Stego on FPGA: An IWT Approach

    Directory of Open Access Journals (Sweden)

    Balakrishnan Ramalingam

    2014-01-01

    Full Text Available A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE and the highest peak signal-to-noise ratio (PSNR. The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA.

  12. Greening the NetFPGA Reference Router

    Directory of Open Access Journals (Sweden)

    Feng Guo

    2016-06-01

    Full Text Available Energy efficiency is an important criterion in the design of next generation networks for both economic and environmental concerns. This paper presents an energy-efficient router that is able to dynamically adapt its routing capability in response to real-time traffic load, achieving energy proportional routing. The NetFPGA reference router, which operates at one of two frequencies (125 MHz or 62.5 MHz, requires a board reset to switch frequencies. We have modified the reference router to allow dynamic switching among five operating frequencies. Experiments with real traces indicate that, compared to the reference router, a 10% power reduction can be achieved through dynamic frequency scaling. When the router is further modified to support green traffic engineering and Ethernet port shut-down, power consumption can be reduced by 46% while maintaining the required quality of service. This allows the router to meet the instantaneous performance requirements while minimizing power dissipation. Similar results can be expected when these general power-saving principles are applied in future commercial routers.

  13. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  14. Circuit Connectors

    Science.gov (United States)

    1979-01-01

    The U-shaped wire devices in the upper photo are Digi-Klipsm; aids to compact packaging of electrical and electronic devices. They serve as connectors linking the circuitry of one circuit board with another in multi-board systems. Digi-Klips were originally developed for Goddard Space Flight Center to meet a need for lightweight, reliable connectors to replace hand-wired connections formerly used in spacecraft. They are made of beryllium copper wire, noted for its excellent conductivity and its spring-like properties, which assure solid electrical contact over a long period of time.

  15. FPGA-based real-time phase measuring profilometry algorithm design and implementation

    Science.gov (United States)

    Zhan, Guomin; Tang, Hongwei; Zhong, Kai; Li, Zhongwei; Shi, Yusheng

    2016-11-01

    Phase measuring profilometry (PMP) has been widely used in many fields, like Computer Aided Verification (CAV), Flexible Manufacturing System (FMS) et al. High frame-rate (HFR) real-time vision-based feedback control will be a common demands in near future. However, the instruction time delay in the computer caused by numerous repetitive operations greatly limit the efficiency of data processing. FPGA has the advantages of pipeline architecture and parallel execution, and it fit for handling PMP algorithm. In this paper, we design a fully pipelined hardware architecture for PMP. The functions of hardware architecture includes rectification, phase calculation, phase shifting, and stereo matching. The experiment verified the performance of this method, and the factors that may influence the computation accuracy was analyzed.

  16. Novel cascade FPGA accelerator for support vector machines classification.

    Science.gov (United States)

    Papadonikolakis, Markos; Bouganis, Christos-Savvas

    2012-07-01

    Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.

  17. FPGA design and implementation for EIT data acquisition.

    Science.gov (United States)

    Yue, Xicai; McLeod, Chris

    2008-10-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power.

  18. A novel pipeline based FPGA implementation of a genetic algorithm

    Science.gov (United States)

    Thirer, Nonel

    2014-05-01

    To solve problems when an analytical solution is not available, more and more bio-inspired computation techniques have been applied in the last years. Thus, an efficient algorithm is the Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by the mechanism of "natural selection", where the strong has higher chances to survive. A genetic algorithm is an iterative procedure which operates on a population of individuals called "chromosomes" or "possible solutions" (usually represented by a binary code). GA performs several processes with the population individuals to produce a new population, like in the biological evolution. To provide a high speed solution, pipelined based FPGA hardware implementations are used, with a nstages pipeline for a n-phases genetic algorithm. The FPGA pipeline implementations are constraints by the different execution time of each stage and by the FPGA chip resources. To minimize these difficulties, we propose a bio-inspired technique to modify the crossover step by using non identical twins. Thus two of the chosen chromosomes (parents) will build up two new chromosomes (children) not only one as in classical GA. We analyze the contribution of this method to reduce the execution time in the asynchronous and synchronous pipelines and also the possibility to a cheaper FPGA implementation, by using smaller populations. The full hardware architecture for a FPGA implementation to our target ALTERA development card is presented and analyzed.

  19. Real-time panoramic infrared imaging system based on FPGA

    Science.gov (United States)

    Zhang, Hao-Jun; Shen, Yong-Ge

    2010-11-01

    During the past decades, signal processing architecture, which is based on FPGA, conventional DSP processor and host computer, is popular for infrared or other electro-optical systems. With the increasing processing requirement, the former architecture starts to show its limitation in several respects. This paper elaborates a solution based on FPGA for panoramic imaging system as our first step of upgrading the processing module to System-on-Chip (SoC) solution. Firstly, we compare this new architecture with the traditional to show its superiority mainly in the video processing ability, reduction in the development workload and miniaturization of the system architecture. Afterwards, this paper provides in-depth description of this imaging system, including the system architecture and its function, and addresses several related issues followed by the future development. FPGA has developed so rapidly during the past years, not only in silicon device but also in the design flow and tools. In the end, we briefly present our future system development and introduce those new design tools to make up the limitation of the traditional FPGA design methodology. The advanced design flow through Simulink and Xilinx System Generator (Sysgen) has been elaborated, which enables engineers to develop sophisticated DSP algorithms and implement them in FPGA more efficiently. It is believed that this new design approach can shorten system design cycle by allowing rapid prototyping and refining design process.

  20. FPGA-Based Implementation Direct Torque Control of Induction Motor

    Directory of Open Access Journals (Sweden)

    Saber Krim

    2015-02-01

    Full Text Available This paper proposes a digital implementation of the direct torque control (DTC of an Induction Motor (IM with an observation strategy on the Field Programmable Gate Array (FPGA. The hardware solution based on the FPGA is caracterised by fast processing speed due to the parallel processing. In this study the FPGA is used to overcome the limitation of the software solutions (Digital Signal Processor (DSP and Microcontroller. Also, the DTC of IM has many drawbacks such as for example; The open loop pure integration has from the problems of integration especially at the low speed and the variation of the stator resistance due to the temperature. To tackle these problems we use the Sliding Mode Observer (SMO. This observer is used estimate the stator flux, the stator current and the stator resistance. The hardware implementation method is based on Xilinx System Generator (XSG which a modeling tool developed by Xilinx for the design of implemented systems on FPGA; from the design of the DTC with SMO from XSG we can automatically generate the VHDL code. The model of the DTC with SMO has been designed and simulated using XSG blocks, synthesized with Xilinx ISE 12.4 tool and implemented on Xilinx Virtex-V FPGA.

  1. Dynamics of Nonlinear Time-Delay Systems

    CERN Document Server

    Lakshmanan, Muthusamy

    2010-01-01

    Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant. This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics. Special attention is devoted to scalar chaotic/hyperchaotic time-delay systems, and some higher order models, occurring in different bran...

  2. FPGA implementation of short critical path CORDIC-based approximation of the eight-point DCT

    CERN Document Server

    Vashkevich, Maxim; Petrovsky, Alexander

    2011-01-01

    This paper presents an efficient approach for multiplierless implementation for eight-point DCT approximation, which based on coordinate rotation digital computer (CORDIC) algorithm. The main design objective is to make critical path of corresponding circuits shorter and reduce the combinational delay of proposed scheme.

  3. LOGIC CIRCUIT

    Science.gov (United States)

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  4. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  5. Immunity of FPGA chips by direct injection

    OpenAIRE

    Aurand, Tobias; Dawson, J.F.; Robinson, Martin Paul; Marvin, A.C.

    2009-01-01

    Immunity measurements of Xilinix XC3S200TQ144 and Altera EP3C10E144C7N FPGAs by direct injection are presented and the immunity of individual pins is shown to depend greatly on the load seen by nearby pins. The implications of this on in circuit immunity prediction are discussed.

  6. An Auto ranging Data Converter Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    Jithin Krishnan

    2013-06-01

    Full Text Available A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA - i.e. an all-digital analog to digital (A/D converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range detection unit with 7 bits and a sign bit for polarity detection. The analog part of the modulator is done utilizing the LVDS transceiver in the FPGA making it a real digital one. The digital section of sigma delta ADC containing the decimation filter banks is done in a cascaded filter structure form including a CIC decimation filter, droop compensation and half-band filters. The top level module was coded using VHDL and the simulation was carried out with ModelSim and MATLAB.

  7. FPGA Prototyping of RNN Decoder for Convolutional Codes

    Directory of Open Access Journals (Sweden)

    Salcic Zoran

    2006-01-01

    Full Text Available This paper presents prototyping of a recurrent type neural network (RNN convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA, thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.

  8. A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

    Science.gov (United States)

    Lin, Changxing; Zhang, Jian; Shao, Beibei

    This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2dB.

  9. Simple generation of threshold for images binarization on FPGA

    Directory of Open Access Journals (Sweden)

    Egidio Ieno

    2015-12-01

    Full Text Available This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.

  10. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  11. A simple digital delay for nuclear physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Marques, J.G., E-mail: jmarques@ctn.ist.utl.pt [C2TN, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS (Portugal); Cruz, C. [LATR, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS (Portugal)

    2014-05-01

    A simple high precision digital delay for nuclear physics experiments was developed using fast ECL electronics. The circuit uses an oscillator synchronized with the signal to be delayed and a presettable counter. It is capable of delaying a negative NIM signal by 2 µs with a precision better than 50 ps. The circuit was developed for use in slow-fast coincidence units for Perturbed Angular Correlation spectrometers but it is not limited to this application.

  12. Exploring the energy consumption of lightweight blockciphers in FPGA

    DEFF Research Database (Denmark)

    Banik, Subhadeep; Bogdanov, Andrey; Regazzoni, Francesco

    2015-01-01

    . Concentrating on applications that require a number of parallel encryptions, we instantiate several designs on the target FPGA and we analyze how the energy consumption varies in each algorithm when changing the amount of unrolled rounds. Our results, obtained on the Xc6slx45t device of the Spartan6 family......, demonstrate that Present is the most energy efficient algorithm and that the relation between the energy consumption and the number of unrolled rounds measured on FPGA is similar to the one measured on dedicated hardware....

  13. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  14. Radiation Tolerant, FPGA-Based SmallSat Computer System

    Science.gov (United States)

    LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

    2015-01-01

    The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

  15. Design and Implementation of Car Parking System on FPGA

    Directory of Open Access Journals (Sweden)

    Ramneet Kaur

    2013-06-01

    Full Text Available As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic congestion, pollution (noise and air. To overcome this problem A FPGA based parking system has been proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system has two main modules i.e. identification module and slot checking module. Identification module identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor interfacing, stepper motor and LCD.

  16. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  17. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance......In this paper an implementation technique for Field Programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops...

  18. Small Signal Circuit Model of Double Photodiodes

    Institute of Scientific and Technical Information of China (English)

    HAN Jian-zhong; Ni Guo-qiang; MAO Lu-hong

    2004-01-01

    The transmission delay of photogenerated carriers in a CMOS-process-compatible double photodiode (DPD) is analyzed by using device simulation. The DPD small signal equivalent circuit model which includes transmission delay of photogenerated carriers is given. From analysis on the frequency domain of the circuit model the device has two poles. One has the relationship with junction capacitance and the DPD's load,the other with the depth and the doping concentration of the N-well in the DPD. Different depth of the Nwell and different area of the DPDs with bandwidth were compared. The analysis results are important to design the high speed DPDs.

  19. Commutation circuit for an HVDC circuit breaker

    Science.gov (United States)

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  20. Modeling the critical safety functions status tree of a NPP using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos Santana; Oliveira, Mauro Vitor de; Jaime, Guilherme Dutra Gonzaga; Almeida, Jose Carlos Soares de; Augusto, Silas Cordeiro, E-mail: msantana@ien.gov.br, E-mail: mvitor@ien.gov.br, E-mail: gdjaime@ien.gov.br, E-mail: jcsa@ien.gov.br, E-mail: silas@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Divisao de Engenharia Nuclear

    2013-07-01

    Field Programmable Gate Arrays (FPGAs) based systems and equipment are beginning to appear in new plants I and C applications, as well as in retrofits for operating plants, in particular for safety applications due to their capability to face the systems obsolescence since they are circuit independent. The circuits implemented can be portable to different FPGAs architectures. Moreover, they reduce complexity for regulatory approval as compared to conventional microprocessor-based systems. Critical safety function (CSF) is the most significant design concept for prioritize operator actions for NPP based on the potential threat to the three barriers (fuel cladding, primary coolant system boundary, and containment) and allows the operator to respond to these threats prior to event diagnosis. CSF has a hierarchical information structure that organizes the system variables affecting the plant safety in terms of goal-means relations. This paper describes the application of FPGA in the implementation of the CSFs status tree logic for a Westinghouse 3-loops NPP simulator. (author)

  1. Distributed Continuous Event-Based Data Acquisition Using the IEEE 1588 Synchronization and FlexRIO FPGA

    Science.gov (United States)

    Taliercio, C.; Luchetta, A.; Manduchi, G.; Rigoni, A.

    2017-07-01

    High-speed event driven acquisition is normally performed by analog-to-digital converter (ADC) boards with a given number of pretrigger sample and posttrigger sample that are recorded upon the occurrence of a hardware trigger. A direct physical connection is, therefore, required between the source of event (trigger) and the ADC, because any other software-based communication method would introduce a delay in triggering that would turn out to be not acceptable in many cases. This paper proposes a solution for the relaxation of the event communication time that can be, in this case, carried out by software messaging (e.g., via an LAN), provided that the system components are synchronized in time using the IEEE 1588 synchronization mechanism. The information about the exact event occurrence time is contained in the software packet that is sent to communicate the event and is used by the ADC FPGA to identify the exact sample in the ADC sample queue. The length of the ADC sample queue will depend on the maximum delay in software event message communication time. A prototype implementation using a National FlexRIO FPGA board connected with an ADC device is presented as the proof of concept.

  2. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  3. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  4. RESEARCH ON SHARING DEGREE-BASED FPGA RECONFIGURABLE RESOURCE ALLOCATION ALGORITHM%基于共享度的FPGA可重构资源分配算法研究

    Institute of Scientific and Technical Information of China (English)

    李瑞娟

    2013-01-01

    针对FPGA可重构设计中高效率的资源分配面临的困难,提出基于共享度的FPGA可重构设计算法.描述基于共享度对FPGA资源分配策略的实施过程,并给出基于共享度的资源分配最优策略及证明过程.经过模拟测试表明,所设计的FPGA资源分配算法在资源利用率和任务平均等待延时方面均优于传统的FF算法,其平均任务等待延时比传统的FF算法缩短了8%.%To the difficulties of high-efficient resource allocation in FPGA reconfigurable design, we put forward a sharing degree-based FPGA reconfigurable design algorithm. It describes the implementing process of FPGA resource allocation based on sharing degree, and gives the optimal policy of sharing degree-based resource allocation and the proof process. Simulation test shows, the FPGA resource allocation algorithm we designed is superior to traditional FF algorithm in resource utilisation rate and average task waiting delay. The average task waiting delay shortens by 8% than the traditional FF algorithm.

  5. DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

    Directory of Open Access Journals (Sweden)

    Priya Gupta

    2011-09-01

    Full Text Available This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing on board in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

  6. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  7. Single Event Effects in FPGA Devices 2014-2015

    Science.gov (United States)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2015-01-01

    This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  8. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    Science.gov (United States)

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  9. Power Efficient Gurumukhi Unicode Reader Design and Implementation on FPGA

    DEFF Research Database (Denmark)

    Kaur, Amanpreet; Pandey, Bishwajeet; Hussain, Dil Muhammed Akbar

    2017-01-01

    and is implemented on Virtex-6 FPGA on Xilinx software. This GUR design is tested at an different frequencies by applying frequency scaling techniques .The reader is also observed on two different IO Standards i.e. on SSTL (Stub-Series Terminated Logic) and LVDCI (Low Voltage Digitally Controlled Impedance) logic...

  10. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...

  11. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  12. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  13. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  14. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    Science.gov (United States)

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  15. FPGA implementation of filtered image using 2D Gaussian filter

    Directory of Open Access Journals (Sweden)

    Leila kabbai

    2016-07-01

    Full Text Available Image filtering is one of the very useful techniques in image processing and computer vision. It is used to eliminate useless details and noise from an image. In this paper, a hardware implementation of image filtered using 2D Gaussian Filter will be present. The Gaussian filter architecture will be described using a different way to implement convolution module. Thus, multiplication is in the heart of convolution module, for this reason, three different ways to implement multiplication operations will be presented. The first way is done using the standard method. The second way uses Field Programmable Gate Array (FPGA features Digital Signal Processor (DSP to ensure and make fast the scalability of the effective FPGA resource and then to speed up calculation. The third way uses real multiplier for more precision and a the maximum uses of FPGA resources. In this paper, we compare the image quality of hardware (VHDL and software (MATLAB implementation using the Peak Signal-to-Noise Ratio (PSNR. Also, the FPGA resource usage for different sizes of Gaussian kernel will be presented in order to provide a comparison between fixed-point and floating point implementations.

  16. A displacement sensor of dual-light based on FPGA

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    The dual-light displacement sensor is presented to obtain a higher accuracy compared with the single. The structure and principle of the system are also introduced, and the hardware and software are brought in too. The function of the system is feasible through the experiments and simulating the data process based on FPGA.

  17. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture

    Science.gov (United States)

    2009-08-01

    Inside the FPGA, we currently use a single-channel 233 MHz DDR2 memory controller based on the BEE3 memory controller [1]. It supports up to a 2GB dual...pages between cores. 28 13.0 REFERENCES [1] DDR2 DRAM Controller for BEE3, online at http://research.microsoft.com/en-us/projects/BEE3/, 2008

  18. Analog circuit design designing waveform processing circuits

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    The fourth volume in the set Designing Waveform-Processing Circuits builds on the previous 3 volumes and presents a variety of analog non-amplifier circuits, including voltage references, current sources, filters, hysteresis switches and oscilloscope trigger and sweep circuitry, function generation, absolute-value circuits, and peak detectors.

  19. Charge Measurement System Design Based on FPGA%基于FPGA的电荷测量系统设计

    Institute of Scientific and Technical Information of China (English)

    沈亚勇; 张宇翔; 赵豫斌; 邹剑雄; 陈少佳; 李月华

    2013-01-01

    It introduces a kind of charge measurement system based on FPGA.The system has a multi-channel,high speed and high-precision data processing ability.The input signal was first amplified,formed,filtered by analog modulation circuit and then sent to ADC for deeper sampling,the sampled data was sent to FPGA for peak seeking processing,after that transmitted to the upper machine through the USB bus.The System design mainly includes the front end of the analog signal conditioning,ADC analog-to-digital conversion,FPGA and USB interface.At the end of the article the whole system test results are presented.%介绍了一种基于FPGA的电荷测量系统.该系统具有并行、高速、高精度的数据处理能力.系统输入信号首先经过模拟调理电路放大、成型、滤波,然后送给ADC进行采样,采样后的数据送到FP-GA内部进行处理,最后通过USB总线传送到上位机.系统设计主要包括前端模拟信号的调理部分、ADC模数转换部分,FPGA处理和USB接口部分.最后给出了整个系统的测试结果.

  20. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  1. The high speed low noise multi-data processing signal process circuit research of remote sensing

    Science.gov (United States)

    Su, Lei; Jiang, Haibin; Dong, Wang

    2013-08-01

    The high speed, low noise and integration characteristic are the main technology and the main development directions on the signal process circuit of the image sensor, especially in high resolution remote sensing. With these developments, the high noise limiting circuits, high speed data transfer system and the integrated design of the signal process circuit become more and more important. Therefore the requirement of the circuit system simulation is more and more important during the system design and PCB board design process. A CCD signal process circuit system which has the high speed, low noise and several selectable operate modes function was designed and certificated in this paper, during the CCD signal process circuit system design, simulation was made which include the signal integrity and the power integrity. The important devices such as FPGA and the DDR2 device were simulated, using the power integrity simulation the sensitive power planes of the FPGA on the PCB was modified to make the circuit operate more stabilize on a higher frequency. The main clock path and the high speed data path of the PCB board were simulated with the signal integrity. All the simulation works make the signal process circuit system's image's SNR value get higher and make the circuit system could operate well on higher frequency. In the board testing process, the PCB time diagrams were listed on the testing chapter and the wave's parameter meets the request. The real time diagram and the simulated result of the PCB board was listed respectively. The CCD signal process circuit system's images' SNR (Signal Noise Ratio) value, the 14bit AFE slew rate and the data transfer frequency is listed in the paper respective.

  2. Timing Analysis of Genetic Logic Circuits using D-VASim

    DEFF Research Database (Denmark)

    Baig, Hasan; Madsen, Jan

    A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to controlgene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electroniclogic circuits, timing and propagation...... delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing...... and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...

  3. A novel method based solely on FPGA units enabling measurement of time and charge of analog signals in Positron Emission Tomography

    CERN Document Server

    Pałka, M; Białas, P; Czerwiński, E; Kapłon, Ł; Kochanowski, A; Korcyl, G; Kowal, J; Kowalski, P; Kozik, T; Krzemień, W; Molenda, M; Moskal, P; Niedźwiecki, Sz; Pawlik, M; Raczyński, L; Rudy, Z; Salabura, P; Sharma, N G; Silarski, M; Słomski, A; Smyrski, J; Strzelecki, A; Wiślicki, W; Zieliński, M; Zoń, N

    2013-01-01

    This article presents a novel technique for precise measurement of time and charge based solely on FPGA (Field Programmable Gate Array) device and few satellite discrete electronic components used in Positron Emission Tomography (PET). Described approach simplifies electronic circuits, reduces the power consumption, lowers costs, merges front-end electronics with digital electronics and also makes more compact final design. Furthermore, it allows to measure time when analog signals cross a reference voltage at different threshold levels with a very high precision of $\\sim$ 10ps (rms) and thus enables sampling of signals in a voltage domain.

  4. Implementation of Carrier-Based Simple Boost Pulse Width Modulation (PWM) for Z-Source Inverter (ZSI) using Field Programming Gate Array (FPGA)

    Science.gov (United States)

    Muhammad, M.; Rasin, Z.; Jidin, A.

    2017-08-01

    In recent years, the research on the Z-source inverter (ZSI) has received a wide acceptance due to its attractive solution for example in the renewable energy interface that requires voltage boost capability. The conventional inverter circuit based on the SPWM technique for example does not able to fully utilize its DC input voltage to produce a greater output voltage. The ZSI shoot-through implementation in high switching frequency requires a processor with fast sampling and high precision. In simulation, this can be easily carried out with the available advanced engineering software. In the hardware implementation however, the processor used is not only handle the switching, but also needs to read the data obtained by the sensor, voltage and current control, information display etc. This limits the capacity that can be used to implement the switching fast sampling with high precision. The aims of this work are to implement high precision of carrier-based simple boost PWM for ZSI using FPGA and to verify its real time hardware implementation. The high precision of PWM control algorithm based on the FPGA platform is verified by comparing the simulation results with the experimental results for different modulation index and boost factor, and a good agreement is concluded. It is observed that the application of FPGA reduces complexity, increases speed and the design of the switching technique can be altered without having to modify the hardware implementation.

  5. An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

    Science.gov (United States)

    Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

    2016-01-01

    A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

  6. Decoding of IRIG-B(DC) code based on FPGA%基于FPGA的IRIG-B(DC)码解码

    Institute of Scientific and Technical Information of China (English)

    卢韦明; 卢韦平

    2012-01-01

    A decoding means of IRIG-B(DC) time code is proposed on the basis of analyzing the wave characteristics of IRIG-B(DC)code. This design is made up of peripheral circuits and FPGA to implement decoding of IRIG-B(DC) code and 1 pps signal output and real-time time display and serial asynchronous communication. Compared with traditional methods, it has lots of advantages such as smaller size, lower cost and more reliable stability, and can replace the main functions of traditional B-code device.%在分析了IRIG-B(DC)码码型特点的基础上,提出了一种IRIG-B(DC)时间码解码的设计方法.该方法由少量外围电路与一片现场可编程门阵列(FPGA)芯片组成,来实现对IRIG- B(DC)码的解码、1 PPS信号输出、实时时间显示以及串行异步通信.与传统的方法相比,该设计方案具有体积小、成本低、工作稳定等优点,完全能够替代传统的B码机箱的功能.

  7. Implementation of Signal Sampling with FPGA%基于FPGA的高速采样单元实现

    Institute of Scientific and Technical Information of China (English)

    王健

    2012-01-01

    A high-speed sampling unit hardware realization based on FPGA is proposed, including the circuit design of data acquisition ; the approach of high speed data transmission ; the design of operational processor system and bus control system, and the VHDL program framework. The signal types are iransformed by the sampler and then processed and stored with programmable gate arrays FPGA. Finally, the data of the sample unit is transmitted under the control of the whole system.%介绍了一种基于FPGA的高速采样单元硬件实现,包括数据采集器周边电路设计、高速数据传输方法和设计要点、运算处理单元设计、总线控制设计和VHDL程序编写框架。将信号进行样式转换,由采样器转换并通过可编程门阵列FPGA进行处理并存储,再由系统进行控制完成整个采样单元的数据传输。

  8. Verification of FPGA-Signal using the test board which is applied to Safety-related controller

    Energy Technology Data Exchange (ETDEWEB)

    Chung, Youn-Hu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [SOOSAN ENS, Seoul (Korea, Republic of)

    2016-10-15

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. Saftety-related PLC must meet the international standard specifications. With this reason, we use V and V according to an international standard in order to secure high reliability and safety. By using this, we are supposed to proceed to a variety of verification courses for extra reliability and safety analysis. In order to have efficient verification of test results, we propose the test using the newly changed BGA socket which can resolve the problems of the conventional socket on this paper. The Verification of processes is divided into verification of Hardware and firmware. That processes are carried out in the unit testing and integration testing. The proposed test method is simple, the effect of cost reductions by batch process. In addition, it is advantageous to measure the signal from the Hi-speed-IC due to its short length of the pins and it was plated with the copper around it. Further, it also to prevent abrasion on the IC ball because it has no direct contact with the PCB. Therefore, it can be actually applied is to the BGA package test and we can easily verify logic as well as easily checking the operation of the designed data.

  9. Slow light on a printed circuit board.

    Science.gov (United States)

    Lanin, Aleksandr A; Voronin, Aleksandr A; Sokolov, Viktor I; Fedotov, Ilya V; Fedotov, Andrei B; Akhmanov, Aleksandr S; Panchenko, Vladislav Ya; Zheltikov, Aleksei M

    2011-05-15

    Slow-light effects induced by stimulated Raman scattering in polymer waveguides on a printed circuit board are shown to enable a widely tunable delay of broadband optical signals, suggesting an advantageous platform for optical information processing and ultrafast optical waveform transformation. © 2011 Optical Society of America

  10. Designing asynchronous circuits using NULL convention logic (NCL)

    CERN Document Server

    Smith, Scott

    2009-01-01

    Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design

  11. A high-resolution time interpolator based on a delay locked loop and an RC delay line

    CERN Document Server

    Mota, M

    1999-01-01

    An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7- mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low- power, high-resolution time interpolation circuit in a standard digital CMOS technology. (11 refs).

  12. High Performance Hardware Design Of IEEE Floating Point Adder In FPGA With VHDL

    Directory of Open Access Journals (Sweden)

    2013-07-01

    Full Text Available In this paper, we present the design and implementation of a floating-point adder that is compliant with the current draft revision of this standard. We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths.Our work is an important design resource for development of floating-point adder hardware on FPGAs. All sub components within the floating-point adder and known algorithms are researched and implemented to provide versatility and flexibility to designers as an alternative to intellectual property where they have no control over the design. The VHDL code is open source and can be used by designers with proper reference. Each of the sub-operation is researched for different implementations and then synthesized onto a Spartan FPGA device to be chosen for best performance. Our implementation of the standard algorithm occupied 370 slices and had an overall delay of 31 ns. The standard algorithm was pipelined into five stages to run at 100 MHz which took an area of 324 slices and power is 30mw.

  13. FPGA-based High-precision Measurement Algorithm for the Ultrasonic Echo Time of Flight

    Institute of Scientific and Technical Information of China (English)

    Bo-xiong WANG; Jin ZHANG

    2010-01-01

    Based on the evaluation of advantages and disadvantages of high-precision digital time interval measuring algorithms, and combined with the principle of the typical time-difference ultrasonic flow measurement,the requirements far the measurement of echo time of flight put forward by the ultrasonic flow measurement are an-alyzed.A new high-precision time interval measurement algorithm is presented, which combines the pulse counting method with the phase delay interpolation. The pulse counting method is used to ensure a large dynamic measuring range, and a double-edge triggering counter is designed to improve the accuracy and reduce the counting quantiza-tion error.The phase delay interpolation is used to reduce the quanti-zation error of pulse counting for further improving the time measure-ment resolution.Test data show that the system for the measurement of the ultrasonic echo time of flight based on this algorithm and im-plemented on an Field Programmable Gate Array(FPGA) needs a rel-atively short time for measurement,and has a measurement error of less than 105 ps.

  14. Radiation-Tolerant Reprogrammable FPGA for Digital Signal Processing Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Field Programmable Gate Arrays are a widely used technology; however, they are generally limited in reprogrammability. Radiation hard, low power and high density...

  15. Radiation-Tolerant Reprogrammable FPGA for Digital Signal Processing Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Field Programmable Gate Arrays are a widely used technology; however, they are generally limited in reprogrammability. Radiation hard, low power and high density...

  16. Design and Implementation of Virtual Logic Analyzer Based on FPGA%基于 FPGA 的虚拟逻辑分析仪的设计与实现

    Institute of Scientific and Technical Information of China (English)

    王万昭; 张鹏云; 和志强

    2014-01-01

    介绍一种基于FPGA芯片的虚拟逻辑分析仪,它由信号调整电路、采样模块、触发模块、通信模块、数据处理模块( NIOS II软核)以及总线接口等组成,实现了8路并行采样,其采样速率可以达到100 MS/s。%This paper introduces a virtual logic analyzer based on FPGA chip , which consists of signal conditioning circuit , sam-pling module, trigger module, communication module, NIOS Ⅱsoft-core, and bus interface.The 8-way parallel sampling is a-chieved.The sampling rate is up to 100MS/s.

  17. Relativistic causality and clockless circuits

    CERN Document Server

    Matherat, Philippe; 10.1145/2043643.2043650

    2011-01-01

    Time plays a crucial role in the performance of computing systems. The accurate modelling of logical devices, and of their physical implementations, requires an appropriate representation of time and of all properties that depend on this notion. The need for a proper model, particularly acute in the design of clockless delay-insensitive (DI) circuits, leads one to reconsider the classical descriptions of time and of the resulting order and causal relations satisfied by logical operations. This questioning meets the criticisms of classical spacetime formulated by Einstein when founding relativity theory and is answered by relativistic conceptions of time and causality. Applying this approach to clockless circuits and considering the trace formalism, we rewrite Udding's rules which characterize communications between DI components. We exhibit their intrinsic relation with relativistic causality. For that purpose, we introduce relativistic generalizations of traces, called R-traces, which provide a pertinent des...

  18. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  19. Simple Autonomous Chaotic Circuits

    Science.gov (United States)

    Piper, Jessica; Sprott, J.

    2010-03-01

    Over the last several decades, numerous electronic circuits exhibiting chaos have been proposed. Non-autonomous circuits with as few as two components have been developed. However, the operation of such circuits relies on the non-ideal behavior of the devices used, and therefore the circuit equations can be quite complex. In this paper, we present two simple autonomous chaotic circuits using only opamps and linear passive components. The circuits each use one opamp as a comparator, to provide a signum nonlinearity. The chaotic behavior is robust, and independent of nonlinearities in the passive components. Moreover, the circuit equations are among the algebraically simplest chaotic systems yet constructed.

  20. Circuit analysis for dummies

    CERN Document Server

    Santiago, John

    2013-01-01

    Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

  1. Current limiter circuit system

    Energy Technology Data Exchange (ETDEWEB)

    Witcher, Joseph Brandon; Bredemann, Michael V.

    2017-09-05

    An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

  2. Analytical delay models for RLC interconnects under ramp input

    Institute of Scientific and Technical Information of China (English)

    REN Yinglei; MAO Junfa; LI Xiaochun

    2007-01-01

    Analytical delay models for Resistance Inductance Capacitance (RLC)interconnects with ramp input are presented for difierent situations,which include overdamped,underdamped and critical response cases.The errors of delay estimation using the analytical models proposed in this paper are less bv 3%in comparison to the SPICE-computed delay.These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.

  3. FPGA helix tracking algorithm for PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Yutie; Galuska, Martin; Gessler, Thomas; Hu, Jifeng; Kuehn, Wolfgang; Lange, Jens Soeren; Muenchow, David; Spruck, Bjoern [II. Physikalisches, Giessen University (Germany); Ye, Hua [II. Physikalisches, Giessen University (Germany); Institute of High Energy Physics, Beijing (China); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA detector is a general-purpose detector for physics with high luminosity cooled antiproton beams, planed to operate at the FAIR facility in Darmstadt, Germany. The central detector includes a silicon Micro Vertex Detector (MVD) and a Straw Tube Tracker (STT). Without any hardware trigger, large amounts of raw data are streaming into the data acquisition system. The data reduction task is performed in the online system by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays) as first level and on a farm of GPUs or PCs as a second level. One important part in the system is the online track reconstruction. In this presentation, an online tracking finding algorithm for helix track reconstruction in the solenoidal field is shown. A performance study using C++ and the status of the VHDL implementation are presented.

  4. Improved Circuits with Capacitive Feedback for Readout Resistive Sensor Arrays

    Directory of Open Access Journals (Sweden)

    Óscar Oballe-Peinado

    2016-01-01

    Full Text Available One of the most suitable ways of distributing a resistive sensor array for reading is an array with M rows and N columns. This allows reduced wiring and a certain degree of parallelism in the implementation, although it also introduces crosstalk effects. Several types of circuits can carry out the analogue-digital conversion of this type of sensors. This article focuses on the use of operational amplifiers with capacitive feedback and FPGAs for this task. Specifically, modifications of a previously reported circuit are proposed to reduce the errors due to the non-idealities of the amplifiers and the I/O drivers of the FPGA. Moreover, calibration algorithms are derived from the analysis of the proposed circuitry to reduce the crosstalk error and improve the accuracy. Finally, the performances of the proposals is evaluated experimentally on an array of resistors and for different ranges.

  5. Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

    CERN Document Server

    Zhang, Linlin; Khalid, Mohammed; Houzet, Dominique; Legrand, Anne-Claire

    2010-01-01

    The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional NoCs (Network on Chip) are not optimal for dataflow applications with large amount of data. On the opposite, point to point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data.

  6. Design and implementation of a simple acousto optic dual control circuit

    Science.gov (United States)

    Li, Biqing; Li, Zhao

    2017-04-01

    This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

  7. Adaptation of a Fault-Tolerant Fpga-Based Launch Sequencer as a Cubesat Payload Processor

    Science.gov (United States)

    2014-06-01

    FAULT–TOLERANT FPGA –BASED LAUNCH SEQUENCER AS A CUBESAT PAYLOAD PROCESSOR by Jordan K. Goff June 2014 Thesis Co-Advisors: Herschel H...TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE ADAPTATION OF A FAULT–TOLERANT FPGA –BASED LAUNCH SEQUENCER AS A CUBESAT PAYLOAD...set. This processor is implemented on a field programmable gate array ( FPGA ) and will be used as the foundation for a payload processor on a cube

  8. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  9. Analog circuit for controlling acoustic transducer arrays

    Energy Technology Data Exchange (ETDEWEB)

    Drumheller, Douglas S. (Cedar Crest, NM)

    1991-01-01

    A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

  10. DNA Strand-Displacement Timer Circuits.

    Science.gov (United States)

    Fern, Joshua; Scalise, Dominic; Cangialosi, Angelo; Howie, Dylan; Potters, Leo; Schulman, Rebecca

    2017-02-17

    Chemical circuits can coordinate elaborate sequences of events in cells and tissues, from the self-assembly of biological complexes to the sequence of embryonic development. However, autonomously directing the timing of events in synthetic systems using chemical signals remains challenging. Here we demonstrate that a simple synthetic DNA strand-displacement circuit can release target sequences of DNA into solution at a constant rate after a tunable delay that can range from hours to days. The rates of DNA release can be tuned to the order of 1-100 nM per day. Multiple timer circuits can release different DNA strands at different rates and times in the same solution. This circuit can thus facilitate precise coordination of chemical events in vitro without external stimulation.

  11. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    Directory of Open Access Journals (Sweden)

    D. K.M. Al-Aubidy

    2007-01-01

    Full Text Available This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the micro-operation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

  12. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  13. High-Performance CCSDS Encapsulation Service Implementation in FPGA

    Science.gov (United States)

    Clare, Loren P.; Torgerson, Jordan L.; Pang, Jackson

    2010-01-01

    The Consultative Committee for Space Data Systems (CCSDS) Encapsulation Service is a convergence layer between lower-layer space data link framing protocols, such as CCSDS Advanced Orbiting System (AOS), and higher-layer networking protocols, such as CFDP (CCSDS File Delivery Protocol) and Internet Protocol Extension (IPE). CCSDS Encapsulation Service is considered part of the data link layer. The CCSDS AOS implementation is described in the preceding article. Recent advancement in RF modem technology has allowed multi-megabit transmission over space links. With this increase in data rate, the CCSDS Encapsulation Service needs to be optimized to both reduce energy consumption and operate at a high rate. CCSDS Encapsulation Service has been implemented as an intellectual property core so that the aforementioned problems are solved by way of operating the CCSDS Encapsulation Service inside an FPGA. The CCSDS En capsula tion Service in FPGA implementation consists of both packetizing and de-packetizing features

  14. FPGA Simulation Engine for Customized Construction of Neural Microcircuits.

    Science.gov (United States)

    Blair, Hugh T; Cong, Jason; Wu, Di

    2013-04-01

    In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.

  15. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  16. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  17. Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA

    Directory of Open Access Journals (Sweden)

    Salman Sadruddin

    2013-01-01

    Full Text Available A novel and highly efficient design of a software defined radiation tolerant baseband module for a LEO satellite telecommand receiver using FPGA is presented. FPGAs in space are subject to single event upsets (SEUs due to high radiation environment. Traditionally, triple modular redundancy (TMR is used for mitigating Single Event Upsets (SEUs. The drawback of using TMR is that it consumes a lot of hardware resources and requires more power. Reduced precision redundancy (RPR can be a viable alternative of TMR in digital systems for arithmetic operations. This paper uses the combination of RPR and TMR for mitigating SEUs. The designed module consumes less resources on FPGA and has bit error rate (BER identical to theoretical results, apart from degradation due to implementation losses. An improved Costas loop and timing recovery algorithm are implemented for achieving carrier recovery and bit synchronization. The hybrid approach mitigates SEUs while consuming 26% less resources than a customary TMR protected receiver.

  18. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  19. A fast and accurate FPGA based QRS detection system.

    Science.gov (United States)

    Shukla, Ashish; Macchiarulo, Luca

    2008-01-01

    An accurate Field Programmable Gate Array (FPGA) based ECG Analysis system is described in this paper. The design, based on a popular software based QRS detection algorithm, calculates the threshold value for the next peak detection cycle, from the median of eight previously detected peaks. The hardware design has accuracy in excess of 96% in detecting the beats correctly when tested with a subset of five 30 minute data records obtained from the MIT-BIH Arrhythmia database. The design, implemented using a proprietary design tool (System Generator), is an extension of our previous work and uses 76% resources available in a small-sized FPGA device (Xilinx Spartan xc3s500), has a higher detection accuracy as compared to our previous design and takes almost half the analysis time in comparison to software based approach.

  20. Towards a FPGA-controlled deep phase modulation interferometer

    CERN Document Server

    Terán, M; Gesa, L l; Mateos, I; Gibert, F; Karnesis, N; Ramos-Castro, J; Schwarze, T S; Gerberding, O; Heinzel, G; Guzmán, F; Nofrarias, M

    2014-01-01

    Deep phase modulation interferometry was proposed as a method to enhance homodyne interferometers to work over many fringes. In this scheme, a sinusoidal phase modulation is applied in one arm while the demodulation takes place as a post-processing step. In this contribution we report on the development to implement this scheme in a fiber coupled interferometer controlled by means of a FPGA, which includes a LEON3 soft-core processor. The latter acts as a CPU and executes a custom made application to communicate with a host PC. In contrast to usual FPGA-based designs, this implementation allows a real-time fine tuning of the parameters involved in the setup, from the control to the post-processing parameters.

  1. Colorimetric Sensor Arrays System Based on FPGA for Image Recognition

    Institute of Scientific and Technical Information of China (English)

    Rui Chen; Jian-Hua Xu; Ya-Dong Jiang

    2009-01-01

    A FPGA-based image recognition system is designed for colorimetric sensor array in order to recognize a wide range of volatile organic compounds. The gas molecule is detected by the responsive sensor array and the responsive image is obtained. The image is decomposed to RGB color components using CMOS image sensor. An embedded image recognition archi- tecture based on Xilinx Spartan-3 FPGA is designed to implement the algorithms of image recognition. The algorithm of color coherence vector is discussed in detail[X1] compared with the algorithm of color histograms, and experimental results demonstrate that both of the two algorithms could be analyzed effectively to represent different volatile organic compounds according to their different responsive images in this system.

  2. Linux embebido en FPGA para sistemas de monitoreo industrial

    Directory of Open Access Journals (Sweden)

    José F. Carmona Martínez

    2013-03-01

    Full Text Available Actualmente la obtención en FPGA (Field Programmable Gate Array de módulos independientes para aplicaciones específicas de monitoreo industrial, ha hecho que su reutilización e integración sea compleja y que los tiempos de desarrollo y puesta a punto de los mismos sean considerablemente elevados. En este trabajo se propone una solución a este problema basada en embeber Linux en un FPGA, específicamente utilizando el kit Spartan3AN. Las herramientas de codiseño hardware/software utilizadas para lograr este objetivo han permitido tener resultados a corto plazo, que indican el enfoque para futuras investigaciones. De manera que se logró ejecutar aplicaciones de uso general para el control de ip-cores empotrados en hardware reconfigurable. La plataforma obtenida es estable y flexible a futuras implementaciones tanto de software como de hardware.

  3. FPGA-based amplitude and phase detection in DLLRF

    Institute of Scientific and Technical Information of China (English)

    LIU Rong; WANG Zheng; PAN Wei-Min; WANG Guang-Wei; LIN Hai-Ying; SHA Peng; ZENG Ri-Hua

    2009-01-01

    The new generation particle accelerator requires a highly stable radio frequency (RF) system. The stability of the RF system is realized by the Low Level RF (LLRF) subsystem which controls the amplitude and phase of the RF signal. The detection of the RF signal's amplitude and phase is fundamental to LLRF controls. High-speed ADC (Analog to Digital Converter), DAC (Digital to Analog Converter) and FPGA (Field Programmable Gate Array) play very important roles in digital LLRF control systems. This paper describes the implementation of real-time amplitude and phase detection based of the FPGA with an analysis of the main factors that affect the detection accuracy such as jitter, algorithm's defects and non-linearity of devices, which is helpful for future work on high precision detection and control.

  4. HIGH SPEED POINT ARITHMETIC ARCHITECTURE FOR ECC ON FPGA

    Directory of Open Access Journals (Sweden)

    Rahila Bilal,

    2010-09-01

    Full Text Available Elliptic curve cryptography plays a crucial role in networking and communication security. ECC have evolved in the recent past as an important alternative to established systems like RSA. This paper describes the implementation of an elliptic curve coprocessor based on the FPGA , which can provide a significant speedup for these cryptosystems. The FPGA configuration file is synthesized from VHDL code applying different hardware synthesis products. The implementation of ECC lies in three levels: scalar multiplication, point addition/doubling and finite field modular arithmetic. In this paper, we present a novel fast architecture for the point addition/doubling level in the projective coordinate. The proposed Architecture is based on Binary Field. The Design performs multiplication using Polynomial Basis. Analysis shows that, with reasonable hardware overhead, our architecture can achieve a high speedup for the point addition operation and point Doubling operation.Furthermore, the architecture is parameterized for different data widths to evaluate the optimal resource utilization.

  5. A digital coincidence measurement system using FPGA techniques

    Energy Technology Data Exchange (ETDEWEB)

    Zhu Fengming; Hsieh, S.C.; Yen, W.W. [Department of Engineering and System Science, National Tsing Hua University, Hsinchu, 30043, Taiwan (China); Chou, H.P., E-mail: hpc@ess.nthu.edu.tw [Department of Engineering and System Science, National Tsing Hua University, Hsinchu, 30043, Taiwan (China)

    2011-10-01

    A field programmable gate array (FPGA) based digital coincidence system has been developed to use with NaI scintillators for field applications. The analog output signal from the photomultiplier anode is directly transferred into digital signals by pulse height for pulse width conversion. The digital signal contains the energy and timing information of the radiation events. The pulse width is then measured by a vernier type of time-to-digital converter (TDC). The timing information of radiation events is recorded and analyzed by a coincidence unit. Both the TDC unit and the coincidence unit are implemented using a commercial available FPGA board. The measured data is then sent to a personal computer for spectrum display. Efficiency as well as energy calibration has been performed. The system showed a timing resolution about 13 ns and an energy resolution of 12% for 0.511 MeV annihilation gammas; it also successfully demonstrated the background rejection ability through coincidence measurement.

  6. FPGA-based Controller for a Mobile Robot

    CERN Document Server

    Kale, Shilpa

    2009-01-01

    With application in the robotics and automation, more and more it becomes necessary the development of applications based on methodologies that facilitate future modifications, updates and enhancements in the original projected system. This project presents a conception of mobile robots using rapid prototyping, distributing the several control actions in growing levels of complexity and computing proposal oriented to embed systems implementation. This kind of controller can be tested on different platform representing the mobile robots using reprogrammable logic components (FPGA). This mobile robot will detect obstacle and also be able to control the speed. Different modules will be Actuators, Sensors, wireless transmission. All this modules will be interfaced using FPGA controller. I would like to construct a mechanically simple robot model, which can measure the distance from obstacle with the aid of sensor and accordingly should able to control the speed of motor. I would like to construct a mechanically s...

  7. Application of FPGA technology to performance limitations in radiation therapy

    Science.gov (United States)

    DeMarco, John J.; Smathers, J. B.; Solberg, Tim D.; Casselman, Steve

    1996-10-01

    The field programmable gate array (FPGA) is a promising technology for increasing computation performance by providing for the design of custom chips through programmable logic blocks. This technology was used to implement and test a hardware random number generator (RNG) versus four software algorithms. The custom hardware consists of a sun SBus-based board (EVC) which has been designed around a Xilinx FPGA. A timing analysis indicates the Sun/EVC hardware generator computes 1 multiplied by 106 random numbers approximately 50 times faster than the multiplicative congruential algorithm. The hardware and software RNGs were also compare using a Monte Carlo photon transport algorithm. For this comparison the Sun/EVC generator produces a performance increase of approximately 2.0 versus the software generators. This comparison is based upon 1 multiplied by 105 photon histories.

  8. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  9. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...... the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible...

  10. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    CERN Document Server

    Liang, Yutie; Galuska, Martin J; Gessler, Thomas; Kühn, Wolfgang; Lange, Jens Sören; Wagner, Milan N; Liu, Zhen'an; Zhao, Jingzhou

    2016-01-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  11. Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth

    2015-01-01

    This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

  12. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  13. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  14. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolin, M.; Nald, G.; Mattan, A.; Maccaferr, A.; De Biagg, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  15. DNA Assembly with De Bruijn Graphs Using an FPGA Platform.

    Science.gov (United States)

    Poirier, Carl; Gosselin, Benoit; Fortier, Paul

    2017-04-24

    This paper presents an FPGA implementation of a DNA assembly algorithm, called Ray, initially developed to run on parallel CPUs. The OpenCL language is used and the focus is placed on modifying and optimizing the original algorithm to better suit the new parallelization tool and the radically different hardware architecture. The results show that the execution time is roughly one fourth that of the CPU and factoring energy consumption yields a tenfold savings.

  16. Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

    Science.gov (United States)

    Wiśniewski, Remigiusz; Grobelna, Iwona; Stefanowicz, Łukasz

    2016-12-01

    Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

  17. FPGA-oriented synthesis of multivalued logical networks

    Science.gov (United States)

    Deniziak, S.; Wiśniewski, M.; Kurczyna, K.

    2016-12-01

    Multivalued logical network consists of modules connected by multivalued signals. During synthesis each module is decomposed into smaller ones using the symbolic decomposition. Since the efficiency of the decomposition strongly depends on encoding of multivalued signals, the result of synthesis depends on the order, in which the consecutive modules are implemented. This paper presents the method of FPGA-oriented synthesis of multivalued logical networks. Experimental results showed that our approach significantly reduces the cost of implementation.

  18. Reconfiguring an FPGA-based RISC for LNS arithmetic

    Science.gov (United States)

    Arnold, Mark G.; Winkel, Mark D.

    2001-07-01

    Field Programmable Gate Arrays (FPGAs) have some difficulty with the implementation of floating-point operations. In particular, devoting the large number of slices needed by floating-point multipliers prohibits incorporating floating point into smaller, less expensive FPGAs. An alternative is the Logarithmic Number System (LNS), where multiplication and division are easy and fast. LNS also has the advantage of lower power consumption than fixed point. The problem with LNS has been the implementation of addition. There are many price/performance tradeoffs in the LNS design space between pure software and specialised-high-speed hardware. This paper focuses on a compromise between these extremes. We report on a small RISC core of our own design (loosely inspired by the popular ARM processor) in which only 4 percent additional investment in FPGA resources beyond that required for the integer RISC core more than doubles the speed of LNS addition compared to a pure software approach. Our approach shares resources in the datapath of the non-LNS parts of the RISC so that the only significant cost is the decoding and control for the LNS instruction. Since adoption of LNS depends on its cost effectiveness (e.g., FLOPs/slice), we compare our design against an earlier LNS ALU implemented in a similar FPGA. Our preliminary experiments suggest modest LNS-FPGA implementations, like ours, are more cost effective than pure software and can be as cost effective as more expensive LNS-FPGA implementations that attempt to maximise speed. Thus, our LNS-RISC fits in the Virtex-300, which is not possible for a comparable design.

  19. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  20. Hidden circuits and argumentation

    Science.gov (United States)

    Leinonen, Risto; Kesonen, Mikko H. P.; Hirvonen, Pekka E.

    2016-11-01

    Despite the relevance of DC circuits in everyday life and schools, they have been shown to cause numerous learning difficulties at various school levels. In the course of this article, we present a flexible method for teaching DC circuits at lower secondary level. The method is labelled as hidden circuits, and the essential idea underlying hidden circuits is in hiding the actual wiring of DC circuits, but to make their behaviour evident for pupils. Pupils are expected to find out the wiring of the circuit which should enhance their learning of DC circuits. We present two possible ways to utilise hidden circuits in a classroom. First, they can be used to test and enhance pupils’ conceptual understanding when pupils are expected to find out which one of the offered circuit diagram options corresponds to the actual circuit shown. This method aims to get pupils to evaluate the circuits holistically rather than locally, and as a part of that aim this method highlights any learning difficulties of pupils. Second, hidden circuits can be used to enhance pupils’ argumentation skills with the aid of argumentation sheet that illustrates the main elements of an argument. Based on the findings from our co-operating teachers and our own experiences, hidden circuits offer a flexible and motivating way to supplement teaching of DC circuits.

  1. Neural harmonic detection approaches for FPGA area efficient implementation

    Science.gov (United States)

    Dzondé, S. R. N.; Kom, C.-H.; Berviller, H.; Blondé, J.-P.; Flieller, D.; Kom, M.; Braun, F.

    2011-12-01

    This paper deals with new neural networks based harmonics detection approaches to minimize hardware resources needed for FPGA implementation. A simple type of neural network called Adaline is used to build an intelligent Active Power Filter control unit for harmonics current elimination and reactive power compensation. For this purpose, two different approaches called Improved Three-Monophase (ITM) and Two-Phase Flow (TPF) methods are proposed. The ITM method corresponds to a simplified structure of the three-monophase method whereas the TPF method derives from the Synchronous Reference Frame method. Indeed, for both proposed methods, only 50% of Adalines with regard to the original methods is used. The corresponding designs were implemented on a FPGA Stratix II platform through Altera DSP Builder® development tool. After analyzing those two methods with respect to performance and size criteria, a comparative study with the popular p-q and also the direct method is reported. From there, one can notice that the p-q is still the most powerful method for three-phase compensation but the TPF method is the fastest and the most compact in terms of size. An experimental result is shown to validate the feasibility of FPGA implementation of ANN-based harmonics extraction algorithms.

  2. Design of transient light signal simulator based on FPGA

    Science.gov (United States)

    Kang, Jing; Chen, Rong-li; Wang, Hong

    2014-11-01

    A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

  3. An FPGA implementation to detect selective cationic antibacterial peptides.

    Science.gov (United States)

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides.

  4. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  5. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  6. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  7. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    2013-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  8. An FPGA Based Controller for a SOFC DC-DC Power System

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Bhuyan

    2013-01-01

    Full Text Available Fuel cells are an attractive option for alternative power and of use in a variety of applications. This paper proposes a state space model for the solid oxide fuel cell (SOFC based power system that comprises fuel cell, DC-DC buck converter, and load. In this investigation we have taken up a case study for SOFC feeding a DC load where a DC-DC buck converter acts as the interface between the load and the source. A proportional-integral (PI controller is used in conjunction with pulse width modulation (PWM that computes the pulse width and switches the MOSFET at the right instant so that the desired voltage is obtained. The proposed model is validated through extensive simulation using MATLAB/SIMULINK. Controller for the fuel cell power system (FCPS is prototyped using XC3S500E development board containing a SPARTAN 3E Xilinx FPGA that simplifies the entire control circuit besides providing additional flexibility for further improvement. The results clearly indicate improved performance and validate our proposed model.

  9. AES Cardless Automatic Teller Machine (ATM) Biometric Security System Design Using FPGA Implementation

    Science.gov (United States)

    Ahmad, Nabihah; Rifen, A. Aminurdin M.; Helmy Abd Wahab, Mohd

    2016-11-01

    Automated Teller Machine (ATM) is an electronic banking outlet that allows bank customers to complete a banking transactions without the aid of any bank official or teller. Several problems are associated with the use of ATM card such card cloning, card damaging, card expiring, cast skimming, cost of issuance and maintenance and accessing customer account by third parties. The aim of this project is to give a freedom to the user by changing the card to biometric security system to access the bank account using Advanced Encryption Standard (AES) algorithm. The project is implemented using Field Programmable Gate Array (FPGA) DE2-115 board with Cyclone IV device, fingerprint scanner, and Multi-Touch Liquid Crystal Display (LCD) Second Edition (MTL2) using Very High Speed Integrated Circuit Hardware (VHSIC) Description Language (VHDL). This project used 128-bits AES for recommend the device with the throughput around 19.016Gbps and utilized around 520 slices. This design offers a secure banking transaction with a low rea and high performance and very suited for restricted space environments for small amounts of RAM or ROM where either encryption or decryption is performed.

  10. The Design of FPGA-based Array CCD Sensor Drive System

    Directory of Open Access Journals (Sweden)

    Chengtao Cai

    2014-01-01

    Full Text Available CCD Sensor is the crutial equipment for environment perception which is widely used in various fields such as surveilliance,vision navigation and machine vision. The commercial CCD device has been encapsulated the sensor driver inside which is not opened for secondary development. Even this mode facilitate the usage but it really can not content the customizable need. For solving this challenging but imperative issue, we designed a novel CCD sensor driver system which implement the efficient and effective image acquisition task in customizing approach. The working principle and driving timing sequence about ICX625AQA the interline CCD image sensor used in our system are discussed in detail. For handling with this data intensive task, a high performance Field Programmable GateArray (FPGA controller is used for data allocation and translation, the peripheral circuits including AD9974 and CXD3400 drive interface which process the horizontal signal and vertical signal, respectively. The designed system proposed at the end of this paper.

  11. FPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach

    Directory of Open Access Journals (Sweden)

    Zulhelmi .

    2014-03-01

    Full Text Available This paper proposes design and implementation of a 16-bit multiplier based upon Vedic mathematicapproach, where the design has been targeted to the Xilinx Field Programmable Gate Arrays (FPGAs board, deviceXC5VLX30. The approach is different from a number of approaches that have been used to realize multipliers.  Ithas been reported that previous algorithms such as Booth, Modified Booth, and Carry  Save Multipliers only suitablefor improving  speed or decreasing area utilization; therefore, those algorithms are not appropriate for designingmultipliers that are used for digital signal processing (DSP applications. Moreover, they are not flexible to beimplemented on FPGAs or on a single chip using application specific integration circuits (ASICs. Vedic approach,on the other hand, can be used to design multipliers with optimum speed and less area utilization. In addition, it isreliable to be implemented on FPGAs or on a single chip.  Behavioral and post-route simulation results prove that theproposed multiplier shows better performance in terms of speed compared to the other reported multipliers whenbeing  implemented on the FPGA. In terms of area utilization, better results are also obtained.

  12. Noise impact of single-event upsets on an FPGA-based digital filter

    Energy Technology Data Exchange (ETDEWEB)

    Morgan, Keith S [Los Alamos National Laboratory; Caffrey, Michael P [Los Alamos National Laboratory; Graham, Paul S [Los Alamos National Laboratory; Pratt, Brian H [Los Alamos National Laboratory; Wirthlin, Michael J [BYU

    2009-01-01

    Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.

  13. BDD, BNN, and FPGA on Fuzzy Techniques for Rapid System Analysis

    Directory of Open Access Journals (Sweden)

    Rahul Dixit

    2012-01-01

    Full Text Available This paper looks at techniques to simplify data analysis of large multivariate military sensor systems. The approach is illustrated using representative raw data from a video-scene analyzer. First, develop fuzzy neural net relations using Matlab. This represents the best fidelity fit to the data and will be used as reference for comparison. The data is then converted to Boolean, and using Boolean Decision Diagrams (BDD techniques, to find similar relations between input vectors and output parameter. It will be shown that such Boolean techniques offer dramatic improvement in system analysis time, and with minor loss of fidelity. To further this study, Boolean Neural Net techniques (BNN were employed to bridge the Fuzzy Neural Network (FNN to BDD representations of the data. Neural network approaches give an estimation method for the complexity of Boolean Decision Diagrams, and this can be used to predict the complexity of digital circuits. The neural network model can be used for complexity estimation over a set of BDDs derived from Boolean logic expressions. Experimental results show good correlation with theoretical results and give insights to the complexity. The BNN representations can be useful as a means to FPGA implementation of the system relationships and can be used in embedded processor based multi-variate situations.

  14. 基于USB-FIFO的FPGA与上位机通信的设计与实现%Design of Communication Between PC and FPGA Based on USB-FIFO

    Institute of Scientific and Technical Information of China (English)

    裴向东; 陈箫; 谭秋林; 朱思敏; 熊继军

    2012-01-01

    This paper has described the operation principle of the FT245RL which is an USB protocol chipi designed the interface circuit between FT245RL and FPGA,showed the description of the FPGA to send and receive data frames used VHDL language. And debuged the communication between FPGA and the host computer. It has facilitated the circuit design and improved the tesi efficiency, the design has a strong all-purpose commonality, the design has been successfully applied to some space test devices.%介绍了USB协议芯片FT245RL的工作原理,设计了FT245RL与FPGA的接口电路,给出了FPGA发送和接收数据帧状态机的VHDL语言的描述,并调试其与上位机的通信;简化了电路设计,提高了测试效率,该设计具有很强的通用性,该电路已成功地应用到航天某型号的测试设备中.

  15. Assessment of Proper Bonding Methods and Mechanical Characterization FPGA CQFPs

    Science.gov (United States)

    Davis, Milton C.

    2008-01-01

    This presentation discusses fractured leads on field-programmable gate array (FPGA) during flight vibration. Actions taken to determine root cause and resolution of the failure include finite element analysis (FEA) and vibration testing and scanning electron microscopy (with X-ray microanalysis) and energy dispersive spectrometry (SEM/EDS) failure assessment. Bonding methods for surface mount parts is assessed, including critical analysis and assessment of random fatigue damage. Regarding ceramic quad flat pack (CQFP) lead fracture, after disassembling the attitude control electronics (ACE) configuration, photographs showed six leads cracked on FPGA RTSX72SU-1 CQ208B package located on the RWIC card. An identical package (FPGA RTSX32SU-1 CQ208B) mounted on the RWIC did not results in cracked pins due to vibration. FPGA lead failure theories include workmanship issues in the lead-forming, material defect in the leads of the FPGA packages, and the insecure mounting of the board in the card guides, among other theories. Studies were conducted using simple calculations to determine the response and fatigue life of the package. Shorter packages exhibited more response when loaded by out-of-plane displacement of PCB while taller packages exhibit more response when loaded by in-plane acceleration of PCB. Additionally, under-fill did not contribute to reducing stress in leads due to out-of-plane PCB loading or from component twisting, as much as corner bonding. The combination of corner bond and under-fill is best to address mechanical and thermal S/C environment. Test results of bonded parts showed reduced (dampened) amplitude and slightly shifted peaks at the un-bonded natural frequency and an additional response at the bonded frequency. Stress due to PCBB out-of-plane loading was decreased on in the corners when only a corner bond was used. Future work may address CQFP fatigue assessment, including the investigation of discrepancy in predicted fatigue damage, as well as

  16. SAD5 Stereo Correlation Line-Striping in an FPGA

    Science.gov (United States)

    Villalpando, Carlos Y.; Morfopoulos, Arin C.

    2011-01-01

    High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output. In stereo, the general rule of thumb is that the disparity search range must be 1/10 the image size. In the new algorithm, BRAM usage scales linearly with disparity search range and scales again linearly with line width. So a doubling of image size, say from 640 to 1,280, would in the previous design be an effective 4 of BRAM usage: 2 for line width, 2 again for disparity search range. The minimum strip size is twice the search range, and will produce an output strip width equal to the disparity search range. So assuming a disparity search range of 1/10 image width, 10 sequential runs of the minimum strip size would produce a full output image. This approach allowed the innovators to fit 1280 960 wide SAD5 stereo disparity in less than 80 BRAM, 52k Slices on a Virtex 5LX330T, 25% and 24% of resources, respectively. Using a 100-MHz clock, this build would perform stereo at 39 Hz. Of particular interest to JPL is that there is a flight qualified version of the Virtex 5: this could produce stereo results even for very large image sizes at 3 orders of magnitude faster than could be computed on the PowerPC 750 flight computer. The work covered in the report allows the stereo algorithm to run on much larger images than before, and using much less BRAM. This opens up choices for a smaller flight FPGA (which saves power and space), or for other algorithms

  17. Diseño e implementación con FPGA de un demodulador para comunicaciones digitales

    OpenAIRE

    Guerrero Balmori, Juan Antonio

    2006-01-01

    Haciendo uso de un kit de desarrollo de FPGA's de Xilinx se deberá programar una FPGA para implementar un demodulador digital que formará parte de un sistema linealizador de amplificadores de radiofrecuencia.

  18. Diseño e implementación con FPGA de un demodulador para comunicaciones digitales

    OpenAIRE

    Guerrero Balmori, Juan Antonio

    2006-01-01

    Haciendo uso de un kit de desarrollo de FPGA's de Xilinx se deberá programar una FPGA para implementar un demodulador digital que formará parte de un sistema linealizador de amplificadores de radiofrecuencia.

  19. Measuring information-transfer delays.

    Directory of Open Access Journals (Sweden)

    Michael Wibral

    Full Text Available In complex networks such as gene networks, traffic systems or brain circuits it is important to understand how long it takes for the different parts of the network to effectively influence one another. In the brain, for example, axonal delays between brain areas can amount to several tens of milliseconds, adding an intrinsic component to any timing-based processing of information. Inferring neural interaction delays is thus needed to interpret the information transfer revealed by any analysis of directed interactions across brain structures. However, a robust estimation of interaction delays from neural activity faces several challenges if modeling assumptions on interaction mechanisms are wrong or cannot be made. Here, we propose a robust estimator for neuronal interaction delays rooted in an information-theoretic framework, which allows a model-free exploration of interactions. In particular, we extend transfer entropy to account for delayed source-target interactions, while crucially retaining the conditioning on the embedded target state at the immediately previous time step. We prove that this particular extension is indeed guaranteed to identify interaction delays between two coupled systems and is the only relevant option in keeping with Wiener's principle of causality. We demonstrate the performance of our approach in detecting interaction delays on finite data by numerical simulations of stochastic and deterministic processes, as well as on local field potential recordings. We also show the ability of the extended transfer entropy to detect the presence of multiple delays, as well as feedback loops. While evaluated on neuroscience data, we expect the estimator to be useful in other fields dealing with network dynamics.

  20. Electrical Circuits and Water Analogies

    Science.gov (United States)

    Smith, Frederick A.; Wilson, Jerry D.

    1974-01-01

    Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)