Feasibility study to use an SRAM-based FPGA in the readout electronics of the upgraded LHCb outer tracker detector

International Nuclear Information System (INIS)

Faerber, Christian

2014-01-01

This thesis presents a study of the feasibility to use SRAM-based FPGAs as central component of the upgraded LHCb Outer Tracker readout electronics. The FPGA should contain the functionality of a TDC and should provide fast data links using multi-GBit/s transceivers. The TDC core that was developed provides 5 bit time measurements for 32 channels with a bin size of 780 ps. The TDC has the required time resolution of better than 1 ns. This was achieved by manually placing every logic element of the TDC channels and with an iterative procedure feeding timing measurements back to the Place and Route step of the router software. A transceiver and TDC card, and an adapter board for the existing readout electronics was developed. Both boards were used successfully to read out drift times from an Outer Tracker straw-tube module in a cosmic setup. To qualify the proposed electronics for the expected radiation levels an irradiation test with 22 MeV protons and two FPGA boards was performed up to a total ionization dose of 30 Mrad. Both chips sustained the irradiation expected for the full life time of the upgraded LHCb detector of up to 30 krad. After an irradiation dose of 150 krad the first deteriorations of the performance of the chips were observed. The proton cross section for configuration bit flips was determined to be 1.6.10 16 cm 2 per bit. The measured error rate scaled to the upgrade environment would correspond to a manageable firmware error rate.

Data acquisition system for charge-division mechanism based on FPGA

International Nuclear Information System (INIS)

Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

2010-01-01

Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

Radiation tolerance studies using fault injection on the Readout Control FPGA design of the ALICE TPC detector

Science.gov (United States)

Alme, J.; Fehlker, D.; Lippmann, C.; Mager, M.; Rehman, A. U.; Røed, K.; Röhrich, D.; Ullaland, K.

2013-01-01

Single Event Upsets (SEUs) are a major concern for the TPC Readout Control Unit (RCU) of the ALICE experiment. A SEU is defined as a radiation related bit-flip in a memory cell, and a SEU in the onboard SRAM based FPGA of the RCU may lead to corrupted data or, even worse, a system malfunction. The latter situation will affect the operation of the ALICE detector since it causes a premature end of data taking. Active partial reconfiguration is utilized in a dedicated reconfiguration solution on the RCU, and this makes it possible to implement fault injection. Fault injection means inserting bit flips in the configuration memory of the FPGA in a controlled laboratory environment. This paper presents the results of the fault injection study and shows how this result can be combined with SEU measurements to estimate the functional failure rate as a function of luminosity.

Study of FPGA and GPU based pixel calibration for ATLAS IBL

CERN Document Server

Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

2010-01-01

The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

The new FPGA based discriminator board for the CBELSA/TAPS experiment

Energy Technology Data Exchange (ETDEWEB)

Fix, Eugenia [HISKP, Universitaet Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

2016-07-01

The Crystal Barrel calorimeter at ELSA, which consists of 1320 CsI(Tl) crystals has been upgraded by a new Avalanche Photo Diode (APD) crystal readout.The APD readout electronics will provide a fast trigger signal down to 10 MeV energy deposit per single crystal. The processing of these trigger signals requires the development of a previously not existent timing branch of the readout chain of the Crystal Barrel calorimeter. Core component of the timing branch is a newly developed, FPGA based discriminator board. Its firmware contains modules for time to digital conversion, rise time compensation and parts of a cluster finder. In addition the reference voltages and discriminator thresholds are controlled and monitored. This poster presents the design and the achievable accuracy of the new discriminator.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

FPGA-based upgrade of the read-out electronics for the low energy polarimeter at COSY/Juelich

Energy Technology Data Exchange (ETDEWEB)

Hempelmann, Nils [Institut fuer Kernphysik, Forschungszentrum Juelich (Germany); Collaboration: JEDI-Collaboration

2016-07-01

The Cooler Synchrotron (COSY) is a facility for cooled polarized beams at the Forschungszentrum in Juelich. The Low Energy Polarimeter (LEP) is the polarimeter in the injection beam line of COSY. The beam polarization is measured using scattering off carbon and polyethylene (CH2) targets. The outgoing particles are detected using twelve plastic scintillators installed in groups of three to the left, to the right, above, and below the beam. The LEP is the routine tool for beam set-up, but its performance was limited by the old read-out electronics consisting of analog NIM modules. A new system using analog pulse sampling and an FPGA chip for signal processing was installed and tested. The ejectile particles were identified by relative time of flight measurement using a signal from the RF amplifier of the cyclotron used for acceleration as a reference. The new system is able to measure the time at which a particle arrives to an accuracy in the order of 50 ps. The presentation includes a review of available systems and a report about measurements in May and December 2015.

Development of an event builder for the new SADC-readout of the crystal barrel calorimeter

Energy Technology Data Exchange (ETDEWEB)

Schultes, Jan; Muellers, Johannes [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

2016-07-01

The CBELSA/TAPS experiment at the electron accelerator ELSA in Bonn investigates the photoproduction of mesons off nucleons. Presently the readout of the CsI(Tl)-crystals of the Crystal Barrel calorimeter is being upgraded from a PIN-diode readout to an APD readout to create a fast signal for first-level-triggering. Furthermore, an entirely new setup consisting of Sampling-ADCs (SADC) with FPGA-based readout is being prepared to increase the possible data rate achievable. The SADC is capable of sampling pulses from the detector with 80 MHz, extracting features by FPGA-logic and transferring this data via UDP. To improve package-handling, a server-client structure will be provided. It is foreseen to receive packages from each of the 48 SADC units (32 channels each), detect and handle possible package losses, distribute the received information further via TCP and control the SADC-behaviour. In addition and to assist the FPGA firmware development, a tool to monitor outgoing pulses and to extract important features, such as the deposited energy, timing information and pile-up detection to cross-check the information given by the FPGA is being developed.

Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

CERN Document Server

Åkerstedt, Henrik; The ATLAS collaboration; Drake, Gary; Anderson, Kelby; Bohm, Christian; Oreglia, Mark; Tang, Fukun

2015-01-01

The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of ...

Implementation of the Timepix ASIC in the Scalable Readout System

Energy Technology Data Exchange (ETDEWEB)

Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

2016-09-11

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

International Nuclear Information System (INIS)

Ericson, M.N.; Allen, M.D.; Boissevain, J.

1997-11-01

Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

Qualification of FPGA-Based Safety-Related PRM System

International Nuclear Information System (INIS)

Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

2011-01-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

Flexible experimental FPGA based platform

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2016-01-01

This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

LHCb: Radiation tolerance tests of SRAM-based FPGAs for the possible usage in the readout electronics for the LHCb experiment

CERN Multimedia

Faerber, C; Wiedner, D; Leveringzon, B; Ekelhof, R

2013-01-01

This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfils the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of 10$^{-6}$ Hz makes the chip viable for the LHCb Upgrade.

Irradiation test of FPGA for BES III

International Nuclear Information System (INIS)

Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

2005-01-01

The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

An optical fiber-based flexible readout system for micro-pattern gas detectors

Science.gov (United States)

Li, C.; Feng, C. Q.; Zhu, D. Y.; Liu, S. B.; An, Q.

2018-04-01

This paper presents an optical fiber-based readout system that is intended to provide a general purpose multi-channel readout solution for various Micro-Pattern Gas Detectors (MPGDs). The proposed readout system is composed of several front-end cards (FECs) and a data collection module (DCM). The FEC exploits the capability of an existing 64-channel generic TPC readout ASIC chip, named AGET, to implement 256 channels readout. AGET offers FEC a large flexibility in gain range (4 options from 120 fC to 10 pC), peaking time (16 options from 50 ns to 1 us) and sampling freqency (100 MHz max.). The DCM contains multiple 1 Gbps optical fiber serial link interfaces that allow the system scaling up to 1536 channels with 6 FECs and 1 DCM. Further scaling up is possible through cascading of multiple DCMs, by configuring one DCM as a master while other DCMs in slave mode. This design offers a rapid readout solution for different application senario. Tests indicate that the nonlinearity of each channel is less than 1%, and the equivalent input noise charge is typically around 0.7 fC in RMS (root mean square), with a noise slope of about 0.01 fC/pF. The system level trigger rate limit is about 700 Hz in all channel readout mode. When in hit channel readout mode, supposing that typically 10 percent of channels are fired, trigger rate can go up to about 7 kHz. This system has been tested with Micromegas detector and GEM detector, confirming its capability in MPGD readout. Details of hardware and FPGA firmware design, as well as system performances, are described in the paper.

Development and Implementation of Optimal Filtering in a Virtex FPGA for the Upgrade of the ATLAS LAr Calorimeter Readout

CERN Document Server

Stärz, S; The ATLAS collaboration

2012-01-01

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation in the high-luminosity phase of the LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming detector signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

Overview and future developments of the FPGA-based DAQ of COMPASS

Energy Technology Data Exchange (ETDEWEB)

Bai, Yunpeng; Huber, Stefan; Konorov, Igor; Levit, Dmytro [Physik-Department E18, Technische Universitaet Muenchen (Germany); Bodlak, Martin [Department of Low-Temperature Physics, Charles University Prague (Czech Republic); Frolov, Vladimir [European Organization for Nuclear Research - CERN (Switzerland); Jary, Vladimir; Virius, Miroslav [Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Novy, Josef [European Organization for Nuclear Research - CERN (Switzerland); Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Steffen, Dominik [Physik-Department E18, Technische Universitaet Muenchen (Germany); European Organization for Nuclear Research - CERN (Switzerland)

2016-07-01

COMPASS is a fixed-target experiment at the SPS accelerator at CERN dedicated to the study of hadron structure and spectroscopy. In 2014, an FPGA-based data acquisition system (FDAQ) was deployed. Its hardware event builder consisting of nine custom designed FPGA-cards replaced 30 distributed online computers and around 100 PCI cards. As a result, the new DAQ provides higher bandwidth and better reliability. By buffering the data, the system exploits the spill structure of the SPS averaging the maximum on-spill data rate of 1.5 GB/s over the whole SPS duty cycle. A modern run control software allows user-friendly monitoring and configuration of the hardware nodes of the event builder. From 2016, it is planned to wire all point-to-point high-speed links via a fully programmable crosspoint switch. The crosspoint switch will provide a fully customizable DAQ network topology between front-end electronics, the event building hardware, and the readout computers. It will therefore simplify compensation for hardware failure and improve load balancing.

Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS

CERN Document Server

Singpiel, Holger

2000-01-01

This thesis describes the conception and implementation of the hybrid FPGA/CPU based processing system ATLANTIS as trigger processor for the proposed ATLAS experiment at CERN. CompactPCI provides the close coupling of a multi FPGA system and a standard CPU. The system is scalable in computing power and flexible in use due to its partitioning into dedicated FPGA boards for computation, I/O tasks and a private communication. Main focus of the research activities based on the usage of the ATLANTIS system are two areas in the second level trigger (LVL2). First, the acceleration of time critical B physics trigger algorithms is the major aim. The execution of the full scan TRT algorithm on ATLANTIS, which has been used as a demonstrator, results in a speedup of 5.6 compared to a standard CPU. Next, the ATLANTIS system is used as a hardware platform for research work in conjunction with the ATLAS readout systems. For further studies a permanent installation of the ATLANTIS system in the LVL2 application testbed is f...

FPGA-based 10-Gbit Ethernet Data Acquisition Interface for the Upgraded Electronics of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Grohs, J P; The ATLAS collaboration

2013-01-01

The readout of the trigger signals of the ATLAS Liquid Argon (LAr) calorimeters is foreseen to be upgraded in order to prepare for operation during the first high-luminosity phase of the Large Hadron Collider (LHC). Signals with improved spatial granularity are planned to be received from the detector by a Digitial Processing System (DPS) in ATCA technology and will be sent in real-time to the ATLAS trigger system using custom optical links. These data are also sampled by the DPS for monitoring and will be read out by the regular Data Acquisition (DAQ) system of ATLAS which is a network-based PC-farm. The bandwidth between DPS module and DAQ system is expected to be in the order of 10 Gbit/s per module and a standard Ethernet protocol is foreseen to be used. DSP data will be prepared and sent by a modern FPGA either through a switch or directly to a Read-Out System (ROS) PC serving as buffer interface of the ATLAS DAQ. In a prototype setup, an ATCA blade equipped with a Xilinx Virtex-5 FPGA is used to send da...

The prototype readout chain for CBM using the AFCK board and its software components

Science.gov (United States)

Loizeau, Pierre-Alain; Emscherman, David; Lehnert, Jörg; Müller, Walter F. J.; Yang, Junfeng

2015-09-01

This paper presents a prototype for the readout chain of the Compressed Baryonic Matter (CBM) experiment using the AFCK FPGA board as Data Processing Board (DPB). The components of the readout chain are described, followed by some test setups, all based on different flavors of AFCK-DPB. Details about the functional blocks in the different versions of the DPB firmware are given, followed by a description of the corresponding software elements.

The MCD circuit based on FPGA

International Nuclear Information System (INIS)

Vu Quoc Trong

2003-01-01

Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

Multichannel FPGA-Based Data-Acquisition-System for Time-Resolved Synchrotron Radiation Experiments

Science.gov (United States)

Choe, Hyeokmin; Gorfman, Semen; Heidbrink, Stefan; Pietsch, Ullrich; Vogt, Marco; Winter, Jens; Ziolkowski, Michael

2017-06-01

The aim of this contribution is to describe our recent development of a novel compact field-programmable gatearray (FPGA)-based data acquisition (DAQ) system for use with multichannel X-ray detectors at synchrotron radiation facilities. The system is designed for time resolved counting of single photons arriving from several-currently 12-independent detector channels simultaneously. Detector signals of at least 2.8 ns duration are latched by asynchronous logic and then synchronized with the system clock of 100 MHz. The incoming signals are subsequently sorted out into 10 000 time-bins where they are counted. This occurs according to the arrival time of photons with respect to the trigger signal. Repeatable mode of triggered operation is used to achieve high statistic of accumulated counts. The time-bin width is adjustable from 10 ns to 1 ms. In addition, a special mode of operation with 2 ns time resolution is provided for two detector channels. The system is implemented in a pocketsize FPGA-based hardware of 10 cm × 10 cm × 3 cm and thus can easily be transported between synchrotron radiation facilities. For setup of operation and data read-out, the hardware is connected via USB interface to a portable control computer. DAQ applications are provided in both LabVIEW and MATLAB environments.

Development of FPGA-based safety-related I and C systems

Energy Technology Data Exchange (ETDEWEB)

Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

2006-07-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

100 Gbps PCI-Express readout for the LHCb upgrade

International Nuclear Information System (INIS)

Durante, P.; Neufeld, N.; Schwemmer, R.; Balbi, G.; Marconi, U.

2015-01-01

We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-Express bus, on Altera Stratix 5 devices, using a DMA mechanism and different synchronization schemes between the FPGA and the readout unit. Finally we discuss hardware and software design considerations necessary to achieve a data throughput of 100 Gbps in the final readout board

Development of FPGA-based safety-related instrumentation and control systems

Energy Technology Data Exchange (ETDEWEB)

Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

2004-07-01

Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

SPIDR, a general-purpose readout system for pixel ASICs

International Nuclear Information System (INIS)

Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

2017-01-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Energy Technology Data Exchange (ETDEWEB)

Cardinali, Matteo [Helmholtz Institut Mainz (Germany); Collaboration: PANDA Cherenkov-Collaboration

2014-07-01

The next generation of high-luminosity experiments requires excellent Particle Identification (PID) detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected data rates. The planned PANDA experiment at FAIR expects average interaction rates of 20 MHz. A Barrel DIRC will provide PID in the central region of the Target Spectrometer. A single photo-electron timing resolution of better than 100 ps is projected for the Barrel DIRC to disentangle the complicated patterns created by the focusing optics on the image plane. The typically large amount of readout channels (approx 15,000 in case of the PANDA Barrel DIRC) places non-negligible limits on size and power consumption of the Front-End Electronics (FEE). The proposed design is based on the TRBv3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom FEE with high-bandwidth pre-amplifiers and fast discriminators. Two types of FEE cards optimised for reading out 64-channel Photonis Planacon MCP-PMTs were tested: one based on the NINO ASIC developed for the ALICE RPC readout and the other, called PaDiWa, using FPGA-based discriminators. Both types of FEE cards were tested with a small DIRC prototype comprising a radiator bar with focusing lens and an oil-filled expansion volume instrumented with 6 Planacon 64-channel MCP-PMTs. In the presentation the result of a test experiment performed at MAMI B, Mainz, are addressed.

A new PCI card for readout in high energy physics experiments

CERN Document Server

Floris, M; Marras, D; Usai, G L; David, A

2004-01-01

Recently some high energy physics experiments started to adopt readout systems based on the PCI architecture. In this context a new PCI card that can be adapted to several readout schemes has been designed. The card contains a large 64 MB local buffer, programmable FPGA logic and a PLX PCI bridge. The solution to use a PCI bridge external to the programmable logic allows to greatly simplify projects at the level of the on-board local bus. The card is presently used as the basic readout unit of the NA60 experiment. In this context, coupling it to different mezzanine cards it is possible to create interfaces to VME/CAMAC modules or to custom front-end electronics as for the case of the silicon vertex detector. Moreover, it is used as a readout test system for the ALICE muon chambers. (10 refs).

Acceleration of Cherenkov angle reconstruction with the new Intel Xeon/FPGA compute platform for the particle identification in the LHCb Upgrade

Science.gov (United States)

Faerber, Christian

2017-10-01

The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40 MHz. This increases the data bandwidth from the detector down to the Event Filter farm to 40 TBit/s, which also has to be processed to select the interesting proton-proton collision for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new Event Filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade the usage of an experimental FPGA accelerated computing platform in the Event Building or in the Event Filter farm is being considered and therefore tested. This platform from Intel hosts a general CPU and a high performance FPGA linked via a high speed link which is for this platform a QPI link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. As a first step, a computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported in Verilog to the Intel Xeon/FPGA platform and accelerated by a factor of 35. The same algorithm was ported to the Intel Xeon/FPGA platform with OpenCL. The implementation work and the performance will be compared. Also another FPGA accelerator the Nallatech 385 PCIe accelerator with the same Stratix V FPGA were tested for performance. The results show that the Intel

100 Gbps PCI-Express Readout for the LHCb Upgrade

CERN Document Server

Durante, Paolo; Schwemmer, Rainer; Marconi, Umberto; Balbi, Gabriele; Lax, Ignazio

2015-01-01

We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new common readout board, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We describe a new high-performance DMA controller for data acquisition, implemented on an FPGA, coupled with a custom software module for the Linux kernel. Lastly, we describe how these components can be leveraged to achieve a throughput of 100 Gbit/s per readout board.

Flexible, fpga-based electronics for modular robots

DEFF Research Database (Denmark)

Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

2008-01-01

In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

Control software for the CBM readout chain

Energy Technology Data Exchange (ETDEWEB)

Loizeau, Pierre-Alain [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH (Germany)

2016-07-01

The Compressed Baryonic Matter (CBM) experiment, which will be built at FAIR, will use free-streaming readout electronics to acquire high-statistics data-sets of physics probes in fixed target heavy-ion collisions. Since no simple signatures suitable for a hardware trigger are available for most of them, reconstruction and selection of the interesting collisions will be done in software, in a computer farm called First Level Event Selector (FLES). The raw data coming from the detectors is pre-processed, pre-calibrated and aggregated in a FPGA based layer called Data Preprocessing Boards (DPB). IPbus will be used to communicate with the DPBs and through them with the elements of the readout chain closer to detectors. A slow control environment based on this software is developed by CBM to configure in an efficient way the DPBs as well as the Front-End Electronics and monitor their performances. This contribution presents the layout planned for the slow control software, its first implementation and corresponding test results.

FPGA based Control of a Production Cell System

NARCIS (Netherlands)

Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

Verification of FPGA-based NPP I and C systems. General approach and techniques

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

2011-01-01

This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

Time over threshold readout method of SiPM based small animal PET detector

International Nuclear Information System (INIS)

Valastyan, I.; Gal, J.; Hegyesi, G.; Kalinka, G.; Nagy, F.; Kiraly, B.; Imrek, J.; Molnar, J.

2012-01-01

Complete text of publication follows. The aim of the work was to design a readout concept for silicon photomultiplier (SiPM) sensor array used in small animal PET scanner. The detector module consist of LYSO 35x35 scintillation crystals, 324 SiPM sensors (arranged in 2x2 blocks and those quads in a 9x9 configuration) and FPGA based readout electronics. The dimensions of the SiPM matrix are area: 48x48 mm 2 and the size of one SiPM sensor is 1.95x2.2 mm 2 . Due to the high dark current of the SiPM, conventional Anger based readout method does not provide sufficient crystal position maps. Digitizing the 324 SiPM channels is a straightforward way to obtain proper crystal position maps. However handling hundreds of analogue input channels and the required DSP resources cause large racks of data acquisition electronics. Therefore coding of the readout channels is required. Proposed readout method: The coding of the 324 SiPMs consists two steps: Step 1) Reduction of the channels from 324 to 36: Row column readout, SiPMs are connected to each other in column by column and row-by row, thus the required channels are 36. The dark current of 18 connected SiPMs is small in off for identifying pulses coming from scintillating events. Step 2) Reduction of the 18 rows and columns to 4 channels: Comparators were connected to each rows and columns, and the level was set above the level of dark noise. Therefore only few comparators are active when scintillation light enters in the tile. The output of the comparator rows and columns are divided to two parts using resistor chains. Then the outputs of the resistor chains are digitized by a 4 channel ADC. However instead of the Anger method, time over threshold (ToT) was used. Figure 1 shows the readout concept of the SiPM matrix. In order to validate the new method and optimize the front-end electronics of the detector, the analogue signals were digitized before the comparators using a CAEN DT5740 32 channel digitizer, then the

An FPGA based backup version of the TileCal digitizer

International Nuclear Information System (INIS)

Eriksson, D; Muschter, S; Bohm, C

2010-01-01

The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

An FPGA based backup version of the TileCal digitizer.

Science.gov (United States)

Eriksson, D.; Muschter, S.; Bohm, C.

2010-11-01

The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

Commercial FPGA based multipurpose controller: implementation perspective

International Nuclear Information System (INIS)

Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

2012-01-01

This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

International Nuclear Information System (INIS)

Anvar, Shebli; Château, Frédéric; Le Provost, Hervé; Louis, Frédéric; Manolopoulos, Konstantinos; Moudden, Yassir; Vallage, Bertrand; Zonca, Eric

2014-01-01

A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described

FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

Directory of Open Access Journals (Sweden)

B. Lakshmi

2010-09-01

Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

Entwicklung, Implementierung and Test eines FPGA-Designs für die Level-1-Frontend-Elektronik des Äusseren Spurkammersystems im LHCb-Detektor

CERN Document Server

Nedos, Mirco

For measurements of CP-violation in the B-meson system, as well as the search for new physics, the LHCb-experiment has been built at the Large Hadron Collider at CERN. One component of the sophisticated LHCb-detector is the Outer Tracker. Its measured data is transmitted serially via optical links into the readout network. For the interface between the frontend electronics on the detector and the data acquisition network a common readout board is used. This FPGA-based board, dubbed the TELL1, preprocesses the data. In this thesis the developments of the detector specific parts of the TELL1 firmware and the integration of the TELL1 board into the readout chain of the Outer Tracker are described. It covers the synchronisation and the error detection of the data received, as well as the generation of the Outer Tracker DAQ data format. In addition a zero-suppression algorithm has been implemented in the FPGA in order to reduce the network payload and guarantee operation at maximum trigger rate.

An FPGA-Based Electronic Cochlea

Directory of Open Access Journals (Sweden)

M. P. Leong

2003-06-01

Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

Development of an FPGA-based controller for safety critical application

International Nuclear Information System (INIS)

Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

2011-01-01

In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

A software radio platform based on ARM and FPGA

Directory of Open Access Journals (Sweden)

Yang Xin.

2016-01-01

Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

A FPGA-based architecture for real-time image matching

Science.gov (United States)

Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

2013-10-01

Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

Long-distance configuration of FPGA based on serial communication

International Nuclear Information System (INIS)

Liu Xiang; Song Kezhu; Zhang Sifeng

2010-01-01

To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

FPGA based Smart Wireless MIMO Control System

International Nuclear Information System (INIS)

Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

2013-01-01

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

FPGA-based trigger system for the Fermilab SeaQuest experimentz

Energy Technology Data Exchange (ETDEWEB)

Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

2015-12-01

The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ{sup +} and μ{sup −} produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

FPGA based VME boards for Indus-2 timing control system

International Nuclear Information System (INIS)

Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

2009-01-01

FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

Energy Technology Data Exchange (ETDEWEB)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

2011-08-15

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

ALICE common read-out receiver card status and HLT implementation

Energy Technology Data Exchange (ETDEWEB)

Engel, Heiko; Kebschull, Udo [IRI, Goethe-Universitaet Frankfurt am Main (Germany); Collaboration: ALICE-Collaboration

2015-07-01

The ALICE Common Read-Out Receiver Card (C-RORC) is an FPGA based PCIe read out board with optical interfaces primarily developed to replace the previous ALICE High-Level Trigger (HLT) and Data Acquisition (DAQ) Read-Out Receiver Cards from Run1 with a state of the art hardware platform to cope with the increased link rates and event data volume of Run2. The large scale production of the C-RORCs for Run2 has been completed in cooperation with ATLAS and the boards are installed in the productive clusters of ALICE HLT, ALICE DAQ and ATLAS TDAQ ROS. This contribution describes the hardware and firmware of the C-RORC in the ALICE HLT application and its online processing capabilities. Additionally, a high level dataflow description approach to implement hardware processing steps more efficiently is presented.

Embedded system in FPGA-based LLRF controller for FLASH

Science.gov (United States)

Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

2006-10-01

FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

Investigation of a Huffman-based compression algorithm for the ALICE TPC read-out in LHC Run 3

Energy Technology Data Exchange (ETDEWEB)

Klewin, Sebastian [Physikalisches Institut, University of Heidelberg (Germany); Collaboration: ALICE-Collaboration

2016-07-01

Within the scope of the ALICE upgrade towards the Run 3 of the Large Hadron Collider at CERN, starting in 2020, the ALICE Time Projection Chamber (TPC) will be reworked in order to allow for a continuous read-out. This rework includes not only a replacement of the current read-out chambers with Gas Electron Multiplier (GEM) technology, but also new front-end electronics. To be able to read out the whole data stream without loosing information, in particular without zero-suppression, a lossless compression algorithm, the Huffman encoding, was investigated and adapted to the needs of the TPC. In this talk, an algorithm, adapted for an FPGA implementation, is presented. We show its capability to reduce the data volume to less than 40% of its original size.

Spatial and color clustering on an FPGA-based computer system

Science.gov (United States)

Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

1998-10-01

We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

Directory of Open Access Journals (Sweden)

Bhattacharyya Shuvra S

2003-01-01

Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

R&D Studies of the ATLAS LAr Calorimeter Readout Electronics for super-LHC

CERN Document Server

Chen, H

2010-01-01

The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors, total about 180,000 signals are digitized and processed real-time on detector, to provide energy and time deposited in each detector element at every occurrence of the L1-trigger. A luminosity upgrade (x10) of the LHC will occur ~2017, the current readout electronics will have to be upgraded to sustain the higher radiation levels. A completely innovative readout scheme is being developed. The front-end readout will send out data continuously at each bunch crossing through high speed radiation resistant optical links, the data will be processed real-time with the possibility of implementing trigger algorithms. This article is an overview of the R&D activities and architectural studies the ATLAS LAr collaboration is developing: front-end analog and mixed-signal ASIC design, radiation resistance optical-links in SOS, high-speed back-end processing units based on FPGA architectures and power supply d...

A natural-color mapping for single-band night-time image based on FPGA

Science.gov (United States)

Wang, Yilun; Qian, Yunsheng

2018-01-01

A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

Controlling and Monitoring the Data Flow of the LHCb Read-out and DAQ Network

CERN Multimedia

Schwemmer, R; Neufeld, N; Svantesson, D

2011-01-01

The LHCb readout uses a set of 320 FPGA based boards as interface between the on-detector hardware and the GBE DAQ network. The boards are the logical Level 1 (L1) read-out electronics and aggregate the experiment's raw data into event fragments that are sent to the DAQ network. To control the many parameters of the read-out boards, an embedded PC is included on each board, connecting to the boards ICs and FPGAs. The data from the L1 boards is sent through an aggregation network into the High Level Trigger farm. The farm comprises approximately 1500 PCs which at first assemble the fragments from the L1 boards and then do a partial reconstruction and selection of the events. In total there are approximately 3500 network connections. Data is pushed through the network and there is no mechanism for resending packets. Loss of data on a small scale is acceptable but care has to be taken to avoid data loss if possible. To monitor and debug losses, different probes are inserted throughout the entire read-out chain t...

Design for an IO block array in a tile-based FPGA

International Nuclear Information System (INIS)

Ding Guangxin; Chen Lingdou; Liu Zhongli

2009-01-01

A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

Energy Technology Data Exchange (ETDEWEB)

Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

2015-07-01

A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

Energy Technology Data Exchange (ETDEWEB)

Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

2006-11-15

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

Application-specific mesh-based heterogeneous FPGA architectures

CERN Document Server

Parvez, Husain

2011-01-01

This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

Diversity for security: case assessment for FPGA-based safety-critical systems

Directory of Open Access Journals (Sweden)

Kharchenko Vyacheslav

2016-01-01

Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

DRM2: the readout board for the ALICE TOF upgrade

CERN Document Server

Falchieri, Davide

2018-01-01

For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low-jitter clock. Compared to the old board, the DRM2 is able to cope with faster trigger rates and provides a larger data bandwidth towards the DAQ. The results of the measurements on the received clock jitter and data transmission performances in a full crate are given.

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

NARCIS (Netherlands)

Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

2014-01-01

In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

CERN Document Server

Fiergolski, Adrian

2017-01-01

The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

Directory of Open Access Journals (Sweden)

Tomyslav Sledevič

2013-05-01

Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

International Nuclear Information System (INIS)

Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

2016-01-01

Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

On the speed of response of an FPGA-based shutdown system in CANDU nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

She Jingke, E-mail: jshe2@uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada); Jiang Jin, E-mail: jjiang@eng.uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada)

2011-06-15

Highlights: > Design and implementation of an FPGA-based CANDU SDS1. > Hardware-in-the-loop simulation for performance evaluation involved with an NPP simulator. > Comparison of the response time between FPGA-based trip channel and software-based PLC. - Abstract: Several issues in an FPGA based implementation of shutdown systems in CANDU nuclear power plants have been investigated in this paper. A particular attention is on the response time of an FPGA implementation of safety shutdown systems in comparison with operating system based software solutions as in existing CANDU plants. The trip decision logic under 'steam generator (SG) level low' condition has been examined in detail. The design and implementation of this logic on an FPGA platform have been carried out. The functionality tests are performed in a hardware-in-the-loop (HIL) environment by connecting the FPGA based system to an NPP simulator, and replacing one channel of Shutdown System Number 1 (SDS1) in the simulator by the FPGA implementation. The response time of the designed system is also measured through multiple tests under different conditions, and statistical data analysis has been performed. The results of the response time tests are compared against those of a software-based implementation of the same trip logic.

An FPGA-based track finder for the L1 trigger of the CMS experiment at the HL-LHC

CERN Document Server

Cieri, Davide; Harder, Kristian; Manolopoulos, Konstantinos; Shepherd-Themistocleous, Claire; Tomalin, Ian; Aggleton, Robin; Ball, Fionn; Brooke, Jim; Clement, Emyr; Newbold, Dave; Paramesvaran, Sudarshan; Hobson, Peter; Morton, Alexander Davide; Reid, Ivan; Hall, Geoff; Iles, Gregory; James, Thomas Owen; Matsushita, Takashi; Pesaresi, Mark; Rose, Andrew William; Shtipliyski, Antoni; Summers, Sioni; Tapper, Alex; Uchida, Kirika; Vichoudis, Paschalis; Ardila-Perez, Luis; Balzer, Matthias; Caselle, Michele; Sander, Oliver; Schuh, Thomas; Weber, Marc

2017-01-01

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial component of this upgrade will be the ability to reconstruct within a few microseconds all charged particle tracks with transverse momentum above 3 GeV, so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform followed by a track fitting based on the linear regression technique. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying latency constraints. T...

Photoelectric radar servo control system based on ARM+FPGA

Science.gov (United States)

Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

2016-01-01

In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

Development, verification and validation of an FPGA-based core heat removal protection system for a PWR

Energy Technology Data Exchange (ETDEWEB)

Wu, Yichun, E-mail: ycwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China); Shui, Xuanxuan, E-mail: 807001564@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Cai, Yuanfeng, E-mail: 1056303902@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Zhou, Junyi, E-mail: 1032133755@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Wu, Zhiqiang, E-mail: npic_wu@126.com [State Key Laboratory of Reactor System Design Technology, Nuclear Power Institute of China, Chengdu 610041 (China); Zheng, Jianxiang, E-mail: zwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China)

2016-05-15

Highlights: • An example on life cycle development process and V&V on FPGA-based I&C is presented. • Software standards and guidelines are used in FPGA-based NPP I&C system logic V&V. • Diversified FPGA design and verification languages and tools are utilized. • An NPP operation principle simulator is used to simulate operation scenarios. - Abstract: To reach high confidence and ensure reliability of nuclear FPGA-based safety system, life cycle processes of discipline specification and implementation of design as well as regulations verification and validation (V&V) are needed. A specific example on how to conduct life cycle development process and V&V on FPGA-based core heat removal (CHR) protection system for CPR1000 pressure water reactor (PWR) is presented in this paper. Using the existing standards and guidelines for life cycle development and V&V, a simplified FPGA-based CHR protection system for PWR has been designed, implemented, verified and validated. Diversified verification and simulation languages and tools are used by the independent design team and the V&V team. In the system acceptance testing V&V phase, a CPR1000 NPP operation principle simulator (OPS) model is utilized to simulate normal and abnormal operation scenarios, and provide input data to the under-test FPGA-based CHR protection system and a verified C code CHR function module. The evaluation results are applied to validate the under-test FPGA-based CHR protection system. The OPS model operation outputs also provide reasonable references for the tests. Using an OPS model in the system acceptance testing V&V is cost-effective and high-efficient. A dedicated OPS, as a commercial-off-the-shelf (COTS) item, would contribute as an important tool in the V&V process of NPP I&C systems, including FPGA-based and microprocessor-based systems.

Realise of PWM-generating based on FPGA

International Nuclear Information System (INIS)

Su Rongfeng; Xu Ruinian; Huang Maomao

2012-01-01

The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Directory of Open Access Journals (Sweden)

Swapnil Mhaske

2017-01-01

Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

Controlling and Monitoring the Data Flow of the LHCb Read-out and DAQ Network

CERN Document Server

Schwemmer, Rainer; Neufeld, N; Svantesson, D

2011-01-01

The LHCb read-out uses a set of 320 FPGA based boards as interface between the on-detector hardware and the GBE DAQ network. The boards are the logical Level 1 (L1) read-out electronics and aggregate the experiment’s raw data into event fragments that are sent to the DAQ network. To control the many parameters of the read-out boards, an embedded PC is included on each board, connecting to the boards ICs and FPGAs. The data from the L1 boards is sent through an aggregation network into the High Level Trigger farm. The farm comprises approximately 1500 PCs which at first assemble the fragments from the L1 boards and then do a partial reconstruction and selection of the events. In total there are approximately 3500 network connections. Data is pushed through the network and there is no mechanism for resending packets. Loss of data on a small scale is acceptable but care has to be taken to avoid data loss if possible. To monitor and debug losses, different probes are inserted throughout the entire read-out cha...

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

International Nuclear Information System (INIS)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

2010-10-01

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

FPGA Compute Acceleration for High-Throughput Data Processing in High-Energy Physics Experiments

CERN Multimedia

CERN. Geneva

2017-01-01

The upgrades of the four large experiments of the LHC at CERN in the coming years will result in a huge increase of data bandwidth for each experiment which needs to be processed very efficiently. For example the LHCb experiment will upgrade its detector 2019/2020 to a 'triggerless' readout scheme, where all of the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40MHz. This increases the data bandwidth from the detector down to the event filter farm to 40TBit/s, which must be processed to select the interesting proton-proton collisions for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered.    In the high performance computing sector more and more FPGA compute accelerators are being used to improve the compute performance and reduce the...

FPGA-Based Sonar Processing

National Research Council Canada - National Science Library

Graham, Paul; Nelson, Brent

1998-01-01

This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Energy Technology Data Exchange (ETDEWEB)

Cardinali, M., E-mail: cardinal@kph.uni-mainz.de [Institut für Kernphysik, Johannes Gutenberg-University Mainz, Mainz (Germany); Helmholtz Institut Mainz, Mainz (Germany); Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (Germany); Dodokhov, V.Kh. [Joint Institute for Nuclear Research, Dubna (Russian Federation); Britting, A. [Friedrich Alexander-University of Erlangen-Nuremberg, Erlangen (Germany); and others

2014-12-01

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R and D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype. - Highlights: • Frontend electronics for Cherenkov detectors have been developed. • FPGA-TDCs have been used for high precision timing. • Time over threshold has been utilised for walk correction. • Single photo-electron timing resolution less than 100 ps has been achieved.

A 40 MHz Trigger-free Readout Architecture for the LHCb Experiment

CERN Document Server

Alessio, F; Guzik, Z

2009-01-01

The LHCb experiment is considering an upgrade towards a trigger-free 40 MHz complete event readout in which the event selection will only be performed on a processing farm by a high-level software trigger with access to all detector information. This would allow operating LHCb at ten times the current design luminosity and improving the trigger efficiencies in order to collect more than ten times the statistics foreseen in the first phase. In this paper we present the new architecture in consideration. In particular, we investigate new technologies and protocols for the distribution of timing and synchronous control commands, and rate control. This so called Timing and Fast Control (TFC) system will also perform a central destination control for the events and manage the load balancing of the readout network and the event filter farm. The TFC system will be centred on a single FPGA-based multimaster allowing concurrent stand-alone operation of any subset of sub-detectors. The TFC distribution network under in...

An FPGA-based heterogeneous image fusion system design method

Science.gov (United States)

Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

2011-08-01

Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

Digital readouts for large microwave low-temperature detector arrays

International Nuclear Information System (INIS)

Mazin, Benjamin A.; Day, Peter K.; Irwin, Kent D.; Reintsema, Carl D.; Zmuidzinas, Jonas

2006-01-01

Over the last several years many different types of low-temperature detectors (LTDs) have been developed that use a microwave resonant circuit as part of their readout. These devices include microwave kinetic inductance detectors (MKID), microwave SQUID readouts for transition edge sensors (TES), and NIS bolometers. Current readout techniques for these devices use analog frequency synthesizers and IQ mixers. While these components are available as microwave integrated circuits, one set is required for each resonator. We are exploring a new readout technique for this class of detectors based on a commercial-off-the-shelf technology called software defined radio (SDR). In this method a fast digital to analog (D/A) converter creates as many tones as desired in the available bandwidth. Our prototype system employs a 100MS/s 16-bit D/A to generate an arbitrary number of tones in 50MHz of bandwidth. This signal is then mixed up to the desired detector resonant frequency (∼10GHz), sent through the detector, then mixed back down to baseband. The baseband signal is then digitized with a series of fast analog to digital converters (80MS/s, 14-bit). Next, a numerical mixer in a dedicated integrated circuit or FPGA mixes the resonant frequency of a specified detector to 0Hz, and sends the complex detector output over a computer bus for processing and storage. In this paper we will report on our results in using a prototype system to readout a MKID array, including system noise performance, X-ray pulse response, and cross-talk measurements. We will also discuss how this technique can be scaled to read out many thousands of detectors

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Science.gov (United States)

Cardinali, M.; Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M.; Dodokhov, V. Kh.; Britting, A.; Eyrich, W.; Lehmann, A.; Uhlig, F.; Düren, M.; Föhl, K.; Hayrapetyan, A.; Kröck, B.; Merle, O.; Rieke, J.; Cowie, E.; Keri, T.; Montgomery, R.; Rosner, G.; Achenbach, P.; Corell, O.; Ferretti Bondy, M. I.; Hoek, M.; Lauth, W.; Rosner, C.; Sfienti, C.; Thiel, M.; Bühler, P.; Gruber, L.; Marton, J.; Suzuki, K.

2014-12-01

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype.

Algorithmic strategies for FPGA-based vision

OpenAIRE

Lim, Yoong Kang

2016-01-01

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

An FPGA-Based People Detection System

Directory of Open Access Journals (Sweden)

James J. Clark

2005-05-01

Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

A low delay transmission method of multi-channel video based on FPGA

Science.gov (United States)

Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

2018-03-01

In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Chalimbaud Pierre

2007-01-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Pierre Chalimbaud

2006-12-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Tethered Forth system for FPGA applications

Science.gov (United States)

Goździkowski, Paweł; Zabołotny, Wojciech M.

2013-10-01

This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

Energy Technology Data Exchange (ETDEWEB)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

2010-10-15

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

CERN Document Server

AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

The upgrade of the multiwire drift chamber readout of the HADES experiment at GSI: the optical end point board

Energy Technology Data Exchange (ETDEWEB)

Tarantola, Attilio; Michel, Jan; Muentz, Christian; Stroth, Joachim [Institut fuer Kernphysik, Goethe-Universitaet, Frankfurt (Germany); GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Froehlich, Ingo; Stroebele, Herbert [Institut fuer Kernphysik, Goethe-Universitaet, Frankfurt (Germany); Kolb, Burkhard; Traxler, Michael [GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Palka, Marek [Smoluchowski Institute of Physics, Jagiellonian University, Krakow (Poland); GSI, Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Wuestenfeld, Joern [Institut fuer Strahlenphysik, Forschungszentrum, Dresden-Rossendorf (Germany)

2009-07-01

One of the goal of the HADES upgrade project is the realization of a new data acquisition scheme for the 24 Multiwire Drift Chambers (MDCs), which allows to increase the readout speed of the 40.000 TDC channels. On the existing MDC Front End Electronic (FEE) side an Optical End Point Board (OEPB) has been designed to control configuration and readout of the chamber's TDCs. The OEPB uses Plastic Optical Fibres (POF) for data transmission, which results in total electromagnetic immunity, amazing simplicity in handling and low power consumption. The employment of a Lattice ECP2/M FPGA with SERDES manages serial data transmission and its large resources allow for the storage of several events close-to-front-end. As 400 OEPBs will be located in the detector acceptance, dedicated FPGA hardware is used to detect Single Event Upsets (SEUs).

Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

DEFF Research Database (Denmark)

Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

2012-01-01

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

Fault tolerance based on serial communication of FPGA

International Nuclear Information System (INIS)

Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

2012-01-01

There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-05-23

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

FPGA-based network data transmission scheme for CSNS

International Nuclear Information System (INIS)

Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

2012-01-01

This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

A single FPGA-based portable ultrasound imaging system for point-of-care applications.

Science.gov (United States)

Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

2012-07-01

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

An FPGA-based trigger processor for a measurement of deeply virtual Compton scattering at the COMPASS-II experiment

Energy Technology Data Exchange (ETDEWEB)

Schopferer, Sebastian

2013-12-16

The COMPASS-II experiment at CERN is focusing on a measurement of the deeply virtual Compton scattering. Several upgrades of the experimental setup have been performed in 2012, namely the construction of a long liquid hydrogen target and a surrounding recoil proton detector called CAMERA. Based on a time-of-flight measurement between two barrels of scintillators, the CAMERA detector allows to detect protons with a kinetic energy down to 35 MeV, which leave the target under large polar angles. At the same time, protons can be distinguished from other particles resulting from background processes by means of an energy loss measurement in the scintillating material. In order to extend the existing COMPASS trigger scheme, a digital trigger system has been developed, which is detailed in the thesis at hand. The trigger system is able to select events with a recoil proton in the final state while suppressing background events, using the particle identification capabilities of the CAMERA detector. Challenging selection criteria based on both the time-of-flight and the energy loss measurement call for a powerful programmable logic board. At the same time, the integration into the existing COMPASS trigger system poses strict constraints on the latency of the trigger decision. For the implementation of the proton trigger system, a new FPGA-based trigger and DAQ hardware called TIGER has been built. The module is operated in two firmware configurations, serving two distinct purposes. Firstly, the trigger processor is responsible for the generation of a trigger signal based on recoil particles, which is included in the global first-level trigger decision. Secondly, a readout concentrator allows to multiplex the data streams of up to 18 readout modules into one link to the DAQ. The CAMERA detector and the corresponding readout and trigger electronics was commissioned during a test run in autumn 2012. This thesis contains details about the trigger concept, the development of the

An FPGA based track finder for the L1 trigger of the CMS experiment at the High Luminosity LHC

CERN Document Server

Tomalin, Ian; Ball, Fionn Amhairghen; Balzer, Matthias Norbert; Boudoul, Gaelle; Brooke, James John; Caselle, Michele; Calligaris, Luigi; Cieri, Davide; Clement, Emyr John; Dutta, Suchandra; Hall, Geoffrey; Harder, Kristian; Hobson, Peter; Iles, Gregory Michiel; James, Thomas Owen; Manolopoulos, Konstantinos; Matsushita, Takashi; Morton, Alexander; Newbold, David; Paramesvaran, Sudarshan; Pesaresi, Mark Franco; Pozzobon, Nicola; Reid, Ivan; Rose, A. W; Sander, Oliver; Shepherd-Themistocleous, Claire; Shtipliyski, Antoni; Schuh, Thomas; Skinnari, Louise; Summers, Sioni Paris; Tapper, Alexander; Thea, Alessandro; Uchida, Kirika; Vichoudis, Paschalis; Viret, Sebastien; Weber, M; Aggleton, Robin Cameron

2017-12-14

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2-3 GeV within 4$\\mu$s so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. ...

Exploration of Heterogeneous FPGA Architectures

Directory of Open Access Journals (Sweden)

Umer Farooq

2011-01-01

mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

Science.gov (United States)

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Readout system of TPC/MPD NICA project

Energy Technology Data Exchange (ETDEWEB)

Averyanov, A. V.; Bajajin, A. G.; Chepurnov, V. F.; Cheremukhina, G. A.; Fateev, O. V.; Korotkova, A. M.; Levchanovskiy, F. V.; Lukstins, J.; Movchan, S. A.; Razin, S. V.; Rybakov, A. A.; Vereschagin, S. V., E-mail: vereschagin@jinr.ru; Zanevsky, Yu. V.; Zaporozhets, S. A.; Zruyev, V. N. [Joint Institute for Nuclear Research (Russian Federation)

2015-12-15

The time-projection chamber (TPC) is the main tracking detector in the MPD/NICA. The information on charge-particle tracks in the TPC is registered by the MWPG with cathode pad readout. The frontend electronics (FEE) are developed with use of modern technologies such as application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), and data transfer to a concentrator via a fast optical interface. The main parameters of the FEE are as follows: total number of channels, ∼95 000; data stream from the whole TPC, 5 GB/s; low power consumption, less than 100 mW/ch; signal to noise ratio (S/N), 30; equivalent noise charge (ENC), <1000e{sup –} (C{sub in} = 10–20 pF); and zero suppression (pad signal rejection ∼90%). The article presents the status of the readout chamber construction and the data acquisition system. The results of testing FEE prototypes are presented.

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Directory of Open Access Journals (Sweden)

He Chen

2011-12-01

Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

Directory of Open Access Journals (Sweden)

Lai Chiu-Keng

2016-01-01

Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

2016-01-01

As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

Wire Position Monitoring with FPGA based Electronics

International Nuclear Information System (INIS)

Eddy, N.; Lysenko, O.

2009-01-01

This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

CERN Document Server

Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

2018-01-01

The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

FPGA design best practices for team-based reuse

CERN Document Server

Simpson, Philip Andrew

2015-01-01

This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

FPGA communications based on Gigabit Ethernet

International Nuclear Information System (INIS)

Doolittle, L.R.; Serrano, C.

2012-01-01

The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

Directory of Open Access Journals (Sweden)

Y. Hou

2016-06-01

Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

International Nuclear Information System (INIS)

Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

International Nuclear Information System (INIS)

Magazzù, G; Borgese, G; Costantino, N; Fanucci, L; Saponara, S; Incandela, J

2013-01-01

In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

Science.gov (United States)

Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

2013-02-01

In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

Development of FPGA-based digital signal processing system for radiation spectroscopy

International Nuclear Information System (INIS)

Lee, Pil Soo; Lee, Chun Sik; Lee, Ju Hahn

2013-01-01

We have developed an FPGA-based digital signal processing system that performs both online digital signal filtering and pulse-shape analysis for both particle and gamma-ray spectroscopy. Such functionalities were made possible by a state-of-the-art programmable logic device and system architectures employed. The system performance as measured, for example, in the system dead time and accuracy for pulse-height and rise-time determination, was evaluated with standard alpha- and gamma-ray sources using a CsI(Tl) scintillation detector. It is resulted that the present system has shown its potential application to various radiation-related fields such as particle identification, radiography, and radiation imaging. - Highlights: ► An FPGA-based digital processing system was developed for radiation spectroscopy. ► Our digital system has a 14-bit resolution and a 100-MHz sampling rate. ► The FPGA implements the online digital filtering and pulse-shape analysis. ► The pileup rejection is implemented in trigger logic before digital filtering process. ► Our digital system was verified in alpha-gamma measurements using a CsI detector

Motion camera based on a custom vision sensor and an FPGA architecture

Science.gov (United States)

Arias-Estrada, Miguel

1998-09-01

A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

The implementing of high resolution time measuring circuit based on FPGA

International Nuclear Information System (INIS)

Zhang Ji; Zeng Yun; Wang Zheng; Li Quiju; Lu Jifang; Wu Jinyuan

2011-01-01

It presents the implementing of TDC based on FPGA. The fine timing function part is accomplished through the time interpolators that are composed of the carry chain of intrinsic adders in FPGA. This architecture dates back to the latest technology-WUTDC (Wave Union TDC) that is developed to sub-divide the ultra-wide bins and improve the measure resolution. The board and the online test have been proved that the linearity of converters is satisfying and the time resolution is better than 40 ps. (authors)

LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

Science.gov (United States)

Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

2007-09-01

Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

A fast embedded readout system for large-area Medipix and Timepix systems

International Nuclear Information System (INIS)

Brogna, A S; Balzer, M; Smale, S; Hartmann, J; Bormann, D; Hamann, E; Cecilia, A; Zuber, M; Koenig, T; Weber, M; Fiederle, M; Baumbach, T; Zwerger, A

2014-01-01

In this work we present a novel readout electronics for an X-ray sensor based on a Si crystal bump-bonded to an array of 3 × 2 Medipix ASICs. The pixel size is 55 μm × 55 μm with a total number of ∼ 400k pixels and a sensitive area of 42 mm × 28 mm. The readout electronics operate Medipix-2 MXR or Timepix ASICs with a clock speed of 125 MHz. The data acquisition system is centered around an FPGA and each of the six ASICs has a dedicated I/O port for simultaneous data acquisition. The settings of the auxiliary devices (ADCs and DACs) are also processed in the FPGA. Moreover, a high-resolution timer operates the electronic shutter to select the exposure time from 8 ns to several milliseconds. A sophisticated trigger is available in hardware and software to synchronize the acquisition with external electro-mechanical motors. The system includes a diagnostic subsystem to check the sensor temperature and to control the cooling Peltier cells and a programmable high-voltage generator to bias the crystal. A network cable transfers the data, encapsulated into the UDP protocol and streamed at 1 Gb/s. Therefore most notebooks or personal computers are able to process the data and to program the system without a dedicated interface. The data readout software is compatible with the well-known Pixelman 2.x running both on Windows and GNU/Linux. Furthermore the open architecture encourages users to write their own applications. With a low-level interface library which implements all the basic features, a MATLAB or Python script can be implemented for special manipulations of the raw data. In this paper we present selected images taken with a microfocus X-ray tube to demonstrate the capability to collect the data at rates up to 120 fps corresponding to 0.76 Gb/s

FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

International Nuclear Information System (INIS)

Shanjie, Xiao; Tatjana, Jevremovic

2010-01-01

The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

Note: Design of FPGA based system identification module with application to atomic force microscopy

Science.gov (United States)

Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

2018-05-01

The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

International Nuclear Information System (INIS)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah; Choi, Jong Gyun

2014-01-01

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

Energy Technology Data Exchange (ETDEWEB)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

2014-08-15

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

Development of readout system for FE-I4 pixel module using SiTCP

Energy Technology Data Exchange (ETDEWEB)

Teoh, J.J., E-mail: jjteoh@champ.hep.sci.osaka-u.ac.jp [Graduate School of Science, Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka, 560-0043 (Japan); Hanagaki, K. [Graduate School of Science, Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka, 560-0043 (Japan); Ikegami, Y.; Takubo, Y.; Terada, S.; Unno, Y. [Institute for Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba City, Ibaraki-ken 305-0801 (Japan)

2013-12-11

The ATLAS pixel detector will be replaced in the future High Luminosity-Large Hadron Collider (HL-LHC) upgrade to preserve or improve the detector performance at high luminosity environment. To meet the tight requirements of the upgrade, a new pixel Front-End (FE) Integrated Circuit (IC) called FE-I4 has been developed. We have then devised a readout system for the new FE IC. Our system incorporates Silicon Transmission Control Protocol (SiTCP) technology (Uchida, 2008 [1]) which utilizes the standard TCP/IP and UDP communication protocols. This technology allows direct data access and transfer between a readout hardware chain and PC via a high speed Ethernet. In addition, the communication protocols are small enough to be implemented in a single Field-Programable Gate Array (FPGA). Relying on this technology, we have been able to construct a very compact, versatile and fast readout system. We have developed a firmware and software together with the readout hardware chain. We also have established basic functionalities for reading out FE-I4.

Intermediate Frequency Digital Receiver Based on Multi-FPGA System

Directory of Open Access Journals (Sweden)

Chengchang Zhang

2016-01-01

Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

The design and test of VME clock distribution module of the Daya Bay RPC readout system

International Nuclear Information System (INIS)

Zhao Heng; Liang Hao; Zhou Yongzhao

2011-01-01

It describes the design of the VME Clock Distribution module of the Daya Bay RPC readout system, including the function and the hardware structure of the module and the logic design of the FPGA on the module. After the building and debugging of the module, a series of tests have been made to check its function and stability. (authors)

Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

DEFF Research Database (Denmark)

Hasanuzzaman, G. K.M.; Spolitis, Sandis; Salgals, T.

2017-01-01

We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.......We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA....

An FPGA bridge preserving traffing quality of service for on-chip network-based systems

NARCIS (Netherlands)

Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

2011-01-01

FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

FPGA Design Methodologies Applicable to Nuclear Power Plants

International Nuclear Information System (INIS)

Kwong, Yongil; Jeong, Choongheui

2013-01-01

In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

A FPGA-based signal processing unit for a GEM array detector

International Nuclear Information System (INIS)

Yen, W.W.; Chou, H.P.

2013-06-01

in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

Protection and Control with FPGA technology

Energy Technology Data Exchange (ETDEWEB)

Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-03-15

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

Protection and Control with FPGA technology

International Nuclear Information System (INIS)

Sohn, K. Y.; Yi, W. J.; Koo, I. S.

2012-01-01

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

Development of telescope readout system based on FELIX for testbeam experiments

CERN Document Server

Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

2017-01-01

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

FPGA-Based Embedded Motion Estimation Sensor

Directory of Open Access Journals (Sweden)

Zhaoyi Wei

2008-01-01

Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

FPGA based algorithms for data reduction at Belle II

Energy Technology Data Exchange (ETDEWEB)

Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

2011-07-01

Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

Fpga based L-band pulse doppler radar design and implementation

Science.gov (United States)

Savci, Kubilay

As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

ATLAS CSC Collaboration; The ATLAS collaboration

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)664042

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

Claus, Richard; The ATLAS collaboration

2015-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thro...

Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

National Research Council Canada - National Science Library

Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

2005-01-01

.... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

Controlling and monitoring the data flow of the LHCb read-out and DAQ network

International Nuclear Information System (INIS)

Schwemmer, R.; Gaspar, C.; Neufeld, N.; Svantesson, D.

2012-01-01

The LHCb read-out uses a set of 320 FPGA based boards as interface between the on-detector hardware and the GBE DAQ network. The boards are the logical Level 1 (L1) read-out electronics and aggregate the experiment's raw data into event fragments that are sent to the DAQ network. To control the many parameters of the read-out boards, an embedded PC is included on each board, connecting to the boards ICs and FPGAs. The data from the L1 boards is sent through an aggregation network into the High Level Trigger farm. The farm comprises approximately 1500 PCs which at first assemble the fragments from the L1 boards and then do a partial reconstruction and selection of the events. In total there are approximately 3500 network connections. Data is pushed through the network and there is no mechanism for resending packets. Loss of data on a small scale is acceptable but care has to be taken to avoid data loss if possible. To monitor and debug losses, different probes are inserted throughout the entire read-out chain to count fragments, packets and their rates at different positions. To keep uniformity throughout the experiment, all control software was developed using the common SCADA software, PVSS, with the JCOP framework as base. The presentation will focus on the low level controls interface developed for the L1 boards and the networking probes, as well as the integration of the high level user interfaces into PVSS. (authors)

A Signature-Based Power Model for MPSoC on FPGA

Directory of Open Access Journals (Sweden)

Roberta Piscitelli

2012-01-01

Full Text Available This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

Design of optical axis jitter control system for multi beam lasers based on FPGA

Science.gov (United States)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

Science.gov (United States)

Zhu, Yuhua; Zhu, Dan; Wang, Jianing

2012-09-01

As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

Science.gov (United States)

Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

2018-02-01

Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

Embedded algorithms within an FPGA-based system to process nonlinear time series data

Science.gov (United States)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

High-definition video display based on the FPGA and THS8200

Science.gov (United States)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

An FPGA-based torus communication network

Energy Technology Data Exchange (ETDEWEB)

Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

2011-02-15

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

An FPGA-based torus communication network

International Nuclear Information System (INIS)

Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

2011-02-01

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

Energy Technology Data Exchange (ETDEWEB)

Rovati, L; Bonaiuti, M [Dipartimento di Ingegneria dell' Informazione, Universita di Modena e Reggio Emilia, Modena (Italy); Bettarini, S [Dipartimento di Fisica, Universita di Pisa and INFN Pisa, Pisa (Italy); Bosisio, L [Dipartimento di Fisica, Universita di Trieste and INFN Trieste, Trieste (Italy); Dalla Betta, G-F; Tyzhnevyi, V [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita di Trento e INFN Trento, Trento (Italy); Verzellesi, G [Dipartimento di Scienze e Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia and INFN Trento, Reggio Emilia (Italy); Zorzi, N, E-mail: giovanni.verzellesi@unimore.i [Fondazione Bruno Kessler (FBK), Trento (Italy)

2009-11-15

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

International Nuclear Information System (INIS)

Rovati, L; Bonaiuti, M; Bettarini, S; Bosisio, L; Dalla Betta, G-F; Tyzhnevyi, V; Verzellesi, G; Zorzi, N

2009-01-01

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

International Nuclear Information System (INIS)

Anderson, Harold D.; Williams, John T.

2009-01-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens

A novel FPGA-based bunch purity monitor system at the APS storage ring

International Nuclear Information System (INIS)

Norum, W.E.

2008-01-01

Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

Fast optical readout for Mu3e experiment

Energy Technology Data Exchange (ETDEWEB)

Huang, Qinhua [Institut fuer Kernphysik, Universitaet Mainz, Mainz (Germany); Collaboration: Mu3e-Collaboration

2016-07-01

Charged lepton flavour violation is highly suppressed in the Standard Model, which results in a prediction for the branching ratio of μ{sup +}→e{sup +}e{sup +}e{sup -} below O(10{sup -54}). The Mu3e experiment will search for this rare decay with a sensitivity of 10{sup -16}. An observation would be a clear sign for new physics. A high muon stopping rate of 2.10{sup 9} Hz is required so that sufficient statistics can be accumulated in about one year of data taking. The high event rate and the requirement of a full online track reconstruction demand a fast readout system which should provide a bandwidth above 1 Tbit/s. Reconfigurable devices, namely FPGAs, can easily parallelise the data processing, so it becomes possible to sort, merge, pack and route the data with low latency at high throughput. Optical fibres are the only option for the interconnection between different FPGA-based boards. The fibres also reduce the crosstalk and signal attenuation, especially over long distance links. As part of the readout system prototyping, firmware for synchronous merging of different data streams is being developed. In addition, the optical links have been tested and show a bit error rate below O(10{sup -16}) at 6.4 Gbit/s for a single fibre.

FPGA-based GEM detector signal acquisition for SXR spectroscopy system

Science.gov (United States)

Wojenski, A.; Pozniak, K. T.; Kasprowicz, G.; Kolasinski, P.; Krawczyk, R.; Zabolotny, W.; Chernyshova, M.; Czarski, T.; Malinowski, K.

2016-11-01

The presented work is related to the Gas Electron Multiplier (GEM) detector soft X-ray spectroscopy system for tokamak applications. The used GEM detector has one-dimensional, 128 channel readout structure. The channels are connected to the radiation-hard electronics with configurable analog stage and fast ADCs, supporting speeds of 125 MSPS for each channel. The digitalized data is sent directly to the FPGAs using fast serial links. The preprocessing algorithms are implemented in the FPGAs, with the data buffering made in the on-board 2Gb DDR3 memory chips. After the algorithmic stage, the data is sent to the Intel Xeon-based PC for further postprocessing using PCI-Express link Gen 2. For connection of multiple FPGAs, PCI-Express switch 8-to-1 was designed. The whole system can support up to 2048 analog channels. The scope of the work is an FPGA-based implementation of the recorder of the raw signal from GEM detector. Since the system will work in a very challenging environment (neutron radiation, intense electro-magnetic fields), the registered signals from the GEM detector can be corrupted. In the case of the very intense hot plasma radiation (e.g. laser generated plasma), the registered signals can overlap. Therefore, it is valuable to register the raw signals from the GEM detector with high number of events during soft X-ray radiation. The signal analysis will have the direct impact on the implementation of photon energy computation algorithms. As the result, the system will produce energy spectra and topological distribution of soft X-ray radiation. The advanced software was developed in order to perform complex system startup and monitoring of hardware units. Using the array of two one-dimensional GEM detectors it will be possible to perform tomographic reconstruction of plasma impurities radiation in the SXR region.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

DEFF Research Database (Denmark)

Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

2015-01-01

standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

Real-time FPGA architectures for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2000-03-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

Readout Architecture for Hybrid Pixel Readout Chips

CERN Document Server

AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

Merlin: a fast versatile readout system for Medipix3

International Nuclear Information System (INIS)

Plackett, R; Horswell, I; Gimenez, E N; Marchal, J; Omar, D; Tartoni, N

2013-01-01

This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in 'pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

Merlin: a fast versatile readout system for Medipix3

Science.gov (United States)

Plackett, R.; Horswell, I.; Gimenez, E. N.; Marchal, J.; Omar, D.; Tartoni, N.

2013-01-01

This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in `pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

Real-time distortion correction for visual inspection systems based on FPGA

Science.gov (United States)

Liang, Danhua; Zhang, Zhaoxia; Chen, Xiaodong; Yu, Daoyin

2008-03-01

Visual inspection is a kind of new technology based on the research of computer vision, which focuses on the measurement of the object's geometry and location. It can be widely used in online measurement, and other real-time measurement process. Because of the defects of the traditional visual inspection, a new visual detection mode -all-digital intelligent acquisition and transmission is presented. The image processing, including filtering, image compression, binarization, edge detection and distortion correction, can be completed in the programmable devices -FPGA. As the wide-field angle lens is adopted in the system, the output images have serious distortion. Limited by the calculating speed of computer, software can only correct the distortion of static images but not the distortion of dynamic images. To reach the real-time need, we design a distortion correction system based on FPGA. The method of hardware distortion correction is that the spatial correction data are calculated first under software circumstance, then converted into the address of hardware storage and stored in the hardware look-up table, through which data can be read out to correct gray level. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified.

A signature-based power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used

Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

Science.gov (United States)

Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

2018-02-01

In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

LSST camera readout chip ASPIC: test tools

Science.gov (United States)

Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

2012-02-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

LSST camera readout chip ASPIC: test tools

International Nuclear Information System (INIS)

Antilogus, P; Bailly, Ph; Juramy, C; Lebbolo, H; Martin, D; Jeglot, J; Moniez, M; Tocut, V; Wicek, F

2012-01-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

A novel digitization scheme with FPGA-base TDC for beam loss monitors operating at cryogenic temperature

Energy Technology Data Exchange (ETDEWEB)

Wu, Jinyuan; Warner, Arden; /Fermilab

2011-11-01

Recycling integrators are common current-to-frequency converting circuits for measurements of low current such as that produced by Fermilab's cryogenic ionization chambers. In typical digitization/readout schemes, a counter is utilized to accumulate the number of pulses generated by the recycling integrator to adequately digitize the total charge. In order to calculate current with reasonable resolution (e.g., 7-8 bits), hundreds of pulses must be accumulated which corresponds to a long sampling period, i.e., a very low sampling rate. In our new scheme, an FPGA-based Time-to-Digital Convertor (TDC) is utilized to measure the time intervals between the pulses output from the recycling integrator. Using this method, a sample point of the current can be made with good resolution (>10 bits) for each pulse. This effectively increases the sampling rates by hundreds of times for the same recycling integrator front-end electronics. This scheme provides a fast response to the beams loss and is potentially suitable for accelerator protection applications. Moreover, the method is also self-zero-suppressed, i.e., it produces more data when the beam loss is high while it produces significantly less data when the beam loss is low.

Architecture exploration of FPGA based accelerators for bioinformatics applications

CERN Document Server

Varma, B Sharat Chandra; Balakrishnan, M

2016-01-01

This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

Directory of Open Access Journals (Sweden)

Guo Yao-Hua

2014-07-01

Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

Directory of Open Access Journals (Sweden)

Peter Irgens

2017-04-01

Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

Design issues on using FPGA-based I and C systems in nuclear reactors

Energy Technology Data Exchange (ETDEWEB)

Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

2015-07-01

The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

A Full Slice Test Version of a Tentative Upgraded Readout System for TileCal

CERN Document Server

Muschter, S; The ATLAS collaboration; Bohm, C; Eriksson, D; Kavianipour, H; Oreglia, M; Tang, F

2011-01-01

The upgrade plans on the ATLAS hadronic calorimeter (TileCal) include the full readout of all data to the counting room. In order to study functional requirements of the future upgraded TileCal readout system we have assembled a minimal TDAQ slice. The aim is to implement a tentative readout chain for TileCal, starting with a newly developed 3-in-1 FE-board from University of Chicago and ending with the storage of triggered data on a PC. Later we will use PMT pulses, amplified and shaped by the 3-in-1 board, as a data source. However, for simplicity we start by using well defined calibration pulses also generated by the 3-in-1 board. The pulses are sampled by a 12 bit ADC, which is connected to an ML605 evaluation board from XILINX. These boards emulate the new on-detector electronics. The ML605 communicates via two 5Gb/s optical links with a Virtex-6 FPGA development board from HighTech Global which emulates the off-detector electronics. The off-detector board is situated in a PC and uses PCIe for readout an...

Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

CERN Document Server

Shibin, Konstantin

2016-01-01

During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom...

Adaptive Hardware Cryptography Engine Based on FPGA

International Nuclear Information System (INIS)

Afify, M.A.A.

2011-01-01

In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

A low-cost, FPGA-based servo controller with lock-in amplifier

International Nuclear Information System (INIS)

Yang, G; Barry, J F; Shuman, E S; Steinecker, M H; DeMille, D

2012-01-01

We describe the design and implementation of a low-cost, FPGA-based servo controller with an integrated waveform synthesizer and lock-in amplifier. This system has been designed with the specific application of laser frequency locking in mind but should be adaptable to a variety of other purposes as well. The system incorporates an onboard waveform synthesizer, a lock-in amplifier, two channels of proportional-integral (PI) servo control, and a ramp generator on a single FPGA chip. The system is based on an inexpensive, off-the-shelf FPGA evaluation board with a wide variety of available accessories, allowing the system to interface with standard laser controllers and detectors while minimizing the use of custom hardware and electronics. Gains, filter constants, and other relevant parameters are adjustable via onboard knobs and switches. These parameters and other information are displayed to the user via an integrated LCD, allowing full operation of the device without an accompanying computer. We demonstrate the performance of the system in a test setup, in which the frequency of a tunable external-cavity diode laser (ECDL) is locked to a resonant optical transmission peak of a Fabry-Perot cavity. In this setup, we achieve a total servo-loop bandwidth of ∼ 7 kHz and achieve locking of the ECDL to the cavity with a full-width-at-half-maximum (FWHM) linewidth of ∼ 200 kHz.

Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

2012-01-01

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

Science.gov (United States)

Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

2016-05-01

This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

A viable on-chip FPGA configuration memory scrubbing approach for CBM-ToF

Energy Technology Data Exchange (ETDEWEB)

Oancea, Andrei-Dumitru; Stuellein, Christian; Manz, Sebastian; Gebelein, Jano; Kebschull, Udo [Infrastruktur und Rechnersysteme in der Informationsverarbeitung (IRI), Goethe-Universitaet, Senckenberganlage 31, 60325 Frankfurt am Main (Germany); Collaboration: CBM-Collaboration

2015-07-01

The ToF Detector of the CBM Experiment will be equipped with FPGA-based read-out boards (ROBs). These ROBs will be operated in a radiation environment, and therefore need a mitigation mechanism against soft errors in the SRAM-based configuration memories of the FPGAs. The proposed approach combines intrinsic on-chip single upset correction with extrinsic selective frame scrubbing for multiple-bit upsets. The slow control is realized using the GBT-SCA, which is capable of handling interrupts. This enables the new approach of event-driven configuration frame correction. While conventional blind scrubbing leads to a continuous load on the control path, the selective frame scrubbing reduces this load to a minimum. For verification purposes, radiation tests with a proton beam were performed at COSY, Juelich. The occurred soft errors were classified into single and multiple- bit upsets, enabling an estimation of the rate at which extrinsic intervention is necessary.

FPGA remote update for nuclear environments

Energy Technology Data Exchange (ETDEWEB)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

2015-07-01

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Directory of Open Access Journals (Sweden)

Paolo Meloni

2012-01-01

Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

International Nuclear Information System (INIS)

Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

2012-01-01

Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

Implementation of FPGA based PID Controller for DC Motor Speed Control System

Directory of Open Access Journals (Sweden)

Savita SONOLI

2010-03-01

Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

Energy Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Kenn Toft, Jakob; Nannarelli, Alberto

2014-01-01

Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

Research on acceleration method of reactor physics based on FPGA platforms

International Nuclear Information System (INIS)

Li, C.; Yu, G.; Wang, K.

2013-01-01

The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

Design of FPGA-based radiation tolerant quench detectors for LHC

Science.gov (United States)

Steckert, J.; Skoczen, A.

2017-04-01

The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

Design of FPGA-based radiation tolerant quench detectors for LHC

International Nuclear Information System (INIS)

Steckert, J.; Skoczen, A.

2017-01-01

The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

Directory of Open Access Journals (Sweden)

Jovanović Bojan

2011-01-01

Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

FPGA design

CERN Document Server

Simpson, Philip

2010-01-01

This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

FPGA based data-flow injection module at 10 Gbit/s reading data from network exported storage and using standard protocols

International Nuclear Information System (INIS)

Lemouzy, B; Garnier, J-C; Neufeld, N

2011-01-01

The goal of the LHCb readout upgrade is to accelerate the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or similar technologies and might also need new networking protocols such as a customized, light-weight TCP or more specialized protocols. A test module is being implemented to be integrated in the existing LHCb infrastructure. It is a multiple 10-Gigabit traffic generator, driven by a Stratix IV FPGA, and flexible enough to generate LHCb's raw data packets. Traffic data are either internally generated or read from external storage via the network. We have implemented a light-weight industry standard protocol ATA over Ethernet (AoE) and we present an outlook of using a file-system on these network-exported disk-drivers.

FF-LYNX: protocol and interfaces for the control and readout of future Silicon detectors

Energy Technology Data Exchange (ETDEWEB)

Amendola, A; Bianchi, G; Fanucci, L; Saponara, S; Tongiani, C [Universita di Pisa, Dipartimento di Ingegneria dell' Informazione (DII-EIT), Via G. Caruso 16, 56122 Pisa (Italy); Castaldi, R; Minuti, M; Verdini, P G [INFN, Sezione di Pisa, Largo B. Pontecorvo 3, 56018 Pisa (Italy); Incandela, J; Magazzu, G; Rossin, R, E-mail: Guido.Magazzu@pi.infn.i [University of California at Santa Barbara (UCSB), Department of Physics, 5113 Broida Hall, CA 93106 Santa Barbara (United States)

2010-06-15

The FF-LYNX protocol provides an innovative solution for the integrated distribution of Timing, Trigger and Control signals and the data readout in future High Energy Physics experiments. Transmitter and receiver interfaces implementing the FF-LYNX protocol have been simulated with a high-level simulator and in an FPGA based emulator. The design of the interfaces in a commercial CMOS technology as radiation tolerant and low power modules is ongoing and the submission of a test circuit is foreseen in fall 2010. The key features of the protocol are described in this paper as well as its possible application for the transmission from Silicon Trackers to trigger processors with short and constant latency of data to be used for the L1 trigger generation.

A time projection chamber with GEM-based readout

Energy Technology Data Exchange (ETDEWEB)

Attié, David [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); Behnke, Ties [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); Bellerive, Alain [Carleton University, Department of Physics, 1125 Colonel By Drive, Ottawa, ON, Canada K1S 5B6 (Canada); Bezshyyko, Oleg [Taras Shevchenko National University of Kyiv, 64/13, Volodymyrska Street, City of Kyiv 01601 (Ukraine); Bhattacharya, Deb Sankar [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); now at Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); Bhattacharya, Purba [Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); now at National Institute of Science Education and Research (NISER) Bhubaneswar, P.O. Jatni, Khurda 752050, Odisha (India); Bhattacharya, Sudeb [Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); Caiazza, Stefano [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); now at Johannes Gutenberg Universität Mainz, Institut für Physik, 55099 Mainz (Germany); Colas, Paul [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); Lentdecker, Gilles De [Inter University ULB-VUB, Av. Fr. Roosevelt 50, B1050 Bruxelles (Belgium); Dehmelt, Klaus [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); now at State University of New York at Stony Brook, Department of Physics and Astronomy, Stony Brook, NY 11794-3800 (United States); Desch, Klaus [Universität Bonn, Physikalisches Institut, Nußallee 12, 53115 Bonn (Germany); and others

2017-06-01

For the International Large Detector concept at the planned International Linear Collider, the use of time projection chambers (TPC) with micro-pattern gas detector readout as the main tracking detector is investigated. In this paper, results from a prototype TPC, placed in a 1 T solenoidal field and read out with three independent Gas Electron Multiplier (GEM) based readout modules, are reported. The TPC was exposed to a 6 GeV electron beam at the DESY II synchrotron. The efficiency for reconstructing hits, the measurement of the drift velocity, the space point resolution and the control of field inhomogeneities are presented.

Random number generators for large-scale parallel Monte Carlo simulations on FPGA

Science.gov (United States)

Lin, Y.; Wang, F.; Liu, B.

2018-05-01

Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

Evolution of the ReadOut System of the ATLAS experiment

CERN Document Server

Borga, A; The ATLAS collaboration; Joos, M; Schumacher, J; Tremblet, L; Vandelli, W; Vermeulen, J; Werner, P; Wickens, F

2014-01-01

The ReadOut System (ROS) is a central and essential part of the ATLAS data-acquisition system. It receives and buffers event data accepted from all sub-detectors and first-level trigger subsystems. Event data are subsequently forwarded to the High-Level Trigger system and Event Builder via a GbE-based network. The ATLAS ROS will be completely renewed in view of the demanding conditions expected during LHC Run 2 and Run 3. The new ROS will consist of roughly 100 Linux-based 2U-high rack-mounted server PCs, each equipped with 2 PCIe I/O cards and four 10GbE interfaces. The FPGA-based PCIe I/O cards, developed by the ALICE collaboration, will be configured with ATLAS-specific firmware, called RobinNP. They will provide connectivity to about 2000 point-to-point optical links conveying the ATLAS event data. This dense configuration provides an excellent test bench for studying I/O efficiency and challenges in current COTS PC architectures with non-uniform memory and I/O access paths. In this paper the requirements...

Evolution of the ReadOut System of the ATLAS experiment

CERN Document Server

Borga, A; The ATLAS collaboration; Green, B; Kugel, A; Joos, M; Panduro Vazquez, W; Schumacher, J; Teixeira-Dias, P; Tremblet, L; Vandelli, W; Vermeulen, J; Werner, P; Wickens, F

2014-01-01

The ReadOut System (ROS) is a central and essential part of the ATLAS DAQ system. It receives and buffers data of events accepted by the first-level trigger from all subdetectors and first-level trigger subsystems. Event data are subsequently forwarded to the High-Level Trigger system and Event Builder via a 1 GbE-based network. The ATLAS ROS is completely renewed in view of the demanding conditions expected during LHC Run 2 and Run 3, to replace obsolete technologies and space constraints require it to be compact. The new ROS will consist of roughly 100 Linux-based 2U high rack mounted server PCs, each equipped with 2 PCIe I/O cards and two four 10 GbE interfaces. The FPGA-based PCIe I/O cards, developed by the ALICE collaboration, will be configured with ATLAS-specific firmware, the so-called RobinNP firmware. They will provide the connectivity to about 2000 optical point-to-point links conveying the ATLAS event data. This dense configuration provides an excellent test bench for studying I/O efficiency and ...

FPGA implementation of PCI to CAMAC interface for Embedded CAMAC Controller (ECC)

International Nuclear Information System (INIS)

Jha, K.; Behere, Anita; Ghodgaonkar, M.D.

2005-01-01

CAMAC controllers are used for control systems and nuclear physics experiments. Control applications need more number of physically distributed crates with regular scanning of all the parameters, the control being with a centralized computer. On the other hand, nuclear physics experiments need a high throughput with a large number of parameters in one or more crates. The nature of events is random hence buffering of data in LIST mode acquisition is needed. For a large number of parameters, this translates to high transfer rate. Hence it is essential that the CAMAC readout time is minimized and also the data transfer speed is improved to achieve maximum effective throughput. The ECC is designed to achieve these objectives using an embedded controller with PC architecture having PCI bus as interface for add on logic. The PCI Add-on to CAMAC interface protocol has been implemented in an AL TERA FPGA and all the functionality coded in VHDL. This paper discusses the design aspects of the FPGA implementation of the PCI to CAMAC interface. (author)

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

Directory of Open Access Journals (Sweden)

Manuel Saldaña

2012-01-01

Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

An Intelligent FPGA Based Anti-Sweating System for Bed Sore Prevention in a Clinical Environment

Directory of Open Access Journals (Sweden)

K. S. Jaichandar

2011-01-01

Full Text Available Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient’s skin to bed surface. Based on the temperature change, the FPGA chip select the - mode (heater/cooler and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient’s skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

Computer vision camera with embedded FPGA processing

Science.gov (United States)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Evaluation of a feature extraction framework for FPGA firmware generation during a beam-test at CERN-SPS for the CBM-TRD experiment

Energy Technology Data Exchange (ETDEWEB)

Garcia Chavez, Cruz de Jesus; Munoz Castillo, Carlos Enrique; Kebschull, Udo [Infrastructure and Computer Systems in Data Processing (IRI), Goethe University, Frankfurt am Main (Germany); Collaboration: CBM-Collaboration

2016-07-01

A feature extraction framework has been developed to allow easy FPGA firmware generation for specific feature extraction algorithms in order to find and extract regions of interest within time-based signals. This framework allows the instantiation of multiple well-known feature extraction algorithms such as center of gravity, time over threshold and cluster finder, just to mention a few of them. A graphical user interface has also been built on top of the framework to provide a user-friendly way to visualize the data-flow architecture across processing stages. The FPGA platform constraints are automatically set up by the framework itself. This feature reduces the need of low-level hardware configuration knowledge that would normally be provided by the user, centering the attention in setting up the processing algorithms for the given task more than in writing hardware description code. During November 2015, a beam-test was performed at the CERN-SPS hall. The presented framework was used to generate a firmware for the SysCore3 FPGA development board used to readout two TRD detectors by means of the SPADIC 1.0 front-end chip. The framework architecture, design methodology, as well as the achieved results during the mentioned beam-test are presented.

Intensity-based readout of resonant-waveguide grating biosensors: Systems and nanostructures

Science.gov (United States)

Paulsen, Moritz; Jahns, Sabrina; Gerken, Martina

2017-09-01

Resonant waveguide gratings (RWG) - also called photonic crystal slabs (PCS) - have been established as reliable optical transducers for label-free biochemical assays as well as for cell-based assays. Current readout systems are based on mechanical scanning and spectrometric measurements with system sizes suitable for laboratory equipment. Here, we review recent progress in compact intensity-based readout systems for point-of-care (POC) applications. We briefly introduce PCSs as sensitive optical transducers and introduce different approaches for intensity-based readout systems. Photometric measurements have been realized with a simple combination of a light source and a photodetector. Recently a 96-channel, intensity-based readout system for both biochemical interaction analyses as well as cellular assays was presented employing the intensity change of a near cut-off mode. As an alternative for multiparametric detection, a camera system for imaging detection has been implemented. A portable, camera-based system of size 13 cm × 4.9 cm × 3.5 cm with six detection areas on an RWG surface area of 11 mm × 7 mm has been demonstrated for the parallel detection of six protein binding kinetics. The signal-to-noise ratio of this system corresponds to a limit of detection of 168 M (24 ng/ml). To further improve the signal-to-noise ratio advanced nanostructure designs are investigated for RWGs. Here, results on multiperiodic and deterministic aperiodic nanostructures are presented. These advanced nanostructures allow for the design of the number and wavelengths of the RWG resonances. In the context of intensity-based readout systems they are particularly interesting for the realization of multi-LED systems. These recent trends suggest that compact point-of-care systems employing disposable test chips with RWG functional areas may reach market in the near future.

Study on Method of Ultrasonic Gas Temperature Measure Based on FPGA

Energy Technology Data Exchange (ETDEWEB)

Wen, S H; Xu, F R [Institute of Electrical Engineering, Yanshan University, Qinhuangdao, 066004 (China)

2006-10-15

It is always a problem to measure instantaneous temperature of high-temperature and high-pressure gas. There is difficulty for the conventional method of measuring temperature to measure quickly and exactly, and the measuring precision is low, the ability of anti-jamming is bad, etc. So the article introduces a method of measuring burning gas temperature using ultrasonic based on Field-Programmable Gate Array (FPGA). The mathematic model of measuring temperature is built with the relation of velocity of ultrasonic transmitting and gas Kelvin in the ideal gas. The temperature can be figured out by measuring the difference of ultrasonic frequency {delta}f. FPGA is introduced and a high-precision data acquisition system based on digital phase-shift technology is designed. The feasibility of proposed above is confirmed more by measuring pressure of burning gas timely. Experimental result demonstrates that the error is less than 12.. and the precision is heightened to 0.8%.

FPGA Acceleration by Dynamically-Loaded Hardware Libraries

DEFF Research Database (Denmark)

Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

Moessbauer spectrometric data acquisition based on FPGA

International Nuclear Information System (INIS)

Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

2008-01-01

FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

3 ns single-shot read-out in a quantum dot-based memory structure

International Nuclear Information System (INIS)

Nowozin, T.; Bimberg, D.; Beckel, A.; Lorke, A.; Geller, M.

2014-01-01

Fast read-out of two to six charges per dot from the ground and first excited state in a quantum dot (QD)-based memory is demonstrated using a two-dimensional electron gas. Single-shot measurements on modulation-doped field-effect transistor structures with embedded InAs/GaAs QDs show read-out times as short as 3 ns. At low temperature (T = 4.2 K) this read-out time is still limited by the parasitics of the setup and the device structure. Faster read-out times and a larger read-out signal are expected for an improved setup and device structure

Development of a Timepix3 readout system based on the Merlin readout system

International Nuclear Information System (INIS)

Crevatin, G.; Carrato, S.; Horswell, I.; Omar, D.; Tartoni, N.; Cautero, G.

2015-01-01

Timepix3 chip is a new ASIC specifically designed to readout hybrid pixel detectors. The main purpose of Timepix3 is to measure the time of arrival of events. This characteristic can be exploited very effectively to develop detectors for time resolved experiments at synchrotron radiation facilities. In order to investigate how the ASIC can be applied to synchrotron experiments the Merlin readout system, developed at Diamond for the Medipix3 ASIC, has been adapted to readout the Timepix3 ASIC. The first tests of the ASIC with pulse injection and with alpha particles show that its behaviour is consistent with its nominal characteristics

Development of an FPGA-Based Motion Control IC for Caving Machine

Directory of Open Access Journals (Sweden)

Chiu-Keng Lai

2014-03-01

Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

Science.gov (United States)

Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

2015-10-01

Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

Logic synthesis for FPGA-based finite state machines

CERN Document Server

Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

2016-01-01

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

A Hardware Framework for on-Chip FPGA Acceleration

DEFF Research Database (Denmark)

Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

2016-01-01

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

Embedded active vision system based on an FPGA architecture

OpenAIRE

Chalimbaud , Pierre; Berry , François

2006-01-01

International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

FPGA programming using FX3

CERN Document Server

Calleja, Stefano

2014-01-01

An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

LHCb: FPGA based data-flow injection module at 10 Gbit/s reading data from network exported storage and using standard protocols

CERN Multimedia

Lemouzy, B; Garnier, J-C

2010-01-01

The goal of the LHCb readout upgrade is to speed up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or similar technologies and might also need new networking protocols such as a customized, light-weight TCP or more specialised protocols. A test module is being implemented, which integrates in the existing LHCb infrastructure. It is a multiple 10-Gigabit traffic generator, driven by a Stratix IV FPGA, which is flexibile enough to either generate LHCb's raw data packets internally or read them from external storage via the network. For reading the data we have implemented a light-weight industry standard protocol ATA over Ethernet (AoE) and we present an outlook of using a filesystem on these network-exported disk-drivers.

Design and development of FPGA based TCP/IP module for real time computers in nuclear power plants

International Nuclear Information System (INIS)

Balasri, G. Janani; Santhana Raj, A.; Gour, Aditya; Murali, N.; Manikandan, J.

2013-01-01

An VME (Virtual Module Europa) bus based Real Time Computer's (RTC's) are being developed for Prototype Fast Breeder Reactor (PFBR) which is in an advanced stage of construction at Kalpakkam, where the RTC's have to communicate to the central process computer on the data collected from the field instrument and receive data from the central process computer. A Distributed Digital Control System (DDSC) architecture has been designed for this communication which is based on Transfer Communication Protocol/Internet Protocol (TCP/IP) over Ethernet. Currently the RTC's uses 'Wiznet Module', a bought out chip which implements the TCP/IP stack in hardware. This project concentrates on the design and development of Field Programmable Gate Array (FPGA) based TCP/IP module that runs on Microblaze, a 32-bit softcore processor, to take care of the communication as that of Wiznet module. Advantage of switching over to FPGA based system are its reconfigurability, desired number of sockets, and the design is stable even if the FPGA's get obsolete. (author)

An Improved Rotary Interpolation Based on FPGA

Directory of Open Access Journals (Sweden)

Mingyu Gao

2014-08-01

Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

FPGA-based digital convolution for wireless applications

CERN Document Server

Guan, Lei

2017-01-01

This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

Carry-chain propagation delay impacts on resolution of FPGA-based TDC

International Nuclear Information System (INIS)

Dong Lei; Yang Junfeng; Song Kezhu

2014-01-01

The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

Compression module for the BCM1F microTCA raw data readout

CERN Document Server

Dostanic, Milica

2017-01-01

BCM1F is a diamond based detector and one of the luminometers and background monitors operated by the BRIL group, part of the CMS experiment. BCM1F's front-end produces analog signals which are digitized in a new microTCA back-end. An FPGA in the back-end part takes care of signal processing and stores raw data. The raw data readout has been improved by implementing a data compression module in the firmware. This module has allowed storing larger amount of data in short time intervals. The module has been implemented in VHDL, using a zero suppression algorithm: only data above a defined threshold is stored into memory, while the samples around the base line are discarded. Thanks to metadata, describing the suppressed data, the shape of input signals and time information are preserved. Tests with simulations and a pulse generator showed good results and proved that the module can achieve large compression factor.

Readout of the UFFO Slewing Mirror Telescope to detect UV/optical photons from Gamma-Ray Bursts

International Nuclear Information System (INIS)

Kim, J E; Jung, A; Linder, E V; Na, G W; Lim, H; Nam, J W; Chen, P; Liu, T-C; Brandt, S; Budtz-Jorgensen, C; Castro-Tirado, A J; Choi, H S; Grossan, B; Huang, M A; Jeong, S; Kim, M B; Lee, J; Park, I H; Kim, S-W; Panasyuk, M I

2013-01-01

The Slewing Mirror Telescope (SMT) was proposed for rapid response to prompt UV/optical photons from Gamma-Ray Bursts (GRBs). The SMT is a key component of the Ultra-Fast Flash Observatory (UFFO)-pathfinder, which will be launched aboard the Lomonosov spacecraft at the end of 2013. The SMT utilizes a motorized mirror that slews rapidly forward to its target within a second after triggering by an X-ray coded mask camera, which makes unnecessary a reorientation of the entire spacecraft. Subsequent measurement of the UV/optical is accomplished by a 10 cm aperture Ritchey-Chrètien telescope and the focal plane detector of Intensified Charge-Coupled Device (ICCD). The ICCD is sensitive to UV/optical photons of 200–650 nm in wavelength by using a UV-enhanced S20 photocathode and amplifies photoelectrons at a gain of 10 4 –10 6 in double Micro-Channel Plates. These photons are read out by a Kodak KAI-0340 interline CCD sensor and a CCD Signal Processor with 10-bit Analog-to-Digital Converter. Various control clocks for CCD readout are implemented using a Field Programmable Gate Array (FPGA). The SMT readout is in charge of not only data acquisition, storage and transfer, but also control of the slewing mirror, the ICCD high voltage adjustments, power distribution, and system monitoring by interfacing to the UFFO-pathfinder. These functions are realized in the FPGA to minimize power consumption and to enhance processing time. The SMT readout electronics are designed and built to meet the spacecraft's constraints of power consumption, mass, and volume. The entire system is integrated with the SMT optics, as is the UFFO-pathfinder. The system has been tested and satisfies the conditions of launch and those of operation in space: those associated with shock and vibration and those associated with thermal and vacuum, respectively. In this paper, we present the SMT readout electronics: the design, construction, and performance, as well as the results of space environment

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

Science.gov (United States)

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Parallel Hough Transform-Based Straight Line Detection and Its FPGA Implementation in Embedded Vision

Directory of Open Access Journals (Sweden)

Nam Ling

2013-07-01

Full Text Available Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

Science.gov (United States)

Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

2013-07-17

Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

A new FPGA-based time-over-threshold system for the time of flight detectors at the BGO-OD experiment

Energy Technology Data Exchange (ETDEWEB)

Freyermuth, Oliver [Physikalisches Institut, Nussallee 12, D-53115 Bonn (Germany); Collaboration: BGO-OD-Collaboration

2015-07-01

The BGO-OD experiment at the ELSA accelerator facility at Bonn is built for the systematic investigation of meson photoproduction in the GeV region. It features the unique combination of a central, highly segmented BGO crystal calorimeter covering almost 4π in acceptance and a forward magnetic spectrometer complemented by time of flight walls. The readout of the ToF scintillator bars was upgraded to an FPGA-based VME-board equipped with discriminator mezzanines including per-channel remotely adjustable thresholds. A firmware was developed combining a time-over-threshold (ToT) measurement by implementing a dual-edge TDC, a configurable meantimer trigger logic including a special cosmics trigger, adjustable input delays and gateable scalers, all inside a single electronics module. An experimentally obtained relation between ToT and slope of a PMT signal can be used for a time walk correction to achieve time resolutions comparable to a classical chain of CFD and standard TDC. Additionally, the time-over-threshold information can be exploited for gain matching and allows to monitor online the gain-stability and check for electronics problems such as pulse reflections or baseline jitter. The system is well-suited for a wide range of PMT-based fast detectors with many channels and further applications foreseen.

FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

2013-05-15

In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

Optical network and FPGA/DSP based control system for free electron laser

International Nuclear Information System (INIS)

Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

2005-01-01

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

Science.gov (United States)

Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

2017-08-01

In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

Implementation of an FPGA based system survey and diagnostic reader with the aim to increase system dependability

CERN Document Server

Alsdorf, M; Kwiatkowski, M; Vigano, W; Zamantzas, C

2012-01-01

The operation and machine protection of accelerators practically rely on their underlying instrumentation systems and a failure of any of those systems could pose a significant impact on the overall reliability and availability. In order to improve the detection and in some cases the prevention of failures, a survey mechanism could be integrated to the system that collects crucial information about the current system status through a number of acquisition modules. The implementation and integration of such a method is presented with the aim to standardize the implementation, where the acquisition modules share a common build and are connected through a standardized interface to a survey reader. The reader collects regularly data and controls the readout intervals. The information collected from these modules is used locally in the FPGA device to identify critical system failures and results in an immediate failsafe reaction with the data also transmitted and stored in external databases for offline analysis.

FPGA-based architecture for motion recovering in real-time

Science.gov (United States)

Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

2002-03-01

A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

Directory of Open Access Journals (Sweden)

P. Fiala

2015-09-01

Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

FPGA-based prototype of portable environmental radiation monitor

Energy Technology Data Exchange (ETDEWEB)

Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

2015-07-01

This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

CERN Document Server

Zhu, Yu

2010-01-01

Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

High speed FPGA-based Phasemeter for the far-infrared laser interferometers on EAST

Science.gov (United States)

Yao, Y.; Liu, H.; Zou, Z.; Li, W.; Lian, H.; Jie, Y.

2017-12-01

The far-infrared laser-based HCN interferometer and POlarimeter/INTerferometer\\break (POINT) system are important diagnostics for plasma density measurement on EAST tokamak. Both HCN and POINT provide high spatial and temporal resolution of electron density measurement and used for plasma density feedback control. The density is calculated by measuring the real-time phase difference between the reference beams and the probe beams. For long-pulse operations on EAST, the calculation of density has to meet the requirements of Real-Time and high precision. In this paper, a Phasemeter for far-infrared laser-based interferometers will be introduced. The FPGA-based Phasemeter leverages fast ADCs to obtain the three-frequency signals from VDI planar-diode Mixers, and realizes digital filters and an FFT algorithm in FPGA to provide real-time, high precision electron density output. Implementation of the Phasemeter will be helpful for the future plasma real-time feedback control in long-pulse discharge.

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

Design of area array CCD image acquisition and display system based on FPGA

Science.gov (United States)

Li, Lei; Zhang, Ning; Li, Tianting; Pan, Yue; Dai, Yuming

2014-09-01

With the development of science and technology, CCD(Charge-coupled Device) has been widely applied in various fields and plays an important role in the modern sensing system, therefore researching a real-time image acquisition and display plan based on CCD device has great significance. This paper introduces an image data acquisition and display system of area array CCD based on FPGA. Several key technical challenges and problems of the system have also been analyzed and followed solutions put forward .The FPGA works as the core processing unit in the system that controls the integral time sequence .The ICX285AL area array CCD image sensor produced by SONY Corporation has been used in the system. The FPGA works to complete the driver of the area array CCD, then analog front end (AFE) processes the signal of the CCD image, including amplification, filtering, noise elimination, CDS correlation double sampling, etc. AD9945 produced by ADI Corporation to convert analog signal to digital signal. Developed Camera Link high-speed data transmission circuit, and completed the PC-end software design of the image acquisition, and realized the real-time display of images. The result through practical testing indicates that the system in the image acquisition and control is stable and reliable, and the indicators meet the actual project requirements.

FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

Directory of Open Access Journals (Sweden)

Elmar Yusifli

2017-03-01

Full Text Available With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit Hardware Description Language (VHDL implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC builder based Central Processing Unit (CPU core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC module. The IPDC is programmed in C++ and can run on a Personal Computer (PC or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

Burst-Mode Asynchronous Controllers on FPGA

Directory of Open Access Journals (Sweden)

Duarte L. Oliveira

2008-01-01

Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

FPGA fault tolerance in particle physics experiments

Energy Technology Data Exchange (ETDEWEB)

Gebelein, Jano; Engel, Heiko; Kebschull, Udo [Kirchhoff-Institute for Physics, Heidelberg University (Germany)

2010-07-01

The behavior of matter in physically extreme conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which immediately decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurance of hardware failures within the detector's electronic devices. This contribution is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as detector-control-system.

Development of Digital Signal Processing with FPGAs for the Readout of the ATLAS Liquid Argon Calorimeter at HL-LHC

CERN Document Server

Stärz, Steffen; Zuber, K

2010-01-01

The Liquid Argon calorimeter of the ATLAS detector at CERN in Geneva is supposed to be equipped with advanced readout electronics for the operation at High Luminosity LHC. In this diploma thesis the aspect of fast serial data transmission and data processing to be used for the communication between different readout modules and data storage buffers of the trigger shall be further developed. Furthermore, the main focus is put on first preparation of the detector raw data with regard to a signal correction using a FIR filter. It is aimed at a most efficient, most resource economising and minimal latency causing solution that allows to process the huge amount of upcoming detector raw data in real time. Therefore a via UDP/IP reconfigurable prototype of a 5-stage FIR filter with Gigabit Ethernet Interface was implemented in a Xilinx Virtex-5 FPGA. The performance reached is fully within the the requirements for the upgraded calorimeter readout of ATLAS.

A Fastbus-based silicon strip readout system

International Nuclear Information System (INIS)

Neoustroev, P.; Stepanov, V.; Svoiski, M.; Uvarov, L.; Matthew, P.; Russ, J.; Cooper, P.

1995-01-01

The readout system we describe here is built specifically to work with the LBL-designed SVX chip. It is typical of systems using a master sequencer module to direct the trigger and readout cycles of the sparse data source and to push data into a digitization and storage module. (orig.)

FPGA - Based Technology and Systems for I and C of Existing and Advanced Reactors

International Nuclear Information System (INIS)

Bachmach, E.; Siora, O.; Tokarev, V.; Reshetytsky, S.; Kharchenko, V.; Bezsalyi, V.

2011-01-01

Control systems of modern nuclear installations (including water-cooled, WCR) are based on programmable technologies. Most of control systems modernizations which are implemented at operating nuclear installations are also based on application of programmable technologies. Besides, a range of features and properties is defied for programmable technologies. These features and properties make licensing process more complicated, facilitate appearance of common cause failures, make safety evaluation procedures more complicated, etc. Also it is known that programmable technologies significantly extend the time periods for project realization of new power units construction and modernization of the existing power units, and also it involves rise of its value. Company RADIY has developed the Platform of digital equipment RADIY on FPGA-based technology. In the article there is a description of the features of FPGA-technology developed and applied by Company RADIY, features of the Platform RADIY and systems realized on its base, which allow to minimize significantly above-mentioned negative features and properties of programmable technologies. Technology which realized in Platform RADIY allows to solve the whole set of tasks of control (including regulation) and protection of nuclear installations. Platform RADIY is a combination of the best features of traditional programmable technologies and FPGA-technology. According to the opinion of the authors of this article the technology which is realized in Platform RADIY is the key factor for solving of control and protection tasks of nuclear installations in the nearest future. (author)

Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

Energy Technology Data Exchange (ETDEWEB)

Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

2015-07-01

The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

The characterization and application of a low resource FPGA-based time to digital converter

Energy Technology Data Exchange (ETDEWEB)

Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

2014-03-01

Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

A positron emission tomograph based on LSO-APD modules with a sampling ADC read-out system for a students' advanced laboratory course

International Nuclear Information System (INIS)

Schneider, Florian R.; Mann, Alexander B.; Technische Univ. Muenchen, Klinikum rechts der Isar; Konorov, Igor; Paul, Stephan; Delso, Gaspar; Ziegler, Sibylle I.

2012-01-01

A one-day laboratory course on positron emission tomography (PET) for the education of physics students and PhD students in medical physics has been set up. In the course, the physical background and the principles of a PET scanner are introduced. Course attendees set the system in operation, calibrate it using a 22 Na point source and reconstruct different source geometries filled with 18 F. The PET scanner features an individual channel read-out of 96 lutetium oxyorthosilicate (LSO) scintillator crystals coupled to avalanche photodiodes (APD). The analog data of each APD are digitized by fast sampling analog to digital converters (SADC) and processed within field programmable gate arrays (FPGA) to extract amplitudes and time stamps. All SADCs are continuously sampling with a precise rate of 80 MHz, which is synchronous for the whole system. The data is transmitted via USB to a Linux PC, where further processing and the image reconstruction are performed. The course attendees get an insight into detector techniques, modern read-out electronics, data acquisition and PET image reconstruction. In addition, a short introduction to some common software applications used in particle and high energy physics is part of the course. (orig.)

FPGA-based real time implementation of MPPT-controller for photovoltaic systems

Energy Technology Data Exchange (ETDEWEB)

Mellit, A.; Rezzouk, H.; Medjahed, B. [Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200 Djelfa (Algeria)

2011-05-15

In this paper an FPGA-based implementation of a real time perturb and observe (P and O) algorithm for tracking the Maximum Power Point (MPP) of a photovoltaic (PV) generator is presented. The P and O algorithm has been designed using the very high-speed description language (VHDL) and implemented on Xilinx Virtex-II-Pro(xc2v1000-4fg456) - Field Programmable Gate Array (FPGA). The algorithm and the hardware have been simulated and tested by conditioning the power produced by the PV-modules installed on the rooftop of the ''Hall of Technology Laboratory'' at Jijel University. The main advantages of the developed MPPT are low cost, good velocity, acceptable reliability, and easy implementation. However, its main disadvantage is related to the fact that for fast changes in irradiance it may fail to track the maximum power point. The efficiency of the implemented P and O controller is about 96%. (author)

Automatic generation of application specific FPGA multicore accelerators

DEFF Research Database (Denmark)

Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

2014-01-01

High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

NARCIS (Netherlands)

Hasanuzzaman, G. K.M.; Spolitis, S.; Salgals, T.; Braunfelds, J.; Morales, A.; Gonzalez, L. E.; Rommel, S.; Puerta, R.; Asensio, P.; Bobrovs, V.; Iezekiel, S.; Tafur Monroy, I.

2017-01-01

We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.

Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

DEFF Research Database (Denmark)

Singh, Ritu; Kalia, Kartik; Minver, M. H.

2016-01-01

Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

Clock and trigger distribution for ALICE using the CRU FPGA card

CERN Document Server

Imrek, Jozsef

2017-01-01

ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.

A scalable FPGA-based digitizing platform for radiation data acquisition

International Nuclear Information System (INIS)

Schiffer, Randolph T.; Flaska, Marek; Pozzi, Sara A.; Carney, Sean; Wentzloff, David D.

2011-01-01

Regulating the proliferation of nuclear materials has become an important issue in our society. In order to detect the radiation given off by nuclear materials, systems implementing detectors connected to data processing modules have been developed. We have implemented a scalable, portable detection platform with a data processing module about the size of an external DVD drive. The data processing component of our system utilizes real-time data handling and has the potential for growth and behavior modifications through custom FPGA code editing. The size of our system is dynamic, so additional input channels can be implemented if necessary. This paper presents a scalable, portable detection system capable of transmitting streaming data from its inputs to a PC or laptop. The system also performs tail/total integral pulse shape discrimination (PSD) in real time on the FPGA to filter the data and selectively transmit pulses to a PC. The data arrives at the inputs of the data capturing module, is processed in real time by the onboard FPGA and is then transferred to a PC or laptop via a PCIe cord in discrete packets. The maximum transfer rate from the FPGA to the PC is 2000 MB/s. The Detection for Nuclear Non-Proliferation Group at University of Michigan will use the detection platform to achieve pre-processing of radiation data in real time. Such pre-processing includes PSD, pulse height distributions and particle times of arrival.

Real-time particle image velocimetry based on FPGA technology;Velocimetria PIV en tiempo real basada en logica programable FPGA

Energy Technology Data Exchange (ETDEWEB)

Iriarte Munoz, Jose Miguel [Universidad Nacional de Cuyo, Instituto Balseiro, Centro Atomico Bariloche (Argentina)

2008-07-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach.;La velocimetria por imagenes de particulas (PIV), basada en plano laser, es una potente herramienta de medicion en dinamica de fluidos, capaz de medir sin grandes errores, un campo de velocidades distribuido en liquidos, gases y flujo multifase.Los altos requerimientos computacionales de los algoritmos PIV dificultan su empleo en tiempo-real.En este trabajo presentamos el diseno de una plataforma basada en tecnologia FPGA para capturar video y procesar en tiempo real el algoritmo de correlacion cruzada bidimensional.Mostramos resultados de un primer abordaje de la captura de imagenes y procesamiento de un campo fisico de velocidades en tiempo real.

FPGA Based Low Power ROM Design Using Capacitance Scaling

DEFF Research Database (Denmark)

Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

2015-01-01

An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

FPGA Implementation of Video Transmission System Based on LTE

Directory of Open Access Journals (Sweden)

Lu Yan

2015-01-01

Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

Clock Gating Based Energy Efficient and Thermal Aware Design for Vedic Equation Solver on 28nm and 40nm FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Pandey, Sujeet; Sharma, Shivani

2016-01-01

In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can e......, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA....

FPGA-based real-time simulation of power converters of renewable energy sources

Energy Technology Data Exchange (ETDEWEB)

Kokenyesi, Tamas; Varjasi, Istvan [Budapest University of Technology and Economics, Department of Automation and Applied Informatics (Hungary)], e-mail: kokenyesi.tamas@gmail.com, email: varjasi@aut.bme.hu

2011-07-01

This paper presents a hardware-in-the-loop testing (HIL) approach based on a field programmable gate array (FPGA) real-time simulation with real measured signals designed to reduce the cost and time for testing the main circuit of a power converter significantly. This method allows the control unit to measure its outputs on the same signal level in a completely transparent way, unlike other computer based simulation methods. As an example, a simulator for a three-phase inverter used for DC/AC conversion or frequency control is described and the simulated network illustrated. The calculation procedure and relative equations are also detailed, with simulation parameters and some measurement results being presented. It was found that the main advantage of this method is speed, which was only limited by the actual capabilities of the FPGA used. This method can be applied to a wide variety of analog circuits, reducing time to market. More complex circuits and higher frequencies could be simulated in the future with the evolution of FPGAs.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Science.gov (United States)

Claus, R.; ATLAS Collaboration

2016-07-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

International Nuclear Information System (INIS)

Claus, R.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Science.gov (United States)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R. T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A. J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Yildiz, S. C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

International Nuclear Information System (INIS)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R.T.; Huffer, M.; Kocian, M.; Ruckman, L.; Russell, J.; Su, D.; Wittgen, M.; Iakovidis, G.; Iordanidou, K.; Moschovakos, P.; Ntekas, K.; Kwan, K.; Lankford, A.J.; Nelson, A.; Schernau, M.; Schlenker, S.; Valderanis, C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Energy Technology Data Exchange (ETDEWEB)

Claus, R., E-mail: claus@slac.stanford.edu

2016-07-11

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

An FPGA-based reconfigurable DDC algorithm

Science.gov (United States)

Juszczyk, B.; Kasprowicz, G.

2016-09-01

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

Study on modulation amplitude stabilization method for PEM based on FPGA in atomic magnetometer

Science.gov (United States)

Wang, Qinghua; Quan, Wei; Duan, Lihong

2017-10-01

Atomic magnetometer which uses atoms as sensitive elements have ultra-high precision and has wide applications in scientific researches. The photoelastic modulation method based on photoelastic modulator (PEM) is used in the atomic magnetometer to detect the small optical rotation angle of a linearly polarized light. However, the modulation amplitude of the PEM will drift due to the environmental factors, which reduces the precision and long-term stability of the atomic magnetometer. Consequently, stabilizing the PEM's modulation amplitude is essential to precision measurement. In this paper, a modulation amplitude stabilization method for PEM based on Field Programmable Gate Array (FPGA) is proposed. The designed control system contains an optical setup and an electrical part. The optical setup is used to measure the PEM's modulation amplitude. The FPGA chip, with the PID control algorithm implemented in it, is used as the electrical part's micro controller. The closed loop control method based on the photoelastic modulation detection system can directly measure the PEM's modulation amplitude in real time, without increasing the additional optical devices. In addition, the operating speed of the modulation amplitude stabilization control system can be greatly improved because of the FPGA's parallel computing feature, and the PID control algorithm ensures flexibility to meet different needs of the PEM's modulation amplitude set values. The Modelsim simulation results show the correctness of the PID control algorithm, and the long-term stability of the PEM's modulation amplitude reaches 0.35% in a 3-hour continuous measurement.

Development of FPGA-based High Speed Serial Links for High Energy Physics Experiments

CERN Document Server

Perrella, Sabrina; Giordano, Raffaele; Izzo, Vincenzo

Ricerca Simple Search Advanced Search Ultime accessioni Browse Browse by Author Browse by Subject Browse by Year Browse by Type Browse by Accessibilità del full-text Informazioni Policy About FAQ Contatti Perrella, Sabrina (2016) Development of FPGA-based High-Speed serial links for High Energy Physics Experiments. [Tesi di dottorato] [img] Text Perrella_Sabrina_28.pdf Download (59MB) | Preview [error in script] [error in script] Item Type: Tesi di dottorato Lingua: English Title: Development of FPGA-based High-Speed serial links for High Energy Physics Experiments Creators: Creators\tEmail Perrella, Sabrina\tsa.perrella@gmail.com Date: 31 March 2016 Number of Pages: 113 Institution: Università degli Studi di Napoli Federico II Department: Fisica Scuola di dottorato: Scienze fisiche Dottorato: Fisica fondamentale ed applicata Ciclo di dottorato: 28 Coordinatore del Corso di dottorato: nome\temail Velotta, Raffaele\tvelotta@na.infn.it Tutor: nome\temail Alviggi, Mariagrazia\tUNSPECIFIED Giordano, ...

FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

Directory of Open Access Journals (Sweden)

M. Santhi

2010-03-01

Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

Science.gov (United States)

Wang, Runchun M; Thakur, Chetan S; van Schaik, André

2018-01-01

This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

Directory of Open Access Journals (Sweden)

Runchun M. Wang

2018-04-01

Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

Development of a prototype acquisition and data processing system based on FPGA

International Nuclear Information System (INIS)

Romero, L; Bellino, P

2012-01-01

We present the first stage of the expansion and improvement of a signal acquisition system based on FPGA. This system will acquire and process signals from nuclear detectors working in both pulse and current mode. The aim of this development is to unify all the actual systems for physical measurements in nuclear facilities and reactors (author)

Fpga As A Part Of Ms Windows Control Environment

Directory of Open Access Journals (Sweden)

Krzysztof Kołek

2007-01-01

Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

A positron emission tomograph based on LSO-APD modules with a sampling ADC read-out system for a students' advanced laboratory course

Energy Technology Data Exchange (ETDEWEB)

Schneider, Florian R.; Mann, Alexander B. [Technische Univ. Muenchen, Garching (Germany). Physik-Department E18; Technische Univ. Muenchen, Klinikum rechts der Isar (Germany). Nuklearmedizinische Klinik und Poliklinik; Konorov, Igor; Paul, Stephan [Technische Univ. Muenchen, Garching (Germany). Physik-Department E18; Delso, Gaspar; Ziegler, Sibylle I. [Technische Univ. Muenchen, Klinikum rechts der Isar (Germany). Nuklearmedizinische Klinik und Poliklinik

2012-07-01

A one-day laboratory course on positron emission tomography (PET) for the education of physics students and PhD students in medical physics has been set up. In the course, the physical background and the principles of a PET scanner are introduced. Course attendees set the system in operation, calibrate it using a {sup 22}Na point source and reconstruct different source geometries filled with {sup 18}F. The PET scanner features an individual channel read-out of 96 lutetium oxyorthosilicate (LSO) scintillator crystals coupled to avalanche photodiodes (APD). The analog data of each APD are digitized by fast sampling analog to digital converters (SADC) and processed within field programmable gate arrays (FPGA) to extract amplitudes and time stamps. All SADCs are continuously sampling with a precise rate of 80 MHz, which is synchronous for the whole system. The data is transmitted via USB to a Linux PC, where further processing and the image reconstruction are performed. The course attendees get an insight into detector techniques, modern read-out electronics, data acquisition and PET image reconstruction. In addition, a short introduction to some common software applications used in particle and high energy physics is part of the course. (orig.)

Development of γ dose rate monitor based on FPGA and single-chip microcomputer

International Nuclear Information System (INIS)

He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

2009-01-01

A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

A low power flash-FPGA based brain implant micro-system of PID control.

Science.gov (United States)

Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

2017-07-01

In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

Real-time particle image velocimetry based on FPGA technology

International Nuclear Information System (INIS)

Iriarte Munoz, Jose Miguel

2008-01-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

DEFF Research Database (Denmark)

Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

2016-01-01

Multiplier is used for multiplication of a signal and a constant in digital signal processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XPower Analyzer. Vedic multiplier gain speed improvements by parallelizing the generation...... Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...... efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively....

Prototype readout system for a multi Mpixels UV single-photon imaging detector capable of space flight operation

Science.gov (United States)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2018-02-01

Our collaboration works on the development of a large aperture, high resolution, UV single-photon imaging detector, funded through NASA's Strategic Astrophysics Technology (SAT) program. The detector uses a microchannel plate for charge multiplication, and orthogonal cross strip (XS) anodes for charge readout. Our target is to make an advancement in the technology readiness level (TRL), which enables real scale prototypes to be tested for future NASA missions. The baseline detector has an aperture of 50×50 mm and requires 160 low-noise charge-sensitive channels, in order to extrapolate the incoming photon position with a spatial resolution of about 20 μm FWHM. Technologies involving space flight require highly integrated electronic systems operating at very low power. We have designed two ASICs which enable the construction of such readout system. First, a charge sensitive amplifier (CSAv3) ASIC provides an equivalent noise charge (ENC) of around 600 e-, and a baseline gain of 10 mV/fC. The second, a Giga Sample per Second (GSPS) ASIC, called HalfGRAPH, is a 12-bit analog to digital converter. Its architecture is based on waveform sampling capacitor arrays and has about 8 μs of analog storage memory per channel. Both chips encapsulate 16 measurement channels. Using these chips, a small scale prototype readout system has been constructed on a FPGA Mezzanine Board (FMC), equipped with 32 measurement channels for system evaluation. We describe the construction of HalfGRAPH ASIC, detector's readout system concept and obtained results from the prototype system. As part of the space flight qualification, these chips were irradiated with a Cobalt gamma-ray source, to verify functional operation under ionizing radiation exposure.

Integrated optical readout for miniaturization of cantilever-based sensor system

DEFF Research Database (Denmark)

Nordström, Maria; Zauner, Dan; Calleja, Montserrat

2007-01-01

The authors present the fabrication and characterization of an integrated optical readout scheme based on single-mode waveguides for cantilever-based sensors. The cantilever bending is read out by monitoring changes in the optical intensity of light transmitted through the cantilever that also acts...

Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

International Nuclear Information System (INIS)

Abbas, Syed Haider; Lee, Jung-Ryul; Jang, Jae-Kyeong; Kim, Zaeill

2016-01-01

Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

Energy Technology Data Exchange (ETDEWEB)

Abbas, Syed Haider; Lee, Jung-Ryul [Department of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Jang, Jae-Kyeong [The Engineering Institute-Korea, Chonbuk National University, Jeonju (Korea, Republic of); Kim, Zaeill [The 4th R& D Institute-1st directorate, Agency for Defense Development, Daejeon (Korea, Republic of)

2016-07-15

Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

Cantilever-based sensor with integrated optical read-out using single mode waveguides

DEFF Research Database (Denmark)

Nordström, Maria; Zauner, Dan; Calleja, Montserrat

2007-01-01

This work presents the design, fabrication and mechanical characterisation of an integrated optical read-out scheme for cantilever-based biosensors. A cantilever can be used as a biosensor by monitoring its bending caused by the surface stress generated due to chemical reactions occurring on its...... surface. Here, we present a novel integrated optical read-out scheme based on single-mode waveguides that enables the fabrication of a compact system. The complete system is fabricated in the polymer SU-8. This manuscript shows the principle of operation and the design well as the fabrication...

Readout electronic for multichannel detectors

CERN Document Server

Kulibaba, V I; Naumov, S V

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

Readout electronic for multichannel detectors

International Nuclear Information System (INIS)

Kulibaba, V.I.; Maslov, N.I.; Naumov, S.V.

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc

Design and implementation of STD32-BUS based reactor protection trip unit on FPGA imbaby

International Nuclear Information System (INIS)

Mahmoud, I.; Elnokity, O.A.; Refai, M.K.

2007-01-01

This paper presents a way to design and implement the Trip Unit of a Reactor Protection System (RPS) using a Field Programmable Gate Arrays (FPGA). Instead of the traditional embedded Microprocessor based interface design method, a proposed tailor made FPGA based circuit is built to substitute the Trip Unit (TL1) existing in Egypt's 2' ' Research reactor ETRR-2. The existing embedded system is built around the STD32 field Computer Bus which used in industrial and process control applications. It is modular, rugged, reliable, and easy-to-use and is able to support a large mix of I/O cards and to easily change its configuration in the future. Therefore, the state machine of this bus is extracted from its timing diagrams and implemented in VHDL to interface the designed TU circuit. The proposed designed circuit implemented using ALTERA EPF10K10LC84-3 chip replaces the Single Board Computer which have the embedded SAY program of the TU providing the same integrated HAV and SAV functions implemented in FPGA Chip housed in an printed circuit board, which uses the same shape and specifications of STD32 boards. H/W implementation of both TU and STD32 Bus in VHDL addresses the issues of safety and reusability

Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

International Nuclear Information System (INIS)

Suetoe, J.; Hegyesi, G.

2012-01-01

Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

The FPGA realization of the general cellular automata based cryptographic hash functions: Performance and effectiveness

Directory of Open Access Journals (Sweden)

P. G. Klyucharev

2014-01-01

Full Text Available In the paper the author considers hardware implementation of the GRACE-H family general cellular automata based cryptographic hash functions. VHDL is used as a language and Altera FPGA as a platform for hardware implementation. Performance and effectiveness of the FPGA implementations of GRACE-H hash functions were compared with Keccak (SHA-3, SHA-256, BLAKE, Groestl, JH, Skein hash functions. According to the performed tests, performance of the hardware implementation of GRACE-H family hash functions significantly (up to 12 times exceeded performance of the hardware implementation of previously known hash functions, and effectiveness of that hardware implementation was also better (up to 4 times.

Implementation of T-box/T/sup -1/-box based AES design on latest xilinx fpga

International Nuclear Information System (INIS)

Kundi, D.E.; Aziz, A.

2015-01-01

This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. (author)

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

Energy Technology Data Exchange (ETDEWEB)

Hu, Wei [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Choi, Yong, E-mail: ychoi.image@gmail.com [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Hong, Key Jo [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kang, Jihoon [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Jung, Jin Ho [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Huh, Youn Suk [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Lim, Hyun Keong; Kim, Sang Su [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kim, Byung-Tae [Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Chung, Yonghyun [Department of Radiological Science, Yonsei University College of Health Science, 234 Meaji, Heungup Wonju, Kangwon-Do 220-710 (Korea, Republic of)

2012-02-01

Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm) coupled 1:1 with LYSO scintillators (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm Multiplication-Sign 20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and

Energy efficiency analysis and implementation of AES on an FPGA

Science.gov (United States)

Kenney, David

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

[Design of extracorporeal apparatus of capsule endoscopy based on ARM+FPGA].

Science.gov (United States)

Wang, Shenghua; Zhang, Sijie; Wang, Yue; Wang, Zhenxing

2011-10-01

Considering that the patients would bear the annoyance of fixed posture for long time when they are examined with gastrointestinal wireless endoscopy, even though portable devices have been developed, the treatments still depend on PC so much, we proposed an embedded solution based on ARM + FPGA. It used embedded ARM9 S3C2440 as processor core, collected images from digestive tract through capsule endoscopy which can be swallowed down there, and wirelessly transferred these images to the receiving system, then used video decoder chip SAA7114H for analog of NTSC video image decode. And under FPGA's logic controlling, effective digital video signal was transferred to S3C2440 for further treatment. Finally within the embedded Linux environment, we programmed the visual user interfaces using the QT/Embedded, realizing the offline record of the real-time video images of digestive tract portable and preferences. It can make patients move more freely and even without PC when examining. In addition, the method greatly improves the efficiency of the doctor, and is more intelligent and with more humane nature.

DNA Processing and Reassembly on General Purpose FPGA-based Development Boards

Directory of Open Access Journals (Sweden)

SZÁSZ Csaba

2017-05-01

Full Text Available The great majority of researchers involved in microelectronics generally agree that many scientific challenges in life sciences have associated with them a powerful computational requirement that must be solved before scientific progress can be made. The current trend in Deoxyribonucleic Acid (DNA computing technologies is to develop special hardware platforms capable to provide the needed processing performance at lower cost. In this endeavor the FPGA-based (Field Programmable Gate Arrays configurations aimed to accelerate genome sequencing and reassembly plays a leading role. This paper emphasizes benefits and advantages using general purpose FPGA-based development boards in DNA reassembly applications beside the special hardware architecture solutions. An original approach is unfolded which outlines the versatility of high performance ready-to-use manufacturer development platforms endowed with powerful hardware resources fully optimized for high speed processing applications. The theoretical arguments are supported via an intuitive implementation example where the designer it is discharged from any hardware development effort and completely assisted in exclusive concentration only on software design issues providing greatly reduced application development cycles. The experiments prove that such boards available on the market are suitable to fulfill in all a wide range of DNA sequencing and reassembly applications.

Prototyping Advanced Control Systems on FPGA

Directory of Open Access Journals (Sweden)

Simard Stéphane

2009-01-01

Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

A micro-TCA based data acquisition system for the Triple-GEM detectors for the upgrade of the CMS forward muon spectrometer

CERN Document Server

Lenzi, Thomas

2016-01-01

We will present the electronic and DAQ system being developed for TripleGEM detectors which will be installed in the CMS muon spectrometer. The microTCA system uses an Advanced Mezzanine Card equipped with an FPGA and the Versatile Link with the GBT chipset to link the front and back-end. On the detector an FPGA mezzanine board, the OptoHybrid, has to collect the data from the detector readout chips to transmit them optically to the microTCA boards using the GBT protocol. We will describe the hardware architecture, report on the status of the developments, and present results obtained with the system.In this contribution we will report on the progress of the design of the electronic readout and data acquisition (DAQ) system being developed for Triple-GEM detectors which will be installed in the forward region (1.5 < eta < 2.2) of the CMS muon spectrometer during the 2nd long shutdown of the LHC, planed for the period 2018-2019. The architecture of the Triple-GEM readout system is based on the use of the...

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J; Madison, Kirk W

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J.; Madison, Kirk W.

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

FPGA and optical-network-based LLRF distributed control system for TESLA-XFEL linear accelerator

Science.gov (United States)

Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Czarski, Tomasz; Giergusiewicz, Wojciech; Jalmuzna, Wojciech; Olowski, Krysztof; Perkuszewski, Karol; Zielinski, Jerzy; Simrock, Stefan

2005-02-01

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

OpenAIRE

Wang Kaiyu; Yu Zongmin; Guan Sanghai; Yang Xing; Sheng Menglin; Tang Zhenan

2016-01-01

Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA), and set up a 1:10 verification platfo...

FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

DEFF Research Database (Denmark)

Thind, Vandana; Hussain, Dil muhammed Akbar

2015-01-01

and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

A positron emission tomograph based on LSO-APD modules with a sampling ADC read-out system for a students' advanced laboratory course.

Science.gov (United States)

Schneider, Florian R; Mann, Alexander B; Konorov, Igor; Delso, Gaspar; Paul, Stephan; Ziegler, Sibylle I

2012-06-01

A one-day laboratory course on positron emission tomography (PET) for the education of physics students and PhD students in medical physics has been set up. In the course, the physical background and the principles of a PET scanner are introduced. Course attendees set the system in operation, calibrate it using a (22)Na point source and reconstruct different source geometries filled with (18)F. The PET scanner features an individual channel read-out of 96 lutetium oxyorthosilicate (LSO) scintillator crystals coupled to avalanche photodiodes (APD). The analog data of each APD are digitized by fast sampling analog to digital converters (SADC) and processed within field programmable gate arrays (FPGA) to extract amplitudes and time stamps. All SADCs are continuously sampling with a precise rate of 80MHz, which is synchronous for the whole system. The data is transmitted via USB to a Linux PC, where further processing and the image reconstruction are performed. The course attendees get an insight into detector techniques, modern read-out electronics, data acquisition and PET image reconstruction. In addition, a short introduction to some common software applications used in particle and high energy physics is part of the course. Copyright © 2011. Published by Elsevier GmbH.

Design of FPGA based high-speed data acquisition and real-time data processing system on J-TEXT tokamak

International Nuclear Information System (INIS)

Zheng, W.; Liu, R.; Zhang, M.; Zhuang, G.; Yuan, T.

2014-01-01

Highlights: • It is a data acquisition system for polarimeter–interferometer diagnostic on J-TEXT tokamak based on FPGA and PXIe devices. • The system provides a powerful data acquisition and real-time data processing performance. • Users can implement different data processing applications on the FPGA in a short time. • This system supports EPICS and has been integrated into the J-TEXT CODAC system. - Abstract: Tokamak experiment requires high-speed data acquisition and processing systems. In traditional data acquisition system, the sampling rate, channel numbers and processing speed are limited by bus throughput and CPU speed. This paper presents a data acquisition and processing system based on FPGA. The data can be processed in real-time before it is passed to the CPU. It provides processing ability for more channels with higher sampling rates than the traditional data acquisition system while ensuring deterministic real-time performance. A working prototype is developed for the newly built polarimeter–interferometer diagnostic system on the Joint Texas Experimental Tokamak (J-TEXT). It provides 16 channels with 120 MHz maximum sampling rate and 16 bit resolution. The onboard FPGA is able to calculate the plasma electron density and Faraday rotation angel. A RAID 5 storage device is adopted providing 700 MB/s read–write speed to buffer the data to the hard disk continuously for better performance

A 32-channel 840Msps TDC based on Altera Cyclone III FPGA

International Nuclear Information System (INIS)

Grigoriev, D.N.; Kasyanenko, P.V.; Kravchenko, E.A.; Shamov, A.G.; Talyshev, A.A.

2017-01-01

In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Directory of Open Access Journals (Sweden)

Y. H. Lee

2016-01-01

Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

An Update on ConSys Including a New LabVIEW FPGA Based LLRF System

DEFF Research Database (Denmark)

Worm, Torben; Nielsen, Jørgen S.

. This system use a National Instruments NI-PCIe7852R DAQ card, which includes an on-board FPGA and are hosted in a standard PC. The fast (50 kHz) amplitude loop has been implemented on the FPGA, whereas the slower tuning and phase loops are implemented in the real-time system. An operator interface including......ConSys, the Windows based control system for ASTRID and ASTRID2, is now a mature system, having been in operation for more than 15 years. All the standard programs (Console, plots, data logging, control setting store/restore etc.) are fully general and are configured through a database or file. Con......Sys is a standard publisher/subscriber system, where all nodes can act both as client and server. One very strong feature is the easy ability to make virtual devices (devices which do not depend on hardware directly, but combine hardware parameters.) For ASTRID2 a new LabVIEW based Low-Level RF system has been made...

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

Science.gov (United States)

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-12-15

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

FAS: Using FPGA to Accelerate and Secure SDN Software Switches

Directory of Open Access Journals (Sweden)

Wenwen Fu

2018-01-01

Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

Directory of Open Access Journals (Sweden)

Stamen Gadzhanov

2013-04-01

Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

Energy Technology Data Exchange (ETDEWEB)

Pozniak, K.T.; Romaniuk, R.S. [Institute of Electronic Systems, Warsaw (Poland); Kierzkowski, K. [Institute of Experimental Physics, Warsaw (Poland)

2005-07-01

The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

International Nuclear Information System (INIS)

Pozniak, K.T.; Romaniuk, R.S.; Kierzkowski, K.

2005-01-01

The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-04-20

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

DSP+FPGA-based real-time histogram equalization system of infrared image

Science.gov (United States)

Gu, Dongsheng; Yang, Nansheng; Pi, Defu; Hua, Min; Shen, Xiaoyan; Zhang, Ruolan

2001-10-01

Histogram Modification is a simple but effective method to enhance an infrared image. There are several methods to equalize an infrared image's histogram due to the different characteristics of the different infrared images, such as the traditional HE (Histogram Equalization) method, and the improved HP (Histogram Projection) and PE (Plateau Equalization) method and so on. If to realize these methods in a single system, the system must have a mass of memory and extremely fast speed. In our system, we introduce a DSP + FPGA based real-time procession technology to do these things together. FPGA is used to realize the common part of these methods while DSP is to do the different part. The choice of methods and the parameter can be input by a keyboard or a computer. By this means, the function of the system is powerful while it is easy to operate and maintain. In this article, we give out the diagram of the system and the soft flow chart of the methods. And at the end of it, we give out the infrared image and its histogram before and after the process of HE method.

FPGA-based calibration and monitoring system for the HADES electromagnetic calorimeter

Energy Technology Data Exchange (ETDEWEB)

Lai, Alessandra [University of Turin (Italy); GSI Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Collaboration: HADES-Collaboration

2015-07-01

The High Acceptance Di-Electron Spectrometer (HADES) at GSI was designed to measure dileptons and strangeness in elementary and heavy-ion collisions. An upgrade of HADES with an Electromagnetic Calorimeter (ECAL) has started and will be ready for beam in 2017. The goal is to measure π{sup 0} and η meson yields together with the dielectron data in pion and proton-induced reactions as well as in heavy ion collisions. Moreover, photon measurement is important for Λ{sup 0} (1405) and Σ{sup 0} (1385) spectroscopy. It is essential to precisely calibrate all the lead-glass crystal modules individually in order to achieve the required ECAL performances. Continuous monitoring with a light pulser system is required. It is foreseen to use blue light from an LED source, driven by short signals from a flexible pulse generator and distributed with optical fibers to each module of the ECAL. Due to their great flexibility, Field Programmable Gate Arrays (FPGA) have been chosen to implement the mentioned monitoring system. In this contribution an FPGA-based calibration system for commissioning as well as long term stability of the ECAL modules are presented.

Implementation of FPGA-Based Diverse Protection System

International Nuclear Information System (INIS)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

2015-01-01

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

Implementation of FPGA-Based Diverse Protection System

Energy Technology Data Exchange (ETDEWEB)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

2015-10-15

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

FPGA-based fully digital fast power switch fault detection and compensation for three-phase shunt active filters

Energy Technology Data Exchange (ETDEWEB)

Karimi, S.; Saadate, S. [Groupe de Recherche en Electrotechnique et Electronique de Nancy, GREEN-UHP, CNRS UMR 7037 (France); Poure, P. [Laboratoire d' Instrumentation Electronique de Nancy, LIEN, EA 3440, France Nancy Universite - Universite Henri Poincare de Nancy I, BP 239, 54506 Vandoeuvre les Nancy cedex (France)

2008-11-15

This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 {mu}s by using simultaneously a ''time criterion'' and a ''voltage criterion''. In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. ''FPGA in the loop'' prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. (author)

Uranus: a rapid prototyping tool for FPGA embedded computer vision

Science.gov (United States)

Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

2007-01-01

The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

Rapid Newcastle Disease Virus Detection Based on Loop-Mediated Isothermal Amplification and Optomagnetic Readout

DEFF Research Database (Denmark)

Tian, Bo; Ma, Jing; Zardán Gómez de la Torre, Teresa

2016-01-01

Rapid and sensitive diagnostic methods based on isothermal amplification are ideal substitutes for PCR in out-of-lab settings. However, there are bottlenecks in terms of establishing low-cost and user-friendly readout methods for isothermal amplification schemes. Combining the high amplification...... efficiency of loop-mediated isothermal amplification (LAMP) with an optomagnetic nanoparticle-based readout system, we demonstrate ultrasensitive and rapid detection of Newcastle disease virus RNA. Biotinylated amplicons of LAMP and reverse transcription LAMP (RT-LAMP) bind to streptavidin-coated magnetic...... nanoparticles (MNPs) resulting in a dramatical increase in the hydrodynamic size of the MNPs. This increase was measured by an optomagnetic readout system and provided quantitative information on the amount of LAMP target sequence. Our assay resulted in a limit of detection of 10 aM of target sequence...

Etude et modélisation du comportement du FPGA A54SX72A d’Actel en milieu radiatif et à températures contrôlées - Application a l’environnement du LHC

CERN Document Server

AUTHOR|(CDS)2080629; DEPASSE, Pierre; LAZIC, Dragoslav-Laza; CASAS-CUBILLOS, Juan; GALEZ, Christine; BOUTEMEUR, Madjid; PASSARD, Michelle

The Large Hadrons Collider (LHC) at CERN (Geneva) will provide proton-proton collisions at center of mass energy of 14 TeV. The beam bending and trajectory in the 27 km ring is maintained by superconducting dipole magnets. The dipole coils are made of Nb-Ti filaments cooled at a temperature below 1.9 K and provide a nominal field of 8.65 T. The monitoring of the cryogenic system, such as the measurement of the temperature and the pressure, is provided by a set of resistive cryogenic sensors placed inside the magnets. However, some of these sensors should be fed with currents not exceeding 1A. Therefore the output voltages are very small and the readout electronics should be placed very close to the sensors. The readout electronic cards are placed under the dipole magnets. The main digital component, embedded in the cards, is an FPGA chip. It is an integrated circuit (IC) of type FPGA A54SX72A from Actel (CMOS technology) whose purpose is signal filtering and analysis. Depending of the location along the 27...

Commissioning of FPGA-based Transverse and Longitudinal Bunch-by-Bunch Feedback System for the TLS

International Nuclear Information System (INIS)

Hu, K. H.; Kuo, C. H.; Lau, W. K.; Yeh, M. S.; Hsu, S. Y.; Chou, P. J.; Wang, M. H.; Lee, Demi; Chen, Jenny; Wang, C. J.; Hsu, K. T.; Kobayashi, K.; Nakamura, T.; Dehler, M.

2006-01-01

Multi-bunch instabilities deteriorate beam quality, increasing beam emittance, or even causing beam loss in the synchrotron light source. The feedback system is essential to suppress multi-bunch instabilities caused by the impedances of beam ducts, and trapped ions. A new FPGA based transverse and longitudinal bunch-by-bunch feedback system have been commissioned at the Taiwan Light Source recently, A single feedback loop is used to simultaneously suppress the horizontal and the vertical multi-bunch instabilities. Longitudinal instabilities caused by cavity-like structures are suppressed by the longitudinal feedback loop. The same FPGA processor is employed in the transverse feedback and the longitudinal feedback system respectively. Diagnostic memory is included in the system to capture the bunch oscillation signal, which supports various studies

High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

International Nuclear Information System (INIS)

Nieto, J.; Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M.; Vega, J.; Castro, R.

2016-01-01

Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

Energy Technology Data Exchange (ETDEWEB)

Nieto, J., E-mail: jnieto@sec.upm.es [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M. [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Vega, J.; Castro, R. [Asociación EURATOM/CIEMAT para Fusión, Madrid (Spain)

2016-11-15

Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

A low-power wave union TDC implemented in FPGA

International Nuclear Information System (INIS)

Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

2011-01-01

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

Directory of Open Access Journals (Sweden)

Burhan Khurshid

2015-05-01

Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

FPGA based hardware optimized implementation of signal processing system for LFM pulsed radar

Science.gov (United States)

Azim, Noor ul; Jun, Wang

2016-11-01

Signal processing is one of the main parts of any radar system. Different signal processing algorithms are used to extract information about different parameters like range, speed, direction etc, of a target in the field of radar communication. This paper presents LFM (Linear Frequency Modulation) pulsed radar signal processing algorithms which are used to improve target detection, range resolution and to estimate the speed of a target. Firstly, these algorithms are simulated in MATLAB to verify the concept and theory. After the conceptual verification in MATLAB, the simulation is converted into implementation on hardware using Xilinx FPGA. Chosen FPGA is Xilinx Virtex-6 (XC6LVX75T). For hardware implementation pipeline optimization is adopted and also other factors are considered for resources optimization in the process of implementation. Focusing algorithms in this work for improving target detection, range resolution and speed estimation are hardware optimized fast convolution processing based pulse compression and pulse Doppler processing.

FPGA-based implementation of sorting networks in MMC applications

DEFF Research Database (Denmark)

Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

2016-01-01

, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

A design of high resolution one-clock-cycle TDC based on FPGA

International Nuclear Information System (INIS)

Qi Ji; Deng Zhi; Liu Yinong

2011-01-01

It describes an FPGA-based high resolution TDC. Using delay chain and Wave Union methods, this TDC has a resolution of 9 ps, which is comparable to ASIC TDC. The design uses XORs and MUXs to implement a quick 1 -cycle encoder, which reduces the dead time. Self-calibration method makes the design easy to be migrated into other FPGAs. This TDC can be used in TOF experiment, medical imaging system, etc (authors)

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

International Nuclear Information System (INIS)

Messai, A.; Mellit, A.; Massi Pavan, A.; Guessoum, A.; Mekki, H.

2011-01-01

Research highlights: → FL-MPPT controller is implemented on FPGA. → Results obtained with ModelSim show a satisfactory performance. → Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

Energy Technology Data Exchange (ETDEWEB)

Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mellit, A., E-mail: a.mellit@yahoo.co.u [Department of Electronics, Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Massi Pavan, A. [Department of Materials and Natural Resources, University of Trieste, Via A. Valerio, 2 - 34127 Trieste (Italy); Guessoum, A. [Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mekki, H. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria)

2011-07-15

Research highlights: {yields} FL-MPPT controller is implemented on FPGA. {yields} Results obtained with ModelSim show a satisfactory performance. {yields} Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

Test of a PCIe based readout option for PANDA

Energy Technology Data Exchange (ETDEWEB)

Reiter, Simon; Lange, Soeren; Kuehn, Wolfgang [Justus-Liebig-Universitaet Giessen (Germany); Engel, Heiko [Goethe-Universitaet Frankfurt (Germany); Collaboration: PANDA-Collaboration

2016-07-01

The future PANDA detector will achieve an event rate at about 20 MHz resulting in a high data load of up to 200 GB/s. The data acquisition system will be based on a triggerless readout concept, leading to the requirement of large data bandwidths. The data reduction will be guaranteed on the first level by an array of FPGAs running a full on-line reconstruction followed by the second level of a CPU/GPU cluster to achieve a reduction factor more than 1000. The C-RORC (Common Readout Receiver Card), originally developed for ALICE, provides on the one hand 12 optical links with 6.25 Gbps each, and on the other hand a PCIe interface with up to 40 Gbps. The receiver card has been installed and tested, and the firmware has been adjusted for the Panda data format. Test results are presented.

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

Directory of Open Access Journals (Sweden)

Esteban Tlelo-Cuautle

Full Text Available Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL. In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

Science.gov (United States)

Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

2016-01-01

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

An FPGA-based rapid prototyping platform for wavelet coprocessors

Science.gov (United States)

Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

2007-04-01

MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

Design of the device of auto-measuring radon continuously based on FPGA

International Nuclear Information System (INIS)

Wang Yan; Shen Zhengqin; Chen Qiong

2004-01-01

This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

FPGA development board for applications in cosmic rays physics

International Nuclear Information System (INIS)

Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

2013-01-01

The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

FPGA-based RF spectrum merging and adaptive hopset selection

Science.gov (United States)

McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

FPGA-based trigger system for the LUX dark matter experiment

Science.gov (United States)

Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D.-M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O`Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

2016-05-01

LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be > 99 % efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

FPGA-based trigger system for the LUX dark matter experiment

Energy Technology Data Exchange (ETDEWEB)

Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D. -M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O׳Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

2016-05-01

LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be >99% efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

Research on the design of surface acquisition system of active lap based on FPGA and FX2LP

Science.gov (United States)

Zhao, Hongshen; Li, Xiaojin; Fan, Bin; Zeng, Zhige

2014-08-01

In order to research the dynamic surface shape changes of active lap during the processing, this paper introduces a dynamic surface shape acquisition system of active lap using FPGA and USB communication. This system consists of high-precision micro-displacement sensor array, acquisition board, PC computer composition, and acquisition circuit board includes six sub-boards based on FPGA, a hub-board based on FPGA and USB communication. A sub-board is responsible for a number of independent channel sensors' data acquisition; hub-board is responsible for creating encoder simulation tools to active lap deformation control system with location information, sending synchronization information to latch the sensor data in all of the sub-boards for a time, while addressing the sub-boards to gather the sensor data in each sub-board one by one and transmitting all the sensor data together with location information via the USB chip FX2LP to the host computer. Experimental results show that the system is capable of fixing the location and speed of active lap, meanwhile the control of surface transforming and dynamic surface data acquisition at a certain location in the processing is implemented.

FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

Directory of Open Access Journals (Sweden)

Mohammed Bahoura

2016-02-01

Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

Performance of an optical readout GEM-based TPC

International Nuclear Information System (INIS)

Margato, L.M.S.; Fraga, F.A.F.; Fetal, S.T.G.; Fraga, M.M.F.R.; Balau, E.F.S.; Blanco, A.; Marques, R. Ferreira; Policarpo, A.J.P.L

2004-01-01

We report on the operation of a GEM-based small TPC using an optical readout. The detector was operated with a mixture of Ar+CF 4 using 5.48 MeV alpha particles obtained from a 241 Am source and the GEM scintillation was concurrently read by a CCD camera and a photomultiplier. Precision collimators were used to define the track orientation. Qualitative results on the accuracy of the track angle, length and charge deposition measurements are presented

An FPGA based Node-on-Chip Architecture, for Rapid Robotics Research

DEFF Research Database (Denmark)

Falsig, Simon; Sørensen, Anders Stengaard

2010-01-01

One of the major costs and inhibitors to practical robotics research is the time invested in design, implementation, integration, adjusting and debugging of the embedded control systems, that implement the discrete event control in experimental robots and robot systems. Usually researchers can...... with the compactness and integration associated with customized hardware. In this paper we present an FPGA based architecture and a framework of template modules for modular embedded control that has: • Dramatically reduced the time we spend on instrumentation of experimental robots. • Increased the quality...

On the evaluation of the sensitivity of SRAM-Based FPGA to errors due to natural radiation environment

International Nuclear Information System (INIS)

Bocquillon, Alexandre

2009-01-01

This work aims at designing a test methodology to analyze the effect of natural radiation on FPGA SRAM-based chip-sets. Study of likely errors due to single or multiple events occurring in the configuration memory will be based on fault-injection experiments performed with laser devices. It relies on both a description of scientific background and a description of complex architecture of FPGA SRAM-Based and usual testing apparatus. Fault injection experiments with laser are conducted on several classes of components in order to perform static tests of the configuration memory and identify the links with the application. It shows the organization and sensitivity of SRAM configuration cells. Criticality criteria for configuration bits have been specified following dynamic tests in protons accelerator, in regard to their impact on the application. From this classification was developed a predicting tool for critical error rate estimation. (author) [fr

Optimized readout configuration for PIXE spectrometers based on Silicon Drift Detectors: Architecture and performance

International Nuclear Information System (INIS)

Alberti, R.; Grassi, N.; Guazzoni, C.; Klatka, T.

2009-01-01

An optimized readout configuration based on a charge preamplifier with pulsed-reset has been designed for Silicon Drift Detectors (SDDs) to be used in Particle Induced X-ray Emission (PIXE) measurements. The customized readout electronics is able to manage the large pulses originated by the protons backscattered from the target material that would otherwise cause significant degradation of X-ray spectra and marked increase in dead time. In this way, the excellent performance of SDDs can be exploited in high-quality proton-induced spectroscopy of low- and medium-energy X-rays. This paper describes the designed readout architecture and the performance characterization carried out in a PIXE setup with MeV proton beams.

The RTE inversion on FPGA aboard the solar orbiter PHI instrument

Science.gov (United States)

Cobos Carrascosa, J. P.; Aparicio del Moral, B.; Ramos Mas, J. L.; Balaguer, M.; López Jiménez, A. C.; del Toro Iniesta, J. C.

2016-07-01

In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA's Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device - Xilinx XQR4VSX55-. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.

High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

DEFF Research Database (Denmark)

Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

2017-01-01

and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

A camac based data acquisition system for flat-panel image array readout

International Nuclear Information System (INIS)

Morton, E.J.; Antonuk, L.E.; Berry, J.E.; Huang, W.; Mody, P.; Yorkston, J.; Longo, M.J.

1993-01-01

A readout system has been developed to facilitate the digitization and subsequent display of image data from two-dimensional, pixellated, flat-panel, amorphous silicon imaging arrays. These arrays have been designed specifically for medical x-ray imaging applications. The readout system is based on hardware and software developed for various experiments at CERN and Fermi National Accelerator Laboratory. Additional analog signal processing and digital control electronics were constructed specifically for this application. The authors report on the form of the resulting data acquisition system, discuss aspects of its performance, and consider the compromises which were involved in its design

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

Science.gov (United States)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

DOOCS environment for FPGA-based cavity control system and control algorithms development

International Nuclear Information System (INIS)

Pucyk, P.; Koprek, W.; Kaleta, P.; Szewinski, J.; Pozniak, K.T.; Czarski, T.; Romaniuk, R.S.

2005-01-01

The paper describes the concept and realization of the DOOCS control software for FPGAbased TESLA cavity controller and simulator (SIMCON). It bases on universal software components, created for laboratory purposes and used in MATLAB based control environment. These modules have been recently adapted to the DOOCS environment to ensure a unified software to hardware communication model. The presented solution can be also used as a general platform for control algorithms development. The proposed interfaces between MATLAB and DOOCS modules allow to check the developed algorithm in the operation environment before implementation in the FPGA. As the examples two systems have been presented. (orig.)

Embedded 3D Graphics Core for FPGA-based System-on-Chip Applications

DEFF Research Database (Denmark)

Holten-Lund, Hans Erik

2005-01-01

This paper presents a 3D graphics accelerator core for an FPGA based system, and illustrates how to build a System-on-Chip containing a Xilinx MicroBlaze soft-core CPU and our 3D graphics accelerator core. The system is capable of running uClinux and hardware accelerated 3D graphics applications......, and the video display which periodically reads from memory to display the final rendered graphics. The graphics core uses internal scratch-pad memory to reduce its external bandwidth requirement, this is achieved by implementing a tile-based rendering algorithm. Reduced external bandwidth means that the power...

Frequency multiplexing for readout of spin qubits

Energy Technology Data Exchange (ETDEWEB)

Hornibrook, J. M.; Colless, J. I.; Mahoney, A. C.; Croot, X. G.; Blanvillain, S.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, University of Sydney, Sydney, NSW 2006 (Australia); Lu, H.; Gossard, A. C. [Materials Department, University of California, Santa Barbara, California 93106 (United States)

2014-03-10

We demonstrate a low loss, chip-level frequency multiplexing scheme for readout of scaled-up spin qubit devices. By integrating separate bias tees and resonator circuits on-chip for each readout channel, we realise dispersive gate-sensing in combination with charge detection based on two radio frequency quantum point contacts. We apply this approach to perform multiplexed readout of a double quantum dot in the few-electron regime and further demonstrate operation of a 10-channel multiplexing device. Limitations for scaling spin qubit readout to large numbers of multiplexed channels are discussed.

Implementation of FPGA-based Level-1 Tracking at CMS for the HL-LHC

CERN Document Server

Chaves, Jorge Enrique

2014-01-01

A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of $5\\times10^{34} $cm$^{-2}$s$^{-1}$. This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 $\\mu$s, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilo...

Generic FPGA-Based Platform for Distributed IO in Proton Therapy Patient Safety Interlock System

Science.gov (United States)

Eichin, Michael; Carmona, Pablo Fernandez; Johansen, Ernst; Grossmann, Martin; Mayor, Alexandre; Erhardt, Daniel; Gomperts, Alexander; Regele, Harald; Bula, Christian; Sidler, Christof

2017-06-01

At the Paul Scherrer Institute (PSI) in Switzerland, cancer patients are treated with protons. Proton therapy at PSI has a long history and started in the 1980s. More than 30 years later, a new gantry has recently been installed in the existing facility. This new machine has been delivered by an industry partner. A big challenge is the integration of the vendor's safety system into the existing PSI environment. Different interface standards and the complexity of the system made it necessary to find a technical solution connecting an industry system to the existing PSI infrastructure. A novel very flexible distributed IO system based on field-programmable gate array (FPGA) technology was developed, supporting many different IO interface standards and high-speed communication links connecting the device to a PSI standard versa module eurocard-bus input output controller. This paper summarizes the features of the hardware technology, the FPGA framework with its high-speed communication link protocol, and presents our first measurement results.

Multirate Digital Filters Based on FPGA and Its Applications

International Nuclear Information System (INIS)

Sharaf El-Din, R.M.A.

2013-01-01

Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

FPGA based fast synchronous serial multi-wire links synchronization

Science.gov (United States)

Pozniak, Krzysztof T.

2013-10-01

The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

Design of a system based on DSP and FPGA for video recording and replaying

Science.gov (United States)

Kang, Yan; Wang, Heng

2013-08-01

This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA

Microcontroller based four-channel current readout unit for beam slit monitor

International Nuclear Information System (INIS)

Holikatti, A.C.; Puntambekar, T.A.; Pithawa, C.K.

2009-01-01

This paper describes the design and development of a microcontroller based four-channel current readout unit for Beam Slit Monitor (BSM) installed in Transport Line-1 of Indus Accelerator Complex. BSM is a diagnostic device consisting of two horizontal and two vertical blades, which can be moved independently in to the beam pipe to cut the beam transversely. The readout unit employs switched integrators with reset, hold and select switches and timing and control unit. It integrates the current output of the four blades of BSM and produces an output corresponding to the beam charge intercepted by the blade. The integrator outputs are then multiplexed and digitized using 12-bit ADC. Acquired digital data from ADC is stored into on-chip RAM of the microcontroller. The readout sequence is synchronized with the Microtron beam-timing signal. The timing of integration, hold and reset cycles is controlled by the microcontroller. The unit is connected on a serial link to the host computer in main control room. This unit has been integrated with the BSM system and is being used to obtain the electron beam profile. (author)

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Directory of Open Access Journals (Sweden)

Ramu Seva

2017-11-01

Full Text Available The high performance of FPGA (Field Programmable Gate Array in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

Estimation of channel impulse response and FPGA simulation

Directory of Open Access Journals (Sweden)

YU Longjie

2015-02-01

Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

SEU mitigation exploratory tests in a ITER related FPGA

International Nuclear Information System (INIS)

Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

2017-01-01

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

SEU mitigation exploratory tests in a ITER related FPGA

Energy Technology Data Exchange (ETDEWEB)

Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

2017-05-15

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

FPGA based mixed-signal circuit novel testing techniques

International Nuclear Information System (INIS)

Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

2013-01-01

Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

Science.gov (United States)

Ladbury, R. L.; Berg, M. D.; Wilcox, E. P.; LaBel, K. A.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

2013-01-01

We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

International Nuclear Information System (INIS)

An, M.; Zhang, W.; Xiao, L.; Gao, C.; Chen, C.; Huang, G.; Ji, R.; Liu, J.; Pei, H.; Sun, X.; Wang, K.; Yang, P.; Zhou, W.; Han, M.; Mei, Y.; Li, X.; Sun, Q.

2017-01-01

We present the detailed study of the digital readout of Topmetal-II - CMOS pixel direct charge sensor. Topmetal-II - is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

A minimal SATA III Host Controller based on FPGA

Science.gov (United States)

Liu, Hailiang

2018-03-01

SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

Directory of Open Access Journals (Sweden)

Wang Kaiyu

2016-01-01

Full Text Available Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA, and set up a 1:10 verification platform of smart car to verify the fuzzy garage parking system with real car. Verification results show that, the system can complete the parking task very well.

FPGA-based prototype storage system with phase change memory

Science.gov (United States)

Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

2016-10-01

With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

An FPGA-based bolometer for the MAST-U Super-X divertor

Energy Technology Data Exchange (ETDEWEB)

Lovell, Jack, E-mail: jack.lovell@durham.ac.uk [Durham University, South Road, Durham DH1 3LE (United Kingdom); Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Naylor, Graham; Field, Anthony [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Drewelow, Peter [MPI für Plasmaphysik, Greifswald (Germany); Sharples, Ray [Durham University, South Road, Durham DH1 3LE (United Kingdom); Collaboration: EUROfusion Consortium, JET, Culham Science Centre, Abingdon OX14 3DB (United Kingdom)

2016-11-15

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

Directory of Open Access Journals (Sweden)

Kyeonghwan Park

2017-04-01

Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

Performance study of large area encoding readout MRPC

Science.gov (United States)

Chen, X. L.; Wang, Y.; Chen, G.; Han, D.; Wang, X.; Zeng, M.; Zeng, Z.; Zhao, Z.; Guo, B.

2018-02-01

Muon tomography system built by the 2-D readout high spatial resolution Multi-gap Resistive Plate Chamber (MRPC) detector is a project of Tsinghua University. An encoding readout method based on the fine-fine configuration has been used to minimize the number of the readout electronic channels resulting in reducing the complexity and the cost of the system. In this paper, we provide a systematic comparison of the MRPC detector performance with and without fine-fine encoding readout. Our results suggest that the application of the fine-fine encoding readout leads us to achieve a detecting system with slightly worse spatial resolution but dramatically reduce the number of electronic channels.

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Directory of Open Access Journals (Sweden)

Hasitha Muthumala Waidyasooriya

2017-01-01

Full Text Available Finite difference time domain (FDTD method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language. As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

Energy Technology Data Exchange (ETDEWEB)

Ahmed, Ibrahim; Heo, Gyunyoung [Kyunghee Univ., Yongin (Korea, Republic of); Jung, Jaecheon [KEPCO, Ulsan (Korea, Republic of)

2016-10-15

Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks.

Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Heo, Gyunyoung; Jung, Jaecheon

2016-01-01

Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks

FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

Directory of Open Access Journals (Sweden)

Bakos Jason D

2010-04-01

Full Text Available Abstract Background Likelihood (ML-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10× speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs 1.

FPGA-based implementation of a cavity field controller for FLASH and X-FEL

Science.gov (United States)

Fafara, Przemyslaw; Jalmuzna, Wojciech; Koprek, Waldemar; Pozniak, Krzysztof; Romaniuk, Ryszard; Szewinski, Jaroslaw; Cichalewski, Wojciech

2007-08-01

The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

FPGA Implementation of Heart Rate Monitoring System.

Science.gov (United States)

Panigrahy, D; Rakshit, M; Sahu, P K

2016-03-01

This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

The current state of FPGA technology in the nuclear domain

Energy Technology Data Exchange (ETDEWEB)

Ranta, J.

2012-07-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

The current state of FPGA technology in the nuclear domain

International Nuclear Information System (INIS)

Ranta, J.

2012-01-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation

Directory of Open Access Journals (Sweden)

David L. Ndzi

2011-01-01

Full Text Available This paper describes the development of a fast adaptable FPGA-based wideband channel sounder with signal bandwidths of up to 200 MHz and channel sampling rates up to 5.4 kHz. The application of FPGA allows the user to vary the number of real-time channel response averages, channel sampling interval, and duration of measurement. The waveform, bandwidth, and frequency resolution of the sounder can be adapted for any channel under investigation. The design approach and technology used has led to a reduction in size and weight by more than 60%. This makes the sounder ideal for mobile time-variant wireless communication channels studies. Averaging allows processing gains of up to 30 dB to be achieved for measurement in weak signal conditions. The technique applied also improves reliability, reduces power consumption, and has shifted sounder design complexity from hardware to software. Test results show that the sounder can detect very small-scale variations in channels.

Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

Directory of Open Access Journals (Sweden)

SKLYAROV, V.

2014-05-01

Full Text Available This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations. Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.

TELL1 data acquisition system for LHCb detectors

International Nuclear Information System (INIS)

Gong Guanghua; Xue Tao; Gong Hui; Shao Beibei

2004-01-01

A FPGA based data acquisition readout board has been developed for the LHCb detectors. With optical or analogue daughter cards, it can readout data from several different off-detector electronics. The data synchronization, buffering, pre-processing, zero-suppression and many interfaces to memory chips and communication buses are all implemented by the FPGA in VHDL code. The board sends data out via a 4 channel Gigabit Ethernet adapter. The TELL1 can accepts 24 optical links running at 1.6 GHz and provides for the analogue option 64 10-bit ADC channels sampling at 40 MHz. (authors)

Wireless, low-cost, FPGA-based miniature gamma ray spectrometer

Energy Technology Data Exchange (ETDEWEB)

Becker, E.M., E-mail: beckere@engr.orst.edu; Farsoni, A.T.

2014-10-11

A compact, low-cost, wireless gamma-ray spectrometer is a tool sought by a number of different organizations in the field of radiation detection. Such a device has applications in emergency response, battlefield assessment, and personal dosimetry. A prototype device fitting this description has been constructed in the Advanced Radiation Instrumentation Laboratory at Oregon State University. The prototype uses a CsI(Tl) scintillator coupled to a solid-state photomultiplier and a 40 MHz, 12-bit, FPGA-based digital pulse processor to measure gamma radiation, and is able to be accessed wirelessly by mobile phone. The prototype device consumes roughly 420 mW, weighs about 28 g (not including battery), and measures 2.54×3.81 cm{sup 2}. The prototype device is able to achieve 5.9% FWHM energy resolution at 662 keV.

FPGA based compute nodes for high level triggering in PANDA

International Nuclear Information System (INIS)

Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

2008-01-01

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

From OO to FPGA :

Energy Technology Data Exchange (ETDEWEB)

Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

2012-09-01

Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

40-Gbps optical backbone network deep packet inspection based on FPGA

Science.gov (United States)

Zuo, Yuan; Huang, Zhiping; Su, Shaojing

2014-11-01

In the era of information, the big data, which contains huge information, brings about some problems, such as high speed transmission, storage and real-time analysis and process. As the important media for data transmission, the Internet is the significant part for big data processing research. With the large-scale usage of the Internet, the data streaming of network is increasing rapidly. The speed level in the main fiber optic communication of the present has reached 40Gbps, even 100Gbps, therefore data on the optical backbone network shows some features of massive data. Generally, data services are provided via IP packets on the optical backbone network, which is constituted with SDH (Synchronous Digital Hierarchy). Hence this method that IP packets are directly mapped into SDH payload is named POS (Packet over SDH) technology. Aiming at the problems of real time process of high speed massive data, this paper designs a process system platform based on ATCA for 40Gbps POS signal data stream recognition and packet content capture, which employs the FPGA as the CPU. This platform offers pre-processing of clustering algorithms, service traffic identification and data mining for the following big data storage and analysis with high efficiency. Also, the operational procedure is proposed in this paper. Four channels of 10Gbps POS signal decomposed by the analysis module, which chooses FPGA as the kernel, are inputted to the flow classification module and the pattern matching component based on TCAM. Based on the properties of the length of payload and net flows, buffer management is added to the platform to keep the key flow information. According to data stream analysis, DPI (deep packet inspection) and flow balance distribute, the signal is transmitted to the backend machine through the giga Ethernet ports on back board. Practice shows that the proposed platform is superior to the traditional applications based on ASIC and NP.

An FPGA-Based Quench Detection and Protection System for Superconducting Accelerator Magnets

CERN Document Server

Carcagno, Ruben H; Lamm, Michael J; Makulski, Andrzej; Nehring, Roger; Orris, Darryl; Pishchalnikov, Yu M; Tartaglia, M

2005-01-01

A new quench detection and protection system for superconducting accelerator magnets was developed at the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commerically available, integrated hardware and software components. It provides most of the functionality of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and has a more powerful user interface and analysis tools. First applications of the new system will be for testing corrector coil packages. In this paper we describe the new system and present results of testing LHC Interaction Region Quadrupole (IRQ) correctors.

An FPGA-based quench detection and protection system for superconducting accelerator magnets

International Nuclear Information System (INIS)

Carcagno, R.H.; Feher, S.; Lamm, M.; Makulski, A.; Nehring, R.; Orris, D.F.; Pischalnikov, Y.; Tartaglia, M.; Fermilab

2005-01-01

A new quench detection and protection system for superconducting accelerator magnets was developed for the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commercially available, integrated hardware and software components. It provides all the functions of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and a more powerful user interface and analysis tools. The new system has been used successfully for testing LHC Interaction Region Quadrupoles correctors and High Field Magnet HFDM04. In this paper we describe the system and present results

An FPGA-based quench detection and protection system for superconducting accelerator magnets

Energy Technology Data Exchange (ETDEWEB)

Carcagno, R.H.; Feher, S.; Lamm, M.; Makulski, A.; Nehring, R.; Orris, D.F.; Pischalnikov, Y.; Tartaglia, M.; /Fermilab

2005-05-01

A new quench detection and protection system for superconducting accelerator magnets was developed for the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commercially available, integrated hardware and software components. It provides all the functions of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and a more powerful user interface and analysis tools. The new system has been used successfully for testing LHC Interaction Region Quadrupoles correctors and High Field Magnet HFDM04. In this paper we describe the system and present results.

Effective and efficient FPGA synthesis through general functional decomposition

NARCIS (Netherlands)

Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

2003-01-01

In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

OpenAIRE

Basil M Hamed; Mohammed S. El-Moghany

2012-01-01

The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

Energy Technology Data Exchange (ETDEWEB)

Yoo, Junbeom; Lee, Jonghoon [Konkuk Univ., Seoul (Korea, Republic of); Lee, Jangsoo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2013-08-15

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

International Nuclear Information System (INIS)

Yoo, Junbeom; Lee, Jonghoon; Lee, Jangsoo

2013-01-01

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea

A RESEARCH ON SEAMLESS PLATFORM CHANGE OF REACTOR PROTECTION SYSTEM FROM PLC TO FPGA

Directory of Open Access Journals (Sweden)

JUNBEOM YOO

2013-08-01

Full Text Available The PLC (Programmable Logic Controller has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems. Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array. Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

VHDL resolved function based inner communication bus for FPGA

Science.gov (United States)

Pozniak, Krzysztof T.

2017-08-01

This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

International Nuclear Information System (INIS)

Pramila; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-01-01

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

Energy Technology Data Exchange (ETDEWEB)

Pramila, E-mail: pramila@ipr.res.in; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-11-15

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

Science.gov (United States)

Mandal, Swagata; Saini, Jogender; Zabołotny, Wojciech M.; Sau, Suman; Chakrabarti, Amlan; Chattopadhyay, Subhasis

2017-03-01

Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

Science.gov (United States)

Du, Hongtao; Qi, Hairong; Szu, Harold H.

2005-03-01

Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

Implementation of Wireless Communications Systems on FPGA-Based Platforms

Directory of Open Access Journals (Sweden)

Voros NS

2007-01-01

Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

Directory of Open Access Journals (Sweden)

Sanjay Singh

2016-03-01

Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

FASTBUS readout system for the CDF DAQ upgrade

International Nuclear Information System (INIS)

Andresen, J.; Areti, H.; Black, D.

1993-11-01

The Data Acquisition System (DAQ) at the Collider Detector at Fermilab is currently being upgraded to handle a minimum of 100 events/sec for an aggregate bandwidth that is at least 25 Mbytes/sec. The DAQ System is based on a commercial switching network that has interfaces to VME bus. The modules that readout the front end crates (FASTBUS and RABBIT) have to deliver the data to the VME bus based host adapters of the switch. This paper describes a readout system that has the required bandwidth while keeping the experiment dead time due to the readout to a minimum

Design and implementation of FPGA-based LQ control of active magnetic bearings

Energy Technology Data Exchange (ETDEWEB)

Jastrzebski, R.

2007-07-01

The need for high performance, high precision, and energy saving in rotating machinery demands an alternative solution to traditional bearings. Because of the contactless operation principle, the rotating machines employing active magnetic bearings (AMBs) provide many advantages over the traditional ones. The advantages such as contamination-free operation, low maintenance costs, high rotational speeds, low parasitic losses, programmable stiffness and damping, and vibration insulation come at expense of high cost, and complex technical solution. All these properties make the use of AMBs appropriate primarily for specific and highly demanding applications. High performance and high precision control requires model-based control methods and accurate models of the flexible rotor. In turn, complex models lead to high-order controllers and feature considerable computational burden. Fortunately, in the last few years the advancements in signal processing devices provide new perspective on the real-time control of AMBs. The design and the real-time digital implementation of the high-order LQ controllers, which focus on fast execution times, are the subjects of this work. In particular, the control design and implementation in the field programmable gate array (FPGA) circuits are investigated. The optimal design is guided by the physical constraints of the system for selecting the optimal weighting matrices. The plant model is complemented by augmenting appropriate disturbance models. The compensation of the force-field nonlinearities is proposed for decreasing the uncertainty of the actuator. A disturbance-observer-based unbalance compensation for canceling the magnetic force vibrations or vibrations in the measured positions is presented. The theoretical studies are verified by the practical experiments utilizing a custom-built laboratory test rig. The test rig uses a prototyping control platform developed in the scope of this work. To sum up, the work makes a step in

Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

Directory of Open Access Journals (Sweden)

Sumedh Dhabu

2015-09-01

Full Text Available This paper presents the design and FPGA implementation of interpolated continuously variable fractional delay structure based filter (ICVFD filter with fine control over the cutoff frequency. In the ICVFD filter, each unit delay of the prototype lowpass filter is replaced by a continuously variable fractional delay (CVFD element proposed in this paper. The CVFD element requires the same number of multiplications as that of the second-order fractional delay structure used in the existing fractional delay structure based variable filter (FDS based filter, however it provides fractional delays corresponding to the higher-order fractional delay structures. Hence, the proposed ICVFD filter provides wider cutoff frequency range compared to the FDS based filter. The ICVFD filter is also capable of providing variable bandpass and highpass responses. We use two-stage approach for the FPGA implementation of the ICVFD filter. First, we use pipelining stages to shorten the critical path and improve the operating frequency. Then, we make use of specific hardware resource, i.e. RAM-based Shift Register (SRL to further improve the operating frequency and resource usage.

A Control System and Streaming DAQ Platform with Image-Based Trigger for X-ray Imaging

Science.gov (United States)

Stevanovic, Uros; Caselle, Michele; Cecilia, Angelica; Chilingaryan, Suren; Farago, Tomas; Gasilov, Sergey; Herth, Armin; Kopmann, Andreas; Vogelgesang, Matthias; Balzer, Matthias; Baumbach, Tilo; Weber, Marc

2015-06-01

High-speed X-ray imaging applications play a crucial role for non-destructive investigations of the dynamics in material science and biology. On-line data analysis is necessary for quality assurance and data-driven feedback, leading to a more efficient use of a beam time and increased data quality. In this article we present a smart camera platform with embedded Field Programmable Gate Array (FPGA) processing that is able to stream and process data continuously in real-time. The setup consists of a Complementary Metal-Oxide-Semiconductor (CMOS) sensor, an FPGA readout card, and a readout computer. It is seamlessly integrated in a new custom experiment control system called Concert that provides a more efficient way of operating a beamline by integrating device control, experiment process control, and data analysis. The potential of the embedded processing is demonstrated by implementing an image-based trigger. It records the temporal evolution of physical events with increased speed while maintaining the full field of view. The complete data acquisition system, with Concert and the smart camera platform was successfully integrated and used for fast X-ray imaging experiments at KIT's synchrotron radiation facility ANKA.

Characterization of a DAQ system for the readout of a SiPM based shashlik calorimeter

International Nuclear Information System (INIS)

Berra, A.; Bonvicini, V.; Bosisio, L.; Lietti, D.; Penzo, A.; Prest, M.; Rabaioli, S.; Rashevskaya, I.; Vallazza, E.

2014-01-01

Silicon PhotoMultipliers (SiPMs) are a recently developed type of silicon photodetector characterized by high gain and insensitivity to magnetic fields, which make them a suitable detector for the next generation high energy and space physics experiments. This paper presents the performance of a readout system for SiPMs based on the MAROC3 ASIC. The ASIC consists of 64 channels working in parallel, each one with a variable gain pre-amplifier, a tunable slow shaper with a sample and hold circuit for the analog readout and a tunable fast shaper for the digital one. In the tests described in this paper, only the analog part of the ASIC has been used. A frontend board based on the MAROC3 ASIC has been tested at CERN coupled to a scintillator-lead shashlik calorimeter, readout with 36 large area SiPMs. The performance of the system has been characterized in terms of linearity and energy resolution on the CERN PS-T9 and SPS-H2 beamlines, using different configurations of the ASIC parameters

improvement of digital image watermarking techniques based on FPGA implementation

International Nuclear Information System (INIS)

EL-Hadedy, M.E

2006-01-01

digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

Test and improvement of readout system based on APV25 chip for GEM detector

International Nuclear Information System (INIS)

Hu Shouyang; Jian Siyu; Zhou Jing; Shan Chao; Li Xinglong; Li Xia; Li Xiaomei; Zhou Yi

2014-01-01

Gas electron multiplier (GEM) is the most promising position sensitive gas detector. The new generation of readout electronics system includes APV25 front-end card, multi-purpose digitizer (MPD), VME controller and Linux-based acquisition software DAQ. The construction and preliminary test of this readout system were finished, and the ideal data with the system working frequency of 40 MHz and 20 MHz were obtained. The long time running test shows that the system has a very good time-stable ability. Through optimizing the software configuration and improving hardware quality, the noise level was reduced, and the signal noise ratio was improved. (authors)

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

DEFF Research Database (Denmark)

Saini, Rishita; Bansal, Neha; Bansal, Meenakshi

2015-01-01

Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient...

An FPGA- Based General-Purpose Data Acquisition Controller

Science.gov (United States)

Robson, C. C. W.; Bousselham, A.; Bohm

2006-08-01

System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

FPGA Techniques Based New Hybrid Modulation Strategies for Voltage Source Inverters

Science.gov (United States)

Sudha, L. U.; Baskaran, J.; Elankurisil, S. A.

2015-01-01

This paper corroborates three different hybrid modulation strategies suitable for single-phase voltage source inverter. The proposed method is formulated using fundamental switching and carrier based pulse width modulation methods. The main tale of this proposed method is to optimize a specific performance criterion, such as minimization of the total harmonic distortion (THD), lower order harmonics, switching losses, and heat losses. The proposed method is articulated using fundamental switching and carrier based pulse width modulation methods. Thus, the harmonic pollution in the power system will be reduced and the power quality will be augmented with better harmonic profile for a target fundamental output voltage. The proposed modulation strategies are simulated in MATLAB r2010a and implemented in a Xilinx spartan 3E-500 FG 320 FPGA processor. The feasibility of these modulation strategies is authenticated through simulation and experimental results. PMID:25821852

Image processing system design for microcantilever-based optical readout infrared arrays

Science.gov (United States)

Tong, Qiang; Dong, Liquan; Zhao, Yuejin; Gong, Cheng; Liu, Xiaohua; Yu, Xiaomei; Yang, Lei; Liu, Weiyu

2012-12-01

Compared with the traditional infrared imaging technology, the new type of optical-readout uncooled infrared imaging technology based on MEMS has many advantages, such as low cost, small size, producing simple. In addition, the theory proves that the technology's high thermal detection sensitivity. So it has a very broad application prospects in the field of high performance infrared detection. The paper mainly focuses on an image capturing and processing system in the new type of optical-readout uncooled infrared imaging technology based on MEMS. The image capturing and processing system consists of software and hardware. We build our image processing core hardware platform based on TI's high performance DSP chip which is the TMS320DM642, and then design our image capturing board based on the MT9P031. MT9P031 is Micron's company high frame rate, low power consumption CMOS chip. Last we use Intel's company network transceiver devices-LXT971A to design the network output board. The software system is built on the real-time operating system DSP/BIOS. We design our video capture driver program based on TI's class-mini driver and network output program based on the NDK kit for image capturing and processing and transmitting. The experiment shows that the system has the advantages of high capturing resolution and fast processing speed. The speed of the network transmission is up to 100Mbps.

Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

International Nuclear Information System (INIS)

Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

2008-01-01

A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

FASTBUS Readout Controller card for high speed data acquisition

International Nuclear Information System (INIS)

Zimmermann, S.

1991-10-01

This article describes a FASTBUS Readout Controller (FRC) for high speed data acquisition in FASTBUS based systems. The controller has two main interfaces: to FASTBUS and to a Readout Port. The FASTBUS interface performs FASTBUS master and slave operations at a maximum transfer rate exceeding 40 MBytes/s. The Readout Port can be adapted for a variety of protocols. Currently, it will be interfaced to a VME bus based processor with a VSB port. The on-board LR33000 embedded processor controls the readout, executing a list of operations download into its memory. It scans the FASTBUS modules and stores the data in a triple port DRAM (TPDRAM), through one of the Serial Access Memory (SAM) ports of the (TPDRAM). Later, it transfers this data to the readout port using the other SAM. The FRC also supports serial communication via RS232 and Ethernet interfaces. This device is intended for use in the data acquisition system at the Collider Detector at Fermilab. 5 refs., 3 figs

A readout system for the micro-vertex-detector demonstrator for the CBM experiment at FAIR

Energy Technology Data Exchange (ETDEWEB)

Schrader, Christoph

2011-06-09

The Compressed Baryonic Matter Experiment (CBM) is a fixed target heavy ion experiment currently in preparation at the future FAIR accelerator complex in Darmstadt. The CBM experiment focuses on the measurements of diagnostic probes of the early and dense phase of the fireball at beam energies from 8 up to 45 AGeV. As observables, rare hadronic, leptonic and photonic probes are used, including open charm. Open charm will be identified by reconstructing the secondary decay vertex of the corresponding short lived particles. As the central component for track reconstruction, a detector system based on silicon semiconductor detectors is planned. The first three stations of the Silicon Tracking System (STS) make up the so-called Micro-Vertex-Detector (MVD) operating in moderate vacuum. Because of the well-balanced compromise between an excellent spatial resolution (few {mu}m), low material budget ({proportional_to}50 {mu}m Si), adequate radiation tolerance and readout speed, Monolithic Active Pixel Sensors (MAPS) based on CMOS technology are more suited than any other technology for the reconstruction of the secondary vertex in CBM. A new detector concept has to be developed. Two MVD-Demonstrator modules have been successfully tested with 120 GeV pions at the CERN-SPS. The main topic of this thesis is the development of a control and readout concept of several MVD-Demonstrator modules with a common data acquisition system. In order to achieve the required results a front-end electronics device has been developed which is capable of reading the analogue signals of two sensors on a ex-print cable. The high data rate of the MAPS sensors (1.2 Gbit per second and sensor by 50 MHz and 12 bit ADC resolution) requires a readout system which processes the data on-line in a pipeline to avoid dead times. In order to implement the pipeline processing an FPGA is used, which is located on an additional hardware platform. In order to integrate the MVD-Demonstrator readout board in the

A readout system for the micro-vertex-detector demonstrator for the CBM experiment at FAIR

International Nuclear Information System (INIS)

Schrader, Christoph

2011-01-01

The Compressed Baryonic Matter Experiment (CBM) is a fixed target heavy ion experiment currently in preparation at the future FAIR accelerator complex in Darmstadt. The CBM experiment focuses on the measurements of diagnostic probes of the early and dense phase of the fireball at beam energies from 8 up to 45 AGeV. As observables, rare hadronic, leptonic and photonic probes are used, including open charm. Open charm will be identified by reconstructing the secondary decay vertex of the corresponding short lived particles. As the central component for track reconstruction, a detector system based on silicon semiconductor detectors is planned. The first three stations of the Silicon Tracking System (STS) make up the so-called Micro-Vertex-Detector (MVD) operating in moderate vacuum. Because of the well-balanced compromise between an excellent spatial resolution (few μm), low material budget (∝50 μm Si), adequate radiation tolerance and readout speed, Monolithic Active Pixel Sensors (MAPS) based on CMOS technology are more suited than any other technology for the reconstruction of the secondary vertex in CBM. A new detector concept has to be developed. Two MVD-Demonstrator modules have been successfully tested with 120 GeV pions at the CERN-SPS. The main topic of this thesis is the development of a control and readout concept of several MVD-Demonstrator modules with a common data acquisition system. In order to achieve the required results a front-end electronics device has been developed which is capable of reading the analogue signals of two sensors on a ex-print cable. The high data rate of the MAPS sensors (1.2 Gbit per second and sensor by 50 MHz and 12 bit ADC resolution) requires a readout system which processes the data on-line in a pipeline to avoid dead times. In order to implement the pipeline processing an FPGA is used, which is located on an additional hardware platform. In order to integrate the MVD-Demonstrator readout board in the HADES data

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

Directory of Open Access Journals (Sweden)

Preethi Padmanabhan

2018-02-01

Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

Science.gov (United States)

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

Science.gov (United States)

Zhang, Chen; Liang, Tianzhu; Mok, Philip K T; Yu, Weichuan

2017-07-01

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

Energy Technology Data Exchange (ETDEWEB)

Rakotozafy, Mamianja [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France); Poure, Philippe [Laboratoire d' Instrumentation Electronique de Nancy (LIEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Saadate, Shahrokh [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Bordas, Cedric; Leclere, Loic [CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France)

2011-02-15

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital simulators.As an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (author)

Video Watermarking Implementation Based on FPGA

International Nuclear Information System (INIS)

EL-ARABY, W.S.M.S.

2012-01-01

The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

DNA Nanobiosensors: An Outlook on Signal Readout Strategies

Directory of Open Access Journals (Sweden)

Arun Richard Chandrasekaran

2017-01-01

Full Text Available A suite of functionalities and structural versatility makes DNA an apt material for biosensing applications. DNA-based biosensors are cost-effective and sensitive and have the potential to be used as point-of-care diagnostic tools. Along with robustness and biocompatibility, these sensors also provide multiple readout strategies. Depending on the functionality of DNA-based biosensors, a variety of output strategies have been reported: fluorescence- and FRET-based readout, nanoparticle-based colorimetry, spectroscopy-based techniques, electrochemical signaling, gel electrophoresis, and atomic force microscopy.

FPGA Implementation of the stepwise shutdown system

International Nuclear Information System (INIS)

Lotjonen, L.

2012-01-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

FPGA Implementation of the stepwise shutdown system

Energy Technology Data Exchange (ETDEWEB)

Lotjonen, L.

2012-07-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

FPGA-based real-time phase measuring profilometry algorithm design and implementation

Science.gov (United States)

Zhan, Guomin; Tang, Hongwei; Zhong, Kai; Li, Zhongwei; Shi, Yusheng

2016-11-01

Phase measuring profilometry (PMP) has been widely used in many fields, like Computer Aided Verification (CAV), Flexible Manufacturing System (FMS) et al. High frame-rate (HFR) real-time vision-based feedback control will be a common demands in near future. However, the instruction time delay in the computer caused by numerous repetitive operations greatly limit the efficiency of data processing. FPGA has the advantages of pipeline architecture and parallel execution, and it fit for handling PMP algorithm. In this paper, we design a fully pipelined hardware architecture for PMP. The functions of hardware architecture includes rectification, phase calculation, phase shifting, and stereo matching. The experiment verified the performance of this method, and the factors that may influence the computation accuracy was analyzed.

The TOTEM DAQ based on the Scalable Readout System (SRS)

Science.gov (United States)

Quinto, Michele; Cafagna, Francesco S.; Fiergolski, Adrian; Radicioni, Emilio

2018-02-01

The TOTEM (TOTal cross section, Elastic scattering and diffraction dissociation Measurement at the LHC) experiment at LHC, has been designed to measure the total proton-proton cross-section and study the elastic and diffractive scattering at the LHC energies. In order to cope with the increased machine luminosity and the higher statistic required by the extension of the TOTEM physics program, approved for the LHC's Run Two phase, the previous VME based data acquisition system has been replaced with a new one based on the Scalable Readout System. The system features an aggregated data throughput of 2GB / s towards the online storage system. This makes it possible to sustain a maximum trigger rate of ˜ 24kHz, to be compared with the 1KHz rate of the previous system. The trigger rate is further improved by implementing zero-suppression and second-level hardware algorithms in the Scalable Readout System. The new system fulfils the requirements for an increased efficiency, providing higher bandwidth, and increasing the purity of the data recorded. Moreover full compatibility has been guaranteed with the legacy front-end hardware, as well as with the DAQ interface of the CMS experiment and with the LHC's Timing, Trigger and Control distribution system. In this contribution we describe in detail the architecture of full system and its performance measured during the commissioning phase at the LHC Interaction Point.

FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

CERN Document Server

Pozniak, Krzysztof T

2004-01-01

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

Single Event Effects in FPGA Devices 2015-2016

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

A readout buffer prototype for ATLAS high-level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2001-01-01

Readout buffers are critical components in the dataflow chain of the ATLAS trigger/data-acquisition system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several readout buffers are grouped to form a readout buffer complex that acts as a data server for the high-level trigger selection algorithms and for the final data-collection system. This paper describes a functional prototype of a readout buffer based on a custom-made PCI mezzanine card that is designed to accept input data at up to 160 MB /s, to store up to 8 MB of data, and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and complex programmable logic devices. We present the integration of several of these cards in a readout buffer complex. We measure various performance figures and discuss to which extent these can fulfil ATLAS needs. (5 refs).

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Science.gov (United States)

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Design and development of VHDL based IP core for coincidence analyzer for FPGA based TDCR system

International Nuclear Information System (INIS)

Agarwal, Shivam; Gupta, Ashutosh; Chaudhury, Probal; Sharma, M.K.; Kulkarni, M.S.

2018-01-01

The coincidence counting technique is used in activity measurement methods to determine the activity of radionuclide e.g. 4πβ-γ method and Triple to Double Coincidence Ratio (TDCR) method etc. The 4πβ-γ method requires two inputs Coincidence Analyzer (CA) whereas; TDCR method requires three inputs CA. A VHDL (Very High Speed Integrated Circuit Hardware Description Language) based IP (Intellectual Property) core for coincidence analyzer has been designed and implemented in FPGA (Field Programmable Gate Array) for TDCR system. The developed IP not only facilitates the coincidence counting of three channels simultaneously but also provides an extendable dead time feature

Timing and Readout Contorl in the LHCb Upgraded Readout System

CERN Document Server

Alessio, Federico

2016-01-01

In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

[Evaluation of Image Quality of Readout Segmented EPI with Readout Partial Fourier Technique].

Science.gov (United States)

Yoshimura, Yuuki; Suzuki, Daisuke; Miyahara, Kanae

Readout segmented EPI (readout segmentation of long variable echo-trains: RESOLVE) segmented k-space in the readout direction. By using the partial Fourier method in the readout direction, the imaging time was shortened. However, the influence on image quality due to insufficient data sampling is concerned. The setting of the partial Fourier method in the readout direction in each segment was changed. Then, we examined signal-to-noise ratio (SNR), contrast-to-noise ratio (CNR), and distortion ratio for changes in image quality due to differences in data sampling. As the number of sampling segments decreased, SNR and CNR showed a low value. In addition, the distortion ratio did not change. The image quality of minimum sampling segments is greatly different from full data sampling, and caution is required when using it.

1 GSPS digitizer based on the FPGA Mezzanine Card (FMC) standard with low-count pin connector.

CERN Document Server

Vasilyev, Mikhail

2015-01-01

Under the scope of a CERN summer student project, the schematic for ADC based on FMC mezzanine card with 1 GSPS sampling rate and 8 bit resolution was developed. The mezzanine is fully compatible with the standard: FPGA Mezzanine Card (FMC) [1]. A low-pin count connector was used to connect the mezzanine with the “carrier”. The carrier was an Open Hardware project: Simple PCIe FMC carrier (SPEC).

A real-time data transmission method based on Linux for physical experimental readout systems

International Nuclear Information System (INIS)

Cao Ping; Song Kezhu; Yang Junfeng

2012-01-01

In a typical physical experimental instrument, such as a fusion or particle physical application, the readout system generally implements an interface between the data acquisition (DAQ) system and the front-end electronics (FEE). The key task of a readout system is to read, pack, and forward the data from the FEE to the back-end data concentration center in real time. To guarantee real-time performance, the VxWorks operating system (OS) is widely used in readout systems. However, VxWorks is not an open-source OS, which gives it has many disadvantages. With the development of multi-core processor and new scheduling algorithm, Linux OS exhibits performance in real-time applications similar to that of VxWorks. It has been successfully used even for some hard real-time systems. Discussions and evaluations of real-time Linux solutions for a possible replacement of VxWorks arise naturally. In this paper, a real-time transmission method based on Linux is introduced. To reduce the number of transfer cycles for large amounts of data, a large block of contiguous memory buffer for DMA transfer is allocated by modifying the Linux Kernel (version 2.6) source code slightly. To increase the throughput for network transmission, the user software is designed into formation of parallelism. To achieve high performance in real-time data transfer from hardware to software, mapping techniques must be used to avoid unnecessary data copying. A simplified readout system is implemented with 4 readout modules in a PXI crate. This system can support up to 48 MB/s data throughput from the front-end hardware to the back-end concentration center through a Gigabit Ethernet connection. There are no restrictions on the use of this method, hardware or software, which means that it can be easily migrated to other interrupt related applications.

FPGA-Based Flexible Hardware Architecture for Image Interest Point Detection

Directory of Open Access Journals (Sweden)

Ana Hernandez-Lopez

2015-07-01

Full Text Available An important challenge in computer vision is the implementation of fast and accurate feature detectors, as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in embedded scenarios, mainly due to the fact that they are time consuming and require a significant amount of processing power. Although some feature detectors have been implemented in hardware, most implementations target a single detector under very specific constraints. This paper proposes a flexible hardware implementation approach for computing interest point extraction from grey-level images based on two different detectors, Harris and SUSAN, suitable for robotic applications. The design is based on parallel and configurable processing elements for window operators and a buffering strategy to support a coarse-grain pipeline scheme for operator sequencing. When targeted to a Virtex-6 FPGA, a throughput of 49.45 Mpixel/s (processing rate of 161 frames per second of VGA image resolution is achieved at a clock frequency of 50 MHz.

LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Kaur, Amanpreet; Kumar, Tanesh

2014-01-01

-transistor logic (LVTTL) IO standard is used in this design to make it power optimized. This design is implemented on Kintex-7 FPGA, Device XC7K70T and -3 speed grades. When we are scaling the device operating frequency from 100GHz to 5GHz, there is 94.93% saving in total power of the watermark generator...

FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

Science.gov (United States)

Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar

2013-09-01

Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion. Copyright © 2013 Elsevier Ltd. All rights reserved.

Signal compression in radar using FPGA

OpenAIRE

Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

2010-01-01

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

Online data reduction with FPGA-based track reconstruction for the Belle II DEPFET pixel detector

Energy Technology Data Exchange (ETDEWEB)

Deschamps, Bruno; Wessel, Christian; Marinas, Carlos; Dingfelder, Jochen [Physikalisches Institut, Universitaet Bonn (Germany)

2016-07-01

The innermost two layers of the Belle II vertex detector at the KEK facility in Tsukuba, Japan, will be covered by high-granularity DEPFET pixel sensors (PXD). The large number of pixels leads to a maximum data rate of 256 Gbps, which has to be significantly reduced by the Data Acquisition System (DATCON). For the data reduction the hit information of the surrounding Silicon strip Vertex Detector (SVD) is utilized to define so-called Regions of Interest (ROI). Only hit information of the pixels located inside these ROIs are saved. The ROIs for the PXD are computed by reconstructing track segments from SVD data and extrapolation to the PXD. The goal is to achieve a data reduction of at least a factor of 10 with this ROI selection. All the necessary processing stages, the receiving, decoding and multiplexing of SVD data on 48 optical fibers, the track reconstruction and the definition of the ROIs, will be performed by the presented system. The planned hardware design is based on a distributed set of Advanced Mezzanine Cards (AMC) each equipped with a Field Programmable Gate Array (FPGA) and 4 optical transceivers. In this talk, the status and plans for the DATCON prototype and the FPGA-based tracking algorithm are introduced as well as the plans for their test in the upcoming test beam at DESY.

A Compute Environment of ABC95 Array Computer Based on Multi-FPGA Chip

Institute of Scientific and Technical Information of China (English)

无

2000-01-01

ABC95 array computer is a multi-function network's computer based on FPGA technology, The multi-function network supports processors conflict-free access data from memory and supports processors access data from processors based on enhanced MESH network.ABC95 instruction's system includes control instructions, scalar instructions, vectors instructions.Mostly net-work instructions are introduced.A programming environment of ABC95 array computer assemble language is designed.A programming environment of ABC95 array computer for VC++ is advanced.It includes load function of ABC95 array computer program and data, store function, run function and so on.Specially, The data type of ABC95 array computer conflict-free access is defined.The results show that these technologies can develop programmer of ABC95 array computer effectively.

Technologies for faults diagnosis of FPGA logic blocks

Directory of Open Access Journals (Sweden)

C. U. Ngene

2012-08-01

Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

Directory of Open Access Journals (Sweden)

Arkani Mohammad

2014-08-01

Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

Directory of Open Access Journals (Sweden)

S. Tsakiris

2009-09-01

Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

CERN Document Server

Ponce-Cruz, Pedro; MacCleery, Brian

2016-01-01

This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

The effect of structural design parameters on FPGA-based feed-forward space-time trellis coding-orthogonal frequency division multiplexing channel encoders

Science.gov (United States)

Passas, Georgios; Freear, Steven; Fawcett, Darren

2010-08-01

Orthogonal frequency division multiplexing (OFDM)-based feed-forward space-time trellis code (FFSTTC) encoders can be synthesised as very high speed integrated circuit hardware description language (VHDL) designs. Evaluation of their FPGA implementation can lead to conclusions that help a designer to decide the optimum implementation, given the encoder structural parameters. VLSI architectures based on 1-bit multipliers and look-up tables (LUTs) are compared in terms of FPGA slices and block RAMs (area), as well as in terms of minimum clock period (speed). Area and speed graphs versus encoder memory order are provided for quadrature phase shift keying (QPSK) and 8 phase shift keying (8-PSK) modulation and two transmit antennas, revealing best implementation under these conditions. The effect of number of modulation bits and transmit antennas on the encoder implementation complexity is also investigated.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

Science.gov (United States)

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

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Kearney David

2007-01-01

Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

International Nuclear Information System (INIS)

Suratia, Pooja; Patel, Jigneshkumar; Rajpal, Rachana; Kotia, Sorum; Govindarajan, J.

2012-01-01

Highlights: ► Evaluation and comparison of the working performance of FLC is done with that of PID Controller. ► FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. ► FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. ► Developed FLC controller is able to maintain the plasma column within required range of ±0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional–Integral–Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

FPGA-Based Smart Sensor for Online Displacement Measurements Using a Heterodyne Interferometer

Science.gov (United States)

Vera-Salas, Luis Alberto; Moreno-Tapia, Sandra Veronica; Garcia-Perez, Arturo; de Jesus Romero-Troncoso, Rene; Osornio-Rios, Roque Alfredo; Serroukh, Ibrahim; Cabal-Yepez, Eduardo

2011-01-01

The measurement of small displacements on the nanometric scale demands metrological systems of high accuracy and precision. In this context, interferometer-based displacement measurements have become the main tools used for traceable dimensional metrology. The different industrial applications in which small displacement measurements are employed requires the use of online measurements, high speed processes, open architecture control systems, as well as good adaptability to specific process conditions. The main contribution of this work is the development of a smart sensor for large displacement measurement based on phase measurement which achieves high accuracy and resolution, designed to be used with a commercial heterodyne interferometer. The system is based on a low-cost Field Programmable Gate Array (FPGA) allowing the integration of several functions in a single portable device. This system is optimal for high speed applications where online measurement is needed and the reconfigurability feature allows the addition of different modules for error compensation, as might be required by a specific application. PMID:22164040

High-speed real-time OFDM transmission based on FPGA

Science.gov (United States)